openlane/int_ram/config.json

{
    "DESIGN_NAME": "int_ram",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v", 
        "dir::../../verilog/rtl/ppcpu/rtl/embed/int_ram.v"
    ],
    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
    "CLOCK_PERIOD": 10,
    "CLOCK_PORT": "i_clk",
    "CLOCK_NET": "i_clk",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 550 550",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.35,
    "VDD_NETS": ["vccd1"],
    "GND_NETS": ["vssd1"],
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "RT_MAX_LAYER": "met4"
    },
    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.35,
    "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.45,
    "ROUTING_CORES": 6
}