| - status: 0 - openlane design prep |
| runtime_s: 1.89 |
| runtime_ts: 0h0m1s885ms |
| - status: 1 - synthesis - yosys |
| runtime_s: 14.66 |
| runtime_ts: 0h0m14s659ms |
| - status: 2 - sta - openroad |
| runtime_s: 0.93 |
| runtime_ts: 0h0m0s932ms |
| - status: 3 - floorplan initialization - openroad |
| runtime_s: 1.15 |
| runtime_ts: 0h0m1s147ms |
| - status: 4 - io_place - openlane |
| runtime_s: 0.39 |
| runtime_ts: 0h0m0s394ms |
| - status: 5 - tap/decap insertion - openroad |
| runtime_s: 0.56 |
| runtime_ts: 0h0m0s557ms |
| - status: 6 - pdn generation - openroad |
| runtime_s: 0.73 |
| runtime_ts: 0h0m0s726ms |
| - status: 7 - global placement - openroad |
| runtime_s: 14.07 |
| runtime_ts: 0h0m14s71ms |
| - status: 8 - resizer design optimizations - openroad |
| runtime_s: 3.06 |
| runtime_ts: 0h0m3s60ms |
| - status: 9 - detailed placement - openroad |
| runtime_s: 0.75 |
| runtime_ts: 0h0m0s747ms |
| - status: 10 - cts - openroad |
| runtime_s: 33.11 |
| runtime_ts: 0h0m33s113ms |
| - status: 11 - resizer timing optimizations - openroad |
| runtime_s: 2.54 |
| runtime_ts: 0h0m2s544ms |
| - status: 12 - resizer timing optimizations - openroad |
| runtime_s: 2.8 |
| runtime_ts: 0h0m2s796ms |
| - status: 14 - detailed placement - openroad |
| runtime_s: 0.8 |
| runtime_ts: 0h0m0s803ms |
| - status: 14 - diode insertion - openlane |
| runtime_s: 0.89 |
| runtime_ts: 0h0m0s888ms |
| - status: 15 - fill insertion - openroad |
| runtime_s: 1.0 |
| runtime_ts: 0h0m0s997ms |
| - status: 17 - write verilog - openroad |
| runtime_s: 0.68 |
| runtime_ts: 0h0m0s676ms |
| - status: 17 - global routing - openroad |
| runtime_s: 0.79 |
| runtime_ts: 0h0m0s794ms |
| - status: 18 - detailed_routing - openroad |
| runtime_s: 209.96 |
| runtime_ts: 0h3m29s962ms |
| - status: 19 - wire lengths - openlane |
| runtime_s: 0.72 |
| runtime_ts: 0h0m0s725ms |
| - status: 20 - parasitics extraction - openroad |
| runtime_s: 3.02 |
| runtime_ts: 0h0m3s19ms |
| - status: 21 - sta - openroad |
| runtime_s: 30.73 |
| runtime_ts: 0h0m30s725ms |
| - status: 22 - parasitics extraction - openroad |
| runtime_s: 3.58 |
| runtime_ts: 0h0m3s581ms |
| - status: 23 - sta - openroad |
| runtime_s: 32.07 |
| runtime_ts: 0h0m32s73ms |
| - status: 24 - parasitics extraction - openroad |
| runtime_s: 3.44 |
| runtime_ts: 0h0m3s435ms |
| - status: 25 - sta - openroad |
| runtime_s: 31.3 |
| runtime_ts: 0h0m31s300ms |
| - status: 26 - sta - openroad |
| runtime_s: 7.64 |
| runtime_ts: 0h0m7s639ms |
| - status: 27 - ir drop report - openroad |
| runtime_s: 1.71 |
| runtime_ts: 0h0m1s706ms |
| - status: 28 - gdsii - magic |
| runtime_s: 17.73 |
| runtime_ts: 0h0m17s731ms |
| - status: 29 - gdsii - klayout |
| runtime_s: 1.84 |
| runtime_ts: 0h0m1s843ms |
| - status: 30 - xor - klayout |
| runtime_s: 44.94 |
| runtime_ts: 0h0m44s944ms |
| - status: 31 - spice extraction - magic |
| runtime_s: 24.7 |
| runtime_ts: 0h0m24s696ms |
| - status: 33 - write verilog - openroad |
| runtime_s: 0.88 |
| runtime_ts: 0h0m0s880ms |
| - status: 33 - write powered verilog - openlane |
| runtime_s: 1.02 |
| runtime_ts: 0h0m1s18ms |
| - status: 34 - lvs - netgen |
| runtime_s: 4.08 |
| runtime_ts: 0h0m4s84ms |
| - status: 35 - drc - magic |
| runtime_s: 79.54 |
| runtime_ts: 0h1m19s536ms |
| - status: 36 - antenna check - openroad |
| runtime_s: 1.21 |
| runtime_ts: 0h0m1s213ms |
| - status: 37 - erc - circuit validity checker |
| runtime_s: 0.55 |
| runtime_ts: 0h0m0s553ms |
| --- |
| - status: routed |
| runtime_s: 296.0 |
| runtime_ts: 0h4m56s0ms |
| - status: flow failed |
| runtime_s: 590.0 |
| runtime_ts: 0h9m50s0ms |
