commit	0852199dbc4636f5dc459b603d6625949eef2f8b	[log] [tgz]
author	Piotro <piotro888@wp.pl>	Fri Dec 30 15:14:32 2022 +0100
committer	Piotro <piotro888@wp.pl>	Fri Dec 30 15:17:12 2022 +0100
tree	05ff53076b2ff39cb1ed9e4ed2a3c295a735ff4a
parent	4592fc35ba09ab49db01eac18b8c925a947ea6d8 [diff]

Add ppcpu as normal dir

.gitmodules[Deleted - diff]
verilog/rtl/ppcpu[Deleted - diff]
verilog/rtl/ppcpu/rtl/config.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/alu.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/alu_mul_div.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/core.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/decode.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/execute.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/fetch.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/memwb.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/pc.v[Added - diff]
verilog/rtl/ppcpu/rtl/core/ports[Added - diff]
verilog/rtl/ppcpu/rtl/core/rf.v[Added - diff]
verilog/rtl/ppcpu/rtl/dcache/dcache.v[Added - diff]
verilog/rtl/ppcpu/rtl/dcache/dcache_ram.v[Added - diff]
verilog/rtl/ppcpu/rtl/embed/gpio.v[Added - diff]
verilog/rtl/ppcpu/rtl/embed/int_ram.v[Added - diff]
verilog/rtl/ppcpu/rtl/embed/sspi.v[Added - diff]
verilog/rtl/ppcpu/rtl/icache/icache.v[Added - diff]
verilog/rtl/ppcpu/rtl/icache/icache_ram.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/inner/dmmu.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/inner/immu.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/inner/intercore_sregs.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/inner/mem_dcache_arb.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/inner/wishbone_arbiter.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/interconnect_inner.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/interconnect_outer.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/outer/clk_div.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/outer/ff_mb_sync.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/outer/reset_sync.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/outer/wb_compressor.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/outer/wb_cross_clk.v[Added - diff]
verilog/rtl/ppcpu/rtl/interconnect/outer/wb_decomp.v[Added - diff]
verilog/rtl/ppcpu/rtl/top.v[Added - diff]
verilog/rtl/ppcpu/soc/bootloader.s[Added - diff]
verilog/rtl/ppcpu/soc/irq_ctrl.v[Added - diff]
verilog/rtl/ppcpu/soc/sdram.v[Added - diff]
verilog/rtl/ppcpu/soc/serialout.v[Added - diff]
verilog/rtl/ppcpu/soc/soc.v[Added - diff]
verilog/rtl/ppcpu/soc/soc_rom.v[Added - diff]
verilog/rtl/ppcpu/soc/spi.v[Added - diff]
verilog/rtl/ppcpu/soc/timer.v[Added - diff]
verilog/rtl/ppcpu/soc/uart.v[Added - diff]
verilog/rtl/ppcpu/test/arch/Makefile[Added - diff]
verilog/rtl/ppcpu/test/arch/aarith.s[Added - diff]
verilog/rtl/ppcpu/test/arch/arch.cpp[Added - diff]
verilog/rtl/ppcpu/test/arch/fncall.s[Added - diff]
verilog/rtl/ppcpu/test/arch/sreg0.s[Added - diff]
verilog/rtl/ppcpu/test/tb_core.cpp[Added - diff]
verilog/rtl/ppcpu/test/tb_decode.cpp[Added - diff]
verilog/rtl/ppcpu/test/tb_fetch.cpp[Added - diff]
verilog/rtl/ppcpu/test/tb_icache.cpp[Added - diff]
verilog/rtl/ppcpu/test/tb_memwb.cpp[Added - diff]
verilog/rtl/ppcpu/test/tb_upper_core.cpp[Added - diff]
verilog/rtl/ppcpu/test/upasm/run[Added - diff]
verilog/rtl/ppcpu/test/upasm/test_stdmem.s[Added - diff]
verilog/rtl/ppcpu/test/upasm/test_sys_and_pg.s[Added - diff]
verilog/rtl/ppcpu/test/upasm/upcore_asm.cpp[Added - diff]
verilog/rtl/ppcpu/test/wishbone/tb_mb_downconverter.cpp[Added - diff]
verilog/rtl/ppcpu/test/wishbone/tb_wishbone_arbiter.cpp[Added - diff]
verilog/rtl/ppcpu/test/wishbone/tb_wishbone_master.cpp[Added - diff]

61 files changed

tree: 05ff53076b2ff39cb1ed9e4ed2a3c295a735ff4a

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.