UETRV_ECORE_v2 is a RISC-V based SoC derived from UETRV_ESoC with a few changes . UETRV_ESoC_v2 has been passed through the Cadence VLSI flow for submission to Google and Efabless' Open MPW-8 shuttle program using Skywater‘s open-source 130 nm PDK (the project can be found on Efabless’ website here). The verilog RTL used in this repo is generated from Scala source, available here. Further details about the peripheral memory map, bootloader, example programs, testbenches etc. are also provided in that repo.
Practical demonstration of a plotter's operation controlled by UETRV_ESoC_v2, programmed to an FPGA, can be viewed in this video.
The following are the differences between UETRV_ESoC_v2 and UETRV_ESoC:
The io_ports testbench provided in the caravel_user_project template configures and tests GPIOs' functionality. It has been merged with UETRV_ESoC‘s testbench (old tb), resulting in io_ports_tb.v. This testbench runs full chip simulation by configuring the GPIOs using firmware for caravel’s management SoC. Following this, reset is applied which causes UETRV_ESoC_v2 to run its bootloader. The testbench mimics an SPI-based flash memory and loads a firmware into UETRV_ESoC_v2‘s instruction memory over GPIOs configured for SPI, in conjunction with the bootloader. Once loading of firmware is finished, the bootloader hands control over to the firmware. The firmware program transmits characters over UART, which are fed back to UETRV_ESoC_v2 by UART loopback. Some of these characters are commands for moving a plotter’s pen as described below:
The testbench waits for each command to occur and verifies that the step and direction outputs for two stepper motors moving the pen in the 2D-grid, and the PWM output for the servo motor lifting and dropping the pen, have changed properly.