SoC-osu: Single-cycle RISC-V processor developed by OSU.

Clone this repo:
  1. 8ec4089 Updating the shuttle_url value in `info.yaml` file. by Tim 'mithro' Ansell · 1 year, 7 months ago main
  2. 4d990ad caravel_fix by Jeff DiCorpo · 3 years, 1 month ago master
  3. 97cb8ba final gds & drc results by Jeff DiCorpo · 3 years, 5 months ago mpw-one-final
  4. a048dca final gds & drc results by Jeff DiCorpo · 3 years, 5 months ago
  5. 52f6cf8 Add checks folder from DRC-fixed precheck by Alex Underwood · 3 years, 5 months ago

OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.