commit: 8ec40893d27977b04fbbb0a2145fac03c8936ae3
[log] [tgz]
author: Tim 'mithro' Ansell <me@mith.ro>
Thu Dec 29 18:55:07 2022 +0000
committer: Tim 'mithro' Ansell <me@mith.ro>
Thu Dec 29 18:55:07 2022 +0000
tree: 346e814c819fa7ac9d6943e922b0afa0fe290e1c
parent: 4d990ad253eaf4f275ce79d6369283f93683d0f8 [diff]

Updating the shuttle_url value in `info.yaml` file.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

info.yaml[diff]

1 file changed

tree: 346e814c819fa7ac9d6943e922b0afa0fe290e1c

README.md

OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.