- b823400 Test read from RO port for dual port SRAMs by AmoghLonkar · 2 years, 11 months ago
- 5bd0765 Working testbench for logic analyzer interface by AmoghLonkar · 2 years, 11 months ago
- 395ad9d Finish serial communication with GPIO by AmoghLonkar · 2 years, 11 months ago
- 5ae71db Proper timing for single cycle input transfer by AmoghLonkar · 2 years, 11 months ago
- d6f65a9 sram_clk toggles as expected by AmoghLonkar · 2 years, 11 months ago
- ea2e590 Removed read_data register to reduce delay by AmoghLonkar · 2 years, 11 months ago
- 4e483a7 Get SRAM clock timing right by AmoghLonkar · 2 years, 11 months ago
- c5fa7ae Partial testbench by AmoghLonkar · 2 years, 11 months ago
- b7422ec Parsing input packet and making SRAM input connections by AmoghLonkar · 2 years, 11 months ago
- eaf938e Merge pull request #4 from AmoghLonkar/control_macro by Amogh Lonkar · 2 years, 11 months ago
- 7503247 Adding macro files by AmoghLonkar · 2 years, 11 months ago
- cf608e2 Use control logic macro by AmoghLonkar · 2 years, 11 months ago
- a99e3dd Merge pull request #3 from AmoghLonkar/chisel by Amogh Lonkar · 3 years ago
- 1f8c571 Adding chisel files by AmoghLonkar · 3 years ago
- 8487a58 TO-DO by AmoghLonkar · 3 years ago
- 40f794e Deleted old files by AmoghLonkar · 3 years ago
- b9a5f3a Deleted old files by AmoghLonkar · 3 years ago
- a927158 Deleted old files by AmoghLonkar · 3 years ago
- bb967ab Disabled Klayout XOR step by AmoghLonkar · 3 years ago
- 7c55d39 remove extra folders by Jesse Cirimelli-Low · 3 years ago
- 20d0669 remove extra files from repo; gbl routing to 0.2 by Jesse Cirimelli-Low · 3 years ago
- 28026c5 add extracted version of user project wrapper gds by Jesse Cirimelli-Low · 3 years ago
- 1926623 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip by Jesse Cirimelli-Low · 3 years ago
- 4fc0624 update lef power names by Jesse Cirimelli-Low · 3 years ago
- d55f176 Removed optimization envs because no standard cells by AmoghLonkar · 3 years ago
- b29e94a Added : by AmoghLonkar · 3 years ago
- f27be30 Initial macro arrangement by AmoghLonkar · 3 years ago
- d7ce953 Included single port files and fixed gds error by AmoghLonkar · 3 years ago
- 9bff904 Moved files to proper directories by AmoghLonkar · 3 years ago
- 9fa43b7 Updated power pin names by AmoghLonkar · 3 years ago
- 05994cf Updated power pin names by AmoghLonkar · 3 years ago
- 9375078 Updated power pin names by AmoghLonkar · 3 years ago
- 7dfc0e6 Updated power pin names by AmoghLonkar · 3 years ago
- eaf3d99 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip by Jesse Cirimelli-Low · 3 years ago
- ef394c4 update power pin names by Jesse Cirimelli-Low · 3 years ago
- 43506d4 Delete openram_testchip.lef by Amogh Lonkar · 3 years ago
- d60e9a9 Delete openram_testchip.gds by Amogh Lonkar · 3 years ago
- 7e4a9fd Updated wrapper to include new memory instances by AmoghLonkar · 3 years ago
- 5d91038 Updated verilog file for single port mem support by AmoghLonkar · 3 years ago
- a51bbbe Disabled optimizations, much faster by AmoghLonkar · 3 years ago
- 0581393 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 years ago
- e5369e1 New gds file by AmoghLonkar · 3 years ago
- 1a8f9b7 New lef file by AmoghLonkar · 3 years ago
- 61ce399 Delete sky130_sram_1kbyte_1rw1r_32x256_8.v by Amogh Lonkar · 3 years ago
- c8d0fb6 Merge pull request #2 from AmoghLonkar/feature/floorplan by Amogh Lonkar · 3 years ago
- 10663ac Merge branch 'main' into feature/floorplan by Amogh Lonkar · 3 years ago
- 49efff8 Update config file by AmoghLonkar · 3 years ago
- 56cda99 New SRAM macro by AmoghLonkar · 3 years ago
- 3bf691e New SRAM macro by AmoghLonkar · 3 years ago
- 6f08bba Update power pins on SRAM by AmoghLonkar · 3 years ago
- df0160f New file with changed power pins by AmoghLonkar · 3 years ago
- 9efc609 add singleport memories by Jesse Cirimelli-Low · 3 years ago
- 63f0643 Removed macro placement for control unit by AmoghLonkar · 3 years ago
- 41062a7 Updated config file to use pdn script and removed macro files for control logic by AmoghLonkar · 3 years ago
- 520c9fb Placed macros far apart to avoid overlap by AmoghLonkar · 3 years ago
- 00023dc Updated SRAM macro name by AmoghLonkar · 3 years ago
- 220784c Added intial macro placement by AmoghLonkar · 3 years ago
- 7d7491d Added wrapper gds and lef to env by AmoghLonkar · 3 years ago
- 714daf0 Modifications to pass synthesis by AmoghLonkar · 3 years ago
- a74fac0 Connecting control logic module to SRAMs and Caravel clock/IO interfaces by AmoghLonkar · 3 years ago
- accab47 Updating config file by AmoghLonkar · 3 years ago
- f56156e Adding lef files by AmoghLonkar · 3 years ago
- 868c59b Adding macros by AmoghLonkar · 3 years ago
- f8d3dbf Update config.tcl by AmoghLonkar · 3 years ago
- 9b07397 Added synthesizable verilog using Chisel by AmoghLonkar · 3 years ago
- a0b8d4a Delete test_chip.v by Amogh Lonkar · 3 years ago
- 54f9d9c Added rst logic by AmoghLonkar · 3 years ago
- 79717b9 Updated testchip to reflect synchronous logic by AmoghLonkar · 3 years ago
- b76334a Modified SRAM read logic by AmoghLonkar · 3 years ago
- da4b9cf Added rst conditions and needed to set web to low after writing. Mask/wdata when disabling is a small issue by AmoghLonkar · 3 years ago
- ad022ab Added FFs for inputs and outputs by AmoghLonkar · 3 years ago
- ced003a Adding script for Power Distribution Network. Taken from Professor's repo by AmoghLonkar · 3 years ago
- 3308457 Added clock net and pdn script from professor's repo by AmoghLonkar · 3 years ago
- 72c2d1a Added conditional defs for vdd, gnd by AmoghLonkar · 3 years ago
- 8090539 Changed paths to verilog dir by AmoghLonkar · 3 years ago
- 988bba9 Commented out include statements for yosys parsing by AmoghLonkar · 3 years ago
- 1ad4c69 Initial config file for hardening macro by AmoghLonkar · 3 years ago
- 646a136 Rename test_chip.v to openram_testchip.v by Amogh Lonkar · 3 years ago
- 6fe1dd3 Renamed module and filename for yosys parsing by AmoghLonkar · 3 years ago
- 9f7f84b Merge pull request #1 from AmoghLonkar/feature/control_logic by Amogh Lonkar · 3 years ago
- b7d2984 Delete defines.v by Amogh Lonkar · 3 years ago
- 8c3a274 Delete storage.v by Amogh Lonkar · 3 years ago
- d289bd3 Working testbench for test chip with 2 SRAMs by AmoghLonkar · 3 years ago
- f91aaa7 Connected output port by AmoghLonkar · 3 years ago
- b9ee443 Incorporated port mux logic into tests by AmoghLonkar · 3 years ago
- 48d0c8c Added extra module to mux in data from both read ports by AmoghLonkar · 3 years ago
- 4852de0 Instantiated all modules and connections by AmoghLonkar · 3 years ago
- 2fa2292 Read and split input packet from logic analyzer or GPIO by AmoghLonkar · 3 years ago
- fbb0983 Adding wrapper for control logic and SRAM modules by AmoghLonkar · 3 years ago
- 386bcc4 Passes read and write tests to both SRAMs by AmoghLonkar · 3 years ago
- e612a20 Compiles, assertions failing by AmoghLonkar · 3 years ago
- 16928ae Wrote test for writing to SRAM, compilation fails by AmoghLonkar · 3 years ago
- d98506e Instantiated all required modules by AmoghLonkar · 3 years ago
- 333b2a1 Instantiated all required modules by AmoghLonkar · 3 years ago
- 573f629 Added extra input for chip select in input module and truncated packet by AmoghLonkar · 3 years ago
- 54fff2a Removed compilation errors, need to test by AmoghLonkar · 3 years ago
- 3488ee5 Added new module to receive read data from SRAMs, getting 'not valid l-value error' by AmoghLonkar · 3 years ago
- d286473 Added new module to receive read data from SRAMs by AmoghLonkar · 3 years ago
- 8acfe86 Made separate module for forwarding input to SRAM by AmoghLonkar · 3 years ago
- dbc6c5a Made separate module for forwarding input to SRAM by AmoghLonkar · 3 years ago
