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foss-eda-tools / third_party / shuttle / sky130 / mpw-002 / slot-009 / HEAD
  1. 076f16c Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 years, 5 months ago
  2. f70bb92 Added global csr pin by AmoghLonkar · 3 years, 5 months ago
  3. eb5a605 Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 years, 5 months ago
  4. 8bde8f8 Remove extra character by mrg · 3 years, 5 months ago
  5. d617e93 Fixed index on GPIO output pin range by AmoghLonkar · 3 years, 5 months ago
  6. 2603fb9 Remove old verilog by mrg · 3 years, 5 months ago
  7. d54b7b1 Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 years, 5 months ago
  8. 0d14b0b Use single clock, top-level gate place and route by mrg · 3 years, 5 months ago
  9. 3ff7d07 Add clock_mux by AmoghLonkar · 3 years, 5 months ago
  10. 9ccd2e3 Added reg declaration for sram_data and removed duplicate sram_dout declaration by AmoghLonkar · 3 years, 5 months ago
  11. 3a0040d Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 years, 5 months ago
  12. 0dd2159 Resolve clock port and net issue by making clock_mux by mrg · 3 years, 5 months ago
  13. dbb04f6 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 years, 5 months ago
  14. 309e08c Changed module name, compiles without error by AmoghLonkar · 3 years, 5 months ago
  15. 3a93f37 Delete openram_testchip_tb.v by Amogh Lonkar · 3 years, 5 months ago
  16. 7c387d1 Correct pattern by AmoghLonkar · 3 years, 5 months ago
  17. 7c0e55a Pin 21 for output by AmoghLonkar · 3 years, 5 months ago
  18. d15e74c Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 years, 5 months ago
  19. 8188070 Change reset to resetn by mrg · 3 years, 5 months ago
  20. 9ff09f0 Proper assignment to idle sramX_dataY by AmoghLonkar · 3 years, 5 months ago
  21. ee5398d Removed duplicate declaration for sramX_doutY by AmoghLonkar · 3 years, 5 months ago
  22. 144ab80 Included the relevant files by AmoghLonkar · 3 years, 5 months ago
  23. 6ec2acd Switched from index to explicitly declared shift by AmoghLonkar · 3 years, 5 months ago
  24. af01516 Working simulation over GPIO interface by AmoghLonkar · 3 years, 5 months ago
  25. 37e8d43 In scan and memory operations correct, do correct out scan of GPIO bits by AmoghLonkar · 3 years, 5 months ago
  26. 197c62f openram_testchip_la_tb.v by AmoghLonkar · 3 years, 5 months ago
  27. df3c015 Replaced index with shift by AmoghLonkar · 3 years, 5 months ago
  28. 1ccad06 Works for all memories using LA interface by AmoghLonkar · 3 years, 5 months ago
  29. 041a753 Works for dual port memories by AmoghLonkar · 3 years, 5 months ago
  30. aef5f1a Switched to for loops, check why assertion fails by AmoghLonkar · 3 years, 5 months ago
  31. 741732c Switched to for loops, check why assertion fails by AmoghLonkar · 3 years, 5 months ago
  32. dca58fa Used defines for splitting into fields by AmoghLonkar · 3 years, 5 months ago
  33. 4b706b1 Set correct indices for storing read out, inefficient csb0 port assignment by AmoghLonkar · 3 years, 5 months ago
  34. 1388555 Working for LA for SRAM0, finish for other SRAMs by AmoghLonkar · 3 years, 5 months ago
  35. d0c71b0 Compiles without errors and warnings by AmoghLonkar · 3 years, 5 months ago
  36. 31eb2d3 Proper address wire connection by AmoghLonkar · 3 years, 5 months ago
  37. e8af1ae Proper bits and variable name for temp_sram11_dout0 by AmoghLonkar · 3 years, 5 months ago
  38. 2b607c0 TO-DO: Remove sram clk from ports by AmoghLonkar · 3 years, 5 months ago
  39. f11d9b5 Changed sramX_doutY to sramX_dataY by AmoghLonkar · 3 years, 5 months ago
  40. f3080b6 Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 years, 5 months ago
  41. a7d42c9 Figure out temp_sram11_dout0 binding issue by AmoghLonkar · 3 years, 5 months ago
  42. 8de4e28 Incrase PL_DIAMOND_SEARCH_HEIGHT by mrg · 3 years, 5 months ago
  43. 2cd561f Remove errors in configs by mrg · 3 years, 5 months ago
  44. f8348ee Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main by mrg · 3 years, 5 months ago
  45. b8597a7 Move sram_clk to user_project_wrapper by mrg · 3 years, 5 months ago
  46. 5b5b2e7 Proper variable names for csb by AmoghLonkar · 3 years, 5 months ago
  47. 43fb1ea Fixed TOTAL_SIZE by AmoghLonkar · 3 years, 5 months ago
  48. 7c79b4d Merge branch 'main' of https://github.com/AmoghLonkar/openram_testchip into main by AmoghLonkar · 3 years, 5 months ago
  49. 9e6146a New port connections by AmoghLonkar · 3 years, 5 months ago
  50. 53295f0 Add custom SDC script by mrg · 3 years, 5 months ago
  51. 48dbc1e Update macros by mrg · 3 years, 5 months ago
  52. 7f4fa4b Fix wire width output from SRAM11 by mrg · 3 years, 5 months ago
  53. 2f1a8ef Debug user_project_wrapper verilog by mrg · 3 years, 5 months ago
  54. 44a125a Don't route clocks until debugged by mrg · 3 years, 5 months ago
  55. 231495b Don't check supply connectivity. Resolve multiple pin regex warning. by mrg · 3 years, 5 months ago
  56. 0418bc2 Update macro placement. Remove a dual port mem. by mrg · 3 years, 5 months ago
  57. 5f35125 Fix port size by AmoghLonkar · 3 years, 5 months ago
  58. 08b141b Initial floorplan by mrg · 3 years, 5 months ago
  59. 9e8c375 Add pins to sides of block. by mrg · 3 years, 5 months ago
  60. 3dbe3c4 Merge pull request #5 from AmoghLonkar/control_verilog by Amogh Lonkar · 3 years, 5 months ago
  61. 34e4779 Make macro almost chip height by mrg · 3 years, 5 months ago
  62. e004c29 Update so 0..7 is dual and 8..15 is single by mrg · 3 years, 5 months ago
  63. 0c951e1 Use defines in the design by mrg · 3 years, 5 months ago
  64. 763d546 Increase area so we can have enough IO pins by mrg · 3 years, 5 months ago
  65. cc5c1f2 Fix control block errors. Instantiate more memories. by mrg · 3 years, 5 months ago
  66. 45f14ab Add all dual port memories by mrg · 3 years, 5 months ago
  67. 605185e Update wrapper for new control. by mrg · 3 years, 5 months ago
  68. b40bbc7 Update for max of 16 SRAMs by mrg · 3 years, 5 months ago
  69. a976e9e Sent sram_clk to each SRAM from within Control module by AmoghLonkar · 3 years, 5 months ago
  70. 737be46 Single port for gpio scanning, connected out_data to MSB by AmoghLonkar · 3 years, 5 months ago
  71. cb196fa Works for SRAM0 by AmoghLonkar · 3 years, 5 months ago
  72. 954cb24 Figure out why correct dout is not stored in sram_register by AmoghLonkar · 3 years, 5 months ago
  73. c52702b Fixed read_data bit width by AmoghLonkar · 3 years, 5 months ago
  74. ff1d0fc Figure out why csb0, web0, etc are changing by AmoghLonkar · 3 years, 5 months ago
  75. 15b80b2 Fixed sram clock selection by AmoghLonkar · 3 years, 5 months ago
  76. 66e1cb8 Writes to SRAM0 correctly by AmoghLonkar · 3 years, 5 months ago
  77. 78ec137 Fixed dual port address bits, set sram DFF to 32 bits, idle SRAM inputs to 1 by AmoghLonkar · 3 years, 5 months ago
  78. 7a68107 Set dout inputs to 32 bits by AmoghLonkar · 3 years, 5 months ago
  79. 5d991a9 Made connections, compiles, set proper values by AmoghLonkar · 3 years, 5 months ago
  80. caefc58 Set proper bits. Compiles without errors, need to test by AmoghLonkar · 3 years, 5 months ago
  81. a83e12c Removed two extra registers to hold dout0,1 by AmoghLonkar · 3 years, 5 months ago
  82. c9d38d5 Incorporated control signals. TO-DO: Figure out how to integrate 64b data, currently only supports 32b by AmoghLonkar · 3 years, 6 months ago
  83. 4602c4e Added control signal inputs and loading sram register by AmoghLonkar · 3 years, 6 months ago
  84. d6591e8 Removed sram clk logic and converted output connections to combinational logic by AmoghLonkar · 3 years, 6 months ago
  85. eb10e35 Merge branch 'control_verilog' of https://github.com/AmoghLonkar/openram_testchip into control_verilog by AmoghLonkar · 3 years, 6 months ago
  86. 617c9f5 Delete chisel directory by Amogh Lonkar · 3 years, 6 months ago
  87. 8269657 Macro with two clock ports by AmoghLonkar · 3 years, 6 months ago
  88. 1b30acd Delete clks.sdc by Amogh Lonkar · 3 years, 6 months ago
  89. 6a2b76e Delete openram_testchip_tb.v by Amogh Lonkar · 3 years, 6 months ago
  90. c6b61a8 Delete openram_testchip.v by Amogh Lonkar · 3 years, 6 months ago
  91. 5bb2036 Macro for verilog based control module by AmoghLonkar · 3 years, 6 months ago
  92. c0fe556 Two input clocks for control module by AmoghLonkar · 3 years, 6 months ago
  93. ec3c4bf Fixed io pin typos by AmoghLonkar · 3 years, 6 months ago
  94. 58d416f Clock selection at top level by AmoghLonkar · 3 years, 6 months ago
  95. dc757e4 Use new verilog control module by AmoghLonkar · 3 years, 6 months ago
  96. 245e98f Single clock by AmoghLonkar · 3 years, 6 months ago
  97. a44330c Macros from new verilog control by AmoghLonkar · 3 years, 6 months ago
  98. c16cb81 LA Testbench by AmoghLonkar · 3 years, 6 months ago
  99. 92534d0 Output transfer started properly by AmoghLonkar · 3 years, 6 months ago
  100. ceae645 GPIO serial loading works, do data transfer by AmoghLonkar · 3 years, 6 months ago