commit: 2fa2292f0cc9540bc7ddf00734fa92f226f1dfec
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Thu May 13 07:41:36 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Thu May 13 07:41:36 2021 -0700
tree: eb13c76f9bfbd3319dff0d4a9036d800fba9ff17
parent: fbb0983fbd80025a218e3a7c3089b91c7d4479ec [diff]

Read and split input packet from logic analyzer or GPIO

verilog/rtl/testchip/test_chip.v[diff]

1 file changed

tree: eb13c76f9bfbd3319dff0d4a9036d800fba9ff17

README.md

Caravel User Project

NOTE

Fill this README with your caravel user project documentation.

Refer to README for this sample project documentation.