)]}'
{
  "commit": "2fa2292f0cc9540bc7ddf00734fa92f226f1dfec",
  "tree": "eb13c76f9bfbd3319dff0d4a9036d800fba9ff17",
  "parents": [
    "fbb0983fbd80025a218e3a7c3089b91c7d4479ec"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu May 13 07:41:36 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu May 13 07:41:36 2021 -0700"
  },
  "message": "Read and split input packet from logic analyzer or GPIO\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d332b8a1a45c864b7b72ceffa65f49255bfb6934",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/test_chip.v",
      "new_id": "df38cbdf80a977e0a14fe53b2aed2a3139c74e03",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/test_chip.v"
    }
  ]
}