commit: 5bd0765a2404b2a5bd74ef6407ab0a906ab5f241
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 15:51:41 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 15:51:41 2021 -0700
tree: 10c6c58aba07f9db2d239aebe57e3e9cf5e8a248
parent: 395ad9d504277264bdf699b3675c0cebbbd83cfd [diff]

Working testbench for logic analyzer interface

verilog/rtl/openram_testchip_tb.v[diff]

1 file changed

tree: 10c6c58aba07f9db2d239aebe57e3e9cf5e8a248

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.