)]}'
{
  "commit": "5bd0765a2404b2a5bd74ef6407ab0a906ab5f241",
  "tree": "10c6c58aba07f9db2d239aebe57e3e9cf5e8a248",
  "parents": [
    "395ad9d504277264bdf699b3675c0cebbbd83cfd"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu Jun 10 15:51:41 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu Jun 10 15:51:41 2021 -0700"
  },
  "message": "Working testbench for logic analyzer interface\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "38f441af454633f200c19e490bcfbb7d33d20702",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "c6229ac3f095b5677f90352eeb29368a3eb0dc39",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
    }
  ]
}