commit: 988bba95b3c20fd37149c341848c8f858daffe9f
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 10:36:14 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 10:36:14 2021 -0700
tree: df091a35a3b7f3e995b4692ec31c7dd732748730
parent: 1ad4c6971a6f377b58f412229031b72ba37f280b [diff]

Commented out include statements for yosys parsing

verilog/rtl/testchip/openram_testchip.v[diff]

1 file changed

tree: df091a35a3b7f3e995b4692ec31c7dd732748730

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.