)]}'
{
  "commit": "988bba95b3c20fd37149c341848c8f858daffe9f",
  "tree": "df091a35a3b7f3e995b4692ec31c7dd732748730",
  "parents": [
    "1ad4c6971a6f377b58f412229031b72ba37f280b"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 10:36:14 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 10:36:14 2021 -0700"
  },
  "message": "Commented out include statements for yosys parsing\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8afe30f05180d9430da7520fa52a9caf3fcc03c6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/openram_testchip.v",
      "new_id": "597d02dcd6326e3fb6a2e6709ee6a364102790d9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/openram_testchip.v"
    }
  ]
}