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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
714daf0bd9255f6965762a05ffb16c044d946d47
commit
714daf0bd9255f6965762a05ffb16c044d946d47
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log
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tgz
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author
AmoghLonkar <alonkar@ucsc.edu>
Tue May 18 09:58:30 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Tue May 18 09:58:30 2021 -0700
tree
c066fd88978a1b7d0c35e582d417739d8161ed6c
parent
a74fac0f1afd4380ae744ffab19e510e46d64e30
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diff
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Modifications to pass synthesis
verilog/rtl/user_project_wrapper.v
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diff
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1 file changed
tree: c066fd88978a1b7d0c35e582d417739d8161ed6c
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
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README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.