Modifications to pass synthesis
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3ddbcc9..7208a36 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -78,52 +78,6 @@ output [2:0] user_irq ); -/*--------------------------------------*/ -/* User project is instantiated here */ -/*--------------------------------------*/ - -user_proj_example mprj ( - `ifdef USE_POWER_PINS - .vdda1(vdda1), // User area 1 3.3V power - .vdda2(vdda2), // User area 2 3.3V power - .vssa1(vssa1), // User area 1 analog ground - .vssa2(vssa2), // User area 2 analog ground - .vccd1(vccd1), // User area 1 1.8V power - .vccd2(vccd2), // User area 2 1.8V power - .vssd1(vssd1), // User area 1 digital ground - .vssd2(vssd2), // User area 2 digital ground - `endif - - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - - // MGMT SoC Wishbone Slave - - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - - // IO Pads - - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), - - // IRQ - .irq(user_irq) -); - wire [54:0] sram0_connections; wire [54:0] sram1_connections; @@ -145,13 +99,9 @@ .io_sram0_connections(sram0_connections), .io_sram1_connections(sram1_connections), .io_sram_data(la_data_out[31:0]) -) +); -sky130_sram_1kbyte_1rw1r_32x256_8 - #(// FIXME: This delay is arbitrary. - .DELAY (3), - .VERBOSE (0)) - SRAM0 +sky130_sram_1kbyte_1rw1r_32x256_8 SRAM0 ( .clk0 (wb_clk_i), .csb0 (sram0_connections[54]), @@ -165,11 +115,7 @@ .addr1 (sram0_connections[7:0]), .dout1 (sram0_ro_out)); -sky130_sram_1kbyte_1rw1r_32x256_8 - #(// FIXME: This delay is arbitrary. - .DELAY (3), - .VERBOSE (0)) - SRAM1 +sky130_sram_1kbyte_1rw1r_32x256_8 SRAM1 ( .clk0 (wb_clk_i), .csb0 (sram1_connections[54]),