commit: a74fac0f1afd4380ae744ffab19e510e46d64e30
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Tue May 18 09:48:21 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Tue May 18 09:48:21 2021 -0700
tree: 4f201841a38f28ff8ac4fdcf7e1e056c1b7d29f9
parent: accab4798add03d574b16cbf9ceb3432d43cac6c [diff]

Connecting control logic module to SRAMs and Caravel clock/IO interfaces

verilog/rtl/user_project_wrapper.v[diff]

1 file changed

tree: 4f201841a38f28ff8ac4fdcf7e1e056c1b7d29f9

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.