commit: 386bcc4ffb128b10d78aa17640df0f45b91f25dc
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Wed May 12 21:38:23 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Wed May 12 21:38:23 2021 -0700
tree: 6a15725e316933ff7d4ab4b98bb0775819dbf428
parent: e612a20f1646590234b790fb099ddad43ddb7316 [diff]

Passes read and write tests to both SRAMs

verilog/rtl/testchip/control_logic_tb.v[diff]

1 file changed

tree: 6a15725e316933ff7d4ab4b98bb0775819dbf428

README.md

Caravel User Project

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Refer to README for this sample project documentation.