)]}'
{
  "commit": "386bcc4ffb128b10d78aa17640df0f45b91f25dc",
  "tree": "6a15725e316933ff7d4ab4b98bb0775819dbf428",
  "parents": [
    "e612a20f1646590234b790fb099ddad43ddb7316"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Wed May 12 21:38:23 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Wed May 12 21:38:23 2021 -0700"
  },
  "message": "Passes read and write tests to both SRAMs\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "824533c6e113fe52929b0b18ea400aa905c8cec3",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/control_logic_tb.v",
      "new_id": "162fe659c3f9ce056c8658575a37a923972a4bbc",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/control_logic_tb.v"
    }
  ]
}