commit: 5d91038d46b355c4e137e9f6caf23f94a8711071
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Sun May 30 22:03:19 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sun May 30 22:03:19 2021 -0700
tree: 202d33add9961a1a10c00d52653122903908ad37
parent: a51bbbe5d2d1ad6fcb686a4e4d8f8f8044dad48b [diff]

Updated verilog file for single port mem support

verilog/rtl/testchip/openram_testchip.v[diff]

1 file changed

tree: 202d33add9961a1a10c00d52653122903908ad37

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.