commit: 6fe1dd359ef3b3caa68c8ee99d9446a4d911b5b9
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Sun May 16 21:38:36 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Sun May 16 21:38:36 2021 -0700
tree: 83271044c486c8aa2627869780633ba2736682fc
parent: 9f7f84b188ee739e23b8666f40e6f1772b89db51 [diff]

Renamed module and filename for yosys parsing

verilog/rtl/testchip/openram_testchip.v[Added - diff]

1 file changed

tree: 83271044c486c8aa2627869780633ba2736682fc

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.