)]}'
{
  "commit": "6fe1dd359ef3b3caa68c8ee99d9446a4d911b5b9",
  "tree": "83271044c486c8aa2627869780633ba2736682fc",
  "parents": [
    "9f7f84b188ee739e23b8666f40e6f1772b89db51"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sun May 16 21:38:36 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sun May 16 21:38:36 2021 -0700"
  },
  "message": "Renamed module and filename for yosys parsing\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8afe30f05180d9430da7520fa52a9caf3fcc03c6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/openram_testchip.v"
    }
  ]
}