Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
ad022ab9abe47e919730bf0378d498632b06cfc8
commit
ad022ab9abe47e919730bf0378d498632b06cfc8
[
log
]
[
tgz
]
author
AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 18:37:35 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 18:37:35 2021 -0700
tree
aed112ba576193e317e1cf77f682b959db0a6cde
parent
ced003af83e0ee3afc9a31b2a3dfe297ff647e5f
[
diff
]
Added FFs for inputs and outputs
verilog/rtl/testchip/control_logic.v
[
diff
]
1 file changed
tree: aed112ba576193e317e1cf77f682b959db0a6cde
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.