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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
6f08bba30c8aebcb6bc67020ecce4f11dc3202e3
commit
6f08bba30c8aebcb6bc67020ecce4f11dc3202e3
[
log
]
[
tgz
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author
AmoghLonkar <alonkar@ucsc.edu>
Sat May 29 21:21:23 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Sat May 29 21:21:23 2021 -0700
tree
afe6c6f3fa6c131f96e9a3e3cf5da4577e33507d
parent
df0160f6b8bf4d2c49ef76c1ae3fa7597d79d906
[
diff
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Update power pins on SRAM
verilog/rtl/user_project_wrapper.v
[
diff
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1 file changed
tree: afe6c6f3fa6c131f96e9a3e3cf5da4577e33507d
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
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LICENSE
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README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.