Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
72c2d1a2a8f67973ff201990d203a48b79f3dceb
commit
72c2d1a2a8f67973ff201990d203a48b79f3dceb
[
log
]
[
tgz
]
author
AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 11:16:24 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 11:16:24 2021 -0700
tree
c004439773e25e73305fb0ff5c37a9cfc2c7dddf
parent
809053906ca98531e388b32b752ca6c9c554e20a
[
diff
]
Added conditional defs for vdd, gnd
verilog/rtl/testchip/openram_testchip.v
[
diff
]
verilog/rtl/testchip/sky130_sram_1kbyte_1rw1r_32x256_8.v
[
diff
]
2 files changed
tree: c004439773e25e73305fb0ff5c37a9cfc2c7dddf
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.