)]}'
{
  "commit": "72c2d1a2a8f67973ff201990d203a48b79f3dceb",
  "tree": "c004439773e25e73305fb0ff5c37a9cfc2c7dddf",
  "parents": [
    "809053906ca98531e388b32b752ca6c9c554e20a"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 11:16:24 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 11:16:24 2021 -0700"
  },
  "message": "Added conditional defs for vdd, gnd\n",
  "tree_diff": [
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      "new_path": "verilog/rtl/testchip/openram_testchip.v"
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}