commit: 48d0c8c4bf3f933ea7e4dd10cc6babfa0b7b4ff5
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Thu May 13 08:03:07 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Thu May 13 08:03:07 2021 -0700
tree: 063992597b9b378b3f97d84f76588e3fa6d4b684
parent: 4852de0725ada0780fc7863025716d60258bc94a [diff]

Added extra module to mux in data from both read ports

verilog/rtl/testchip/control_logic.v[diff]

1 file changed

tree: 063992597b9b378b3f97d84f76588e3fa6d4b684

README.md

Caravel User Project

NOTE

Fill this README with your caravel user project documentation.

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