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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
54f9d9caac54965f0729db719437f17c4e36ff1a
commit
54f9d9caac54965f0729db719437f17c4e36ff1a
[
log
]
[
tgz
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author
AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 19:27:14 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 19:27:14 2021 -0700
tree
c9a52d2f00af6908307c26a5b7a5bd378c2294e2
parent
79717b92d1b850f7dbf0e9a4f983b2ade111a492
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diff
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Added rst logic
verilog/rtl/testchip/openram_testchip.v
[
diff
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1 file changed
tree: c9a52d2f00af6908307c26a5b7a5bd378c2294e2
.github/
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docs/
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lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
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