commit: 79717b92d1b850f7dbf0e9a4f983b2ade111a492
[log] [tgz]
author: AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 19:25:26 2021 -0700
committer: AmoghLonkar <alonkar@ucsc.edu>
Mon May 17 19:25:26 2021 -0700
tree: 260345564f07f58c64cddd5e3be6f6b6d3b4f54e
parent: b76334ad0533b8cd4b05b4a5dc2348f4b261da93 [diff]

Updated testchip to reflect synchronous logic

verilog/rtl/testchip/test_chip_tb.v[diff]

1 file changed

tree: 260345564f07f58c64cddd5e3be6f6b6d3b4f54e

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.