update
diff --git a/caravel b/caravel
index 1a96c0e..192a5b1 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 1a96c0e34b42e9f1d7c79acdac5cd46c2327e1b5
+Subproject commit 192a5b1fe5cd068c3a8a7b30aee8458ca738f73b
diff --git a/openlane/.flake8 b/openlane/.flake8
new file mode 100644
index 0000000..3293868
--- /dev/null
+++ b/openlane/.flake8
@@ -0,0 +1,11 @@
+[flake8]
+ignore = E203,E266,E302,E501,W503
+exclude =
+ .git,
+ __pycache__,
+ scripts/klayout,
+ docker/tar,
+ install/,
+ venv/,
+ pdks/,
+ dependencies/includedyaml
\ No newline at end of file
diff --git a/openlane/.gitattributes b/openlane/.gitattributes
new file mode 100644
index 0000000..1253c4c
--- /dev/null
+++ b/openlane/.gitattributes
@@ -0,0 +1,3 @@
+# Settings to improve linguist data reporting (used by GitHub) (copied from Tim Ansell: https://github.com/SymbiFlow/symbiflow-examples/commit/70b13fe74a56dd5ebfa2060c2473050dfff1a0c6#diff-fc723d30b02a4cca7a534518111c1a66)
+*.v linguist-language=Verilog
+*.vh linguist-language=Verilog
diff --git a/openlane/.github/ISSUE_TEMPLATE/bug_report.md b/openlane/.github/ISSUE_TEMPLATE/bug_report.md
new file mode 100644
index 0000000..1ac33e2
--- /dev/null
+++ b/openlane/.github/ISSUE_TEMPLATE/bug_report.md
@@ -0,0 +1,39 @@
+---
+name: Bug Report
+about: If OpenLane is not behaving as expected, please report here.
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+<!-- NOTE: This template is NOT a suggestion. Issues not using this template will be marked invalid. -->
+
+### Description
+A clear and concise description of what the bug is.
+
+### Environment
+```
+Please run the following set of commands in the OpenLane folder:
+
+make survey || python3 ./env.py issue-survey
+
+And copy and paste the ENTIRE output between the triple-backticks. Please do not gzip and upload the output.
+
+If neither command succeeds, you are using an out of date version of OpenLane and should probably update.
+```
+
+### Reproduction Material
+* Upload a tarball containing the relevant design.
+* List the commands used to run the design.
+
+If you see a message like `Reproducible packaged: Please tarball and upload <PATH> if you're going to submit an issue` in your logs, please also tarball and include that path. This will greatly speed up the fixing process.
+
+### Expected behavior
+A clear and concise description of what you expected to happen.
+
+### Logs
+```
+Add any relevant logs here. Please do ensure they're enclosed by the triple-backticks.
+```
+
diff --git a/openlane/.github/ISSUE_TEMPLATE/feature_request.md b/openlane/.github/ISSUE_TEMPLATE/feature_request.md
new file mode 100644
index 0000000..54ddb03
--- /dev/null
+++ b/openlane/.github/ISSUE_TEMPLATE/feature_request.md
@@ -0,0 +1,14 @@
+---
+name: Feature Requests and Enhancements
+about: Have any ideas? Find any shortcomings? Feel free to share them.
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+### Prompt
+A clear and concise description of what shortcoming you feel OpenLane has.
+
+### Proposal
+A clear and concise description of what you want to happen.
diff --git a/openlane/.github/diagrams/flow.png b/openlane/.github/diagrams/flow.png
new file mode 100644
index 0000000..84ce0c7
--- /dev/null
+++ b/openlane/.github/diagrams/flow.png
Binary files differ
diff --git a/openlane/.github/diagrams/src/actor.png b/openlane/.github/diagrams/src/actor.png
new file mode 100644
index 0000000..15e02a4
--- /dev/null
+++ b/openlane/.github/diagrams/src/actor.png
Binary files differ
diff --git a/openlane/.github/diagrams/src/flow.dot b/openlane/.github/diagrams/src/flow.dot
new file mode 100644
index 0000000..f405bca
--- /dev/null
+++ b/openlane/.github/diagrams/src/flow.dot
@@ -0,0 +1,69 @@
+digraph G {
+ subgraph main {
+ rankDir=UD;
+ compound=true;
+ nodesep=2;
+ margin=0
+ style="invis"
+
+ scheduler [
+ shapefile="./actor.png",
+ peripheries = 0,
+ label="\n\n\n\n\n\n\n\nGitHub Actions Cron",
+ rank=min
+ ]
+
+ contributor [
+ shapefile="./actor.png",
+ peripheries = 0,
+ label="\n\n\n\n\n\n\n\nContributor",
+ rank=min
+ ]
+
+ maintainer [
+ shapefile="./actor.png",
+ peripheries = 0,
+ label="\n\n\n\n\n\n\n\nMaintainer",
+ rank=min
+ ]
+
+ edge [arrowhead="vee", label=""];
+
+ # Tool Updater Flow
+ scheduler -> "Tool Updater" [label="Every Midnight UTC"]
+
+ "Tool Updater" -> "Check for PDK Updates"
+ "Tool Updater" -> "Check for Tool Updates"
+
+ "Check for Tool Updates" -> "Pull Request" [label="[updates found]"]
+ "Check for PDK Updates" -> "Pull Request"
+ [label="[updates found]"]
+
+ # Pull Request Flow
+ bdi_fast [
+ label="Build Docker Image"
+ ]
+ contributor -> "Pull Request"
+ "Pull Request" -> bdi_fast
+ bdi_fast -> "Fastest Test Set" [label="[image built successfully]"]
+ bdi_fast -> "PR CI Fails" [label="[else]"]
+ "Fastest Test Set" -> "Valid Pull Request" [label="[test pass]"]
+ "Fastest Test Set" -> "PR CI Fails" [label="[else]"]
+ "Valid Pull Request" -> "Review"
+ maintainer -> "Review" [label="approve"]
+ "Review" -> "Good Pull Request"
+
+ # Extended Test Set Flow
+ bdi_full [
+ label="Build Docker Image"
+ ]
+ maintainer -> bdi_full [label="Manual Dispatch"]
+ scheduler -> bdi_full [ label="Every Midnight UTC"]
+ bdi_full -> "Extended Test Set" [label="[image built successfully]"]
+ bdi_full -> "Deployment CI Fails" [label="[else]"]
+ "Extended Test Set" -> "Create New Version" [label="[tests pass]"]
+ "Extended Test Set" -> "Deployment CI Fails" [label="[else]"]
+ "Create New Version" -> "Deploy Docker Image To DockerHub"
+ }
+
+}
\ No newline at end of file
diff --git a/openlane/.github/legacy_diagrams/cron_job_workflow.png b/openlane/.github/legacy_diagrams/cron_job_workflow.png
new file mode 100644
index 0000000..4cfe388
--- /dev/null
+++ b/openlane/.github/legacy_diagrams/cron_job_workflow.png
Binary files differ
diff --git a/openlane/.github/legacy_diagrams/delete_workflow.png b/openlane/.github/legacy_diagrams/delete_workflow.png
new file mode 100644
index 0000000..f63231b
--- /dev/null
+++ b/openlane/.github/legacy_diagrams/delete_workflow.png
Binary files differ
diff --git a/openlane/.github/legacy_diagrams/pull_request_workflow.png b/openlane/.github/legacy_diagrams/pull_request_workflow.png
new file mode 100644
index 0000000..e075cff
--- /dev/null
+++ b/openlane/.github/legacy_diagrams/pull_request_workflow.png
Binary files differ
diff --git a/openlane/.github/legacy_diagrams/push_to_branch_workflow.png b/openlane/.github/legacy_diagrams/push_to_branch_workflow.png
new file mode 100644
index 0000000..4de9d4a
--- /dev/null
+++ b/openlane/.github/legacy_diagrams/push_to_branch_workflow.png
Binary files differ
diff --git a/openlane/.github/legacy_diagrams/push_to_cid_latest_x_branch_workflow.png b/openlane/.github/legacy_diagrams/push_to_cid_latest_x_branch_workflow.png
new file mode 100644
index 0000000..fbe8c06
--- /dev/null
+++ b/openlane/.github/legacy_diagrams/push_to_cid_latest_x_branch_workflow.png
Binary files differ
diff --git a/openlane/.github/scripts/determine_test_set.py b/openlane/.github/scripts/determine_test_set.py
new file mode 100644
index 0000000..9173422
--- /dev/null
+++ b/openlane/.github/scripts/determine_test_set.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from gh import gh
+import os
+import json
+
+github_event_name = os.environ["EVENT_NAME"]
+
+if github_event_name in ["schedule", "workflow_dispatch"]:
+ gh.export_env("USE_ETS", "1")
+elif github_event_name == "pull_request":
+ gh_event_str = open(os.environ["GITHUB_EVENT_PATH"]).read()
+ gh_event = json.loads(gh_event_str)
+ pr_body = gh_event["pull_request"]["body"] or ""
+
+ if "[ci ets]" in pr_body:
+ gh.export_env("USE_ETS", "1")
+ else:
+ gh.export_env("USE_ETS", "0")
+else:
+ gh.export_env("USE_ETS", "0")
diff --git a/openlane/.github/scripts/generate_tag.py b/openlane/.github/scripts/generate_tag.py
new file mode 100644
index 0000000..dc5b4a0
--- /dev/null
+++ b/openlane/.github/scripts/generate_tag.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import datetime
+import subprocess
+from gh import gh
+
+new_tag = "NO_NEW_TAG"
+
+print("Getting latest release index…")
+
+print("Getting the latest tag…")
+
+latest_tag = None
+latest_tag_commit = None
+for tag in gh.openlane.tags:
+ commit, name = tag
+ latest_tag = name
+ latest_tag_commit = commit
+
+commit_count = int(
+ subprocess.check_output(
+ ["git", "rev-list", "--count", "%s..%s" % (latest_tag_commit, "HEAD")]
+ )
+)
+
+if commit_count == 0:
+ print("No new commits. A tag will not be created.")
+else:
+ now = datetime.datetime.now()
+
+ new_tag = now.strftime("%Y.%m.%d_%H.%M.%S")
+
+ print("Naming new tag %s." % new_tag)
+
+gh.export_env("NEW_TAG", new_tag)
diff --git a/openlane/.github/scripts/gh.py b/openlane/.github/scripts/gh.py
new file mode 100644
index 0000000..e897395
--- /dev/null
+++ b/openlane/.github/scripts/gh.py
@@ -0,0 +1,148 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import subprocess
+from types import SimpleNamespace
+
+
+def export_env_default(key, value):
+ with open(os.getenv("GITHUB_ENV"), "a") as f:
+ f.write("%s=%s\n" % (key, value))
+
+
+export_env = export_env_default
+
+
+class Repo(object):
+ def __init__(self, name, url, branch_rx=None, extraction_rx=None):
+ print("[Repo Object] Initializing repo %s with URL %s…" % (name, url))
+ self.name = name
+ self.url = url
+ self.commit = None
+ self.branch_rx = branch_rx
+ self.extraction_rx = extraction_rx
+
+ self._latest_commit = None
+ self._branches = None
+ self._tags = None
+
+ @property
+ def latest_commit(self):
+ if self._latest_commit is None:
+ print("[Repo Object] Fetching latest commit for %s…" % self.name)
+ p = subprocess.check_output(["git", "ls-remote", self.url]).decode("utf8")
+ for line in p.split("\n"):
+ if "HEAD" in line:
+ self._latest_commit = line[:40]
+ return self._latest_commit
+
+ @property
+ def branches(self):
+ if self._branches is None:
+ print("[Repo Object] Fetching branches for %s…" % self.name)
+ p = subprocess.check_output(
+ ["git", "ls-remote", "--heads", self.url]
+ ).decode("utf8")
+ branches = []
+ for line in p.split("\n"):
+ if line.strip() == "":
+ continue
+
+ match = line.split()
+
+ hash = match[0]
+ name = match[1]
+
+ branches.append((hash, name))
+ self._branches = branches
+ return self._branches
+
+ @property
+ def tags(self):
+ if self._tags is None:
+ print("[Repo Object] Fetching tags for %s…" % self.name)
+ p = subprocess.check_output(
+ ["git", "ls-remote", "--tags", "--sort=creatordate", self.url]
+ ).decode("utf8")
+
+ tags = []
+ for line in p.split("\n"):
+ if line.strip() == "":
+ continue
+
+ match = line.split()
+
+ hash = match[0]
+ name = match[1].split("/")[2]
+
+ tags.append((hash, name))
+ self._tags = tags
+ return self._tags
+
+ def out_of_date(self):
+ return self.commit != self.latest_commit
+
+
+if os.getenv("GITHUB_ACTIONS") != "true":
+ dn = os.path.dirname
+ git_directory = dn(dn(dn(os.path.realpath(__file__))))
+
+ def git_command(*args):
+ return subprocess.check_output(["git"] + list(args), cwd=git_directory).decode(
+ "utf-8"
+ )[:-1]
+
+ repo_url = git_command("remote", "get-url", "origin")
+ branch = git_command("branch", "--show-current")
+
+ os.environ["REPO_URL"] = repo_url
+ os.environ["BRANCH_NAME"] = branch
+ os.environ["GITHUB_WORKSPACE"] = git_directory
+ os.environ["GITHUB_EVENT_NAME"] = "workspace_dispatch"
+ os.environ["GITHUB_RUN_ID"] = "mock_gha_run"
+
+ def export_env_alt(key, value):
+ os.environ[key] = value
+ print("Setting ENV[%s] to %s..." % (key, value))
+
+ export_env = export_env_alt
+
+ if os.getenv("PDK_ROOT") is None:
+ print('Environment variables required: "PDK_ROOT"')
+ exit(os.EX_CONFIG)
+
+ if os.getenv("OPENLANE_IMAGE_NAME") is None:
+ print('Environment variables required: "OPENLANE_IMAGE_NAME"')
+ exit(os.EX_CONFIG)
+
+origin = os.getenv("REPO_URL")
+repo = Repo("Openlane", origin)
+
+# public
+gh = SimpleNamespace(
+ **{
+ "run_id": os.getenv("GITHUB_RUN_ID"),
+ "origin": origin,
+ "branch": os.getenv("BRANCH_NAME"),
+ "image": os.getenv("OPENLANE_IMAGE_NAME"),
+ "root": os.getenv("GITHUB_WORKSPACE"),
+ "pdk": os.getenv("PDK_ROOT"),
+ "tool": os.getenv("TOOL"),
+ "event": SimpleNamespace(**{"name": os.getenv("GITHUB_EVENT_NAME")}),
+ "export_env": export_env,
+ "Repo": Repo,
+ "openlane": repo,
+ }
+)
diff --git a/openlane/.github/scripts/run_tests.py b/openlane/.github/scripts/run_tests.py
new file mode 100644
index 0000000..a726c21
--- /dev/null
+++ b/openlane/.github/scripts/run_tests.py
@@ -0,0 +1,106 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import sys
+import yaml
+import glob
+import shlex
+import getpass
+import subprocess
+from gh import gh
+
+threads_used = int(subprocess.check_output(["nproc"]).decode("utf-8")) - 1
+test_name = "ci_test"
+design = sys.argv[1]
+print(f"Running on designs {test_name} using {threads_used} threads…")
+
+username = getpass.getuser()
+user = subprocess.check_output(["id", "-u", username]).decode("utf8")[:-1]
+group = subprocess.check_output(["id", "-g", username]).decode("utf8")[:-1]
+
+docker_command = [
+ "docker",
+ "run",
+ "-v",
+ f"{os.path.realpath(gh.root)}:/openlane",
+ "-v",
+ f"{os.path.realpath(gh.root)}/designs:/openlane/install",
+ "-v",
+ f"{gh.pdk}:{gh.pdk}",
+ "-u",
+ f"{user}:{group}",
+ "-e",
+ f"PDK_ROOT={gh.pdk}",
+ gh.image,
+ "bash",
+ "-c",
+ shlex.join(
+ [
+ "python3",
+ "run_designs.py",
+ "--disable_timestamp",
+ "--tag",
+ test_name,
+ "--threads",
+ str(threads_used),
+ "--benchmark",
+ os.path.join("regression_results", "benchmark_results", "SW_HD.csv"),
+ "--show_output",
+ design,
+ ]
+ ),
+]
+
+print(f"Running {shlex.join(docker_command)} in {os.getenv('PWD')}…")
+
+try:
+ subprocess.run(docker_command, check=True)
+except subprocess.CalledProcessError as e:
+ if e.returncode != 2:
+ raise e
+
+
+def cat(x):
+ print(open(x).read())
+
+
+results_folder = os.path.join(gh.root, "regression_results", test_name)
+
+print("Verbose differences within the benchmark:")
+for report in glob.glob(os.path.join(results_folder, f"{test_name}*.rpt")):
+ cat(report)
+
+design_test_report = os.path.join(results_folder, f"{test_name}.rpt.yml")
+if not os.path.exists(design_test_report):
+ print(f"Couldn't find final design test report at {design_test_report}.")
+ exit(-1)
+
+cat(design_test_report)
+
+dtr_str = open(design_test_report).read()
+dtr = yaml.safe_load(dtr_str)
+
+print("Tarballing run...")
+subprocess.check_call(
+ ["tar", "-czf", "./reproducible.tar.gz", os.path.join("designs", design, "runs")]
+)
+print("Created ./reproducible.tar.gz.")
+
+if not dtr[design]["pass"]:
+ print("Testing the design has failed.")
+ exit(-1)
+
+print("Done.")
diff --git a/openlane/.github/scripts/update_tools.py b/openlane/.github/scripts/update_tools.py
new file mode 100644
index 0000000..7898895
--- /dev/null
+++ b/openlane/.github/scripts/update_tools.py
@@ -0,0 +1,70 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import sys
+import yaml
+import argparse
+from gh import gh
+
+dependencies_path = os.path.join(gh.root, "dependencies")
+metadata_path = os.path.join(dependencies_path, "tool_metadata.yml")
+
+sys.path.append(dependencies_path)
+
+from tool import Tool # noqa E402
+
+parser = argparse.ArgumentParser()
+parser.add_argument("tools", nargs="+")
+args = parser.parse_args()
+
+tools = Tool.from_metadata_yaml(open(metadata_path).read())
+
+# Handle Multiline Strings Properly / https://stackoverflow.com/a/33300001
+def represent_str(dumper: yaml.Dumper, data: str):
+ if "\n" in data:
+ return dumper.represent_scalar("tag:yaml.org,2002:str", data, style="|")
+ return dumper.represent_scalar("tag:yaml.org,2002:str", data)
+
+
+yaml.add_representer(str, represent_str)
+dump_options = {"sort_keys": False}
+
+changes = False
+for tool_name in args.tools:
+ tool = tools[tool_name]
+
+ repo = gh.Repo(tool_name, tool.repo)
+ repo.commit = tool.commit
+
+ print("Found %s@%s (latest: %s)." % (repo.url, repo.commit, repo.latest_commit))
+
+ if repo.commit != repo.latest_commit:
+ changes = True
+ metadata_str = open(metadata_path).read()
+ metadata = yaml.safe_load(metadata_str)
+ for tool in metadata:
+ if tool["name"] == tool_name:
+ tool["commit"] = repo.latest_commit
+ metadata_str = yaml.dump(metadata, **dump_options)
+ with open(metadata_path, "w") as f:
+ f.write(metadata_str)
+
+ if len(args.tools) == 1:
+ gh.export_env("TOOL_COMMIT_HASH", repo.latest_commit)
+ else:
+ gh.export_env(f"{tool_name.upper()}_COMMIT_HASH", repo.latest_commit)
+
+gh.export_env("NO_UPDATE", "0" if changes else "1")
diff --git a/openlane/.github/test_sets/extended_test_set b/openlane/.github/test_sets/extended_test_set
new file mode 100644
index 0000000..90bb975
--- /dev/null
+++ b/openlane/.github/test_sets/extended_test_set
@@ -0,0 +1 @@
+BM64 salsa20 aes_core blabla picorv32a PPU y_huff aes
\ No newline at end of file
diff --git a/openlane/.github/test_sets/fastest_test_set b/openlane/.github/test_sets/fastest_test_set
new file mode 100644
index 0000000..9d4ceaf
--- /dev/null
+++ b/openlane/.github/test_sets/fastest_test_set
@@ -0,0 +1 @@
+inverter wbqspiflash APU s44 zipdiv xtea usb usb_cdc_core manual_macro_placement_test spm gcd caravel_upw
\ No newline at end of file
diff --git a/openlane/.github/test_sets/get_test_matrix.py b/openlane/.github/test_sets/get_test_matrix.py
new file mode 100755
index 0000000..35c04b5
--- /dev/null
+++ b/openlane/.github/test_sets/get_test_matrix.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import re
+import sys
+import json
+
+args = sys.argv[1:]
+
+if len(args) < 1:
+ print(
+ f"Usage: {__file__} [test set 0 name [test set 1 name [...]]]", file=sys.stderr
+ )
+ exit(os.EX_USAGE)
+
+directory = os.path.dirname(os.path.realpath(__file__))
+
+files = [os.path.join(directory, x) for x in args]
+
+designs = []
+
+for file in files:
+ designs_temp = re.split(r"\s+", open(file).read().strip())
+ for design in designs_temp:
+ if design.startswith("#") or design == "":
+ continue
+ designs.append(design)
+
+print(json.dumps({"design": designs}))
diff --git a/openlane/.github/workflow-documentation.md b/openlane/.github/workflow-documentation.md
new file mode 100644
index 0000000..bb67756
--- /dev/null
+++ b/openlane/.github/workflow-documentation.md
@@ -0,0 +1,32 @@
+# Openlane CI/CD
+There are two primary flows: the pull request flow and the deployment flow.
+
+The deployment flow occurs on a daily basis. The PR flow happens whenever someone creates a new Pull Request. PRs can be created by contributors or by an automated tool updater that runs on a schedule.
+
+
+* A maintainer cannot review their own code, but they can merge it after a review by another maintainer.
+
+# Required Secrets
+Repository secrets are used to protect certain credentials, but also as repository-dependent parameters for the CI.
+
+## Common
+| Secret | Description |
+|---------------|---------------------------------------------------------------|
+| `MAIN_BRANCH` | The main branch for OpenLane. Format: `main`|`master`|`etc` |
+
+## CI
+
+| Secret | Description |
+|---------------|---------------------------------------------------------------|
+| `DOCKER_IMAGE` | The name of the resulting Docker image (minus the tag). In our case, we use `efabless/openlane`. |
+| `TOOL_DOCKER_IMAGE` | The name of the resulting Docker images for tools (minus the tag). In our case, we use `efabless/openlane-tools`. |
+| `DOCKERHUB_USER` | A username for a user that has push access to the organization that owns `DOCKER_IMAGE` on Docker Hub. In our case, that's an Efabless Employee with push access. |
+| `DOCKERHUB_PASSWORD` | The password/token for the given username that has push access to the organization that owns `DOCKER_IMAGE` on Docker Hub.|
+| `LOG_UPLOAD_INFO` | **Currently unused**: Information on a cloud platform to upload buckets to, in the format `platform:bucket:encoded_credentials`, where `platform` can be `gcp`/`aws`/etc, `bucket` is the bucket name, and `encoded_credentials` are simply the relevant credentials encoded in base64. It's a bit convoluted, but it makes it so different CI users can switch the platform out by changing a single secret. Currently, only the Google Cloud Platform is supported. Support for other platforms can be added to `upload_log_tarballs.py`. If this secret is not specified, the logs will not be uploaded. |
+
+## Tool Updater
+
+| Secret | Description |
+|---------------|---------------------------------------------------------------|
+| `FORK_NAME` | A fork to push branches for tool updates to. Format `bot-account/OpenLane` |
+| `MY_TOKEN` | A token for the bot account that owns the fork. |
\ No newline at end of file
diff --git a/openlane/.github/workflows/lint.yml b/openlane/.github/workflows/lint.yml
new file mode 100644
index 0000000..8ebc618
--- /dev/null
+++ b/openlane/.github/workflows/lint.yml
@@ -0,0 +1,23 @@
+name: Lint
+on:
+ # Runs on pushes to all but CID-latest-branches
+ # CID-latest branches automatically create PRs, let's just let the tests run on those
+ push:
+ # Runs on Pull Requests
+ pull_request:
+ # Runs manually
+ workflow_dispatch:
+
+jobs:
+ lint_python:
+ name: Lint Python Code
+ runs-on: ubuntu-20.04
+ steps:
+ - name: Check out Git repository
+ uses: actions/checkout@v2
+ - name: Install Linters
+ run: python3 -m pip install -r ./requirements_lint.txt
+ - name: Ensure Black Formatting
+ run: black --check .
+ - name: Lint with Flake8
+ run: flake8 .
diff --git a/openlane/.github/workflows/openlane_ci.yml b/openlane/.github/workflows/openlane_ci.yml
new file mode 100644
index 0000000..c135379
--- /dev/null
+++ b/openlane/.github/workflows/openlane_ci.yml
@@ -0,0 +1,327 @@
+name: CI
+
+# To run on the GCP replace all 'ubuntu-latest' with 'self-hosted'
+on:
+ # Runs on pushes to all but CID-latest-branches
+ # CID-latest branches automatically create PRs, let's just let the tests run on those
+ push:
+ # Runs on Pull Requests
+ pull_request:
+ # Runs every day at midnight UTC
+ schedule:
+ - cron: "0 0 * * *"
+ # Manual Dispatch
+ workflow_dispatch:
+
+jobs:
+ docker_build:
+ runs-on: ubuntu-20.04
+ outputs:
+ matrix: ${{ steps.set-matrix.outputs.matrix }}
+ issue_regression_matrix: ${{ steps.set-matrix.outputs.issue_regression_matrix }}
+ steps:
+ - uses: actions/checkout@v2
+
+ # EXPORT BLOCK
+ - name: Export Repo URL
+ run: echo "REPO_URL=https://github.com/${{ github.repository }}.git" >> $GITHUB_ENV
+
+ - name: Export PDK ROOT
+ run: echo "PDK_ROOT=/usr/local/pdk" >> $GITHUB_ENV
+
+ - name: Export Branch Name
+ run: echo "BRANCH_NAME=${GITHUB_REF##*/}" >> $GITHUB_ENV
+
+ - name: Export Temp Image Name
+ run: echo "OPENLANE_IMAGE_NAME=openlane:intermediate" >> $GITHUB_ENV
+ # END EXPORT BLOCK
+
+ - name: Check If Going To Push An Image To Docker
+ # # Uncomment the next line if you want to only build & push a container if entire test set succeeds
+ # if: needs.test.result == 'success'
+ # Ruby snippet to print 0 if this is a PR or if there is no DOCKERHUB_USER secret set, otherwise, 1
+ run: |
+ export PUSHING=$(ruby -e 'if ("${{ github.event_name }}" != "pull_request" && "${{ secrets.DOCKERHUB_USER }}" != ""); print(1) else print(0) end')
+ echo "PUSHING=$PUSHING" >> $GITHUB_ENV
+
+ - name: Login to DockerHub
+ if: ${{ env.PUSHING == '1' }}
+ uses: docker/login-action@v1
+ with:
+ username: ${{ secrets.DOCKERHUB_USER }}
+ password: ${{ secrets.DOCKERHUB_PASSWORD }}
+
+ - name: Docker Build
+ run: |
+ export BUILD_IF_CANT_PULL=1
+ if [ $PUSHING = '1' ]; then
+ export BUILD_IF_CANT_PULL_THEN_PUSH=1
+ fi
+ cd docker/ && make merge
+
+ - name: Build (or Get) PDK
+ run: |
+ sudo mkdir -p ${{ env.PDK_ROOT }}
+ sudo chown -R $USER:$USER ${{ env.PDK_ROOT }}
+ go get -u github.com/tcnksm/ghr
+ export PATH=$PATH:$(go env GOPATH)/bin
+ python3 -m pip install --upgrade --no-cache-dir volare
+ export OPDKS_VER="$(python3 ./dependencies/tool.py open_pdks -f commit)"
+ if [ "${{ secrets.VOLARE_REPO }}" != "" ]; then
+ volare enable_or_build\
+ --also-push\
+ --token ${{ secrets.MY_TOKEN }}\
+ --owner ${{ secrets.VOLARE_OWNER }}\
+ --repository ${{ secrets.VOLARE_REPO }}\
+ -j$(nproc)\
+ $OPDKS_VER
+ else
+ volare enable_or_build\
+ --token ${{ secrets.MY_TOKEN }}\
+ -j$(nproc)\
+ $OPDKS_VER
+ fi
+
+ - name: Export Docker Image
+ run: docker save -o /tmp/image.tar ${{ env.OPENLANE_IMAGE_NAME }}
+
+ - name: Upload Docker Image
+ uses: actions/upload-artifact@v2
+ with:
+ name: docker-image
+ path: /tmp/image.tar
+
+ - name: Tarball PDK
+ run: |
+ tar -cf /tmp/sky130A.tar -C $PDK_ROOT/sky130A .
+
+ - name: Upload PDK Tarball
+ uses: actions/upload-artifact@v2
+ with:
+ name: pdk-tarball
+ path: /tmp/sky130A.tar
+
+ - name: Determine If Running Extended Test Set
+ run: |
+ export EVENT_NAME=${{ github.event_name }};
+ python3 ./.github/scripts/determine_test_set.py
+
+ - name: Prepare Test Matrix
+ id: set-matrix
+ run: |
+ if [[ "$USE_ETS" = "1" ]]; then
+ echo "::set-output name=matrix::$(python3 ./.github/test_sets/get_test_matrix.py fastest_test_set extended_test_set)"
+ else
+ echo "::set-output name=matrix::$(python3 ./.github/test_sets/get_test_matrix.py fastest_test_set)"
+ fi
+ echo "::set-output name=issue_regression_matrix::$(python3 ./run_issue_regressions.py get_matrix)"
+
+ issue_regression_test:
+ needs: docker_build
+ runs-on: ubuntu-20.04
+ strategy:
+ fail-fast: false
+ matrix: ${{ fromJSON(needs.docker_build.outputs.issue_regression_matrix) }}
+ name: Test Issue Regression ${{ matrix.design }}
+ steps:
+ - uses: actions/checkout@v2
+ # EXPORT BLOCK
+ - name: Export Repo URL
+ run: echo "REPO_URL=https://github.com/${{ github.repository }}.git" >> $GITHUB_ENV
+
+ - name: Export PDK ROOT
+ run: echo "PDK_ROOT=/usr/local/pdk" >> $GITHUB_ENV
+
+ - name: Export Branch Name
+ run: echo "BRANCH_NAME=${GITHUB_REF##*/}" >> $GITHUB_ENV
+
+ - name: Export Temp Image Name
+ run: echo "OPENLANE_IMAGE_NAME=openlane:intermediate" >> $GITHUB_ENV
+ # END EXPORT BLOCK
+
+ - name: Download Docker Image
+ uses: actions/download-artifact@v2
+ with:
+ name: docker-image
+ path: /tmp
+
+ - name: Import Docker Image
+ run: docker load --input /tmp/image.tar
+
+ - name: Download PDK Tarball
+ uses: actions/download-artifact@v2
+ with:
+ name: pdk-tarball
+ path: /tmp
+
+ - name: Unpack PDK Tarball
+ run: |
+ sudo mkdir -p ${{ env.PDK_ROOT }}/sky130A
+ sudo chown -R $USER:$USER ${{ env.PDK_ROOT }}
+ tar -xf /tmp/sky130A.tar -C $PDK_ROOT/sky130A .
+
+ - name: Get Pyyaml
+ run: python3 -m pip install pyyaml
+
+ - name: Run Issue Regression Test
+ run: cd ${GITHUB_WORKSPACE}/ && make run_issue_regression ISSUE_REGRESSION_DESIGN=${{ matrix.design }}
+ # Each test has two components: a fast test set and an extended test set.
+ # The fast test set is run on all PRs, etc. The extended test set runs on schedule.
+ test:
+ needs: docker_build
+ runs-on: ubuntu-20.04
+ strategy:
+ fail-fast: false
+ matrix: ${{ fromJSON(needs.docker_build.outputs.matrix) }}
+ name: Test Design ${{ matrix.design }}
+ steps:
+ - uses: actions/checkout@v2
+
+ # EXPORT BLOCK
+ - name: Export Repo URL
+ run: echo "REPO_URL=https://github.com/${{ github.repository }}.git" >> $GITHUB_ENV
+
+ - name: Export PDK ROOT
+ run: echo "PDK_ROOT=/usr/local/pdk" >> $GITHUB_ENV
+
+ - name: Export Branch Name
+ run: echo "BRANCH_NAME=${GITHUB_REF##*/}" >> $GITHUB_ENV
+
+ - name: Export Temp Image Name
+ run: echo "OPENLANE_IMAGE_NAME=openlane:intermediate" >> $GITHUB_ENV
+ # END EXPORT BLOCK
+
+ - name: Download Docker Image
+ uses: actions/download-artifact@v2
+ with:
+ name: docker-image
+ path: /tmp
+
+ - name: Import Docker Image
+ run: docker load --input /tmp/image.tar
+
+ - name: Download PDK Tarball
+ uses: actions/download-artifact@v2
+ with:
+ name: pdk-tarball
+ path: /tmp
+
+ - name: Unpack PDK Tarball
+ run: |
+ sudo mkdir -p ${{ env.PDK_ROOT }}/sky130A
+ sudo chown -R $USER:$USER ${{ env.PDK_ROOT }}
+ tar -xf /tmp/sky130A.tar -C $PDK_ROOT/sky130A .
+
+ - name: Get Pyyaml
+ run: python3 -m pip install pyyaml
+
+ - name: Run Test
+ run: cd ${GITHUB_WORKSPACE}/ && python3 ${GITHUB_WORKSPACE}/.github/scripts/run_tests.py ${{ matrix.design }}
+
+ - name: Upload Run Tarball
+ if: ${{ always() }}
+ uses: actions/upload-artifact@v2
+ with:
+ name: ${{ matrix.design }}
+ path: ./reproducible.tar.gz
+
+ cleanup_and_deploy:
+ name: Cleanup (and Possibly Deployment)
+ needs: [test, issue_regression_test]
+ if: always()
+ runs-on: ubuntu-20.04
+ steps:
+ - name: Check If Going To Push An Image To Docker
+ # # Uncomment the next line if you want to only build & push a container if entire test set succeeds
+ # if: needs.test.result == 'success'
+ # Ruby snippet to print 0 if this is a PR or if there is no DOCKERHUB_USER secret set, otherwise, 1
+ run: |
+ export PUSHING=$(ruby -e 'if ("${{ github.event_name }}" != "pull_request" && "${{ secrets.DOCKERHUB_USER }}" != ""); print(1) else print(0) end')
+ echo "PUSHING=$PUSHING" >> $GITHUB_ENV
+
+ - uses: actions/checkout@v2
+ if: ${{ env.PUSHING == '1' }}
+ with:
+ fetch-depth: 0
+
+ # EXPORT BLOCK
+ - name: Export Repo URL
+ run: echo "REPO_URL=https://github.com/${{ github.repository }}.git" >> $GITHUB_ENV
+
+ - name: Export PDK ROOT
+ run: echo "PDK_ROOT=/usr/local/pdk" >> $GITHUB_ENV
+
+ - name: Export Branch Name
+ run: echo "BRANCH_NAME=${GITHUB_REF##*/}" >> $GITHUB_ENV
+
+ - name: Export Temp Image Name
+ run: echo "OPENLANE_IMAGE_NAME=openlane:intermediate" >> $GITHUB_ENV
+ # END EXPORT BLOCK
+
+ - name: Download Docker Image
+ if: ${{ env.PUSHING == '1' }}
+ uses: actions/download-artifact@v2
+ with:
+ name: docker-image
+ path: /tmp
+
+ - name: Delete Docker Image
+ uses: geekyeggo/delete-artifact@v1
+ with:
+ name: docker-image
+
+ - name: Delete PDK
+ uses: geekyeggo/delete-artifact@v1
+ with:
+ name: pdk-tarball
+
+ - name: Import Docker Image
+ if: ${{ env.PUSHING == '1' }}
+ run: docker load --input /tmp/image.tar
+
+ - name: Write Main Branch
+ if: ${{ env.PUSHING == '1' }}
+ run: |
+ echo "MAIN_BRANCH=${{ secrets.MAIN_BRANCH }}" >> $GITHUB_ENV
+
+ - name: Write Hash
+ run: |
+ echo "GIT_COMMIT_HASH=$(git rev-parse HEAD)" >> $GITHUB_ENV
+
+ - name: Create Tag (If scheduled or dispatched)
+ if: ${{ env.PUSHING == '1' && (github.event_name == 'schedule' || github.event_name == 'workflow_dispatch') && env.BRANCH_NAME == env.MAIN_BRANCH }}
+ run: cd ${GITHUB_WORKSPACE}/ && python3 ${GITHUB_WORKSPACE}/.github/scripts/generate_tag.py
+
+ - name: Tag Commit (If scheduled or dispatched)
+ if: ${{ env.PUSHING == '1' && (github.event_name == 'schedule' || github.event_name == 'workflow_dispatch') && env.NEW_TAG != 'NO_NEW_TAG' }}
+ uses: tvdias/github-tagger@v0.0.1
+ with:
+ tag: "${{ env.NEW_TAG }}"
+ repo-token: "${{ secrets.MY_TOKEN }}"
+
+ - name: Login to DockerHub
+ if: ${{ env.PUSHING == '1' }}
+ uses: docker/login-action@v1
+ with:
+ username: ${{ secrets.DOCKERHUB_USER }}
+ password: ${{ secrets.DOCKERHUB_PASSWORD }}
+
+ - name: Docker Push (Hash)
+ if: ${{ env.PUSHING == '1' && github.event_name == 'push' && env.BRANCH_NAME == env.MAIN_BRANCH }}
+ run: |
+ docker image tag ${{ env.OPENLANE_IMAGE_NAME }} ${{ secrets.DOCKER_IMAGE }}:${{ env.GIT_COMMIT_HASH }}
+ docker push ${{ secrets.DOCKER_IMAGE }}:${{ env.GIT_COMMIT_HASH }}
+
+ - name: Docker Push (Branch)
+ if: ${{ env.PUSHING == '1' && github.event_name == 'push' }}
+ run: |
+ docker image tag ${{ env.OPENLANE_IMAGE_NAME }} ${{ secrets.DOCKER_IMAGE }}:${{ env.BRANCH_NAME }}
+ docker push ${{ secrets.DOCKER_IMAGE }}:${{ env.BRANCH_NAME }}
+
+ - name: Docker Push (Tag) (If scheduled or dispatched)
+ if: ${{ env.PUSHING == '1' && (github.event_name == 'schedule' || github.event_name == 'workflow_dispatch') && env.NEW_TAG != 'NO_NEW_TAG' }}
+ run: |
+ docker image tag ${{ env.OPENLANE_IMAGE_NAME }} ${{ secrets.DOCKER_IMAGE }}:${{ env.NEW_TAG }}
+ docker image tag ${{ env.OPENLANE_IMAGE_NAME }} ${{ secrets.DOCKER_IMAGE }}:latest
+ docker push ${{ secrets.DOCKER_IMAGE }}:${{ env.NEW_TAG }}
+ docker push ${{ secrets.DOCKER_IMAGE }}:latest
diff --git a/openlane/.github/workflows/tool_updater.yml b/openlane/.github/workflows/tool_updater.yml
new file mode 100644
index 0000000..629c281
--- /dev/null
+++ b/openlane/.github/workflows/tool_updater.yml
@@ -0,0 +1,95 @@
+name: Tool Updater
+
+# To run on the GCP replace all 'ubuntu-latest' with 'self-hosted'
+on:
+ # Runs every day at midnight UTC
+ schedule:
+ - cron: "0 0 * * *"
+ # Manual Dispatch
+ workflow_dispatch:
+
+jobs:
+ create-cid-tools-branches:
+ runs-on: ubuntu-20.04
+ strategy:
+ matrix:
+ tools: [magic, netgen, yosys, openroad_app]
+ steps:
+ # EXPORT BLOCK
+ - name: Export Repo URL
+ run: echo "REPO_URL=https://github.com/${{ github.repository }}" >> $GITHUB_ENV
+
+ - name: Export Branch Name
+ run: echo "BRANCH_NAME=${{ secrets.MAIN_BRANCH }}" >> $GITHUB_ENV
+
+ - name: Export PDK ROOT
+ run: echo "PDK_ROOT=${{ github.workspace }}/pdks" >> $GITHUB_ENV
+ # END EXPORT BLOCK
+
+ - uses: actions/checkout@v2
+ with:
+ ref: ${{ secrets.MAIN_BRANCH }}
+
+ - name: Export TOOL Name
+ run: echo "TOOL=${{ matrix.tools }}" >> $GITHUB_ENV
+
+ - name: Update TOOL
+ run: cd ${GITHUB_WORKSPACE}/ && python3 ${GITHUB_WORKSPACE}/.github/scripts/update_tools.py ${{ env.TOOL }}
+
+ - name: Create Pull Request
+ if: ${{ env.NO_UPDATE != '1' }}
+ uses: peter-evans/create-pull-request@v3
+ with:
+ token: ${{ secrets.MY_TOKEN }}
+ title: "[BOT] Update ${{ env.TOOL }}"
+ body: |
+ This is an automated PR.
+
+ See the individual commits for details.
+ commit-message: |
+ [BOT] Update ${{ env.TOOL }}
+
+ ${{ env.TOOL }} -> ${{ env.TOOL_COMMIT_HASH }}
+ branch: ${{ matrix.tools }}-update-branch
+ push-to-fork: ${{ secrets.FORK_NAME }}
+ delete-branch: true
+ create-cid-pdk-branch:
+ runs-on: ubuntu-20.04
+ steps:
+ # EXPORT BLOCK
+ - name: Export Repo URL
+ run: echo "REPO_URL=https://github.com/${{ github.repository }}" >> $GITHUB_ENV
+
+ - name: Export Branch Name
+ run: echo "BRANCH_NAME=${{ secrets.MAIN_BRANCH }}" >> $GITHUB_ENV
+
+ - name: Export PDK ROOT
+ run: echo "PDK_ROOT=${{ github.workspace }}/pdks" >> $GITHUB_ENV
+ # END EXPORT BLOCK
+
+ - uses: actions/checkout@v2
+ with:
+ ref: ${{ secrets.MAIN_BRANCH }}
+
+ - name: Update PDK
+ run: python3 ${GITHUB_WORKSPACE}/.github/scripts/update_tools.py sky130 open_pdks
+
+ - name: Create Pull Request
+ if: ${{ env.NO_UPDATE != '1' }}
+ uses: peter-evans/create-pull-request@v3
+ with:
+ token: ${{ secrets.MY_TOKEN }}
+ title: "[BOT] Update PDK"
+ body: |
+ This is an automated PR.
+
+ See the individual commits for details.
+ commit-message: |
+ [BOT] Update PDK
+
+ sky130 -> ${{ env.SKY130_COMMIT_HASH }}
+ open_pdks -> ${{ env.OPEN_PDKS_COMMIT_HASH }}
+ base: ${{ env.BRANCH_NAME }}
+ branch: pdk-update-branch
+ push-to-fork: ${{ secrets.FORK_NAME }}
+ delete-branch: true
diff --git a/openlane/.gitignore b/openlane/.gitignore
index e4867d8..af6c640 100644
--- a/openlane/.gitignore
+++ b/openlane/.gitignore
@@ -1,2 +1,47 @@
-*/runs
+# vim swaps
+**/*.swp
+tags
+.vim
+
+# emacs backup files
+*~
+
+# Flow Artifacts
+dummy.guide
+lefRWarning.log
+run.param
+macrocell.list
default.cvcrc
+*.log
+*.tar.gz
+
+# Python cache
+**/__pycache__
+/*.lef
+/*.def
+
+# Mac
+.DS_Store
+
+# VScode
+**/.vscode/
+
+# Local docs Build
+**/_build/
+
+# Regression artifacts
+*.config
+
+# PDK
+pdks/
+
+# Misc
+/resolved_version
+
+/docker_build/
+
+# Local Install
+/install
+
+# Venv
+/venv
\ No newline at end of file
diff --git a/openlane/.readthedocs.yml b/openlane/.readthedocs.yml
new file mode 100644
index 0000000..c2976e9
--- /dev/null
+++ b/openlane/.readthedocs.yml
@@ -0,0 +1,13 @@
+# .readthedocs.yml
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+# Build documentation in the docs/ directory with Sphinx
+sphinx:
+ configuration: conf.py
+
+conda:
+ environment: docs/environment.yml
diff --git a/openlane/AUTHORS.md b/openlane/AUTHORS.md
new file mode 100644
index 0000000..1ad9250
--- /dev/null
+++ b/openlane/AUTHORS.md
@@ -0,0 +1,36 @@
+Efabless Corporation is the principal author of this software for the purpose
+of copyright. All binaries provided are also distributed by Efabless Corporation.
+
+https://efabless.com
+
+# OpenLane Project Founders
+
+- Tim Edwards <tim@efabless.com>
+- Kareem Farid <kareem.farid@efabless.com>
+- Ahmed Ghazy <ahmed.ghazy@efabless.com>
+- Amr Gouhar <aagouhar@efabless.com>
+- Mohamed Shalan, PhD. <mshalan@efabless.com>
+
+# OpenLane Core Team
+
+- Manar Abdelatty <manarabdelaty@efabless.com>
+- Tim Edwards <tim@efabless.com>
+- Kareem Farid <kareem.farid@efabless.com>
+- Mohamed Gaber <mohamed.gaber@efabless.com>
+- Mohamed Shalan, PhD. <mshalan@efabless.com>
+
+# All Contributors
+https://github.com/The-OpenROAD-Project/OpenLane/graphs/contributors
+
+# Special Thanks
+
+- Tim Ansell <tansell@google.com>
+- Risto Bell <rb@efabless.com>
+- Andrew Kahng <abk@eng.ucsd.edu>
+- Mohamed Kassem <mkk@efabless.com>
+- Tom Spyrou <aspyrou@eng.ucsd.edu>
+
+It must be said that this effort is built on a foundation from various indirect
+contributions by countless open source software and hardware leaders.
+
+We are grateful and proud to be a part of this larger group.
\ No newline at end of file
diff --git a/openlane/CONTRIBUTING.md b/openlane/CONTRIBUTING.md
new file mode 100644
index 0000000..551d832
--- /dev/null
+++ b/openlane/CONTRIBUTING.md
@@ -0,0 +1,31 @@
+# How to Contribute
+We'd love to accept your patches and contributions to this project. There are
+just a few small guidelines you need to follow.
+
+# Branching
+For various reasons, it's recommended to call working branches, even in your forks, something else other than `master` or `main`, as those two branch names do have some special behavior associated with them.
+
+# Testing and Code Standards
+Before you submit your changes, it's prudent to perform some kind of smoke test. `make test` tests a simple spm design to ensure nothing has gone horribly wrong.
+
+You will also need to ensure that your Python code passes linting with two tools: `black` and `flake8`. The commands are simply `black .` and `flake8 .`. Please fix all warnings.
+
+Try to write all major code in Python. Writing some Tcl is usually a necessity because this project's backbone is unfortunately written in Tcl, but just keep the Tcl to as close to a Python shim as possible.
+
+Please do not write new shell scripts.
+
+# Submissions
+Make your changes and then submit them as a pull requests to the `master` branch.
+
+Consult [GitHub Help](https://help.github.com/articles/about-pull-requests/) for more information on using pull requests.
+
+## The Approval Process
+For a PR to be merged, there are two requirements:
+
+- There are two automated checks, one for linting and the other for functionality. Both must pass.
+- An OpenLane team member must inspect and approve the PR.
+
+# Licensing and Copyright
+Please add you (or your employer's) copyright headers to any files to which you have made major edits.
+
+Please note all code contributions must have the same license as OpenLane, i.e., the Apache License, version 2.0.
\ No newline at end of file
diff --git a/openlane/Jenkinsfile b/openlane/Jenkinsfile
new file mode 100644
index 0000000..b9062ea
--- /dev/null
+++ b/openlane/Jenkinsfile
@@ -0,0 +1,112 @@
+// This file is used for internal testing by the OpenROAD team.
+def NEW_SHA = "NONE"
+def OLD_SHA = "NONE"
+pipeline {
+ agent any;
+ options {
+ timeout(time: 8, unit: 'HOURS');
+ }
+ environment {
+ ROUTING_CORES = 32;
+ }
+ stages {
+
+ // not used, checkout just to keep track of changes
+ stage("Update OpenROAD to HEAD of master branch") {
+ steps {
+ checkout([$class: "GitSCM",
+ branches: [[name: "*/master"]],
+ userRemoteConfigs: [[url: "https://github.com/The-OpenROAD-Project/OpenROAD"]],
+ extensions: [[$class: 'RelativeTargetDirectory', relativeTargetDir: 'openroad']]
+ ]);
+ }
+ }
+
+ stage('Build OpenROAD Docker image with master branch') {
+ steps {
+ sh 'PDK_ROOT=$(pwd)/pdks OPENLANE_IMAGE_NAME=efabless/openlane python3 .github/scripts/update_tools.py openroad_app';
+ sh 'make -C docker build-openroad_app';
+ script { NEW_SHA = sh (returnStdout: true, script: "python3 dependencies/tool.py -f commit openroad_app").trim(); }
+ }
+ }
+
+ stage('Build Docker OpenLane image with openroad_app master') {
+ steps {
+ sh 'make -C docker openlane';
+ sh 'docker save efabless/openlane:current | gzip > openlane-current.tar.gz';
+ stash name: 'data', includes: 'openlane-current.tar.gz';
+ }
+ }
+
+ stage('Run Tests') {
+ matrix {
+ axes {
+ axis {
+ name 'DESIGN';
+ values "aes",
+ "aes_core",
+ "APU",
+ "blabla",
+ "BM64",
+ "gcd",
+ "inverter",
+ "manual_macro_placement_test",
+ "picorv32a",
+ "PPU",
+ "s44",
+ "salsa20",
+ "spm",
+ "usb",
+ "usb_cdc_core",
+ "wbqspiflash",
+ "xtea",
+ "y_huff",
+ "zipdiv";
+ }
+ }
+ stages {
+ stage('Test') {
+ agent any;
+ steps {
+ script {
+ stage("${DESIGN} - Install PDK") {
+ sh 'python3 -m pip install --user --upgrade --no-cache-dir pip';
+ sh 'python3 -m pip install --user --upgrade --no-cache-dir volare';
+ sh 'PDK_ROOT=$(pwd)/pdks ~/.local/bin/volare enable_or_build -t NULL -j$(nproc) $(python3 ./dependencies/tool.py open_pdks -f commit)';
+ }
+ stage("${DESIGN} - Import Docker image") {
+ unstash "data";
+ sh 'docker load --input openlane-current.tar.gz';
+ }
+ stage("${DESIGN} - Update OpenROAD commit") {
+ script { OLD_SHA = sh (returnStdout: true, script: "python3 dependencies/tool.py -f commit openroad_app").trim(); }
+ sh "sed -i s/${OLD_SHA}/${NEW_SHA}/ ./dependencies/tool_metadata.yml"
+ }
+ stage("${DESIGN} - Run test") {
+ sh "make OPENLANE_DOCKER_TAG=current TEST_DESIGN=${DESIGN} test";
+ }
+ }
+ }
+ post {
+ failure {
+ archiveArtifacts artifacts: "designs/**/*.log, designs/**/openroad_issue_reproducible/**/*";
+ }
+ }
+ }
+ }
+ }
+ }
+
+ }
+
+ post {
+ failure {
+ emailext(
+ to: '$DEFAULT_RECIPIENTS',
+ subject: '$DEFAULT_SUBJECT',
+ body: '$DEFAULT_CONTENT',
+ );
+ }
+ }
+
+}
diff --git a/openlane/LICENSE b/openlane/LICENSE
new file mode 100644
index 0000000..a452d9b
--- /dev/null
+++ b/openlane/LICENSE
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+ 1. Definitions.
+
+ "License" shall mean the terms and conditions for use, reproduction,
+ and distribution as defined by Sections 1 through 9 of this document.
+
+ "Licensor" shall mean the copyright owner or entity authorized by
+ the copyright owner that is granting the License.
+
+ "Legal Entity" shall mean the union of the acting entity and all
+ other entities that control, are controlled by, or are under common
+ control with that entity. For the purposes of this definition,
+ "control" means (i) the power, direct or indirect, to cause the
+ direction or management of such entity, whether by contract or
+ otherwise, or (ii) ownership of fifty percent (50%) or more of the
+ outstanding shares, or (iii) beneficial ownership of such entity.
+
+ "You" (or "Your") shall mean an individual or Legal Entity
+ exercising permissions granted by this License.
+
+ "Source" form shall mean the preferred form for making modifications,
+ including but not limited to software source code, documentation
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+
+ "Object" form shall mean any form resulting from mechanical
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+ not limited to compiled object code, generated documentation,
+ and conversions to other media types.
+
+ "Work" shall mean the work of authorship, whether in Source or
+ Object form, made available under the License, as indicated by a
+ copyright notice that is included in or attached to the work
+ (an example is provided in the Appendix below).
+
+ "Derivative Works" shall mean any work, whether in Source or Object
+ form, that is based on (or derived from) the Work and for which the
+ editorial revisions, annotations, elaborations, or other modifications
+ represent, as a whole, an original work of authorship. For the purposes
+ of this License, Derivative Works shall not include works that remain
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+ the Work and Derivative Works thereof.
+
+ "Contribution" shall mean any work of authorship, including
+ the original version of the Work and any modifications or additions
+ to that Work or Derivative Works thereof, that is intentionally
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+ communication on electronic mailing lists, source code control systems,
+ and issue tracking systems that are managed by, or on behalf of, the
+ Licensor for the purpose of discussing and improving the Work, but
+ excluding communication that is conspicuously marked or otherwise
+ designated in writing by the copyright owner as "Not a Contribution."
+
+ "Contributor" shall mean Licensor and any individual or Legal Entity
+ on behalf of whom a Contribution has been received by Licensor and
+ subsequently incorporated within the Work.
+
+ 2. Grant of Copyright License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+ copyright license to reproduce, prepare Derivative Works of,
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+ Work and such Derivative Works in Source or Object form.
+
+ 3. Grant of Patent License. Subject to the terms and conditions of
+ this License, each Contributor hereby grants to You a perpetual,
+ worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+ (except as stated in this section) patent license to make, have made,
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+ with the Work to which such Contribution(s) was submitted. If You
+ institute patent litigation against any entity (including a
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+ granted to You under this License for that Work shall terminate
+ as of the date such litigation is filed.
+
+ 4. Redistribution. You may reproduce and distribute copies of the
+ Work or Derivative Works thereof in any medium, with or without
+ modifications, and in Source or Object form, provided that You
+ meet the following conditions:
+
+ (a) You must give any other recipients of the Work or
+ Derivative Works a copy of this License; and
+
+ (b) You must cause any modified files to carry prominent notices
+ stating that You changed the files; and
+
+ (c) You must retain, in the Source form of any Derivative Works
+ that You distribute, all copyright, patent, trademark, and
+ attribution notices from the Source form of the Work,
+ excluding those notices that do not pertain to any part of
+ the Derivative Works; and
+
+ (d) If the Work includes a "NOTICE" text file as part of its
+ distribution, then any Derivative Works that You distribute must
+ include a readable copy of the attribution notices contained
+ within such NOTICE file, excluding those notices that do not
+ pertain to any part of the Derivative Works, in at least one
+ of the following places: within a NOTICE text file distributed
+ as part of the Derivative Works; within the Source form or
+ documentation, if provided along with the Derivative Works; or,
+ within a display generated by the Derivative Works, if and
+ wherever such third-party notices normally appear. The contents
+ of the NOTICE file are for informational purposes only and
+ do not modify the License. You may add Your own attribution
+ notices within Derivative Works that You distribute, alongside
+ or as an addendum to the NOTICE text from the Work, provided
+ that such additional attribution notices cannot be construed
+ as modifying the License.
+
+ You may add Your own copyright statement to Your modifications and
+ may provide additional or different license terms and conditions
+ for use, reproduction, or distribution of Your modifications, or
+ for any such Derivative Works as a whole, provided Your use,
+ reproduction, and distribution of the Work otherwise complies with
+ the conditions stated in this License.
+
+ 5. Submission of Contributions. Unless You explicitly state otherwise,
+ any Contribution intentionally submitted for inclusion in the Work
+ by You to the Licensor shall be under the terms and conditions of
+ this License, without any additional terms or conditions.
+ Notwithstanding the above, nothing herein shall supersede or modify
+ the terms of any separate license agreement you may have executed
+ with Licensor regarding such Contributions.
+
+ 6. Trademarks. This License does not grant permission to use the trade
+ names, trademarks, service marks, or product names of the Licensor,
+ except as required for reasonable and customary use in describing the
+ origin of the Work and reproducing the content of the NOTICE file.
+
+ 7. Disclaimer of Warranty. Unless required by applicable law or
+ agreed to in writing, Licensor provides the Work (and each
+ Contributor provides its Contributions) on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied, including, without limitation, any warranties or conditions
+ of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+ PARTICULAR PURPOSE. You are solely responsible for determining the
+ appropriateness of using or redistributing the Work and assume any
+ risks associated with Your exercise of permissions under this License.
+
+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
+ unless required by applicable law (such as deliberate and grossly
+ negligent acts) or agreed to in writing, shall any Contributor be
+ liable to You for damages, including any direct, indirect, special,
+ incidental, or consequential damages of any character arising as a
+ result of this License or out of the use or inability to use the
+ Work (including but not limited to damages for loss of goodwill,
+ work stoppage, computer failure or malfunction, or any and all
+ other commercial damages or losses), even if such Contributor
+ has been advised of the possibility of such damages.
+
+ 9. Accepting Warranty or Additional Liability. While redistributing
+ the Work or Derivative Works thereof, You may choose to offer,
+ and charge a fee for, acceptance of support, warranty, indemnity,
+ or other liability obligations and/or rights consistent with this
+ License. However, in accepting such obligations, You may act only
+ on Your own behalf and on Your sole responsibility, not on behalf
+ of any other Contributor, and only if You agree to indemnify,
+ defend, and hold each Contributor harmless for any liability
+ incurred by, or claims asserted against, such Contributor by reason
+ of your accepting any such warranty or additional liability.
+
+ END OF TERMS AND CONDITIONS
+
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
+ boilerplate notice, with the fields enclosed by brackets "[]"
+ replaced with your own identifying information. (Don't include
+ the brackets!) The text should be enclosed in the appropriate
+ comment syntax for the file format. We also recommend that a
+ file or class name and description of purpose be included on the
+ same "printed page" as the copyright notice for easier
+ identification within third-party archives.
+
+ Copyright 2020 efabless corporation
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
diff --git a/openlane/Makefile b/openlane/Makefile
deleted file mode 120000
index 48e5b4a..0000000
--- a/openlane/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..2e1090a
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,172 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+PYTHON_BIN ?= python3
+
+OPENLANE_DIR ?= $(shell pwd)
+
+DOCKER_OPTIONS = $(shell $(PYTHON_BIN) ./env.py docker-config)
+
+# Allow Configuring Memory Limits
+ifneq (,$(DOCKER_SWAP)) # Set to -1 for unlimited
+DOCKER_OPTIONS += --memory-swap=$(DOCKER_SWAP)
+endif
+ifneq (,$(DOCKER_MEMORY))
+DOCKER_OPTIONS += --memory=$(DOCKER_MEMORY)
+# To verify: cat /sys/fs/cgroup/memory/memory.limit_in_bytes inside the container
+endif
+
+# Allow using GUIs
+UNAME_S = $(shell uname -s)
+ifeq ($(UNAME_S),Linux)
+DOCKER_OPTIONS += -e DISPLAY=$(DISPLAY) -v /tmp/.X11-unix:/tmp/.X11-unix -v $(HOME)/.Xauthority:/.Xauthority --network host
+ ifneq ("$(wildcard $(HOME)/.openroad)","")
+ DOCKER_OPTIONS += -v $(HOME)/.openroad:/.openroad
+ endif
+endif
+
+THREADS ?= 1
+
+ifneq (,$(ROUTING_CORES))
+DOCKER_OPTIONS += -e ROUTING_CORES=$(ROUTING_CORES)
+endif
+
+ifeq ($(OPENLANE_IMAGE_NAME),)
+OPENLANE_DOCKER_TAG ?= $(shell $(PYTHON_BIN) ./dependencies/get_tag.py)
+ifneq ($(OPENLANE_DOCKER_TAG),)
+export OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_DOCKER_TAG)
+endif
+endif
+
+TEST_DESIGN ?= spm
+DESIGN_LIST ?= spm
+QUICK_RUN_DESIGN ?= spm
+BENCHMARK ?= regression_results/benchmark_results/SW_HD.csv
+REGRESSION_TAG ?= TEST_SW_HD
+FASTEST_TEST_SET_TAG ?= FASTEST_TEST_SET
+EXTENDED_TEST_SET_TAG ?= EXTENDED_TEST_SET
+PRINT_REM_DESIGNS_TIME ?= 0
+
+SKYWATER_COMMIT ?= $(shell $(PYTHON_BIN) ./dependencies/tool.py sky130 -f commit)
+OPEN_PDKS_COMMIT ?= $(shell $(PYTHON_BIN) ./dependencies/tool.py open_pdks -f commit)
+
+PDK_OPTS =
+EXTERNAL_PDK_INSTALLATION ?= 1
+ifeq ($(EXTERNAL_PDK_INSTALLATION), 1)
+export PDK_ROOT ?= ./pdks
+export PDK_ROOT := $(shell $(PYTHON_BIN) -c "import os; print(os.path.realpath('$(PDK_ROOT)'), end='')")
+PDK_OPTS = -v $(PDK_ROOT):$(PDK_ROOT) -e PDK_ROOT=$(PDK_ROOT)
+endif
+
+export STD_CELL_LIBRARY ?= sky130_fd_sc_hd
+STD_CELL_OPTS := -e STD_CELL_LIBRARY=$(STD_CELL_LIBRARY)
+
+# ./designs is mounted over ./install so env.tcl is not found inside the Docker
+# container if the user had previously installed it.
+ENV_START = docker run --rm\
+ -v $(OPENLANE_DIR):/openlane\
+ -v $(OPENLANE_DIR)/designs:/openlane/install\
+ $(PDK_OPTS)\
+ $(STD_CELL_OPTS)\
+ $(DOCKER_OPTIONS)
+
+ENV_COMMAND = $(ENV_START) $(OPENLANE_IMAGE_NAME)
+
+.DEFAULT_GOAL := all
+
+.PHONY: all
+all: get-openlane pdk
+
+.PHONY: openlane
+openlane: venv/created
+ @PYTHON_BIN=$(PWD)/venv/bin/$(PYTHON_BIN) $(MAKE) -C docker openlane
+
+pull-openlane:
+ @docker pull $(OPENLANE_IMAGE_NAME)
+
+get-openlane:
+ @$(MAKE) pull-openlane || $(MAKE) openlane
+
+.PHONY: mount
+mount:
+ cd $(OPENLANE_DIR) && \
+ $(ENV_START) -ti $(OPENLANE_IMAGE_NAME)
+
+.PHONY: pdk
+pdk: venv/created
+ ./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir volare
+ ./venv/bin/volare enable
+
+.PHONY: survey
+survey:
+ $(PYTHON_BIN) ./env.py issue-survey
+
+venv/created: ./requirements.txt ./dependencies/python/precompile_time.txt ./dependencies/python/run_time.txt
+ rm -rf ./venv
+ $(PYTHON_BIN) -m venv ./venv
+ ./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir pip
+ ./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir -r ./requirements.txt
+ touch $@
+
+DLTAG=custom_design_List
+.PHONY: test_design_list fastest_test_set extended_test_set
+fastest_test_set: DESIGN_LIST=$(shell cat ./.github/test_sets/fastest_test_set)
+fastest_test_set: DLTAG=$(FASTEST_TEST_SET_TAG)
+fastest_test_set: test_design_list
+extended_test_set: DESIGN_LIST=$(shell cat ./.github/test_sets/extended_test_set)
+extended_test_set: DLTAG=$(EXTENDED_TEST_SET_TAG)
+extended_test_set: test_design_list
+test_design_list:
+ cd $(OPENLANE_DIR) && \
+ $(ENV_COMMAND) sh -c "\
+ python3 run_designs.py\
+ --tag $(DLTAG)\
+ --threads $(THREADS)\
+ --print_rem $(PRINT_REM_DESIGNS_TIME)\
+ --benchmark $(BENCHMARK)\
+ $(DESIGN_LIST)\
+ "
+# -u is needed, as the python buffers the stdout, so no output is generated
+run_issue_regression:
+ cd $(OPENLANE_DIR) && \
+ $(ENV_COMMAND) sh -c "\
+ python3 -u run_issue_regressions.py run $(ISSUE_REGRESSION_DESIGN)"
+
+issue_regression_all:
+ cd $(OPENLANE_DIR) && \
+ $(ENV_COMMAND) sh -c "\
+ python3 -u run_issue_regressions.py run_all"
+
+.PHONY: test
+test:
+ cd $(OPENLANE_DIR) && \
+ $(ENV_COMMAND) sh -c "./flow.tcl -design $(TEST_DESIGN) -tag openlane_test -overwrite"
+ @[ -f $(OPENLANE_DIR)/designs/$(TEST_DESIGN)/runs/openlane_test/results/signoff/$(TEST_DESIGN).gds ] && \
+ echo "Basic test passed" || \
+ echo "Basic test failed"
+
+.PHONY: quick_run
+quick_run:
+ cd $(OPENLANE_DIR) && \
+ $(ENV_COMMAND) sh -c "./flow.tcl -design $(QUICK_RUN_DESIGN)"
+
+.PHONY: veryclean clean_runs clean_results
+veryclean:
+ @git clean -fdX
+
+clean_runs:
+ @rm -rf ./designs/*/runs && rm -rf ./_build/it_tc_logs && echo "Runs cleaned successfully." || echo "Failed to delete runs."
+ @rm -rf ./tests/*/runs && echo "Test runs cleaned successfully." || echo "Failed to delete test runs."
+
+clean_results:
+ @{ find regression_results -mindepth 1 -maxdepth 1 -type d | grep -v benchmark | xargs rm -rf ; } && echo "Results cleaned successfully." || echo "Failed to delete results."
\ No newline at end of file
diff --git a/openlane/README.md b/openlane/README.md
new file mode 100644
index 0000000..3941207
--- /dev/null
+++ b/openlane/README.md
@@ -0,0 +1,409 @@
+# OpenLane
+[](https://opensource.org/licenses/Apache-2.0) [](https://openlane.readthedocs.io/) [](#) [](https://invite.skywater.tools) [](https://github.com/psf/black)
+
+OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.
+
+You can find the latest release of OpenLane [here](https://github.com/The-OpenROAD-Project/OpenLane/releases).
+
+This documentation is also available at [ReadTheDocs](https://openlane.readthedocs.io/).
+
+# Table of contents
+- [Prerequisites](#prerequisites)
+- [Setting up OpenLane](#setting-up-openlane)
+ - [Installation Notes](#installation-notes)
+ - [Updating OpenLane](#updating-openlane)
+ - [Pulling or Building the OpenLane Docker Container](#pulling-or-building-the-openlane-docker-container)
+- [Running OpenLane](#running-openlane)
+ - [Command line arguments](#command-line-arguments)
+ - [Adding a design](#adding-a-design)
+- [OpenLane Architecture](#openlane-architecture)
+ - [OpenLane Design Stages](#openlane-design-stages)
+ - [OpenLane Output](#openlane-output)
+ - [Flow configuration](#flow-configuration)
+- [Regression And Design Configurations Exploration](#regression-and-design-configurations-exploration)
+- [Hardening Macros](#hardening-macros)
+- [Chip Integration](#chip-integration)
+- [Commands and Configurations](#commands-and-configurations)
+- [How To Contribute](#how-to-contribute)
+- [Authors](#authors)
+- [Additional Material](#additional-material)
+ - [Papers](#papers)
+ - [Videos And Tutorials](#videos-and-tutorials)
+
+# Prerequisites
+At a minimum:
+
+- GNU Make
+- Python 3.6+ with pip and virtualenv
+- Git 2.35+
+- Docker 19.03.12+
+
+## On Ubuntu, that's...
+`apt install -y build-essential python3 python3-venv python3-pip`
+
+* [Docker Installation Instructions](https://docs.docker.com/engine/install/ubuntu/)
+
+## On macOS, that's...
+Get [Homebrew](https://brew.sh/), then:
+
+`brew install python make`
+`brew install --cask docker`
+
+## Containerless/Local Installations
+Please see [here](./docs/source/local_installs.md).
+
+# Setting Up OpenLane
+You can set up the Sky130 PDK and OpenLane by running:
+
+```bash
+ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
+ cd OpenLane/
+ make
+ make test # This a ~5 minute test that verifies that the flow and the pdk were properly installed
+```
+
+- The Makefile should do the following when you run the above:
+ - Pulls the OpenLane Docker image.
+ - Pulls and updates the PDK
+ - Test the whole setup with a complete run on a small design, `spm`.
+
+This should produce a clean run for the spm. The final layout will be generated at this path: `./designs/spm/runs/openlane_test/results/magic/spm.gds`.
+
+If everything is okay, you can skip forward to [running OpenLane](#running-openlane).
+
+## Updating OpenLane
+
+If you already have the repo locally, then there is no need to re-clone it. You can run the following:
+
+```bash
+ cd OpenLane/
+ git checkout master
+ git pull
+ make
+ make test # This is to test that the flow and the pdk were properly updated
+```
+
+## Pulling or Building the OpenLane Docker Container
+
+**DISCLAIMER: This sub-section is to give you an understanding of what happens under the hood in the Makefile. You don't need to run the instructions here, if you already ran `make pull-openlane`.**
+
+For curious users: For more details about the docker container and its process, the [following instructions][1] walk you through the process of using docker containers to build the needed tools then integrate them into OpenLane flow. **You Don't Need To Re-Build It.**
+
+## Building the PDK Manually
+You don't have to build the PDK yourself anymore. But, if you insist, or require SCLs that are not installed by default, you can try the follow
+
+```bash
+ <configuration variables: see notes below>
+ make build-pdk-conda
+```
+* The default pdk installation directory is $PWD/pdks. If you want to install the PDK at a different location, you'll need add this configuration variable:
+ * `export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>`
+ * Be sure to add this to your shell's profile for future use.
+* The default SCL to be installed is `sky130_fd_sc_hd`.
+ * To change that, you can add this configuration variable: `export STD_CELL_LIBRARY=<Library name, i.e. sky130_fd_sc_ls>`, where the library name is one of:
+ - sky130_fd_sc_hd
+ - sky130_fd_sc_hs
+ - sky130_fd_sc_ms
+ - sky130_fd_sc_ls
+ - sky130_fd_sc_hdll
+ * You can install all Sky130 SCLs by invoking `FULL_PDK=1 make build-pdk-conda`.
+ * You can install the PDK manually, outside of the Makefile, by following the instructions provided [here][30].
+ * Refer to [this][24] for more details on OpenLane-compatible PDK structures.
+
+# Running OpenLane
+You need to start the Docker container with proper paths mounted. There are two ways to do this.
+
+The easiest way to mount the proper directories into the docker container would be to rely on the Makefile:
+
+```bash
+ make mount
+```
+
+* **Note:**
+ - Default PDK_ROOT is `$(pwd)/pdks`. If you have installed the PDK at a different location, run the following before `make mount`:
+ ```bash
+ export PDK_ROOT=<absolute path to where skywater-pdk, open_pdks, and sky130A reside>
+ ```
+ - Default OPENLANE_IMAGE_NAME is dynamically obtained using your current git version. If you want to use a specific image, run the following before `make mount`:
+ ```bash
+ export OPENLANE_IMAGE_NAME=<docker image name>
+ ```
+
+The following is roughly what happens under the hood when you run `make mount` + the required exports:
+
+```bash
+ export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
+ export OPENLANE_IMAGE_NAME=<docker image name>
+ docker run -it -v $(pwd):/openlane -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $OPENLANE_IMAGE_NAME
+```
+
+**Note: this will mount the OpenLane directory and the PDK_ROOT directory inside the container.**
+
+You can use the following example to check the overall setup:
+
+```bash
+./flow.tcl -design spm
+```
+
+To run OpenLane on multiple designs at the same time, check this [section](#regression-and-design-configurations-exploration).
+
+Having trouble running the flow? check [FAQs](https://github.com/The-OpenROAD-Project/OpenLane/wiki)
+
+## Command line arguments
+
+The following are arguments that can be passed to `flow.tcl`
+
+| Argument | Description |
+| - | - |
+| `-design <folder path>` <br>(Required) | Specifies the design folder. A design folder should contain a config.tcl defining the design parameters. <br>If the folder is not found, ./designs directory is searched |
+| `-from <stage>` <br>(Optional) | Specifies stage to start flow execution from |
+| `-to <stage>` <br>(Optional) | Specifies stage to stop flow execution at (included) |
+| `-config_file <file>` <br>(Optional) | Specifies the design's configuration file for running the flow. <br>For example, to run the flow using `/spm/config2.tcl` <br>Use run `./flow.tcl -design /spm -config_file /spm/config2.tcl` <br>By default `config.tcl` is used. |
+| `-override_env` <br> Optional | Allows you to override certain configuration environment variables for this run. Format: `KEY1=VALUE1,KEY2=VALUE2` |
+| `-config_tag <name>` <br>(Optional) | Specifies the design's configuration file for running the flow. <br>For example, to run the flow using `designs/spm/config2.tcl` <br>Use run `./flow.tcl -design spm -config_tag config2` <br>By default `config` is used. |
+| `-tag <name>` <br>(Optional) | Specifies a `name` for a specific run. If the tag is not specified, a timestamp is generated for identification of that run. <br>Can Specify the configuration file name in case of using `-init_design_config` |
+| `-run_path <path>` <br>(Optional) | Specifies a `path` to save the run in. By default the run is in `design_path/`, where the design path is the one passed to `-design` |
+| `-src <verilog_source_file>` <br>(Optional) | Sets the verilog source code file(s) in case of using `-init\_design\_config`. <br>The default is that the source code files are under `design_path/src/`, where the design path is the one passed to `-design` |
+| `-init_design_config` <br>(Optional) | Creates a tcl configuration file for a design. `-tag <name>` can be added to rename the config file to `<name>.tcl` |
+| `-overwrite` <br>(Optional) | Flag to overwirte an existing run with the same tag |
+| `-interactive` <br>(Optional) | Flag to run openlane flow in interactive mode |
+| `-file <file_path>` <br>(Optional) | Passes a script of interactive commands in interactive mode |
+| `-synth_explore` <br>(Boolean) | If enabled, synthesis exploration will be run (only synthesis exploration), which will try out the available synthesis strategies against the input design. The output will be the four possible gate level netlists under <run_path/results/synthesis> and a summary report under reports that compares the 4 outputs. |
+| `-lvs` <br>(Boolean) | If enabled, only LVS will be run on the design. in which case the user must also pass: -design DESIGN\_DIR -gds DESIGN\_GDS -net DESIGN_NETLIST. |
+| `-drc` <br>(Boolean) | If enabled, only DRC will be run on the design. in which case the user must also pass: -design DESIGN\_DIR -gds DESIGN\_GDS -report OUTPUT\_REPORT\_PATH -magicrc MAGICRC. |
+| `-save` <br>(Optional) | A flag to save a runs results like .mag and .lef in the design's folder. |
+| `-save_path <path>` <br>(Optional) | Specifies a different path to save the design's result. This option is to be used with the `-save` flag. |
+
+## Adding a design
+
+To add a new design, follow the instructions provided [here](./designs/README.md)
+
+This [file](./designs/README.md) also includes useful information about the design configuration files. It also includes useful utilities for exploring and updating design configurations for each (PDK,STD_CELL_LIBRARY) pair.
+
+# OpenLane Architecture
+
+<table>
+ <tr>
+ <td align="center"><img src="./docs/_static/openlane.flow.1.png" ></td>
+ </tr>
+
+</table>
+
+
+## OpenLane Design Stages
+
+OpenLane flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLane can also be run interactively as shown [here][25].
+
+1. **Synthesis**
+ 1. `yosys` - Performs RTL synthesis
+ 2. `abc` - Performs technology mapping
+ 3. `OpenSTA` - Performs static timing analysis on the resulting netlist to generate timing reports
+2. **Floorplan and PDN**
+ 1. `init_fp` - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
+ 2. `ioplacer` - Places the macro input and output ports
+ 3. `pdn` - Generates the power distribution network
+ 4. `tapcell` - Inserts welltap and decap cells in the floorplan
+3. **Placement**
+ 1. `RePLace` - Performs global placement
+ 2. `Resizer` - Performs optional optimizations on the design
+ 3. `OpenDP` - Perfroms detailed placement to legalize the globally placed components
+4. **CTS**
+ 1. `TritonCTS` - Synthesizes the clock distribution network (the clock tree)
+5. **Routing**
+ 1. `FastRoute` - Performs global routing to generate a guide file for the detailed router
+ 2. `CU-GR` - Another option for performing global routing.
+ 3. `TritonRoute` - Performs detailed routing
+ 4. `SPEF-Extractor` - Performs SPEF extraction
+6. **GDSII Generation**
+ 1. `Magic` - Streams out the final GDSII layout file from the routed def
+ 2. `Klayout` - Streams out the final GDSII layout file from the routed def as a back-up
+7. **Checks**
+ 1. `Magic` - Performs DRC Checks & Antenna Checks
+ 2. `Klayout` - Performs DRC Checks
+ 3. `Netgen` - Performs LVS Checks
+ 4. `CVC` - Performs Circuit Validity Checks
+
+OpenLane integrated several key open source tools over the execution stages:
+- RTL Synthesis, Technology Mapping, and Formal Verification : [yosys + abc][4]
+- Static Timing Analysis: [OpenSTA][8]
+- Floor Planning: [init_fp][5], [ioPlacer][6], [pdn][16] and [tapcell][7]
+- Placement: [RePLace][9] (Global), [Resizer][15] and [OpenPhySyn][28] (formerly), and [OpenDP][10] (Detailed)
+- Clock Tree Synthesis: [TritonCTS][11]
+- Fill Insertion: [OpenDP/filler_placement][10]
+- Routing: [FastRoute][12] or [CU-GR][36] (Global) and [TritonRoute][13] (Detailed)
+- SPEF Extraction: [SPEF-Extractor][27] (formerly), [OpenRCX][37]
+- GDSII Streaming out: [Magic][14] and [Klayout][35]
+- DRC Checks: [Magic][14] and [Klayout][35]
+- LVS check: [Netgen][22]
+- Antenna Checks: [Magic][14]
+- Circuit Validity Checker: [CVC][31]
+
+## OpenLane Output
+
+All output run data is placed by default under ./designs/design_name/runs. Each flow cycle will output a timestamp-marked folder containing the following file structure:
+
+```
+designs/<design_name>
+├── config.tcl
+├── runs
+│ ├── <tag>
+│ │ ├── config.tcl
+│ │ ├── {logs, reports, tmp}
+│ │ │ ├── cts
+│ │ │ ├── signoff
+│ │ │ ├── floorplan
+│ │ │ ├── placement
+│ │ │ ├── routing
+│ │ │ └── synthesis
+│ │ ├── results
+│ │ │ ├── final
+│ │ │ ├── cts
+│ │ │ ├── signoff
+│ │ │ ├── floorplan
+│ │ │ ├── placement
+│ │ │ ├── routing
+│ │ │ └── synthesis
+```
+
+To delete all generated runs under all designs:
+`make clean_runs`
+
+## Flow configuration
+
+1. PDK / technology specific
+2. Flow specific
+3. Design specific
+
+- A PDK should define at least one standard cell library(SCL) for the PDK. A common configuration file for all SCLs is located in:
+
+ ```
+ $PDK_ROOT/$PDK/config.tcl
+ ```
+
+ - Sometimes the PDK comes with several standard cell libraries. Each has an own configuration file that defines extra variables specific to the SCL. It may also override variables in the common PDK configuration file which is located in:
+
+ ```
+ $PDK_ROOT/$PDK/$STD_CELL_LIBRARY/config.tcl
+ ```
+ - More on configuring a new PDK in this [section](#setting-up-OpenLane)
+
+- Flow specific variables are related to the flow and are initialized with default values in:
+
+ ```
+ ./configuration/
+ ```
+
+- Finally, each design should have it's own configuration file with some required variables which are available in this [list][17]. A design configuration file may override any of the variables defined in PDK or flow configuration files. This is the global configurations for the design:
+
+ ```
+ ./designs/<design>/config.tcl
+ ```
+ - More on design configurations in [here](./designs/README.md)
+
+A list of all available variables can be found [here][17].
+
+
+
+# Regression And Design Configurations Exploration
+
+As mentioned earlier, everytime a new design or a new (PDK,STD_CELL_LIBRARY) pair is added, or any update happens in the flow tools, a re-configuration for the designs is needed. The reconfiguration is methodical and so an exploration script was developed to aid the designer in reconfiguring his designs if needed.
+As explained [here](#adding-a-design) that each design has multiple configuration files for each (PDK,STD_CELL_LIBRARY) pair.
+
+OpenLane provides `run_designs.py`, a script that can do multiple runs in a parallel using different configurations. A run consists of a set of designs and a configuration file that contains the configuration values. It is useful to explore the design implementation using different configurations to figure out the best one(s).
+
+Also, it can be used for testing the flow by running the flow against several designs using their best configurations. For example the following run: spm using its default configuration files `config.tcl.` :
+```
+python3 run_designs.py --tag test --threads 3 spm xtea md5 aes256
+```
+
+For more information on how to run this script, refer to this [file][21]
+
+OpenLane also has flow for issue regression testing. Refer to this [document][38].
+
+For more information on design configurations, how to update them, and the need for an exploration for each design, refer to this [file](./designs/README.md)
+
+# Hardening Macros
+
+This is discussed in more detail [here][29].
+
+# Chip Integration
+
+The first step of chip integration is hardening the macros. To learn more about this check this [file][29].
+
+Using OpenLane, you can produce a GDSII from a chip RTL. This is done by applying a certain methodology that we follow using our custom scripts and the integrated tools.
+
+To learn more about Chip Integration. Check this [file][26]
+
+# Commands and Configurations
+
+To get a full list of the OpenLane commands, first introduce yourself to the interactive mode of OpenLane [here][25]. Then check the full documentation of the OpenLane commands [here][34].
+
+The full documentation of OpenLane run configurations could be found [here][2].
+
+# How To Contribute
+
+We discuss the details of how to contribute to OpenLane in [this documentation][32].
+
+# Authors
+
+To check the original author list of OpenLane, check [this][33].
+
+# Additional Material
+
+## Papers
+- Ahmed Ghazy and Mohamed Shalan, "OpenLANE: The Open-Source Digital ASIC Implementation Flow", Article No.21, Workshop on Open-Source EDA Technology (WOSET), 2020. [Paper](https://github.com/woset-workshop/woset-workshop.github.io/blob/master/PDFs/2020/a21.pdf)
+- M. Shalan and T. Edwards, "Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-6. [Paper](https://ieeexplore.ieee.org/document/9256623/)
+- R. Timothy Edwards, M. Shalan and M. Kassem, "Real Silicon using Open Source EDA," in IEEE Design & Test, doi: 10.1109/MDAT.2021.3050000. [Paper](https://ieeexplore.ieee.org/document/9336682)
+
+## Videos and Tutorials
+
+### OpenLane Specific
+
+- [FOSSi Dial-Up - OpenLane, A Digital ASIC Flow for SkyWater 130nm Open PDK, Mohamed Shalan](https://www.youtube.com/watch?v=Vhyv0eq_mLU)
+- [Openlane Overview, Ahmed Ghazy](https://www.youtube.com/watch?v=d0hPdkYg5QI)
+- [Free VLSI Tutorial - VSD - A complete guide to install Openlane and Sky130nm PDK](https://www.udemy.com/course/vsd-a-complete-guide-to-install-openlane-and-sky130nm-pdk)
+- [Sky130 - Exploring OpenLANE and OpenDB to create a register file , Sylvain Munaut](https://www.youtube.com/watch?v=AT_LcmaCZmw)
+- [VLSI SoC EDA openLANE with Skywater 130 PDK, Gary Huang](https://www.youtube.com/watch?v=QnJzoJjC7RQ)
+
+### Caravel & SkyWater PDK
+- [Aboard Caravel, Ahmed Ghazy](https://www.youtube.com/watch?v=9QV8SDelURk)
+- [FOSSi Dial-Up - Skywater PDK: Fully open source manufacturable PDK for a 130nm process, Tim Ansell](https://www.youtube.com/watch?v=EczW2IWdnOM&)
+- [Skywater 130nm PDK - Initial Discovery, Sylvain Munaut](https://www.youtube.com/watch?v=gRYBdTXbxiU)
+
+[1]: ./docker/README.md
+[2]: ./configuration/README.md
+[4]: https://github.com/YosysHQ/yosys
+[5]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ifp
+[6]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ppl
+[7]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/tap
+[8]: https://github.com/The-OpenROAD-Project/OpenSTA
+[9]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/replace
+[10]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/dpl
+[11]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/cts
+[12]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/grt
+[13]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/TritonRoute
+[14]: https://github.com/RTimothyEdwards/magic
+[15]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rsz
+[16]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pdn
+[17]: ./configuration/README.md
+[18]: https://github.com/RTimothyEdwards/qflow/blob/master/src/addspacers.c
+[19]: https://github.com/The-OpenROAD-Project/
+[20]: https://github.com/git-lfs/git-lfs/wiki/Installation
+[21]: ./regression_results/README.md
+[22]: https://github.com/RTimothyEdwards/netgen
+[24]: ./docs/source/pdk_structure.md
+[25]: ./docs/source/advanced_readme.md
+[26]: ./docs/source/chip_integration.md
+[27]: https://github.com/HanyMoussa/SPEF_EXTRACTOR
+[28]: https://github.com/scale-lab/OpenPhySyn
+[29]: ./docs/source/hardening_macros.md
+[30]: ./docs/source/manual_pdk_installation.md
+[31]: https://github.com/d-m-bailey/cvc
+[32]: ./CONTRIBUTING.md
+[33]: ./AUTHORS.md
+[34]: ./docs/source/openlane_commands.md
+[35]: https://github.com/KLayout/klayout
+[36]: https://github.com/cuhk-eda/cu-gr
+[37]: https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rcx
+[38]: ./docs/source/issue_regression_tests.md
+
diff --git a/openlane/conf.py b/openlane/conf.py
new file mode 100644
index 0000000..beef768
--- /dev/null
+++ b/openlane/conf.py
@@ -0,0 +1,118 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+# Yes, it needs to be in this directory. Don't try to move it.
+# Yes, it needs to be called conf.py
+
+
+# -- Path setup --------------------------------------------------------------
+import os
+import sys
+from recommonmark.parser import CommonMarkParser
+
+sys.path.insert(0, os.path.abspath("docs/_ext"))
+
+# -- Project information -----------------------------------------------------
+project = "OpenLane"
+copyright = "2020-2021 Efabless Corporation"
+author = "Efabless Corporation"
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ "sphinx.ext.todo",
+ "markdown_code_links", # CUSTOM
+ "markdown_cross_doc_section_links", # CUSTOM
+ "sphinx.ext.autosectionlabel",
+ "sphinx_markdown_tables",
+ "image_links", # CUSTOM
+ "toc_from_markdown", # CUSTOM
+ "recommonmark",
+]
+
+# Expand source suffixes
+
+source_parsers = {
+ ".md": CommonMarkParser,
+}
+
+source_suffix = {
+ ".rst": "restructuredtext",
+ ".md": "markdown",
+}
+
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ["_templates"]
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ "_build",
+ "Thumbs.db",
+ "scripts/tcl_commands/README.md",
+ # Files included in other rst files.
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_title = "OpenLane Documentation"
+
+html_theme = "furo"
+
+# Theme options are theme-specific and customize the look and feel of a theme
+# further. For a list of options available for each theme, see the
+# documentation.
+html_theme_options = {}
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ["docs/_static"]
+
+html_sidebars = {}
+
+todo_include_todos = True
+numfig = True
+markdown_code_links_githubrepo = "https://github.com/The-OpenROAD-Project/OpenLane"
+markdown_code_links_githubbranch = "blob/master"
+markdown_code_links_codefileextensions = [
+ ".tcl",
+ ".sh",
+ ".cfg",
+ ".gds",
+ ".sdc",
+ "/",
+ ".json",
+ "Makefile",
+]
+autosectionlabel_prefix_document = True
+
+suppress_warnings = ["misc.highlighting_failure"] # supress json highlight warnings
+
+
+def setup(app):
+ app.emit("create_index_softlink", "README.md", True)
+ app.emit("toc_from_markdown", "README.md", ".autotoc.rst", True)
diff --git a/openlane/configuration/README.md b/openlane/configuration/README.md
new file mode 100644
index 0000000..5695d39
--- /dev/null
+++ b/openlane/configuration/README.md
@@ -0,0 +1,329 @@
+# Variables information
+
+This page describes configuration variables and their default values.
+
+## Required variables
+
+| Variable | Description |
+|---------------|-------------------------------------------------------|
+| `DESIGN_NAME` | The name of the top level module of the design |
+| `VERILOG_FILES` | The path of the design's verilog files |
+| `CLOCK_PERIOD` | The clock period for the design in ns |
+| `CLOCK_NET` | The name of the Net input to root clock buffer used in Clock Tree Synthesis. |
+| `CLOCK_PORT` | The name of the design's clock port used in Static Timing Analysis. |
+
+## Optional variables
+
+These variables are optional that can be specified in the design configuration file.
+
+### Synthesis
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `SYNTH_BIN` | The yosys binary used in the flow. <br> (Default: `yosys`) |
+| `LIB_SYNTH` | The library used for synthesis by yosys. <br> (Default: `$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__tt_025C_1v80.lib`)|
+| `SYNTH_DRIVING_CELL` | The cell to drive the input ports. <br>(Default: `sky130_fd_sc_hd__inv_1`)|
+| `SYNTH_DRIVING_CELL_PIN` | The name of the SYNTH_DRIVING_CELL output pin. <br>(Default: `Y`)|
+| `SYNTH_CAP_LOAD` | The capacitive load on the output ports in femtofarads. <br> (Default: `33.5` ff)|
+| `SYNTH_MAX_FANOUT` | The max load that the output ports can drive. <br> (Default: `5` cells) |
+| `SYNTH_MAX_TRAN` | The max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis <br> (Default: Calculated at runtime as `10%` of the provided clock period, unless this exceeds a set DEFAULT_MAX_TRAN, in which case it will be used as is). |
+| `SYNTH_CLOCK_UNCERTAINITY` | Specifies a value for the clock uncertainity in the pre-CTS stages. <br> (Default: `0.25`) |
+| `SYNTH_CLOCK_TRANSITION` | Specifies a value for the clock transition in the pre-CTS stages. <br> (Default: `0.15`) |
+| `SYNTH_TIMING_DERATE` | Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing. <br> (Default: `+5%/-5%`) |
+| `SYNTH_STRATEGY` | Strategies for abc logic synthesis and technology mapping <br> Possible values are `DELAY/AREA 0-4/0-3`; the first part refers to the optimization target of the synthesis strategy (area vs. delay) and the second one is an index. <br> (Default: `AREA 0`)|
+| `SYNTH_BUFFERING` | Enables abc cell buffering <br> Enabled = 1, Disabled = 0 <br> (Default: `1`)|
+| `SYNTH_SIZING` | Enables abc cell sizing (instead of buffering) <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
+| `SYNTH_READ_BLACKBOX_LIB` | A flag that enable reading the full(untrimmed) liberty file as a blackbox for synthesis. Please note that this is not used in technology mapping. This should only be used when trying to preserve gate instances in the rtl of the design. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
+| `SYNTH_NO_FLAT` | A flag that disables flattening the hierarchy during synthesis, only flattening it after synthesis, mapping and optimizations. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
+| `SYNTH_SHARE_RESOURCES` | A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. <br> Enabled = 1, Disabled = 0 <br> (Default: `1`)|
+| `SYNTH_ADDER_TYPE` | Adder type to which the $add and $sub operators are mapped to. <br> Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder. <br> (Default: `YOSYS`)|
+| `SYNTH_EXTRA_MAPPING_FILE` | Points to extra techmap file for yosys that runs right after yosys `synth` before generic techmap. <br> (Default: `""`)|
+| `LIB_FASTEST` | Points to the lib file, corresponding to the slowest corner, for max delay calculation during STA. <br> (Default: `$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib`) |
+| `LIB_SLOWEST` | Points to the lib file, corresponding to the fastest corner, for min delay calculation during STA. <br> (Default: `$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ss_100C_1v60.lib`) |
+| `LIB_TYPICAL` | Library used for typical delay calculation during STA. <br> (Default`LIB_SYNTH`) |
+| `CLOCK_BUFFER_FANOUT` | Fanout of clock tree buffers. <br> (Default: `16`) |
+| `ROOT_CLK_BUFFER` | Root clock buffer of the clock tree. <br> (Default: `sky130_fd_sc_hd__clkbuf_16`) |
+| `CLK_BUFFER` | Clock buffer used for inner nodes of the clock tree. <br> (Default: `sky130_fd_sc_hd__clkbuf_4`) |
+| `CLK_BUFFER_INPUT` | Input pin of the clock tree buffer. <br> (Default: `A`) |
+| `CLK_BUFFER_OUTPUT` | Output pin of the clock tree buffer. <br> (Default: `X`) |
+| `BASE_SDC_FILE` | Specifies the base sdc file to source before running Static Timing Analysis. <br> (Default: `$::env(OPENLANE_ROOT)/scripts/base.sdc`) |
+| `VERILOG_INCLUDE_DIRS` | Specifies the verilog includes directories. <br> Optional. |
+| `SYNTH_FLAT_TOP` | Specifies whether or not the top level should be flattened during elaboration. 1 = True, 0= False <br> Default: `0`. |
+| `IO_PCT` | Specifies the percentage of the clock period used in the input/output delays. Ranges from 0 to 1.0. <br> (Default: `0.2`) |
+| `VERILOG_FILES_BLACKBOX` | To point at the blackboxes (the hardened macros). Ideally, this should include all the other verilog files |
+
+### Floorplanning
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `FP_CORE_UTIL` | The core utilization percentage. <br> (Default: `50` percent)|
+| `FP_ASPECT_RATIO` | The core's aspect ratio (height / width). <br> (Default: `1`)|
+| `FP_SIZING` | Whether to use relative sizing by making use of `FP_CORE_UTIL` or absolute one using `DIE_AREA`. <br> (Default: `"relative"` - accepts "absolute" as well)|
+| `DIE_AREA` | Specific die area to be used in floorplanning. Specified as a 4-corner rectangle "x0 y0 x1 y1". Units in um <br> (Default: unset)|
+| `FP_IO_MODE` | Decides the mode of the random IO placement option. 0=matching mode, 1=random equidistant mode <br> (Default: `1`)|
+| `FP_WELLTAP_CELL` | The name of the welltap cell during welltap insertion. |
+| `FP_ENDCAP_CELL` | The name of the endcap cell during endcap insertion. |
+| `FP_PDN_VOFFSET` | The offset of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `16.32`) |
+| `FP_PDN_VPITCH` | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
+| `FP_PDN_HOFFSET` | The offset of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.65`) |
+| `FP_PDN_HPITCH` | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
+| `FP_PDN_AUTO_ADJUST` | Decides whether or not the flow should attempt to re-adjust the power grid, in order for it to fit inside the core area of the design, if needed. <br> 1=enabled, 0 =disabled (Default: `1`) |
+| `FP_TAPCELL_DIST` | The horizontal distance between two tapcell columns <br> (Default: `14`) |
+| `FP_IO_VEXTEND` | Extends the vertical io pins outside of the die by the specified units<br> (Default: `-1` Disabled) |
+| `FP_IO_HEXTEND` | Extends the horizontal io pins outside of the die by the specified units<br> (Default: `-1` Disabled) |
+| `FP_IO_VLENGTH` | The length of the vertical IOs in microns. <br> (Default: `4`) |
+| `FP_IO_HLENGTH` | The length of the horizontal IOs in microns. <br> (Default: `4`) |
+| `FP_IO_VTHICKNESS_MULT` | A multiplier for vertical pin thickness. Base thickness is the pins layer minwidth <br> (Default: `2`) |
+| `FP_IO_HTHICKNESS_MULT` | A multiplier for horizontal pin thickness. Base thickness is the pins layer minwidth <br> (Default: `2`) |
+| `FP_IO_UNMATCHED_ERROR` | Exit on unmatched pins in a provided `FP_PIN_ORDER_CFG` file. 0=Disable 1=Enable. <br> (Default: `1` Enabled) |
+| `BOTTOM_MARGIN_MULT` | The core margin, in multiples of site heights, from the bottom boundary. <br> (Default: `4`) |
+| `TOP_MARGIN_MULT` | The core margin, in multiples of site heights, from the top boundary. <br> (Default: `4`) |
+| `LEFT_MARGIN_MULT` | The core margin, in multiples of site widths, from the left boundary. <br> (Default: `12`) |
+| `RIGHT_MARGIN_MULT` | The core margin, in multiples of site widths, from the right boundary. <br> (Default: `12`) |
+| `FP_PDN_CORE_RING` | Enables adding a core ring around the design. More details on the control variables in the pdk configurations documentation. 0=Disable 1=Enable. <br> (Default: `0`) |
+| `FP_PDN_ENABLE_RAILS` | Enables the creation of rails in the power grid. 0=Disable 1=Enable. <br> (Default: `1`) |
+| `FP_PDN_ENABLE_MACROS_GRID` | Enables the connection of macros to the top level power grid. 0=Disable 1=Enable. <br> (Default: `1`) |
+| `FP_PDN_MACRO_HOOKS` | Specifies explicit power connections of internal macros to the top level power grid. Comma separated list of macro instance names and power domain vdd and ground net names: `<instance_name> <vdd_net> <gnd_net>` |
+| `FP_PDN_CHECK_NODES` | Enables checking for unconnected nodes in the power grid. 0=Disable 1=Enable. <br> (Default: `1`) |
+| `FP_TAP_HORIZONTAL_HALO` | Specify the horizontal halo size around macros during tap insertion. The value provided is in microns. <br> Default: `10` |
+| `FP_TAP_VERTICAL_HALO` | Specify the vertical halo size around macros during tap insertion. The value provided is in microns. <br> Default: set to the value of `FP_TAP_HORIZONTAL_HALO` |
+| `FP_PDN_HORIZONTAL_HALO` | Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns. <br> Default: `10` |
+| `FP_PDN_VERTICAL_HALO` | Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. <br> Default: set to the value of `FP_PDN_HORIZONTAL_HALO` |
+| `DESIGN_IS_CORE` | Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
+| `FP_PIN_ORDER_CFG` | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). Check this [file][0] as an example. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
+| `FP_CONTEXT_DEF` | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
+| `FP_CONTEXT_LEF` | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
+| `FP_DEF_TEMPLATE` | Points to the DEF file to be used as a template when running `apply_def_template`. This will be used to exctract pin names, locations, shapes -excluding power and ground pins- as well as the die area and replicate all this information in the `CURRENT_DEF`. |
+| `VDD_NETS` | Specifies the power nets/pins to be used when creating the power grid for the design. |
+| `GND_NETS` | Specifies the ground nets/pins to be used when creating the power grid for the design. |
+| `SYNTH_USE_PG_PINS_DEFINES` | Specifies the power guard used in the verilog source code to specify the power and ground pins. This is used to automatically extract `VDD_NETS` and `GND_NET` variables from the verilog, with the assumption that they will be order `inout vdd1, inout gnd1, inout vdd2, inout gnd2, ...`. |
+| `FP_PDN_IRDROP` | Enable calculation of power grid IR drop during PDN generation. <br> (Default: `1`)|
+| `FP_IO_MIN_DISTANCE` | The minmimum distance between the IOs in microns. <br> (Default: `3`) |
+
+#### Deprecated I/O Layer variables
+These variables worked initially, but they were too sky130 specific and will be removed. Currently, if you define them in your design, they'll be used, but it's recommended to update your configuration to use `FP_IO_HLAYER` and `FP_IO_VLAYER`, which are defined in the PDK.
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `FP_IO_HMETAL` | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br>(Default: `4`)|
+| `FP_IO_VMETAL` | The metal layer on which to place the io pins vertically (sides of the die) <br> (Default: `3`)|
+
+
+### Placement
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `0.55`)|
+| `PL_TIME_DRIVEN` | Specifies whether the placer should use time driven placement. 0 = false, 1 = true <br> (Default: `1`)|
+| `PL_LIB` | Specifies the library for time driven placement <br> (Default: `LIB_TYPICAL`)|
+| `PL_BASIC_PLACEMENT` | Specifies whether the placer should run basic placement or not (by running initial placement, increasing the minimum overflow to 0.9, and limiting the number of iterations to 20). 0 = false, 1 = true <br> (Default: `0`) |
+| `PL_SKIP_INITIAL_PLACEMENT` | Specifies whether the placer should run initial placement or not. 0 = false, 1 = true <br> (Default: `0`) |
+| `PL_RANDOM_GLB_PLACEMENT` | Specifies whether the placer should run random placement or not. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true <br> (Default: `0`) |
+| `PL_RANDOM_INITIAL_PLACEMENT` | Specifies whether the placer should run random placement or not followed by replace's initial placement. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true <br> (Default: `0`) |
+| `PL_ROUTABILITY_DRIVEN` | Specifies whether the placer should use routability driven placement. 0 = false, 1 = true <br> (Default: `1`) |
+| `PL_RESIZER_DESIGN_OPTIMIZATIONS` | Specifies whether resizer design optimizations should be performed or not. 0 = false, 1 = true <br> (Default: `1`) |
+| `PL_RESIZER_TIMING_OPTIMIZATIONS` | Specifies whether resizer timing optimizations should be performed or not. 0 = false, 1 = true <br> (Default: `1`) |
+| `PL_RESIZER_MAX_WIRE_LENGTH` | Specifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns. <br> (Default: `0`)|
+| `PL_RESIZER_MAX_SLEW_MARGIN` | Specifies a margin for the slews in percentage. <br> (Default: `20`)|
+| `PL_RESIZER_MAX_CAP_MARGIN` | Specifies a margin for the capacitances in percentage. <br> (Default: `20`)|
+| `PL_RESIZER_HOLD_SLACK_MARGIN` | Specifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix. <br> (Default: `0.1ns`.)|
+| `PL_RESIZER_SETUP_SLACK_MARGIN` | Specifies a time margin for the slack when fixing setup violations. <br> (Default: `0.05ns`)|
+| `PL_RESIZER_HOLD_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `50`)|
+| `PL_RESIZER_SETUP_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `50`)|
+| `PL_RESIZER_ALLOW_SETUP_VIOS` | Allows setup violations when fixing hold. <br> (Default: `0`)|
+| `LIB_RESIZER_OPT` | Points to the lib file, corresponding to the typical corner, that is used during resizer optimizations. This is copy of `LIB_SYNTH_COMPLETE`. <br> Default: `$::env(synthesis_tmpfiles)/resizer_<library-name>.lib` |
+| `DONT_USE_CELLS` | The list of cells to not use during resizer optimizations. <br> Default: the contents of `DRC_EXCLUDE_CELL_LIST`. |
+| `PL_ESTIMATE_PARASITICS` | Specifies whether or not to run STA after global placement using OpenROAD's estimate_parasitics -placement and generates reports under `logs/placement`. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `PL_OPTIMIZE_MIRRORING` | Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `PL_RESIZER_BUFFER_INPUT_PORTS` | Specifies whether or not to insert buffers on input ports whenever resizer optimizations are run. For this to be used, `PL_RESIZER_DESIGN_OPTIMIZATIONS` must be set to 1. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `PL_RESIZER_BUFFER_OUTPUT_PORTS` | Specifies whether or not to insert buffers on output ports whenever resizer optimizations are run. For this to be used, `PL_RESIZER_DESIGN_OPTIMIZATIONS` must be set to 1. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `PL_RESIZER_REPAIR_TIE_FANOUT` | Specifies whether or not to repair tie cells fanout whenever resizer optimizations are run. For this to be used, `PL_RESIZER_DESIGN_OPTIMIZATIONS` must be set to 1. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `PL_MAX_DISPLACEMENT_X` | Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement. <br> (Default: `500`um) |
+| `PL_MAX_DISPLACEMENT_Y` | Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement. <br> (Default: `100`um) |
+| `PL_MACRO_HALO` | Macro placement halo. Format: `{Horizontal} {Vertical}` <br> (Default: `0 0`um). |
+| `PL_MACRO_CHANNEL` | Channel widths between macros. Format: `{Horizontal} {Vertical}` <br> (Default: `0 0`um). |
+| `MACRO_PLACEMENT_CFG` | Specifies the path a file specifying how openlane should place certain macros |
+| `LIB_OPT` | **Removed**: Points to the lib file, corresponding to the slowest corner, for max delay calculation during OpenPhySyn optimizations. This is usually a trimmed version of `LIB_SYNTH`. <br> Default: `$::env(TMP_DIR)/opt.lib` |
+| `PL_DIAMOND_SEARCH_HEIGHT` | **Removed: Use PL_MAX_DISPLACEMENT_(X/Y) instead**: Specifies the diamond search height used for legalizing the cells during detailed placement. The search width is calculated internally as `heigh*5`. For designs that contain big macros, increasing this value to above 400 will allow for more search space and more potentail for successful legalization. <br> (Default: `100`) |
+| `PL_OPENPHYSYN_OPTIMIZATIONS` | **Removed**: Specifies whether OpenPhySyn should be used to perform timing optimizations or not. 0 = false, 1 = true <br> (Default: `0`) |
+| `PSN_ENABLE_RESIZING` | **Removed**: Enables driver resizing by OpenPhySyn. 0 = Disabled, 1 = Enabled <br> (Default: `1`)|
+| `PSN_ENABLE_PIN_SWAP` | **Removed**: Enables pin swapping for timing optimization by OpenPhySyn. 0 = Disabled, 1 = Enabled <br> (Default: `1`)|
+
+### CTS
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `CTS_TARGET_SKEW` | The target clock skew in picoseconds. <br> (Default: `200`ps)|
+| `CTS_ROOT_BUFFER`| The name of cell inserted at the root of the clock tree. |
+| `CLOCK_TREE_SYNTH` | Enable clock tree synthesis. <br> (Default: `1`)|
+| `RUN_SIMPLE_CTS` | Runs an alternative simple clock tree synthesis after synthesis instead of TritonCTS. 1 = Enabled, 0 = Disabled <br> (Default: `0`)|
+| `FILL_INSERTION` | Enables fill cells insertion after cts (if enabled). 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `CTS_TOLERANCE` | An integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR <br> (Default: `100`) |
+| `CTS_SINK_CLUSTERING_SIZE` | Specifies the maximum number of sinks per cluster. <br> (Default: `25`) |
+| `CTS_SINK_CLUSTERING_MAX_DIAMETER` | Specifies maximum diameter (in micron) of sink cluster. <br> (Default: `50`) |
+| `CTS_REPORT_TIMING` | Specifies whether or not to run STA after clock tree synthesis using OpenROAD's estimate_parasitics -placement and generates reports under `logs/cts`. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `CTS_CLK_MAX_WIRE_LENGTH` | Specifies the maximum wire length on the clock net. Value in microns. <br> (Default: `0`) |
+| `CTS_DISABLE_POST_PROCESSING` | Specifies whether or not to disable post cts processing for outlier sinks. <br> (Default: `0`) |
+| `CTS_DISTANCE_BETWEEN_BUFFERS` | Specifies the distance (in microns) between buffers when creating the clock tree (Default: `0`) |
+| `LIB_CTS` | The liberty file used for CTS. By default, this is the `LIB_SYNTH_COMPLETE` minus the cells with drc errors as specified by the drc exclude list. <br> (Default: `$::env(cts_tmpfiles)/cts.lib`) |
+
+### Routing
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
+| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or` (identical to `tritonroute`, deprecated) or `drcu`. <br> (Default: `tritonroute`)|
+| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. Can be overriden via environment variable. <br> (Default: `2`) |
+| `RT_CLOCK_MIN_LAYER` | The name of lowest layer to be used in routing the clock net. <br> (Default: `RT_MIN_LAYER`)|
+| `RT_CLOCK_MAX_LAYER` | The name of highest layer to be used in routing the clock net. <br> (Default: `RT_MAX_LAYER`)|
+| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resulting guides. 0 = false, 1 = true <br> (Default: `0`)
+| `GLB_RT_OVERFLOW_ITERS` | The maximum number of iterations waiting for the overflow to reach the desired value. <br> (Default: `50`) |
+| `GLB_RT_ANT_ITERS` | The maximum number of iterations for global router repair_antenna. This option is only available in `DIODE_INSERTION_STRATEGY` = `3`. <br> (Default: `3`) |
+| `GLB_RT_ESTIMATE_PARASITICS` | Specifies whether or not to run STA after global routing using OpenROAD's estimate_parasitics -global_routing and generates reports under `logs/routing`. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `GLB_RT_MAX_DIODE_INS_ITERS` | Controls the maximum number of iterations at which re-running Fastroute for diode insertion stops. Each iteration ARC detects the violations and FastRoute fixes them by inserting diodes, then producing the new DEF. The number of antenna violations is compared with the previous iteration and if they are equal or the number is greater the iterations stop and the DEF from the previous iteration is used in the rest of the flow. If the current antenna violations reach zero, the current def will be used and the iterations will not continue. This option is only available in DIODE_INSERTION_STRATEGY = `3`. <br> (Default: `1`) |
+| `GLB_RT_OBS` | Specifies custom obstruction to be added prior to global routing. Comma separated list of layer and coordinates: `layer llx lly urx ury`.<br> (Example: `li1 0 100 1000 300, met5 0 0 1000 500`) <br> (Default: unset) |
+| `GLB_RESIZER_TIMING_OPTIMIZATIONS` | Specifies whether resizer timing optimizations should be performed after global routing or not. 0 = false, 1 = true <br> (Default: `1`)
+| `GLB_RESIZER_MAX_WIRE_LENGTH` | Specifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns. <br> (Default: `0`)|
+| `GLB_RESIZER_MAX_SLEW_MARGIN` | Specifies a margin for the slews. <br> (Default: `10`)|
+| `GLB_RESIZER_MAX_CAP_MARGIN` | Specifies a margin for the capacitances. <br> (Default: `10`)|
+| `GLB_RESIZER_HOLD_SLACK_MARGIN` | Specifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix. <br> (Default: `0.1ns`)|
+| `GLB_RESIZER_SETUP_SLACK_MARGIN` | Specifies a time margin for the slack when fixing setup violations. <br> (Default: `0.05ns`)|
+| `GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `50`)|
+| `GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `50`)|
+| `GLB_RESIZER_ALLOW_SETUP_VIOS` | Allows setup violations when fixing hold. <br> (Default: `0`)|
+| `GLB_OPTIMIZE_MIRRORING` | Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens after Routing timing optimization. This pass will mirror the cells whenever possible to optimize the design. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
+| `GLB_RT_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. <br> 1 = most reduction, 0 = least reduction <br> (Default: `0.3`)|
+| `GLB_RT_MACRO_EXTENSION` | Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches. <br> (Default: `0`) |
+| `DRT_MIN_LAYER` | An optional override to the lowest layer used in detailed routing. For example, in sky130, you may want global routing to avoid li1, but let detailed routing use li1 if it has to. <br> (Default: `RT_MIN_LAYER`)|
+| `DRT_MAX_LAYER` | An optional override to the highest layer used in detailed routing. <br> (Default: `RT_MAX_LAYER`)|
+| `DRT_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
+| `ROUTING_OPT_ITERS` |**Deprecated: Use DRT_OPT_ITERS**: Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
+
+#### Deprecated Layer Adjustment Variables
+These variables worked initially, but they were too sky130 specific and will be removed. Currently, if you define them in your design, they'll be concatenated into GLB_RT_LAYER_ADJUSTMENTS, but it's recommended to update your configuration to use `GLB_RT_LAYER_ADJUSTMENTS`, which is defined in the PDK.
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `GLB_RT_L1_ADJUSTMENT` | **Deprecated**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in sky130A. Values range from 0 to 1 <br> (Default: `0.99`) |
+| `GLB_RT_L2_ADJUSTMENT` | **Deprecated**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in sky130A. Values range from 0 to 1 <br> (Default: `0`) |
+| `GLB_RT_L3_ADJUSTMENT` | **Deprecated**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met2 in sky130A. Values range from 0 to 1 <br> (Default: `0`) |
+| `GLB_RT_L4_ADJUSTMENT` | **Deprecated**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met3 in sky130A. Values range from 0 to 1 <br> (Default: `0`) |
+| `GLB_RT_L5_ADJUSTMENT` | **Deprecated**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met4 in sky130A. Values range from 0 to 1 <br> (Default: `0`) |
+| `GLB_RT_L6_ADJUSTMENT` | **Deprecated**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met5 in sky130A. Values range from 0 to 1 <br> (Default: `0`) |
+
+#### Deprecated Min/Max Layer Variables
+These variables worked initially, but they were too sky130 specific and will be removed. Currently, if you define them in your design, they'll be translated to the correct variables, `RT_{MIN/MAX}_LAYER` and `RT_CLOCK_{MIN/MAX}_LAYER`.
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `GLB_RT_MINLAYER` | **Deprecated**: The number of lowest layer to be used in routing. <br> (Default: `1`)|
+| `GLB_RT_MAXLAYER` | **Deprecated**: The number of highest layer to be used in routing. <br> (Default: `6`)|
+| `GLB_RT_CLOCK_MINLAYER` | **Deprecated**: The number of lowest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MINLAYER`)|
+| `GLB_RT_CLOCK_MAXLAYER` | **Deprecated**: The number of highest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MAXLAYER`)|
+
+#### Removed
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `GLB_RT_UNIDIRECTIONAL` | **Removed**: Allow unidirectional routing. 0 = false, 1 = true <br> (Default: `1`) |
+| `GLB_RT_TILES` | **Removed**: The size of the GCELL used by Fastroute during global routing. <br> (Default: `15`) |
+
+### RC Extraction
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `SPEF_EXTRACTOR` | Specifies which spef extractor to use. Values: `openrcx` or (removed: `def2spef`). <br> (Default: `openrcx`) |
+| `RCX_MERGE_VIA_WIRE_RES` | Specifies whether to merge the via resistance with the wire resistance or separate it from the wire resistance. 1 = Merge via resistance, 0 = Separate via resistance <br> (Default: `1`)|
+| `SPEF_WIRE_MODEL` | Specifies the wire model used in SPEF extraction. Options are `L` or `Pi` <br> (Default: `L`) |
+| `SPEF_EDGE_CAP_FACTOR` | Specifies the edge capacitance factor used in SPEF extraction. Ranges from 0 to 1 <br> (Default: `1`) |
+| `RCX_CORNER_COUNT` | **Removed**: Specifies the number of corners used during the parasitic extractions. <br> (Default: `1`)|
+| `RCX_MAX_RESISTANCE` | **Removed**: Specifies the maximum threshold value for combining resistors in series. Resistors in series are combined up to this value. Units in ohms <br> (Default: `50`)|
+| `RCX_COUPLING_THRESHOLD` | **Removed**: Specifies the maximum threshold value for grounding coupling values. Coupling values below this threshold are grounded. Units in fF <br> (Default: `0.1`)|
+| `RCX_CC_MODEL` | **Removed**: Specifies the maximum number of tracks on the same routing level. Coupling is calculated within the `RCX_CC_MODEL` distance. <br> (Default: `10`)|
+| `RCX_CONTEXT_DEPTH` | **Removed**: Specifies the number of levels considered when calculating the capacitance. <br> (Default: `5`)|
+
+### Magic
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `MAGIC_PAD` | A flag to pad the views generated by magic (.mag, .lef, .gds) with one site. 1 = Enabled, 0 = Disabled <br> (Default: `0` )|
+| `MAGIC_ZEROIZE_ORIGIN` | A flag to move the layout such that it's origin in the lef generated by magic is 0,0. 1 = Enabled, 0 = Disabled <br> (Default: `1` )|
+| `MAGIC_GENERATE_GDS` | A flag to generate gds view via magic . 1 = Enabled, 0 = Disabled <br> (Default: `1` )|
+| `MAGIC_GENERATE_LEF` | A flag to generate lef view via magic . 1 = Enabled, 0 = Disabled <br> (Default: `1` )|
+| `MAGIC_GENERATE_MAGLEF` | A flag to generate maglef view via magic . 1 = Enabled, 0 = Disabled <br> (Default: `1` )|
+| `MAGIC_WRITE_FULL_LEF` | A flag to specify whether or not the output LEF should include all shapes inside the macro or an abstracted view of the macro lef view via magic . 1 = Full View, 0 = Abstracted View <br> (Default: `0` )|
+| `MAGIC_DRC_USE_GDS` | A flag to choose whether to run the magic DRC checks on GDS or not. If not, then the checks will be done on the DEF/LEF. 1 = GDS, 0 = DEF/LEF <br> (Default: `1` )|
+| `MAGIC_EXT_USE_GDS` | A flag to choose whether to run the magic extractions on GDS or DEF/LEF. If GDS was used Device Level LVS will be run. Otherwise, blackbox LVS will be run. 1 = GDS, 0 = DEF/LEF <br> (Default: `0` )|
+| `MAGIC_INCLUDE_GDS_POINTERS` | A flag to choose whether to include GDS pointers in the generated mag files or not. 1 = Enabled, 0 = Disabled <br> (Default: `0` )|
+| `MAGIC_DISABLE_HIER_GDS` | A flag to disable cif hier and array during GDS-II writing.* 1=Enabled `<so this hier gds will be disabled>`, 0=Disabled `<so this hier gds will be enabled>`. <br> (Default: `1` )|
+
+> * Tim Edwards's Explanation on disabling hier gds: The following is an explanation by Tim Edwards, provided in a slack thread, on how this affects the GDS writing process: "Magic can take a very long time writing out GDS while checking hierarchical interactions in a standard cell layout. If your design is all digital, I recommend using "gds *hier write disable" before "gds write" so that it does not try to resolve hierarchical interactions (since by definition, standard cells are designed to just sit next to each other without creating DRC issues). That can actually make the difference between a 20 hour GDS write and a 2 minute GDS write. For a standard cell design that takes up the majority of the user space, a > 24 hour write time (without disabling the hierarchy checks) would not surprise me."
+
+### LVS
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `LVS_INSERT_POWER_PINS` | Enables power pins insertion before running lvs. 1 = Enabled, 0 = Disabled <br> (Default: `1` )|
+| `LVS_CONNECT_BY_LABEL` | Enables connections by label in LVS by skipping `extract unique` in magic extractions. <br> Default: `0` |
+| `YOSYS_REWRITE_VERILOG` | Enables yosys to rewrite the verilog before LVS producing a canonical verilog netlist with verbose wire declarations. This flag will be ignored if `LEC_ENABLE` is 1, and it will be rewritten anyways. 1 = Enabled, 0 = Disabled <br> (Default: `0` ) |
+
+### Misc
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `PDK` | Specifies the process design kit (PDK). <br> (Default: `sky130A` )|
+| `STD_CELL_LIBRARY` | Specifies the standard cell library to be used under the specified PDK. <br> (Default: `sky130_fd_sc_hd` )|
+| `STD_CELL_LIBRARY_OPT` | Specifies the standard cell library to be used during resizer optimizations. <br> (Default: `$STD_CELL_LIBRARY` )|
+| `PDK_ROOT` | Specifies the folder path of the PDK. It searches for a `config.tcl` in `$PDK_ROOT/$PDK/libs.tech/openlane/` directory and at least have one standard cell library config defined in `$PDK_ROOT/$PDK/libs.tech/openlane/$STD_CELL_LIBRARY`. |
+| `CELL_PAD` | Cell padding; increases the width of cells. <br> (Default: `4` microns -- 4 sites)|
+| `DIODE_PADDING` | Diode cell padding; increases the width of diode cells during placement checks. <br> (Default: `2` microns -- 2 sites)|
+| `MERGED_LEF_UNPADDED` | Points to `merged_unpadded.lef` by default. it contains the technology LEF for the used STD_CELL_LIBRARY merged with the LEF file for all the cells. |
+| `MERGED_LEF` | points to `merged.lef`, which is `merged_unpadded.lef` but with cell padding. This is controlled by CELL_PAD. |
+| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
+| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells` and if it's not found, then the original liberty will be used as is. In other words, `DRC_EXCLUDE_CELL_LIST` contain the only excluded cell list in timing optimizations. |
+| `EXTRA_LEFS` | Specifies LEF files of pre-hardened macros to be merged in the design currently getting hardened |
+| `EXTRA_GDS_FILES` | Specifies GDS files of pre-hardened macros to be merged in the design currently getting hardened |
+| `SAVE_FINAL_VIEWS` | Specifies whether OpenLane should save all final views to a specific folder or not. (Default: `0`) |
+| `TEST_MISMATCHES` | Test for mismatches between the OpenLane tool versions and the current environment. `all` tests all mismatches. `tools` tests all except the PDK. `pdk` only tests the PDK. `none` disables the check.<br> (Default: `all`) |
+| `QUIT_ON_MISMATCHES` | Whether to halt the flow execution or not if mismatches are found. (Default: `1`) |
+
+### Flow control
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `USE_GPIO_PADS` | Decides whether or not to use the gpio pads in routing by merging their LEF file set in `::env(USE_GPIO_ROUTING_LEF)` and blackboxing their verilog modules set in `::env(GPIO_PADS_VERILOG)`. 1=Enabled, 0=Disabled. <br> (Default: `0`) |
+| `LEC_ENABLE` | Enables logic verification using yosys, for comparing each netlist at each stage of the flow with the previous netlist and verifying that they are logically equivalent. Warning: this will increase the runtime significantly. 1 = Enabled, 0 = Disabled <br> (Default: `0`)|
+| `RUN_ROUTING_DETAILED` | Enables detailed routing. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `RUN_LVS` | Enables running LVS. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `PRIMARY_SIGNOFF_TOOL` | Determines whether `magic` or `klayout` is the primary signoff tool. <br> (Default: `magic`) |
+| `RUN_MAGIC` | Enables running magic and GDSII streaming. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `RUN_MAGIC_DRC` | Enables running magic DRC on GDS-II produced by magic. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `RUN_KLAYOUT` | Enables running Klayout and GDSII streaming. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `RUN_KLAYOUT_DRC` | Enables running Klayout DRC on GDS-II produced by magic. 1 = Enabled, 0 = Disabled <br> (Default: `0`)|
+| `KLAYOUT_DRC_KLAYOUT_GDS` | Enables running Klayout DRC on GDS-II produced by Klayout. 1 = Enabled, 0 = Disabled <br> (Default: `0`)|
+| `RUN_KLAYOUT_XOR` | Enables running Klayout XOR on 2 GDS-IIs, the defaults are the one produced by magic vs the one produced by klayout. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `KLAYOUT_XOR_GDS` | If `RUN_KLAYOUT_XOR` is enabled, this will enable producing a GDS output from the XOR along with it's PNG export. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `KLAYOUT_XOR_XML` | If `RUN_KLAYOUT_XOR` is enabled, this will enable producing an XML output from the XOR. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `TAKE_LAYOUT_SCROT` | Enables running Klayout to take a PNG screenshot of the produced layout (currently configured to run on the results of each stage).1 = Enabled, 0 = Disabled <br> (Default: `0`)|
+| `TAP_DECAP_INSERTION` | Enables tap and decap cells insertion after floorplanning (if enabled) .1 = Enabled, 0 = Disabled <br> (Default: `1`) |
+| `DIODE_INSERTION_STRATEGY` | Specifies the insertion strategy of diodes to be used in the flow. 0 = No diode insertion, 1 = Spray diodes, 2 = insert fake diodes and replace them with real diodes if needed. 3= use FastRoute Antenna Avoidance flow, 4 = Use Sylvian's Custom Script for diode insertion on design pins and smartly inserting needed diodes inside the design, 5 = a mix of strategy 2 and 4. <br> (Default: `3`) |
+| `WIDEN_SITE` | Specifies the new virtual width of the site to be used in all stages up to diode insertion, then switched back to the original site width. It can be either a factor or an absolute value controlled by `WIDEN_SITE_IS_FACTOR` <br> (Default: `1`) |
+| `WIDEN_SITE_IS_FACTOR` | Specifies whether the given `WIDEN_SITE` should be treated as a factor or an absolute value. 0 = absolute, 1 = factor <br> (Default: `1`) |
+| `USE_ARC_ANTENNA_CHECK` | Specifies whether to use the openroad ARC antenna checker or magic antenna checker. 0=magic antenna checker, 1=ARC OR antenna checker <br> (Default: `1`)
+| `RUN_SPEF_EXTRACTION` | Specifies whether or not to run SPEF extraction on the routed DEF. 1=enabled 0=disabled <br> Default: `1` |
+| `GENERATE_FINAL_SUMMARY_REPORT` | Specifies whether or not to generate a final summary report after the run is completed. Check command `generate_final_summary_report`. 1=enabled 0=disabled <br> Default: `1` |
+| `MAGIC_CONVERT_DRC_TO_RDB` | Specifies whether or not generate a Calibre RDB out of the magic.drc report. Result is saved in `<run_path>/results/magic/`. 1=enabled 0=disabled <br> Default: `1`|
+| `RUN_CVC` | Runs CVC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. Thus, it controls the command `run_lef_cvc`. 1=Enabled, 0=Disabled. <br> Default: `1` |
+
+### Checkers
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `CHECK_UNMAPPED_CELLS` | Checks if there are unmapped cells after synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `CHECK_ASSIGN_STATEMENTS` | Checks for assign statement in the generated gate level netlist and aborts of any was found.1 = Enabled, 0 = Disabled <br> (Default: `0`)|
+| `QUIT_ON_TR_DRC` | Checks for DRC violations after routing and exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `QUIT_ON_MAGIC_DRC` | Checks for DRC violations after magic DRC is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `QUIT_ON_ILLEGAL_OVERLAPS` | Checks for illegal overlaps during magic extraction. In some cases, these imply existing undetected shorts in the design. It also exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+| `QUIT_ON_LVS_ERROR` | Checks for LVS errors after netgen LVS is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
+
+
+[0]: ./../designs/spm/pin_order.cfg
diff --git a/openlane/configuration/checkers.tcl b/openlane/configuration/checkers.tcl
new file mode 100755
index 0000000..bc5802a
--- /dev/null
+++ b/openlane/configuration/checkers.tcl
@@ -0,0 +1,41 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Synthesis
+set ::env(CHECK_ASSIGN_STATEMENTS) 0
+set ::env(CHECK_UNMAPPED_CELLS) 1
+
+# Static timing analysis
+set ::env(QUIT_ON_TIMING_VIOLATIONS) 1
+set ::env(QUIT_ON_HOLD_VIOLATIONS) 1
+set ::env(QUIT_ON_SETUP_VIOLATIONS) 1
+
+# Floor Planning
+
+
+# Placement
+
+
+# Routing
+set ::env(QUIT_ON_TR_DRC) 1
+
+# Magic
+# This is disabled by default for now until we are 100% sure we want to make this
+# shift in flow dynamics, as it will affect the current benchmarks.
+set ::env(QUIT_ON_MAGIC_DRC) 1
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 1
+
+# NetGen
+# This is disabled by default as it's the stage before the last, so why not do the last stage anyways.
+set ::env(QUIT_ON_LVS_ERROR) 1
diff --git a/openlane/configuration/cts.tcl b/openlane/configuration/cts.tcl
new file mode 100755
index 0000000..391bb4c
--- /dev/null
+++ b/openlane/configuration/cts.tcl
@@ -0,0 +1,24 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# cts defaults
+set ::env(CLOCK_TREE_SYNTH) 1
+set ::env(CTS_TARGET_SKEW) 200
+set ::env(CTS_TOLERANCE) 100
+set ::env(CTS_SINK_CLUSTERING_SIZE) 25
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 50
+set ::env(CTS_REPORT_TIMING) 1
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) 0
+set ::env(CTS_DISABLE_POST_PROCESSING) 0
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) 0
diff --git a/openlane/configuration/extraction.tcl b/openlane/configuration/extraction.tcl
new file mode 100644
index 0000000..7fd0c5a
--- /dev/null
+++ b/openlane/configuration/extraction.tcl
@@ -0,0 +1,25 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Options are rcx/def2spef
+set ::env(SPEF_EXTRACTOR) "openrcx"
+
+# OpenRCX default condigurations
+set ::env(RCX_MERGE_VIA_WIRE_RES) 1
+
+# DEF2SPEF default configurations
+set ::env(SPEF_WIRE_MODEL) "L"
+set ::env(SPEF_EDGE_CAP_FACTOR) 1
+
+
diff --git a/openlane/configuration/floorplan.tcl b/openlane/configuration/floorplan.tcl
new file mode 100755
index 0000000..80b145a
--- /dev/null
+++ b/openlane/configuration/floorplan.tcl
@@ -0,0 +1,56 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Floorplan defaults
+set ::env(FP_SIZING) relative
+set ::env(FP_CORE_UTIL) 50
+set ::env(FP_CORE_MARGIN) 0
+set ::env(FP_ASPECT_RATIO) 1
+
+set ::env(FP_PDN_VOFFSET) 16.32
+set ::env(FP_PDN_VPITCH) 153.6
+set ::env(FP_PDN_HOFFSET) 16.65
+set ::env(FP_PDN_HPITCH) 153.18
+
+set ::env(FP_PDN_AUTO_ADJUST) 1
+
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(FP_PDN_ENABLE_RAILS) 1
+
+set ::env(FP_PDN_CHECK_NODES) 1
+set ::env(FP_PDN_IRDROP) 1
+
+set ::env(FP_IO_MODE) 1; # 0 matching mode - 1 random equidistant mode
+set ::env(FP_IO_HLENGTH) 4
+set ::env(FP_IO_VLENGTH) 4
+set ::env(FP_IO_VEXTEND) -1
+set ::env(FP_IO_HEXTEND) -1
+set ::env(FP_IO_VTHICKNESS_MULT) 2
+set ::env(FP_IO_HTHICKNESS_MULT) 2
+set ::env(FP_IO_MIN_DISTANCE) 3
+set ::env(FP_IO_UNMATCHED_ERROR) 1
+
+set ::env(BOTTOM_MARGIN_MULT) 4
+set ::env(TOP_MARGIN_MULT) 4
+set ::env(LEFT_MARGIN_MULT) 12
+set ::env(RIGHT_MARGIN_MULT) 12
+
+set ::env(FP_PDN_HORIZONTAL_HALO) 10
+set ::env(FP_PDN_VERTICAL_HALO) $::env(FP_PDN_HORIZONTAL_HALO)
+set ::env(FP_TAP_HORIZONTAL_HALO) 10
+set ::env(FP_TAP_VERTICAL_HALO) $::env(FP_TAP_HORIZONTAL_HALO)
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1
+set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
+
+set ::env(DESIGN_IS_CORE) 1
diff --git a/openlane/configuration/general.tcl b/openlane/configuration/general.tcl
new file mode 100755
index 0000000..d7e92a3
--- /dev/null
+++ b/openlane/configuration/general.tcl
@@ -0,0 +1,95 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# default pdk/scl
+if { ![info exists ::env(PDK)] } {
+ set ::env(PDK) "sky130A"
+}
+if { ![info exists ::env(STD_CELL_LIBRARY)] } {
+ set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+}
+
+set ::env(USE_GPIO_PADS) 0
+
+if { ![info exists ::env(QUIT_ON_MISMATCHES)] } {
+ set ::env(QUIT_ON_MISMATCHES) {1}
+}
+if { ![info exists ::env(TEST_MISMATCHES)] } {
+ set ::env(TEST_MISMATCHES) {all}
+}
+
+# Flow control defaults
+set ::env(RUN_LVS) 1
+
+set ::env(LEC_ENABLE) 0
+set ::env(YOSYS_REWRITE_VERILOG) 0
+
+set ::env(PRIMARY_SIGNOFF_TOOL) magic
+
+set ::env(RUN_MAGIC) 1
+set ::env(RUN_MAGIC_DRC) 1
+set ::env(MAGIC_PAD) 0
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+set ::env(MAGIC_GENERATE_GDS) 1
+set ::env(MAGIC_GENERATE_LEF) 1
+set ::env(MAGIC_GENERATE_MAGLEF) 1
+set ::env(MAGIC_WRITE_FULL_LEF) 0
+set ::env(MAGIC_DRC_USE_GDS) 1
+set ::env(MAGIC_EXT_USE_GDS) 0
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) 0
+set ::env(MAGIC_DISABLE_HIER_GDS) 1
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) 1
+
+set ::env(KLAYOUT_XOR_GDS) 1
+set ::env(KLAYOUT_XOR_XML) 1
+
+set ::env(RUN_ROUTING_DETAILED) 1
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(RUN_KLAYOUT) 1
+set ::env(TAKE_LAYOUT_SCROT) 0
+set ::env(RUN_KLAYOUT_DRC) 0
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) 0
+set ::env(RUN_KLAYOUT_XOR) 1
+set ::env(USE_ARC_ANTENNA_CHECK) 1
+
+set ::env(FILL_INSERTION) 1
+set ::env(TAP_DECAP_INSERTION) 1
+
+set ::env(WIDEN_SITE) 1
+set ::env(WIDEN_SITE_IS_FACTOR) 1
+
+set ::env(RUN_SPEF_EXTRACTION) 1
+set ::env(RUN_CVC) 1
+
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1
+
+
+# 0: no diodes
+# 1: spray inputs with diodes
+# 2: spray inputs with fake diodes first then fix up the violators with real ones
+# 3: use FR Antenna Avoidance flow
+# 4: Spray diodes on design pins, and add diodes where they need to be added for each macro.
+# 5: Same as 2 but behaves like 4.
+set ::env(DIODE_INSERTION_STRATEGY) 3
+
+set ::env(STA_REPORT_POWER) {1}
+set ::env(SAVE_FINAL_VIEWS) {1}
+
+## ECO Flow
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_STARTED) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_SKIP_PIN) {1}
\ No newline at end of file
diff --git a/openlane/configuration/lvs.tcl b/openlane/configuration/lvs.tcl
new file mode 100755
index 0000000..aff458b
--- /dev/null
+++ b/openlane/configuration/lvs.tcl
@@ -0,0 +1,3 @@
+set ::env(RUN_LVS) 1
+set ::env(LVS_INSERT_POWER_PINS) 1
+set ::env(LVS_CONNECT_BY_LABEL) 0
diff --git a/openlane/configuration/placement.tcl b/openlane/configuration/placement.tcl
new file mode 100755
index 0000000..6395ec6
--- /dev/null
+++ b/openlane/configuration/placement.tcl
@@ -0,0 +1,42 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Placement defaults
+set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(PL_ROUTABILITY_DRIVEN) 1
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 0
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_SKIP_INITIAL_PLACEMENT) 0
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) 0
+set ::env(PL_ESTIMATE_PARASITICS) 1
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 0
+set ::env(PL_OPTIMIZE_MIRRORING) 1
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 1
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 1
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 20
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 20
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1
+set ::env(PL_RESIZER_TIE_SEPERATION) 0
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) 0.05
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 50
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) 50
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 0
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 1
+set ::env(PL_MAX_DISPLACEMENT_X) 500
+set ::env(PL_MAX_DISPLACEMENT_Y) 100
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MACRO_CHANNEL) {0 0}
diff --git a/openlane/configuration/routing.tcl b/openlane/configuration/routing.tcl
new file mode 100755
index 0000000..c5dd180
--- /dev/null
+++ b/openlane/configuration/routing.tcl
@@ -0,0 +1,52 @@
+# Copyright 2020-2021 Efabless Corporation
+# ECO Flow Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Routing defaults
+if { ![info exists ::env(ROUTING_CORES)] } {
+ set ::env(ROUTING_CORES) 2
+}
+
+set ::env(GLOBAL_ROUTER) fastroute
+set ::env(DETAILED_ROUTER) tritonroute
+
+set ::env(GLB_OPTIMIZE_MIRRORING) 1
+
+set ::env(GLB_RT_ADJUSTMENT) 0.3
+set ::env(GLB_RT_ALLOW_CONGESTION) 0
+set ::env(GLB_RT_OVERFLOW_ITERS) 50
+set ::env(GLB_RT_ANT_ITERS) 3
+set ::env(GLB_RT_ESTIMATE_PARASITICS) 1
+set ::env(GLB_RT_MACRO_EXTENSION) 0
+
+set ::env(DIODE_PADDING) 2
+
+# GLB_RT_MAX_DIODE_INS_ITERS is set to 1 because of the bulk testing we're running (as it will speed-up the runtime for big designs).
+# However, the user is advised to set it up to 5 or more, in case of running a specific design.
+# It is capable to detect any divergence, so, you'll probably end up with the lowest # of Antenna violations possible.
+# Check the configuration/README.md for more.
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 1
+
+set ::env(DRT_OPT_ITERS) 64
+
+# GLB Resizer
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) 0
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 10
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) 10
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.1
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) 0.05
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) 50
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) 50
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 0
\ No newline at end of file
diff --git a/openlane/configuration/synthesis.tcl b/openlane/configuration/synthesis.tcl
new file mode 100755
index 0000000..3a7149e
--- /dev/null
+++ b/openlane/configuration/synthesis.tcl
@@ -0,0 +1,35 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Synth defaults
+set ::env(SYNTH_BIN) yosys
+set ::env(SYNTH_SCRIPT) $::env(SCRIPTS_DIR)/yosys/synth.tcl
+set ::env(SYNTH_NO_FLAT) 0
+set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25
+set ::env(SYNTH_CLOCK_TRANSITION) 0.15
+set ::env(SYNTH_TIMING_DERATE) 0.05
+set ::env(SYNTH_SHARE_RESOURCES) 1
+set ::env(SYNTH_BUFFERING) 1
+set ::env(SYNTH_SIZING) 0
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_ADDER_TYPE) "YOSYS"
+set ::env(CLOCK_BUFFER_FANOUT) 16
+set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+set ::env(SYNTH_TOP_LEVEL) 0
+set ::env(SYNTH_FLAT_TOP) 0
+set ::env(IO_PCT) 0.2
+set ::env(SYNTH_EXTRA_MAPPING_FILE) ""
+
+set ::env(BASE_SDC_FILE) $::env(OPENLANE_ROOT)/scripts/base.sdc
diff --git a/openlane/dependencies/arch/run_time.txt b/openlane/dependencies/arch/run_time.txt
new file mode 100644
index 0000000..0057c26
--- /dev/null
+++ b/openlane/dependencies/arch/run_time.txt
@@ -0,0 +1,40 @@
+https://aur.archlinux.org/tcllib.git
+
+autoconf
+bison
+cairo
+clang
+curl
+eigen
+flex
+gawk
+gcc
+gdb
+gettext
+git
+graphviz
+help2man
+klayout
+libffi
+libsm
+libx11
+make
+ncurses
+neovim
+ninja
+patch
+pcre2
+python
+python-pip
+readline
+spdlog
+strace
+swig
+tcl
+tcsh
+texinfo
+tk
+wget
+xdot
+xorg-server-xvfb
+zlib
diff --git a/openlane/dependencies/centos-7/compile_time.txt b/openlane/dependencies/centos-7/compile_time.txt
new file mode 100644
index 0000000..595b440
--- /dev/null
+++ b/openlane/dependencies/centos-7/compile_time.txt
@@ -0,0 +1,72 @@
+devtoolset-8
+devtoolset-8-libatomic-devel
+
+llvm-toolset-7.0-clang
+llvm-toolset-7.0-libomp-devel
+
+Xvfb
+autoconf
+automake
+bison
+boost169-devel
+boost169-static
+bzip2
+cairo
+cairo-devel
+clang
+csh
+curl
+flex
+gawk
+gcc
+gdb
+gettext
+gettext-devel
+git
+glibc-static
+graphviz
+help2man
+libcurl-devel
+libSM
+libX11-devel
+libXext
+libXft
+libffi
+libffi-devel
+libgomp
+libjpeg-turbo-devel
+libstdc++
+libstdc++-static
+libxml2-devel
+libxslt-devel
+make
+mesa-libGLU-devel
+ncurses-devel
+ninja-build
+patch
+pcre-devel
+python36-devel
+python36-libs
+qt5-qtbase-devel
+qt5-qtmultimedia-devel
+qt5-qtxmlpatterns-devel
+qt5-qtsvg-devel
+qt5-qttools-devel
+readline-devel
+ruby-devel
+strace
+spdlog-devel
+swig3
+tcl
+tcl-devel
+tcl-tclreadline-devel
+tcllib
+tclx
+texinfo
+tk
+tk-devel
+vim-common
+wget
+which
+zlib-devel
+zlib-static
diff --git a/openlane/dependencies/centos-7/precompile_time.txt b/openlane/dependencies/centos-7/precompile_time.txt
new file mode 100644
index 0000000..98d7827
--- /dev/null
+++ b/openlane/dependencies/centos-7/precompile_time.txt
@@ -0,0 +1,2 @@
+https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm
+centos-release-scl
\ No newline at end of file
diff --git a/openlane/dependencies/centos-7/run_time.txt b/openlane/dependencies/centos-7/run_time.txt
new file mode 100644
index 0000000..c99d303
--- /dev/null
+++ b/openlane/dependencies/centos-7/run_time.txt
@@ -0,0 +1,56 @@
+alsa-lib
+cairo
+gdb
+gettext
+git
+libffi
+libgomp
+libjpeg
+libSM
+libXcursor
+libXext
+libXft
+libXinerama
+libXrandr
+libyaml
+llvm-toolset-7-libomp
+make
+mesa-libGLU
+patch
+pciutils
+pciutils-libs
+perl
+perl-Switch
+python36
+python36-pip
+python36-tkinter
+qt
+qt5-qtbase
+qt5-qtimageformats
+qt5-qtmultimedia
+qt5-qtxmlpatterns
+qt5-qtsvg
+qt5-qttools
+qt5-qttools-libs-designer
+qt5-qttools-libs-designercomponents
+qt5-qttools-libs-help
+qt-settings
+qt-x11
+ruby
+rubygem-io-console
+rubygem-json
+rubygem-psych
+rubygem-rdoc
+rubygems
+ruby-irb
+ruby-libs
+strace
+tcl
+tcllib
+tcl-tclreadline-devel
+tclx
+tk
+wget
+which
+Xvfb
+zlib
\ No newline at end of file
diff --git a/openlane/dependencies/env_info.py b/openlane/dependencies/env_info.py
new file mode 100644
index 0000000..895d5a2
--- /dev/null
+++ b/openlane/dependencies/env_info.py
@@ -0,0 +1,179 @@
+#!/usr/bin/env python3
+
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import sys
+import json
+import platform
+import subprocess
+
+try:
+ from typing import Optional
+except ImportError:
+ pass
+
+
+class StringRepresentable(object):
+ def __str__(self):
+ return str(self.__dict__)
+
+ def __repr__(self):
+ return str(self.__dict__)
+
+
+class ContainerInfo(StringRepresentable):
+ engine = "UNKNOWN" # type: str
+ version = "UNKNOWN" # type: str
+ conmon = False # type: bool
+ rootless = False # type : bool
+
+ def __init__(self):
+ self.engine = "UNKNOWN"
+ self.version = "UNKNOWN"
+ self.conmon = False
+ self.rootless = False
+
+ @staticmethod
+ def get():
+ # type: () -> Optional['ContainerInfo']
+ try:
+ cinfo = ContainerInfo()
+
+ info = ""
+ try:
+ info = subprocess.check_output(
+ ["docker", "info", "--format", "{{json .}}"]
+ ).decode("utf8")
+ except Exception:
+ return None
+
+ try:
+ info = json.loads(info)
+ except Exception:
+ raise Exception("Docker info was not valid JSON.")
+
+ if info.get("host") is not None:
+ if info["host"].get("conmon") is not None:
+ cinfo.conmon = True
+ if (
+ info["host"].get("remoteSocket") is not None
+ and "podman" in info["host"]["remoteSocket"]["path"]
+ ):
+ cinfo.engine = "podman"
+
+ cinfo.version = info["version"]["Version"]
+ elif (
+ info.get("Docker Root Dir") is not None
+ or info.get("DockerRootDir") is not None
+ ):
+ cinfo.engine = "docker"
+
+ # Get Version
+ try:
+ version_output = (
+ subprocess.check_output(["docker", "--version"])
+ .decode("utf8")
+ .strip()
+ )
+ cinfo.version = re.split(r"\s", version_output)[2].strip(",")
+ except Exception:
+ print("Could not extract Docker version.", file=sys.stderr)
+
+ security_options = info.get("SecurityOptions")
+ for option in security_options:
+ if "rootless" in option:
+ cinfo.rootless = True
+
+ return cinfo
+ except Exception as e:
+ print(e, file=sys.stderr)
+ return None
+
+
+class OSInfo(StringRepresentable):
+ kernel = "" # type: str
+ python_version = "" # type: str
+ kernel_version = "" # type: str
+ distro = None # type: Optional[str]
+ distro_version = None # type: Optional[str]
+ container_info = None # type: Optional[ContainerInfo]
+
+ def __init__(self):
+ self.kernel = platform.system()
+ self.python_version = platform.python_version()
+ self.kernel_version = (
+ platform.release()
+ ) # Unintuitively enough, it's the kernel's release
+ self.distro = None
+ self.distro_version = None
+ self.container_info = None
+
+ @staticmethod
+ def get():
+ # type: () -> Optional['OSInfo']
+ osinfo = OSInfo()
+
+ if osinfo.kernel not in ["Linux", "Darwin"]:
+ print("Platform %s is unsupported." % osinfo.name, file=sys.stderr)
+ return None
+
+ if osinfo.kernel == "Darwin":
+ osinfo.distro = "macOS"
+ osinfo.distro_version = platform.mac_ver()[0]
+ osinfo.kernel_version = platform.release()
+ osinfo.package_manager = None
+ try:
+ subprocess.check_output(["brew", "--version"])
+ osinfo.package_manager = "brew"
+ except Exception:
+ pass
+
+ if osinfo.kernel == "Linux":
+ os_release = ""
+ try:
+ os_release += open("/etc/lsb-release").read()
+ except Exception:
+ pass
+ try:
+ os_release += open("/etc/os-release").read()
+ except Exception:
+ pass
+
+ if os_release.strip() != "":
+ config = {}
+ for line in os_release.split("\n"):
+ if line.strip() == "":
+ continue
+ key, value = line.split("=")
+ value = value.strip('"')
+
+ config[key] = value
+
+ osinfo.distro = config.get("ID") or config.get("DISTRIB_ID")
+ osinfo.distro_version = config.get("VERSION_ID") or config.get(
+ "DISTRIB_RELEASE"
+ )
+
+ else:
+ print("Failed to get distribution info.", file=sys.stderr)
+
+ osinfo.container_info = ContainerInfo.get()
+
+ return osinfo
+
+
+if __name__ == "__main__":
+ print(OSInfo.get())
diff --git a/openlane/dependencies/get_tag.py b/openlane/dependencies/get_tag.py
new file mode 100755
index 0000000..be718d6
--- /dev/null
+++ b/openlane/dependencies/get_tag.py
@@ -0,0 +1,79 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import subprocess
+
+
+class NoGitException(Exception):
+ pass
+
+
+def get_tag() -> str:
+ try:
+ if os.path.exists("/git_version"):
+ return open("/git_version").read().strip()
+
+ try:
+ subprocess.run(
+ ["git", "status"], stdout=subprocess.PIPE, stderr=subprocess.PIPE
+ )
+ except FileNotFoundError:
+ raise NoGitException(
+ "Cannot find the git binary. Please specify OPENLANE_IMAGE_NAME manually."
+ )
+
+ branch_name_data: subprocess.CompletedProcess = subprocess.run(
+ ["git", "branch", "--show-current"],
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE,
+ )
+
+ if branch_name_data.returncode != 0:
+ raise NoGitException(
+ f"Cannot determine git branch. Please specify OPENLANE_IMAGE_NAME manually.\nFull output: {branch_name_data.stderr.decode('utf8').strip()}"
+ )
+
+ branch_name = branch_name_data.stdout.decode("utf8").strip()
+ if branch_name != "":
+ if branch_name not in ["main", "master"]:
+ return f"{branch_name}-dev"
+
+ process_data: subprocess.CompletedProcess = subprocess.run(
+ ["git", "rev-parse", "HEAD"],
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE,
+ )
+ if process_data.returncode != 0:
+ raise NoGitException(
+ f"Failed to get commit. Please specify OPENLANE_IMAGE_NAME manually.\nFull output: {process_data.stderr.decode('utf8').strip()}"
+ )
+ return process_data.stdout.decode("utf8").strip()
+ except NoGitException as e:
+ raise e
+ except Exception as e:
+ raise Exception(
+ f"An unexpected error has occurred when trying to find the OpenLane version: {e}."
+ )
+
+
+if __name__ == "__main__":
+ try:
+ print(get_tag(), end="")
+ except Exception as e:
+ print(e, file=sys.stderr)
+ sys.exit(os.EX_UNAVAILABLE)
diff --git a/openlane/dependencies/includedyaml/LICENSE b/openlane/dependencies/includedyaml/LICENSE
new file mode 100644
index 0000000..2f1b8e1
--- /dev/null
+++ b/openlane/dependencies/includedyaml/LICENSE
@@ -0,0 +1,20 @@
+Copyright (c) 2017-2021 Ingy döt Net
+Copyright (c) 2006-2016 Kirill Simonov
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/openlane/dependencies/includedyaml/__init__.py b/openlane/dependencies/includedyaml/__init__.py
new file mode 100644
index 0000000..9bd754e
--- /dev/null
+++ b/openlane/dependencies/includedyaml/__init__.py
@@ -0,0 +1,471 @@
+from .error import *
+
+from .tokens import *
+from .events import *
+from .nodes import *
+
+from .loader import *
+from .dumper import *
+
+__version__ = "6.0"
+try:
+ from .cyaml import *
+
+ __with_libyaml__ = True
+except ImportError:
+ __with_libyaml__ = False
+
+import io
+
+# ------------------------------------------------------------------------------
+# XXX "Warnings control" is now deprecated. Leaving in the API function to not
+# break code that uses it.
+# ------------------------------------------------------------------------------
+def warnings(settings=None):
+ if settings is None:
+ return {}
+
+
+# ------------------------------------------------------------------------------
+def scan(stream, Loader=Loader):
+ """
+ Scan a YAML stream and produce scanning tokens.
+ """
+ loader = Loader(stream)
+ try:
+ while loader.check_token():
+ yield loader.get_token()
+ finally:
+ loader.dispose()
+
+
+def parse(stream, Loader=Loader):
+ """
+ Parse a YAML stream and produce parsing events.
+ """
+ loader = Loader(stream)
+ try:
+ while loader.check_event():
+ yield loader.get_event()
+ finally:
+ loader.dispose()
+
+
+def compose(stream, Loader=Loader):
+ """
+ Parse the first YAML document in a stream
+ and produce the corresponding representation tree.
+ """
+ loader = Loader(stream)
+ try:
+ return loader.get_single_node()
+ finally:
+ loader.dispose()
+
+
+def compose_all(stream, Loader=Loader):
+ """
+ Parse all YAML documents in a stream
+ and produce corresponding representation trees.
+ """
+ loader = Loader(stream)
+ try:
+ while loader.check_node():
+ yield loader.get_node()
+ finally:
+ loader.dispose()
+
+
+def load(stream, Loader):
+ """
+ Parse the first YAML document in a stream
+ and produce the corresponding Python object.
+ """
+ loader = Loader(stream)
+ try:
+ return loader.get_single_data()
+ finally:
+ loader.dispose()
+
+
+def load_all(stream, Loader):
+ """
+ Parse all YAML documents in a stream
+ and produce corresponding Python objects.
+ """
+ loader = Loader(stream)
+ try:
+ while loader.check_data():
+ yield loader.get_data()
+ finally:
+ loader.dispose()
+
+
+def full_load(stream):
+ """
+ Parse the first YAML document in a stream
+ and produce the corresponding Python object.
+
+ Resolve all tags except those known to be
+ unsafe on untrusted input.
+ """
+ return load(stream, FullLoader)
+
+
+def full_load_all(stream):
+ """
+ Parse all YAML documents in a stream
+ and produce corresponding Python objects.
+
+ Resolve all tags except those known to be
+ unsafe on untrusted input.
+ """
+ return load_all(stream, FullLoader)
+
+
+def safe_load(stream):
+ """
+ Parse the first YAML document in a stream
+ and produce the corresponding Python object.
+
+ Resolve only basic YAML tags. This is known
+ to be safe for untrusted input.
+ """
+ return load(stream, SafeLoader)
+
+
+def safe_load_all(stream):
+ """
+ Parse all YAML documents in a stream
+ and produce corresponding Python objects.
+
+ Resolve only basic YAML tags. This is known
+ to be safe for untrusted input.
+ """
+ return load_all(stream, SafeLoader)
+
+
+def unsafe_load(stream):
+ """
+ Parse the first YAML document in a stream
+ and produce the corresponding Python object.
+
+ Resolve all tags, even those known to be
+ unsafe on untrusted input.
+ """
+ return load(stream, UnsafeLoader)
+
+
+def unsafe_load_all(stream):
+ """
+ Parse all YAML documents in a stream
+ and produce corresponding Python objects.
+
+ Resolve all tags, even those known to be
+ unsafe on untrusted input.
+ """
+ return load_all(stream, UnsafeLoader)
+
+
+def emit(
+ events,
+ stream=None,
+ Dumper=Dumper,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+):
+ """
+ Emit YAML parsing events into a stream.
+ If stream is None, return the produced string instead.
+ """
+ getvalue = None
+ if stream is None:
+ stream = io.StringIO()
+ getvalue = stream.getvalue
+ dumper = Dumper(
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ )
+ try:
+ for event in events:
+ dumper.emit(event)
+ finally:
+ dumper.dispose()
+ if getvalue:
+ return getvalue()
+
+
+def serialize_all(
+ nodes,
+ stream=None,
+ Dumper=Dumper,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+):
+ """
+ Serialize a sequence of representation trees into a YAML stream.
+ If stream is None, return the produced string instead.
+ """
+ getvalue = None
+ if stream is None:
+ if encoding is None:
+ stream = io.StringIO()
+ else:
+ stream = io.BytesIO()
+ getvalue = stream.getvalue
+ dumper = Dumper(
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ encoding=encoding,
+ version=version,
+ tags=tags,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ )
+ try:
+ dumper.open()
+ for node in nodes:
+ dumper.serialize(node)
+ dumper.close()
+ finally:
+ dumper.dispose()
+ if getvalue:
+ return getvalue()
+
+
+def serialize(node, stream=None, Dumper=Dumper, **kwds):
+ """
+ Serialize a representation tree into a YAML stream.
+ If stream is None, return the produced string instead.
+ """
+ return serialize_all([node], stream, Dumper=Dumper, **kwds)
+
+
+def dump_all(
+ documents,
+ stream=None,
+ Dumper=Dumper,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+):
+ """
+ Serialize a sequence of Python objects into a YAML stream.
+ If stream is None, return the produced string instead.
+ """
+ getvalue = None
+ if stream is None:
+ if encoding is None:
+ stream = io.StringIO()
+ else:
+ stream = io.BytesIO()
+ getvalue = stream.getvalue
+ dumper = Dumper(
+ stream,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ encoding=encoding,
+ version=version,
+ tags=tags,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ sort_keys=sort_keys,
+ )
+ try:
+ dumper.open()
+ for data in documents:
+ dumper.represent(data)
+ dumper.close()
+ finally:
+ dumper.dispose()
+ if getvalue:
+ return getvalue()
+
+
+def dump(data, stream=None, Dumper=Dumper, **kwds):
+ """
+ Serialize a Python object into a YAML stream.
+ If stream is None, return the produced string instead.
+ """
+ return dump_all([data], stream, Dumper=Dumper, **kwds)
+
+
+def safe_dump_all(documents, stream=None, **kwds):
+ """
+ Serialize a sequence of Python objects into a YAML stream.
+ Produce only basic YAML tags.
+ If stream is None, return the produced string instead.
+ """
+ return dump_all(documents, stream, Dumper=SafeDumper, **kwds)
+
+
+def safe_dump(data, stream=None, **kwds):
+ """
+ Serialize a Python object into a YAML stream.
+ Produce only basic YAML tags.
+ If stream is None, return the produced string instead.
+ """
+ return dump_all([data], stream, Dumper=SafeDumper, **kwds)
+
+
+def add_implicit_resolver(tag, regexp, first=None, Loader=None, Dumper=Dumper):
+ """
+ Add an implicit scalar detector.
+ If an implicit scalar value matches the given regexp,
+ the corresponding tag is assigned to the scalar.
+ first is a sequence of possible initial characters or None.
+ """
+ if Loader is None:
+ loader.Loader.add_implicit_resolver(tag, regexp, first)
+ loader.FullLoader.add_implicit_resolver(tag, regexp, first)
+ loader.UnsafeLoader.add_implicit_resolver(tag, regexp, first)
+ else:
+ Loader.add_implicit_resolver(tag, regexp, first)
+ Dumper.add_implicit_resolver(tag, regexp, first)
+
+
+def add_path_resolver(tag, path, kind=None, Loader=None, Dumper=Dumper):
+ """
+ Add a path based resolver for the given tag.
+ A path is a list of keys that forms a path
+ to a node in the representation tree.
+ Keys can be string values, integers, or None.
+ """
+ if Loader is None:
+ loader.Loader.add_path_resolver(tag, path, kind)
+ loader.FullLoader.add_path_resolver(tag, path, kind)
+ loader.UnsafeLoader.add_path_resolver(tag, path, kind)
+ else:
+ Loader.add_path_resolver(tag, path, kind)
+ Dumper.add_path_resolver(tag, path, kind)
+
+
+def add_constructor(tag, constructor, Loader=None):
+ """
+ Add a constructor for the given tag.
+ Constructor is a function that accepts a Loader instance
+ and a node object and produces the corresponding Python object.
+ """
+ if Loader is None:
+ loader.Loader.add_constructor(tag, constructor)
+ loader.FullLoader.add_constructor(tag, constructor)
+ loader.UnsafeLoader.add_constructor(tag, constructor)
+ else:
+ Loader.add_constructor(tag, constructor)
+
+
+def add_multi_constructor(tag_prefix, multi_constructor, Loader=None):
+ """
+ Add a multi-constructor for the given tag prefix.
+ Multi-constructor is called for a node if its tag starts with tag_prefix.
+ Multi-constructor accepts a Loader instance, a tag suffix,
+ and a node object and produces the corresponding Python object.
+ """
+ if Loader is None:
+ loader.Loader.add_multi_constructor(tag_prefix, multi_constructor)
+ loader.FullLoader.add_multi_constructor(tag_prefix, multi_constructor)
+ loader.UnsafeLoader.add_multi_constructor(tag_prefix, multi_constructor)
+ else:
+ Loader.add_multi_constructor(tag_prefix, multi_constructor)
+
+
+def add_representer(data_type, representer, Dumper=Dumper):
+ """
+ Add a representer for the given type.
+ Representer is a function accepting a Dumper instance
+ and an instance of the given data type
+ and producing the corresponding representation node.
+ """
+ Dumper.add_representer(data_type, representer)
+
+
+def add_multi_representer(data_type, multi_representer, Dumper=Dumper):
+ """
+ Add a representer for the given type.
+ Multi-representer is a function accepting a Dumper instance
+ and an instance of the given data type or subtype
+ and producing the corresponding representation node.
+ """
+ Dumper.add_multi_representer(data_type, multi_representer)
+
+
+class YAMLObjectMetaclass(type):
+ """
+ The metaclass for YAMLObject.
+ """
+
+ def __init__(cls, name, bases, kwds):
+ super(YAMLObjectMetaclass, cls).__init__(name, bases, kwds)
+ if "yaml_tag" in kwds and kwds["yaml_tag"] is not None:
+ if isinstance(cls.yaml_loader, list):
+ for loader in cls.yaml_loader:
+ loader.add_constructor(cls.yaml_tag, cls.from_yaml)
+ else:
+ cls.yaml_loader.add_constructor(cls.yaml_tag, cls.from_yaml)
+
+ cls.yaml_dumper.add_representer(cls, cls.to_yaml)
+
+
+class YAMLObject(metaclass=YAMLObjectMetaclass):
+ """
+ An object that can dump itself to a YAML stream
+ and load itself from a YAML stream.
+ """
+
+ __slots__ = () # no direct instantiation, so allow immutable subclasses
+
+ yaml_loader = [Loader, FullLoader, UnsafeLoader]
+ yaml_dumper = Dumper
+
+ yaml_tag = None
+ yaml_flow_style = None
+
+ @classmethod
+ def from_yaml(cls, loader, node):
+ """
+ Convert a representation node to a Python object.
+ """
+ return loader.construct_yaml_object(node, cls)
+
+ @classmethod
+ def to_yaml(cls, dumper, data):
+ """
+ Convert a Python object to a representation node.
+ """
+ return dumper.represent_yaml_object(
+ cls.yaml_tag, data, cls, flow_style=cls.yaml_flow_style
+ )
diff --git a/openlane/dependencies/includedyaml/composer.py b/openlane/dependencies/includedyaml/composer.py
new file mode 100644
index 0000000..431c70d
--- /dev/null
+++ b/openlane/dependencies/includedyaml/composer.py
@@ -0,0 +1,146 @@
+__all__ = ["Composer", "ComposerError"]
+
+from .error import MarkedYAMLError
+from .events import *
+from .nodes import *
+
+
+class ComposerError(MarkedYAMLError):
+ pass
+
+
+class Composer:
+ def __init__(self):
+ self.anchors = {}
+
+ def check_node(self):
+ # Drop the STREAM-START event.
+ if self.check_event(StreamStartEvent):
+ self.get_event()
+
+ # If there are more documents available?
+ return not self.check_event(StreamEndEvent)
+
+ def get_node(self):
+ # Get the root node of the next document.
+ if not self.check_event(StreamEndEvent):
+ return self.compose_document()
+
+ def get_single_node(self):
+ # Drop the STREAM-START event.
+ self.get_event()
+
+ # Compose a document if the stream is not empty.
+ document = None
+ if not self.check_event(StreamEndEvent):
+ document = self.compose_document()
+
+ # Ensure that the stream contains no more documents.
+ if not self.check_event(StreamEndEvent):
+ event = self.get_event()
+ raise ComposerError(
+ "expected a single document in the stream",
+ document.start_mark,
+ "but found another document",
+ event.start_mark,
+ )
+
+ # Drop the STREAM-END event.
+ self.get_event()
+
+ return document
+
+ def compose_document(self):
+ # Drop the DOCUMENT-START event.
+ self.get_event()
+
+ # Compose the root node.
+ node = self.compose_node(None, None)
+
+ # Drop the DOCUMENT-END event.
+ self.get_event()
+
+ self.anchors = {}
+ return node
+
+ def compose_node(self, parent, index):
+ if self.check_event(AliasEvent):
+ event = self.get_event()
+ anchor = event.anchor
+ if anchor not in self.anchors:
+ raise ComposerError(
+ None, None, "found undefined alias %r" % anchor, event.start_mark
+ )
+ return self.anchors[anchor]
+ event = self.peek_event()
+ anchor = event.anchor
+ if anchor is not None:
+ if anchor in self.anchors:
+ raise ComposerError(
+ "found duplicate anchor %r; first occurrence" % anchor,
+ self.anchors[anchor].start_mark,
+ "second occurrence",
+ event.start_mark,
+ )
+ self.descend_resolver(parent, index)
+ if self.check_event(ScalarEvent):
+ node = self.compose_scalar_node(anchor)
+ elif self.check_event(SequenceStartEvent):
+ node = self.compose_sequence_node(anchor)
+ elif self.check_event(MappingStartEvent):
+ node = self.compose_mapping_node(anchor)
+ self.ascend_resolver()
+ return node
+
+ def compose_scalar_node(self, anchor):
+ event = self.get_event()
+ tag = event.tag
+ if tag is None or tag == "!":
+ tag = self.resolve(ScalarNode, event.value, event.implicit)
+ node = ScalarNode(
+ tag, event.value, event.start_mark, event.end_mark, style=event.style
+ )
+ if anchor is not None:
+ self.anchors[anchor] = node
+ return node
+
+ def compose_sequence_node(self, anchor):
+ start_event = self.get_event()
+ tag = start_event.tag
+ if tag is None or tag == "!":
+ tag = self.resolve(SequenceNode, None, start_event.implicit)
+ node = SequenceNode(
+ tag, [], start_event.start_mark, None, flow_style=start_event.flow_style
+ )
+ if anchor is not None:
+ self.anchors[anchor] = node
+ index = 0
+ while not self.check_event(SequenceEndEvent):
+ node.value.append(self.compose_node(node, index))
+ index += 1
+ end_event = self.get_event()
+ node.end_mark = end_event.end_mark
+ return node
+
+ def compose_mapping_node(self, anchor):
+ start_event = self.get_event()
+ tag = start_event.tag
+ if tag is None or tag == "!":
+ tag = self.resolve(MappingNode, None, start_event.implicit)
+ node = MappingNode(
+ tag, [], start_event.start_mark, None, flow_style=start_event.flow_style
+ )
+ if anchor is not None:
+ self.anchors[anchor] = node
+ while not self.check_event(MappingEndEvent):
+ # key_event = self.peek_event()
+ item_key = self.compose_node(node, None)
+ # if item_key in node.value:
+ # raise ComposerError("while composing a mapping", start_event.start_mark,
+ # "found duplicate key", key_event.start_mark)
+ item_value = self.compose_node(node, item_key)
+ # node.value[item_key] = item_value
+ node.value.append((item_key, item_value))
+ end_event = self.get_event()
+ node.end_mark = end_event.end_mark
+ return node
diff --git a/openlane/dependencies/includedyaml/constructor.py b/openlane/dependencies/includedyaml/constructor.py
new file mode 100644
index 0000000..1de226f
--- /dev/null
+++ b/openlane/dependencies/includedyaml/constructor.py
@@ -0,0 +1,862 @@
+__all__ = [
+ "BaseConstructor",
+ "SafeConstructor",
+ "FullConstructor",
+ "UnsafeConstructor",
+ "Constructor",
+ "ConstructorError",
+]
+
+from .error import *
+from .nodes import *
+
+import collections.abc, datetime, base64, binascii, re, sys, types
+
+
+class ConstructorError(MarkedYAMLError):
+ pass
+
+
+class BaseConstructor:
+
+ yaml_constructors = {}
+ yaml_multi_constructors = {}
+
+ def __init__(self):
+ self.constructed_objects = {}
+ self.recursive_objects = {}
+ self.state_generators = []
+ self.deep_construct = False
+
+ def check_data(self):
+ # If there are more documents available?
+ return self.check_node()
+
+ def check_state_key(self, key):
+ """Block special attributes/methods from being set in a newly created
+ object, to prevent user-controlled methods from being called during
+ deserialization"""
+ if self.get_state_keys_blacklist_regexp().match(key):
+ raise ConstructorError(
+ None,
+ None,
+ "blacklisted key '%s' in instance state found" % (key,),
+ None,
+ )
+
+ def get_data(self):
+ # Construct and return the next document.
+ if self.check_node():
+ return self.construct_document(self.get_node())
+
+ def get_single_data(self):
+ # Ensure that the stream contains a single document and construct it.
+ node = self.get_single_node()
+ if node is not None:
+ return self.construct_document(node)
+ return None
+
+ def construct_document(self, node):
+ data = self.construct_object(node)
+ while self.state_generators:
+ state_generators = self.state_generators
+ self.state_generators = []
+ for generator in state_generators:
+ for dummy in generator:
+ pass
+ self.constructed_objects = {}
+ self.recursive_objects = {}
+ self.deep_construct = False
+ return data
+
+ def construct_object(self, node, deep=False):
+ if node in self.constructed_objects:
+ return self.constructed_objects[node]
+ if deep:
+ old_deep = self.deep_construct
+ self.deep_construct = True
+ if node in self.recursive_objects:
+ raise ConstructorError(
+ None, None, "found unconstructable recursive node", node.start_mark
+ )
+ self.recursive_objects[node] = None
+ constructor = None
+ tag_suffix = None
+ if node.tag in self.yaml_constructors:
+ constructor = self.yaml_constructors[node.tag]
+ else:
+ for tag_prefix in self.yaml_multi_constructors:
+ if tag_prefix is not None and node.tag.startswith(tag_prefix):
+ tag_suffix = node.tag[len(tag_prefix) :]
+ constructor = self.yaml_multi_constructors[tag_prefix]
+ break
+ else:
+ if None in self.yaml_multi_constructors:
+ tag_suffix = node.tag
+ constructor = self.yaml_multi_constructors[None]
+ elif None in self.yaml_constructors:
+ constructor = self.yaml_constructors[None]
+ elif isinstance(node, ScalarNode):
+ constructor = self.__class__.construct_scalar
+ elif isinstance(node, SequenceNode):
+ constructor = self.__class__.construct_sequence
+ elif isinstance(node, MappingNode):
+ constructor = self.__class__.construct_mapping
+ if tag_suffix is None:
+ data = constructor(self, node)
+ else:
+ data = constructor(self, tag_suffix, node)
+ if isinstance(data, types.GeneratorType):
+ generator = data
+ data = next(generator)
+ if self.deep_construct:
+ for dummy in generator:
+ pass
+ else:
+ self.state_generators.append(generator)
+ self.constructed_objects[node] = data
+ del self.recursive_objects[node]
+ if deep:
+ self.deep_construct = old_deep
+ return data
+
+ def construct_scalar(self, node):
+ if not isinstance(node, ScalarNode):
+ raise ConstructorError(
+ None,
+ None,
+ "expected a scalar node, but found %s" % node.id,
+ node.start_mark,
+ )
+ return node.value
+
+ def construct_sequence(self, node, deep=False):
+ if not isinstance(node, SequenceNode):
+ raise ConstructorError(
+ None,
+ None,
+ "expected a sequence node, but found %s" % node.id,
+ node.start_mark,
+ )
+ return [self.construct_object(child, deep=deep) for child in node.value]
+
+ def construct_mapping(self, node, deep=False):
+ if not isinstance(node, MappingNode):
+ raise ConstructorError(
+ None,
+ None,
+ "expected a mapping node, but found %s" % node.id,
+ node.start_mark,
+ )
+ mapping = {}
+ for key_node, value_node in node.value:
+ key = self.construct_object(key_node, deep=deep)
+ if not isinstance(key, collections.abc.Hashable):
+ raise ConstructorError(
+ "while constructing a mapping",
+ node.start_mark,
+ "found unhashable key",
+ key_node.start_mark,
+ )
+ value = self.construct_object(value_node, deep=deep)
+ mapping[key] = value
+ return mapping
+
+ def construct_pairs(self, node, deep=False):
+ if not isinstance(node, MappingNode):
+ raise ConstructorError(
+ None,
+ None,
+ "expected a mapping node, but found %s" % node.id,
+ node.start_mark,
+ )
+ pairs = []
+ for key_node, value_node in node.value:
+ key = self.construct_object(key_node, deep=deep)
+ value = self.construct_object(value_node, deep=deep)
+ pairs.append((key, value))
+ return pairs
+
+ @classmethod
+ def add_constructor(cls, tag, constructor):
+ if not "yaml_constructors" in cls.__dict__:
+ cls.yaml_constructors = cls.yaml_constructors.copy()
+ cls.yaml_constructors[tag] = constructor
+
+ @classmethod
+ def add_multi_constructor(cls, tag_prefix, multi_constructor):
+ if not "yaml_multi_constructors" in cls.__dict__:
+ cls.yaml_multi_constructors = cls.yaml_multi_constructors.copy()
+ cls.yaml_multi_constructors[tag_prefix] = multi_constructor
+
+
+class SafeConstructor(BaseConstructor):
+ def construct_scalar(self, node):
+ if isinstance(node, MappingNode):
+ for key_node, value_node in node.value:
+ if key_node.tag == "tag:yaml.org,2002:value":
+ return self.construct_scalar(value_node)
+ return super().construct_scalar(node)
+
+ def flatten_mapping(self, node):
+ merge = []
+ index = 0
+ while index < len(node.value):
+ key_node, value_node = node.value[index]
+ if key_node.tag == "tag:yaml.org,2002:merge":
+ del node.value[index]
+ if isinstance(value_node, MappingNode):
+ self.flatten_mapping(value_node)
+ merge.extend(value_node.value)
+ elif isinstance(value_node, SequenceNode):
+ submerge = []
+ for subnode in value_node.value:
+ if not isinstance(subnode, MappingNode):
+ raise ConstructorError(
+ "while constructing a mapping",
+ node.start_mark,
+ "expected a mapping for merging, but found %s"
+ % subnode.id,
+ subnode.start_mark,
+ )
+ self.flatten_mapping(subnode)
+ submerge.append(subnode.value)
+ submerge.reverse()
+ for value in submerge:
+ merge.extend(value)
+ else:
+ raise ConstructorError(
+ "while constructing a mapping",
+ node.start_mark,
+ "expected a mapping or list of mappings for merging, but found %s"
+ % value_node.id,
+ value_node.start_mark,
+ )
+ elif key_node.tag == "tag:yaml.org,2002:value":
+ key_node.tag = "tag:yaml.org,2002:str"
+ index += 1
+ else:
+ index += 1
+ if merge:
+ node.value = merge + node.value
+
+ def construct_mapping(self, node, deep=False):
+ if isinstance(node, MappingNode):
+ self.flatten_mapping(node)
+ return super().construct_mapping(node, deep=deep)
+
+ def construct_yaml_null(self, node):
+ self.construct_scalar(node)
+ return None
+
+ bool_values = {
+ "yes": True,
+ "no": False,
+ "true": True,
+ "false": False,
+ "on": True,
+ "off": False,
+ }
+
+ def construct_yaml_bool(self, node):
+ value = self.construct_scalar(node)
+ return self.bool_values[value.lower()]
+
+ def construct_yaml_int(self, node):
+ value = self.construct_scalar(node)
+ value = value.replace("_", "")
+ sign = +1
+ if value[0] == "-":
+ sign = -1
+ if value[0] in "+-":
+ value = value[1:]
+ if value == "0":
+ return 0
+ elif value.startswith("0b"):
+ return sign * int(value[2:], 2)
+ elif value.startswith("0x"):
+ return sign * int(value[2:], 16)
+ elif value[0] == "0":
+ return sign * int(value, 8)
+ elif ":" in value:
+ digits = [int(part) for part in value.split(":")]
+ digits.reverse()
+ base = 1
+ value = 0
+ for digit in digits:
+ value += digit * base
+ base *= 60
+ return sign * value
+ else:
+ return sign * int(value)
+
+ inf_value = 1e300
+ while inf_value != inf_value * inf_value:
+ inf_value *= inf_value
+ nan_value = -inf_value / inf_value # Trying to make a quiet NaN (like C99).
+
+ def construct_yaml_float(self, node):
+ value = self.construct_scalar(node)
+ value = value.replace("_", "").lower()
+ sign = +1
+ if value[0] == "-":
+ sign = -1
+ if value[0] in "+-":
+ value = value[1:]
+ if value == ".inf":
+ return sign * self.inf_value
+ elif value == ".nan":
+ return self.nan_value
+ elif ":" in value:
+ digits = [float(part) for part in value.split(":")]
+ digits.reverse()
+ base = 1
+ value = 0.0
+ for digit in digits:
+ value += digit * base
+ base *= 60
+ return sign * value
+ else:
+ return sign * float(value)
+
+ def construct_yaml_binary(self, node):
+ try:
+ value = self.construct_scalar(node).encode("ascii")
+ except UnicodeEncodeError as exc:
+ raise ConstructorError(
+ None,
+ None,
+ "failed to convert base64 data into ascii: %s" % exc,
+ node.start_mark,
+ )
+ try:
+ if hasattr(base64, "decodebytes"):
+ return base64.decodebytes(value)
+ else:
+ return base64.decodestring(value)
+ except binascii.Error as exc:
+ raise ConstructorError(
+ None, None, "failed to decode base64 data: %s" % exc, node.start_mark
+ )
+
+ timestamp_regexp = re.compile(
+ r"""^(?P<year>[0-9][0-9][0-9][0-9])
+ -(?P<month>[0-9][0-9]?)
+ -(?P<day>[0-9][0-9]?)
+ (?:(?:[Tt]|[ \t]+)
+ (?P<hour>[0-9][0-9]?)
+ :(?P<minute>[0-9][0-9])
+ :(?P<second>[0-9][0-9])
+ (?:\.(?P<fraction>[0-9]*))?
+ (?:[ \t]*(?P<tz>Z|(?P<tz_sign>[-+])(?P<tz_hour>[0-9][0-9]?)
+ (?::(?P<tz_minute>[0-9][0-9]))?))?)?$""",
+ re.X,
+ )
+
+ def construct_yaml_timestamp(self, node):
+ value = self.construct_scalar(node)
+ match = self.timestamp_regexp.match(node.value)
+ values = match.groupdict()
+ year = int(values["year"])
+ month = int(values["month"])
+ day = int(values["day"])
+ if not values["hour"]:
+ return datetime.date(year, month, day)
+ hour = int(values["hour"])
+ minute = int(values["minute"])
+ second = int(values["second"])
+ fraction = 0
+ tzinfo = None
+ if values["fraction"]:
+ fraction = values["fraction"][:6]
+ while len(fraction) < 6:
+ fraction += "0"
+ fraction = int(fraction)
+ if values["tz_sign"]:
+ tz_hour = int(values["tz_hour"])
+ tz_minute = int(values["tz_minute"] or 0)
+ delta = datetime.timedelta(hours=tz_hour, minutes=tz_minute)
+ if values["tz_sign"] == "-":
+ delta = -delta
+ tzinfo = datetime.timezone(delta)
+ elif values["tz"]:
+ tzinfo = datetime.timezone.utc
+ return datetime.datetime(
+ year, month, day, hour, minute, second, fraction, tzinfo=tzinfo
+ )
+
+ def construct_yaml_omap(self, node):
+ # Note: we do not check for duplicate keys, because it's too
+ # CPU-expensive.
+ omap = []
+ yield omap
+ if not isinstance(node, SequenceNode):
+ raise ConstructorError(
+ "while constructing an ordered map",
+ node.start_mark,
+ "expected a sequence, but found %s" % node.id,
+ node.start_mark,
+ )
+ for subnode in node.value:
+ if not isinstance(subnode, MappingNode):
+ raise ConstructorError(
+ "while constructing an ordered map",
+ node.start_mark,
+ "expected a mapping of length 1, but found %s" % subnode.id,
+ subnode.start_mark,
+ )
+ if len(subnode.value) != 1:
+ raise ConstructorError(
+ "while constructing an ordered map",
+ node.start_mark,
+ "expected a single mapping item, but found %d items"
+ % len(subnode.value),
+ subnode.start_mark,
+ )
+ key_node, value_node = subnode.value[0]
+ key = self.construct_object(key_node)
+ value = self.construct_object(value_node)
+ omap.append((key, value))
+
+ def construct_yaml_pairs(self, node):
+ # Note: the same code as `construct_yaml_omap`.
+ pairs = []
+ yield pairs
+ if not isinstance(node, SequenceNode):
+ raise ConstructorError(
+ "while constructing pairs",
+ node.start_mark,
+ "expected a sequence, but found %s" % node.id,
+ node.start_mark,
+ )
+ for subnode in node.value:
+ if not isinstance(subnode, MappingNode):
+ raise ConstructorError(
+ "while constructing pairs",
+ node.start_mark,
+ "expected a mapping of length 1, but found %s" % subnode.id,
+ subnode.start_mark,
+ )
+ if len(subnode.value) != 1:
+ raise ConstructorError(
+ "while constructing pairs",
+ node.start_mark,
+ "expected a single mapping item, but found %d items"
+ % len(subnode.value),
+ subnode.start_mark,
+ )
+ key_node, value_node = subnode.value[0]
+ key = self.construct_object(key_node)
+ value = self.construct_object(value_node)
+ pairs.append((key, value))
+
+ def construct_yaml_set(self, node):
+ data = set()
+ yield data
+ value = self.construct_mapping(node)
+ data.update(value)
+
+ def construct_yaml_str(self, node):
+ return self.construct_scalar(node)
+
+ def construct_yaml_seq(self, node):
+ data = []
+ yield data
+ data.extend(self.construct_sequence(node))
+
+ def construct_yaml_map(self, node):
+ data = {}
+ yield data
+ value = self.construct_mapping(node)
+ data.update(value)
+
+ def construct_yaml_object(self, node, cls):
+ data = cls.__new__(cls)
+ yield data
+ if hasattr(data, "__setstate__"):
+ state = self.construct_mapping(node, deep=True)
+ data.__setstate__(state)
+ else:
+ state = self.construct_mapping(node)
+ data.__dict__.update(state)
+
+ def construct_undefined(self, node):
+ raise ConstructorError(
+ None,
+ None,
+ "could not determine a constructor for the tag %r" % node.tag,
+ node.start_mark,
+ )
+
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:null", SafeConstructor.construct_yaml_null
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:bool", SafeConstructor.construct_yaml_bool
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:int", SafeConstructor.construct_yaml_int
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:float", SafeConstructor.construct_yaml_float
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:binary", SafeConstructor.construct_yaml_binary
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:timestamp", SafeConstructor.construct_yaml_timestamp
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:omap", SafeConstructor.construct_yaml_omap
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:pairs", SafeConstructor.construct_yaml_pairs
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:set", SafeConstructor.construct_yaml_set
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:str", SafeConstructor.construct_yaml_str
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:seq", SafeConstructor.construct_yaml_seq
+)
+
+SafeConstructor.add_constructor(
+ "tag:yaml.org,2002:map", SafeConstructor.construct_yaml_map
+)
+
+SafeConstructor.add_constructor(None, SafeConstructor.construct_undefined)
+
+
+class FullConstructor(SafeConstructor):
+ # 'extend' is blacklisted because it is used by
+ # construct_python_object_apply to add `listitems` to a newly generate
+ # python instance
+ def get_state_keys_blacklist(self):
+ return ["^extend$", "^__.*__$"]
+
+ def get_state_keys_blacklist_regexp(self):
+ if not hasattr(self, "state_keys_blacklist_regexp"):
+ self.state_keys_blacklist_regexp = re.compile(
+ "(" + "|".join(self.get_state_keys_blacklist()) + ")"
+ )
+ return self.state_keys_blacklist_regexp
+
+ def construct_python_str(self, node):
+ return self.construct_scalar(node)
+
+ def construct_python_unicode(self, node):
+ return self.construct_scalar(node)
+
+ def construct_python_bytes(self, node):
+ try:
+ value = self.construct_scalar(node).encode("ascii")
+ except UnicodeEncodeError as exc:
+ raise ConstructorError(
+ None,
+ None,
+ "failed to convert base64 data into ascii: %s" % exc,
+ node.start_mark,
+ )
+ try:
+ if hasattr(base64, "decodebytes"):
+ return base64.decodebytes(value)
+ else:
+ return base64.decodestring(value)
+ except binascii.Error as exc:
+ raise ConstructorError(
+ None, None, "failed to decode base64 data: %s" % exc, node.start_mark
+ )
+
+ def construct_python_long(self, node):
+ return self.construct_yaml_int(node)
+
+ def construct_python_complex(self, node):
+ return complex(self.construct_scalar(node))
+
+ def construct_python_tuple(self, node):
+ return tuple(self.construct_sequence(node))
+
+ def find_python_module(self, name, mark, unsafe=False):
+ if not name:
+ raise ConstructorError(
+ "while constructing a Python module",
+ mark,
+ "expected non-empty name appended to the tag",
+ mark,
+ )
+ if unsafe:
+ try:
+ __import__(name)
+ except ImportError as exc:
+ raise ConstructorError(
+ "while constructing a Python module",
+ mark,
+ "cannot find module %r (%s)" % (name, exc),
+ mark,
+ )
+ if name not in sys.modules:
+ raise ConstructorError(
+ "while constructing a Python module",
+ mark,
+ "module %r is not imported" % name,
+ mark,
+ )
+ return sys.modules[name]
+
+ def find_python_name(self, name, mark, unsafe=False):
+ if not name:
+ raise ConstructorError(
+ "while constructing a Python object",
+ mark,
+ "expected non-empty name appended to the tag",
+ mark,
+ )
+ if "." in name:
+ module_name, object_name = name.rsplit(".", 1)
+ else:
+ module_name = "builtins"
+ object_name = name
+ if unsafe:
+ try:
+ __import__(module_name)
+ except ImportError as exc:
+ raise ConstructorError(
+ "while constructing a Python object",
+ mark,
+ "cannot find module %r (%s)" % (module_name, exc),
+ mark,
+ )
+ if module_name not in sys.modules:
+ raise ConstructorError(
+ "while constructing a Python object",
+ mark,
+ "module %r is not imported" % module_name,
+ mark,
+ )
+ module = sys.modules[module_name]
+ if not hasattr(module, object_name):
+ raise ConstructorError(
+ "while constructing a Python object",
+ mark,
+ "cannot find %r in the module %r" % (object_name, module.__name__),
+ mark,
+ )
+ return getattr(module, object_name)
+
+ def construct_python_name(self, suffix, node):
+ value = self.construct_scalar(node)
+ if value:
+ raise ConstructorError(
+ "while constructing a Python name",
+ node.start_mark,
+ "expected the empty value, but found %r" % value,
+ node.start_mark,
+ )
+ return self.find_python_name(suffix, node.start_mark)
+
+ def construct_python_module(self, suffix, node):
+ value = self.construct_scalar(node)
+ if value:
+ raise ConstructorError(
+ "while constructing a Python module",
+ node.start_mark,
+ "expected the empty value, but found %r" % value,
+ node.start_mark,
+ )
+ return self.find_python_module(suffix, node.start_mark)
+
+ def make_python_instance(
+ self, suffix, node, args=None, kwds=None, newobj=False, unsafe=False
+ ):
+ if not args:
+ args = []
+ if not kwds:
+ kwds = {}
+ cls = self.find_python_name(suffix, node.start_mark)
+ if not (unsafe or isinstance(cls, type)):
+ raise ConstructorError(
+ "while constructing a Python instance",
+ node.start_mark,
+ "expected a class, but found %r" % type(cls),
+ node.start_mark,
+ )
+ if newobj and isinstance(cls, type):
+ return cls.__new__(cls, *args, **kwds)
+ else:
+ return cls(*args, **kwds)
+
+ def set_python_instance_state(self, instance, state, unsafe=False):
+ if hasattr(instance, "__setstate__"):
+ instance.__setstate__(state)
+ else:
+ slotstate = {}
+ if isinstance(state, tuple) and len(state) == 2:
+ state, slotstate = state
+ if hasattr(instance, "__dict__"):
+ if not unsafe and state:
+ for key in state.keys():
+ self.check_state_key(key)
+ instance.__dict__.update(state)
+ elif state:
+ slotstate.update(state)
+ for key, value in slotstate.items():
+ if not unsafe:
+ self.check_state_key(key)
+ setattr(instance, key, value)
+
+ def construct_python_object(self, suffix, node):
+ # Format:
+ # !!python/object:module.name { ... state ... }
+ instance = self.make_python_instance(suffix, node, newobj=True)
+ yield instance
+ deep = hasattr(instance, "__setstate__")
+ state = self.construct_mapping(node, deep=deep)
+ self.set_python_instance_state(instance, state)
+
+ def construct_python_object_apply(self, suffix, node, newobj=False):
+ # Format:
+ # !!python/object/apply # (or !!python/object/new)
+ # args: [ ... arguments ... ]
+ # kwds: { ... keywords ... }
+ # state: ... state ...
+ # listitems: [ ... listitems ... ]
+ # dictitems: { ... dictitems ... }
+ # or short format:
+ # !!python/object/apply [ ... arguments ... ]
+ # The difference between !!python/object/apply and !!python/object/new
+ # is how an object is created, check make_python_instance for details.
+ if isinstance(node, SequenceNode):
+ args = self.construct_sequence(node, deep=True)
+ kwds = {}
+ state = {}
+ listitems = []
+ dictitems = {}
+ else:
+ value = self.construct_mapping(node, deep=True)
+ args = value.get("args", [])
+ kwds = value.get("kwds", {})
+ state = value.get("state", {})
+ listitems = value.get("listitems", [])
+ dictitems = value.get("dictitems", {})
+ instance = self.make_python_instance(suffix, node, args, kwds, newobj)
+ if state:
+ self.set_python_instance_state(instance, state)
+ if listitems:
+ instance.extend(listitems)
+ if dictitems:
+ for key in dictitems:
+ instance[key] = dictitems[key]
+ return instance
+
+ def construct_python_object_new(self, suffix, node):
+ return self.construct_python_object_apply(suffix, node, newobj=True)
+
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/none", FullConstructor.construct_yaml_null
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/bool", FullConstructor.construct_yaml_bool
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/str", FullConstructor.construct_python_str
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/unicode", FullConstructor.construct_python_unicode
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/bytes", FullConstructor.construct_python_bytes
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/int", FullConstructor.construct_yaml_int
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/long", FullConstructor.construct_python_long
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/float", FullConstructor.construct_yaml_float
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/complex", FullConstructor.construct_python_complex
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/list", FullConstructor.construct_yaml_seq
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/tuple", FullConstructor.construct_python_tuple
+)
+
+FullConstructor.add_constructor(
+ "tag:yaml.org,2002:python/dict", FullConstructor.construct_yaml_map
+)
+
+FullConstructor.add_multi_constructor(
+ "tag:yaml.org,2002:python/name:", FullConstructor.construct_python_name
+)
+
+
+class UnsafeConstructor(FullConstructor):
+ def find_python_module(self, name, mark):
+ return super(UnsafeConstructor, self).find_python_module(
+ name, mark, unsafe=True
+ )
+
+ def find_python_name(self, name, mark):
+ return super(UnsafeConstructor, self).find_python_name(name, mark, unsafe=True)
+
+ def make_python_instance(self, suffix, node, args=None, kwds=None, newobj=False):
+ return super(UnsafeConstructor, self).make_python_instance(
+ suffix, node, args, kwds, newobj, unsafe=True
+ )
+
+ def set_python_instance_state(self, instance, state):
+ return super(UnsafeConstructor, self).set_python_instance_state(
+ instance, state, unsafe=True
+ )
+
+
+UnsafeConstructor.add_multi_constructor(
+ "tag:yaml.org,2002:python/module:", UnsafeConstructor.construct_python_module
+)
+
+UnsafeConstructor.add_multi_constructor(
+ "tag:yaml.org,2002:python/object:", UnsafeConstructor.construct_python_object
+)
+
+UnsafeConstructor.add_multi_constructor(
+ "tag:yaml.org,2002:python/object/new:",
+ UnsafeConstructor.construct_python_object_new,
+)
+
+UnsafeConstructor.add_multi_constructor(
+ "tag:yaml.org,2002:python/object/apply:",
+ UnsafeConstructor.construct_python_object_apply,
+)
+
+# Constructor is same as UnsafeConstructor. Need to leave this in place in case
+# people have extended it directly.
+class Constructor(UnsafeConstructor):
+ pass
diff --git a/openlane/dependencies/includedyaml/cyaml.py b/openlane/dependencies/includedyaml/cyaml.py
new file mode 100644
index 0000000..7ad380b
--- /dev/null
+++ b/openlane/dependencies/includedyaml/cyaml.py
@@ -0,0 +1,177 @@
+__all__ = [
+ "CBaseLoader",
+ "CSafeLoader",
+ "CFullLoader",
+ "CUnsafeLoader",
+ "CLoader",
+ "CBaseDumper",
+ "CSafeDumper",
+ "CDumper",
+]
+
+from yaml._yaml import CParser, CEmitter
+
+from .constructor import *
+
+from .serializer import *
+from .representer import *
+
+from .resolver import *
+
+
+class CBaseLoader(CParser, BaseConstructor, BaseResolver):
+ def __init__(self, stream):
+ CParser.__init__(self, stream)
+ BaseConstructor.__init__(self)
+ BaseResolver.__init__(self)
+
+
+class CSafeLoader(CParser, SafeConstructor, Resolver):
+ def __init__(self, stream):
+ CParser.__init__(self, stream)
+ SafeConstructor.__init__(self)
+ Resolver.__init__(self)
+
+
+class CFullLoader(CParser, FullConstructor, Resolver):
+ def __init__(self, stream):
+ CParser.__init__(self, stream)
+ FullConstructor.__init__(self)
+ Resolver.__init__(self)
+
+
+class CUnsafeLoader(CParser, UnsafeConstructor, Resolver):
+ def __init__(self, stream):
+ CParser.__init__(self, stream)
+ UnsafeConstructor.__init__(self)
+ Resolver.__init__(self)
+
+
+class CLoader(CParser, Constructor, Resolver):
+ def __init__(self, stream):
+ CParser.__init__(self, stream)
+ Constructor.__init__(self)
+ Resolver.__init__(self)
+
+
+class CBaseDumper(CEmitter, BaseRepresenter, BaseResolver):
+ def __init__(
+ self,
+ stream,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+ ):
+ CEmitter.__init__(
+ self,
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ encoding=encoding,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ version=version,
+ tags=tags,
+ )
+ Representer.__init__(
+ self,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ sort_keys=sort_keys,
+ )
+ Resolver.__init__(self)
+
+
+class CSafeDumper(CEmitter, SafeRepresenter, Resolver):
+ def __init__(
+ self,
+ stream,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+ ):
+ CEmitter.__init__(
+ self,
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ encoding=encoding,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ version=version,
+ tags=tags,
+ )
+ SafeRepresenter.__init__(
+ self,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ sort_keys=sort_keys,
+ )
+ Resolver.__init__(self)
+
+
+class CDumper(CEmitter, Serializer, Representer, Resolver):
+ def __init__(
+ self,
+ stream,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+ ):
+ CEmitter.__init__(
+ self,
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ encoding=encoding,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ version=version,
+ tags=tags,
+ )
+ Representer.__init__(
+ self,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ sort_keys=sort_keys,
+ )
+ Resolver.__init__(self)
diff --git a/openlane/dependencies/includedyaml/dumper.py b/openlane/dependencies/includedyaml/dumper.py
new file mode 100644
index 0000000..6f1b885
--- /dev/null
+++ b/openlane/dependencies/includedyaml/dumper.py
@@ -0,0 +1,138 @@
+__all__ = ["BaseDumper", "SafeDumper", "Dumper"]
+
+from .emitter import *
+from .serializer import *
+from .representer import *
+from .resolver import *
+
+
+class BaseDumper(Emitter, Serializer, BaseRepresenter, BaseResolver):
+ def __init__(
+ self,
+ stream,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+ ):
+ Emitter.__init__(
+ self,
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ )
+ Serializer.__init__(
+ self,
+ encoding=encoding,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ version=version,
+ tags=tags,
+ )
+ Representer.__init__(
+ self,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ sort_keys=sort_keys,
+ )
+ Resolver.__init__(self)
+
+
+class SafeDumper(Emitter, Serializer, SafeRepresenter, Resolver):
+ def __init__(
+ self,
+ stream,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+ ):
+ Emitter.__init__(
+ self,
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ )
+ Serializer.__init__(
+ self,
+ encoding=encoding,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ version=version,
+ tags=tags,
+ )
+ SafeRepresenter.__init__(
+ self,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ sort_keys=sort_keys,
+ )
+ Resolver.__init__(self)
+
+
+class Dumper(Emitter, Serializer, Representer, Resolver):
+ def __init__(
+ self,
+ stream,
+ default_style=None,
+ default_flow_style=False,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ sort_keys=True,
+ ):
+ Emitter.__init__(
+ self,
+ stream,
+ canonical=canonical,
+ indent=indent,
+ width=width,
+ allow_unicode=allow_unicode,
+ line_break=line_break,
+ )
+ Serializer.__init__(
+ self,
+ encoding=encoding,
+ explicit_start=explicit_start,
+ explicit_end=explicit_end,
+ version=version,
+ tags=tags,
+ )
+ Representer.__init__(
+ self,
+ default_style=default_style,
+ default_flow_style=default_flow_style,
+ sort_keys=sort_keys,
+ )
+ Resolver.__init__(self)
diff --git a/openlane/dependencies/includedyaml/emitter.py b/openlane/dependencies/includedyaml/emitter.py
new file mode 100644
index 0000000..2f6311c
--- /dev/null
+++ b/openlane/dependencies/includedyaml/emitter.py
@@ -0,0 +1,1239 @@
+# Emitter expects events obeying the following grammar:
+# stream ::= STREAM-START document* STREAM-END
+# document ::= DOCUMENT-START node DOCUMENT-END
+# node ::= SCALAR | sequence | mapping
+# sequence ::= SEQUENCE-START node* SEQUENCE-END
+# mapping ::= MAPPING-START (node node)* MAPPING-END
+
+__all__ = ["Emitter", "EmitterError"]
+
+from .error import YAMLError
+from .events import *
+
+
+class EmitterError(YAMLError):
+ pass
+
+
+class ScalarAnalysis:
+ def __init__(
+ self,
+ scalar,
+ empty,
+ multiline,
+ allow_flow_plain,
+ allow_block_plain,
+ allow_single_quoted,
+ allow_double_quoted,
+ allow_block,
+ ):
+ self.scalar = scalar
+ self.empty = empty
+ self.multiline = multiline
+ self.allow_flow_plain = allow_flow_plain
+ self.allow_block_plain = allow_block_plain
+ self.allow_single_quoted = allow_single_quoted
+ self.allow_double_quoted = allow_double_quoted
+ self.allow_block = allow_block
+
+
+class Emitter:
+
+ DEFAULT_TAG_PREFIXES = {
+ "!": "!",
+ "tag:yaml.org,2002:": "!!",
+ }
+
+ def __init__(
+ self,
+ stream,
+ canonical=None,
+ indent=None,
+ width=None,
+ allow_unicode=None,
+ line_break=None,
+ ):
+
+ # The stream should have the methods `write` and possibly `flush`.
+ self.stream = stream
+
+ # Encoding can be overridden by STREAM-START.
+ self.encoding = None
+
+ # Emitter is a state machine with a stack of states to handle nested
+ # structures.
+ self.states = []
+ self.state = self.expect_stream_start
+
+ # Current event and the event queue.
+ self.events = []
+ self.event = None
+
+ # The current indentation level and the stack of previous indents.
+ self.indents = []
+ self.indent = None
+
+ # Flow level.
+ self.flow_level = 0
+
+ # Contexts.
+ self.root_context = False
+ self.sequence_context = False
+ self.mapping_context = False
+ self.simple_key_context = False
+
+ # Characteristics of the last emitted character:
+ # - current position.
+ # - is it a whitespace?
+ # - is it an indention character
+ # (indentation space, '-', '?', or ':')?
+ self.line = 0
+ self.column = 0
+ self.whitespace = True
+ self.indention = True
+
+ # Whether the document requires an explicit document indicator
+ self.open_ended = False
+
+ # Formatting details.
+ self.canonical = canonical
+ self.allow_unicode = allow_unicode
+ self.best_indent = 2
+ if indent and 1 < indent < 10:
+ self.best_indent = indent
+ self.best_width = 80
+ if width and width > self.best_indent * 2:
+ self.best_width = width
+ self.best_line_break = "\n"
+ if line_break in ["\r", "\n", "\r\n"]:
+ self.best_line_break = line_break
+
+ # Tag prefixes.
+ self.tag_prefixes = None
+
+ # Prepared anchor and tag.
+ self.prepared_anchor = None
+ self.prepared_tag = None
+
+ # Scalar analysis and style.
+ self.analysis = None
+ self.style = None
+
+ def dispose(self):
+ # Reset the state attributes (to clear self-references)
+ self.states = []
+ self.state = None
+
+ def emit(self, event):
+ self.events.append(event)
+ while not self.need_more_events():
+ self.event = self.events.pop(0)
+ self.state()
+ self.event = None
+
+ # In some cases, we wait for a few next events before emitting.
+
+ def need_more_events(self):
+ if not self.events:
+ return True
+ event = self.events[0]
+ if isinstance(event, DocumentStartEvent):
+ return self.need_events(1)
+ elif isinstance(event, SequenceStartEvent):
+ return self.need_events(2)
+ elif isinstance(event, MappingStartEvent):
+ return self.need_events(3)
+ else:
+ return False
+
+ def need_events(self, count):
+ level = 0
+ for event in self.events[1:]:
+ if isinstance(event, (DocumentStartEvent, CollectionStartEvent)):
+ level += 1
+ elif isinstance(event, (DocumentEndEvent, CollectionEndEvent)):
+ level -= 1
+ elif isinstance(event, StreamEndEvent):
+ level = -1
+ if level < 0:
+ return False
+ return len(self.events) < count + 1
+
+ def increase_indent(self, flow=False, indentless=False):
+ self.indents.append(self.indent)
+ if self.indent is None:
+ if flow:
+ self.indent = self.best_indent
+ else:
+ self.indent = 0
+ elif not indentless:
+ self.indent += self.best_indent
+
+ # States.
+
+ # Stream handlers.
+
+ def expect_stream_start(self):
+ if isinstance(self.event, StreamStartEvent):
+ if self.event.encoding and not hasattr(self.stream, "encoding"):
+ self.encoding = self.event.encoding
+ self.write_stream_start()
+ self.state = self.expect_first_document_start
+ else:
+ raise EmitterError("expected StreamStartEvent, but got %s" % self.event)
+
+ def expect_nothing(self):
+ raise EmitterError("expected nothing, but got %s" % self.event)
+
+ # Document handlers.
+
+ def expect_first_document_start(self):
+ return self.expect_document_start(first=True)
+
+ def expect_document_start(self, first=False):
+ if isinstance(self.event, DocumentStartEvent):
+ if (self.event.version or self.event.tags) and self.open_ended:
+ self.write_indicator("...", True)
+ self.write_indent()
+ if self.event.version:
+ version_text = self.prepare_version(self.event.version)
+ self.write_version_directive(version_text)
+ self.tag_prefixes = self.DEFAULT_TAG_PREFIXES.copy()
+ if self.event.tags:
+ handles = sorted(self.event.tags.keys())
+ for handle in handles:
+ prefix = self.event.tags[handle]
+ self.tag_prefixes[prefix] = handle
+ handle_text = self.prepare_tag_handle(handle)
+ prefix_text = self.prepare_tag_prefix(prefix)
+ self.write_tag_directive(handle_text, prefix_text)
+ implicit = (
+ first
+ and not self.event.explicit
+ and not self.canonical
+ and not self.event.version
+ and not self.event.tags
+ and not self.check_empty_document()
+ )
+ if not implicit:
+ self.write_indent()
+ self.write_indicator("---", True)
+ if self.canonical:
+ self.write_indent()
+ self.state = self.expect_document_root
+ elif isinstance(self.event, StreamEndEvent):
+ if self.open_ended:
+ self.write_indicator("...", True)
+ self.write_indent()
+ self.write_stream_end()
+ self.state = self.expect_nothing
+ else:
+ raise EmitterError("expected DocumentStartEvent, but got %s" % self.event)
+
+ def expect_document_end(self):
+ if isinstance(self.event, DocumentEndEvent):
+ self.write_indent()
+ if self.event.explicit:
+ self.write_indicator("...", True)
+ self.write_indent()
+ self.flush_stream()
+ self.state = self.expect_document_start
+ else:
+ raise EmitterError("expected DocumentEndEvent, but got %s" % self.event)
+
+ def expect_document_root(self):
+ self.states.append(self.expect_document_end)
+ self.expect_node(root=True)
+
+ # Node handlers.
+
+ def expect_node(self, root=False, sequence=False, mapping=False, simple_key=False):
+ self.root_context = root
+ self.sequence_context = sequence
+ self.mapping_context = mapping
+ self.simple_key_context = simple_key
+ if isinstance(self.event, AliasEvent):
+ self.expect_alias()
+ elif isinstance(self.event, (ScalarEvent, CollectionStartEvent)):
+ self.process_anchor("&")
+ self.process_tag()
+ if isinstance(self.event, ScalarEvent):
+ self.expect_scalar()
+ elif isinstance(self.event, SequenceStartEvent):
+ if (
+ self.flow_level
+ or self.canonical
+ or self.event.flow_style
+ or self.check_empty_sequence()
+ ):
+ self.expect_flow_sequence()
+ else:
+ self.expect_block_sequence()
+ elif isinstance(self.event, MappingStartEvent):
+ if (
+ self.flow_level
+ or self.canonical
+ or self.event.flow_style
+ or self.check_empty_mapping()
+ ):
+ self.expect_flow_mapping()
+ else:
+ self.expect_block_mapping()
+ else:
+ raise EmitterError("expected NodeEvent, but got %s" % self.event)
+
+ def expect_alias(self):
+ if self.event.anchor is None:
+ raise EmitterError("anchor is not specified for alias")
+ self.process_anchor("*")
+ self.state = self.states.pop()
+
+ def expect_scalar(self):
+ self.increase_indent(flow=True)
+ self.process_scalar()
+ self.indent = self.indents.pop()
+ self.state = self.states.pop()
+
+ # Flow sequence handlers.
+
+ def expect_flow_sequence(self):
+ self.write_indicator("[", True, whitespace=True)
+ self.flow_level += 1
+ self.increase_indent(flow=True)
+ self.state = self.expect_first_flow_sequence_item
+
+ def expect_first_flow_sequence_item(self):
+ if isinstance(self.event, SequenceEndEvent):
+ self.indent = self.indents.pop()
+ self.flow_level -= 1
+ self.write_indicator("]", False)
+ self.state = self.states.pop()
+ else:
+ if self.canonical or self.column > self.best_width:
+ self.write_indent()
+ self.states.append(self.expect_flow_sequence_item)
+ self.expect_node(sequence=True)
+
+ def expect_flow_sequence_item(self):
+ if isinstance(self.event, SequenceEndEvent):
+ self.indent = self.indents.pop()
+ self.flow_level -= 1
+ if self.canonical:
+ self.write_indicator(",", False)
+ self.write_indent()
+ self.write_indicator("]", False)
+ self.state = self.states.pop()
+ else:
+ self.write_indicator(",", False)
+ if self.canonical or self.column > self.best_width:
+ self.write_indent()
+ self.states.append(self.expect_flow_sequence_item)
+ self.expect_node(sequence=True)
+
+ # Flow mapping handlers.
+
+ def expect_flow_mapping(self):
+ self.write_indicator("{", True, whitespace=True)
+ self.flow_level += 1
+ self.increase_indent(flow=True)
+ self.state = self.expect_first_flow_mapping_key
+
+ def expect_first_flow_mapping_key(self):
+ if isinstance(self.event, MappingEndEvent):
+ self.indent = self.indents.pop()
+ self.flow_level -= 1
+ self.write_indicator("}", False)
+ self.state = self.states.pop()
+ else:
+ if self.canonical or self.column > self.best_width:
+ self.write_indent()
+ if not self.canonical and self.check_simple_key():
+ self.states.append(self.expect_flow_mapping_simple_value)
+ self.expect_node(mapping=True, simple_key=True)
+ else:
+ self.write_indicator("?", True)
+ self.states.append(self.expect_flow_mapping_value)
+ self.expect_node(mapping=True)
+
+ def expect_flow_mapping_key(self):
+ if isinstance(self.event, MappingEndEvent):
+ self.indent = self.indents.pop()
+ self.flow_level -= 1
+ if self.canonical:
+ self.write_indicator(",", False)
+ self.write_indent()
+ self.write_indicator("}", False)
+ self.state = self.states.pop()
+ else:
+ self.write_indicator(",", False)
+ if self.canonical or self.column > self.best_width:
+ self.write_indent()
+ if not self.canonical and self.check_simple_key():
+ self.states.append(self.expect_flow_mapping_simple_value)
+ self.expect_node(mapping=True, simple_key=True)
+ else:
+ self.write_indicator("?", True)
+ self.states.append(self.expect_flow_mapping_value)
+ self.expect_node(mapping=True)
+
+ def expect_flow_mapping_simple_value(self):
+ self.write_indicator(":", False)
+ self.states.append(self.expect_flow_mapping_key)
+ self.expect_node(mapping=True)
+
+ def expect_flow_mapping_value(self):
+ if self.canonical or self.column > self.best_width:
+ self.write_indent()
+ self.write_indicator(":", True)
+ self.states.append(self.expect_flow_mapping_key)
+ self.expect_node(mapping=True)
+
+ # Block sequence handlers.
+
+ def expect_block_sequence(self):
+ indentless = self.mapping_context and not self.indention
+ self.increase_indent(flow=False, indentless=indentless)
+ self.state = self.expect_first_block_sequence_item
+
+ def expect_first_block_sequence_item(self):
+ return self.expect_block_sequence_item(first=True)
+
+ def expect_block_sequence_item(self, first=False):
+ if not first and isinstance(self.event, SequenceEndEvent):
+ self.indent = self.indents.pop()
+ self.state = self.states.pop()
+ else:
+ self.write_indent()
+ self.write_indicator("-", True, indention=True)
+ self.states.append(self.expect_block_sequence_item)
+ self.expect_node(sequence=True)
+
+ # Block mapping handlers.
+
+ def expect_block_mapping(self):
+ self.increase_indent(flow=False)
+ self.state = self.expect_first_block_mapping_key
+
+ def expect_first_block_mapping_key(self):
+ return self.expect_block_mapping_key(first=True)
+
+ def expect_block_mapping_key(self, first=False):
+ if not first and isinstance(self.event, MappingEndEvent):
+ self.indent = self.indents.pop()
+ self.state = self.states.pop()
+ else:
+ self.write_indent()
+ if self.check_simple_key():
+ self.states.append(self.expect_block_mapping_simple_value)
+ self.expect_node(mapping=True, simple_key=True)
+ else:
+ self.write_indicator("?", True, indention=True)
+ self.states.append(self.expect_block_mapping_value)
+ self.expect_node(mapping=True)
+
+ def expect_block_mapping_simple_value(self):
+ self.write_indicator(":", False)
+ self.states.append(self.expect_block_mapping_key)
+ self.expect_node(mapping=True)
+
+ def expect_block_mapping_value(self):
+ self.write_indent()
+ self.write_indicator(":", True, indention=True)
+ self.states.append(self.expect_block_mapping_key)
+ self.expect_node(mapping=True)
+
+ # Checkers.
+
+ def check_empty_sequence(self):
+ return (
+ isinstance(self.event, SequenceStartEvent)
+ and self.events
+ and isinstance(self.events[0], SequenceEndEvent)
+ )
+
+ def check_empty_mapping(self):
+ return (
+ isinstance(self.event, MappingStartEvent)
+ and self.events
+ and isinstance(self.events[0], MappingEndEvent)
+ )
+
+ def check_empty_document(self):
+ if not isinstance(self.event, DocumentStartEvent) or not self.events:
+ return False
+ event = self.events[0]
+ return (
+ isinstance(event, ScalarEvent)
+ and event.anchor is None
+ and event.tag is None
+ and event.implicit
+ and event.value == ""
+ )
+
+ def check_simple_key(self):
+ length = 0
+ if isinstance(self.event, NodeEvent) and self.event.anchor is not None:
+ if self.prepared_anchor is None:
+ self.prepared_anchor = self.prepare_anchor(self.event.anchor)
+ length += len(self.prepared_anchor)
+ if (
+ isinstance(self.event, (ScalarEvent, CollectionStartEvent))
+ and self.event.tag is not None
+ ):
+ if self.prepared_tag is None:
+ self.prepared_tag = self.prepare_tag(self.event.tag)
+ length += len(self.prepared_tag)
+ if isinstance(self.event, ScalarEvent):
+ if self.analysis is None:
+ self.analysis = self.analyze_scalar(self.event.value)
+ length += len(self.analysis.scalar)
+ return length < 128 and (
+ isinstance(self.event, AliasEvent)
+ or (
+ isinstance(self.event, ScalarEvent)
+ and not self.analysis.empty
+ and not self.analysis.multiline
+ )
+ or self.check_empty_sequence()
+ or self.check_empty_mapping()
+ )
+
+ # Anchor, Tag, and Scalar processors.
+
+ def process_anchor(self, indicator):
+ if self.event.anchor is None:
+ self.prepared_anchor = None
+ return
+ if self.prepared_anchor is None:
+ self.prepared_anchor = self.prepare_anchor(self.event.anchor)
+ if self.prepared_anchor:
+ self.write_indicator(indicator + self.prepared_anchor, True)
+ self.prepared_anchor = None
+
+ def process_tag(self):
+ tag = self.event.tag
+ if isinstance(self.event, ScalarEvent):
+ if self.style is None:
+ self.style = self.choose_scalar_style()
+ if (not self.canonical or tag is None) and (
+ (self.style == "" and self.event.implicit[0])
+ or (self.style != "" and self.event.implicit[1])
+ ):
+ self.prepared_tag = None
+ return
+ if self.event.implicit[0] and tag is None:
+ tag = "!"
+ self.prepared_tag = None
+ else:
+ if (not self.canonical or tag is None) and self.event.implicit:
+ self.prepared_tag = None
+ return
+ if tag is None:
+ raise EmitterError("tag is not specified")
+ if self.prepared_tag is None:
+ self.prepared_tag = self.prepare_tag(tag)
+ if self.prepared_tag:
+ self.write_indicator(self.prepared_tag, True)
+ self.prepared_tag = None
+
+ def choose_scalar_style(self):
+ if self.analysis is None:
+ self.analysis = self.analyze_scalar(self.event.value)
+ if self.event.style == '"' or self.canonical:
+ return '"'
+ if not self.event.style and self.event.implicit[0]:
+ if not (
+ self.simple_key_context
+ and (self.analysis.empty or self.analysis.multiline)
+ ) and (
+ self.flow_level
+ and self.analysis.allow_flow_plain
+ or (not self.flow_level and self.analysis.allow_block_plain)
+ ):
+ return ""
+ if self.event.style and self.event.style in "|>":
+ if (
+ not self.flow_level
+ and not self.simple_key_context
+ and self.analysis.allow_block
+ ):
+ return self.event.style
+ if not self.event.style or self.event.style == "'":
+ if self.analysis.allow_single_quoted and not (
+ self.simple_key_context and self.analysis.multiline
+ ):
+ return "'"
+ return '"'
+
+ def process_scalar(self):
+ if self.analysis is None:
+ self.analysis = self.analyze_scalar(self.event.value)
+ if self.style is None:
+ self.style = self.choose_scalar_style()
+ split = not self.simple_key_context
+ # if self.analysis.multiline and split \
+ # and (not self.style or self.style in '\'\"'):
+ # self.write_indent()
+ if self.style == '"':
+ self.write_double_quoted(self.analysis.scalar, split)
+ elif self.style == "'":
+ self.write_single_quoted(self.analysis.scalar, split)
+ elif self.style == ">":
+ self.write_folded(self.analysis.scalar)
+ elif self.style == "|":
+ self.write_literal(self.analysis.scalar)
+ else:
+ self.write_plain(self.analysis.scalar, split)
+ self.analysis = None
+ self.style = None
+
+ # Analyzers.
+
+ def prepare_version(self, version):
+ major, minor = version
+ if major != 1:
+ raise EmitterError("unsupported YAML version: %d.%d" % (major, minor))
+ return "%d.%d" % (major, minor)
+
+ def prepare_tag_handle(self, handle):
+ if not handle:
+ raise EmitterError("tag handle must not be empty")
+ if handle[0] != "!" or handle[-1] != "!":
+ raise EmitterError("tag handle must start and end with '!': %r" % handle)
+ for ch in handle[1:-1]:
+ if not (
+ "0" <= ch <= "9" or "A" <= ch <= "Z" or "a" <= ch <= "z" or ch in "-_"
+ ):
+ raise EmitterError(
+ "invalid character %r in the tag handle: %r" % (ch, handle)
+ )
+ return handle
+
+ def prepare_tag_prefix(self, prefix):
+ if not prefix:
+ raise EmitterError("tag prefix must not be empty")
+ chunks = []
+ start = end = 0
+ if prefix[0] == "!":
+ end = 1
+ while end < len(prefix):
+ ch = prefix[end]
+ if (
+ "0" <= ch <= "9"
+ or "A" <= ch <= "Z"
+ or "a" <= ch <= "z"
+ or ch in "-;/?!:@&=+$,_.~*'()[]"
+ ):
+ end += 1
+ else:
+ if start < end:
+ chunks.append(prefix[start:end])
+ start = end = end + 1
+ data = ch.encode("utf-8")
+ for ch in data:
+ chunks.append("%%%02X" % ord(ch))
+ if start < end:
+ chunks.append(prefix[start:end])
+ return "".join(chunks)
+
+ def prepare_tag(self, tag):
+ if not tag:
+ raise EmitterError("tag must not be empty")
+ if tag == "!":
+ return tag
+ handle = None
+ suffix = tag
+ prefixes = sorted(self.tag_prefixes.keys())
+ for prefix in prefixes:
+ if tag.startswith(prefix) and (prefix == "!" or len(prefix) < len(tag)):
+ handle = self.tag_prefixes[prefix]
+ suffix = tag[len(prefix) :]
+ chunks = []
+ start = end = 0
+ while end < len(suffix):
+ ch = suffix[end]
+ if (
+ "0" <= ch <= "9"
+ or "A" <= ch <= "Z"
+ or "a" <= ch <= "z"
+ or ch in "-;/?:@&=+$,_.~*'()[]"
+ or (ch == "!" and handle != "!")
+ ):
+ end += 1
+ else:
+ if start < end:
+ chunks.append(suffix[start:end])
+ start = end = end + 1
+ data = ch.encode("utf-8")
+ for ch in data:
+ chunks.append("%%%02X" % ch)
+ if start < end:
+ chunks.append(suffix[start:end])
+ suffix_text = "".join(chunks)
+ if handle:
+ return "%s%s" % (handle, suffix_text)
+ else:
+ return "!<%s>" % suffix_text
+
+ def prepare_anchor(self, anchor):
+ if not anchor:
+ raise EmitterError("anchor must not be empty")
+ for ch in anchor:
+ if not (
+ "0" <= ch <= "9" or "A" <= ch <= "Z" or "a" <= ch <= "z" or ch in "-_"
+ ):
+ raise EmitterError(
+ "invalid character %r in the anchor: %r" % (ch, anchor)
+ )
+ return anchor
+
+ def analyze_scalar(self, scalar):
+
+ # Empty scalar is a special case.
+ if not scalar:
+ return ScalarAnalysis(
+ scalar=scalar,
+ empty=True,
+ multiline=False,
+ allow_flow_plain=False,
+ allow_block_plain=True,
+ allow_single_quoted=True,
+ allow_double_quoted=True,
+ allow_block=False,
+ )
+
+ # Indicators and special characters.
+ block_indicators = False
+ flow_indicators = False
+ line_breaks = False
+ special_characters = False
+
+ # Important whitespace combinations.
+ leading_space = False
+ leading_break = False
+ trailing_space = False
+ trailing_break = False
+ break_space = False
+ space_break = False
+
+ # Check document indicators.
+ if scalar.startswith("---") or scalar.startswith("..."):
+ block_indicators = True
+ flow_indicators = True
+
+ # First character or preceded by a whitespace.
+ preceded_by_whitespace = True
+
+ # Last character or followed by a whitespace.
+ followed_by_whitespace = (
+ len(scalar) == 1 or scalar[1] in "\0 \t\r\n\x85\u2028\u2029"
+ )
+
+ # The previous character is a space.
+ previous_space = False
+
+ # The previous character is a break.
+ previous_break = False
+
+ index = 0
+ while index < len(scalar):
+ ch = scalar[index]
+
+ # Check for indicators.
+ if index == 0:
+ # Leading indicators are special characters.
+ if ch in "#,[]{}&*!|>'\"%@`":
+ flow_indicators = True
+ block_indicators = True
+ if ch in "?:":
+ flow_indicators = True
+ if followed_by_whitespace:
+ block_indicators = True
+ if ch == "-" and followed_by_whitespace:
+ flow_indicators = True
+ block_indicators = True
+ else:
+ # Some indicators cannot appear within a scalar as well.
+ if ch in ",?[]{}":
+ flow_indicators = True
+ if ch == ":":
+ flow_indicators = True
+ if followed_by_whitespace:
+ block_indicators = True
+ if ch == "#" and preceded_by_whitespace:
+ flow_indicators = True
+ block_indicators = True
+
+ # Check for line breaks, special, and unicode characters.
+ if ch in "\n\x85\u2028\u2029":
+ line_breaks = True
+ if not (ch == "\n" or "\x20" <= ch <= "\x7E"):
+ if (
+ ch == "\x85"
+ or "\xA0" <= ch <= "\uD7FF"
+ or "\uE000" <= ch <= "\uFFFD"
+ or "\U00010000" <= ch < "\U0010ffff"
+ ) and ch != "\uFEFF":
+ unicode_characters = True
+ if not self.allow_unicode:
+ special_characters = True
+ else:
+ special_characters = True
+
+ # Detect important whitespace combinations.
+ if ch == " ":
+ if index == 0:
+ leading_space = True
+ if index == len(scalar) - 1:
+ trailing_space = True
+ if previous_break:
+ break_space = True
+ previous_space = True
+ previous_break = False
+ elif ch in "\n\x85\u2028\u2029":
+ if index == 0:
+ leading_break = True
+ if index == len(scalar) - 1:
+ trailing_break = True
+ if previous_space:
+ space_break = True
+ previous_space = False
+ previous_break = True
+ else:
+ previous_space = False
+ previous_break = False
+
+ # Prepare for the next character.
+ index += 1
+ preceded_by_whitespace = ch in "\0 \t\r\n\x85\u2028\u2029"
+ followed_by_whitespace = (
+ index + 1 >= len(scalar)
+ or scalar[index + 1] in "\0 \t\r\n\x85\u2028\u2029"
+ )
+
+ # Let's decide what styles are allowed.
+ allow_flow_plain = True
+ allow_block_plain = True
+ allow_single_quoted = True
+ allow_double_quoted = True
+ allow_block = True
+
+ # Leading and trailing whitespaces are bad for plain scalars.
+ if leading_space or leading_break or trailing_space or trailing_break:
+ allow_flow_plain = allow_block_plain = False
+
+ # We do not permit trailing spaces for block scalars.
+ if trailing_space:
+ allow_block = False
+
+ # Spaces at the beginning of a new line are only acceptable for block
+ # scalars.
+ if break_space:
+ allow_flow_plain = allow_block_plain = allow_single_quoted = False
+
+ # Spaces followed by breaks, as well as special character are only
+ # allowed for double quoted scalars.
+ if space_break or special_characters:
+ allow_flow_plain = (
+ allow_block_plain
+ ) = allow_single_quoted = allow_block = False
+
+ # Although the plain scalar writer supports breaks, we never emit
+ # multiline plain scalars.
+ if line_breaks:
+ allow_flow_plain = allow_block_plain = False
+
+ # Flow indicators are forbidden for flow plain scalars.
+ if flow_indicators:
+ allow_flow_plain = False
+
+ # Block indicators are forbidden for block plain scalars.
+ if block_indicators:
+ allow_block_plain = False
+
+ return ScalarAnalysis(
+ scalar=scalar,
+ empty=False,
+ multiline=line_breaks,
+ allow_flow_plain=allow_flow_plain,
+ allow_block_plain=allow_block_plain,
+ allow_single_quoted=allow_single_quoted,
+ allow_double_quoted=allow_double_quoted,
+ allow_block=allow_block,
+ )
+
+ # Writers.
+
+ def flush_stream(self):
+ if hasattr(self.stream, "flush"):
+ self.stream.flush()
+
+ def write_stream_start(self):
+ # Write BOM if needed.
+ if self.encoding and self.encoding.startswith("utf-16"):
+ self.stream.write("\uFEFF".encode(self.encoding))
+
+ def write_stream_end(self):
+ self.flush_stream()
+
+ def write_indicator(
+ self, indicator, need_whitespace, whitespace=False, indention=False
+ ):
+ if self.whitespace or not need_whitespace:
+ data = indicator
+ else:
+ data = " " + indicator
+ self.whitespace = whitespace
+ self.indention = self.indention and indention
+ self.column += len(data)
+ self.open_ended = False
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+
+ def write_indent(self):
+ indent = self.indent or 0
+ if (
+ not self.indention
+ or self.column > indent
+ or (self.column == indent and not self.whitespace)
+ ):
+ self.write_line_break()
+ if self.column < indent:
+ self.whitespace = True
+ data = " " * (indent - self.column)
+ self.column = indent
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+
+ def write_line_break(self, data=None):
+ if data is None:
+ data = self.best_line_break
+ self.whitespace = True
+ self.indention = True
+ self.line += 1
+ self.column = 0
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+
+ def write_version_directive(self, version_text):
+ data = "%%YAML %s" % version_text
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ self.write_line_break()
+
+ def write_tag_directive(self, handle_text, prefix_text):
+ data = "%%TAG %s %s" % (handle_text, prefix_text)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ self.write_line_break()
+
+ # Scalar streams.
+
+ def write_single_quoted(self, text, split=True):
+ self.write_indicator("'", True)
+ spaces = False
+ breaks = False
+ start = end = 0
+ while end <= len(text):
+ ch = None
+ if end < len(text):
+ ch = text[end]
+ if spaces:
+ if ch is None or ch != " ":
+ if (
+ start + 1 == end
+ and self.column > self.best_width
+ and split
+ and start != 0
+ and end != len(text)
+ ):
+ self.write_indent()
+ else:
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end
+ elif breaks:
+ if ch is None or ch not in "\n\x85\u2028\u2029":
+ if text[start] == "\n":
+ self.write_line_break()
+ for br in text[start:end]:
+ if br == "\n":
+ self.write_line_break()
+ else:
+ self.write_line_break(br)
+ self.write_indent()
+ start = end
+ else:
+ if ch is None or ch in " \n\x85\u2028\u2029" or ch == "'":
+ if start < end:
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end
+ if ch == "'":
+ data = "''"
+ self.column += 2
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end + 1
+ if ch is not None:
+ spaces = ch == " "
+ breaks = ch in "\n\x85\u2028\u2029"
+ end += 1
+ self.write_indicator("'", False)
+
+ ESCAPE_REPLACEMENTS = {
+ "\0": "0",
+ "\x07": "a",
+ "\x08": "b",
+ "\x09": "t",
+ "\x0A": "n",
+ "\x0B": "v",
+ "\x0C": "f",
+ "\x0D": "r",
+ "\x1B": "e",
+ '"': '"',
+ "\\": "\\",
+ "\x85": "N",
+ "\xA0": "_",
+ "\u2028": "L",
+ "\u2029": "P",
+ }
+
+ def write_double_quoted(self, text, split=True):
+ self.write_indicator('"', True)
+ start = end = 0
+ while end <= len(text):
+ ch = None
+ if end < len(text):
+ ch = text[end]
+ if (
+ ch is None
+ or ch in '"\\\x85\u2028\u2029\uFEFF'
+ or not (
+ "\x20" <= ch <= "\x7E"
+ or (
+ self.allow_unicode
+ and ("\xA0" <= ch <= "\uD7FF" or "\uE000" <= ch <= "\uFFFD")
+ )
+ )
+ ):
+ if start < end:
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end
+ if ch is not None:
+ if ch in self.ESCAPE_REPLACEMENTS:
+ data = "\\" + self.ESCAPE_REPLACEMENTS[ch]
+ elif ch <= "\xFF":
+ data = "\\x%02X" % ord(ch)
+ elif ch <= "\uFFFF":
+ data = "\\u%04X" % ord(ch)
+ else:
+ data = "\\U%08X" % ord(ch)
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end + 1
+ if (
+ 0 < end < len(text) - 1
+ and (ch == " " or start >= end)
+ and self.column + (end - start) > self.best_width
+ and split
+ ):
+ data = text[start:end] + "\\"
+ if start < end:
+ start = end
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ self.write_indent()
+ self.whitespace = False
+ self.indention = False
+ if text[start] == " ":
+ data = "\\"
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ end += 1
+ self.write_indicator('"', False)
+
+ def determine_block_hints(self, text):
+ hints = ""
+ if text:
+ if text[0] in " \n\x85\u2028\u2029":
+ hints += str(self.best_indent)
+ if text[-1] not in "\n\x85\u2028\u2029":
+ hints += "-"
+ elif len(text) == 1 or text[-2] in "\n\x85\u2028\u2029":
+ hints += "+"
+ return hints
+
+ def write_folded(self, text):
+ hints = self.determine_block_hints(text)
+ self.write_indicator(">" + hints, True)
+ if hints[-1:] == "+":
+ self.open_ended = True
+ self.write_line_break()
+ leading_space = True
+ spaces = False
+ breaks = True
+ start = end = 0
+ while end <= len(text):
+ ch = None
+ if end < len(text):
+ ch = text[end]
+ if breaks:
+ if ch is None or ch not in "\n\x85\u2028\u2029":
+ if (
+ not leading_space
+ and ch is not None
+ and ch != " "
+ and text[start] == "\n"
+ ):
+ self.write_line_break()
+ leading_space = ch == " "
+ for br in text[start:end]:
+ if br == "\n":
+ self.write_line_break()
+ else:
+ self.write_line_break(br)
+ if ch is not None:
+ self.write_indent()
+ start = end
+ elif spaces:
+ if ch != " ":
+ if start + 1 == end and self.column > self.best_width:
+ self.write_indent()
+ else:
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end
+ else:
+ if ch is None or ch in " \n\x85\u2028\u2029":
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ if ch is None:
+ self.write_line_break()
+ start = end
+ if ch is not None:
+ breaks = ch in "\n\x85\u2028\u2029"
+ spaces = ch == " "
+ end += 1
+
+ def write_literal(self, text):
+ hints = self.determine_block_hints(text)
+ self.write_indicator("|" + hints, True)
+ if hints[-1:] == "+":
+ self.open_ended = True
+ self.write_line_break()
+ breaks = True
+ start = end = 0
+ while end <= len(text):
+ ch = None
+ if end < len(text):
+ ch = text[end]
+ if breaks:
+ if ch is None or ch not in "\n\x85\u2028\u2029":
+ for br in text[start:end]:
+ if br == "\n":
+ self.write_line_break()
+ else:
+ self.write_line_break(br)
+ if ch is not None:
+ self.write_indent()
+ start = end
+ else:
+ if ch is None or ch in "\n\x85\u2028\u2029":
+ data = text[start:end]
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ if ch is None:
+ self.write_line_break()
+ start = end
+ if ch is not None:
+ breaks = ch in "\n\x85\u2028\u2029"
+ end += 1
+
+ def write_plain(self, text, split=True):
+ if self.root_context:
+ self.open_ended = True
+ if not text:
+ return
+ if not self.whitespace:
+ data = " "
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ self.whitespace = False
+ self.indention = False
+ spaces = False
+ breaks = False
+ start = end = 0
+ while end <= len(text):
+ ch = None
+ if end < len(text):
+ ch = text[end]
+ if spaces:
+ if ch != " ":
+ if start + 1 == end and self.column > self.best_width and split:
+ self.write_indent()
+ self.whitespace = False
+ self.indention = False
+ else:
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end
+ elif breaks:
+ if ch not in "\n\x85\u2028\u2029":
+ if text[start] == "\n":
+ self.write_line_break()
+ for br in text[start:end]:
+ if br == "\n":
+ self.write_line_break()
+ else:
+ self.write_line_break(br)
+ self.write_indent()
+ self.whitespace = False
+ self.indention = False
+ start = end
+ else:
+ if ch is None or ch in " \n\x85\u2028\u2029":
+ data = text[start:end]
+ self.column += len(data)
+ if self.encoding:
+ data = data.encode(self.encoding)
+ self.stream.write(data)
+ start = end
+ if ch is not None:
+ spaces = ch == " "
+ breaks = ch in "\n\x85\u2028\u2029"
+ end += 1
diff --git a/openlane/dependencies/includedyaml/error.py b/openlane/dependencies/includedyaml/error.py
new file mode 100644
index 0000000..b1c80e0
--- /dev/null
+++ b/openlane/dependencies/includedyaml/error.py
@@ -0,0 +1,94 @@
+__all__ = ["Mark", "YAMLError", "MarkedYAMLError"]
+
+
+class Mark:
+ def __init__(self, name, index, line, column, buffer, pointer):
+ self.name = name
+ self.index = index
+ self.line = line
+ self.column = column
+ self.buffer = buffer
+ self.pointer = pointer
+
+ def get_snippet(self, indent=4, max_length=75):
+ if self.buffer is None:
+ return None
+ head = ""
+ start = self.pointer
+ while start > 0 and self.buffer[start - 1] not in "\0\r\n\x85\u2028\u2029":
+ start -= 1
+ if self.pointer - start > max_length / 2 - 1:
+ head = " ... "
+ start += 5
+ break
+ tail = ""
+ end = self.pointer
+ while (
+ end < len(self.buffer) and self.buffer[end] not in "\0\r\n\x85\u2028\u2029"
+ ):
+ end += 1
+ if end - self.pointer > max_length / 2 - 1:
+ tail = " ... "
+ end -= 5
+ break
+ snippet = self.buffer[start:end]
+ return (
+ " " * indent
+ + head
+ + snippet
+ + tail
+ + "\n"
+ + " " * (indent + self.pointer - start + len(head))
+ + "^"
+ )
+
+ def __str__(self):
+ snippet = self.get_snippet()
+ where = ' in "%s", line %d, column %d' % (
+ self.name,
+ self.line + 1,
+ self.column + 1,
+ )
+ if snippet is not None:
+ where += ":\n" + snippet
+ return where
+
+
+class YAMLError(Exception):
+ pass
+
+
+class MarkedYAMLError(YAMLError):
+ def __init__(
+ self,
+ context=None,
+ context_mark=None,
+ problem=None,
+ problem_mark=None,
+ note=None,
+ ):
+ self.context = context
+ self.context_mark = context_mark
+ self.problem = problem
+ self.problem_mark = problem_mark
+ self.note = note
+
+ def __str__(self):
+ lines = []
+ if self.context is not None:
+ lines.append(self.context)
+ if self.context_mark is not None and (
+ self.problem is None
+ or self.problem_mark is None
+ or self.context_mark.name != self.problem_mark.name
+ or self.context_mark.line != self.problem_mark.line
+ or self.context_mark.column != self.problem_mark.column
+ ):
+ lines.append(str(self.context_mark))
+ if self.problem is not None:
+ lines.append(self.problem)
+ if self.problem_mark is not None:
+ lines.append(str(self.problem_mark))
+ if self.note is not None:
+ lines.append(self.note)
+ return "\n".join(lines)
diff --git a/openlane/dependencies/includedyaml/events.py b/openlane/dependencies/includedyaml/events.py
new file mode 100644
index 0000000..b2e3147
--- /dev/null
+++ b/openlane/dependencies/includedyaml/events.py
@@ -0,0 +1,104 @@
+# Abstract classes.
+
+
+class Event(object):
+ def __init__(self, start_mark=None, end_mark=None):
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+ def __repr__(self):
+ attributes = [
+ key for key in ["anchor", "tag", "implicit", "value"] if hasattr(self, key)
+ ]
+ arguments = ", ".join(
+ ["%s=%r" % (key, getattr(self, key)) for key in attributes]
+ )
+ return "%s(%s)" % (self.__class__.__name__, arguments)
+
+
+class NodeEvent(Event):
+ def __init__(self, anchor, start_mark=None, end_mark=None):
+ self.anchor = anchor
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+
+class CollectionStartEvent(NodeEvent):
+ def __init__(
+ self, anchor, tag, implicit, start_mark=None, end_mark=None, flow_style=None
+ ):
+ self.anchor = anchor
+ self.tag = tag
+ self.implicit = implicit
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.flow_style = flow_style
+
+
+class CollectionEndEvent(Event):
+ pass
+
+
+# Implementations.
+
+
+class StreamStartEvent(Event):
+ def __init__(self, start_mark=None, end_mark=None, encoding=None):
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.encoding = encoding
+
+
+class StreamEndEvent(Event):
+ pass
+
+
+class DocumentStartEvent(Event):
+ def __init__(
+ self, start_mark=None, end_mark=None, explicit=None, version=None, tags=None
+ ):
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.explicit = explicit
+ self.version = version
+ self.tags = tags
+
+
+class DocumentEndEvent(Event):
+ def __init__(self, start_mark=None, end_mark=None, explicit=None):
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.explicit = explicit
+
+
+class AliasEvent(NodeEvent):
+ pass
+
+
+class ScalarEvent(NodeEvent):
+ def __init__(
+ self, anchor, tag, implicit, value, start_mark=None, end_mark=None, style=None
+ ):
+ self.anchor = anchor
+ self.tag = tag
+ self.implicit = implicit
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.style = style
+
+
+class SequenceStartEvent(CollectionStartEvent):
+ pass
+
+
+class SequenceEndEvent(CollectionEndEvent):
+ pass
+
+
+class MappingStartEvent(CollectionStartEvent):
+ pass
+
+
+class MappingEndEvent(CollectionEndEvent):
+ pass
diff --git a/openlane/dependencies/includedyaml/loader.py b/openlane/dependencies/includedyaml/loader.py
new file mode 100644
index 0000000..81f883c
--- /dev/null
+++ b/openlane/dependencies/includedyaml/loader.py
@@ -0,0 +1,62 @@
+__all__ = ["BaseLoader", "FullLoader", "SafeLoader", "Loader", "UnsafeLoader"]
+
+from .reader import *
+from .scanner import *
+from .parser import *
+from .composer import *
+from .constructor import *
+from .resolver import *
+
+
+class BaseLoader(Reader, Scanner, Parser, Composer, BaseConstructor, BaseResolver):
+ def __init__(self, stream):
+ Reader.__init__(self, stream)
+ Scanner.__init__(self)
+ Parser.__init__(self)
+ Composer.__init__(self)
+ BaseConstructor.__init__(self)
+ BaseResolver.__init__(self)
+
+
+class FullLoader(Reader, Scanner, Parser, Composer, FullConstructor, Resolver):
+ def __init__(self, stream):
+ Reader.__init__(self, stream)
+ Scanner.__init__(self)
+ Parser.__init__(self)
+ Composer.__init__(self)
+ FullConstructor.__init__(self)
+ Resolver.__init__(self)
+
+
+class SafeLoader(Reader, Scanner, Parser, Composer, SafeConstructor, Resolver):
+ def __init__(self, stream):
+ Reader.__init__(self, stream)
+ Scanner.__init__(self)
+ Parser.__init__(self)
+ Composer.__init__(self)
+ SafeConstructor.__init__(self)
+ Resolver.__init__(self)
+
+
+class Loader(Reader, Scanner, Parser, Composer, Constructor, Resolver):
+ def __init__(self, stream):
+ Reader.__init__(self, stream)
+ Scanner.__init__(self)
+ Parser.__init__(self)
+ Composer.__init__(self)
+ Constructor.__init__(self)
+ Resolver.__init__(self)
+
+
+# UnsafeLoader is the same as Loader (which is and was always unsafe on
+# untrusted input). Use of either Loader or UnsafeLoader should be rare, since
+# FullLoad should be able to load almost all YAML safely. Loader is left intact
+# to ensure backwards compatibility.
+class UnsafeLoader(Reader, Scanner, Parser, Composer, Constructor, Resolver):
+ def __init__(self, stream):
+ Reader.__init__(self, stream)
+ Scanner.__init__(self)
+ Parser.__init__(self)
+ Composer.__init__(self)
+ Constructor.__init__(self)
+ Resolver.__init__(self)
diff --git a/openlane/dependencies/includedyaml/nodes.py b/openlane/dependencies/includedyaml/nodes.py
new file mode 100644
index 0000000..ad8a4bb
--- /dev/null
+++ b/openlane/dependencies/includedyaml/nodes.py
@@ -0,0 +1,51 @@
+class Node(object):
+ def __init__(self, tag, value, start_mark, end_mark):
+ self.tag = tag
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+ def __repr__(self):
+ value = self.value
+ # if isinstance(value, list):
+ # if len(value) == 0:
+ # value = '<empty>'
+ # elif len(value) == 1:
+ # value = '<1 item>'
+ # else:
+ # value = '<%d items>' % len(value)
+ # else:
+ # if len(value) > 75:
+ # value = repr(value[:70]+u' ... ')
+ # else:
+ # value = repr(value)
+ value = repr(value)
+ return "%s(tag=%r, value=%s)" % (self.__class__.__name__, self.tag, value)
+
+
+class ScalarNode(Node):
+ id = "scalar"
+
+ def __init__(self, tag, value, start_mark=None, end_mark=None, style=None):
+ self.tag = tag
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.style = style
+
+
+class CollectionNode(Node):
+ def __init__(self, tag, value, start_mark=None, end_mark=None, flow_style=None):
+ self.tag = tag
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.flow_style = flow_style
+
+
+class SequenceNode(CollectionNode):
+ id = "sequence"
+
+
+class MappingNode(CollectionNode):
+ id = "mapping"
diff --git a/openlane/dependencies/includedyaml/parser.py b/openlane/dependencies/includedyaml/parser.py
new file mode 100644
index 0000000..9850645
--- /dev/null
+++ b/openlane/dependencies/includedyaml/parser.py
@@ -0,0 +1,629 @@
+# The following YAML grammar is LL(1) and is parsed by a recursive descent
+# parser.
+#
+# stream ::= STREAM-START implicit_document? explicit_document* STREAM-END
+# implicit_document ::= block_node DOCUMENT-END*
+# explicit_document ::= DIRECTIVE* DOCUMENT-START block_node? DOCUMENT-END*
+# block_node_or_indentless_sequence ::=
+# ALIAS
+# | properties (block_content | indentless_block_sequence)?
+# | block_content
+# | indentless_block_sequence
+# block_node ::= ALIAS
+# | properties block_content?
+# | block_content
+# flow_node ::= ALIAS
+# | properties flow_content?
+# | flow_content
+# properties ::= TAG ANCHOR? | ANCHOR TAG?
+# block_content ::= block_collection | flow_collection | SCALAR
+# flow_content ::= flow_collection | SCALAR
+# block_collection ::= block_sequence | block_mapping
+# flow_collection ::= flow_sequence | flow_mapping
+# block_sequence ::= BLOCK-SEQUENCE-START (BLOCK-ENTRY block_node?)* BLOCK-END
+# indentless_sequence ::= (BLOCK-ENTRY block_node?)+
+# block_mapping ::= BLOCK-MAPPING_START
+# ((KEY block_node_or_indentless_sequence?)?
+# (VALUE block_node_or_indentless_sequence?)?)*
+# BLOCK-END
+# flow_sequence ::= FLOW-SEQUENCE-START
+# (flow_sequence_entry FLOW-ENTRY)*
+# flow_sequence_entry?
+# FLOW-SEQUENCE-END
+# flow_sequence_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)?
+# flow_mapping ::= FLOW-MAPPING-START
+# (flow_mapping_entry FLOW-ENTRY)*
+# flow_mapping_entry?
+# FLOW-MAPPING-END
+# flow_mapping_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)?
+#
+# FIRST sets:
+#
+# stream: { STREAM-START }
+# explicit_document: { DIRECTIVE DOCUMENT-START }
+# implicit_document: FIRST(block_node)
+# block_node: { ALIAS TAG ANCHOR SCALAR BLOCK-SEQUENCE-START BLOCK-MAPPING-START FLOW-SEQUENCE-START FLOW-MAPPING-START }
+# flow_node: { ALIAS ANCHOR TAG SCALAR FLOW-SEQUENCE-START FLOW-MAPPING-START }
+# block_content: { BLOCK-SEQUENCE-START BLOCK-MAPPING-START FLOW-SEQUENCE-START FLOW-MAPPING-START SCALAR }
+# flow_content: { FLOW-SEQUENCE-START FLOW-MAPPING-START SCALAR }
+# block_collection: { BLOCK-SEQUENCE-START BLOCK-MAPPING-START }
+# flow_collection: { FLOW-SEQUENCE-START FLOW-MAPPING-START }
+# block_sequence: { BLOCK-SEQUENCE-START }
+# block_mapping: { BLOCK-MAPPING-START }
+# block_node_or_indentless_sequence: { ALIAS ANCHOR TAG SCALAR BLOCK-SEQUENCE-START BLOCK-MAPPING-START FLOW-SEQUENCE-START FLOW-MAPPING-START BLOCK-ENTRY }
+# indentless_sequence: { ENTRY }
+# flow_collection: { FLOW-SEQUENCE-START FLOW-MAPPING-START }
+# flow_sequence: { FLOW-SEQUENCE-START }
+# flow_mapping: { FLOW-MAPPING-START }
+# flow_sequence_entry: { ALIAS ANCHOR TAG SCALAR FLOW-SEQUENCE-START FLOW-MAPPING-START KEY }
+# flow_mapping_entry: { ALIAS ANCHOR TAG SCALAR FLOW-SEQUENCE-START FLOW-MAPPING-START KEY }
+
+__all__ = ["Parser", "ParserError"]
+
+from .error import MarkedYAMLError
+from .tokens import *
+from .events import *
+from .scanner import *
+
+
+class ParserError(MarkedYAMLError):
+ pass
+
+
+class Parser:
+ # Since writing a recursive-descendant parser is a straightforward task, we
+ # do not give many comments here.
+
+ DEFAULT_TAGS = {
+ "!": "!",
+ "!!": "tag:yaml.org,2002:",
+ }
+
+ def __init__(self):
+ self.current_event = None
+ self.yaml_version = None
+ self.tag_handles = {}
+ self.states = []
+ self.marks = []
+ self.state = self.parse_stream_start
+
+ def dispose(self):
+ # Reset the state attributes (to clear self-references)
+ self.states = []
+ self.state = None
+
+ def check_event(self, *choices):
+ # Check the type of the next event.
+ if self.current_event is None:
+ if self.state:
+ self.current_event = self.state()
+ if self.current_event is not None:
+ if not choices:
+ return True
+ for choice in choices:
+ if isinstance(self.current_event, choice):
+ return True
+ return False
+
+ def peek_event(self):
+ # Get the next event.
+ if self.current_event is None:
+ if self.state:
+ self.current_event = self.state()
+ return self.current_event
+
+ def get_event(self):
+ # Get the next event and proceed further.
+ if self.current_event is None:
+ if self.state:
+ self.current_event = self.state()
+ value = self.current_event
+ self.current_event = None
+ return value
+
+ # stream ::= STREAM-START implicit_document? explicit_document* STREAM-END
+ # implicit_document ::= block_node DOCUMENT-END*
+ # explicit_document ::= DIRECTIVE* DOCUMENT-START block_node? DOCUMENT-END*
+
+ def parse_stream_start(self):
+
+ # Parse the stream start.
+ token = self.get_token()
+ event = StreamStartEvent(
+ token.start_mark, token.end_mark, encoding=token.encoding
+ )
+
+ # Prepare the next state.
+ self.state = self.parse_implicit_document_start
+
+ return event
+
+ def parse_implicit_document_start(self):
+
+ # Parse an implicit document.
+ if not self.check_token(DirectiveToken, DocumentStartToken, StreamEndToken):
+ self.tag_handles = self.DEFAULT_TAGS
+ token = self.peek_token()
+ start_mark = end_mark = token.start_mark
+ event = DocumentStartEvent(start_mark, end_mark, explicit=False)
+
+ # Prepare the next state.
+ self.states.append(self.parse_document_end)
+ self.state = self.parse_block_node
+
+ return event
+
+ else:
+ return self.parse_document_start()
+
+ def parse_document_start(self):
+
+ # Parse any extra document end indicators.
+ while self.check_token(DocumentEndToken):
+ self.get_token()
+
+ # Parse an explicit document.
+ if not self.check_token(StreamEndToken):
+ token = self.peek_token()
+ start_mark = token.start_mark
+ version, tags = self.process_directives()
+ if not self.check_token(DocumentStartToken):
+ raise ParserError(
+ None,
+ None,
+ "expected '<document start>', but found %r" % self.peek_token().id,
+ self.peek_token().start_mark,
+ )
+ token = self.get_token()
+ end_mark = token.end_mark
+ event = DocumentStartEvent(
+ start_mark, end_mark, explicit=True, version=version, tags=tags
+ )
+ self.states.append(self.parse_document_end)
+ self.state = self.parse_document_content
+ else:
+ # Parse the end of the stream.
+ token = self.get_token()
+ event = StreamEndEvent(token.start_mark, token.end_mark)
+ assert not self.states
+ assert not self.marks
+ self.state = None
+ return event
+
+ def parse_document_end(self):
+
+ # Parse the document end.
+ token = self.peek_token()
+ start_mark = end_mark = token.start_mark
+ explicit = False
+ if self.check_token(DocumentEndToken):
+ token = self.get_token()
+ end_mark = token.end_mark
+ explicit = True
+ event = DocumentEndEvent(start_mark, end_mark, explicit=explicit)
+
+ # Prepare the next state.
+ self.state = self.parse_document_start
+
+ return event
+
+ def parse_document_content(self):
+ if self.check_token(
+ DirectiveToken, DocumentStartToken, DocumentEndToken, StreamEndToken
+ ):
+ event = self.process_empty_scalar(self.peek_token().start_mark)
+ self.state = self.states.pop()
+ return event
+ else:
+ return self.parse_block_node()
+
+ def process_directives(self):
+ self.yaml_version = None
+ self.tag_handles = {}
+ while self.check_token(DirectiveToken):
+ token = self.get_token()
+ if token.name == "YAML":
+ if self.yaml_version is not None:
+ raise ParserError(
+ None, None, "found duplicate YAML directive", token.start_mark
+ )
+ major, minor = token.value
+ if major != 1:
+ raise ParserError(
+ None,
+ None,
+ "found incompatible YAML document (version 1.* is required)",
+ token.start_mark,
+ )
+ self.yaml_version = token.value
+ elif token.name == "TAG":
+ handle, prefix = token.value
+ if handle in self.tag_handles:
+ raise ParserError(
+ None, None, "duplicate tag handle %r" % handle, token.start_mark
+ )
+ self.tag_handles[handle] = prefix
+ if self.tag_handles:
+ value = self.yaml_version, self.tag_handles.copy()
+ else:
+ value = self.yaml_version, None
+ for key in self.DEFAULT_TAGS:
+ if key not in self.tag_handles:
+ self.tag_handles[key] = self.DEFAULT_TAGS[key]
+ return value
+
+ # block_node_or_indentless_sequence ::= ALIAS
+ # | properties (block_content | indentless_block_sequence)?
+ # | block_content
+ # | indentless_block_sequence
+ # block_node ::= ALIAS
+ # | properties block_content?
+ # | block_content
+ # flow_node ::= ALIAS
+ # | properties flow_content?
+ # | flow_content
+ # properties ::= TAG ANCHOR? | ANCHOR TAG?
+ # block_content ::= block_collection | flow_collection | SCALAR
+ # flow_content ::= flow_collection | SCALAR
+ # block_collection ::= block_sequence | block_mapping
+ # flow_collection ::= flow_sequence | flow_mapping
+
+ def parse_block_node(self):
+ return self.parse_node(block=True)
+
+ def parse_flow_node(self):
+ return self.parse_node()
+
+ def parse_block_node_or_indentless_sequence(self):
+ return self.parse_node(block=True, indentless_sequence=True)
+
+ def parse_node(self, block=False, indentless_sequence=False):
+ if self.check_token(AliasToken):
+ token = self.get_token()
+ event = AliasEvent(token.value, token.start_mark, token.end_mark)
+ self.state = self.states.pop()
+ else:
+ anchor = None
+ tag = None
+ start_mark = end_mark = tag_mark = None
+ if self.check_token(AnchorToken):
+ token = self.get_token()
+ start_mark = token.start_mark
+ end_mark = token.end_mark
+ anchor = token.value
+ if self.check_token(TagToken):
+ token = self.get_token()
+ tag_mark = token.start_mark
+ end_mark = token.end_mark
+ tag = token.value
+ elif self.check_token(TagToken):
+ token = self.get_token()
+ start_mark = tag_mark = token.start_mark
+ end_mark = token.end_mark
+ tag = token.value
+ if self.check_token(AnchorToken):
+ token = self.get_token()
+ end_mark = token.end_mark
+ anchor = token.value
+ if tag is not None:
+ handle, suffix = tag
+ if handle is not None:
+ if handle not in self.tag_handles:
+ raise ParserError(
+ "while parsing a node",
+ start_mark,
+ "found undefined tag handle %r" % handle,
+ tag_mark,
+ )
+ tag = self.tag_handles[handle] + suffix
+ else:
+ tag = suffix
+ # if tag == '!':
+ # raise ParserError("while parsing a node", start_mark,
+ # "found non-specific tag '!'", tag_mark,
+ # "Please check 'http://pyyaml.org/wiki/YAMLNonSpecificTag' and share your opinion.")
+ if start_mark is None:
+ start_mark = end_mark = self.peek_token().start_mark
+ event = None
+ implicit = tag is None or tag == "!"
+ if indentless_sequence and self.check_token(BlockEntryToken):
+ end_mark = self.peek_token().end_mark
+ event = SequenceStartEvent(anchor, tag, implicit, start_mark, end_mark)
+ self.state = self.parse_indentless_sequence_entry
+ else:
+ if self.check_token(ScalarToken):
+ token = self.get_token()
+ end_mark = token.end_mark
+ if (token.plain and tag is None) or tag == "!":
+ implicit = (True, False)
+ elif tag is None:
+ implicit = (False, True)
+ else:
+ implicit = (False, False)
+ event = ScalarEvent(
+ anchor,
+ tag,
+ implicit,
+ token.value,
+ start_mark,
+ end_mark,
+ style=token.style,
+ )
+ self.state = self.states.pop()
+ elif self.check_token(FlowSequenceStartToken):
+ end_mark = self.peek_token().end_mark
+ event = SequenceStartEvent(
+ anchor, tag, implicit, start_mark, end_mark, flow_style=True
+ )
+ self.state = self.parse_flow_sequence_first_entry
+ elif self.check_token(FlowMappingStartToken):
+ end_mark = self.peek_token().end_mark
+ event = MappingStartEvent(
+ anchor, tag, implicit, start_mark, end_mark, flow_style=True
+ )
+ self.state = self.parse_flow_mapping_first_key
+ elif block and self.check_token(BlockSequenceStartToken):
+ end_mark = self.peek_token().start_mark
+ event = SequenceStartEvent(
+ anchor, tag, implicit, start_mark, end_mark, flow_style=False
+ )
+ self.state = self.parse_block_sequence_first_entry
+ elif block and self.check_token(BlockMappingStartToken):
+ end_mark = self.peek_token().start_mark
+ event = MappingStartEvent(
+ anchor, tag, implicit, start_mark, end_mark, flow_style=False
+ )
+ self.state = self.parse_block_mapping_first_key
+ elif anchor is not None or tag is not None:
+ # Empty scalars are allowed even if a tag or an anchor is
+ # specified.
+ event = ScalarEvent(
+ anchor, tag, (implicit, False), "", start_mark, end_mark
+ )
+ self.state = self.states.pop()
+ else:
+ if block:
+ node = "block"
+ else:
+ node = "flow"
+ token = self.peek_token()
+ raise ParserError(
+ "while parsing a %s node" % node,
+ start_mark,
+ "expected the node content, but found %r" % token.id,
+ token.start_mark,
+ )
+ return event
+
+ # block_sequence ::= BLOCK-SEQUENCE-START (BLOCK-ENTRY block_node?)* BLOCK-END
+
+ def parse_block_sequence_first_entry(self):
+ token = self.get_token()
+ self.marks.append(token.start_mark)
+ return self.parse_block_sequence_entry()
+
+ def parse_block_sequence_entry(self):
+ if self.check_token(BlockEntryToken):
+ token = self.get_token()
+ if not self.check_token(BlockEntryToken, BlockEndToken):
+ self.states.append(self.parse_block_sequence_entry)
+ return self.parse_block_node()
+ else:
+ self.state = self.parse_block_sequence_entry
+ return self.process_empty_scalar(token.end_mark)
+ if not self.check_token(BlockEndToken):
+ token = self.peek_token()
+ raise ParserError(
+ "while parsing a block collection",
+ self.marks[-1],
+ "expected <block end>, but found %r" % token.id,
+ token.start_mark,
+ )
+ token = self.get_token()
+ event = SequenceEndEvent(token.start_mark, token.end_mark)
+ self.state = self.states.pop()
+ self.marks.pop()
+ return event
+
+ # indentless_sequence ::= (BLOCK-ENTRY block_node?)+
+
+ def parse_indentless_sequence_entry(self):
+ if self.check_token(BlockEntryToken):
+ token = self.get_token()
+ if not self.check_token(
+ BlockEntryToken, KeyToken, ValueToken, BlockEndToken
+ ):
+ self.states.append(self.parse_indentless_sequence_entry)
+ return self.parse_block_node()
+ else:
+ self.state = self.parse_indentless_sequence_entry
+ return self.process_empty_scalar(token.end_mark)
+ token = self.peek_token()
+ event = SequenceEndEvent(token.start_mark, token.start_mark)
+ self.state = self.states.pop()
+ return event
+
+ # block_mapping ::= BLOCK-MAPPING_START
+ # ((KEY block_node_or_indentless_sequence?)?
+ # (VALUE block_node_or_indentless_sequence?)?)*
+ # BLOCK-END
+
+ def parse_block_mapping_first_key(self):
+ token = self.get_token()
+ self.marks.append(token.start_mark)
+ return self.parse_block_mapping_key()
+
+ def parse_block_mapping_key(self):
+ if self.check_token(KeyToken):
+ token = self.get_token()
+ if not self.check_token(KeyToken, ValueToken, BlockEndToken):
+ self.states.append(self.parse_block_mapping_value)
+ return self.parse_block_node_or_indentless_sequence()
+ else:
+ self.state = self.parse_block_mapping_value
+ return self.process_empty_scalar(token.end_mark)
+ if not self.check_token(BlockEndToken):
+ token = self.peek_token()
+ raise ParserError(
+ "while parsing a block mapping",
+ self.marks[-1],
+ "expected <block end>, but found %r" % token.id,
+ token.start_mark,
+ )
+ token = self.get_token()
+ event = MappingEndEvent(token.start_mark, token.end_mark)
+ self.state = self.states.pop()
+ self.marks.pop()
+ return event
+
+ def parse_block_mapping_value(self):
+ if self.check_token(ValueToken):
+ token = self.get_token()
+ if not self.check_token(KeyToken, ValueToken, BlockEndToken):
+ self.states.append(self.parse_block_mapping_key)
+ return self.parse_block_node_or_indentless_sequence()
+ else:
+ self.state = self.parse_block_mapping_key
+ return self.process_empty_scalar(token.end_mark)
+ else:
+ self.state = self.parse_block_mapping_key
+ token = self.peek_token()
+ return self.process_empty_scalar(token.start_mark)
+
+ # flow_sequence ::= FLOW-SEQUENCE-START
+ # (flow_sequence_entry FLOW-ENTRY)*
+ # flow_sequence_entry?
+ # FLOW-SEQUENCE-END
+ # flow_sequence_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)?
+ #
+ # Note that while production rules for both flow_sequence_entry and
+ # flow_mapping_entry are equal, their interpretations are different.
+ # For `flow_sequence_entry`, the part `KEY flow_node? (VALUE flow_node?)?`
+ # generate an inline mapping (set syntax).
+
+ def parse_flow_sequence_first_entry(self):
+ token = self.get_token()
+ self.marks.append(token.start_mark)
+ return self.parse_flow_sequence_entry(first=True)
+
+ def parse_flow_sequence_entry(self, first=False):
+ if not self.check_token(FlowSequenceEndToken):
+ if not first:
+ if self.check_token(FlowEntryToken):
+ self.get_token()
+ else:
+ token = self.peek_token()
+ raise ParserError(
+ "while parsing a flow sequence",
+ self.marks[-1],
+ "expected ',' or ']', but got %r" % token.id,
+ token.start_mark,
+ )
+
+ if self.check_token(KeyToken):
+ token = self.peek_token()
+ event = MappingStartEvent(
+ None, None, True, token.start_mark, token.end_mark, flow_style=True
+ )
+ self.state = self.parse_flow_sequence_entry_mapping_key
+ return event
+ elif not self.check_token(FlowSequenceEndToken):
+ self.states.append(self.parse_flow_sequence_entry)
+ return self.parse_flow_node()
+ token = self.get_token()
+ event = SequenceEndEvent(token.start_mark, token.end_mark)
+ self.state = self.states.pop()
+ self.marks.pop()
+ return event
+
+ def parse_flow_sequence_entry_mapping_key(self):
+ token = self.get_token()
+ if not self.check_token(ValueToken, FlowEntryToken, FlowSequenceEndToken):
+ self.states.append(self.parse_flow_sequence_entry_mapping_value)
+ return self.parse_flow_node()
+ else:
+ self.state = self.parse_flow_sequence_entry_mapping_value
+ return self.process_empty_scalar(token.end_mark)
+
+ def parse_flow_sequence_entry_mapping_value(self):
+ if self.check_token(ValueToken):
+ token = self.get_token()
+ if not self.check_token(FlowEntryToken, FlowSequenceEndToken):
+ self.states.append(self.parse_flow_sequence_entry_mapping_end)
+ return self.parse_flow_node()
+ else:
+ self.state = self.parse_flow_sequence_entry_mapping_end
+ return self.process_empty_scalar(token.end_mark)
+ else:
+ self.state = self.parse_flow_sequence_entry_mapping_end
+ token = self.peek_token()
+ return self.process_empty_scalar(token.start_mark)
+
+ def parse_flow_sequence_entry_mapping_end(self):
+ self.state = self.parse_flow_sequence_entry
+ token = self.peek_token()
+ return MappingEndEvent(token.start_mark, token.start_mark)
+
+ # flow_mapping ::= FLOW-MAPPING-START
+ # (flow_mapping_entry FLOW-ENTRY)*
+ # flow_mapping_entry?
+ # FLOW-MAPPING-END
+ # flow_mapping_entry ::= flow_node | KEY flow_node? (VALUE flow_node?)?
+
+ def parse_flow_mapping_first_key(self):
+ token = self.get_token()
+ self.marks.append(token.start_mark)
+ return self.parse_flow_mapping_key(first=True)
+
+ def parse_flow_mapping_key(self, first=False):
+ if not self.check_token(FlowMappingEndToken):
+ if not first:
+ if self.check_token(FlowEntryToken):
+ self.get_token()
+ else:
+ token = self.peek_token()
+ raise ParserError(
+ "while parsing a flow mapping",
+ self.marks[-1],
+ "expected ',' or '}', but got %r" % token.id,
+ token.start_mark,
+ )
+ if self.check_token(KeyToken):
+ token = self.get_token()
+ if not self.check_token(
+ ValueToken, FlowEntryToken, FlowMappingEndToken
+ ):
+ self.states.append(self.parse_flow_mapping_value)
+ return self.parse_flow_node()
+ else:
+ self.state = self.parse_flow_mapping_value
+ return self.process_empty_scalar(token.end_mark)
+ elif not self.check_token(FlowMappingEndToken):
+ self.states.append(self.parse_flow_mapping_empty_value)
+ return self.parse_flow_node()
+ token = self.get_token()
+ event = MappingEndEvent(token.start_mark, token.end_mark)
+ self.state = self.states.pop()
+ self.marks.pop()
+ return event
+
+ def parse_flow_mapping_value(self):
+ if self.check_token(ValueToken):
+ token = self.get_token()
+ if not self.check_token(FlowEntryToken, FlowMappingEndToken):
+ self.states.append(self.parse_flow_mapping_key)
+ return self.parse_flow_node()
+ else:
+ self.state = self.parse_flow_mapping_key
+ return self.process_empty_scalar(token.end_mark)
+ else:
+ self.state = self.parse_flow_mapping_key
+ token = self.peek_token()
+ return self.process_empty_scalar(token.start_mark)
+
+ def parse_flow_mapping_empty_value(self):
+ self.state = self.parse_flow_mapping_key
+ return self.process_empty_scalar(self.peek_token().start_mark)
+
+ def process_empty_scalar(self, mark):
+ return ScalarEvent(None, None, (True, False), "", mark, mark)
diff --git a/openlane/dependencies/includedyaml/reader.py b/openlane/dependencies/includedyaml/reader.py
new file mode 100644
index 0000000..38547d7
--- /dev/null
+++ b/openlane/dependencies/includedyaml/reader.py
@@ -0,0 +1,208 @@
+# This module contains abstractions for the input stream. You don't have to
+# looks further, there are no pretty code.
+#
+# We define two classes here.
+#
+# Mark(source, line, column)
+# It's just a record and its only use is producing nice error messages.
+# Parser does not use it for any other purposes.
+#
+# Reader(source, data)
+# Reader determines the encoding of `data` and converts it to unicode.
+# Reader provides the following methods and attributes:
+# reader.peek(length=1) - return the next `length` characters
+# reader.forward(length=1) - move the current position to `length` characters.
+# reader.index - the number of the current character.
+# reader.line, stream.column - the line and the column of the current character.
+
+__all__ = ["Reader", "ReaderError"]
+
+from .error import YAMLError, Mark
+
+import codecs, re
+
+
+class ReaderError(YAMLError):
+ def __init__(self, name, position, character, encoding, reason):
+ self.name = name
+ self.character = character
+ self.position = position
+ self.encoding = encoding
+ self.reason = reason
+
+ def __str__(self):
+ if isinstance(self.character, bytes):
+ return (
+ "'%s' codec can't decode byte #x%02x: %s\n"
+ ' in "%s", position %d'
+ % (
+ self.encoding,
+ ord(self.character),
+ self.reason,
+ self.name,
+ self.position,
+ )
+ )
+ else:
+ return "unacceptable character #x%04x: %s\n" ' in "%s", position %d' % (
+ self.character,
+ self.reason,
+ self.name,
+ self.position,
+ )
+
+
+class Reader(object):
+ # Reader:
+ # - determines the data encoding and converts it to a unicode string,
+ # - checks if characters are in allowed range,
+ # - adds '\0' to the end.
+
+ # Reader accepts
+ # - a `bytes` object,
+ # - a `str` object,
+ # - a file-like object with its `read` method returning `str`,
+ # - a file-like object with its `read` method returning `unicode`.
+
+ # Yeah, it's ugly and slow.
+
+ def __init__(self, stream):
+ self.name = None
+ self.stream = None
+ self.stream_pointer = 0
+ self.eof = True
+ self.buffer = ""
+ self.pointer = 0
+ self.raw_buffer = None
+ self.raw_decode = None
+ self.encoding = None
+ self.index = 0
+ self.line = 0
+ self.column = 0
+ if isinstance(stream, str):
+ self.name = "<unicode string>"
+ self.check_printable(stream)
+ self.buffer = stream + "\0"
+ elif isinstance(stream, bytes):
+ self.name = "<byte string>"
+ self.raw_buffer = stream
+ self.determine_encoding()
+ else:
+ self.stream = stream
+ self.name = getattr(stream, "name", "<file>")
+ self.eof = False
+ self.raw_buffer = None
+ self.determine_encoding()
+
+ def peek(self, index=0):
+ try:
+ return self.buffer[self.pointer + index]
+ except IndexError:
+ self.update(index + 1)
+ return self.buffer[self.pointer + index]
+
+ def prefix(self, length=1):
+ if self.pointer + length >= len(self.buffer):
+ self.update(length)
+ return self.buffer[self.pointer : self.pointer + length]
+
+ def forward(self, length=1):
+ if self.pointer + length + 1 >= len(self.buffer):
+ self.update(length + 1)
+ while length:
+ ch = self.buffer[self.pointer]
+ self.pointer += 1
+ self.index += 1
+ if ch in "\n\x85\u2028\u2029" or (
+ ch == "\r" and self.buffer[self.pointer] != "\n"
+ ):
+ self.line += 1
+ self.column = 0
+ elif ch != "\uFEFF":
+ self.column += 1
+ length -= 1
+
+ def get_mark(self):
+ if self.stream is None:
+ return Mark(
+ self.name, self.index, self.line, self.column, self.buffer, self.pointer
+ )
+ else:
+ return Mark(self.name, self.index, self.line, self.column, None, None)
+
+ def determine_encoding(self):
+ while not self.eof and (self.raw_buffer is None or len(self.raw_buffer) < 2):
+ self.update_raw()
+ if isinstance(self.raw_buffer, bytes):
+ if self.raw_buffer.startswith(codecs.BOM_UTF16_LE):
+ self.raw_decode = codecs.utf_16_le_decode
+ self.encoding = "utf-16-le"
+ elif self.raw_buffer.startswith(codecs.BOM_UTF16_BE):
+ self.raw_decode = codecs.utf_16_be_decode
+ self.encoding = "utf-16-be"
+ else:
+ self.raw_decode = codecs.utf_8_decode
+ self.encoding = "utf-8"
+ self.update(1)
+
+ NON_PRINTABLE = re.compile(
+ "[^\x09\x0A\x0D\x20-\x7E\x85\xA0-\uD7FF\uE000-\uFFFD\U00010000-\U0010ffff]"
+ )
+
+ def check_printable(self, data):
+ match = self.NON_PRINTABLE.search(data)
+ if match:
+ character = match.group()
+ position = self.index + (len(self.buffer) - self.pointer) + match.start()
+ raise ReaderError(
+ self.name,
+ position,
+ ord(character),
+ "unicode",
+ "special characters are not allowed",
+ )
+
+ def update(self, length):
+ if self.raw_buffer is None:
+ return
+ self.buffer = self.buffer[self.pointer :]
+ self.pointer = 0
+ while len(self.buffer) < length:
+ if not self.eof:
+ self.update_raw()
+ if self.raw_decode is not None:
+ try:
+ data, converted = self.raw_decode(
+ self.raw_buffer, "strict", self.eof
+ )
+ except UnicodeDecodeError as exc:
+ character = self.raw_buffer[exc.start]
+ if self.stream is not None:
+ position = (
+ self.stream_pointer - len(self.raw_buffer) + exc.start
+ )
+ else:
+ position = exc.start
+ raise ReaderError(
+ self.name, position, character, exc.encoding, exc.reason
+ )
+ else:
+ data = self.raw_buffer
+ converted = len(data)
+ self.check_printable(data)
+ self.buffer += data
+ self.raw_buffer = self.raw_buffer[converted:]
+ if self.eof:
+ self.buffer += "\0"
+ self.raw_buffer = None
+ break
+
+ def update_raw(self, size=4096):
+ data = self.stream.read(size)
+ if self.raw_buffer is None:
+ self.raw_buffer = data
+ else:
+ self.raw_buffer += data
+ self.stream_pointer += len(data)
+ if not data:
+ self.eof = True
diff --git a/openlane/dependencies/includedyaml/representer.py b/openlane/dependencies/includedyaml/representer.py
new file mode 100644
index 0000000..d8a41d4
--- /dev/null
+++ b/openlane/dependencies/includedyaml/representer.py
@@ -0,0 +1,378 @@
+__all__ = ["BaseRepresenter", "SafeRepresenter", "Representer", "RepresenterError"]
+
+from .error import *
+from .nodes import *
+
+import datetime, copyreg, types, base64, collections
+
+
+class RepresenterError(YAMLError):
+ pass
+
+
+class BaseRepresenter:
+
+ yaml_representers = {}
+ yaml_multi_representers = {}
+
+ def __init__(self, default_style=None, default_flow_style=False, sort_keys=True):
+ self.default_style = default_style
+ self.sort_keys = sort_keys
+ self.default_flow_style = default_flow_style
+ self.represented_objects = {}
+ self.object_keeper = []
+ self.alias_key = None
+
+ def represent(self, data):
+ node = self.represent_data(data)
+ self.serialize(node)
+ self.represented_objects = {}
+ self.object_keeper = []
+ self.alias_key = None
+
+ def represent_data(self, data):
+ if self.ignore_aliases(data):
+ self.alias_key = None
+ else:
+ self.alias_key = id(data)
+ if self.alias_key is not None:
+ if self.alias_key in self.represented_objects:
+ node = self.represented_objects[self.alias_key]
+ # if node is None:
+ # raise RepresenterError("recursive objects are not allowed: %r" % data)
+ return node
+ # self.represented_objects[alias_key] = None
+ self.object_keeper.append(data)
+ data_types = type(data).__mro__
+ if data_types[0] in self.yaml_representers:
+ node = self.yaml_representers[data_types[0]](self, data)
+ else:
+ for data_type in data_types:
+ if data_type in self.yaml_multi_representers:
+ node = self.yaml_multi_representers[data_type](self, data)
+ break
+ else:
+ if None in self.yaml_multi_representers:
+ node = self.yaml_multi_representers[None](self, data)
+ elif None in self.yaml_representers:
+ node = self.yaml_representers[None](self, data)
+ else:
+ node = ScalarNode(None, str(data))
+ # if alias_key is not None:
+ # self.represented_objects[alias_key] = node
+ return node
+
+ @classmethod
+ def add_representer(cls, data_type, representer):
+ if not "yaml_representers" in cls.__dict__:
+ cls.yaml_representers = cls.yaml_representers.copy()
+ cls.yaml_representers[data_type] = representer
+
+ @classmethod
+ def add_multi_representer(cls, data_type, representer):
+ if not "yaml_multi_representers" in cls.__dict__:
+ cls.yaml_multi_representers = cls.yaml_multi_representers.copy()
+ cls.yaml_multi_representers[data_type] = representer
+
+ def represent_scalar(self, tag, value, style=None):
+ if style is None:
+ style = self.default_style
+ node = ScalarNode(tag, value, style=style)
+ if self.alias_key is not None:
+ self.represented_objects[self.alias_key] = node
+ return node
+
+ def represent_sequence(self, tag, sequence, flow_style=None):
+ value = []
+ node = SequenceNode(tag, value, flow_style=flow_style)
+ if self.alias_key is not None:
+ self.represented_objects[self.alias_key] = node
+ best_style = True
+ for item in sequence:
+ node_item = self.represent_data(item)
+ if not (isinstance(node_item, ScalarNode) and not node_item.style):
+ best_style = False
+ value.append(node_item)
+ if flow_style is None:
+ if self.default_flow_style is not None:
+ node.flow_style = self.default_flow_style
+ else:
+ node.flow_style = best_style
+ return node
+
+ def represent_mapping(self, tag, mapping, flow_style=None):
+ value = []
+ node = MappingNode(tag, value, flow_style=flow_style)
+ if self.alias_key is not None:
+ self.represented_objects[self.alias_key] = node
+ best_style = True
+ if hasattr(mapping, "items"):
+ mapping = list(mapping.items())
+ if self.sort_keys:
+ try:
+ mapping = sorted(mapping)
+ except TypeError:
+ pass
+ for item_key, item_value in mapping:
+ node_key = self.represent_data(item_key)
+ node_value = self.represent_data(item_value)
+ if not (isinstance(node_key, ScalarNode) and not node_key.style):
+ best_style = False
+ if not (isinstance(node_value, ScalarNode) and not node_value.style):
+ best_style = False
+ value.append((node_key, node_value))
+ if flow_style is None:
+ if self.default_flow_style is not None:
+ node.flow_style = self.default_flow_style
+ else:
+ node.flow_style = best_style
+ return node
+
+ def ignore_aliases(self, data):
+ return False
+
+
+class SafeRepresenter(BaseRepresenter):
+ def ignore_aliases(self, data):
+ if data is None:
+ return True
+ if isinstance(data, tuple) and data == ():
+ return True
+ if isinstance(data, (str, bytes, bool, int, float)):
+ return True
+
+ def represent_none(self, data):
+ return self.represent_scalar("tag:yaml.org,2002:null", "null")
+
+ def represent_str(self, data):
+ return self.represent_scalar("tag:yaml.org,2002:str", data)
+
+ def represent_binary(self, data):
+ if hasattr(base64, "encodebytes"):
+ data = base64.encodebytes(data).decode("ascii")
+ else:
+ data = base64.encodestring(data).decode("ascii")
+ return self.represent_scalar("tag:yaml.org,2002:binary", data, style="|")
+
+ def represent_bool(self, data):
+ if data:
+ value = "true"
+ else:
+ value = "false"
+ return self.represent_scalar("tag:yaml.org,2002:bool", value)
+
+ def represent_int(self, data):
+ return self.represent_scalar("tag:yaml.org,2002:int", str(data))
+
+ inf_value = 1e300
+ while repr(inf_value) != repr(inf_value * inf_value):
+ inf_value *= inf_value
+
+ def represent_float(self, data):
+ if data != data or (data == 0.0 and data == 1.0):
+ value = ".nan"
+ elif data == self.inf_value:
+ value = ".inf"
+ elif data == -self.inf_value:
+ value = "-.inf"
+ else:
+ value = repr(data).lower()
+ # Note that in some cases `repr(data)` represents a float number
+ # without the decimal parts. For instance:
+ # >>> repr(1e17)
+ # '1e17'
+ # Unfortunately, this is not a valid float representation according
+ # to the definition of the `!!float` tag. We fix this by adding
+ # '.0' before the 'e' symbol.
+ if "." not in value and "e" in value:
+ value = value.replace("e", ".0e", 1)
+ return self.represent_scalar("tag:yaml.org,2002:float", value)
+
+ def represent_list(self, data):
+ # pairs = (len(data) > 0 and isinstance(data, list))
+ # if pairs:
+ # for item in data:
+ # if not isinstance(item, tuple) or len(item) != 2:
+ # pairs = False
+ # break
+ # if not pairs:
+ return self.represent_sequence("tag:yaml.org,2002:seq", data)
+
+ # value = []
+ # for item_key, item_value in data:
+ # value.append(self.represent_mapping(u'tag:yaml.org,2002:map',
+ # [(item_key, item_value)]))
+ # return SequenceNode(u'tag:yaml.org,2002:pairs', value)
+
+ def represent_dict(self, data):
+ return self.represent_mapping("tag:yaml.org,2002:map", data)
+
+ def represent_set(self, data):
+ value = {}
+ for key in data:
+ value[key] = None
+ return self.represent_mapping("tag:yaml.org,2002:set", value)
+
+ def represent_date(self, data):
+ value = data.isoformat()
+ return self.represent_scalar("tag:yaml.org,2002:timestamp", value)
+
+ def represent_datetime(self, data):
+ value = data.isoformat(" ")
+ return self.represent_scalar("tag:yaml.org,2002:timestamp", value)
+
+ def represent_yaml_object(self, tag, data, cls, flow_style=None):
+ if hasattr(data, "__getstate__"):
+ state = data.__getstate__()
+ else:
+ state = data.__dict__.copy()
+ return self.represent_mapping(tag, state, flow_style=flow_style)
+
+ def represent_undefined(self, data):
+ raise RepresenterError("cannot represent an object", data)
+
+
+SafeRepresenter.add_representer(type(None), SafeRepresenter.represent_none)
+
+SafeRepresenter.add_representer(str, SafeRepresenter.represent_str)
+
+SafeRepresenter.add_representer(bytes, SafeRepresenter.represent_binary)
+
+SafeRepresenter.add_representer(bool, SafeRepresenter.represent_bool)
+
+SafeRepresenter.add_representer(int, SafeRepresenter.represent_int)
+
+SafeRepresenter.add_representer(float, SafeRepresenter.represent_float)
+
+SafeRepresenter.add_representer(list, SafeRepresenter.represent_list)
+
+SafeRepresenter.add_representer(tuple, SafeRepresenter.represent_list)
+
+SafeRepresenter.add_representer(dict, SafeRepresenter.represent_dict)
+
+SafeRepresenter.add_representer(set, SafeRepresenter.represent_set)
+
+SafeRepresenter.add_representer(datetime.date, SafeRepresenter.represent_date)
+
+SafeRepresenter.add_representer(datetime.datetime, SafeRepresenter.represent_datetime)
+
+SafeRepresenter.add_representer(None, SafeRepresenter.represent_undefined)
+
+
+class Representer(SafeRepresenter):
+ def represent_complex(self, data):
+ if data.imag == 0.0:
+ data = "%r" % data.real
+ elif data.real == 0.0:
+ data = "%rj" % data.imag
+ elif data.imag > 0:
+ data = "%r+%rj" % (data.real, data.imag)
+ else:
+ data = "%r%rj" % (data.real, data.imag)
+ return self.represent_scalar("tag:yaml.org,2002:python/complex", data)
+
+ def represent_tuple(self, data):
+ return self.represent_sequence("tag:yaml.org,2002:python/tuple", data)
+
+ def represent_name(self, data):
+ name = "%s.%s" % (data.__module__, data.__name__)
+ return self.represent_scalar("tag:yaml.org,2002:python/name:" + name, "")
+
+ def represent_module(self, data):
+ return self.represent_scalar(
+ "tag:yaml.org,2002:python/module:" + data.__name__, ""
+ )
+
+ def represent_object(self, data):
+ # We use __reduce__ API to save the data. data.__reduce__ returns
+ # a tuple of length 2-5:
+ # (function, args, state, listitems, dictitems)
+
+ # For reconstructing, we calls function(*args), then set its state,
+ # listitems, and dictitems if they are not None.
+
+ # A special case is when function.__name__ == '__newobj__'. In this
+ # case we create the object with args[0].__new__(*args).
+
+ # Another special case is when __reduce__ returns a string - we don't
+ # support it.
+
+ # We produce a !!python/object, !!python/object/new or
+ # !!python/object/apply node.
+
+ cls = type(data)
+ if cls in copyreg.dispatch_table:
+ reduce = copyreg.dispatch_table[cls](data)
+ elif hasattr(data, "__reduce_ex__"):
+ reduce = data.__reduce_ex__(2)
+ elif hasattr(data, "__reduce__"):
+ reduce = data.__reduce__()
+ else:
+ raise RepresenterError("cannot represent an object", data)
+ reduce = (list(reduce) + [None] * 5)[:5]
+ function, args, state, listitems, dictitems = reduce
+ args = list(args)
+ if state is None:
+ state = {}
+ if listitems is not None:
+ listitems = list(listitems)
+ if dictitems is not None:
+ dictitems = dict(dictitems)
+ if function.__name__ == "__newobj__":
+ function = args[0]
+ args = args[1:]
+ tag = "tag:yaml.org,2002:python/object/new:"
+ newobj = True
+ else:
+ tag = "tag:yaml.org,2002:python/object/apply:"
+ newobj = False
+ function_name = "%s.%s" % (function.__module__, function.__name__)
+ if (
+ not args
+ and not listitems
+ and not dictitems
+ and isinstance(state, dict)
+ and newobj
+ ):
+ return self.represent_mapping(
+ "tag:yaml.org,2002:python/object:" + function_name, state
+ )
+ if not listitems and not dictitems and isinstance(state, dict) and not state:
+ return self.represent_sequence(tag + function_name, args)
+ value = {}
+ if args:
+ value["args"] = args
+ if state or not isinstance(state, dict):
+ value["state"] = state
+ if listitems:
+ value["listitems"] = listitems
+ if dictitems:
+ value["dictitems"] = dictitems
+ return self.represent_mapping(tag + function_name, value)
+
+ def represent_ordered_dict(self, data):
+ # Provide uniform representation across different Python versions.
+ data_type = type(data)
+ tag = "tag:yaml.org,2002:python/object/apply:%s.%s" % (
+ data_type.__module__,
+ data_type.__name__,
+ )
+ items = [[key, value] for key, value in data.items()]
+ return self.represent_sequence(tag, [items])
+
+
+Representer.add_representer(complex, Representer.represent_complex)
+
+Representer.add_representer(tuple, Representer.represent_tuple)
+
+Representer.add_multi_representer(type, Representer.represent_name)
+
+Representer.add_representer(collections.OrderedDict, Representer.represent_ordered_dict)
+
+Representer.add_representer(types.FunctionType, Representer.represent_name)
+
+Representer.add_representer(types.BuiltinFunctionType, Representer.represent_name)
+
+Representer.add_representer(types.ModuleType, Representer.represent_module)
+
+Representer.add_multi_representer(object, Representer.represent_object)
diff --git a/openlane/dependencies/includedyaml/resolver.py b/openlane/dependencies/includedyaml/resolver.py
new file mode 100644
index 0000000..6145d0d
--- /dev/null
+++ b/openlane/dependencies/includedyaml/resolver.py
@@ -0,0 +1,245 @@
+__all__ = ["BaseResolver", "Resolver"]
+
+from .error import *
+from .nodes import *
+
+import re
+
+
+class ResolverError(YAMLError):
+ pass
+
+
+class BaseResolver:
+
+ DEFAULT_SCALAR_TAG = "tag:yaml.org,2002:str"
+ DEFAULT_SEQUENCE_TAG = "tag:yaml.org,2002:seq"
+ DEFAULT_MAPPING_TAG = "tag:yaml.org,2002:map"
+
+ yaml_implicit_resolvers = {}
+ yaml_path_resolvers = {}
+
+ def __init__(self):
+ self.resolver_exact_paths = []
+ self.resolver_prefix_paths = []
+
+ @classmethod
+ def add_implicit_resolver(cls, tag, regexp, first):
+ if not "yaml_implicit_resolvers" in cls.__dict__:
+ implicit_resolvers = {}
+ for key in cls.yaml_implicit_resolvers:
+ implicit_resolvers[key] = cls.yaml_implicit_resolvers[key][:]
+ cls.yaml_implicit_resolvers = implicit_resolvers
+ if first is None:
+ first = [None]
+ for ch in first:
+ cls.yaml_implicit_resolvers.setdefault(ch, []).append((tag, regexp))
+
+ @classmethod
+ def add_path_resolver(cls, tag, path, kind=None):
+ # Note: `add_path_resolver` is experimental. The API could be changed.
+ # `new_path` is a pattern that is matched against the path from the
+ # root to the node that is being considered. `node_path` elements are
+ # tuples `(node_check, index_check)`. `node_check` is a node class:
+ # `ScalarNode`, `SequenceNode`, `MappingNode` or `None`. `None`
+ # matches any kind of a node. `index_check` could be `None`, a boolean
+ # value, a string value, or a number. `None` and `False` match against
+ # any _value_ of sequence and mapping nodes. `True` matches against
+ # any _key_ of a mapping node. A string `index_check` matches against
+ # a mapping value that corresponds to a scalar key which content is
+ # equal to the `index_check` value. An integer `index_check` matches
+ # against a sequence value with the index equal to `index_check`.
+ if not "yaml_path_resolvers" in cls.__dict__:
+ cls.yaml_path_resolvers = cls.yaml_path_resolvers.copy()
+ new_path = []
+ for element in path:
+ if isinstance(element, (list, tuple)):
+ if len(element) == 2:
+ node_check, index_check = element
+ elif len(element) == 1:
+ node_check = element[0]
+ index_check = True
+ else:
+ raise ResolverError("Invalid path element: %s" % element)
+ else:
+ node_check = None
+ index_check = element
+ if node_check is str:
+ node_check = ScalarNode
+ elif node_check is list:
+ node_check = SequenceNode
+ elif node_check is dict:
+ node_check = MappingNode
+ elif (
+ node_check not in [ScalarNode, SequenceNode, MappingNode]
+ and not isinstance(node_check, str)
+ and node_check is not None
+ ):
+ raise ResolverError("Invalid node checker: %s" % node_check)
+ if not isinstance(index_check, (str, int)) and index_check is not None:
+ raise ResolverError("Invalid index checker: %s" % index_check)
+ new_path.append((node_check, index_check))
+ if kind is str:
+ kind = ScalarNode
+ elif kind is list:
+ kind = SequenceNode
+ elif kind is dict:
+ kind = MappingNode
+ elif kind not in [ScalarNode, SequenceNode, MappingNode] and kind is not None:
+ raise ResolverError("Invalid node kind: %s" % kind)
+ cls.yaml_path_resolvers[tuple(new_path), kind] = tag
+
+ def descend_resolver(self, current_node, current_index):
+ if not self.yaml_path_resolvers:
+ return
+ exact_paths = {}
+ prefix_paths = []
+ if current_node:
+ depth = len(self.resolver_prefix_paths)
+ for path, kind in self.resolver_prefix_paths[-1]:
+ if self.check_resolver_prefix(
+ depth, path, kind, current_node, current_index
+ ):
+ if len(path) > depth:
+ prefix_paths.append((path, kind))
+ else:
+ exact_paths[kind] = self.yaml_path_resolvers[path, kind]
+ else:
+ for path, kind in self.yaml_path_resolvers:
+ if not path:
+ exact_paths[kind] = self.yaml_path_resolvers[path, kind]
+ else:
+ prefix_paths.append((path, kind))
+ self.resolver_exact_paths.append(exact_paths)
+ self.resolver_prefix_paths.append(prefix_paths)
+
+ def ascend_resolver(self):
+ if not self.yaml_path_resolvers:
+ return
+ self.resolver_exact_paths.pop()
+ self.resolver_prefix_paths.pop()
+
+ def check_resolver_prefix(self, depth, path, kind, current_node, current_index):
+ node_check, index_check = path[depth - 1]
+ if isinstance(node_check, str):
+ if current_node.tag != node_check:
+ return
+ elif node_check is not None:
+ if not isinstance(current_node, node_check):
+ return
+ if index_check is True and current_index is not None:
+ return
+ if (index_check is False or index_check is None) and current_index is None:
+ return
+ if isinstance(index_check, str):
+ if not (
+ isinstance(current_index, ScalarNode)
+ and index_check == current_index.value
+ ):
+ return
+ elif isinstance(index_check, int) and not isinstance(index_check, bool):
+ if index_check != current_index:
+ return
+ return True
+
+ def resolve(self, kind, value, implicit):
+ if kind is ScalarNode and implicit[0]:
+ if value == "":
+ resolvers = self.yaml_implicit_resolvers.get("", [])
+ else:
+ resolvers = self.yaml_implicit_resolvers.get(value[0], [])
+ wildcard_resolvers = self.yaml_implicit_resolvers.get(None, [])
+ for tag, regexp in resolvers + wildcard_resolvers:
+ if regexp.match(value):
+ return tag
+ implicit = implicit[1]
+ if self.yaml_path_resolvers:
+ exact_paths = self.resolver_exact_paths[-1]
+ if kind in exact_paths:
+ return exact_paths[kind]
+ if None in exact_paths:
+ return exact_paths[None]
+ if kind is ScalarNode:
+ return self.DEFAULT_SCALAR_TAG
+ elif kind is SequenceNode:
+ return self.DEFAULT_SEQUENCE_TAG
+ elif kind is MappingNode:
+ return self.DEFAULT_MAPPING_TAG
+
+
+class Resolver(BaseResolver):
+ pass
+
+
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:bool",
+ re.compile(
+ r"""^(?:yes|Yes|YES|no|No|NO
+ |true|True|TRUE|false|False|FALSE
+ |on|On|ON|off|Off|OFF)$""",
+ re.X,
+ ),
+ list("yYnNtTfFoO"),
+)
+
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:float",
+ re.compile(
+ r"""^(?:[-+]?(?:[0-9][0-9_]*)\.[0-9_]*(?:[eE][-+][0-9]+)?
+ |\.[0-9][0-9_]*(?:[eE][-+][0-9]+)?
+ |[-+]?[0-9][0-9_]*(?::[0-5]?[0-9])+\.[0-9_]*
+ |[-+]?\.(?:inf|Inf|INF)
+ |\.(?:nan|NaN|NAN))$""",
+ re.X,
+ ),
+ list("-+0123456789."),
+)
+
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:int",
+ re.compile(
+ r"""^(?:[-+]?0b[0-1_]+
+ |[-+]?0[0-7_]+
+ |[-+]?(?:0|[1-9][0-9_]*)
+ |[-+]?0x[0-9a-fA-F_]+
+ |[-+]?[1-9][0-9_]*(?::[0-5]?[0-9])+)$""",
+ re.X,
+ ),
+ list("-+0123456789"),
+)
+
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:merge", re.compile(r"^(?:<<)$"), ["<"]
+)
+
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:null",
+ re.compile(
+ r"""^(?: ~
+ |null|Null|NULL
+ | )$""",
+ re.X,
+ ),
+ ["~", "n", "N", ""],
+)
+
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:timestamp",
+ re.compile(
+ r"""^(?:[0-9][0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9]
+ |[0-9][0-9][0-9][0-9] -[0-9][0-9]? -[0-9][0-9]?
+ (?:[Tt]|[ \t]+)[0-9][0-9]?
+ :[0-9][0-9] :[0-9][0-9] (?:\.[0-9]*)?
+ (?:[ \t]*(?:Z|[-+][0-9][0-9]?(?::[0-9][0-9])?))?)$""",
+ re.X,
+ ),
+ list("0123456789"),
+)
+
+Resolver.add_implicit_resolver("tag:yaml.org,2002:value", re.compile(r"^(?:=)$"), ["="])
+
+# The following resolver is only for documentation purposes. It cannot work
+# because plain scalars cannot start with '!', '&', or '*'.
+Resolver.add_implicit_resolver(
+ "tag:yaml.org,2002:yaml", re.compile(r"^(?:!|&|\*)$"), list("!&*")
+)
diff --git a/openlane/dependencies/includedyaml/scanner.py b/openlane/dependencies/includedyaml/scanner.py
new file mode 100644
index 0000000..6aafac6
--- /dev/null
+++ b/openlane/dependencies/includedyaml/scanner.py
@@ -0,0 +1,1555 @@
+# Scanner produces tokens of the following types:
+# STREAM-START
+# STREAM-END
+# DIRECTIVE(name, value)
+# DOCUMENT-START
+# DOCUMENT-END
+# BLOCK-SEQUENCE-START
+# BLOCK-MAPPING-START
+# BLOCK-END
+# FLOW-SEQUENCE-START
+# FLOW-MAPPING-START
+# FLOW-SEQUENCE-END
+# FLOW-MAPPING-END
+# BLOCK-ENTRY
+# FLOW-ENTRY
+# KEY
+# VALUE
+# ALIAS(value)
+# ANCHOR(value)
+# TAG(value)
+# SCALAR(value, plain, style)
+#
+# Read comments in the Scanner code for more details.
+#
+
+__all__ = ["Scanner", "ScannerError"]
+
+from .error import MarkedYAMLError
+from .tokens import *
+
+
+class ScannerError(MarkedYAMLError):
+ pass
+
+
+class SimpleKey:
+ # See below simple keys treatment.
+
+ def __init__(self, token_number, required, index, line, column, mark):
+ self.token_number = token_number
+ self.required = required
+ self.index = index
+ self.line = line
+ self.column = column
+ self.mark = mark
+
+
+class Scanner:
+ def __init__(self):
+ """Initialize the scanner."""
+ # It is assumed that Scanner and Reader will have a common descendant.
+ # Reader do the dirty work of checking for BOM and converting the
+ # input data to Unicode. It also adds NUL to the end.
+ #
+ # Reader supports the following methods
+ # self.peek(i=0) # peek the next i-th character
+ # self.prefix(l=1) # peek the next l characters
+ # self.forward(l=1) # read the next l characters and move the pointer.
+
+ # Had we reached the end of the stream?
+ self.done = False
+
+ # The number of unclosed '{' and '['. `flow_level == 0` means block
+ # context.
+ self.flow_level = 0
+
+ # List of processed tokens that are not yet emitted.
+ self.tokens = []
+
+ # Add the STREAM-START token.
+ self.fetch_stream_start()
+
+ # Number of tokens that were emitted through the `get_token` method.
+ self.tokens_taken = 0
+
+ # The current indentation level.
+ self.indent = -1
+
+ # Past indentation levels.
+ self.indents = []
+
+ # Variables related to simple keys treatment.
+
+ # A simple key is a key that is not denoted by the '?' indicator.
+ # Example of simple keys:
+ # ---
+ # block simple key: value
+ # ? not a simple key:
+ # : { flow simple key: value }
+ # We emit the KEY token before all keys, so when we find a potential
+ # simple key, we try to locate the corresponding ':' indicator.
+ # Simple keys should be limited to a single line and 1024 characters.
+
+ # Can a simple key start at the current position? A simple key may
+ # start:
+ # - at the beginning of the line, not counting indentation spaces
+ # (in block context),
+ # - after '{', '[', ',' (in the flow context),
+ # - after '?', ':', '-' (in the block context).
+ # In the block context, this flag also signifies if a block collection
+ # may start at the current position.
+ self.allow_simple_key = True
+
+ # Keep track of possible simple keys. This is a dictionary. The key
+ # is `flow_level`; there can be no more that one possible simple key
+ # for each level. The value is a SimpleKey record:
+ # (token_number, required, index, line, column, mark)
+ # A simple key may start with ALIAS, ANCHOR, TAG, SCALAR(flow),
+ # '[', or '{' tokens.
+ self.possible_simple_keys = {}
+
+ # Public methods.
+
+ def check_token(self, *choices):
+ # Check if the next token is one of the given types.
+ while self.need_more_tokens():
+ self.fetch_more_tokens()
+ if self.tokens:
+ if not choices:
+ return True
+ for choice in choices:
+ if isinstance(self.tokens[0], choice):
+ return True
+ return False
+
+ def peek_token(self):
+ # Return the next token, but do not delete if from the queue.
+ # Return None if no more tokens.
+ while self.need_more_tokens():
+ self.fetch_more_tokens()
+ if self.tokens:
+ return self.tokens[0]
+ else:
+ return None
+
+ def get_token(self):
+ # Return the next token.
+ while self.need_more_tokens():
+ self.fetch_more_tokens()
+ if self.tokens:
+ self.tokens_taken += 1
+ return self.tokens.pop(0)
+
+ # Private methods.
+
+ def need_more_tokens(self):
+ if self.done:
+ return False
+ if not self.tokens:
+ return True
+ # The current token may be a potential simple key, so we
+ # need to look further.
+ self.stale_possible_simple_keys()
+ if self.next_possible_simple_key() == self.tokens_taken:
+ return True
+
+ def fetch_more_tokens(self):
+
+ # Eat whitespaces and comments until we reach the next token.
+ self.scan_to_next_token()
+
+ # Remove obsolete possible simple keys.
+ self.stale_possible_simple_keys()
+
+ # Compare the current indentation and column. It may add some tokens
+ # and decrease the current indentation level.
+ self.unwind_indent(self.column)
+
+ # Peek the next character.
+ ch = self.peek()
+
+ # Is it the end of stream?
+ if ch == "\0":
+ return self.fetch_stream_end()
+
+ # Is it a directive?
+ if ch == "%" and self.check_directive():
+ return self.fetch_directive()
+
+ # Is it the document start?
+ if ch == "-" and self.check_document_start():
+ return self.fetch_document_start()
+
+ # Is it the document end?
+ if ch == "." and self.check_document_end():
+ return self.fetch_document_end()
+
+ # TODO: support for BOM within a stream.
+ # if ch == '\uFEFF':
+ # return self.fetch_bom() <-- issue BOMToken
+
+ # Note: the order of the following checks is NOT significant.
+
+ # Is it the flow sequence start indicator?
+ if ch == "[":
+ return self.fetch_flow_sequence_start()
+
+ # Is it the flow mapping start indicator?
+ if ch == "{":
+ return self.fetch_flow_mapping_start()
+
+ # Is it the flow sequence end indicator?
+ if ch == "]":
+ return self.fetch_flow_sequence_end()
+
+ # Is it the flow mapping end indicator?
+ if ch == "}":
+ return self.fetch_flow_mapping_end()
+
+ # Is it the flow entry indicator?
+ if ch == ",":
+ return self.fetch_flow_entry()
+
+ # Is it the block entry indicator?
+ if ch == "-" and self.check_block_entry():
+ return self.fetch_block_entry()
+
+ # Is it the key indicator?
+ if ch == "?" and self.check_key():
+ return self.fetch_key()
+
+ # Is it the value indicator?
+ if ch == ":" and self.check_value():
+ return self.fetch_value()
+
+ # Is it an alias?
+ if ch == "*":
+ return self.fetch_alias()
+
+ # Is it an anchor?
+ if ch == "&":
+ return self.fetch_anchor()
+
+ # Is it a tag?
+ if ch == "!":
+ return self.fetch_tag()
+
+ # Is it a literal scalar?
+ if ch == "|" and not self.flow_level:
+ return self.fetch_literal()
+
+ # Is it a folded scalar?
+ if ch == ">" and not self.flow_level:
+ return self.fetch_folded()
+
+ # Is it a single quoted scalar?
+ if ch == "'":
+ return self.fetch_single()
+
+ # Is it a double quoted scalar?
+ if ch == '"':
+ return self.fetch_double()
+
+ # It must be a plain scalar then.
+ if self.check_plain():
+ return self.fetch_plain()
+
+ # No? It's an error. Let's produce a nice error message.
+ raise ScannerError(
+ "while scanning for the next token",
+ None,
+ "found character %r that cannot start any token" % ch,
+ self.get_mark(),
+ )
+
+ # Simple keys treatment.
+
+ def next_possible_simple_key(self):
+ # Return the number of the nearest possible simple key. Actually we
+ # don't need to loop through the whole dictionary. We may replace it
+ # with the following code:
+ # if not self.possible_simple_keys:
+ # return None
+ # return self.possible_simple_keys[
+ # min(self.possible_simple_keys.keys())].token_number
+ min_token_number = None
+ for level in self.possible_simple_keys:
+ key = self.possible_simple_keys[level]
+ if min_token_number is None or key.token_number < min_token_number:
+ min_token_number = key.token_number
+ return min_token_number
+
+ def stale_possible_simple_keys(self):
+ # Remove entries that are no longer possible simple keys. According to
+ # the YAML specification, simple keys
+ # - should be limited to a single line,
+ # - should be no longer than 1024 characters.
+ # Disabling this procedure will allow simple keys of any length and
+ # height (may cause problems if indentation is broken though).
+ for level in list(self.possible_simple_keys):
+ key = self.possible_simple_keys[level]
+ if key.line != self.line or self.index - key.index > 1024:
+ if key.required:
+ raise ScannerError(
+ "while scanning a simple key",
+ key.mark,
+ "could not find expected ':'",
+ self.get_mark(),
+ )
+ del self.possible_simple_keys[level]
+
+ def save_possible_simple_key(self):
+ # The next token may start a simple key. We check if it's possible
+ # and save its position. This function is called for
+ # ALIAS, ANCHOR, TAG, SCALAR(flow), '[', and '{'.
+
+ # Check if a simple key is required at the current position.
+ required = not self.flow_level and self.indent == self.column
+
+ # The next token might be a simple key. Let's save it's number and
+ # position.
+ if self.allow_simple_key:
+ self.remove_possible_simple_key()
+ token_number = self.tokens_taken + len(self.tokens)
+ key = SimpleKey(
+ token_number,
+ required,
+ self.index,
+ self.line,
+ self.column,
+ self.get_mark(),
+ )
+ self.possible_simple_keys[self.flow_level] = key
+
+ def remove_possible_simple_key(self):
+ # Remove the saved possible key position at the current flow level.
+ if self.flow_level in self.possible_simple_keys:
+ key = self.possible_simple_keys[self.flow_level]
+
+ if key.required:
+ raise ScannerError(
+ "while scanning a simple key",
+ key.mark,
+ "could not find expected ':'",
+ self.get_mark(),
+ )
+
+ del self.possible_simple_keys[self.flow_level]
+
+ # Indentation functions.
+
+ def unwind_indent(self, column):
+
+ ## In flow context, tokens should respect indentation.
+ ## Actually the condition should be `self.indent >= column` according to
+ ## the spec. But this condition will prohibit intuitively correct
+ ## constructions such as
+ ## key : {
+ ## }
+ # if self.flow_level and self.indent > column:
+ # raise ScannerError(None, None,
+ # "invalid indentation or unclosed '[' or '{'",
+ # self.get_mark())
+
+ # In the flow context, indentation is ignored. We make the scanner less
+ # restrictive then specification requires.
+ if self.flow_level:
+ return
+
+ # In block context, we may need to issue the BLOCK-END tokens.
+ while self.indent > column:
+ mark = self.get_mark()
+ self.indent = self.indents.pop()
+ self.tokens.append(BlockEndToken(mark, mark))
+
+ def add_indent(self, column):
+ # Check if we need to increase indentation.
+ if self.indent < column:
+ self.indents.append(self.indent)
+ self.indent = column
+ return True
+ return False
+
+ # Fetchers.
+
+ def fetch_stream_start(self):
+ # We always add STREAM-START as the first token and STREAM-END as the
+ # last token.
+
+ # Read the token.
+ mark = self.get_mark()
+
+ # Add STREAM-START.
+ self.tokens.append(StreamStartToken(mark, mark, encoding=self.encoding))
+
+ def fetch_stream_end(self):
+
+ # Set the current indentation to -1.
+ self.unwind_indent(-1)
+
+ # Reset simple keys.
+ self.remove_possible_simple_key()
+ self.allow_simple_key = False
+ self.possible_simple_keys = {}
+
+ # Read the token.
+ mark = self.get_mark()
+
+ # Add STREAM-END.
+ self.tokens.append(StreamEndToken(mark, mark))
+
+ # The steam is finished.
+ self.done = True
+
+ def fetch_directive(self):
+
+ # Set the current indentation to -1.
+ self.unwind_indent(-1)
+
+ # Reset simple keys.
+ self.remove_possible_simple_key()
+ self.allow_simple_key = False
+
+ # Scan and add DIRECTIVE.
+ self.tokens.append(self.scan_directive())
+
+ def fetch_document_start(self):
+ self.fetch_document_indicator(DocumentStartToken)
+
+ def fetch_document_end(self):
+ self.fetch_document_indicator(DocumentEndToken)
+
+ def fetch_document_indicator(self, TokenClass):
+
+ # Set the current indentation to -1.
+ self.unwind_indent(-1)
+
+ # Reset simple keys. Note that there could not be a block collection
+ # after '---'.
+ self.remove_possible_simple_key()
+ self.allow_simple_key = False
+
+ # Add DOCUMENT-START or DOCUMENT-END.
+ start_mark = self.get_mark()
+ self.forward(3)
+ end_mark = self.get_mark()
+ self.tokens.append(TokenClass(start_mark, end_mark))
+
+ def fetch_flow_sequence_start(self):
+ self.fetch_flow_collection_start(FlowSequenceStartToken)
+
+ def fetch_flow_mapping_start(self):
+ self.fetch_flow_collection_start(FlowMappingStartToken)
+
+ def fetch_flow_collection_start(self, TokenClass):
+
+ # '[' and '{' may start a simple key.
+ self.save_possible_simple_key()
+
+ # Increase the flow level.
+ self.flow_level += 1
+
+ # Simple keys are allowed after '[' and '{'.
+ self.allow_simple_key = True
+
+ # Add FLOW-SEQUENCE-START or FLOW-MAPPING-START.
+ start_mark = self.get_mark()
+ self.forward()
+ end_mark = self.get_mark()
+ self.tokens.append(TokenClass(start_mark, end_mark))
+
+ def fetch_flow_sequence_end(self):
+ self.fetch_flow_collection_end(FlowSequenceEndToken)
+
+ def fetch_flow_mapping_end(self):
+ self.fetch_flow_collection_end(FlowMappingEndToken)
+
+ def fetch_flow_collection_end(self, TokenClass):
+
+ # Reset possible simple key on the current level.
+ self.remove_possible_simple_key()
+
+ # Decrease the flow level.
+ self.flow_level -= 1
+
+ # No simple keys after ']' or '}'.
+ self.allow_simple_key = False
+
+ # Add FLOW-SEQUENCE-END or FLOW-MAPPING-END.
+ start_mark = self.get_mark()
+ self.forward()
+ end_mark = self.get_mark()
+ self.tokens.append(TokenClass(start_mark, end_mark))
+
+ def fetch_flow_entry(self):
+
+ # Simple keys are allowed after ','.
+ self.allow_simple_key = True
+
+ # Reset possible simple key on the current level.
+ self.remove_possible_simple_key()
+
+ # Add FLOW-ENTRY.
+ start_mark = self.get_mark()
+ self.forward()
+ end_mark = self.get_mark()
+ self.tokens.append(FlowEntryToken(start_mark, end_mark))
+
+ def fetch_block_entry(self):
+
+ # Block context needs additional checks.
+ if not self.flow_level:
+
+ # Are we allowed to start a new entry?
+ if not self.allow_simple_key:
+ raise ScannerError(
+ None, None, "sequence entries are not allowed here", self.get_mark()
+ )
+
+ # We may need to add BLOCK-SEQUENCE-START.
+ if self.add_indent(self.column):
+ mark = self.get_mark()
+ self.tokens.append(BlockSequenceStartToken(mark, mark))
+
+ # It's an error for the block entry to occur in the flow context,
+ # but we let the parser detect this.
+ else:
+ pass
+
+ # Simple keys are allowed after '-'.
+ self.allow_simple_key = True
+
+ # Reset possible simple key on the current level.
+ self.remove_possible_simple_key()
+
+ # Add BLOCK-ENTRY.
+ start_mark = self.get_mark()
+ self.forward()
+ end_mark = self.get_mark()
+ self.tokens.append(BlockEntryToken(start_mark, end_mark))
+
+ def fetch_key(self):
+
+ # Block context needs additional checks.
+ if not self.flow_level:
+
+ # Are we allowed to start a key (not necessary a simple)?
+ if not self.allow_simple_key:
+ raise ScannerError(
+ None, None, "mapping keys are not allowed here", self.get_mark()
+ )
+
+ # We may need to add BLOCK-MAPPING-START.
+ if self.add_indent(self.column):
+ mark = self.get_mark()
+ self.tokens.append(BlockMappingStartToken(mark, mark))
+
+ # Simple keys are allowed after '?' in the block context.
+ self.allow_simple_key = not self.flow_level
+
+ # Reset possible simple key on the current level.
+ self.remove_possible_simple_key()
+
+ # Add KEY.
+ start_mark = self.get_mark()
+ self.forward()
+ end_mark = self.get_mark()
+ self.tokens.append(KeyToken(start_mark, end_mark))
+
+ def fetch_value(self):
+
+ # Do we determine a simple key?
+ if self.flow_level in self.possible_simple_keys:
+
+ # Add KEY.
+ key = self.possible_simple_keys[self.flow_level]
+ del self.possible_simple_keys[self.flow_level]
+ self.tokens.insert(
+ key.token_number - self.tokens_taken, KeyToken(key.mark, key.mark)
+ )
+
+ # If this key starts a new block mapping, we need to add
+ # BLOCK-MAPPING-START.
+ if not self.flow_level:
+ if self.add_indent(key.column):
+ self.tokens.insert(
+ key.token_number - self.tokens_taken,
+ BlockMappingStartToken(key.mark, key.mark),
+ )
+
+ # There cannot be two simple keys one after another.
+ self.allow_simple_key = False
+
+ # It must be a part of a complex key.
+ else:
+
+ # Block context needs additional checks.
+ # (Do we really need them? They will be caught by the parser
+ # anyway.)
+ if not self.flow_level:
+
+ # We are allowed to start a complex value if and only if
+ # we can start a simple key.
+ if not self.allow_simple_key:
+ raise ScannerError(
+ None,
+ None,
+ "mapping values are not allowed here",
+ self.get_mark(),
+ )
+
+ # If this value starts a new block mapping, we need to add
+ # BLOCK-MAPPING-START. It will be detected as an error later by
+ # the parser.
+ if not self.flow_level:
+ if self.add_indent(self.column):
+ mark = self.get_mark()
+ self.tokens.append(BlockMappingStartToken(mark, mark))
+
+ # Simple keys are allowed after ':' in the block context.
+ self.allow_simple_key = not self.flow_level
+
+ # Reset possible simple key on the current level.
+ self.remove_possible_simple_key()
+
+ # Add VALUE.
+ start_mark = self.get_mark()
+ self.forward()
+ end_mark = self.get_mark()
+ self.tokens.append(ValueToken(start_mark, end_mark))
+
+ def fetch_alias(self):
+
+ # ALIAS could be a simple key.
+ self.save_possible_simple_key()
+
+ # No simple keys after ALIAS.
+ self.allow_simple_key = False
+
+ # Scan and add ALIAS.
+ self.tokens.append(self.scan_anchor(AliasToken))
+
+ def fetch_anchor(self):
+
+ # ANCHOR could start a simple key.
+ self.save_possible_simple_key()
+
+ # No simple keys after ANCHOR.
+ self.allow_simple_key = False
+
+ # Scan and add ANCHOR.
+ self.tokens.append(self.scan_anchor(AnchorToken))
+
+ def fetch_tag(self):
+
+ # TAG could start a simple key.
+ self.save_possible_simple_key()
+
+ # No simple keys after TAG.
+ self.allow_simple_key = False
+
+ # Scan and add TAG.
+ self.tokens.append(self.scan_tag())
+
+ def fetch_literal(self):
+ self.fetch_block_scalar(style="|")
+
+ def fetch_folded(self):
+ self.fetch_block_scalar(style=">")
+
+ def fetch_block_scalar(self, style):
+
+ # A simple key may follow a block scalar.
+ self.allow_simple_key = True
+
+ # Reset possible simple key on the current level.
+ self.remove_possible_simple_key()
+
+ # Scan and add SCALAR.
+ self.tokens.append(self.scan_block_scalar(style))
+
+ def fetch_single(self):
+ self.fetch_flow_scalar(style="'")
+
+ def fetch_double(self):
+ self.fetch_flow_scalar(style='"')
+
+ def fetch_flow_scalar(self, style):
+
+ # A flow scalar could be a simple key.
+ self.save_possible_simple_key()
+
+ # No simple keys after flow scalars.
+ self.allow_simple_key = False
+
+ # Scan and add SCALAR.
+ self.tokens.append(self.scan_flow_scalar(style))
+
+ def fetch_plain(self):
+
+ # A plain scalar could be a simple key.
+ self.save_possible_simple_key()
+
+ # No simple keys after plain scalars. But note that `scan_plain` will
+ # change this flag if the scan is finished at the beginning of the
+ # line.
+ self.allow_simple_key = False
+
+ # Scan and add SCALAR. May change `allow_simple_key`.
+ self.tokens.append(self.scan_plain())
+
+ # Checkers.
+
+ def check_directive(self):
+
+ # DIRECTIVE: ^ '%' ...
+ # The '%' indicator is already checked.
+ if self.column == 0:
+ return True
+
+ def check_document_start(self):
+
+ # DOCUMENT-START: ^ '---' (' '|'\n')
+ if self.column == 0:
+ if self.prefix(3) == "---" and self.peek(3) in "\0 \t\r\n\x85\u2028\u2029":
+ return True
+
+ def check_document_end(self):
+
+ # DOCUMENT-END: ^ '...' (' '|'\n')
+ if self.column == 0:
+ if self.prefix(3) == "..." and self.peek(3) in "\0 \t\r\n\x85\u2028\u2029":
+ return True
+
+ def check_block_entry(self):
+
+ # BLOCK-ENTRY: '-' (' '|'\n')
+ return self.peek(1) in "\0 \t\r\n\x85\u2028\u2029"
+
+ def check_key(self):
+
+ # KEY(flow context): '?'
+ if self.flow_level:
+ return True
+
+ # KEY(block context): '?' (' '|'\n')
+ else:
+ return self.peek(1) in "\0 \t\r\n\x85\u2028\u2029"
+
+ def check_value(self):
+
+ # VALUE(flow context): ':'
+ if self.flow_level:
+ return True
+
+ # VALUE(block context): ':' (' '|'\n')
+ else:
+ return self.peek(1) in "\0 \t\r\n\x85\u2028\u2029"
+
+ def check_plain(self):
+
+ # A plain scalar may start with any non-space character except:
+ # '-', '?', ':', ',', '[', ']', '{', '}',
+ # '#', '&', '*', '!', '|', '>', '\'', '\"',
+ # '%', '@', '`'.
+ #
+ # It may also start with
+ # '-', '?', ':'
+ # if it is followed by a non-space character.
+ #
+ # Note that we limit the last rule to the block context (except the
+ # '-' character) because we want the flow context to be space
+ # independent.
+ ch = self.peek()
+ return ch not in "\0 \t\r\n\x85\u2028\u2029-?:,[]{}#&*!|>'\"%@`" or (
+ self.peek(1) not in "\0 \t\r\n\x85\u2028\u2029"
+ and (ch == "-" or (not self.flow_level and ch in "?:"))
+ )
+
+ # Scanners.
+
+ def scan_to_next_token(self):
+ # We ignore spaces, line breaks and comments.
+ # If we find a line break in the block context, we set the flag
+ # `allow_simple_key` on.
+ # The byte order mark is stripped if it's the first character in the
+ # stream. We do not yet support BOM inside the stream as the
+ # specification requires. Any such mark will be considered as a part
+ # of the document.
+ #
+ # TODO: We need to make tab handling rules more sane. A good rule is
+ # Tabs cannot precede tokens
+ # BLOCK-SEQUENCE-START, BLOCK-MAPPING-START, BLOCK-END,
+ # KEY(block), VALUE(block), BLOCK-ENTRY
+ # So the checking code is
+ # if <TAB>:
+ # self.allow_simple_keys = False
+ # We also need to add the check for `allow_simple_keys == True` to
+ # `unwind_indent` before issuing BLOCK-END.
+ # Scanners for block, flow, and plain scalars need to be modified.
+
+ if self.index == 0 and self.peek() == "\uFEFF":
+ self.forward()
+ found = False
+ while not found:
+ while self.peek() == " ":
+ self.forward()
+ if self.peek() == "#":
+ while self.peek() not in "\0\r\n\x85\u2028\u2029":
+ self.forward()
+ if self.scan_line_break():
+ if not self.flow_level:
+ self.allow_simple_key = True
+ else:
+ found = True
+
+ def scan_directive(self):
+ # See the specification for details.
+ start_mark = self.get_mark()
+ self.forward()
+ name = self.scan_directive_name(start_mark)
+ value = None
+ if name == "YAML":
+ value = self.scan_yaml_directive_value(start_mark)
+ end_mark = self.get_mark()
+ elif name == "TAG":
+ value = self.scan_tag_directive_value(start_mark)
+ end_mark = self.get_mark()
+ else:
+ end_mark = self.get_mark()
+ while self.peek() not in "\0\r\n\x85\u2028\u2029":
+ self.forward()
+ self.scan_directive_ignored_line(start_mark)
+ return DirectiveToken(name, value, start_mark, end_mark)
+
+ def scan_directive_name(self, start_mark):
+ # See the specification for details.
+ length = 0
+ ch = self.peek(length)
+ while "0" <= ch <= "9" or "A" <= ch <= "Z" or "a" <= ch <= "z" or ch in "-_":
+ length += 1
+ ch = self.peek(length)
+ if not length:
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected alphabetic or numeric character, but found %r" % ch,
+ self.get_mark(),
+ )
+ value = self.prefix(length)
+ self.forward(length)
+ ch = self.peek()
+ if ch not in "\0 \r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected alphabetic or numeric character, but found %r" % ch,
+ self.get_mark(),
+ )
+ return value
+
+ def scan_yaml_directive_value(self, start_mark):
+ # See the specification for details.
+ while self.peek() == " ":
+ self.forward()
+ major = self.scan_yaml_directive_number(start_mark)
+ if self.peek() != ".":
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected a digit or '.', but found %r" % self.peek(),
+ self.get_mark(),
+ )
+ self.forward()
+ minor = self.scan_yaml_directive_number(start_mark)
+ if self.peek() not in "\0 \r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected a digit or ' ', but found %r" % self.peek(),
+ self.get_mark(),
+ )
+ return (major, minor)
+
+ def scan_yaml_directive_number(self, start_mark):
+ # See the specification for details.
+ ch = self.peek()
+ if not ("0" <= ch <= "9"):
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected a digit, but found %r" % ch,
+ self.get_mark(),
+ )
+ length = 0
+ while "0" <= self.peek(length) <= "9":
+ length += 1
+ value = int(self.prefix(length))
+ self.forward(length)
+ return value
+
+ def scan_tag_directive_value(self, start_mark):
+ # See the specification for details.
+ while self.peek() == " ":
+ self.forward()
+ handle = self.scan_tag_directive_handle(start_mark)
+ while self.peek() == " ":
+ self.forward()
+ prefix = self.scan_tag_directive_prefix(start_mark)
+ return (handle, prefix)
+
+ def scan_tag_directive_handle(self, start_mark):
+ # See the specification for details.
+ value = self.scan_tag_handle("directive", start_mark)
+ ch = self.peek()
+ if ch != " ":
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected ' ', but found %r" % ch,
+ self.get_mark(),
+ )
+ return value
+
+ def scan_tag_directive_prefix(self, start_mark):
+ # See the specification for details.
+ value = self.scan_tag_uri("directive", start_mark)
+ ch = self.peek()
+ if ch not in "\0 \r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected ' ', but found %r" % ch,
+ self.get_mark(),
+ )
+ return value
+
+ def scan_directive_ignored_line(self, start_mark):
+ # See the specification for details.
+ while self.peek() == " ":
+ self.forward()
+ if self.peek() == "#":
+ while self.peek() not in "\0\r\n\x85\u2028\u2029":
+ self.forward()
+ ch = self.peek()
+ if ch not in "\0\r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a directive",
+ start_mark,
+ "expected a comment or a line break, but found %r" % ch,
+ self.get_mark(),
+ )
+ self.scan_line_break()
+
+ def scan_anchor(self, TokenClass):
+ # The specification does not restrict characters for anchors and
+ # aliases. This may lead to problems, for instance, the document:
+ # [ *alias, value ]
+ # can be interpreted in two ways, as
+ # [ "value" ]
+ # and
+ # [ *alias , "value" ]
+ # Therefore we restrict aliases to numbers and ASCII letters.
+ start_mark = self.get_mark()
+ indicator = self.peek()
+ if indicator == "*":
+ name = "alias"
+ else:
+ name = "anchor"
+ self.forward()
+ length = 0
+ ch = self.peek(length)
+ while "0" <= ch <= "9" or "A" <= ch <= "Z" or "a" <= ch <= "z" or ch in "-_":
+ length += 1
+ ch = self.peek(length)
+ if not length:
+ raise ScannerError(
+ "while scanning an %s" % name,
+ start_mark,
+ "expected alphabetic or numeric character, but found %r" % ch,
+ self.get_mark(),
+ )
+ value = self.prefix(length)
+ self.forward(length)
+ ch = self.peek()
+ if ch not in "\0 \t\r\n\x85\u2028\u2029?:,]}%@`":
+ raise ScannerError(
+ "while scanning an %s" % name,
+ start_mark,
+ "expected alphabetic or numeric character, but found %r" % ch,
+ self.get_mark(),
+ )
+ end_mark = self.get_mark()
+ return TokenClass(value, start_mark, end_mark)
+
+ def scan_tag(self):
+ # See the specification for details.
+ start_mark = self.get_mark()
+ ch = self.peek(1)
+ if ch == "<":
+ handle = None
+ self.forward(2)
+ suffix = self.scan_tag_uri("tag", start_mark)
+ if self.peek() != ">":
+ raise ScannerError(
+ "while parsing a tag",
+ start_mark,
+ "expected '>', but found %r" % self.peek(),
+ self.get_mark(),
+ )
+ self.forward()
+ elif ch in "\0 \t\r\n\x85\u2028\u2029":
+ handle = None
+ suffix = "!"
+ self.forward()
+ else:
+ length = 1
+ use_handle = False
+ while ch not in "\0 \r\n\x85\u2028\u2029":
+ if ch == "!":
+ use_handle = True
+ break
+ length += 1
+ ch = self.peek(length)
+ handle = "!"
+ if use_handle:
+ handle = self.scan_tag_handle("tag", start_mark)
+ else:
+ handle = "!"
+ self.forward()
+ suffix = self.scan_tag_uri("tag", start_mark)
+ ch = self.peek()
+ if ch not in "\0 \r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a tag",
+ start_mark,
+ "expected ' ', but found %r" % ch,
+ self.get_mark(),
+ )
+ value = (handle, suffix)
+ end_mark = self.get_mark()
+ return TagToken(value, start_mark, end_mark)
+
+ def scan_block_scalar(self, style):
+ # See the specification for details.
+
+ if style == ">":
+ folded = True
+ else:
+ folded = False
+
+ chunks = []
+ start_mark = self.get_mark()
+
+ # Scan the header.
+ self.forward()
+ chomping, increment = self.scan_block_scalar_indicators(start_mark)
+ self.scan_block_scalar_ignored_line(start_mark)
+
+ # Determine the indentation level and go to the first non-empty line.
+ min_indent = self.indent + 1
+ if min_indent < 1:
+ min_indent = 1
+ if increment is None:
+ breaks, max_indent, end_mark = self.scan_block_scalar_indentation()
+ indent = max(min_indent, max_indent)
+ else:
+ indent = min_indent + increment - 1
+ breaks, end_mark = self.scan_block_scalar_breaks(indent)
+ line_break = ""
+
+ # Scan the inner part of the block scalar.
+ while self.column == indent and self.peek() != "\0":
+ chunks.extend(breaks)
+ leading_non_space = self.peek() not in " \t"
+ length = 0
+ while self.peek(length) not in "\0\r\n\x85\u2028\u2029":
+ length += 1
+ chunks.append(self.prefix(length))
+ self.forward(length)
+ line_break = self.scan_line_break()
+ breaks, end_mark = self.scan_block_scalar_breaks(indent)
+ if self.column == indent and self.peek() != "\0":
+
+ # Unfortunately, folding rules are ambiguous.
+ #
+ # This is the folding according to the specification:
+
+ if (
+ folded
+ and line_break == "\n"
+ and leading_non_space
+ and self.peek() not in " \t"
+ ):
+ if not breaks:
+ chunks.append(" ")
+ else:
+ chunks.append(line_break)
+
+ # This is Clark Evans's interpretation (also in the spec
+ # examples):
+ #
+ # if folded and line_break == '\n':
+ # if not breaks:
+ # if self.peek() not in ' \t':
+ # chunks.append(' ')
+ # else:
+ # chunks.append(line_break)
+ # else:
+ # chunks.append(line_break)
+ else:
+ break
+
+ # Chomp the tail.
+ if chomping is not False:
+ chunks.append(line_break)
+ if chomping is True:
+ chunks.extend(breaks)
+
+ # We are done.
+ return ScalarToken("".join(chunks), False, start_mark, end_mark, style)
+
+ def scan_block_scalar_indicators(self, start_mark):
+ # See the specification for details.
+ chomping = None
+ increment = None
+ ch = self.peek()
+ if ch in "+-":
+ if ch == "+":
+ chomping = True
+ else:
+ chomping = False
+ self.forward()
+ ch = self.peek()
+ if ch in "0123456789":
+ increment = int(ch)
+ if increment == 0:
+ raise ScannerError(
+ "while scanning a block scalar",
+ start_mark,
+ "expected indentation indicator in the range 1-9, but found 0",
+ self.get_mark(),
+ )
+ self.forward()
+ elif ch in "0123456789":
+ increment = int(ch)
+ if increment == 0:
+ raise ScannerError(
+ "while scanning a block scalar",
+ start_mark,
+ "expected indentation indicator in the range 1-9, but found 0",
+ self.get_mark(),
+ )
+ self.forward()
+ ch = self.peek()
+ if ch in "+-":
+ if ch == "+":
+ chomping = True
+ else:
+ chomping = False
+ self.forward()
+ ch = self.peek()
+ if ch not in "\0 \r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a block scalar",
+ start_mark,
+ "expected chomping or indentation indicators, but found %r" % ch,
+ self.get_mark(),
+ )
+ return chomping, increment
+
+ def scan_block_scalar_ignored_line(self, start_mark):
+ # See the specification for details.
+ while self.peek() == " ":
+ self.forward()
+ if self.peek() == "#":
+ while self.peek() not in "\0\r\n\x85\u2028\u2029":
+ self.forward()
+ ch = self.peek()
+ if ch not in "\0\r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a block scalar",
+ start_mark,
+ "expected a comment or a line break, but found %r" % ch,
+ self.get_mark(),
+ )
+ self.scan_line_break()
+
+ def scan_block_scalar_indentation(self):
+ # See the specification for details.
+ chunks = []
+ max_indent = 0
+ end_mark = self.get_mark()
+ while self.peek() in " \r\n\x85\u2028\u2029":
+ if self.peek() != " ":
+ chunks.append(self.scan_line_break())
+ end_mark = self.get_mark()
+ else:
+ self.forward()
+ if self.column > max_indent:
+ max_indent = self.column
+ return chunks, max_indent, end_mark
+
+ def scan_block_scalar_breaks(self, indent):
+ # See the specification for details.
+ chunks = []
+ end_mark = self.get_mark()
+ while self.column < indent and self.peek() == " ":
+ self.forward()
+ while self.peek() in "\r\n\x85\u2028\u2029":
+ chunks.append(self.scan_line_break())
+ end_mark = self.get_mark()
+ while self.column < indent and self.peek() == " ":
+ self.forward()
+ return chunks, end_mark
+
+ def scan_flow_scalar(self, style):
+ # See the specification for details.
+ # Note that we loose indentation rules for quoted scalars. Quoted
+ # scalars don't need to adhere indentation because " and ' clearly
+ # mark the beginning and the end of them. Therefore we are less
+ # restrictive then the specification requires. We only need to check
+ # that document separators are not included in scalars.
+ if style == '"':
+ double = True
+ else:
+ double = False
+ chunks = []
+ start_mark = self.get_mark()
+ quote = self.peek()
+ self.forward()
+ chunks.extend(self.scan_flow_scalar_non_spaces(double, start_mark))
+ while self.peek() != quote:
+ chunks.extend(self.scan_flow_scalar_spaces(double, start_mark))
+ chunks.extend(self.scan_flow_scalar_non_spaces(double, start_mark))
+ self.forward()
+ end_mark = self.get_mark()
+ return ScalarToken("".join(chunks), False, start_mark, end_mark, style)
+
+ ESCAPE_REPLACEMENTS = {
+ "0": "\0",
+ "a": "\x07",
+ "b": "\x08",
+ "t": "\x09",
+ "\t": "\x09",
+ "n": "\x0A",
+ "v": "\x0B",
+ "f": "\x0C",
+ "r": "\x0D",
+ "e": "\x1B",
+ " ": "\x20",
+ '"': '"',
+ "\\": "\\",
+ "/": "/",
+ "N": "\x85",
+ "_": "\xA0",
+ "L": "\u2028",
+ "P": "\u2029",
+ }
+
+ ESCAPE_CODES = {
+ "x": 2,
+ "u": 4,
+ "U": 8,
+ }
+
+ def scan_flow_scalar_non_spaces(self, double, start_mark):
+ # See the specification for details.
+ chunks = []
+ while True:
+ length = 0
+ while self.peek(length) not in "'\"\\\0 \t\r\n\x85\u2028\u2029":
+ length += 1
+ if length:
+ chunks.append(self.prefix(length))
+ self.forward(length)
+ ch = self.peek()
+ if not double and ch == "'" and self.peek(1) == "'":
+ chunks.append("'")
+ self.forward(2)
+ elif (double and ch == "'") or (not double and ch in '"\\'):
+ chunks.append(ch)
+ self.forward()
+ elif double and ch == "\\":
+ self.forward()
+ ch = self.peek()
+ if ch in self.ESCAPE_REPLACEMENTS:
+ chunks.append(self.ESCAPE_REPLACEMENTS[ch])
+ self.forward()
+ elif ch in self.ESCAPE_CODES:
+ length = self.ESCAPE_CODES[ch]
+ self.forward()
+ for k in range(length):
+ if self.peek(k) not in "0123456789ABCDEFabcdef":
+ raise ScannerError(
+ "while scanning a double-quoted scalar",
+ start_mark,
+ "expected escape sequence of %d hexadecimal numbers, but found %r"
+ % (length, self.peek(k)),
+ self.get_mark(),
+ )
+ code = int(self.prefix(length), 16)
+ chunks.append(chr(code))
+ self.forward(length)
+ elif ch in "\r\n\x85\u2028\u2029":
+ self.scan_line_break()
+ chunks.extend(self.scan_flow_scalar_breaks(double, start_mark))
+ else:
+ raise ScannerError(
+ "while scanning a double-quoted scalar",
+ start_mark,
+ "found unknown escape character %r" % ch,
+ self.get_mark(),
+ )
+ else:
+ return chunks
+
+ def scan_flow_scalar_spaces(self, double, start_mark):
+ # See the specification for details.
+ chunks = []
+ length = 0
+ while self.peek(length) in " \t":
+ length += 1
+ whitespaces = self.prefix(length)
+ self.forward(length)
+ ch = self.peek()
+ if ch == "\0":
+ raise ScannerError(
+ "while scanning a quoted scalar",
+ start_mark,
+ "found unexpected end of stream",
+ self.get_mark(),
+ )
+ elif ch in "\r\n\x85\u2028\u2029":
+ line_break = self.scan_line_break()
+ breaks = self.scan_flow_scalar_breaks(double, start_mark)
+ if line_break != "\n":
+ chunks.append(line_break)
+ elif not breaks:
+ chunks.append(" ")
+ chunks.extend(breaks)
+ else:
+ chunks.append(whitespaces)
+ return chunks
+
+ def scan_flow_scalar_breaks(self, double, start_mark):
+ # See the specification for details.
+ chunks = []
+ while True:
+ # Instead of checking indentation, we check for document
+ # separators.
+ prefix = self.prefix(3)
+ if (prefix == "---" or prefix == "...") and self.peek(
+ 3
+ ) in "\0 \t\r\n\x85\u2028\u2029":
+ raise ScannerError(
+ "while scanning a quoted scalar",
+ start_mark,
+ "found unexpected document separator",
+ self.get_mark(),
+ )
+ while self.peek() in " \t":
+ self.forward()
+ if self.peek() in "\r\n\x85\u2028\u2029":
+ chunks.append(self.scan_line_break())
+ else:
+ return chunks
+
+ def scan_plain(self):
+ # See the specification for details.
+ # We add an additional restriction for the flow context:
+ # plain scalars in the flow context cannot contain ',' or '?'.
+ # We also keep track of the `allow_simple_key` flag here.
+ # Indentation rules are loosed for the flow context.
+ chunks = []
+ start_mark = self.get_mark()
+ end_mark = start_mark
+ indent = self.indent + 1
+ # We allow zero indentation for scalars, but then we need to check for
+ # document separators at the beginning of the line.
+ # if indent == 0:
+ # indent = 1
+ spaces = []
+ while True:
+ length = 0
+ if self.peek() == "#":
+ break
+ while True:
+ ch = self.peek(length)
+ if (
+ ch in "\0 \t\r\n\x85\u2028\u2029"
+ or (
+ ch == ":"
+ and self.peek(length + 1)
+ in "\0 \t\r\n\x85\u2028\u2029"
+ + (",[]{}" if self.flow_level else "")
+ )
+ or (self.flow_level and ch in ",?[]{}")
+ ):
+ break
+ length += 1
+ if length == 0:
+ break
+ self.allow_simple_key = False
+ chunks.extend(spaces)
+ chunks.append(self.prefix(length))
+ self.forward(length)
+ end_mark = self.get_mark()
+ spaces = self.scan_plain_spaces(indent, start_mark)
+ if (
+ not spaces
+ or self.peek() == "#"
+ or (not self.flow_level and self.column < indent)
+ ):
+ break
+ return ScalarToken("".join(chunks), True, start_mark, end_mark)
+
+ def scan_plain_spaces(self, indent, start_mark):
+ # See the specification for details.
+ # The specification is really confusing about tabs in plain scalars.
+ # We just forbid them completely. Do not use tabs in YAML!
+ chunks = []
+ length = 0
+ while self.peek(length) in " ":
+ length += 1
+ whitespaces = self.prefix(length)
+ self.forward(length)
+ ch = self.peek()
+ if ch in "\r\n\x85\u2028\u2029":
+ line_break = self.scan_line_break()
+ self.allow_simple_key = True
+ prefix = self.prefix(3)
+ if (prefix == "---" or prefix == "...") and self.peek(
+ 3
+ ) in "\0 \t\r\n\x85\u2028\u2029":
+ return
+ breaks = []
+ while self.peek() in " \r\n\x85\u2028\u2029":
+ if self.peek() == " ":
+ self.forward()
+ else:
+ breaks.append(self.scan_line_break())
+ prefix = self.prefix(3)
+ if (prefix == "---" or prefix == "...") and self.peek(
+ 3
+ ) in "\0 \t\r\n\x85\u2028\u2029":
+ return
+ if line_break != "\n":
+ chunks.append(line_break)
+ elif not breaks:
+ chunks.append(" ")
+ chunks.extend(breaks)
+ elif whitespaces:
+ chunks.append(whitespaces)
+ return chunks
+
+ def scan_tag_handle(self, name, start_mark):
+ # See the specification for details.
+ # For some strange reasons, the specification does not allow '_' in
+ # tag handles. I have allowed it anyway.
+ ch = self.peek()
+ if ch != "!":
+ raise ScannerError(
+ "while scanning a %s" % name,
+ start_mark,
+ "expected '!', but found %r" % ch,
+ self.get_mark(),
+ )
+ length = 1
+ ch = self.peek(length)
+ if ch != " ":
+ while (
+ "0" <= ch <= "9" or "A" <= ch <= "Z" or "a" <= ch <= "z" or ch in "-_"
+ ):
+ length += 1
+ ch = self.peek(length)
+ if ch != "!":
+ self.forward(length)
+ raise ScannerError(
+ "while scanning a %s" % name,
+ start_mark,
+ "expected '!', but found %r" % ch,
+ self.get_mark(),
+ )
+ length += 1
+ value = self.prefix(length)
+ self.forward(length)
+ return value
+
+ def scan_tag_uri(self, name, start_mark):
+ # See the specification for details.
+ # Note: we do not check if URI is well-formed.
+ chunks = []
+ length = 0
+ ch = self.peek(length)
+ while (
+ "0" <= ch <= "9"
+ or "A" <= ch <= "Z"
+ or "a" <= ch <= "z"
+ or ch in "-;/?:@&=+$,_.!~*'()[]%"
+ ):
+ if ch == "%":
+ chunks.append(self.prefix(length))
+ self.forward(length)
+ length = 0
+ chunks.append(self.scan_uri_escapes(name, start_mark))
+ else:
+ length += 1
+ ch = self.peek(length)
+ if length:
+ chunks.append(self.prefix(length))
+ self.forward(length)
+ length = 0
+ if not chunks:
+ raise ScannerError(
+ "while parsing a %s" % name,
+ start_mark,
+ "expected URI, but found %r" % ch,
+ self.get_mark(),
+ )
+ return "".join(chunks)
+
+ def scan_uri_escapes(self, name, start_mark):
+ # See the specification for details.
+ codes = []
+ mark = self.get_mark()
+ while self.peek() == "%":
+ self.forward()
+ for k in range(2):
+ if self.peek(k) not in "0123456789ABCDEFabcdef":
+ raise ScannerError(
+ "while scanning a %s" % name,
+ start_mark,
+ "expected URI escape sequence of 2 hexadecimal numbers, but found %r"
+ % self.peek(k),
+ self.get_mark(),
+ )
+ codes.append(int(self.prefix(2), 16))
+ self.forward(2)
+ try:
+ value = bytes(codes).decode("utf-8")
+ except UnicodeDecodeError as exc:
+ raise ScannerError("while scanning a %s" % name, start_mark, str(exc), mark)
+ return value
+
+ def scan_line_break(self):
+ # Transforms:
+ # '\r\n' : '\n'
+ # '\r' : '\n'
+ # '\n' : '\n'
+ # '\x85' : '\n'
+ # '\u2028' : '\u2028'
+ # '\u2029 : '\u2029'
+ # default : ''
+ ch = self.peek()
+ if ch in "\r\n\x85":
+ if self.prefix(2) == "\r\n":
+ self.forward(2)
+ else:
+ self.forward()
+ return "\n"
+ elif ch in "\u2028\u2029":
+ self.forward()
+ return ch
+ return ""
diff --git a/openlane/dependencies/includedyaml/serializer.py b/openlane/dependencies/includedyaml/serializer.py
new file mode 100644
index 0000000..92f9221
--- /dev/null
+++ b/openlane/dependencies/includedyaml/serializer.py
@@ -0,0 +1,127 @@
+__all__ = ["Serializer", "SerializerError"]
+
+from .error import YAMLError
+from .events import *
+from .nodes import *
+
+
+class SerializerError(YAMLError):
+ pass
+
+
+class Serializer:
+
+ ANCHOR_TEMPLATE = "id%03d"
+
+ def __init__(
+ self,
+ encoding=None,
+ explicit_start=None,
+ explicit_end=None,
+ version=None,
+ tags=None,
+ ):
+ self.use_encoding = encoding
+ self.use_explicit_start = explicit_start
+ self.use_explicit_end = explicit_end
+ self.use_version = version
+ self.use_tags = tags
+ self.serialized_nodes = {}
+ self.anchors = {}
+ self.last_anchor_id = 0
+ self.closed = None
+
+ def open(self):
+ if self.closed is None:
+ self.emit(StreamStartEvent(encoding=self.use_encoding))
+ self.closed = False
+ elif self.closed:
+ raise SerializerError("serializer is closed")
+ else:
+ raise SerializerError("serializer is already opened")
+
+ def close(self):
+ if self.closed is None:
+ raise SerializerError("serializer is not opened")
+ elif not self.closed:
+ self.emit(StreamEndEvent())
+ self.closed = True
+
+ # def __del__(self):
+ # self.close()
+
+ def serialize(self, node):
+ if self.closed is None:
+ raise SerializerError("serializer is not opened")
+ elif self.closed:
+ raise SerializerError("serializer is closed")
+ self.emit(
+ DocumentStartEvent(
+ explicit=self.use_explicit_start,
+ version=self.use_version,
+ tags=self.use_tags,
+ )
+ )
+ self.anchor_node(node)
+ self.serialize_node(node, None, None)
+ self.emit(DocumentEndEvent(explicit=self.use_explicit_end))
+ self.serialized_nodes = {}
+ self.anchors = {}
+ self.last_anchor_id = 0
+
+ def anchor_node(self, node):
+ if node in self.anchors:
+ if self.anchors[node] is None:
+ self.anchors[node] = self.generate_anchor(node)
+ else:
+ self.anchors[node] = None
+ if isinstance(node, SequenceNode):
+ for item in node.value:
+ self.anchor_node(item)
+ elif isinstance(node, MappingNode):
+ for key, value in node.value:
+ self.anchor_node(key)
+ self.anchor_node(value)
+
+ def generate_anchor(self, node):
+ self.last_anchor_id += 1
+ return self.ANCHOR_TEMPLATE % self.last_anchor_id
+
+ def serialize_node(self, node, parent, index):
+ alias = self.anchors[node]
+ if node in self.serialized_nodes:
+ self.emit(AliasEvent(alias))
+ else:
+ self.serialized_nodes[node] = True
+ self.descend_resolver(parent, index)
+ if isinstance(node, ScalarNode):
+ detected_tag = self.resolve(ScalarNode, node.value, (True, False))
+ default_tag = self.resolve(ScalarNode, node.value, (False, True))
+ implicit = (node.tag == detected_tag), (node.tag == default_tag)
+ self.emit(
+ ScalarEvent(alias, node.tag, implicit, node.value, style=node.style)
+ )
+ elif isinstance(node, SequenceNode):
+ implicit = node.tag == self.resolve(SequenceNode, node.value, True)
+ self.emit(
+ SequenceStartEvent(
+ alias, node.tag, implicit, flow_style=node.flow_style
+ )
+ )
+ index = 0
+ for item in node.value:
+ self.serialize_node(item, node, index)
+ index += 1
+ self.emit(SequenceEndEvent())
+ elif isinstance(node, MappingNode):
+ implicit = node.tag == self.resolve(MappingNode, node.value, True)
+ self.emit(
+ MappingStartEvent(
+ alias, node.tag, implicit, flow_style=node.flow_style
+ )
+ )
+ for key, value in node.value:
+ self.serialize_node(key, node, None)
+ self.serialize_node(value, node, key)
+ self.emit(MappingEndEvent())
+ self.ascend_resolver()
diff --git a/openlane/dependencies/includedyaml/tokens.py b/openlane/dependencies/includedyaml/tokens.py
new file mode 100644
index 0000000..235ab49
--- /dev/null
+++ b/openlane/dependencies/includedyaml/tokens.py
@@ -0,0 +1,129 @@
+class Token(object):
+ def __init__(self, start_mark, end_mark):
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+ def __repr__(self):
+ attributes = [key for key in self.__dict__ if not key.endswith("_mark")]
+ attributes.sort()
+ arguments = ", ".join(
+ ["%s=%r" % (key, getattr(self, key)) for key in attributes]
+ )
+ return "%s(%s)" % (self.__class__.__name__, arguments)
+
+
+# class BOMToken(Token):
+# id = '<byte order mark>'
+
+
+class DirectiveToken(Token):
+ id = "<directive>"
+
+ def __init__(self, name, value, start_mark, end_mark):
+ self.name = name
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+
+class DocumentStartToken(Token):
+ id = "<document start>"
+
+
+class DocumentEndToken(Token):
+ id = "<document end>"
+
+
+class StreamStartToken(Token):
+ id = "<stream start>"
+
+ def __init__(self, start_mark=None, end_mark=None, encoding=None):
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.encoding = encoding
+
+
+class StreamEndToken(Token):
+ id = "<stream end>"
+
+
+class BlockSequenceStartToken(Token):
+ id = "<block sequence start>"
+
+
+class BlockMappingStartToken(Token):
+ id = "<block mapping start>"
+
+
+class BlockEndToken(Token):
+ id = "<block end>"
+
+
+class FlowSequenceStartToken(Token):
+ id = "["
+
+
+class FlowMappingStartToken(Token):
+ id = "{"
+
+
+class FlowSequenceEndToken(Token):
+ id = "]"
+
+
+class FlowMappingEndToken(Token):
+ id = "}"
+
+
+class KeyToken(Token):
+ id = "?"
+
+
+class ValueToken(Token):
+ id = ":"
+
+
+class BlockEntryToken(Token):
+ id = "-"
+
+
+class FlowEntryToken(Token):
+ id = ","
+
+
+class AliasToken(Token):
+ id = "<alias>"
+
+ def __init__(self, value, start_mark, end_mark):
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+
+class AnchorToken(Token):
+ id = "<anchor>"
+
+ def __init__(self, value, start_mark, end_mark):
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+
+class TagToken(Token):
+ id = "<tag>"
+
+ def __init__(self, value, start_mark, end_mark):
+ self.value = value
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+
+
+class ScalarToken(Token):
+ id = "<scalar>"
+
+ def __init__(self, value, plain, start_mark, end_mark, style=None):
+ self.value = value
+ self.plain = plain
+ self.start_mark = start_mark
+ self.end_mark = end_mark
+ self.style = style
diff --git a/openlane/dependencies/installer.py b/openlane/dependencies/installer.py
new file mode 100644
index 0000000..c8f64ee
--- /dev/null
+++ b/openlane/dependencies/installer.py
@@ -0,0 +1,509 @@
+#!/usr/bin/env python3
+
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import os
+import sys
+import uuid
+import tempfile
+import pathlib
+import textwrap
+import subprocess
+from os.path import join, abspath, dirname, exists, realpath
+from typing import Tuple, Union, List
+
+openlane_dir = dirname(dirname(abspath(__file__)))
+is_root = os.geteuid() == 0
+
+
+class chdir(object):
+ def __init__(self, path):
+ self.path = path
+ self.previous = None
+
+ def __enter__(self):
+ self.previous = os.getcwd()
+ os.chdir(self.path)
+
+ def __exit__(self, exc_type, exc_value, traceback):
+ os.chdir(self.previous)
+ if exc_type is not None:
+ raise exc_value
+
+
+def sh(*args: Tuple[str], root: Union[bool, str] = False, **kwargs):
+ """
+ args: shell arguments to run
+ root:
+ if False, the command will be executed as-is
+ if True, if the user is not root, "sudo" will be added to the command
+ if "retry", the command will be executed as-is first, and if it fails,
+ it is retried as root.
+ """
+ args = list(args)
+ if root and not is_root:
+ args = ["sudo"] + args
+ try:
+ subprocess.run(
+ args,
+ check=True,
+ stderr=subprocess.PIPE if root == "retry" else None,
+ **kwargs,
+ )
+ except subprocess.CalledProcessError as e:
+ if root == "retry":
+ args = ["sudo"] + args
+ subprocess.run(args, check=True, **kwargs)
+ else:
+ raise e
+
+
+def download(url: str, ext: str) -> str:
+ path = f"/tmp/{uuid.uuid4()}.{ext}"
+ print(f"{url} -> {path}")
+ target = open(path, "wb")
+ sh("curl", "-L", url, stdout=target)
+ target.close()
+ return path
+
+
+# Installer Class
+class Installer(object):
+ def __init__(self):
+ self.envs: List[Tuple[str, str]] = []
+
+ def input_options(self, env: str, msg: str, options: List[str]) -> str:
+ value = None
+ env_value = os.getenv(env)
+ if env_value is not None and env_value.lower() in options:
+ value = env_value
+ else:
+ options_pretty = [] + options
+ options_pretty[0] = f"{options[0].upper()}"
+ value = input(f"{msg} [{'/'.join(options_pretty)}] > ")
+ if value == "":
+ value = options[0]
+ while value.lower() not in options:
+ value = input(f"Invalid input {value.lower()}, please retry: ")
+
+ value = value.lower()
+ self.envs.append((env, value))
+ return value
+
+ def input_default(self, env: str, msg: str, default: str) -> str:
+ value = None
+ env_value = os.getenv(env)
+ if env_value is not None:
+ value = env_value
+ else:
+ value = input(f"{msg} [{default}] > ")
+ if value == "":
+ value = default
+
+ self.envs.append((env, value))
+ return value
+
+ def run(self):
+ from dependencies.tool import Tool
+ from dependencies.get_tag import NoGitException, get_tag
+ from dependencies.env_info import OSInfo
+
+ try:
+ import venv
+ except ImportError:
+ print(
+ "Python venv does not appear to be installed, and is required for local installations.",
+ file=sys.stderr,
+ )
+
+ try:
+ ol_version = get_tag()
+ except NoGitException:
+ print(
+ "Installing OpenLane locally requires a Git repository.",
+ file=sys.stderr,
+ )
+ exit(-1)
+
+ tools = Tool.from_metadata_yaml(open("./dependencies/tool_metadata.yml").read())
+
+ print(
+ textwrap.dedent(
+ """\
+ OpenLane Local Installer
+
+ Copyright 2021-2022 Efabless Corporation. Available under the Apache License,
+ Version 2.0.
+
+ Ctrl+C at any time to quit.
+
+ Make sure you read the documentation in ./docs/source/local_installs.md.
+ """
+ )
+ )
+
+ install_dir = realpath("./install")
+
+ sh("mkdir", "-p", install_dir, root="retry")
+
+ home_perms = os.stat(os.getenv("HOME"))
+ sh(
+ "chown",
+ "-R",
+ "%i:%i" % (home_perms.st_uid, home_perms.st_gid),
+ install_dir,
+ root="retry",
+ )
+
+ os_list = ["other", "ubuntu-20.04", "centos-7", "arch", "macos"]
+
+ # Try to determine user's OS
+ def set_default_os(x):
+ os_list.insert(0, os_list.pop(os_list.index(x)))
+
+ os_info = OSInfo.get()
+
+ if os_info.distro == "macOS":
+ set_default_os("macos")
+
+ if os_info.distro == "centos" and os_info.distro_version == "7":
+ set_default_os("centos-7")
+
+ if os_info.distro == "ubuntu" and os_info.distro_version == "20.04":
+ set_default_os("ubuntu-20.04")
+
+ if os_info.distro in ["manjaro", "arch"]:
+ set_default_os("arch")
+
+ os_pick = self.input_options(
+ "OS", "Which UNIX/Unix-like OS are you using?", os_list
+ )
+
+ gcc_bin = os.getenv("CC") or "gcc"
+ gxx_bin = os.getenv("CXX") or "g++"
+ try:
+ if os_pick not in [
+ "centos-7",
+ "macos",
+ ]: # The reason we ignore centos 7 and macos is that we're going to just use devtoolset-8/brew gcc anyway.
+ all_output = ""
+ try:
+ gcc_ver_output = subprocess.run(
+ [gcc_bin, "--version"], stdout=subprocess.PIPE
+ )
+ all_output += gcc_ver_output.stdout.decode("utf8")
+ gx_ver_output = subprocess.run(
+ [gxx_bin, "--version"], stdout=subprocess.PIPE
+ )
+ all_output += gx_ver_output.stdout.decode("utf8")
+ except Exception:
+ pass
+ if "clang" in all_output:
+ print(
+ textwrap.dedent(
+ f"""\
+ We've detected that you're using Clang as your default C or C++ compiler.
+ Unfortunately, Clang is not compatible with some of the tools being
+ installed.
+
+ You may continue this installation at your own risk, but we recommend
+ installing GCC.
+
+ You can specify a compiler to use explicitly by invoking this script as
+ follows, for example:
+
+ CC=/usr/local/bin/gcc-8 CXX=/usr/local/bin/g++-8 python3 {__file__}
+ """
+ )
+ )
+ input(
+ "Press return if you understand the risk and wish to continue anyways >"
+ )
+ except FileNotFoundError as e:
+ print(e, "(set as either CC or CXX)")
+ exit(os.EX_CONFIG)
+
+ install_packages = "no"
+ if os_pick != "other":
+ install_packages = self.input_options(
+ "INSTALL_PACKAGES",
+ "Do you want to install dependencies using your package manager?",
+ ["no", "yes"],
+ )
+ if install_packages != "no":
+
+ def cat_all(dir):
+ result = ""
+ for file in os.listdir(dir):
+ result += open(join(dir, file)).read()
+ result += "\n"
+ return result
+
+ if os_pick == "macos":
+ brew_packages = (
+ cat_all(join(openlane_dir, "dependencies", "macos"))
+ .strip()
+ .split("\n")
+ )
+
+ sh("brew", "install", *brew_packages)
+ if os_pick == "centos-7":
+ yum_packages = (
+ cat_all(join(openlane_dir, "dependencies", "centos-7"))
+ .strip()
+ .split("\n")
+ )
+
+ sh("yum", "install", "-y", *yum_packages, root="retry")
+ if os_pick == "arch":
+ raw = (
+ cat_all(join(openlane_dir, "dependencies", "arch"))
+ .strip()
+ .split("\n")
+ )
+
+ arch_packages = []
+ aur_packages = []
+
+ for entry in raw:
+ if entry.strip() == "":
+ continue
+
+ if entry.startswith("https://"):
+ aur_packages.append(entry)
+ else:
+ arch_packages.append(entry)
+
+ sh(
+ "pacman",
+ "-S",
+ "--noconfirm",
+ "--needed",
+ *arch_packages,
+ root="retry",
+ )
+
+ temp_dir = tempfile.gettempdir()
+ oaur_path = os.path.join(temp_dir, "openlane_aur")
+ pathlib.Path(oaur_path).mkdir(parents=True, exist_ok=True)
+ with chdir(oaur_path):
+ for package in aur_packages:
+ sh("rm", "-rf", "current")
+ sh("git", "clone", package, "current")
+ with chdir("current"):
+ sh("makepkg", "-si", "--noconfirm")
+ if os_pick == "ubuntu-20.04":
+ raw = (
+ cat_all(join(openlane_dir, "dependencies", "ubuntu-20.04"))
+ .strip()
+ .split("\n")
+ )
+
+ apt_packages = []
+ apt_debs = []
+
+ for entry in raw:
+ if entry.strip() == "":
+ continue
+
+ if entry.startswith("https://"):
+ apt_debs.append(entry)
+ else:
+ apt_packages.append(entry)
+ sh("apt-get", "update", root="retry")
+ sh("apt-get", "install", "-y", "curl", root="retry")
+ for deb in apt_debs:
+ path = download(deb, "deb")
+ sh("apt-get", "install", "-y", "-f", path, root="retry")
+ sh("apt-get", "install", "-y", *apt_packages, root="retry")
+
+ print("To re-run with the same options: ")
+ print(f"{' '.join(['%s=%s' % env for env in self.envs])} python3 {__file__}")
+
+ run_env = os.environ.copy()
+ run_env["PREFIX"] = install_dir
+ run_env["PATH"] = f"{install_dir}/bin:{os.getenv('PATH')}"
+
+ path_elements = ["$OL_INSTALL_DIR/venv/bin", "$OL_INSTALL_DIR/bin"]
+
+ if os_pick == "centos-7":
+ run_env["CC"] = "/opt/rh/devtoolset-8/root/usr/bin/gcc"
+ run_env["CXX"] = "/opt/rh/devtoolset-8/root/usr/bin/g++"
+ run_env["PATH"] = f"/opt/rh/devtoolset-8/root/usr/bin:{os.getenv('PATH')}"
+ run_env[
+ "LD_LIBRARY_PATH"
+ ] = f"/opt/rh/devtoolset-8/root/usr/lib64:/opt/rh/devtoolset-8/root/usr/lib:/opt/rh/devtoolset-8/root/usr/lib64/dyninst:/opt/rh/devtoolset-8/root/usr/lib/dyninst:/opt/rh/devtoolset-8/root/usr/lib64:/opt/rh/devtoolset-8/root/usr/lib:{os.getenv('LD_LIBRARY_PATH')}"
+ run_env[
+ "CMAKE_INCLUDE_PATH"
+ ] = f"/usr/include/boost169:{os.getenv('CMAKE_INCLUDE_PATH')}"
+ run_env[
+ "CMAKE_LIBRARY_PATH"
+ ] = f"/lib64/boost169:{os.getenv('CMAKE_LIBRARY_PATH')}"
+ elif os_pick == "macos":
+
+ def get_prefix(tool):
+ return (
+ subprocess.check_output(["brew", "--prefix", tool])
+ .decode("utf8")
+ .strip()
+ )
+
+ klayout_app_path = self.input_default(
+ "KLAYOUT_MAC_APP",
+ "Please input the path to klayout.app (0.27.3 or later): ",
+ "/Applications/klayout.app",
+ )
+ klayout_path_element = join(klayout_app_path, "Contents", "MacOS")
+
+ run_env["CC"] = f"{get_prefix('gcc')}/bin/gcc-11"
+ run_env["CXX"] = f"{get_prefix('gcc')}/bin/g++-11"
+ run_env[
+ "PATH"
+ ] = f"{get_prefix('swig@3')}/bin:{get_prefix('bison')}/bin:{get_prefix('flex')}/bin:{get_prefix('gnu-which')}/bin:{os.getenv('PATH')}"
+ run_env[
+ "MAGIC_CONFIG_OPTS"
+ ] = f"--with-tcl={get_prefix('tcl-tk')} --with-tk={get_prefix('tcl-tk')}"
+ run_env["READLINE_CXXFLAGS"] = f"CXXFLAGS=-L{get_prefix('readline')}/lib"
+
+ path_elements.append(f"{klayout_path_element}")
+ path_elements.append(f"{get_prefix('gnu-sed')}/libexec/gnubin")
+ path_elements.append(f"{get_prefix('bash')}/bin")
+ else:
+ run_env["CC"] = gcc_bin
+ self.envs.append(("CC", gcc_bin))
+ run_env["CXX"] = gxx_bin
+ self.envs.append(("CXX", gxx_bin))
+
+ def copy(f):
+ sh("rm", "-rf", f)
+ sh("cp", "-r", join(openlane_dir, f), f)
+
+ def install():
+ print("Copying files...")
+ for folder in ["bin", "lib", "share", "build", "dependencies"]:
+ sh("mkdir", "-p", folder)
+
+ print("Building Python virtual environment...")
+ venv_builder = venv.EnvBuilder(clear=True, with_pip=True)
+ venv_builder.create("./venv")
+
+ subprocess.run(
+ [
+ "bash",
+ "-c",
+ """
+ source ./venv/bin/activate
+ python3 -m pip install --upgrade -r ../dependencies/python/precompile_time.txt
+ python3 -m pip install --upgrade -r ../dependencies/python/compile_time.txt
+ python3 -m pip install --upgrade -r ../dependencies/python/run_time.txt
+ """,
+ ]
+ )
+
+ print("Installing dependencies...")
+ with chdir("build"):
+ for folder in ["repos", "versions"]:
+ sh("mkdir", "-p", folder)
+
+ skip_tools = re.compile(os.getenv("SKIP_TOOLS") or "Unmatchable")
+ tool_queue = list(tools.values()).copy()
+
+ print(tool_queue)
+
+ def pop():
+ return tool_queue.pop(0) if len(tool_queue) else None
+
+ installed = set()
+ tool = pop()
+ while tool is not None:
+ if not (tool.in_install and (skip_tools.match(tool.name) is None)):
+ tool = pop()
+ continue
+
+ if len(tool.dependencies):
+ dependencies = set(tool.dependencies)
+ if not dependencies.issubset(installed):
+ tool_queue.append(tool)
+ tool = pop()
+ continue
+
+ installed_version = ""
+ version_path = f"versions/{tool.name}"
+ try:
+ installed_version = open(version_path).read()
+ except Exception:
+ pass
+ if (
+ installed_version == tool.version_string
+ and os.getenv("FORCE_REINSTALL") != "1"
+ ):
+ print(f"{tool.version_string} already installed, skipping...")
+ else:
+ print(f"Installing {tool.name}...")
+
+ with chdir("repos"):
+ if not exists(tool.name):
+ sh("git", "clone", tool.repo, tool.name)
+
+ with chdir(tool.name):
+ sh("git", "fetch")
+ sh("git", "submodule", "update", "--init")
+ sh("git", "checkout", tool.commit)
+ subprocess.run(
+ [
+ "bash",
+ "-c",
+ f"""\
+ set -e
+ source {install_dir}/venv/bin/activate
+ {tool.build_script}
+ """,
+ ],
+ env=run_env,
+ check=True,
+ )
+
+ with open(version_path, "w") as f:
+ f.write(tool.version_string)
+
+ installed.add(tool.name)
+ tool = pop()
+
+ path_elements.reverse()
+ with open("env.tcl", "w") as f:
+ f.write(
+ textwrap.dedent(
+ f"""\
+ set OL_INSTALL_DIR [file dirname [file normalize [info script]]]
+
+ set ::env(OPENLANE_LOCAL_INSTALL) 1
+ set ::env(OL_INSTALL_DIR) "$OL_INSTALL_DIR"
+ set ::env(PATH) "{":".join(path_elements)}:$::env(PATH)"
+ set ::env(VIRTUAL_ENV) "$OL_INSTALL_DIR/venv"
+ """
+ )
+ )
+
+ with open("installed_version", "w") as f:
+ f.write(ol_version)
+
+ with chdir(install_dir):
+ install()
+
+ print("Done.")
+ print(
+ "To invoke Openlane from now on, invoke ./flow.tcl from the OpenLane root without the Makefile."
+ )
diff --git a/openlane/dependencies/macos/run_time.txt b/openlane/dependencies/macos/run_time.txt
new file mode 100644
index 0000000..f837740
--- /dev/null
+++ b/openlane/dependencies/macos/run_time.txt
@@ -0,0 +1,40 @@
+autoconf
+automake
+bash
+bison
+boost
+bzip2
+cairo
+curl
+eigen
+flex
+gawk
+gcc@11
+gdb
+gettext
+graphviz
+libSM
+libX11
+libXext
+libXft
+libffi
+libjpeg
+libomp
+libxml2
+libxslt
+make
+mesa-glu
+ncurses
+ninja
+patchutils
+pcre
+python
+readline
+spdlog
+swig@3
+tcl-tk
+vim
+wget
+gnu-which
+xdot
+zlib
diff --git a/openlane/dependencies/pdk.mk b/openlane/dependencies/pdk.mk
new file mode 100644
index 0000000..bd61bfd
--- /dev/null
+++ b/openlane/dependencies/pdk.mk
@@ -0,0 +1,98 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# This file is intended to be included by the top-level Makefile.
+# Please don't use it directly. Consider efabless/volare instead.
+
+STD_CELL_LIBRARY ?= sky130_fd_sc_hd
+SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
+IO_LIBRARY ?= sky130_fd_io
+
+LIBRARY_LIST ?= $(STD_CELL_LIBRARY) $(IO_LIBRARY) $(SPECIAL_VOLTAGE_LIBRARY) sky130_fd_pr
+ifeq ($(FULL_PDK),1)
+LIBRARY_LIST = sky130_fd_sc_hd sky130_fd_sc_hs sky130_fd_sc_hdll sky130_fd_sc_ms sky130_fd_sc_ls sky130_fd_sc_hvl sky130_fd_io sky130_fd_pr
+endif
+ifeq ($(NATIVE_PDK),1)
+ENV_COMMAND = env
+endif
+
+OPEN_PDK_ARGS ?= --enable-sram-sky130
+
+.PHONY: build-pdk-conda
+build-pdk-conda: skywater-pdk skywater-library open_pdks build-open_pdks gen-sources
+
+$(PDK_ROOT):
+ mkdir -p $(PDK_ROOT)
+
+$(PDK_ROOT)/skywater-pdk/LICENSE: | $(PDK_ROOT)
+ git clone $(shell $(PYTHON_BIN) ./dependencies/tool.py sky130 -f repo) $(PDK_ROOT)/skywater-pdk
+
+.PHONY: skywater-pdk
+skywater-pdk: $(PDK_ROOT)/skywater-pdk/LICENSE
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git checkout main && \
+ git submodule init && git pull --no-recurse-submodules && \
+ git checkout -qf $(SKYWATER_COMMIT)
+
+.PHONY: skywater-library
+skywater-library: $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ for library in $(LIBRARY_LIST); do \
+ git submodule update --init libraries/$$library/latest ;\
+ done; \
+ $(MAKE) -j$(NPROC) timing
+
+### OPEN_PDKS
+$(PDK_ROOT)/open_pdks:
+ git clone $(shell $(PYTHON_BIN) ./dependencies/tool.py open_pdks -f repo) $(PDK_ROOT)/open_pdks
+
+.PHONY: open_pdks
+open_pdks: $(PDK_ROOT)/ $(PDK_ROOT)/open_pdks
+ cd $(PDK_ROOT)/open_pdks && \
+ git checkout master && \
+ git pull && \
+ git checkout -qf $(OPEN_PDKS_COMMIT)
+
+.PHONY: build-open_pdks
+build-open_pdks: $(PDK_ROOT)/open_pdks $(PDK_ROOT)/skywater-pdk
+ [ -d $(PDK_ROOT)/sky130A ] && rm -rf $(PDK_ROOT)/sky130A || true
+
+ $(ENV_COMMAND) sh -c "\
+ cd $(PDK_ROOT)/open_pdks && \
+ ./configure --enable-sky130-pdk=$(PDK_ROOT)/skywater-pdk/libraries $(OPEN_PDK_ARGS)\
+ "
+
+ cd $(PDK_ROOT)/open_pdks/sky130 && \
+ $(MAKE) veryclean && \
+ $(MAKE) prerequisites
+
+ $(ENV_COMMAND) sh -c "\
+ cd $(PDK_ROOT)/open_pdks/sky130 && \
+ make && \
+ make SHARED_PDKS_PATH=$(PDK_ROOT) install && \
+ make clean \
+ "
+
+gen-sources: $(PDK_ROOT)/sky130A
+ touch $(PDK_ROOT)/sky130A/SOURCES
+ OPENLANE_COMMIT=$(git rev-parse HEAD)
+ printf "openlane " > $(PDK_ROOT)/sky130A/SOURCES
+ cd $(OPENLANE_DIR) && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
+ printf "magic " >> $(PDK_ROOT)/sky130A/SOURCES
+ python3 ./dependencies/tool.py -f commit magic >> $(PDK_ROOT)/sky130A/SOURCES
+ printf "\n" >> $(PDK_ROOT)/sky130A/SOURCES
+ printf "skywater-pdk " >> $(PDK_ROOT)/sky130A/SOURCES
+ cd $(PDK_ROOT)/skywater-pdk && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
+ printf "open_pdks " >> $(PDK_ROOT)/sky130A/SOURCES
+ cd $(PDK_ROOT)/open_pdks && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
diff --git a/openlane/dependencies/python/compile_time.txt b/openlane/dependencies/python/compile_time.txt
new file mode 100644
index 0000000..c013f73
--- /dev/null
+++ b/openlane/dependencies/python/compile_time.txt
@@ -0,0 +1,2 @@
+cmake
+pyinstaller
\ No newline at end of file
diff --git a/openlane/dependencies/python/precompile_time.txt b/openlane/dependencies/python/precompile_time.txt
new file mode 100644
index 0000000..9f60e78
--- /dev/null
+++ b/openlane/dependencies/python/precompile_time.txt
@@ -0,0 +1,2 @@
+pip
+wheel
\ No newline at end of file
diff --git a/openlane/dependencies/python/run_time.txt b/openlane/dependencies/python/run_time.txt
new file mode 100644
index 0000000..1f25abb
--- /dev/null
+++ b/openlane/dependencies/python/run_time.txt
@@ -0,0 +1,4 @@
+click~=8.0.0
+pyyaml~=5.4.0
+install~=1.3.5
+XlsxWriter~=3.0.2
\ No newline at end of file
diff --git a/openlane/dependencies/tool.py b/openlane/dependencies/tool.py
new file mode 100644
index 0000000..04e35f6
--- /dev/null
+++ b/openlane/dependencies/tool.py
@@ -0,0 +1,165 @@
+#!/usr/bin/env python3
+# Copyright 2021-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import sys
+from typing import Dict, List
+
+sys.path.append(os.path.dirname(__file__))
+import includedyaml as yaml # noqa: E402
+
+
+class Tool(object):
+ by_name: Dict[str, "Tool"]
+
+ def __init__(
+ self,
+ name,
+ repo,
+ commit,
+ build_script="make && make install",
+ default_branch=None,
+ in_install=True,
+ in_container=True,
+ dependencies=[],
+ pdk=False,
+ ):
+ self.name = name
+ self.repo = repo
+ self.commit = commit
+ self.build_script = build_script
+ self.default_branch = default_branch
+ self.in_install = in_install
+ self.in_container = in_container
+ self.dependencies = dependencies
+ self.pdk = pdk
+
+ def __repr__(self) -> str:
+ return f"<Tool {self.name} (using {self.repo_pretty or 'None'}@{self.commit or 'None'})>"
+
+ @property
+ def repo_pretty(self):
+ gh_prefix = "https://github.com/"
+ repo = self.repo
+ if repo is not None and repo.startswith(gh_prefix):
+ return repo[len(gh_prefix) :]
+ return repo
+
+ @property
+ def version_string(self) -> str:
+ return f"{self.repo or 'None'}:{self.commit or 'None'}"
+
+ def get_docker_tag(self, for_os: str) -> str:
+ return f"{self.name}-{self.commit}-{for_os}"
+
+ @property
+ def docker_args(self) -> List[str]:
+ return [
+ "--build-arg",
+ f"{self.name.upper()}_REPO={self.repo}",
+ "--build-arg",
+ f"{self.name.upper()}_COMMIT={self.commit}",
+ ]
+
+ @staticmethod
+ def from_metadata_yaml(metadata_yaml: str) -> Dict[str, "Tool"]:
+ final_dict = {}
+ tool_list = yaml.load(metadata_yaml, Loader=yaml.SafeLoader)
+ for tool in tool_list:
+ final_dict[tool["name"]] = Tool(
+ name=tool["name"],
+ repo=tool["repo"],
+ commit=tool["commit"],
+ build_script=tool.get("build") or "",
+ default_branch=tool.get("default_branch") or None,
+ in_container=tool["in_container"]
+ if tool.get("in_container") is not None
+ else True,
+ in_install=tool["in_install"]
+ if tool.get("in_install") is not None
+ else True,
+ dependencies=tool.get("dependencies") or [],
+ pdk=tool.get("pdk") or False,
+ )
+ return final_dict
+
+
+Tool.by_name = Tool.from_metadata_yaml(
+ open(os.path.join(os.path.dirname(__file__), "tool_metadata.yml")).read()
+)
+
+
+def main():
+ import os
+ import argparse
+
+ parser = argparse.ArgumentParser(description="Get Tool Info")
+ parser.add_argument("--containerized", action="store_true")
+ parser.add_argument("--docker-args", action="store_true")
+ parser.add_argument("--no-pdks", action="store_true")
+ parser.add_argument("--docker-tag-for-os", default=None)
+ parser.add_argument("--field", "-f")
+ parser.add_argument("tool")
+ args = parser.parse_args()
+
+ if args.no_pdks:
+ pdk_keys = []
+ for key, value in Tool.by_name.items():
+ if value.pdk:
+ pdk_keys.append(key)
+
+ for key in pdk_keys:
+ del Tool.by_name[key]
+
+ if args.containerized:
+ for tool in Tool.by_name.values():
+ if tool.in_container:
+ print(tool.name, end=" ")
+ exit(0)
+
+ try:
+ tool = Tool.by_name[args.tool]
+ except Exception:
+ print(f"Unknown tool {args.tool}.", file=sys.stderr)
+ exit(os.EX_DATAERR)
+
+ if args.docker_tag_for_os:
+ print(tool.get_docker_tag(for_os=args.docker_tag_for_os))
+ elif args.docker_args:
+ arg_list = tool.docker_args
+
+ # 1. Dependents
+ dependents = []
+ for dependent in Tool.by_name.values():
+ if tool.name in dependent.dependencies:
+ dependents.append(dependent)
+ for dependent in dependents:
+ arg_list += dependent.docker_args
+
+ # 2. Dependencies
+ for dependency_name in tool.dependencies:
+ dependency = Tool.by_name[dependency_name]
+ arg_list += dependency.docker_args
+
+ print(" ".join(arg_list), end="")
+ elif args.field:
+ field = tool.__dict__[args.field]
+ print(field, end="")
+ else:
+ parser.print_help(file=sys.stderr)
+ exit(os.EX_USAGE)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/openlane/dependencies/tool_metadata.yml b/openlane/dependencies/tool_metadata.yml
new file mode 100644
index 0000000..7b1f22c
--- /dev/null
+++ b/openlane/dependencies/tool_metadata.yml
@@ -0,0 +1,108 @@
+- name: cugr
+ repo: https://github.com/ax3ghazy/cu-gr
+ commit: 1632b4b450cbd3e5b6bdc9bf92c96cadde6a01b9
+ build: |
+ xxd -i src/flute/POST9.dat > src/flute/POST9.c
+ xxd -i src/flute/POWV9.dat > src/flute/POWV9.c
+ rm -rf build/
+ mkdir -p build/
+ cd build
+ cmake ../src
+ make clean
+ make -j$(nproc)
+ cp iccad19gr $PREFIX/bin/cugr
+ in_install: false
+- name: cvc
+ repo: https://github.com/d-m-bailey/cvc
+ commit: d172016a791af3089b28070d80ad92bdfef9c585
+ build: |
+ autoreconf -i
+ ./configure --disable-nls --prefix=$PREFIX
+ make clean
+ make -j$(nproc) $READLINE_CXXFLAGS
+ make install
+- name: drcu
+ repo: https://github.com/cuhk-eda/dr-cu
+ commit: 427b4a4f03bb98d8a78b1712fe9e52cfb83a8347
+ build: |
+ rm -rf build/
+ mkdir -p build/
+ cd build
+ cmake ../src
+ make clean
+ make -j$(nproc)
+ cp ispd19dr $PREFIX/bin/drcu
+ in_install: false
+- name: magic
+ repo: https://github.com/rtimothyedwards/magic
+ commit: a205a0e9419f973346740171618956afe08b2d74
+ build: |
+ ./configure --prefix=$PREFIX $MAGIC_CONFIG_OPTS
+ make clean
+ make -j$(nproc)
+ make install
+- name: netgen
+ repo: https://github.com/rtimothyedwards/netgen
+ commit: bfb01e032f668c09ff43e889f35d611ef0e4a317
+ build: |
+ ./configure --prefix=$PREFIX $MAGIC_CONFIG_OPTS
+ make clean
+ make -j$(nproc)
+ make install
+- name: padring
+ repo: https://github.com/donn/padring
+ commit: b2a64abcc8561d758c0bcb3945117dcb13bd9dca
+ build: |
+ bash ./bootstrap.sh
+ cd build
+ ninja clean
+ ninja
+ cp padring $PREFIX/bin
+- name: vlogtoverilog
+ repo: https://github.com/RTimothyEdwards/qflow
+ commit: a550469b63e910ede6e3022e2886bca96462c540
+ build: |
+ # Note that vlogtoverilog is part of the qflow repository.
+ ./configure
+ cd src
+ make clean
+ make -j$(nproc) vlog2Verilog
+ cp vlog2Verilog $PREFIX/bin
+- name: yosys
+ repo: https://github.com/YosysHQ/yosys
+ commit: cfe940a98b08f1a5d08fb44427db155ba1f18b62
+ build: |
+ make clean
+ make PREFIX=$PREFIX config-gcc
+ make PREFIX=$PREFIX -j$(nproc)
+ make PREFIX=$PREFIX install
+- name: klayout
+ repo: https://github.com/KLayout/klayout
+ commit: 428d0fe8c941faece4eceebc54170cc04d916c03
+ build: ''
+ in_install: false
+- name: openroad_app
+ repo: https://github.com/The-OpenROAD-Project/OpenROAD
+ commit: 79a46b62da64bbebc18f06b20c42211046de719a
+ build: ''
+ in_install: false
+- name: git
+ repo: https://github.com/git/git
+ commit: e9d7761bb94f20acc98824275e317fa82436c25d
+ build: ''
+ in_install: false
+- name: open_pdks
+ repo: https://github.com/efabless/open_pdks
+ commit: 41c0908b47130d5675ff8484255b43f66463a7d6
+ build: ''
+ in_install: false
+ pdk: true
+ dependencies:
+ - sky130
+ - magic
+- name: sky130
+ repo: https://github.com/google/skywater-pdk
+ commit: f70d8ca46961ff92719d8870a18a076370b85f6c
+ build: ''
+ in_install: false
+ in_container: false
diff --git a/openlane/dependencies/ubuntu-20.04/run_time.txt b/openlane/dependencies/ubuntu-20.04/run_time.txt
new file mode 100644
index 0000000..b565ea9
--- /dev/null
+++ b/openlane/dependencies/ubuntu-20.04/run_time.txt
@@ -0,0 +1,48 @@
+xvfb
+autoconf
+autopoint
+bison
+bzip2
+libcairo-dev
+clang
+csh
+curl
+flex
+gawk
+gcc
+gdb
+gettext
+git
+graphviz
+help2man
+libeigen3-dev
+libsm-dev
+libx11-dev
+libffi-dev
+libgomp1
+libjpeg9-dev
+libxml2-dev
+libxslt-dev
+libffi-dev
+libspdlog-dev
+make
+ncurses-dev
+ninja-build
+patch
+libpcre2-dev
+python3
+python3-pip
+python3-dev
+python3-tk
+libreadline-dev
+strace
+swig
+tcl-dev
+tk-dev
+tcllib
+tclx8.4-dev
+texinfo
+neovim
+wget
+xdot
+zlib1g
diff --git a/openlane/dependencies/update_pyyaml.sh b/openlane/dependencies/update_pyyaml.sh
new file mode 100644
index 0000000..d02cadd
--- /dev/null
+++ b/openlane/dependencies/update_pyyaml.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+<<DOC
+# What is this?
+A script to manually update the includedyaml file from pyyaml upstream.
+
+# Why?
+These scripts are used in an environment where PIP may not be available,
+and obligatory submodules are a layer of complexity we could really do without.
+
+---
+
+Requires curl, GNU Tar and black.
+DOC
+
+GTAR_BIN=gtar
+if ! [ -x "$(command -v $GTAR_BIN)" ]; then
+ GTAR_BIN=tar
+fi
+
+rm -rf ./includedyaml
+mkdir -p ./includedyaml
+curl -L https://github.com/yaml/pyyaml/tarball/master | $GTAR_BIN --wildcards --strip-components=3 -xvz -C ./includedyaml '*/lib/yaml'
+curl -L https://raw.githubusercontent.com/yaml/pyyaml/master/LICENSE > ./includedyaml/LICENSE
+black ./includedyaml
\ No newline at end of file
diff --git a/openlane/dependencies/verify_versions.py b/openlane/dependencies/verify_versions.py
new file mode 100644
index 0000000..ea52242
--- /dev/null
+++ b/openlane/dependencies/verify_versions.py
@@ -0,0 +1,249 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import re
+import io
+import sys
+import json
+import pathlib
+import traceback
+from os.path import dirname, abspath, join
+from typing import Optional
+
+sys.path.append(os.path.dirname(__file__))
+import includedyaml as yaml # noqa: E402
+
+openlane_dir = abspath(dirname(dirname(__file__)))
+
+
+def verify_versions(
+ no_pdks: bool = False,
+ no_tools: bool = False,
+ report_file: io.TextIOBase = sys.stderr,
+ pdk: Optional[str] = os.getenv("PDK"),
+):
+ # 1. Load Current Flow Script Manifest
+ manifest = None
+ try:
+ flow_script_manifest_path = join(
+ openlane_dir, "dependencies", "tool_metadata.yml"
+ )
+ manifest = yaml.safe_load(open(flow_script_manifest_path))
+ except FileNotFoundError:
+ raise Exception(
+ "Flow script tool manifest not found. This is a fatal error."
+ ) # Is this even possible?
+
+ manifest_dict = {element["name"]: element for element in manifest}
+ mismatches = False
+
+ manifest_names_by_SOURCES_name = {
+ "open_pdks": "open_pdks",
+ "skywater": "sky130",
+ "magic": "magic",
+ }
+ pdk_manifest_names = set(manifest_names_by_SOURCES_name.values())
+
+ if not no_pdks:
+ try:
+ # 2. Check if the PDK is compatible with Flow Scripts
+ pdk_root = os.getenv("PDK_ROOT")
+ if not os.getenv("PDK_ROOT"):
+ pdk_root = join(openlane_dir, "pdks")
+
+ if pdk is not None:
+ pdk_dir = join(pdk_root, pdk)
+
+ if not pathlib.Path(pdk_dir).is_dir():
+ raise Exception(f"{pdk_dir} not found.")
+
+ tool_versions = []
+
+ sources_file = join(pdk_dir, "SOURCES")
+ config_file = join(pdk_dir, ".config", "nodeinfo.json")
+
+ if os.path.isfile(sources_file):
+ sources_str = None
+ try:
+ sources_str = open(sources_file).read()
+ except FileNotFoundError:
+ raise Exception(
+ f"Could not find SOURCES file for the installed {pdk} PDK."
+ )
+
+ sources_str = sources_str.strip()
+
+ # Format: {tool} {commit}
+ #
+ # This regex also handles an issue where older versions used the
+ # non-standard echo -ne command, where the format is -ne {tool}\n{commit}\n.
+ #
+ name_rx = re.compile(
+ r"(?:\-ne\s+)?([\w\-]+)\s+([A-Fa-f0-9]+)", re.MULTILINE
+ )
+
+ for tool_match in name_rx.finditer(sources_str):
+ name = tool_match[1]
+ commit = tool_match[2]
+
+ manifest_name = manifest_names_by_SOURCES_name.get(name)
+ if manifest_name is None:
+ continue
+
+ tool_versions.append((manifest_name, commit))
+ elif os.path.isfile(config_file):
+ config_str = open(config_file).read()
+ try:
+ config = json.loads(config_str)
+ commit_set = config["commit"]
+ if type(commit_set) == str:
+ tool_versions.append(("open_pdks", commit_set))
+ else:
+ for key, value in commit_set.items():
+ # Handle bug in some older versions of opdks where the magic commit field is empty.
+ if value.strip() == "":
+ continue
+ tool_versions.append((key, value))
+ except json.decoder.JSONDecodeError:
+ raise Exception("Malformed .config/nodeinfo.json.")
+
+ else:
+ raise Exception(
+ "Neither SOURCES nor .config/nodeinfo.json exist in the PDK."
+ )
+
+ for name, commit in tool_versions:
+ manifest_commit = manifest_dict[name]["commit"]
+
+ if commit != manifest_commit:
+ mismatches = True
+ print(
+ f"The version of {name} used in building the PDK does not match the version OpenLane was tested on (installed: {commit}, tested: {manifest_commit})",
+ file=report_file,
+ )
+ print(
+ "This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.",
+ file=report_file,
+ )
+
+ pdk_manifest_names.add(name)
+ except Exception as e:
+ print(e, file=report_file)
+ print(traceback.format_exc(), file=report_file)
+ raise Exception("Failed to compare PDKs.")
+
+ if not no_tools:
+ installed = os.getenv("OPENLANE_LOCAL_INSTALL") == "1"
+ environment_manifest = None
+ if installed:
+ # 3a. Compare with installed versions
+ installed_versions_path = join(
+ os.environ["OL_INSTALL_DIR"], "build", "versions"
+ )
+ environment_manifest = []
+ for tool in os.listdir(installed_versions_path):
+ protocol, url, commit = (
+ open(join(installed_versions_path, tool)).read().split(":")
+ )
+ repo = f"{protocol}:{url}"
+ environment_manifest.append(
+ {"name": tool, "repo": repo, "commit": commit}
+ )
+ else:
+ # 3b. Compare Container And Installation Manifests
+ try:
+ container_manifest_path = join("/", "tool_metadata.yml")
+ environment_manifest = yaml.safe_load(open(container_manifest_path))
+ except FileNotFoundError:
+ raise Exception(
+ "Container manifest not found. What this likely means is that the container is severely out of date."
+ )
+
+ tool_set_flow = (
+ set([element["name"] for element in manifest]) - pdk_manifest_names
+ )
+ tool_set_container = (
+ set([element["name"] for element in environment_manifest])
+ - pdk_manifest_names
+ )
+
+ unmatched_tools_flow = tool_set_flow - tool_set_container
+ for tool in unmatched_tools_flow:
+ tool_object = manifest_dict[tool]
+ if (
+ tool_object.get("in_container") is not None
+ and not tool_object["in_container"]
+ ):
+ continue
+ if (
+ installed
+ and tool_object.get("in_install") is not None
+ and not tool_object["in_install"]
+ ):
+ continue
+ print(
+ f"Tool {tool} is required by the flow scripts being used, but appears to not be installed in the environment.",
+ file=report_file,
+ )
+ mismatches = True
+
+ unmatched_tools_container = tool_set_container - tool_set_flow
+ for tool in unmatched_tools_container:
+ print(
+ f"Tool {tool} is installed in the environment, but has no corresponding entry in the flow scripts.",
+ file=report_file,
+ )
+ mismatches = True
+
+ for tool in environment_manifest:
+ if tool["name"] in pdk_manifest_names:
+ continue # PDK Stuff Already Checked
+ flow_script_counterpart = manifest_dict.get(tool["name"])
+ if flow_script_counterpart is None:
+ continue
+ container_commit = tool["commit"]
+ flow_script_commit = flow_script_counterpart["commit"]
+ if container_commit != flow_script_commit:
+ print(
+ f"The version of {tool['name']} installed in the environment does not match the one required by the OpenLane flow scripts (installed: {container_commit}, expected: {flow_script_commit})",
+ file=report_file,
+ )
+ mismatches = True
+
+ return mismatches
+
+
+if __name__ == "__main__":
+ try:
+ no_tools = False
+ no_pdks = False
+ mismatches = os.getenv("TEST_MISMATCHES") or "all"
+ if mismatches == "none":
+ no_tools = True
+ no_pdks = True
+ elif mismatches == "pdk":
+ no_tools = True
+ elif mismatches == "tools":
+ no_pdks = True
+ elif mismatches != "all":
+ print(f"Unknown mismatch test '{mismatches}'.", file=sys.stderr)
+ sys.exit(-1)
+ mismatches = verify_versions(no_tools=no_tools, no_pdks=no_pdks)
+ sys.exit(os.EX_CONFIG if mismatches else os.EX_OK)
+ except Exception as e:
+ print(f"{e}")
+ sys.exit(os.EX_UNAVAILABLE)
diff --git a/openlane/dependencies/version.py b/openlane/dependencies/version.py
new file mode 100644
index 0000000..191f61a
--- /dev/null
+++ b/openlane/dependencies/version.py
@@ -0,0 +1,671 @@
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# https://github.com/pypa/packaging - _structures.py, version.py
+# Copyright (c) Donald Stufft and individual contributors.
+# All rights reserved.
+
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from __future__ import absolute_import, division, print_function
+
+import collections
+import itertools
+import re
+import warnings
+
+
+class InfinityType(object):
+ def __repr__(self):
+ # type: () -> str
+ return "Infinity"
+
+ def __hash__(self):
+ # type: () -> int
+ return hash(repr(self))
+
+ def __lt__(self, other):
+ # type: (object) -> bool
+ return False
+
+ def __le__(self, other):
+ # type: (object) -> bool
+ return False
+
+ def __eq__(self, other):
+ # type: (object) -> bool
+ return isinstance(other, self.__class__)
+
+ def __ne__(self, other):
+ # type: (object) -> bool
+ return not isinstance(other, self.__class__)
+
+ def __gt__(self, other):
+ # type: (object) -> bool
+ return True
+
+ def __ge__(self, other):
+ # type: (object) -> bool
+ return True
+
+ def __neg__(self):
+ # type: (object) -> NegativeInfinityType
+ return NegativeInfinity
+
+
+Infinity = InfinityType()
+
+
+class NegativeInfinityType(object):
+ def __repr__(self):
+ # type: () -> str
+ return "-Infinity"
+
+ def __hash__(self):
+ # type: () -> int
+ return hash(repr(self))
+
+ def __lt__(self, other):
+ # type: (object) -> bool
+ return True
+
+ def __le__(self, other):
+ # type: (object) -> bool
+ return True
+
+ def __eq__(self, other):
+ # type: (object) -> bool
+ return isinstance(other, self.__class__)
+
+ def __ne__(self, other):
+ # type: (object) -> bool
+ return not isinstance(other, self.__class__)
+
+ def __gt__(self, other):
+ # type: (object) -> bool
+ return False
+
+ def __ge__(self, other):
+ # type: (object) -> bool
+ return False
+
+ def __neg__(self):
+ # type: (object) -> InfinityType
+ return Infinity
+
+
+NegativeInfinity = NegativeInfinityType()
+
+
+try:
+ from typing import Callable, Iterator, List, Optional, SupportsInt, Tuple, Union
+
+ InfiniteTypes = Union[InfinityType, NegativeInfinityType]
+ PrePostDevType = Union[InfiniteTypes, Tuple[str, int]]
+ SubLocalType = Union[InfiniteTypes, int, str]
+ LocalType = Union[
+ NegativeInfinityType,
+ Tuple[
+ Union[
+ SubLocalType,
+ Tuple[SubLocalType, str],
+ Tuple[NegativeInfinityType, SubLocalType],
+ ],
+ ...,
+ ],
+ ]
+ CmpKey = Tuple[
+ int, Tuple[int, ...], PrePostDevType, PrePostDevType, PrePostDevType, LocalType
+ ]
+ LegacyCmpKey = Tuple[int, Tuple[str, ...]]
+ VersionComparisonMethod = Callable[
+ [Union[CmpKey, LegacyCmpKey], Union[CmpKey, LegacyCmpKey]], bool
+ ]
+except ImportError:
+ pass
+
+__all__ = ["parse", "Version", "LegacyVersion", "InvalidVersion", "VERSION_PATTERN"]
+
+
+_Version = collections.namedtuple(
+ "_Version", ["epoch", "release", "dev", "pre", "post", "local"]
+)
+
+
+def parse(version):
+ # type: (str) -> Union[LegacyVersion, Version]
+ """
+ Parse the given version string and return either a :class:`Version` object
+ or a :class:`LegacyVersion` object depending on if the given version is
+ a valid PEP 440 version or a legacy version.
+ """
+ try:
+ return Version(version)
+ except InvalidVersion:
+ return LegacyVersion(version)
+
+
+class InvalidVersion(ValueError):
+ """
+ An invalid version was found, users should refer to PEP 440.
+ """
+
+
+class _BaseVersion(object):
+ _key = None # type: Union[CmpKey, LegacyCmpKey]
+
+ def __hash__(self):
+ # type: () -> int
+ return hash(self._key)
+
+ # Please keep the duplicated `isinstance` check
+ # in the six comparisons hereunder
+ # unless you find a way to avoid adding overhead function calls.
+ def __lt__(self, other):
+ # type: (_BaseVersion) -> bool
+ if not isinstance(other, _BaseVersion):
+ return NotImplemented
+
+ return self._key < other._key
+
+ def __le__(self, other):
+ # type: (_BaseVersion) -> bool
+ if not isinstance(other, _BaseVersion):
+ return NotImplemented
+
+ return self._key <= other._key
+
+ def __eq__(self, other):
+ # type: (object) -> bool
+ if not isinstance(other, _BaseVersion):
+ return NotImplemented
+
+ return self._key == other._key
+
+ def __ge__(self, other):
+ # type: (_BaseVersion) -> bool
+ if not isinstance(other, _BaseVersion):
+ return NotImplemented
+
+ return self._key >= other._key
+
+ def __gt__(self, other):
+ # type: (_BaseVersion) -> bool
+ if not isinstance(other, _BaseVersion):
+ return NotImplemented
+
+ return self._key > other._key
+
+ def __ne__(self, other):
+ # type: (object) -> bool
+ if not isinstance(other, _BaseVersion):
+ return NotImplemented
+
+ return self._key != other._key
+
+
+class LegacyVersion(_BaseVersion):
+ def __init__(self, version):
+ # type: (str) -> None
+ self._version = str(version)
+ self._key = _legacy_cmpkey(self._version)
+
+ warnings.warn(
+ "Creating a LegacyVersion has been deprecated and will be removed in the next major release",
+ DeprecationWarning,
+ )
+
+ def __str__(self):
+ # type: () -> str
+ return self._version
+
+ def __repr__(self):
+ # type: () -> str
+ return "<LegacyVersion({0})>".format(repr(str(self)))
+
+ @property
+ def public(self):
+ # type: () -> str
+ return self._version
+
+ @property
+ def base_version(self):
+ # type: () -> str
+ return self._version
+
+ @property
+ def epoch(self):
+ # type: () -> int
+ return -1
+
+ @property
+ def release(self):
+ # type: () -> None
+ return None
+
+ @property
+ def pre(self):
+ # type: () -> None
+ return None
+
+ @property
+ def post(self):
+ # type: () -> None
+ return None
+
+ @property
+ def dev(self):
+ # type: () -> None
+ return None
+
+ @property
+ def local(self):
+ # type: () -> None
+ return None
+
+ @property
+ def is_prerelease(self):
+ # type: () -> bool
+ return False
+
+ @property
+ def is_postrelease(self):
+ # type: () -> bool
+ return False
+
+ @property
+ def is_devrelease(self):
+ # type: () -> bool
+ return False
+
+
+_legacy_version_component_re = re.compile(r"(\d+ | [a-z]+ | \.| -)", re.VERBOSE)
+
+_legacy_version_replacement_map = {
+ "pre": "c",
+ "preview": "c",
+ "-": "final-",
+ "rc": "c",
+ "dev": "@",
+}
+
+
+def _parse_version_parts(s):
+ # type: (str) -> Iterator[str]
+ for part in _legacy_version_component_re.split(s):
+ part = _legacy_version_replacement_map.get(part, part)
+
+ if not part or part == ".":
+ continue
+
+ if part[:1] in "0123456789":
+ # pad for numeric comparison
+ yield part.zfill(8)
+ else:
+ yield "*" + part
+
+ # ensure that alpha/beta/candidate are before final
+ yield "*final"
+
+
+def _legacy_cmpkey(version):
+ # type: (str) -> LegacyCmpKey
+
+ # We hardcode an epoch of -1 here. A PEP 440 version can only have a epoch
+ # greater than or equal to 0. This will effectively put the LegacyVersion,
+ # which uses the defacto standard originally implemented by setuptools,
+ # as before all PEP 440 versions.
+ epoch = -1
+
+ # This scheme is taken from pkg_resources.parse_version setuptools prior to
+ # it's adoption of the packaging library.
+ parts = [] # type: List[str]
+ for part in _parse_version_parts(version.lower()):
+ if part.startswith("*"):
+ # remove "-" before a prerelease tag
+ if part < "*final":
+ while parts and parts[-1] == "*final-":
+ parts.pop()
+
+ # remove trailing zeros from each series of numeric parts
+ while parts and parts[-1] == "00000000":
+ parts.pop()
+
+ parts.append(part)
+
+ return epoch, tuple(parts)
+
+
+# Deliberately not anchored to the start and end of the string, to make it
+# easier for 3rd party code to reuse
+VERSION_PATTERN = r"""
+ v?
+ (?:
+ (?:(?P<epoch>[0-9]+)!)? # epoch
+ (?P<release>[0-9]+(?:\.[0-9]+)*) # release segment
+ (?P<pre> # pre-release
+ [-_\.]?
+ (?P<pre_l>(a|b|c|rc|alpha|beta|pre|preview))
+ [-_\.]?
+ (?P<pre_n>[0-9]+)?
+ )?
+ (?P<post> # post release
+ (?:-(?P<post_n1>[0-9]+))
+ |
+ (?:
+ [-_\.]?
+ (?P<post_l>post|rev|r)
+ [-_\.]?
+ (?P<post_n2>[0-9]+)?
+ )
+ )?
+ (?P<dev> # dev release
+ [-_\.]?
+ (?P<dev_l>dev)
+ [-_\.]?
+ (?P<dev_n>[0-9]+)?
+ )?
+ )
+ (?:\+(?P<local>[a-z0-9]+(?:[-_\.][a-z0-9]+)*))? # local version
+"""
+
+
+class Version(_BaseVersion):
+
+ _regex = re.compile(r"^\s*" + VERSION_PATTERN + r"\s*$", re.VERBOSE | re.IGNORECASE)
+
+ def __init__(self, version):
+ # type: (str) -> None
+
+ # Validate the version and parse it into pieces
+ match = self._regex.search(version)
+ if not match:
+ raise InvalidVersion("Invalid version: '{0}'".format(version))
+
+ # Store the parsed out pieces of the version
+ self._version = _Version(
+ epoch=int(match.group("epoch")) if match.group("epoch") else 0,
+ release=tuple(int(i) for i in match.group("release").split(".")),
+ pre=_parse_letter_version(match.group("pre_l"), match.group("pre_n")),
+ post=_parse_letter_version(
+ match.group("post_l"), match.group("post_n1") or match.group("post_n2")
+ ),
+ dev=_parse_letter_version(match.group("dev_l"), match.group("dev_n")),
+ local=_parse_local_version(match.group("local")),
+ )
+
+ # Generate a key which will be used for sorting
+ self._key = _cmpkey(
+ self._version.epoch,
+ self._version.release,
+ self._version.pre,
+ self._version.post,
+ self._version.dev,
+ self._version.local,
+ )
+
+ def __repr__(self):
+ # type: () -> str
+ return "<Version({0})>".format(repr(str(self)))
+
+ def __str__(self):
+ # type: () -> str
+ parts = []
+
+ # Epoch
+ if self.epoch != 0:
+ parts.append("{0}!".format(self.epoch))
+
+ # Release segment
+ parts.append(".".join(str(x) for x in self.release))
+
+ # Pre-release
+ if self.pre is not None:
+ parts.append("".join(str(x) for x in self.pre))
+
+ # Post-release
+ if self.post is not None:
+ parts.append(".post{0}".format(self.post))
+
+ # Development release
+ if self.dev is not None:
+ parts.append(".dev{0}".format(self.dev))
+
+ # Local version segment
+ if self.local is not None:
+ parts.append("+{0}".format(self.local))
+
+ return "".join(parts)
+
+ @property
+ def epoch(self):
+ # type: () -> int
+ _epoch = self._version.epoch # type: int
+ return _epoch
+
+ @property
+ def release(self):
+ # type: () -> Tuple[int, ...]
+ _release = self._version.release # type: Tuple[int, ...]
+ return _release
+
+ @property
+ def pre(self):
+ # type: () -> Optional[Tuple[str, int]]
+ _pre = self._version.pre # type: Optional[Tuple[str, int]]
+ return _pre
+
+ @property
+ def post(self):
+ # type: () -> Optional[int]
+ return self._version.post[1] if self._version.post else None
+
+ @property
+ def dev(self):
+ # type: () -> Optional[int]
+ return self._version.dev[1] if self._version.dev else None
+
+ @property
+ def local(self):
+ # type: () -> Optional[str]
+ if self._version.local:
+ return ".".join(str(x) for x in self._version.local)
+ else:
+ return None
+
+ @property
+ def public(self):
+ # type: () -> str
+ return str(self).split("+", 1)[0]
+
+ @property
+ def base_version(self):
+ # type: () -> str
+ parts = []
+
+ # Epoch
+ if self.epoch != 0:
+ parts.append("{0}!".format(self.epoch))
+
+ # Release segment
+ parts.append(".".join(str(x) for x in self.release))
+
+ return "".join(parts)
+
+ @property
+ def is_prerelease(self):
+ # type: () -> bool
+ return self.dev is not None or self.pre is not None
+
+ @property
+ def is_postrelease(self):
+ # type: () -> bool
+ return self.post is not None
+
+ @property
+ def is_devrelease(self):
+ # type: () -> bool
+ return self.dev is not None
+
+ @property
+ def major(self):
+ # type: () -> int
+ return self.release[0] if len(self.release) >= 1 else 0
+
+ @property
+ def minor(self):
+ # type: () -> int
+ return self.release[1] if len(self.release) >= 2 else 0
+
+ @property
+ def micro(self):
+ # type: () -> int
+ return self.release[2] if len(self.release) >= 3 else 0
+
+
+def _parse_letter_version(
+ letter, # type: str
+ number, # type: Union[str, bytes, SupportsInt]
+):
+ # type: (...) -> Optional[Tuple[str, int]]
+
+ if letter:
+ # We consider there to be an implicit 0 in a pre-release if there is
+ # not a numeral associated with it.
+ if number is None:
+ number = 0
+
+ # We normalize any letters to their lower case form
+ letter = letter.lower()
+
+ # We consider some words to be alternate spellings of other words and
+ # in those cases we want to normalize the spellings to our preferred
+ # spelling.
+ if letter == "alpha":
+ letter = "a"
+ elif letter == "beta":
+ letter = "b"
+ elif letter in ["c", "pre", "preview"]:
+ letter = "rc"
+ elif letter in ["rev", "r"]:
+ letter = "post"
+
+ return letter, int(number)
+ if not letter and number:
+ # We assume if we are given a number, but we are not given a letter
+ # then this is using the implicit post release syntax (e.g. 1.0-1)
+ letter = "post"
+
+ return letter, int(number)
+
+ return None
+
+
+_local_version_separators = re.compile(r"[\._-]")
+
+
+def _parse_local_version(local):
+ # type: (str) -> Optional[LocalType]
+ """
+ Takes a string like abc.1.twelve and turns it into ("abc", 1, "twelve").
+ """
+ if local is not None:
+ return tuple(
+ part.lower() if not part.isdigit() else int(part)
+ for part in _local_version_separators.split(local)
+ )
+ return None
+
+
+def _cmpkey(
+ epoch, # type: int
+ release, # type: Tuple[int, ...]
+ pre, # type: Optional[Tuple[str, int]]
+ post, # type: Optional[Tuple[str, int]]
+ dev, # type: Optional[Tuple[str, int]]
+ local, # type: Optional[Tuple[SubLocalType]]
+):
+ # type: (...) -> CmpKey
+
+ # When we compare a release version, we want to compare it with all of the
+ # trailing zeros removed. So we'll use a reverse the list, drop all the now
+ # leading zeros until we come to something non zero, then take the rest
+ # re-reverse it back into the correct order and make it a tuple and use
+ # that for our sorting key.
+ _release = tuple(
+ reversed(list(itertools.dropwhile(lambda x: x == 0, reversed(release))))
+ )
+
+ # We need to "trick" the sorting algorithm to put 1.0.dev0 before 1.0a0.
+ # We'll do this by abusing the pre segment, but we _only_ want to do this
+ # if there is not a pre or a post segment. If we have one of those then
+ # the normal sorting rules will handle this case correctly.
+ if pre is None and post is None and dev is not None:
+ _pre = NegativeInfinity # type: PrePostDevType
+ # Versions without a pre-release (except as noted above) should sort after
+ # those with one.
+ elif pre is None:
+ _pre = Infinity
+ else:
+ _pre = pre
+
+ # Versions without a post segment should sort before those with one.
+ if post is None:
+ _post = NegativeInfinity # type: PrePostDevType
+
+ else:
+ _post = post
+
+ # Versions without a development segment should sort after those with one.
+ if dev is None:
+ _dev = Infinity # type: PrePostDevType
+
+ else:
+ _dev = dev
+
+ if local is None:
+ # Versions without a local segment should sort before those with one.
+ _local = NegativeInfinity # type: LocalType
+ else:
+ # Versions with a local segment need that segment parsed to implement
+ # the sorting rules in PEP440.
+ # - Alpha numeric segments sort before numeric segments
+ # - Alpha numeric segments sort lexicographically
+ # - Numeric segments sort numerically
+ # - Shorter versions sort before longer versions when the prefixes
+ # match exactly
+ _local = tuple(
+ (i, "") if isinstance(i, int) else (NegativeInfinity, i) for i in local
+ )
+
+ return epoch, _release, _pre, _post, _dev, _local
diff --git a/openlane/designs/.gitignore b/openlane/designs/.gitignore
new file mode 100644
index 0000000..bc0a362
--- /dev/null
+++ b/openlane/designs/.gitignore
@@ -0,0 +1,8 @@
+*/runs/
+*/lef/
+*/gds/
+*/mag/
+*/config*.tcl
+*/base_config.tcl
+!*/config.tcl
+!*/script.tcl
diff --git a/openlane/designs/APU/config.tcl b/openlane/designs/APU/config.tcl
new file mode 100755
index 0000000..30e2187
--- /dev/null
+++ b/openlane/designs/APU/config.tcl
@@ -0,0 +1,13 @@
+set ::env(DESIGN_NAME) "APU"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/APU.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_PDN_IRDROP) 1
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/APU/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/APU/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..8a405c8
--- /dev/null
+++ b/openlane/designs/APU/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "17.0"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/APU/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/APU/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..50df5fb
--- /dev/null
+++ b/openlane/designs/APU/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(CLOCK_PERIOD) "17.0"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/APU/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/APU/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..50df5fb
--- /dev/null
+++ b/openlane/designs/APU/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(CLOCK_PERIOD) "17.0"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/APU/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/APU/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..50df5fb
--- /dev/null
+++ b/openlane/designs/APU/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(CLOCK_PERIOD) "17.0"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/APU/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/APU/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..50df5fb
--- /dev/null
+++ b/openlane/designs/APU/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(CLOCK_PERIOD) "17.0"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/APU/src/APU.v b/openlane/designs/APU/src/APU.v
new file mode 100644
index 0000000..5ecae16
--- /dev/null
+++ b/openlane/designs/APU/src/APU.v
@@ -0,0 +1,806 @@
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// This program is GPL Licensed. See COPYING for the full license.
+
+module LenCtr_Lookup(input [4:0] X, output [7:0] Yout);
+reg [6:0] Y;
+always @*
+begin
+ case(X)
+ 0: Y = 7'h05;
+ 1: Y = 7'h7F;
+ 2: Y = 7'h0A;
+ 3: Y = 7'h01;
+ 4: Y = 7'h14;
+ 5: Y = 7'h02;
+ 6: Y = 7'h28;
+ 7: Y = 7'h03;
+ 8: Y = 7'h50;
+ 9: Y = 7'h04;
+ 10: Y = 7'h1E;
+ 11: Y = 7'h05;
+ 12: Y = 7'h07;
+ 13: Y = 7'h06;
+ 14: Y = 7'h0D;
+ 15: Y = 7'h07;
+ 16: Y = 7'h06;
+ 17: Y = 7'h08;
+ 18: Y = 7'h0C;
+ 19: Y = 7'h09;
+ 20: Y = 7'h18;
+ 21: Y = 7'h0A;
+ 22: Y = 7'h30;
+ 23: Y = 7'h0B;
+ 24: Y = 7'h60;
+ 25: Y = 7'h0C;
+ 26: Y = 7'h24;
+ 27: Y = 7'h0D;
+ 28: Y = 7'h08;
+ 29: Y = 7'h0E;
+ 30: Y = 7'h10;
+ 31: Y = 7'h0F;
+ endcase
+end
+assign Yout = {Y, 1'b0};
+endmodule
+
+module SquareChan(input clk, input ce, input reset, input sq2,
+ input [1:0] Addr,
+ input [7:0] DIN,
+ input MW,
+ input LenCtr_Clock,
+ input Env_Clock,
+ input Enabled,
+ input [7:0] LenCtr_In,
+ output reg [3:0] Sample,
+ output IsNonZero);
+reg [7:0] LenCtr;
+
+// Register 1
+reg [1:0] Duty;
+reg EnvLoop, EnvDisable, EnvDoReset;
+reg [3:0] Volume, Envelope, EnvDivider;
+wire LenCtrHalt = EnvLoop; // Aliased bit
+assign IsNonZero = (LenCtr != 0);
+// Register 2
+reg SweepEnable, SweepNegate, SweepReset;
+reg [2:0] SweepPeriod, SweepDivider, SweepShift;
+
+reg [10:0] Period;
+reg [11:0] TimerCtr;
+reg [2:0] SeqPos;
+wire [10:0] ShiftedPeriod = (Period >> SweepShift);
+wire [10:0] PeriodRhs = (SweepNegate ? (~ShiftedPeriod + {10'b0, sq2}) : ShiftedPeriod);
+wire [11:0] NewSweepPeriod = Period + PeriodRhs;
+wire ValidFreq = Period[10:3] >= 8 && (SweepNegate || !NewSweepPeriod[11]);
+
+always @(posedge clk) if (reset) begin
+ LenCtr <= 0;
+ Duty <= 0;
+ EnvDoReset <= 0;
+ EnvLoop <= 0;
+ EnvDisable <= 0;
+ Volume <= 0;
+ Envelope <= 0;
+ EnvDivider <= 0;
+ SweepEnable <= 0;
+ SweepNegate <= 0;
+ SweepReset <= 0;
+ SweepPeriod <= 0;
+ SweepDivider <= 0;
+ SweepShift <= 0;
+ Period <= 0;
+ TimerCtr <= 0;
+ SeqPos <= 0;
+ end else if (ce) begin
+ // Check if writing to the regs of this channel
+ // NOTE: This needs to be done before the clocking below.
+ if (MW) begin
+ case(Addr)
+ 0: begin
+// if (sq2) $write("SQ0: Duty=%d, EnvLoop=%d, EnvDisable=%d, Volume=%d\n", DIN[7:6], DIN[5], DIN[4], DIN[3:0]);
+ Duty <= DIN[7:6];
+ EnvLoop <= DIN[5];
+ EnvDisable <= DIN[4];
+ Volume <= DIN[3:0];
+ end
+ 1: begin
+// if (sq2) $write("SQ1: SweepEnable=%d, SweepPeriod=%d, SweepNegate=%d, SweepShift=%d, DIN=%X\n", DIN[7], DIN[6:4], DIN[3], DIN[2:0], DIN);
+ SweepEnable <= DIN[7];
+ SweepPeriod <= DIN[6:4];
+ SweepNegate <= DIN[3];
+ SweepShift <= DIN[2:0];
+ SweepReset <= 1;
+ end
+ 2: begin
+// if (sq2) $write("SQ2: Period=%d. DIN=%X\n", DIN, DIN);
+ Period[7:0] <= DIN;
+ end
+ 3: begin
+ // Upper bits of the period
+// if (sq2) $write("SQ3: PeriodUpper=%d LenCtr=%x DIN=%X\n", DIN[2:0], LenCtr_In, DIN);
+ Period[10:8] <= DIN[2:0];
+ LenCtr <= LenCtr_In;
+ EnvDoReset <= 1;
+ SeqPos <= 0;
+ end
+ endcase
+ end
+
+
+ // Count down the square timer...
+ if (TimerCtr == 0) begin
+ // Timer was clocked
+ TimerCtr <= {Period, 1'b0};
+ SeqPos <= SeqPos - 1;
+ end else begin
+ TimerCtr <= TimerCtr - 1;
+ end
+
+ // Clock the length counter?
+ if (LenCtr_Clock && LenCtr != 0 && !LenCtrHalt) begin
+ LenCtr <= LenCtr - 1;
+ end
+
+ // Clock the sweep unit?
+ if (LenCtr_Clock) begin
+ if (SweepDivider == 0) begin
+ SweepDivider <= SweepPeriod;
+ if (SweepEnable && SweepShift != 0 && ValidFreq)
+ Period <= NewSweepPeriod[10:0];
+ end else begin
+ SweepDivider <= SweepDivider - 1;
+ end
+ if (SweepReset)
+ SweepDivider <= SweepPeriod;
+ SweepReset <= 0;
+ end
+
+ // Clock the envelope generator?
+ if (Env_Clock) begin
+ if (EnvDoReset) begin
+ EnvDivider <= Volume;
+ Envelope <= 15;
+ EnvDoReset <= 0;
+ end else if (EnvDivider == 0) begin
+ EnvDivider <= Volume;
+ if (Envelope != 0 || EnvLoop)
+ Envelope <= Envelope - 1;
+ end else begin
+ EnvDivider <= EnvDivider - 1;
+ end
+ end
+
+ // Length counter forced to zero if disabled.
+ if (!Enabled)
+ LenCtr <= 0;
+end
+
+reg DutyEnabled;
+always @* begin
+ // Determine if the duty is enabled or not
+ case (Duty)
+ 0: DutyEnabled = (SeqPos == 7);
+ 1: DutyEnabled = (SeqPos >= 6);
+ 2: DutyEnabled = (SeqPos >= 4);
+ 3: DutyEnabled = (SeqPos < 6);
+ endcase
+
+ // Compute the output
+ if (LenCtr == 0 || !ValidFreq || !DutyEnabled)
+ Sample = 0;
+ else
+ Sample = EnvDisable ? Volume : Envelope;
+end
+endmodule
+
+
+
+module TriangleChan(input clk, input ce, input reset,
+ input [1:0] Addr,
+ input [7:0] DIN,
+ input MW,
+ input LenCtr_Clock,
+ input LinCtr_Clock,
+ input Enabled,
+ input [7:0] LenCtr_In,
+ output [3:0] Sample,
+ output IsNonZero);
+ //
+ reg [10:0] Period, TimerCtr;
+ reg [4:0] SeqPos;
+ //
+ // Linear counter state
+ reg [6:0] LinCtrPeriod, LinCtr;
+ reg LinCtrl, LinHalt;
+ wire LinCtrZero = (LinCtr == 0);
+ //
+ // Length counter state
+ reg [7:0] LenCtr;
+ wire LenCtrHalt = LinCtrl; // Aliased bit
+ wire LenCtrZero = (LenCtr == 0);
+ assign IsNonZero = !LenCtrZero;
+ //
+ always @(posedge clk) if (reset) begin
+ Period <= 0;
+ TimerCtr <= 0;
+ SeqPos <= 0;
+ LinCtrPeriod <= 0;
+ LinCtr <= 0;
+ LinCtrl <= 0;
+ LinHalt <= 0;
+ LenCtr <= 0;
+ end else if (ce) begin
+ // Check if writing to the regs of this channel
+ if (MW) begin
+ case (Addr)
+ 0: begin
+ LinCtrl <= DIN[7];
+ LinCtrPeriod <= DIN[6:0];
+ end
+ 2: begin
+ Period[7:0] <= DIN;
+ end
+ 3: begin
+ Period[10:8] <= DIN[2:0];
+ LenCtr <= LenCtr_In;
+ LinHalt <= 1;
+ end
+ endcase
+ end
+
+ // Count down the period timer...
+ if (TimerCtr == 0) begin
+ TimerCtr <= Period;
+ end else begin
+ TimerCtr <= TimerCtr - 1;
+ end
+ //
+ // Clock the length counter?
+ if (LenCtr_Clock && !LenCtrZero && !LenCtrHalt) begin
+ LenCtr <= LenCtr - 1;
+ end
+ //
+ // Clock the linear counter?
+ if (LinCtr_Clock) begin
+ if (LinHalt)
+ LinCtr <= LinCtrPeriod;
+ else if (!LinCtrZero)
+ LinCtr <= LinCtr - 1;
+ if (!LinCtrl)
+ LinHalt <= 0;
+ end
+ //
+ // Length counter forced to zero if disabled.
+ if (!Enabled)
+ LenCtr <= 0;
+ //
+ // Clock the sequencer position
+ if (TimerCtr == 0 && !LenCtrZero && !LinCtrZero)
+ SeqPos <= SeqPos + 1;
+ end
+ // Generate the output
+ assign Sample = SeqPos[3:0] ^ {4{~SeqPos[4]}};
+ //
+endmodule
+
+
+module NoiseChan(input clk, input ce, input reset,
+ input [1:0] Addr,
+ input [7:0] DIN,
+ input MW,
+ input LenCtr_Clock,
+ input Env_Clock,
+ input Enabled,
+ input [7:0] LenCtr_In,
+ output [3:0] Sample,
+ output IsNonZero);
+ //
+ // Envelope volume
+ reg EnvLoop, EnvDisable, EnvDoReset;
+ reg [3:0] Volume, Envelope, EnvDivider;
+ // Length counter
+ wire LenCtrHalt = EnvLoop; // Aliased bit
+ reg [7:0] LenCtr;
+ //
+ reg ShortMode;
+ reg [14:0] Shift = 1;
+
+ assign IsNonZero = (LenCtr != 0);
+ //
+ // Period stuff
+ reg [3:0] Period;
+ reg [11:0] NoisePeriod, TimerCtr;
+ always @* begin
+ case (Period)
+ 0: NoisePeriod = 12'h004;
+ 1: NoisePeriod = 12'h008;
+ 2: NoisePeriod = 12'h010;
+ 3: NoisePeriod = 12'h020;
+ 4: NoisePeriod = 12'h040;
+ 5: NoisePeriod = 12'h060;
+ 6: NoisePeriod = 12'h080;
+ 7: NoisePeriod = 12'h0A0;
+ 8: NoisePeriod = 12'h0CA;
+ 9: NoisePeriod = 12'h0FE;
+ 10: NoisePeriod = 12'h17C;
+ 11: NoisePeriod = 12'h1FC;
+ 12: NoisePeriod = 12'h2FA;
+ 13: NoisePeriod = 12'h3F8;
+ 14: NoisePeriod = 12'h7F2;
+ 15: NoisePeriod = 12'hFE4;
+ endcase
+ end
+ //
+ always @(posedge clk) if (reset) begin
+ EnvLoop <= 0;
+ EnvDisable <= 0;
+ EnvDoReset <= 0;
+ Volume <= 0;
+ Envelope <= 0;
+ EnvDivider <= 0;
+ LenCtr <= 0;
+ ShortMode <= 0;
+ Shift <= 1;
+ Period <= 0;
+ TimerCtr <= 0;
+ end else if (ce) begin
+ // Check if writing to the regs of this channel
+ if (MW) begin
+ case (Addr)
+ 0: begin
+ EnvLoop <= DIN[5];
+ EnvDisable <= DIN[4];
+ Volume <= DIN[3:0];
+ end
+ 2: begin
+ ShortMode <= DIN[7];
+ Period <= DIN[3:0];
+ end
+ 3: begin
+ LenCtr <= LenCtr_In;
+ EnvDoReset <= 1;
+ end
+ endcase
+ end
+ // Count down the period timer...
+ if (TimerCtr == 0) begin
+ TimerCtr <= NoisePeriod;
+ // Clock the shift register. Use either
+ // bit 1 or 6 as the tap.
+ Shift <= {
+ Shift[0] ^ (ShortMode ? Shift[6] : Shift[1]),
+ Shift[14:1]};
+ end else begin
+ TimerCtr <= TimerCtr - 1;
+ end
+ // Clock the length counter?
+ if (LenCtr_Clock && LenCtr != 0 && !LenCtrHalt) begin
+ LenCtr <= LenCtr - 1;
+ end
+ // Clock the envelope generator?
+ if (Env_Clock) begin
+ if (EnvDoReset) begin
+ EnvDivider <= Volume;
+ Envelope <= 15;
+ EnvDoReset <= 0;
+ end else if (EnvDivider == 0) begin
+ EnvDivider <= Volume;
+ if (Envelope != 0)
+ Envelope <= Envelope - 1;
+ else if (EnvLoop)
+ Envelope <= 15;
+ end else
+ EnvDivider <= EnvDivider - 1;
+ end
+ if (!Enabled)
+ LenCtr <= 0;
+ end
+ // Produce the output signal
+ assign Sample =
+ (LenCtr == 0 || Shift[0]) ?
+ 0 :
+ (EnvDisable ? Volume : Envelope);
+endmodule
+
+module DmcChan(input clk, input ce, input reset,
+ input odd_or_even,
+ input [2:0] Addr,
+ input [7:0] DIN,
+ input MW,
+ output [6:0] Sample,
+ output DmaReq, // 1 when DMC wants DMA
+ input DmaAck, // 1 when DMC byte is on DmcData. DmcDmaRequested should go low.
+ output [15:0] DmaAddr, // Address DMC wants to read
+ input [7:0] DmaData, // Input data to DMC from memory.
+ output Irq,
+ output IsDmcActive);
+ reg IrqEnable;
+ reg IrqActive;
+ reg Loop; // Looping enabled
+ reg [3:0] Freq; // Current value of frequency register
+ reg [6:0] Dac = 0; // Current value of DAC
+ reg [7:0] SampleAddress; // Base address of sample
+ reg [7:0] SampleLen; // Length of sample
+ reg [7:0] ShiftReg; // Shift register
+ reg [8:0] Cycles; // Down counter, is the period
+ reg [14:0] Address; // 15 bits current address, 0x8000-0xffff
+ reg [11:0] BytesLeft; // 12 bits bytes left counter 0 - 4081.
+ reg [2:0] BitsUsed; // Number of bits left in the SampleBuffer.
+ reg [7:0] SampleBuffer; // Next value to be loaded into shift reg
+ reg HasSampleBuffer; // Sample buffer is nonempty
+ reg HasShiftReg; // Shift reg is non empty
+ reg [8:0] NewPeriod[0:15];
+ reg DmcEnabled;
+ reg [1:0] ActivationDelay;
+ assign DmaAddr = {1'b1, Address};
+ assign Sample = Dac;
+ assign Irq = IrqActive;
+ assign IsDmcActive = DmcEnabled;
+
+ assign DmaReq = !HasSampleBuffer && DmcEnabled && !ActivationDelay[0];
+
+ initial begin
+ NewPeriod[0] = 428;
+ NewPeriod[1] = 380;
+ NewPeriod[2] = 340;
+ NewPeriod[3] = 320;
+ NewPeriod[4] = 286;
+ NewPeriod[5] = 254;
+ NewPeriod[6] = 226;
+ NewPeriod[7] = 214;
+ NewPeriod[8] = 190;
+ NewPeriod[9] = 160;
+ NewPeriod[10] = 142;
+ NewPeriod[11] = 128;
+ NewPeriod[12] = 106;
+ NewPeriod[13] = 84;
+ NewPeriod[14] = 72;
+ NewPeriod[15] = 54;
+ end
+ // Shift register initially loaded with 07
+ always @(posedge clk) begin
+ if (reset) begin
+ IrqEnable <= 0;
+ IrqActive <= 0;
+ Loop <= 0;
+ Freq <= 0;
+ Dac <= 0;
+ SampleAddress <= 0;
+ SampleLen <= 0;
+ ShiftReg <= 8'hff;
+ Cycles <= 439;
+ Address <= 0;
+ BytesLeft <= 0;
+ BitsUsed <= 0;
+ SampleBuffer <= 0;
+ HasSampleBuffer <= 0;
+ HasShiftReg <= 0;
+ DmcEnabled <= 0;
+ ActivationDelay <= 0;
+ end else if (ce) begin
+ if (ActivationDelay == 3 && !odd_or_even) ActivationDelay <= 1;
+ if (ActivationDelay == 1) ActivationDelay <= 0;
+
+ if (MW) begin
+ case (Addr)
+ 0: begin // $4010 il-- ffff IRQ enable, loop, frequency index
+ IrqEnable <= DIN[7];
+ Loop <= DIN[6];
+ Freq <= DIN[3:0];
+ if (!DIN[7]) IrqActive <= 0;
+ end
+ 1: begin // $4011 -ddd dddd DAC
+ // This will get missed if the Dac <= far below runs, that is by design.
+ Dac <= DIN[6:0];
+ end
+ 2: begin // $4012 aaaa aaaa sample address
+ SampleAddress <= DIN[7:0];
+ end
+ 3: begin // $4013 llll llll sample length
+ SampleLen <= DIN[7:0];
+ end
+ 5: begin // $4015 write ---D NT21 Enable DMC (D)
+ IrqActive <= 0;
+ DmcEnabled <= DIN[4];
+ // If the DMC bit is set, the DMC sample will be restarted only if not already active.
+ if (DIN[4] && !DmcEnabled) begin
+ Address <= {1'b1, SampleAddress, 6'b000000};
+ BytesLeft <= {SampleLen, 4'b0000};
+ ActivationDelay <= 3;
+ end
+ end
+ endcase
+ end
+
+ Cycles <= Cycles - 1;
+ if (Cycles == 1) begin
+ Cycles <= NewPeriod[Freq];
+ if (HasShiftReg) begin
+ if (ShiftReg[0]) begin
+ Dac[6:1] <= (Dac[6:1] != 6'b111111) ? Dac[6:1] + 6'b000001 : Dac[6:1];
+ end else begin
+ Dac[6:1] <= (Dac[6:1] != 6'b000000) ? Dac[6:1] + 6'b111111 : Dac[6:1];
+ end
+ end
+ ShiftReg <= {1'b0, ShiftReg[7:1]};
+ BitsUsed <= BitsUsed + 1;
+ if (BitsUsed == 7) begin
+ HasShiftReg <= HasSampleBuffer;
+ ShiftReg <= SampleBuffer;
+ HasSampleBuffer <= 0;
+ end
+ end
+
+ // Acknowledge DMA?
+ if (DmaAck) begin
+ Address <= Address + 1;
+ BytesLeft <= BytesLeft - 1;
+ HasSampleBuffer <= 1;
+ SampleBuffer <= DmaData;
+ if (BytesLeft == 0) begin
+ Address <= {1'b1, SampleAddress, 6'b000000};
+ BytesLeft <= {SampleLen, 4'b0000};
+ DmcEnabled <= Loop;
+ if (!Loop && IrqEnable)
+ IrqActive <= 1;
+ end
+ end
+ end
+ end
+endmodule
+
+module ApuLookupTable(input clk, input [7:0] in_a, input [7:0] in_b, output [15:0] out);
+ reg [15:0] lookup[0:511];
+ reg [15:0] tmp_a, tmp_b;
+ initial begin
+ lookup[ 0] = 0; lookup[ 1] = 760; lookup[ 2] = 1503; lookup[ 3] = 2228;
+ lookup[ 4] = 2936; lookup[ 5] = 3627; lookup[ 6] = 4303; lookup[ 7] = 4963;
+ lookup[ 8] = 5609; lookup[ 9] = 6240; lookup[ 10] = 6858; lookup[ 11] = 7462;
+ lookup[ 12] = 8053; lookup[ 13] = 8631; lookup[ 14] = 9198; lookup[ 15] = 9752;
+ lookup[ 16] = 10296; lookup[ 17] = 10828; lookup[ 18] = 11349; lookup[ 19] = 11860;
+ lookup[ 20] = 12361; lookup[ 21] = 12852; lookup[ 22] = 13334; lookup[ 23] = 13807;
+ lookup[ 24] = 14270; lookup[ 25] = 14725; lookup[ 26] = 15171; lookup[ 27] = 15609;
+ lookup[ 28] = 16039; lookup[ 29] = 16461; lookup[ 30] = 16876; lookup[256] = 0;
+ lookup[257] = 439; lookup[258] = 874; lookup[259] = 1306; lookup[260] = 1735;
+ lookup[261] = 2160; lookup[262] = 2581; lookup[263] = 2999; lookup[264] = 3414;
+ lookup[265] = 3826; lookup[266] = 4234; lookup[267] = 4639; lookup[268] = 5041;
+ lookup[269] = 5440; lookup[270] = 5836; lookup[271] = 6229; lookup[272] = 6618;
+ lookup[273] = 7005; lookup[274] = 7389; lookup[275] = 7769; lookup[276] = 8147;
+ lookup[277] = 8522; lookup[278] = 8895; lookup[279] = 9264; lookup[280] = 9631;
+ lookup[281] = 9995; lookup[282] = 10356; lookup[283] = 10714; lookup[284] = 11070;
+ lookup[285] = 11423; lookup[286] = 11774; lookup[287] = 12122; lookup[288] = 12468;
+ lookup[289] = 12811; lookup[290] = 13152; lookup[291] = 13490; lookup[292] = 13825;
+ lookup[293] = 14159; lookup[294] = 14490; lookup[295] = 14818; lookup[296] = 15145;
+ lookup[297] = 15469; lookup[298] = 15791; lookup[299] = 16110; lookup[300] = 16427;
+ lookup[301] = 16742; lookup[302] = 17055; lookup[303] = 17366; lookup[304] = 17675;
+ lookup[305] = 17981; lookup[306] = 18286; lookup[307] = 18588; lookup[308] = 18888;
+ lookup[309] = 19187; lookup[310] = 19483; lookup[311] = 19777; lookup[312] = 20069;
+ lookup[313] = 20360; lookup[314] = 20648; lookup[315] = 20935; lookup[316] = 21219;
+ lookup[317] = 21502; lookup[318] = 21783; lookup[319] = 22062; lookup[320] = 22339;
+ lookup[321] = 22615; lookup[322] = 22889; lookup[323] = 23160; lookup[324] = 23431;
+ lookup[325] = 23699; lookup[326] = 23966; lookup[327] = 24231; lookup[328] = 24494;
+ lookup[329] = 24756; lookup[330] = 25016; lookup[331] = 25274; lookup[332] = 25531;
+ lookup[333] = 25786; lookup[334] = 26040; lookup[335] = 26292; lookup[336] = 26542;
+ lookup[337] = 26791; lookup[338] = 27039; lookup[339] = 27284; lookup[340] = 27529;
+ lookup[341] = 27772; lookup[342] = 28013; lookup[343] = 28253; lookup[344] = 28492;
+ lookup[345] = 28729; lookup[346] = 28964; lookup[347] = 29198; lookup[348] = 29431;
+ lookup[349] = 29663; lookup[350] = 29893; lookup[351] = 30121; lookup[352] = 30349;
+ lookup[353] = 30575; lookup[354] = 30800; lookup[355] = 31023; lookup[356] = 31245;
+ lookup[357] = 31466; lookup[358] = 31685; lookup[359] = 31904; lookup[360] = 32121;
+ lookup[361] = 32336; lookup[362] = 32551; lookup[363] = 32764; lookup[364] = 32976;
+ lookup[365] = 33187; lookup[366] = 33397; lookup[367] = 33605; lookup[368] = 33813;
+ lookup[369] = 34019; lookup[370] = 34224; lookup[371] = 34428; lookup[372] = 34630;
+ lookup[373] = 34832; lookup[374] = 35032; lookup[375] = 35232; lookup[376] = 35430;
+ lookup[377] = 35627; lookup[378] = 35823; lookup[379] = 36018; lookup[380] = 36212;
+ lookup[381] = 36405; lookup[382] = 36597; lookup[383] = 36788; lookup[384] = 36978;
+ lookup[385] = 37166; lookup[386] = 37354; lookup[387] = 37541; lookup[388] = 37727;
+ lookup[389] = 37912; lookup[390] = 38095; lookup[391] = 38278; lookup[392] = 38460;
+ lookup[393] = 38641; lookup[394] = 38821; lookup[395] = 39000; lookup[396] = 39178;
+ lookup[397] = 39355; lookup[398] = 39532; lookup[399] = 39707; lookup[400] = 39881;
+ lookup[401] = 40055; lookup[402] = 40228; lookup[403] = 40399; lookup[404] = 40570;
+ lookup[405] = 40740; lookup[406] = 40909; lookup[407] = 41078; lookup[408] = 41245;
+ lookup[409] = 41412; lookup[410] = 41577; lookup[411] = 41742; lookup[412] = 41906;
+ lookup[413] = 42070; lookup[414] = 42232; lookup[415] = 42394; lookup[416] = 42555;
+ lookup[417] = 42715; lookup[418] = 42874; lookup[419] = 43032; lookup[420] = 43190;
+ lookup[421] = 43347; lookup[422] = 43503; lookup[423] = 43659; lookup[424] = 43813;
+ lookup[425] = 43967; lookup[426] = 44120; lookup[427] = 44273; lookup[428] = 44424;
+ lookup[429] = 44575; lookup[430] = 44726; lookup[431] = 44875; lookup[432] = 45024;
+ lookup[433] = 45172; lookup[434] = 45319; lookup[435] = 45466; lookup[436] = 45612;
+ lookup[437] = 45757; lookup[438] = 45902; lookup[439] = 46046; lookup[440] = 46189;
+ lookup[441] = 46332; lookup[442] = 46474; lookup[443] = 46615; lookup[444] = 46756;
+ lookup[445] = 46895; lookup[446] = 47035; lookup[447] = 47173; lookup[448] = 47312;
+ lookup[449] = 47449; lookup[450] = 47586; lookup[451] = 47722; lookup[452] = 47857;
+ lookup[453] = 47992; lookup[454] = 48127; lookup[455] = 48260; lookup[456] = 48393;
+ lookup[457] = 48526; lookup[458] = 48658;
+ end
+ always @(posedge clk) begin
+ tmp_a <= lookup[{1'b0, in_a}];
+ tmp_b <= lookup[{1'b1, in_b}];
+ end
+ assign out = tmp_a + tmp_b;
+endmodule
+
+
+module APU(input clk, input ce, input reset,
+ input [4:0] ADDR, // APU Address Line
+ input [7:0] DIN, // Data to APU
+ output [7:0] DOUT, // Data from APU
+ input MW, // Writes to APU
+ input MR, // Reads from APU
+ input [4:0] audio_channels, // Enabled audio channels
+ output [15:0] Sample,
+
+ output DmaReq, // 1 when DMC wants DMA
+ input DmaAck, // 1 when DMC byte is on DmcData. DmcDmaRequested should go low.
+ output [15:0] DmaAddr, // Address DMC wants to read
+ input [7:0] DmaData, // Input data to DMC from memory.
+
+ output odd_or_even,
+ output IRQ); // IRQ asserted
+
+// Which channels are enabled?
+reg [3:0] Enabled;
+
+// Output samples from the 4 channels
+wire [3:0] Sq1Sample,Sq2Sample,TriSample,NoiSample;
+
+// Output samples from the DMC channel
+wire [6:0] DmcSample;
+wire DmcIrq;
+wire IsDmcActive;
+
+// Generate internal memory write signals
+wire ApuMW0 = MW && ADDR[4:2]==0; // SQ1
+wire ApuMW1 = MW && ADDR[4:2]==1; // SQ2
+wire ApuMW2 = MW && ADDR[4:2]==2; // TRI
+wire ApuMW3 = MW && ADDR[4:2]==3; // NOI
+wire ApuMW4 = MW && ADDR[4:2]>=4; // DMC
+wire ApuMW5 = MW && ADDR[4:2]==5; // Control registers
+
+wire Sq1NonZero, Sq2NonZero, TriNonZero, NoiNonZero;
+
+// Common input to all channels
+wire [7:0] LenCtr_In;
+LenCtr_Lookup len(DIN[7:3], LenCtr_In);
+
+
+// Frame sequencer registers
+reg FrameSeqMode;
+reg [15:0] Cycles;
+reg ClkE, ClkL;
+reg Wrote4017;
+reg [1:0] IrqCtr;
+reg InternalClock; // APU Differentiates between Even or Odd clocks
+assign odd_or_even = InternalClock;
+
+
+// Generate each channel
+SquareChan Sq1(clk, ce, reset, 0, ADDR[1:0], DIN, ApuMW0, ClkL, ClkE, Enabled[0], LenCtr_In, Sq1Sample, Sq1NonZero);
+SquareChan Sq2(clk, ce, reset, 1, ADDR[1:0], DIN, ApuMW1, ClkL, ClkE, Enabled[1], LenCtr_In, Sq2Sample, Sq2NonZero);
+TriangleChan Tri(clk, ce, reset, ADDR[1:0], DIN, ApuMW2, ClkL, ClkE, Enabled[2], LenCtr_In, TriSample, TriNonZero);
+NoiseChan Noi(clk, ce, reset, ADDR[1:0], DIN, ApuMW3, ClkL, ClkE, Enabled[3], LenCtr_In, NoiSample, NoiNonZero);
+DmcChan Dmc(clk, ce, reset, odd_or_even, ADDR[2:0], DIN, ApuMW4, DmcSample, DmaReq, DmaAck, DmaAddr, DmaData, DmcIrq, IsDmcActive);
+
+// Reading this register clears the frame interrupt flag (but not the DMC interrupt flag).
+// If an interrupt flag was set at the same moment of the read, it will read back as 1 but it will not be cleared.
+reg FrameInterrupt, DisableFrameInterrupt;
+
+
+//mode 0: 4-step effective rate (approx)
+//---------------------------------------
+// - - - f 60 Hz
+// - l - l 120 Hz
+// e e e e 240 Hz
+
+
+//mode 1: 5-step effective rate (approx)
+//---------------------------------------
+// - - - - - (interrupt flag never set)
+// l - l - - 96 Hz
+// e e e e - 192 Hz
+
+
+always @(posedge clk) if (reset) begin
+ FrameSeqMode <= 0;
+ DisableFrameInterrupt <= 0;
+ FrameInterrupt <= 0;
+ Enabled <= 0;
+ InternalClock <= 0;
+ Wrote4017 <= 0;
+ ClkE <= 0;
+ ClkL <= 0;
+ Cycles <= 4; // This needs to be 5 for proper power up behavior
+ IrqCtr <= 0;
+end else if (ce) begin
+ FrameInterrupt <= IrqCtr[1] ? 1 : (ADDR == 5'h15 && MR || ApuMW5 && ADDR[1:0] == 3 && DIN[6]) ? 0 : FrameInterrupt;
+ InternalClock <= !InternalClock;
+ IrqCtr <= {IrqCtr[0], 1'b0};
+ Cycles <= Cycles + 1;
+ ClkE <= 0;
+ ClkL <= 0;
+ if (Cycles == 7457) begin
+ ClkE <= 1;
+ end else if (Cycles == 14913) begin
+ ClkE <= 1;
+ ClkL <= 1;
+ ClkE <= 1;
+ ClkL <= 1;
+ end else if (Cycles == 22371) begin
+ ClkE <= 1;
+ end else if (Cycles == 29829) begin
+ if (!FrameSeqMode) begin
+ ClkE <= 1;
+ ClkL <= 1;
+ Cycles <= 0;
+ IrqCtr <= 3;
+ FrameInterrupt <= 1;
+ end
+ end else if (Cycles == 37281) begin
+ ClkE <= 1;
+ ClkL <= 1;
+ Cycles <= 0;
+ end
+
+ // Handle one cycle delayed write to 4017.
+ Wrote4017 <= 0;
+ if (Wrote4017) begin
+ if (FrameSeqMode) begin
+ ClkE <= 1;
+ ClkL <= 1;
+ end
+ Cycles <= 0;
+ end
+
+// if (ClkE||ClkL) $write("%d: Clocking %s%s\n", Cycles, ClkE?"E":" ", ClkL?"L":" ");
+
+ // Handle writes to control registers
+ if (ApuMW5) begin
+ case (ADDR[1:0])
+ 1: begin // Register $4015
+ Enabled <= DIN[3:0];
+// $write("$4015 = %X\n", DIN);
+ end
+ 3: begin // Register $4017
+ FrameSeqMode <= DIN[7]; // 1 = 5 frames cycle, 0 = 4 frames cycle
+ DisableFrameInterrupt <= DIN[6];
+
+ // If the internal clock is even, things happen
+ // right away.
+ if (!InternalClock) begin
+ if (DIN[7]) begin
+ ClkE <= 1;
+ ClkL <= 1;
+ end
+ Cycles <= 0;
+ end
+
+ // Otherwise they get delayed one clock
+ Wrote4017 <= InternalClock;
+ end
+ endcase
+ end
+
+
+end
+
+ApuLookupTable lookup(clk,
+ (audio_channels[0] ? {4'b0, Sq1Sample} : 8'b0) +
+ (audio_channels[1] ? {4'b0, Sq2Sample} : 8'b0),
+ (audio_channels[2] ? {4'b0, TriSample} + {3'b0, TriSample, 1'b0} : 8'b0) +
+ (audio_channels[3] ? {3'b0, NoiSample, 1'b0} : 8'b0) +
+ (audio_channels[4] ? {1'b0, DmcSample} : 8'b0),
+ Sample);
+
+wire frame_irq = FrameInterrupt && !DisableFrameInterrupt;
+
+// Generate bus output
+assign DOUT = {DmcIrq, frame_irq, 1'b0,
+ IsDmcActive,
+ NoiNonZero,
+ TriNonZero,
+ Sq2NonZero,
+ Sq1NonZero};
+
+assign IRQ = frame_irq || DmcIrq;
+
+endmodule
diff --git a/openlane/designs/BM64/config.tcl b/openlane/designs/BM64/config.tcl
new file mode 100755
index 0000000..9fdfe65
--- /dev/null
+++ b/openlane/designs/BM64/config.tcl
@@ -0,0 +1,20 @@
+# Design
+
+# User config
+set ::env(DESIGN_NAME) BM64
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+# Fill this
+set ::env(CLOCK_PORT) "Clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+# design has a lot of pins, needs an absolute size
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) {0 0 1000 1000}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/BM64/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/BM64/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..77a5f0b
--- /dev/null
+++ b/openlane/designs/BM64/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20.0"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 18
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/BM64/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/BM64/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..c895327
--- /dev/null
+++ b/openlane/designs/BM64/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "20.0"
+set ::env(FP_CORE_UTIL) 18
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/BM64/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/BM64/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..c895327
--- /dev/null
+++ b/openlane/designs/BM64/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "20.0"
+set ::env(FP_CORE_UTIL) 18
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/BM64/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/BM64/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..c895327
--- /dev/null
+++ b/openlane/designs/BM64/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "20.0"
+set ::env(FP_CORE_UTIL) 18
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/BM64/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/BM64/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..c895327
--- /dev/null
+++ b/openlane/designs/BM64/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "20.0"
+set ::env(FP_CORE_UTIL) 18
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/BM64/src/BM64.v b/openlane/designs/BM64/src/BM64.v
new file mode 100644
index 0000000..5e2cd26
--- /dev/null
+++ b/openlane/designs/BM64/src/BM64.v
@@ -0,0 +1,543 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
+//
+// All rights reserved. The source code contained herein is publicly released
+// under the terms and conditions of the GNU Lesser Public License. No part of
+// this source code may be reproduced or transmitted in any form or by any
+// means, electronic or mechanical, including photocopying, recording, or any
+// information storage and retrieval system in violation of the license under
+// which the source code is released.
+//
+// The souce code contained herein is free; it may be redistributed and/or
+// modified in accordance with the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either version 2.1 of
+// the GNU Lesser General Public License, or any later version.
+//
+// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
+// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
+// more details.)
+//
+// A copy of the GNU Lesser General Public License should have been received
+// along with the source code contained herein; if not, a copy can be obtained
+// by writing to:
+//
+// Free Software Foundation, Inc.
+// 51 Franklin Street, Fifth Floor
+// Boston, MA 02110-1301 USA
+//
+// Further, no use of this source code is permitted in any form or means
+// without inclusion of this banner prominently in any derived works.
+//
+// Michael A. Morris
+// Huntsville, AL
+//
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: M. A. Morris & Associates
+// Engineer: Michael A. Morris
+//
+// Create Date: 12:59:58 10/02/2010
+// Design Name: Fast 4-bit Booth Multiplier
+// Module Name: Booth_Multiplier_4xA.v
+// Project Name: Booth_Multiplier
+// Target Devices: Spartan-3AN
+// Tool versions: Xilinx ISE 10.1 SP3
+//
+// Description:
+//
+// This module implements a parameterized multiplier which uses a Modified
+// Booth algorithm for its implementation. The implementation is based on the
+// algorithm described in "Computer Organization", Hamacher et al, McGraw-
+// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
+//
+// Compared to the standard, 1-bit at a time Booth algorithm, this modified
+// Booth multiplier algorithm shifts the multiplier 4 bits at a time. Thus,
+// this algorithm will compute a 2's complement product four times as fast as
+// the base algorithm.
+//
+// This particular module attempts to optimize the synthesis and implementation
+// results relative to those of the Booth_Multiplier_4x.v module. Examination
+// of the synthesis results of that module indicate that 16 20-bit adders and
+// 16 20-bit subtractors are needed to implement the partial products. This
+// module uses a different approach to eliminate the large number of adders
+// and subtractors such that only two cascaded adders are required; When sub-
+// traction is required, complementing the input and adding a carry into the
+// sum is how the subtractions are implemented. 32:1 multiplexers are used to
+// evaluated the Booth recoding value and determine the value and operation to
+// be performed by the two cascaded adders.
+//
+// Dependencies:
+//
+// Revision:
+//
+// 0.01 10J02 MAM File Created
+//
+// 1.0 12I02 MAM Changed the implementation of the base module to
+// reduced the number of inferred adders and reduce
+// the number of multiplexers required.
+//
+// Additional Comments:
+//
+// The basic operations follow those of the standard Booth multiplier except
+// that the transitions are being tracked across 4 bits plus the guard bit.
+// The result is that the operations required are 0, �1, �2, �3, �4, �5, �6,
+// �7, and �8 times the multiplicand (M). However, it is possible to reduce
+// the number of partial products required to implement the multiplication to
+// two. That is, �3, �5, �6, and �7 can be written in terms of combinations of
+// �1, �2, �4, and �8. For example, 3M = (2M + 1M), 5M = (4M + M), 6M = (4M
+// + 2M), and 7M = (8M - M). Thus, the following 32 entry table defines the
+// operations required for generating the partial products through each pass
+// of the algorithm over the multiplier:
+//
+// Prod[4:0] Operation
+// 00000 Prod <= (Prod + 0*M + 0*M) >> 4;
+// 00001 Prod <= (Prod + 0*M + 1*M) >> 4;
+// 00010 Prod <= (Prod + 0*M + 1*M) >> 4;
+// 00011 Prod <= (Prod + 2*M + 0*M) >> 4;
+// 00100 Prod <= (Prod + 2*M + 0*M) >> 4;
+// 00101 Prod <= (Prod + 2*M + 1*M) >> 4;
+// 00110 Prod <= (Prod + 2*M + 1*M) >> 4;
+// 00111 Prod <= (Prod + 4*M + 0*M) >> 4;
+// 01000 Prod <= (Prod + 4*M + 0*M) >> 4;
+// 01001 Prod <= (Prod + 4*M + 1*M) >> 4;
+// 01010 Prod <= (Prod + 4*M + 1*M) >> 4;
+// 01011 Prod <= (Prod + 4*M + 2*M) >> 4;
+// 01100 Prod <= (Prod + 4*M + 2*M) >> 4;
+// 01101 Prod <= (Prod + 8*M - 1*M) >> 4;
+// 01110 Prod <= (Prod + 8*M - 1*M) >> 4;
+// 01111 Prod <= (Prod + 8*M + 0*M) >> 4;
+// 10000 Prod <= (Prod - 8*M - 0*M) >> 4;
+// 10001 Prod <= (Prod - 8*M + 1*M) >> 4;
+// 10010 Prod <= (Prod - 8*M + 1*M) >> 4;
+// 10011 Prod <= (Prod - 4*M - 2*M) >> 4;
+// 10100 Prod <= (Prod - 4*M - 2*M) >> 4;
+// 10101 Prod <= (Prod - 4*M - 1*M) >> 4;
+// 10110 Prod <= (Prod - 4*M - 1*M) >> 4;
+// 10111 Prod <= (Prod - 4*M - 0*M) >> 4;
+// 11000 Prod <= (Prod - 4*M - 0*M) >> 4;
+// 11001 Prod <= (Prod - 2*M - 1*M) >> 4;
+// 11010 Prod <= (Prod - 2*M - 1*M) >> 4;
+// 11011 Prod <= (Prod - 2*M - 0*M) >> 4;
+// 11100 Prod <= (Prod - 2*M - 0*M) >> 4;
+// 11101 Prod <= (Prod - 0*M - 1*M) >> 4;
+// 11110 Prod <= (Prod - 0*M - 1*M) >> 4;
+// 11111 Prod <= (Prod - 0*M - 0*M) >> 4;
+//
+// One approach to implementing the recoding table is to use a 32:1 multiplexer
+// and simply write out the necessary operations. This is the approach used in
+// the first version of the 4 bits at a time Booth multiplier. The problem is
+// that the implementation of the preceding recoding table in a first prin-
+// ciples manner results in a large number of adders and subtractors being
+// synthesized. Apparently, the structure and character of the RTL code is such
+// that the synthesizer is unable to use multiplexers to determine the operands
+// of the two adders which are required.
+//
+// Examining the previous recoding table shows that seven multiples of the
+// multiplicand (M) are represented in the first multiplicand column, 0x, �2x,
+// �4x, and �8x, and five are represented in the second multiplicand column,
+// 0x, �1x, and �2. The synthesizer is able to identify the need for adders and
+// subractors, but is unable to morph the structure from one embedded in a 32:1
+// multiplexer into one where an 8:1 multiplexer feeds the first multiplicand
+// products into one adder, and another 8:1 multiplexer feeds the second multi-
+// plicand product into another adder cascaded with the first.
+//
+// A review of the corresponding synthesis report shows that the synthesizer
+// extracted 8 adders and 8 subtractors. Refering to the 32 line recoding table
+// above, shows that there are 8 diffent combinations of the multiplicand pro-
+// ducts that must be added/subtracted to the partial product, Prod, to deter-
+// mine the final product. The resulting implementation is correct, as deter-
+// mined by its testbench, but the implementation certainly uses more resources
+// than would be expected when increasing the number of bits processed per
+// stage/iteration from 2 to 4. A natural assumption is that the resources uti-
+// lized would increase by a factor close to 2 as the number of bits processed
+// is increased by powers of 2: 1, 2, 4, etc.
+//
+// It is now clear that the synthesizer is unable to transform the multiplexed
+// adder structure inherent in the current specification into a structure which
+// is composed of multiplexers followed by two cascaded adders. Therefore, that
+// simpler structure must be explcitly specified in this module's RTL. In order
+// to minimize the multiplexers, the recoding table needs to be modified from
+// its current definition to an equivalent definition that can be implemented
+// using just two multiplicand products. The following recoding table can be
+// compared to the one above to see the adjustments made. In essence, the first
+// multiplicand column allows only five multiplicand product values, 0M, �4M,
+// and �8M, and the second multiplicand column also allows only five values,
+// 0M, �1M, and �2M.
+//
+// Prod[4:0] Operation
+// 00000 Prod <= (Prod + 0*M + 0*M) >> 4;
+// 00001 Prod <= (Prod + 0*M + 1*M) >> 4;
+// 00010 Prod <= (Prod + 0*M + 1*M) >> 4;
+// 00011 Prod <= (Prod + 0*M + 2*M) >> 4;
+// 00100 Prod <= (Prod + 0*M + 2*M) >> 4;
+// 00101 Prod <= (Prod + 4*M - 1*M) >> 4;
+// 00110 Prod <= (Prod + 4*M - 1*M) >> 4;
+// 00111 Prod <= (Prod + 4*M + 0*M) >> 4;
+// 01000 Prod <= (Prod + 4*M + 0*M) >> 4;
+// 01001 Prod <= (Prod + 4*M + 1*M) >> 4;
+// 01010 Prod <= (Prod + 4*M + 1*M) >> 4;
+// 01011 Prod <= (Prod + 4*M + 2*M) >> 4;
+// 01100 Prod <= (Prod + 4*M + 2*M) >> 4;
+// 01101 Prod <= (Prod + 8*M - 1*M) >> 4
+// 01110 Prod <= (Prod + 8*M - 1*M) >> 4;
+// 01111 Prod <= (Prod + 8*M + 0*M) >> 4;
+// 10000 Prod <= (Prod - 8*M - 0*M) >> 4;
+// 10001 Prod <= (Prod - 8*M + 1*M) >> 4;
+// 10010 Prod <= (Prod - 8*M + 1*M) >> 4;
+// 10011 Prod <= (Prod - 4*M - 2*M) >> 4;
+// 10100 Prod <= (Prod - 4*M - 2*M) >> 4;
+// 10101 Prod <= (Prod - 4*M - 1*M) >> 4;
+// 10110 Prod <= (Prod - 4*M - 1*M) >> 4;
+// 10111 Prod <= (Prod - 4*M - 0*M) >> 4;
+// 11000 Prod <= (Prod - 4*M - 0*M) >> 4;
+// 11001 Prod <= (Prod - 4*M + 1*M) >> 4;
+// 11010 Prod <= (Prod - 4*M + 1*M) >> 4;
+// 11011 Prod <= (Prod - 0*M - 2*M) >> 4;
+// 11100 Prod <= (Prod - 0*M - 2*M) >> 4;
+// 11101 Prod <= (Prod - 0*M - 1*M) >> 4;
+// 11110 Prod <= (Prod - 0*M - 1*M) >> 4;
+// 11111 Prod <= (Prod - 0*M - 0*M) >> 4;
+//
+// The zero terms and the subtractions will be implemented using logic: bus AND
+// for 0, and bus XOR and carry input for subtraction, i.e. 2sC add. With this
+// additional reduction of operands, the multiplexers at the input to the adder
+// tree only multiplex two values each, {4M, 8M} or {1M, 2M}, respectively. The
+// operations required of the multiplexer and adder for each multiplicand
+// column can be defined by the triple: {PnM, M_Sel, En}. En is the control for
+// the bus AND which forms 0*M. M_Sel is the control for the multiplexer that
+// selects {4M, 8M} or {1M, 2M}, respectively. PnM is the input to the bus XOR
+// and carry input of the adder, and if 0 an addition is performed with the
+// operand at the output of the bus AND, and if 1, the adder is presented with
+// the complement of that operand plus an input carry. The bus AND can be built
+// explicitly after the multiplexer, or it can be included as the default case
+// of the multiplexer itself.
+//
+// In either case, the triples {PnM, M_Sel, En} can be constructed using a 32x6
+// ROM. The first triple refers to the control signals for the first multipli-
+// cand column and the second refers to the control signals for the second
+// multiplicand column. To force the synthesizer to infer a ROM, a fully defin-
+// ed case statement of 32 entries for each column is required:
+//
+// For the first column - B
+//
+// case(Booth)
+// 5'b00000 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
+// 5'b00001 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
+// 5'b00010 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
+// 5'b00011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
+// 5'b00100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
+// 5'b00101 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
+// 5'b00110 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
+// 5'b00111 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
+// 5'b01000 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
+// 5'b01001 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+// 5'b01010 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+// 5'b01011 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
+// 5'b01100 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
+// 5'b01101 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4
+// 5'b01110 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4;
+// 5'b01111 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M + 0*M) >> 4;
+// 5'b10000 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M - 0*M) >> 4;
+// 5'b10001 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
+// 5'b10010 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
+// 5'b10011 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
+// 5'b10100 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
+// 5'b10101 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+// 5'b10110 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+// 5'b10111 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
+// 5'b11000 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
+// 5'b11001 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
+// 5'b11010 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
+// 5'b11011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
+// 5'b11100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
+// 5'b11101 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
+// 5'b11110 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
+// 5'b11111 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+// default : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+// endcase
+//
+// For the second column - C
+//
+// case(Booth)
+// 5'b00000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
+// 5'b00001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
+// 5'b00010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
+// 5'b00011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
+// 5'b00100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
+// 5'b00101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
+// 5'b00110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
+// 5'b00111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
+// 5'b01000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
+// 5'b01001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+// 5'b01010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+// 5'b01011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
+// 5'b01100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
+// 5'b01101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4
+// 5'b01110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4;
+// 5'b01111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 8*M + 0*M) >> 4;
+// 5'b10000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 8*M - 0*M) >> 4;
+// 5'b10001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
+// 5'b10010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
+// 5'b10011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
+// 5'b10100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
+// 5'b10101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+// 5'b10110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+// 5'b10111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
+// 5'b11000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
+// 5'b11001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
+// 5'b11010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
+// 5'b11011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
+// 5'b11100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
+// 5'b11101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
+// 5'b11110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
+// 5'b11111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+// default : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+// endcase
+//
+////////////////////////////////////////////////////////////////////////////////
+
+module BM64 #(
+ parameter N = 256 // Width = N: multiplicand & multiplier
+)(
+ input Rst, // Reset
+ input Clk, // Clock
+
+ input Ld, // Load Registers and Start Multiplier
+ input [(N - 1):0] M, // Multiplicand
+ input [(N - 1):0] R, // Multiplier
+ output reg Valid, // Product Valid
+ output reg [((2*N) - 1):0] P // Product <= M * R
+);
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Local Parameters
+//
+
+localparam pNumCycles = ((N + 1)/4); // No. of cycles required for product
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Declarations
+//
+
+reg [4:0] Cntr; // Operation Counter
+reg [4:0] Booth; // Booth Recoding Field
+reg Guard; // Shift Bit for Booth Recoding
+reg [(N + 3):0] A; // Multiplicand w/ guards
+wire [(N + 3):0] Mx8, Mx4, Mx2, Mx1; // Multiplicand products w/ guards
+reg PnM_B, M_Sel_B, En_B; // Operand B Control Triple
+reg PnM_C, M_Sel_C, En_C; // Operand C Control Triple
+wire [(N + 3):0] Hi; // Upper Half of Product w/ guards
+reg [(N + 3):0] B, C; // Adder tree Operand Inputs
+reg Ci_B, Ci_C; // Adder tree Carry Inputs
+wire [(N + 3):0] T, S; // Adder Tree Outputs w/ guards
+reg [((2*N) + 3):0] Prod; // Double Length Product w/ guards
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Implementation
+//
+
+always @(posedge Clk)
+begin
+ if(Rst)
+ Cntr <= #1 0;
+ else if(Ld)
+ Cntr <= #1 pNumCycles;
+ else if(|Cntr)
+ Cntr <= #1 (Cntr - 1);
+end
+
+// Multiplicand Register
+// includes 4 bits to guard sign of multiplicand in the event the most
+// negative value is provided as the input.
+
+always @(posedge Clk)
+begin
+ if(Rst)
+ A <= #1 0;
+ else if(Ld)
+ A <= #1 {{4{M[(N - 1)]}}, M};
+end
+
+assign Mx8 = {A, 3'b0};
+assign Mx4 = {A, 2'b0};
+assign Mx2 = {A, 1'b0};
+assign Mx1 = A;
+
+// Compute Upper Partial Product: (N + 4) bits in width
+
+always @(*) Booth <= {Prod[3:0], Guard}; // Booth's Multiplier Recoding field
+
+assign Hi = Prod[((2*N) + 3):N]; // Upper Half of Product Register
+
+// Compute the Control Triples for the First and Second Multiplicand Columns
+
+// For the first column - B
+
+always @(*)
+begin
+ case(Booth)
+ 5'b00000 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
+ 5'b00001 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
+ 5'b00010 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 1*M) >> 4;
+ 5'b00011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
+ 5'b00100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod + 0*M + 2*M) >> 4;
+ 5'b00101 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
+ 5'b00110 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M - 1*M) >> 4;
+ 5'b00111 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
+ 5'b01000 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 0*M) >> 4;
+ 5'b01001 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+ 5'b01010 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+ 5'b01011 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
+ 5'b01100 : {PnM_B, M_Sel_B, En_B} <= 3'b001; // (Prod + 4*M + 2*M) >> 4;
+ 5'b01101 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4;
+ 5'b01110 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M - 1*M) >> 4;
+ 5'b01111 : {PnM_B, M_Sel_B, En_B} <= 3'b011; // (Prod + 8*M + 0*M) >> 4;
+ 5'b10000 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M - 0*M) >> 4;
+ 5'b10001 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
+ 5'b10010 : {PnM_B, M_Sel_B, En_B} <= 3'b111; // (Prod - 8*M + 1*M) >> 4;
+ 5'b10011 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
+ 5'b10100 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 2*M) >> 4;
+ 5'b10101 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+ 5'b10110 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+ 5'b10111 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
+ 5'b11000 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M - 0*M) >> 4;
+ 5'b11001 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
+ 5'b11010 : {PnM_B, M_Sel_B, En_B} <= 3'b101; // (Prod - 4*M + 1*M) >> 4;
+ 5'b11011 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
+ 5'b11100 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 2*M) >> 4;
+ 5'b11101 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
+ 5'b11110 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 1*M) >> 4;
+ 5'b11111 : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+ default : {PnM_B, M_Sel_B, En_B} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+ endcase
+end
+
+// For the second column - C
+
+always @(*)
+begin
+ case(Booth)
+ 5'b00000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 0*M + 0*M) >> 4;
+ 5'b00001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
+ 5'b00010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 0*M + 1*M) >> 4;
+ 5'b00011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
+ 5'b00100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 0*M + 2*M) >> 4;
+ 5'b00101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
+ 5'b00110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 4*M - 1*M) >> 4;
+ 5'b00111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
+ 5'b01000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 4*M + 0*M) >> 4;
+ 5'b01001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+ 5'b01010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod + 4*M + 1*M) >> 4;
+ 5'b01011 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
+ 5'b01100 : {PnM_C, M_Sel_C, En_C} <= 3'b011; // (Prod + 4*M + 2*M) >> 4;
+ 5'b01101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4;
+ 5'b01110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod + 8*M - 1*M) >> 4;
+ 5'b01111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod + 8*M + 0*M) >> 4;
+ 5'b10000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 8*M - 0*M) >> 4;
+ 5'b10001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
+ 5'b10010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 8*M + 1*M) >> 4;
+ 5'b10011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
+ 5'b10100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 4*M - 2*M) >> 4;
+ 5'b10101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+ 5'b10110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 4*M - 1*M) >> 4;
+ 5'b10111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
+ 5'b11000 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 4*M - 0*M) >> 4;
+ 5'b11001 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
+ 5'b11010 : {PnM_C, M_Sel_C, En_C} <= 3'b001; // (Prod - 4*M + 1*M) >> 4;
+ 5'b11011 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
+ 5'b11100 : {PnM_C, M_Sel_C, En_C} <= 3'b111; // (Prod - 0*M - 2*M) >> 4;
+ 5'b11101 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
+ 5'b11110 : {PnM_C, M_Sel_C, En_C} <= 3'b101; // (Prod - 0*M - 1*M) >> 4;
+ 5'b11111 : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+ default : {PnM_C, M_Sel_C, En_C} <= 3'b000; // (Prod - 0*M - 0*M) >> 4;
+ endcase
+end
+
+// Compute the first operand - B
+
+always @(*)
+begin
+ case({PnM_B, M_Sel_B, En_B})
+ 3'b001 : {Ci_B, B} <= {1'b0, Mx4};
+ 3'b011 : {Ci_B, B} <= {1'b0, Mx8};
+ 3'b101 : {Ci_B, B} <= {1'b1, ~Mx4};
+ 3'b111 : {Ci_B, B} <= {1'b1, ~Mx8};
+ default : {Ci_B, B} <= 0;
+ endcase
+end
+
+// Compute the second operand - C
+
+always @(*)
+begin
+ case({PnM_C, M_Sel_C, En_C})
+ 3'b001 : {Ci_C, C} <= {1'b0, Mx1};
+ 3'b011 : {Ci_C, C} <= {1'b0, Mx2};
+ 3'b101 : {Ci_C, C} <= {1'b1, ~Mx1};
+ 3'b111 : {Ci_C, C} <= {1'b1, ~Mx2};
+ default : {Ci_C, C} <= 0;
+ endcase
+end
+
+// Compute Partial Sum - Cascaded Adders
+
+assign T = Hi + B + Ci_B;
+assign S = T + C + Ci_C;
+
+// Double Length Product Register
+// Multiplier, R, is loaded into the least significant half on load, Ld
+// Shifted right four places as the product is computed iteratively.
+
+always @(posedge Clk)
+begin
+ if(Rst)
+ Prod <= #1 0;
+ else if(Ld)
+ Prod <= #1 R;
+ else if(|Cntr) // Shift right four bits
+ Prod <= #1 {{4{S[(N + 3)]}}, S, Prod[(N - 1):4]};
+end
+
+always @(posedge Clk)
+begin
+ if(Rst)
+ Guard <= #1 0;
+ else if(Ld)
+ Guard <= #1 0;
+ else if(|Cntr)
+ Guard <= #1 Prod[3];
+end
+
+// Assign the product less the four guard bits to the output port
+// A 4-bit right shift is required since the output product is stored
+// into a synchronous register on the last cycle of the multiply.
+
+always @(posedge Clk)
+begin
+ if(Rst)
+ P <= #1 0;
+ else if(Cntr == 1)
+ P <= #1 {S, Prod[(N - 1):4]};
+end
+
+// Count the number of shifts
+// This implementation does not use any optimizations to perform multiple
+// bit shifts to skip over runs of 1s or 0s.
+
+always @(posedge Clk)
+begin
+ if(Rst)
+ Valid <= #1 0;
+ else
+ Valid <= #1 (Cntr == 1);
+end
+
+endmodule
\ No newline at end of file
diff --git a/openlane/designs/PPU/config.tcl b/openlane/designs/PPU/config.tcl
new file mode 100755
index 0000000..9499267
--- /dev/null
+++ b/openlane/designs/PPU/config.tcl
@@ -0,0 +1,12 @@
+# Design
+set ::env(DESIGN_NAME) "PPU"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/PPU.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/PPU/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/PPU/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..210f243
--- /dev/null
+++ b/openlane/designs/PPU/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "18.0"
+
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
diff --git a/openlane/designs/PPU/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/PPU/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..21c6939
--- /dev/null
+++ b/openlane/designs/PPU/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "18.0"
diff --git a/openlane/designs/PPU/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/PPU/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..21c6939
--- /dev/null
+++ b/openlane/designs/PPU/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "18.0"
diff --git a/openlane/designs/PPU/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/PPU/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..21c6939
--- /dev/null
+++ b/openlane/designs/PPU/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "18.0"
diff --git a/openlane/designs/PPU/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/PPU/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..21c6939
--- /dev/null
+++ b/openlane/designs/PPU/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+
+
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "18.0"
diff --git a/openlane/designs/PPU/src/PPU.v b/openlane/designs/PPU/src/PPU.v
new file mode 100644
index 0000000..f58a2da
--- /dev/null
+++ b/openlane/designs/PPU/src/PPU.v
@@ -0,0 +1,708 @@
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// This program is GPL Licensed. See COPYING for the full license.
+
+// Module handles updating the loopy scroll register
+module LoopyGen(input clk, input ce,
+ input is_rendering,
+ input [2:0] ain, // input address from CPU
+ input [7:0] din, // data input
+ input read, // read
+ input write, // write
+ input is_pre_render, // Is this the pre-render scanline
+ input [8:0] cycle,
+ output [14:0] loopy,
+ output [2:0] fine_x_scroll); // Current loopy value
+ // Controls how much to increment on each write
+ reg ppu_incr; // 0 = 1, 1 = 32
+ // Current VRAM address
+ reg [14:0] loopy_v;
+ // Temporary VRAM address
+ reg [14:0] loopy_t;
+ // Fine X scroll (3 bits)
+ reg [2:0] loopy_x;
+ // Latch
+ reg ppu_address_latch;
+ initial begin
+ ppu_incr = 0;
+ loopy_v = 0;
+ loopy_t = 0;
+ loopy_x = 0;
+ ppu_address_latch = 0;
+ end
+ // Handle updating loopy_t and loopy_v
+ always @(posedge clk) if (ce) begin
+ if (is_rendering) begin
+ // Increment course X scroll right after attribute table byte was fetched.
+ if (cycle[2:0] == 3 && (cycle < 256 || cycle >= 320 && cycle < 336)) begin
+ loopy_v[4:0] <= loopy_v[4:0] + 1;
+ loopy_v[10] <= loopy_v[10] ^ (loopy_v[4:0] == 31);
+ end
+
+ // Vertical Increment
+ if (cycle == 251) begin
+ loopy_v[14:12] <= loopy_v[14:12] + 1;
+ if (loopy_v[14:12] == 7) begin
+ if (loopy_v[9:5] == 29) begin
+ loopy_v[9:5] <= 0;
+ loopy_v[11] <= !loopy_v[11];
+ end else begin
+ loopy_v[9:5] <= loopy_v[9:5] + 1;
+ end
+ end
+ end
+
+ // Horizontal Reset at cycle 257
+ if (cycle == 256)
+ {loopy_v[10], loopy_v[4:0]} <= {loopy_t[10], loopy_t[4:0]};
+
+ // On cycle 256 of each scanline, copy horizontal bits from loopy_t into loopy_v
+ // On cycle 304 of the pre-render scanline, copy loopy_t into loopy_v
+ if (cycle == 304 && is_pre_render) begin
+ loopy_v <= loopy_t;
+ end
+ end
+ if (write && ain == 0) begin
+ loopy_t[10] <= din[0];
+ loopy_t[11] <= din[1];
+ ppu_incr <= din[2];
+ end else if (write && ain == 5) begin
+ if (!ppu_address_latch) begin
+ loopy_t[4:0] <= din[7:3];
+ loopy_x <= din[2:0];
+ end else begin
+ loopy_t[9:5] <= din[7:3];
+ loopy_t[14:12] <= din[2:0];
+ end
+ ppu_address_latch <= !ppu_address_latch;
+ end else if (write && ain == 6) begin
+ if (!ppu_address_latch) begin
+ loopy_t[13:8] <= din[5:0];
+ loopy_t[14] <= 0;
+ end else begin
+ loopy_t[7:0] <= din;
+ loopy_v <= {loopy_t[14:8], din};
+ end
+ ppu_address_latch <= !ppu_address_latch;
+ end else if (read && ain == 2) begin
+ ppu_address_latch <= 0; //Reset PPU address latch
+ end else if ((read || write) && ain == 7 && !is_rendering) begin
+ // Increment address every time we accessed a reg
+ loopy_v <= loopy_v + (ppu_incr ? 32 : 1);
+ end
+ end
+ assign loopy = loopy_v;
+ assign fine_x_scroll = loopy_x;
+endmodule
+
+
+// Generates the current scanline / cycle counters
+module ClockGen(input clk, input ce, input reset,
+ input is_rendering,
+ output reg [8:0] scanline,
+ output reg [8:0] cycle,
+ output reg is_in_vblank,
+ output end_of_line,
+ output at_last_cycle_group,
+ output exiting_vblank,
+ output entering_vblank,
+ output reg is_pre_render);
+ reg second_frame;
+
+ // Scanline 0..239 = picture scan lines
+ // Scanline 240 = dummy scan line
+ // Scanline 241..260 = VBLANK
+ // Scanline -1 = Pre render scanline (Fetches objects for next line)
+ assign at_last_cycle_group = (cycle[8:3] == 42);
+ // Every second pre-render frame is only 340 cycles instead of 341.
+ assign end_of_line = at_last_cycle_group && cycle[3:0] == (is_pre_render && second_frame && is_rendering ? 3 : 4);
+ // Set the clock right before vblank begins
+ assign entering_vblank = end_of_line && scanline == 240;
+ // Set the clock right before vblank ends
+ assign exiting_vblank = end_of_line && scanline == 260;
+ // New value for is_in_vblank flag
+ wire new_is_in_vblank = entering_vblank ? 1'b1 : exiting_vblank ? 1'b0 : is_in_vblank;
+ // Set if the current line is line 0..239
+ always @(posedge clk) if (reset) begin
+ cycle <= 0;
+ is_in_vblank <= 1;
+ end else if (ce) begin
+ cycle <= end_of_line ? 0 : cycle + 1;
+ is_in_vblank <= new_is_in_vblank;
+ end
+// always @(posedge clk) if (ce) begin
+// $write("%x %x %x %x %x\n", new_is_in_vblank, entering_vblank, exiting_vblank, is_in_vblank, entering_vblank ? 1'b1 : exiting_vblank ? 1'b0 : is_in_vblank);
+
+// end
+ always @(posedge clk) if (reset) begin
+ scanline <= 0;
+ is_pre_render <= 0;
+ second_frame <= 0;
+ end else if (ce && end_of_line) begin
+ // Once the scanline counter reaches end of 260, it gets reset to -1.
+ scanline <= exiting_vblank ? 9'b111111111 : scanline + 1;
+ // The pre render flag is set while we're on scanline -1.
+ is_pre_render <= exiting_vblank;
+
+ if (exiting_vblank)
+ second_frame <= !second_frame;
+ end
+
+endmodule // ClockGen
+
+// 8 of these exist, they are used to output sprites.
+module Sprite(input clk, input ce,
+ input enable,
+ input [3:0] load,
+ input [26:0] load_in,
+ output [26:0] load_out,
+ output [4:0] bits); // Low 4 bits = pixel, high bit = prio
+ reg [1:0] upper_color; // Upper 2 bits of color
+ reg [7:0] x_coord; // X coordinate where we want things
+ reg [7:0] pix1, pix2; // Shift registers, output when x_coord == 0
+ reg aprio; // Current prio
+ wire active = (x_coord == 0);
+ always @(posedge clk) if (ce) begin
+ if (enable) begin
+ if (!active) begin
+ // Decrease until x_coord is zero.
+ x_coord <= x_coord - 8'h01;
+ end else begin
+ pix1 <= pix1 >> 1;
+ pix2 <= pix2 >> 1;
+ end
+ end
+ if (load[3]) pix1 <= load_in[26:19];
+ if (load[2]) pix2 <= load_in[18:11];
+ if (load[1]) x_coord <= load_in[10:3];
+ if (load[0]) {upper_color, aprio} <= load_in[2:0];
+ end
+ assign bits = {aprio, upper_color, active && pix2[0], active && pix1[0]};
+ assign load_out = {pix1, pix2, x_coord, upper_color, aprio};
+endmodule // SpriteGen
+
+// This contains all 8 sprites. Will return the pixel value of the highest prioritized sprite.
+// When load is set, and clocked, load_in is loaded into sprite 7 and all others are shifted down.
+// Sprite 0 has highest prio.
+// 226 LUTs, 68 Slices
+module SpriteSet(input clk, input ce, // Input clock
+ input enable, // Enable pixel generation
+ input [3:0] load, // Which parts of the state to load/shift.
+ input [26:0] load_in, // State to load with
+ output [4:0] bits, // Output bits
+ output is_sprite0); // Set to true if sprite #0 was output
+
+ wire [26:0] load_out7, load_out6, load_out5, load_out4, load_out3, load_out2, load_out1, load_out0;
+ wire [4:0] bits7, bits6, bits5, bits4, bits3, bits2, bits1, bits0;
+ Sprite sprite7(clk, ce, enable, load, load_in, load_out7, bits7);
+ Sprite sprite6(clk, ce, enable, load, load_out7, load_out6, bits6);
+ Sprite sprite5(clk, ce, enable, load, load_out6, load_out5, bits5);
+ Sprite sprite4(clk, ce, enable, load, load_out5, load_out4, bits4);
+ Sprite sprite3(clk, ce, enable, load, load_out4, load_out3, bits3);
+ Sprite sprite2(clk, ce, enable, load, load_out3, load_out2, bits2);
+ Sprite sprite1(clk, ce, enable, load, load_out2, load_out1, bits1);
+ Sprite sprite0(clk, ce, enable, load, load_out1, load_out0, bits0);
+ // Determine which sprite is visible on this pixel.
+ assign bits = bits0[1:0] != 0 ? bits0 :
+ bits1[1:0] != 0 ? bits1 :
+ bits2[1:0] != 0 ? bits2 :
+ bits3[1:0] != 0 ? bits3 :
+ bits4[1:0] != 0 ? bits4 :
+ bits5[1:0] != 0 ? bits5 :
+ bits6[1:0] != 0 ? bits6 :
+ bits7;
+ assign is_sprite0 = bits0[1:0] != 0;
+endmodule // SpriteSet
+
+module SpriteRAM(input clk, input ce,
+ input reset_line, // OAM evaluator needs to be reset before processing is started.
+ input sprites_enabled, // Set to 1 if evaluations are enabled
+ input exiting_vblank, // Set to 1 when exiting vblank so spr_overflow can be reset
+ input obj_size, // Set to 1 if objects are 16 pixels.
+ input [8:0] scanline, // Current scan line (compared against Y)
+ input [8:0] cycle, // Current cycle.
+ output reg [7:0] oam_bus, // Current value on the OAM bus, returned to NES through $2004.
+ input oam_ptr_load, // Load oam with specified value, when writing to NES $2003.
+ input oam_load, // Load oam_ptr with specified value, when writing to NES $2004.
+ input [7:0] data_in, // New value for oam or oam_ptr
+ output reg spr_overflow, // Set to true if we had more than 8 objects on a scan line. Reset when exiting vblank.
+ output reg sprite0); // True if sprite#0 is included on the scan line currently being painted.
+ reg [7:0] sprtemp[0:31]; // Sprite Temporary Memory. 32 bytes.
+ reg [7:0] oam[0:255]; // Sprite OAM. 256 bytes.
+ reg [7:0] oam_ptr; // Pointer into oam_ptr.
+ reg [2:0] p; // Upper 3 bits of pointer into temp, the lower bits are oam_ptr[1:0].
+ reg [1:0] state; // Current state machine state
+ wire [7:0] oam_data = oam[oam_ptr];
+ // Compute the current address we read/write in sprtemp.
+ reg [4:0] sprtemp_ptr;
+ // Check if the current Y coordinate is inside.
+ wire [8:0] spr_y_coord = scanline - {1'b0, oam_data};
+ wire spr_is_inside = (spr_y_coord[8:4] == 0) && (obj_size || spr_y_coord[3] == 0);
+ reg [7:0] new_oam_ptr; // [wire] New value for oam ptr
+ reg [1:0] oam_inc; // [wire] How much to increment oam ptr
+ reg sprite0_curr; // If sprite0 is included on the line being processed.
+ reg oam_wrapped; // [wire] if new_oam or new_p wrapped.
+
+ wire [7:0] sprtemp_data = sprtemp[sprtemp_ptr];
+ always @* begin
+ // Compute address to read/write in temp sprite ram
+ case({cycle[8], cycle[2]})
+ 2'b0_?: sprtemp_ptr = {p, oam_ptr[1:0]};
+ 2'b1_0: sprtemp_ptr = {cycle[5:3], cycle[1:0]}; // 1-4. Read Y, Tile, Attribs
+ 2'b1_1: sprtemp_ptr = {cycle[5:3], 2'b11}; // 5-8. Keep reading X.
+ endcase
+ end
+
+ always @* begin
+ /* verilator lint_off CASEOVERLAP */
+ // Compute value to return to cpu through $2004. And also the value that gets written to temp sprite ram.
+ case({sprites_enabled, cycle[8], cycle[6], state, oam_ptr[1:0]})
+ 7'b1_10_??_??: oam_bus = sprtemp_data; // At cycle 256-319 we output what's in sprite temp ram
+ 7'b1_??_00_??: oam_bus = 8'b11111111; // On the first 64 cycles (while inside state 0), we output 0xFF.
+ 7'b1_??_01_00: oam_bus = {4'b0000, spr_y_coord[3:0]}; // Y coord that will get written to temp ram.
+ 7'b?_??_??_10: oam_bus = {oam_data[7:5], 3'b000, oam_data[1:0]}; // Bits 2-4 of attrib are always zero when reading oam.
+ default: oam_bus = oam_data; // Default to outputting from oam.
+ endcase
+ end
+
+ always @* begin
+ // Compute incremented oam counters
+ case ({oam_load, state, oam_ptr[1:0]})
+ 5'b1_??_??: oam_inc = {oam_ptr[1:0] == 3, 1'b1}; // Always increment by 1 when writing to oam.
+ 5'b0_00_??: oam_inc = 2'b01; // State 0: On the the first 64 cycles we fill temp ram with 0xFF, increment low bits.
+ 5'b0_01_00: oam_inc = {!spr_is_inside, spr_is_inside}; // State 1: Copy Y coordinate and increment oam by 1 if it's inside, otherwise 4.
+ 5'b0_01_??: oam_inc = {oam_ptr[1:0] == 3, 1'b1}; // State 1: Copy remaining 3 bytes of the oam.
+ // State 3: We've had more than 8 sprites. Set overflow flag if we found a sprite that overflowed.
+ // NES BUG: It increments both low and high counters.
+ 5'b0_11_??: oam_inc = 2'b11;
+ // While in the final state, keep incrementing the low bits only until they're zero.
+ 5'b0_10_??: oam_inc = {1'b0, oam_ptr[1:0] != 0};
+ endcase
+ /* verilator lint_on CASEOVERLAP */
+ new_oam_ptr[1:0] = oam_ptr[1:0] + {1'b0, oam_inc[0]};
+ {oam_wrapped, new_oam_ptr[7:2]} = {1'b0, oam_ptr[7:2]} + {6'b0, oam_inc[1]};
+ end
+ always @(posedge clk) if (ce) begin
+
+ // Some bits of the OAM are hardwired to zero.
+ if (oam_load)
+ oam[oam_ptr] <= (oam_ptr & 3) == 2 ? data_in & 8'hE3: data_in;
+ if (cycle[0] && sprites_enabled || oam_load || oam_ptr_load) begin
+ oam_ptr <= oam_ptr_load ? data_in : new_oam_ptr;
+ end
+ // Set overflow flag?
+ if (sprites_enabled && state == 2'b11 && spr_is_inside)
+ spr_overflow <= 1;
+ // Remember if sprite0 is included on the scanline, needed for hit test later.
+ sprite0_curr <= (state == 2'b01 && oam_ptr[7:2] == 0 && spr_is_inside || sprite0_curr);
+
+// if (scanline == 0 && cycle[0] && (state == 2'b01 || state == 2'b00))
+// $write("Drawing sprite %d/%d. bus=%d oam_ptr=%X->%X oam_data=%X p=%d (%d %d %d)\n", scanline, cycle, oam_bus, oam_ptr, new_oam_ptr, oam_data, p,
+// cycle[0] && sprites_enabled, oam_load, oam_ptr_load);
+
+ // Always writing to temp ram while we're in state 0 or 1.
+ if (!state[1]) sprtemp[sprtemp_ptr] <= oam_bus;
+ // Update state machine on every second cycle.
+ if (cycle[0]) begin
+ // Increment p whenever oam_ptr carries in state 0 or 1.
+ if (!state[1] && oam_ptr[1:0] == 2'b11) p <= p + 1;
+ // Set sprite0 if sprite1 was included on the scan line
+ case({state, (p == 7) && (oam_ptr[1:0] == 2'b11), oam_wrapped})
+ 4'b00_0_?: state <= 2'b00; // State #0: Keep filling
+ 4'b00_1_?: state <= 2'b01; // State #0: Until we filled 64 items.
+ 4'b01_?_1: state <= 2'b10; // State #1: Goto State 2 if processed all OAM
+ 4'b01_1_0: state <= 2'b11; // State #1: Goto State 3 if we found 8 sprites
+ 4'b01_0_0: state <= 2'b01; // State #1: Keep comparing Y coordinates.
+ 4'b11_?_1: state <= 2'b10; // State #3: Goto State 2 if processed all OAM
+ 4'b11_?_0: state <= 2'b11; // State #3: Keep comparing Y coordinates
+ 4'b10_?_?: state <= 2'b10; // Stuck in state 2.
+ endcase
+ end
+ if (reset_line) begin
+ state <= 0;
+ p <= 0;
+ oam_ptr <= 0;
+ sprite0_curr <= 0;
+ sprite0 <= sprite0_curr;
+ end
+ if (exiting_vblank)
+ spr_overflow <= 0;
+ end
+endmodule // SpriteRAM
+
+
+// Generates addresses in VRAM where we'll fetch sprite graphics from,
+// and populates load, load_in so the SpriteGen can be loaded.
+// 10 LUT, 4 Slices
+module SpriteAddressGen(input clk, input ce,
+ input enabled, // If unset, |load| will be all zeros.
+ input obj_size, // 0: Sprite Height 8, 1: Sprite Height 16.
+ input obj_patt, // Object pattern table selection
+ input [2:0] cycle, // Current load cycle. At #4, first bitmap byte is loaded. At #6, second bitmap byte is.
+ input [7:0] temp, // Input temp data from SpriteTemp. #0 = Y Coord, #1 = Tile, #2 = Attribs, #3 = X Coord
+ output [12:0] vram_addr,// Low bits of address in VRAM that we'd like to read.
+ input [7:0] vram_data, // Byte of VRAM in the specified address
+ output [3:0] load, // Which subset of load_in that is now valid, will be loaded into SpritesGen.
+ output [26:0] load_in); // Bits to load into SpritesGen.
+ reg [7:0] temp_tile; // Holds the tile that we will get
+ reg [3:0] temp_y; // Holds the Y coord (will be swapped based on FlipY).
+ reg flip_x, flip_y; // If incoming bitmap data needs to be flipped in the X or Y direction.
+ wire load_y = (cycle == 0);
+ wire load_tile = (cycle == 1);
+ wire load_attr = (cycle == 2) && enabled;
+ wire load_x = (cycle == 3) && enabled;
+ wire load_pix1 = (cycle == 5) && enabled;
+ wire load_pix2 = (cycle == 7) && enabled;
+ reg dummy_sprite; // Set if attrib indicates the sprite is invalid.
+ // Flip incoming vram data based on flipx. Zero out the sprite if it's invalid. The bits are already flipped once.
+ wire [7:0] vram_f = dummy_sprite ? 0 :
+ !flip_x ? {vram_data[0], vram_data[1], vram_data[2], vram_data[3], vram_data[4], vram_data[5], vram_data[6], vram_data[7]} :
+ vram_data;
+ wire [3:0] y_f = temp_y ^ {flip_y, flip_y, flip_y, flip_y};
+ assign load = {load_pix1, load_pix2, load_x, load_attr};
+ assign load_in = {vram_f, vram_f, temp, temp[1:0], temp[5]};
+ // If $2000.5 = 0, the tile index data is used as usual, and $2000.3
+ // selects the pattern table to use. If $2000.5 = 1, the MSB of the range
+ // result value become the LSB of the indexed tile, and the LSB of the tile
+ // index value determines pattern table selection. The lower 3 bits of the
+ // range result value are always used as the fine vertical offset into the
+ // selected pattern.
+ assign vram_addr = {obj_size ? temp_tile[0] : obj_patt,
+ temp_tile[7:1], obj_size ? y_f[3] : temp_tile[0], cycle[1], y_f[2:0] };
+ always @(posedge clk) if (ce) begin
+ if (load_y) temp_y <= temp[3:0];
+ if (load_tile) temp_tile <= temp;
+ if (load_attr) {flip_y, flip_x, dummy_sprite} <= {temp[7:6], temp[4]};
+ end
+// always @(posedge clk) begin
+// if (load[3]) $write("Loading pix1: %x\n", load_in[26:19]);
+// if (load[2]) $write("Loading pix2: %x\n", load_in[18:11]);
+// if (load[1]) $write("Loading x: %x\n", load_in[10:3]);
+//
+// if (valid_sprite && enabled)
+// $write("%d. Found %d. Flip:%d%d, Addr: %x, Vram: %x!\n", cycle, temp, flip_x, flip_y, vram_addr, vram_data);
+// end
+
+endmodule // SpriteAddressGen
+
+module BgPainter(input clk, input ce,
+ input enable, // Shift registers activated
+ input [2:0] cycle,
+ input [2:0] fine_x_scroll,
+ input [14:0] loopy,
+ output [7:0] name_table, // VRAM name table to read next.
+ input [7:0] vram_data,
+ output [3:0] pixel);
+ reg [15:0] playfield_pipe_1; // Name table pixel pipeline #1
+ reg [15:0] playfield_pipe_2; // Name table pixel pipeline #2
+ reg [8:0] playfield_pipe_3; // Attribute table pixel pipe #1
+ reg [8:0] playfield_pipe_4; // Attribute table pixel pipe #2
+ reg [7:0] current_name_table; // Holds the current name table byte
+ reg [1:0] current_attribute_table; // Holds the 2 current attribute table bits
+ reg [7:0] bg0; // Pixel data for last loaded background
+ wire [7:0] bg1 = vram_data;
+ initial begin
+ playfield_pipe_1 = 0;
+ playfield_pipe_2 = 0;
+ playfield_pipe_3 = 0;
+ playfield_pipe_4 = 0;
+ current_name_table = 0;
+ current_attribute_table = 0;
+ bg0 = 0;
+ end
+ always @(posedge clk) if (ce) begin
+ case (cycle[2:0])
+ 1: current_name_table <= vram_data;
+ 3: current_attribute_table <= (!loopy[1] && !loopy[6]) ? vram_data[1:0] :
+ ( loopy[1] && !loopy[6]) ? vram_data[3:2] :
+ (!loopy[1] && loopy[6]) ? vram_data[5:4] :
+ vram_data[7:6];
+ 5: bg0 <= vram_data; // Pattern table bitmap #0
+// 7: bg1 <= vram_data; // Pattern table bitmap #1
+ endcase
+ if (enable) begin
+ playfield_pipe_1[14:0] <= playfield_pipe_1[15:1];
+ playfield_pipe_2[14:0] <= playfield_pipe_2[15:1];
+ playfield_pipe_3[7:0] <= playfield_pipe_3[8:1];
+ playfield_pipe_4[7:0] <= playfield_pipe_4[8:1];
+ // Load the new values into the shift registers at the last pixel.
+ if (cycle[2:0] == 7) begin
+ playfield_pipe_1[15:8] <= {bg0[0], bg0[1], bg0[2], bg0[3], bg0[4], bg0[5], bg0[6], bg0[7]};
+ playfield_pipe_2[15:8] <= {bg1[0], bg1[1], bg1[2], bg1[3], bg1[4], bg1[5], bg1[6], bg1[7]};
+ playfield_pipe_3[8] <= current_attribute_table[0];
+ playfield_pipe_4[8] <= current_attribute_table[1];
+ end
+ end
+ end
+ assign name_table = current_name_table;
+ wire [3:0] i = {1'b0, fine_x_scroll};
+ assign pixel = {playfield_pipe_4[i], playfield_pipe_3[i],
+ playfield_pipe_2[i], playfield_pipe_1[i]};
+endmodule // BgPainter
+
+module PixelMuxer(input [3:0] bg, input [3:0] obj, input obj_prio, output [3:0] out, output is_obj);
+ wire bg_flag = bg[0] | bg[1];
+ wire obj_flag = obj[0] | obj[1];
+ assign is_obj = !(obj_prio && bg_flag) && obj_flag;
+ assign out = is_obj ? obj : bg;
+endmodule
+
+
+module PaletteRam(input clk, input ce, input [4:0] addr, input [5:0] din, output [5:0] dout, input write);
+ reg [5:0] palette [0:31];
+ initial begin
+ //$readmemh("oam_palette.txt", palette);
+ end
+ // Force read from backdrop channel if reading from any addr 0.
+ wire [4:0] addr2 = (addr[1:0] == 0) ? 0 : addr;
+ assign dout = palette[addr2];
+ always @(posedge clk) if (ce && write) begin
+ // Allow writing only to x0
+ if (!(addr[3:2] != 0 && addr[1:0] == 0))
+ palette[addr2] <= din;
+ end
+endmodule // PaletteRam
+
+module PPU(input clk, input ce, input reset, // input clock 21.48 MHz / 4. 1 clock cycle = 1 pixel
+ output [5:0] color, // output color value, one pixel outputted every clock
+ input [7:0] din, // input data from bus
+ output [7:0] dout, // output data to CPU
+ input [2:0] ain, // input address from CPU
+ input read, // read
+ input write, // write
+ output nmi, // one while inside vblank
+ output vram_r, // read from vram active
+ output vram_w, // write to vram active
+ output [13:0] vram_a, // vram address
+ input [7:0] vram_din, // vram input
+ output [7:0] vram_dout,
+ output [8:0] scanline,
+ output [8:0] cycle,
+ output [19:0] mapper_ppu_flags);
+ // These are stored in control register 0
+ reg obj_patt; // Object pattern table
+ reg bg_patt; // Background pattern table
+ reg obj_size; // 1 if sprites are 16 pixels high, else 0.
+ reg vbl_enable; // Enable VBL flag
+ // These are stored in control register 1
+ reg grayscale; // Disable color burst
+ reg playfield_clip; // 0: Left side 8 pixels playfield clipping
+ reg object_clip; // 0: Left side 8 pixels object clipping
+ reg enable_playfield; // Enable playfield display
+ reg enable_objects; // Enable objects display
+ reg [2:0] color_intensity; // Color intensity
+
+ initial begin
+ obj_patt = 0;
+ bg_patt = 0;
+ obj_size = 0;
+ vbl_enable = 0;
+ grayscale = 0;
+ playfield_clip = 0;
+ object_clip = 0;
+ enable_playfield = 0;
+ enable_objects = 0;
+ color_intensity = 0;
+ end
+
+ reg nmi_occured; // True if NMI has occured but not cleared.
+ reg [7:0] vram_latch;
+ // Clock generator
+ wire is_in_vblank; // True if we're in VBLANK
+ //wire [8:0] scanline; // Current scanline
+ //wire [8:0] cycle; // Current cycle inside of the line
+ wire end_of_line; // At the last pixel of a line
+ wire at_last_cycle_group; // At the very last cycle group of the scan line.
+ wire exiting_vblank; // At the very last cycle of the vblank
+ wire entering_vblank; //
+ wire is_pre_render_line; // True while we're on the pre render scanline
+ wire is_rendering = (enable_playfield || enable_objects) && !is_in_vblank && scanline != 240;
+
+ ClockGen clock(clk, ce, reset, is_rendering, scanline, cycle, is_in_vblank, end_of_line, at_last_cycle_group,
+ exiting_vblank, entering_vblank, is_pre_render_line);
+
+
+ // The loopy module handles updating of the loopy address
+ wire [14:0] loopy;
+ wire [2:0] fine_x_scroll;
+ LoopyGen loopy0(clk, ce, is_rendering, ain, din, read, write, is_pre_render_line, cycle, loopy, fine_x_scroll);
+ // Set to true if the current ppu_addr pointer points into
+ // palette ram.
+ wire is_pal_address = (loopy[13:8] == 6'b111111);
+
+ // Paints background
+ wire [7:0] bg_name_table;
+ wire [3:0] bg_pixel_noblank;
+ BgPainter bg_painter(clk, ce, !at_last_cycle_group, cycle[2:0], fine_x_scroll, loopy, bg_name_table, vram_din, bg_pixel_noblank);
+
+ // Blank out BG in the leftmost 8 pixels?
+ wire show_bg_on_pixel = (playfield_clip || (cycle[7:3] != 0)) && enable_playfield;
+ wire [3:0] bg_pixel = {bg_pixel_noblank[3:2], show_bg_on_pixel ? bg_pixel_noblank[1:0] : 2'b00};
+
+ // This will set oam_ptr to 0 right before the scanline 240 and keep it there throughout vblank.
+ wire before_line = (enable_playfield || enable_objects) && (exiting_vblank || end_of_line && !is_in_vblank);
+ wire [7:0] oam_bus;
+ wire sprite_overflow;
+ wire obj0_on_line; // True if sprite#0 is included on the current line
+ SpriteRAM sprite_ram(clk, ce,
+ before_line, // Condition for resetting the sprite line state.
+ is_rendering, // Condition for enabling sprite ram logic. Check so we're not on
+ exiting_vblank,
+ obj_size,
+ scanline, cycle,
+ oam_bus,
+ write && (ain == 3), // Write to oam_ptr
+ write && (ain == 4), // Write to oam[oam_ptr]
+ din,
+ sprite_overflow,
+ obj0_on_line);
+ wire [4:0] obj_pixel_noblank;
+ wire [12:0] sprite_vram_addr;
+ wire is_obj0_pixel; // True if obj_pixel originates from sprite0.
+ wire [3:0] spriteset_load; // Which subset of the |load_in| to load into SpriteSet
+ wire [26:0] spriteset_load_in; // Bits to load into SpriteSet
+ // Between 256..319 (64 cycles), fetches bitmap data for the 8 sprites and fills in the SpriteSet
+ // so that it can start drawing on the next frame.
+ SpriteAddressGen address_gen(clk, ce,
+ cycle[8] && !cycle[6], // Load sprites between 256..319
+ obj_size, obj_patt, // Object size and pattern table
+ cycle[2:0], // Cycle counter
+ oam_bus, // Info from temp buffer.
+ sprite_vram_addr, // [out] VRAM Address that we want data from
+ vram_din, // [in] Data at the specified address
+ spriteset_load,
+ spriteset_load_in); // Which parts of SpriteGen to load
+ // Between 0..255 (256 cycles), draws pixels.
+ // Between 256..319 (64 cycles), will be populated for next line
+ SpriteSet sprite_gen(clk, ce, !cycle[8], spriteset_load, spriteset_load_in, obj_pixel_noblank, is_obj0_pixel);
+ // Blank out obj in the leftmost 8 pixels?
+ wire show_obj_on_pixel = (object_clip || (cycle[7:3] != 0)) && enable_objects;
+ wire [4:0] obj_pixel = {obj_pixel_noblank[4:2], show_obj_on_pixel ? obj_pixel_noblank[1:0] : 2'b00};
+
+ reg sprite0_hit_bg; // True if sprite#0 has collided with the BG in the last frame.
+ always @(posedge clk) if (ce) begin
+ if (exiting_vblank)
+ sprite0_hit_bg <= 0;
+ else if (is_rendering && // Object rendering is enabled
+ !cycle[8] && // X Pixel 0..255
+ cycle[7:0] != 255 && // X pixel != 255
+ !is_pre_render_line && // Y Pixel 0..239
+ obj0_on_line && // True if sprite#0 is included on the scan line.
+ is_obj0_pixel && // True if the pixel came from tempram #0.
+ show_obj_on_pixel &&
+ bg_pixel[1:0] != 0) begin // Background pixel nonzero.
+ sprite0_hit_bg <= 1;
+
+ end
+
+// if (!cycle[8] && is_visible_line && obj0_on_line && is_obj0_pixel)
+// $write("Sprite0 hit bg scan %d!!\n", scanline);
+
+// if (is_obj0_pixel)
+// $write("drawing obj0 pixel %d/%d\n", scanline, cycle);
+ end
+
+ wire [3:0] pixel;
+ wire pixel_is_obj;
+ PixelMuxer pixel_muxer(bg_pixel, obj_pixel[3:0], obj_pixel[4], pixel, pixel_is_obj);
+
+ // Compute the value to put on the VRAM address bus
+ assign vram_a = !is_rendering ? loopy[13:0] : // VRAM
+ (cycle[2:1] == 0) ? {2'b10, loopy[11:0]} : // Name table
+ (cycle[2:1] == 1) ? {2'b10, loopy[11:10], 4'b1111, loopy[9:7], loopy[4:2]} : // Attribute table
+ cycle[8] && !cycle[6] ? {1'b0, sprite_vram_addr} :
+ {1'b0, bg_patt, bg_name_table, cycle[1], loopy[14:12]}; // Pattern table bitmap #0, #1
+ // Read from VRAM, either when user requested a manual read, or when we're generating pixels.
+ assign vram_r = read && (ain == 7) ||
+ is_rendering && cycle[0] == 0 && !end_of_line;
+
+ // Write to VRAM?
+ assign vram_w = write && (ain == 7) && !is_pal_address && !is_rendering;
+
+ wire [5:0] color2;
+ PaletteRam palette_ram(clk, ce,
+ is_rendering ? {pixel_is_obj, pixel[3:0]} : (is_pal_address ? loopy[4:0] : 5'b0000), // Read addr
+ din[5:0], // Value to write
+ color2, // Output color
+ write && (ain == 7) && is_pal_address); // Condition for writing
+ assign color = grayscale ? {color2[5:4], 4'b0} : color2;
+// always @(posedge clk)
+// if (scanline == 194 && cycle < 8 && color == 15) begin
+// $write("Pixel black %x %x %x %x %x\n", bg_pixel,obj_pixel,pixel,pixel_is_obj,color);
+// end
+
+
+ always @(posedge clk) if (ce) begin
+// if (!is_in_vblank && write)
+// $write("%d/%d: $200%d <= %x\n", scanline, cycle, ain, din);
+ if (write) begin
+ case (ain)
+ 0: begin // PPU Control Register 1
+ // t:....BA.. ........ = d:......BA
+ obj_patt <= din[3];
+ bg_patt <= din[4];
+ obj_size <= din[5];
+ vbl_enable <= din[7];
+
+ //$write("PPU Control #0 <= %X\n", din);
+ end
+ 1: begin // PPU Control Register 2
+ grayscale <= din[0];
+ playfield_clip <= din[1];
+ object_clip <= din[2];
+ enable_playfield <= din[3];
+ enable_objects <= din[4];
+ color_intensity <= din[7:5];
+ if (!din[3] && scanline == 59)
+ $write("Disabling playfield at cycle %d\n", cycle);
+ end
+ endcase
+ end
+
+ // Reset frame specific counters upon exiting vblank
+ if (exiting_vblank)
+ nmi_occured <= 0;
+ // Set the
+ if (entering_vblank)
+ nmi_occured <= 1;
+ // Reset NMI register when reading from Status
+ if (read && ain == 2)
+ nmi_occured <= 0;
+ end
+
+ // If we're triggering a VBLANK NMI
+ assign nmi = nmi_occured && vbl_enable;
+
+ // One cycle after vram_r was asserted, the value
+ // is available on the bus.
+ reg vram_read_delayed;
+ always @(posedge clk) if (ce) begin
+ if (vram_read_delayed)
+ vram_latch <= vram_din;
+ vram_read_delayed = vram_r;
+ end
+
+ // Value currently being written to video ram
+ assign vram_dout = din;
+
+ reg [7:0] latched_dout;
+ always @* begin
+ case (ain)
+ 2: latched_dout = {nmi_occured,
+ sprite0_hit_bg,
+ sprite_overflow,
+ 5'b00000};
+ 4: latched_dout = oam_bus;
+ default: if (is_pal_address) begin
+ latched_dout = {2'b00, color};
+ end else begin
+ latched_dout = vram_latch;
+ end
+ endcase
+ end
+
+ assign dout = latched_dout;
+
+
+ assign mapper_ppu_flags = {scanline, cycle, obj_size, is_rendering};
+
+endmodule // PPU
diff --git a/openlane/designs/README.md b/openlane/designs/README.md
new file mode 100644
index 0000000..56dc733
--- /dev/null
+++ b/openlane/designs/README.md
@@ -0,0 +1,241 @@
+# Designs, Their Configuration, useful utilties:
+
+
+## Adding a design
+
+To add a new design, the following command creates a configuration file for your design:
+
+```bash
+./flow.tcl -design <design_name> -init_design_config
+```
+
+This will create the following directory structure:
+
+```bash
+designs/<design_name>
+├── config.tcl
+```
+In the configuration file, you should edit the required variables and the optional variables, if needed. Further information about the variables can be found [here][2]
+
+Also, the <design_name> could be replaced by the <design_directory>, which will allow you to run any design on your machine.
+
+**Note: config.tcl is a global configuration for all PDKs. For more information about design configuration files please visit this [section](#configuration-files)**
+
+It is recommended to place the design's verilog files in a `src` directory inside the design's folder as following:
+
+```bash
+designs/<design_name>
+├── config.tcl
+├── src
+│ ├── design.v
+```
+
+However, you can point to the src files while initializing the design and they will be pointed to automatically in the configuration file and will also be automatically copied to the src directory creating the same structure shown above.
+
+```bash
+./flow.tcl -design <design_name> -init_design_config -src <list_verilog_files>
+```
+
+Optionally, you can specify the configuration file name (without the extension) by using:
+
+```bash
+./flow.tcl -design <design_name> -init_design_config -tag <config_name>
+```
+
+After adding the design, you can specify the design name using a `-design` argument:
+
+```bash
+./flow.tcl -design <design_name>
+```
+
+Finally, you can specify the configuration file (belonging to that design) the flow should use:
+
+```bash
+./flow.tcl -design <design_name> -config <config_name>
+```
+
+
+## Configuration files
+
+For each design there is a global config.tcl and other config files one for each PDK:
+```bash
+designs/<design_name>
+├── config.tcl
+├── skywater-pdk_sky130_fd_sc_hs_config.tcl
+├── skywater-pdk_sky130_fd_sc_hd_config.tcl
+├── src
+│ ├── design.v
+```
+The general rule generated by using -init_design_config when adding a design is that the global config.tcl should end with:
+```tcl
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
+```
+This implies that if the (PDK)_(STD_CELL_LIBRARY)_config.tcl doesn't exist the flow would resume normally with only the global config.tcl.
+
+This structure allows for storing the best configurations for a given design on all different PDKs and their STD_CELL_LIBRARYs. The best configuration for a given design differ from one PDK and STD_CELL_LIBRARY to another.
+For this reason, upon installing a new PDK/STD_CELL_LIBRARY or a new design, an exploration should be run on different configuration parameters to reach the best configuration. The script that enables this is [here][1].
+After running the exploration, you will find in the logs two .csv newly generated files: {tag}_{timestamp}.csv and {tag}_{timestamp}_best.csv. The configuration name reported in the _best.csv file contains the best added configurations to the current run of the given design using the specified PDK/STD_CELL_LIBRARY.
+
+Two scripts were created for this purpose:
+ - A script to create a new configuration file for a given (PDK, STD_CELL_LIBRARY) pair, or replicate the configuration of a (PDK, STD_CELL_LIBRARY) to another (PDK, STD_CELL_LIBRARY).
+ - A script to update the configuration of a given (PDK, STD_CELL_LIBRARY) according to an exploration result provided by a {tag}_best.csv file.
+
+### Replicate/Create Design Configs for a (PDK,STD_CELL_LIBRARY) Pair:
+
+To run the script to create new (empty) configurations for a (PDK,STD_CELL_LIBRARY) pair:
+```bash
+ python3 ./scripts/replicate_design_configs.py --to-pdk PDK --to-std-cell-lib STD_CELL_LIBRARY
+```
+
+To run the script to replicate configurations from one (PDK,STD_CELL_LIBRARY) pair to another:
+```bash
+ python3 ./scripts/replicate_design_configs.py --from-pdk PDK_FROM --from-std-cell-lib STD_CELL_LIBRARY_FROM --to-pdk PDK --to-std-cell-lib STD_CELL_LIBRARY
+```
+
+The following is the list of flags used with the script:
+<table>
+ <tr>
+ <th>
+ Argument
+ </th>
+ <th >
+ Description
+ </th>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--designs | -d <design1 design2 design3 ...> </code> <br> (Optional)
+ </td>
+ <td align="justify">
+ Specifies the designs to create/replicate the configs for. same as -design argument in flow.tcl <br> Default is to update all designs under designs/
+ </td>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--from-pdk | -fp <PDK></code> <br> (Optional)
+ </td>
+ <td align="justify">
+ The name of the PDK that the replicated design configuration belongs to. <br> if not specified along with from-std-cell-lib, the script will create a new configuration file for (pdkTo,to_std_cell_lib) that is empty.
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--from-std-cell-lib | -fscl <STD_CELL_LIBRARY></code> <br> (Optional)
+ </td>
+ <td align="justify">
+ The name of the STD_CELL_LIBRARY that the replicated design configuration belongs to. <br> if not specified along with from_std_cell_lib, the script will create a new configuration file for (pdkTo,to_std_cell_lib) that is empty.
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--to-pdk | -tp <PDK></code> <br> (Required)
+ </td>
+ <td align="justify">
+ The name of the PDK that the created design configurations belongs to.
+ </td>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--to-std-cell-lib | -tscl <STD_CELL_LIBRARY></code> <br> (Required)
+ </td>
+ <td align="justify">
+ The name of the STD_CELL_LIBRARY that the created design configurations belongs to.
+ </td>
+ </tr>
+</table>
+
+### Update Design Configs for a (PDK,STD_CELL_LIBRARY) Pair after an Exploration:
+
+To run the script to update configurations for a (PDK,STD_CELL_LIBRARY) pair after an exploration:
+```bash
+ python3 ./scripts/update_designs_configs.py --pdk PDK --std-cell-lib STD_CELL_LIBRARY --best_results SW_exploration_best.csv
+```
+
+Check [this][1] for more details on the log files.
+
+The following is the list of flags used with the script:
+<table>
+ <tr>
+ <th>
+ Argument
+ </th>
+ <th >
+ Description
+ </th>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--designs | -d <design1 design2 design3 ...> </code> <br> (Optional)
+ </td>
+ <td align="justify">
+ Specifies the designs to update the configs for. Same us -design in flow.tcl. <br> Default is to update all designs that exist in the given log file (_best.csv)
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--root | -r <dirctory> </code> <br> (Optional)
+ </td>
+ <td align="justify">
+ Sets the root directory. The root should have the following folders under it: designs, logs, and scripts. <br> Default is the assumption that the script is called from the openlane root.
+ </td>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--pdk | -p <PDK></code> <br> (Required)
+ </td>
+ <td align="justify">
+ The name of the PDK that the updated design(s) configuration belongs to.
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--std-cell-lib | -scl <STD_CELL_LIBRARY></code> <br> (Optional)
+ </td>
+ <td align="justify">
+ The name of the STD_CELL_LIBRARY that the updated design(s) configuration belongs to.
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--best_results | -b <csv file></code> <br> (Required)
+ </td>
+ <td align="justify">
+ This is the log file containing the best run for each design in a specific exploration. The log file will be used to determine the name of the configuration file to update from.
+ The csv file provided must one occurance of each design.
+ To tolerate custom log files, the script only exctracts the name of the design, its corresponding configuration file path, and whether the design passed or not by reading the flow_status. If there were more than one occurance of the same design, the last occurance will override others.
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--update_clock_period | -ucp</code> <br> (Boolean)
+ </td>
+ <td align="justify">
+ Specifies whether or not to update the CLOCK_PERIOD of the design based on the suggested_clock_period parameter.<br> Default value: <code>False</code>
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--clean | -cl</code> <br> (Boolean)
+ </td>
+ <td align="justify">
+ Specifies whether or not to delete the configuration file that the updated configuration file is updated from.<br> Default value: <code>False</code>
+ </td>
+ </tr>
+</table>
+
+**Note:** `update_designs_configs.py` skips designs that fail during the exploration, which means their flow_status is not `flow_completed`.
+
+**Important Note:** *The `update_designs_configs` script only copies new configuration to the file. The new configurations are marked with a preceeding "# Regression" comment that is automatically written before them by the exploration script. However, the `replicate_design_configs` script copies the whole file.*
+
+[1]: ../regression_results/README.md
+[2]: ../configuration/README.md
diff --git a/openlane/designs/aes/config.tcl b/openlane/designs/aes/config.tcl
new file mode 100755
index 0000000..39cda9f
--- /dev/null
+++ b/openlane/designs/aes/config.tcl
@@ -0,0 +1,17 @@
+
+# Design
+set ::env(DESIGN_NAME) "aes"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/aes.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(FP_CORE_UTIL) {15}
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/aes/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/aes/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..68c6523
--- /dev/null
+++ b/openlane/designs/aes/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "25"
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.25
diff --git a/openlane/designs/aes/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/aes/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..6b01c5d
--- /dev/null
+++ b/openlane/designs/aes/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,4 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "25.9"
diff --git a/openlane/designs/aes/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/aes/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..6b01c5d
--- /dev/null
+++ b/openlane/designs/aes/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,4 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "25.9"
diff --git a/openlane/designs/aes/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/aes/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..6b01c5d
--- /dev/null
+++ b/openlane/designs/aes/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,4 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "25.9"
diff --git a/openlane/designs/aes/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/aes/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..6b01c5d
--- /dev/null
+++ b/openlane/designs/aes/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,4 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 8
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(CLOCK_PERIOD) "25.9"
diff --git a/openlane/designs/aes/src/aes.v b/openlane/designs/aes/src/aes.v
new file mode 100644
index 0000000..b2c24ba
--- /dev/null
+++ b/openlane/designs/aes/src/aes.v
@@ -0,0 +1,2708 @@
+//======================================================================
+//
+// aes.v
+// --------
+// Top level wrapper for the AES block cipher core.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CTRL_ENCDEC_BIT = 0;
+ localparam CTRL_KEYLEN_BIT = 1;
+
+ localparam ADDR_KEY0 = 8'h10;
+ localparam ADDR_KEY7 = 8'h17;
+
+ localparam ADDR_BLOCK0 = 8'h20;
+ localparam ADDR_BLOCK3 = 8'h23;
+
+ localparam ADDR_RESULT0 = 8'h30;
+ localparam ADDR_RESULT3 = 8'h33;
+
+ localparam CORE_NAME0 = 32'h61657320; // "aes "
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_VERSION = 32'h302e3630; // "0.60"
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg init_reg;
+ reg init_new;
+
+ reg next_reg;
+ reg next_new;
+
+ reg encdec_reg;
+ reg keylen_reg;
+ reg config_we;
+
+ reg [31 : 0] block_reg [0 : 3];
+ reg block_we;
+
+ reg [31 : 0] key_reg [0 : 7];
+ reg key_we;
+
+ reg [127 : 0] result_reg;
+ reg valid_reg;
+ reg ready_reg;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_read_data;
+
+ wire core_encdec;
+ wire core_init;
+ wire core_next;
+ wire core_ready;
+ wire [255 : 0] core_key;
+ wire core_keylen;
+ wire [127 : 0] core_block;
+ wire [127 : 0] core_result;
+ wire core_valid;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+ assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
+ key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
+
+ assign core_block = {block_reg[0], block_reg[1],
+ block_reg[2], block_reg[3]};
+ assign core_init = init_reg;
+ assign core_next = next_reg;
+ assign core_encdec = encdec_reg;
+ assign core_keylen = keylen_reg;
+
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ aes_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .encdec(core_encdec),
+ .init(core_init),
+ .next(core_next),
+ .ready(core_ready),
+
+ .key(core_key),
+ .keylen(core_keylen),
+
+ .block(core_block),
+ .result(core_result),
+ .result_valid(core_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin : reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i < 4 ; i = i + 1)
+ block_reg[i] <= 32'h0;
+
+ for (i = 0 ; i < 8 ; i = i + 1)
+ key_reg[i] <= 32'h0;
+
+ init_reg <= 1'b0;
+ next_reg <= 1'b0;
+ encdec_reg <= 1'b0;
+ keylen_reg <= 1'b0;
+
+ result_reg <= 128'h0;
+ valid_reg <= 1'b0;
+ ready_reg <= 1'b0;
+ end
+ else
+ begin
+ ready_reg <= core_ready;
+ valid_reg <= core_valid;
+ result_reg <= core_result;
+ init_reg <= init_new;
+ next_reg <= next_new;
+
+ if (config_we)
+ begin
+ encdec_reg <= write_data[CTRL_ENCDEC_BIT];
+ keylen_reg <= write_data[CTRL_KEYLEN_BIT];
+ end
+
+ if (key_we)
+ key_reg[address[2 : 0]] <= write_data;
+
+ if (block_we)
+ block_reg[address[1 : 0]] <= write_data;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // api
+ //
+ // The interface command decoding logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : api
+ init_new = 1'b0;
+ next_new = 1'b0;
+ config_we = 1'b0;
+ key_we = 1'b0;
+ block_we = 1'b0;
+ tmp_read_data = 32'h0;
+
+ if (cs)
+ begin
+ if (we)
+ begin
+ if (address == ADDR_CTRL)
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
+
+ if (address == ADDR_CONFIG)
+ config_we = 1'b1;
+
+ if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+ key_we = 1'b1;
+
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+ block_we = 1'b1;
+ end // if (we)
+
+ else
+ begin
+ case (address)
+ ADDR_NAME0: tmp_read_data = CORE_NAME0;
+ ADDR_NAME1: tmp_read_data = CORE_NAME1;
+ ADDR_VERSION: tmp_read_data = CORE_VERSION;
+ ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+ ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
+
+ default:
+ begin
+ end
+ endcase // case (address)
+
+ if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
+ tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
+ end
+ end
+ end // addr_decoder
+endmodule // aes
+
+//======================================================================
+// EOF aes.v
+//======================================================================
+
+
+//======================================================================
+//
+// aes.core.v
+// ----------
+// The AES core. This core supports key size of 128, and 256 bits.
+// Most of the functionality is within the submodules.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_core(
+ input wire clk,
+ input wire reset_n,
+
+ input wire encdec,
+ input wire init,
+ input wire next,
+ output wire ready,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] result,
+ output wire result_valid
+ );
+
+
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam CTRL_IDLE = 2'h0;
+ localparam CTRL_INIT = 2'h1;
+ localparam CTRL_NEXT = 2'h2;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] aes_core_ctrl_reg;
+ reg [1 : 0] aes_core_ctrl_new;
+ reg aes_core_ctrl_we;
+
+ reg result_valid_reg;
+ reg result_valid_new;
+ reg result_valid_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg init_state;
+
+ wire [127 : 0] round_key;
+ wire key_ready;
+
+ reg enc_next;
+ wire [3 : 0] enc_round_nr;
+ wire [127 : 0] enc_new_block;
+ wire enc_ready;
+ wire [31 : 0] enc_sboxw;
+
+ reg dec_next;
+ wire [3 : 0] dec_round_nr;
+ wire [127 : 0] dec_new_block;
+ wire dec_ready;
+
+ reg [127 : 0] muxed_new_block;
+ reg [3 : 0] muxed_round_nr;
+ reg muxed_ready;
+
+ wire [31 : 0] keymem_sboxw;
+
+ reg [31 : 0] muxed_sboxw;
+ wire [31 : 0] new_sboxw;
+
+
+ //----------------------------------------------------------------
+ // Instantiations.
+ //----------------------------------------------------------------
+ aes_encipher_block enc_block(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .next(enc_next),
+
+ .keylen(keylen),
+ .round(enc_round_nr),
+ .round_key(round_key),
+
+ .sboxw(enc_sboxw),
+ .new_sboxw(new_sboxw),
+
+ .block(block),
+ .new_block(enc_new_block),
+ .ready(enc_ready)
+ );
+
+
+ aes_decipher_block dec_block(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .next(dec_next),
+
+ .keylen(keylen),
+ .round(dec_round_nr),
+ .round_key(round_key),
+
+ .block(block),
+ .new_block(dec_new_block),
+ .ready(dec_ready)
+ );
+
+
+ aes_key_mem keymem(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .key(key),
+ .keylen(keylen),
+ .init(init),
+
+ .round(muxed_round_nr),
+ .round_key(round_key),
+ .ready(key_ready),
+
+ .sboxw(keymem_sboxw),
+ .new_sboxw(new_sboxw)
+ );
+
+
+ aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign ready = ready_reg;
+ assign result = muxed_new_block;
+ assign result_valid = result_valid_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ result_valid_reg <= 1'b0;
+ ready_reg <= 1'b1;
+ aes_core_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (result_valid_we)
+ result_valid_reg <= result_valid_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (aes_core_ctrl_we)
+ aes_core_ctrl_reg <= aes_core_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // sbox_mux
+ //
+ // Controls which of the encipher datapath or the key memory
+ // that gets access to the sbox.
+ //----------------------------------------------------------------
+ always @*
+ begin : sbox_mux
+ if (init_state)
+ begin
+ muxed_sboxw = keymem_sboxw;
+ end
+ else
+ begin
+ muxed_sboxw = enc_sboxw;
+ end
+ end // sbox_mux
+
+
+ //----------------------------------------------------------------
+ // encdex_mux
+ //
+ // Controls which of the datapaths that get the next signal, have
+ // access to the memory as well as the block processing result.
+ //----------------------------------------------------------------
+ always @*
+ begin : encdec_mux
+ enc_next = 1'b0;
+ dec_next = 1'b0;
+
+ if (encdec)
+ begin
+ // Encipher operations
+ enc_next = next;
+ muxed_round_nr = enc_round_nr;
+ muxed_new_block = enc_new_block;
+ muxed_ready = enc_ready;
+ end
+ else
+ begin
+ // Decipher operations
+ dec_next = next;
+ muxed_round_nr = dec_round_nr;
+ muxed_new_block = dec_new_block;
+ muxed_ready = dec_ready;
+ end
+ end // encdec_mux
+
+
+ //----------------------------------------------------------------
+ // aes_core_ctrl
+ //
+ // Control FSM for aes core. Basically tracks if we are in
+ // key init, encipher or decipher modes and connects the
+ // different submodules to shared resources and interface ports.
+ //----------------------------------------------------------------
+ always @*
+ begin : aes_core_ctrl
+ init_state = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b0;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b0;
+
+ case (aes_core_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ init_state = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_INIT;
+ aes_core_ctrl_we = 1'b1;
+ end
+ else if (next)
+ begin
+ init_state = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_NEXT;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ init_state = 1'b1;
+
+ if (key_ready)
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_NEXT:
+ begin
+ init_state = 1'b0;
+
+ if (muxed_ready)
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ result_valid_new = 1'b1;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+
+ end
+ endcase // case (aes_core_ctrl_reg)
+
+ end // aes_core_ctrl
+endmodule // aes_core
+
+//======================================================================
+// EOF aes_core.v
+//======================================================================
+
+//======================================================================
+//
+// aes_decipher_block.v
+// --------------------
+// The AES decipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// decciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_decipher_block(
+ input wire clk,
+ input wire reset_n,
+
+ input wire next,
+
+ input wire keylen,
+ output wire [3 : 0] round,
+ input wire [127 : 0] round_key,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] new_block,
+ output wire ready
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES128_ROUNDS = 4'ha;
+ localparam AES256_ROUNDS = 4'he;
+
+ localparam NO_UPDATE = 3'h0;
+ localparam INIT_UPDATE = 3'h1;
+ localparam SBOX_UPDATE = 3'h2;
+ localparam MAIN_UPDATE = 3'h3;
+ localparam FINAL_UPDATE = 3'h4;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_SBOX = 3'h2;
+ localparam CTRL_MAIN = 3'h3;
+ localparam CTRL_FINAL = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Gaolis multiplication functions for Inverse MixColumn.
+ //----------------------------------------------------------------
+ function [7 : 0] gm2(input [7 : 0] op);
+ begin
+ gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+ end
+ endfunction // gm2
+
+ function [7 : 0] gm3(input [7 : 0] op);
+ begin
+ gm3 = gm2(op) ^ op;
+ end
+ endfunction // gm3
+
+ function [7 : 0] gm4(input [7 : 0] op);
+ begin
+ gm4 = gm2(gm2(op));
+ end
+ endfunction // gm4
+
+ function [7 : 0] gm8(input [7 : 0] op);
+ begin
+ gm8 = gm2(gm4(op));
+ end
+ endfunction // gm8
+
+ function [7 : 0] gm09(input [7 : 0] op);
+ begin
+ gm09 = gm8(op) ^ op;
+ end
+ endfunction // gm09
+
+ function [7 : 0] gm11(input [7 : 0] op);
+ begin
+ gm11 = gm8(op) ^ gm2(op) ^ op;
+ end
+ endfunction // gm11
+
+ function [7 : 0] gm13(input [7 : 0] op);
+ begin
+ gm13 = gm8(op) ^ gm4(op) ^ op;
+ end
+ endfunction // gm13
+
+ function [7 : 0] gm14(input [7 : 0] op);
+ begin
+ gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
+ end
+ endfunction // gm14
+
+ function [31 : 0] inv_mixw(input [31 : 0] w);
+ reg [7 : 0] b0, b1, b2, b3;
+ reg [7 : 0] mb0, mb1, mb2, mb3;
+ begin
+ b0 = w[31 : 24];
+ b1 = w[23 : 16];
+ b2 = w[15 : 08];
+ b3 = w[07 : 00];
+
+ mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
+ mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
+ mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
+ mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
+
+ inv_mixw = {mb0, mb1, mb2, mb3};
+ end
+ endfunction // mixw
+
+ function [127 : 0] inv_mixcolumns(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = inv_mixw(w0);
+ ws1 = inv_mixw(w1);
+ ws2 = inv_mixw(w2);
+ ws3 = inv_mixw(w3);
+
+ inv_mixcolumns = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // inv_mixcolumns
+
+ function [127 : 0] inv_shiftrows(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
+ ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
+ ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
+ ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
+
+ inv_shiftrows = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // inv_shiftrows
+
+ function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+ begin
+ addroundkey = data ^ rkey;
+ end
+ endfunction // addroundkey
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] sword_ctr_reg;
+ reg [1 : 0] sword_ctr_new;
+ reg sword_ctr_we;
+ reg sword_ctr_inc;
+ reg sword_ctr_rst;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_we;
+ reg round_ctr_set;
+ reg round_ctr_dec;
+
+ reg [127 : 0] block_new;
+ reg [31 : 0] block_w0_reg;
+ reg [31 : 0] block_w1_reg;
+ reg [31 : 0] block_w2_reg;
+ reg [31 : 0] block_w3_reg;
+ reg block_w0_we;
+ reg block_w1_we;
+ reg block_w2_we;
+ reg block_w3_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] dec_ctrl_reg;
+ reg [2 : 0] dec_ctrl_new;
+ reg dec_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_sboxw;
+ wire [31 : 0] new_sboxw;
+ reg [2 : 0] update_type;
+
+
+ //----------------------------------------------------------------
+ // Instantiations.
+ //----------------------------------------------------------------
+ aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign round = round_ctr_reg;
+ assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with synchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ block_w0_reg <= 32'h0;
+ block_w1_reg <= 32'h0;
+ block_w2_reg <= 32'h0;
+ block_w3_reg <= 32'h0;
+ sword_ctr_reg <= 2'h0;
+ round_ctr_reg <= 4'h0;
+ ready_reg <= 1'b1;
+ dec_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (block_w0_we)
+ block_w0_reg <= block_new[127 : 096];
+
+ if (block_w1_we)
+ block_w1_reg <= block_new[095 : 064];
+
+ if (block_w2_we)
+ block_w2_reg <= block_new[063 : 032];
+
+ if (block_w3_we)
+ block_w3_reg <= block_new[031 : 000];
+
+ if (sword_ctr_we)
+ sword_ctr_reg <= sword_ctr_new;
+
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (dec_ctrl_we)
+ dec_ctrl_reg <= dec_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // round_logic
+ //
+ // The logic needed to implement init, main and final rounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_logic
+ reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
+ reg [127 : 0] addkey_block;
+
+ inv_shiftrows_block = 128'h0;
+ inv_mixcolumns_block = 128'h0;
+ addkey_block = 128'h0;
+ block_new = 128'h0;
+ tmp_sboxw = 32'h0;
+ block_w0_we = 1'b0;
+ block_w1_we = 1'b0;
+ block_w2_we = 1'b0;
+ block_w3_we = 1'b0;
+
+ old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+
+ // Update based on update type.
+ case (update_type)
+ // InitRound
+ INIT_UPDATE:
+ begin
+ old_block = block;
+ addkey_block = addroundkey(old_block, round_key);
+ inv_shiftrows_block = inv_shiftrows(addkey_block);
+ block_new = inv_shiftrows_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ SBOX_UPDATE:
+ begin
+ block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+ case (sword_ctr_reg)
+ 2'h0:
+ begin
+ tmp_sboxw = block_w0_reg;
+ block_w0_we = 1'b1;
+ end
+
+ 2'h1:
+ begin
+ tmp_sboxw = block_w1_reg;
+ block_w1_we = 1'b1;
+ end
+
+ 2'h2:
+ begin
+ tmp_sboxw = block_w2_reg;
+ block_w2_we = 1'b1;
+ end
+
+ 2'h3:
+ begin
+ tmp_sboxw = block_w3_reg;
+ block_w3_we = 1'b1;
+ end
+ endcase // case (sbox_mux_ctrl_reg)
+ end
+
+ MAIN_UPDATE:
+ begin
+ addkey_block = addroundkey(old_block, round_key);
+ inv_mixcolumns_block = inv_mixcolumns(addkey_block);
+ inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
+ block_new = inv_shiftrows_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ FINAL_UPDATE:
+ begin
+ block_new = addroundkey(old_block, round_key);
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (update_type)
+ end // round_logic
+
+
+ //----------------------------------------------------------------
+ // sword_ctr
+ //
+ // The subbytes word counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : sword_ctr
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b0;
+
+ if (sword_ctr_rst)
+ begin
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b1;
+ end
+ else if (sword_ctr_inc)
+ begin
+ sword_ctr_new = sword_ctr_reg + 1'b1;
+ sword_ctr_we = 1'b1;
+ end
+ end // sword_ctr
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_set)
+ begin
+ if (keylen == AES_256_BIT_KEY)
+ begin
+ round_ctr_new = AES256_ROUNDS;
+ end
+ else
+ begin
+ round_ctr_new = AES128_ROUNDS;
+ end
+ round_ctr_we = 1'b1;
+ end
+ else if (round_ctr_dec)
+ begin
+ round_ctr_new = round_ctr_reg - 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end // round_ctr
+
+
+ //----------------------------------------------------------------
+ // decipher_ctrl
+ //
+ // The FSM that controls the decipher operations.
+ //----------------------------------------------------------------
+ always @*
+ begin: decipher_ctrl
+ sword_ctr_inc = 1'b0;
+ sword_ctr_rst = 1'b0;
+ round_ctr_dec = 1'b0;
+ round_ctr_set = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ update_type = NO_UPDATE;
+ dec_ctrl_new = CTRL_IDLE;
+ dec_ctrl_we = 1'b0;
+
+ case(dec_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (next)
+ begin
+ round_ctr_set = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ dec_ctrl_new = CTRL_INIT;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ sword_ctr_rst = 1'b1;
+ update_type = INIT_UPDATE;
+ dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_we = 1'b1;
+ end
+
+ CTRL_SBOX:
+ begin
+ sword_ctr_inc = 1'b1;
+ update_type = SBOX_UPDATE;
+ if (sword_ctr_reg == 2'h3)
+ begin
+ round_ctr_dec = 1'b1;
+ dec_ctrl_new = CTRL_MAIN;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_MAIN:
+ begin
+ sword_ctr_rst = 1'b1;
+ if (round_ctr_reg > 0)
+ begin
+ update_type = MAIN_UPDATE;
+ dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_we = 1'b1;
+ end
+ else
+ begin
+ update_type = FINAL_UPDATE;
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ dec_ctrl_new = CTRL_IDLE;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ // Empty. Just here to make the synthesis tool happy.
+ end
+ endcase // case (dec_ctrl_reg)
+ end // decipher_ctrl
+
+endmodule // aes_decipher_block
+
+//======================================================================
+// EOF aes_decipher_block.v
+//======================================================================
+
+//======================================================================
+//
+// aes_inv_sbox.v
+// --------------
+// The inverse AES S-box. Basically a 256 Byte ROM.
+//
+//
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_inv_sbox(
+ input wire [31 : 0] sword,
+ output wire [31 : 0] new_sword
+ );
+
+
+ //----------------------------------------------------------------
+ // The inverse sbox array.
+ //----------------------------------------------------------------
+ wire [7 : 0] inv_sbox [0 : 255];
+
+
+ //----------------------------------------------------------------
+ // Four parallel muxes.
+ //----------------------------------------------------------------
+ assign new_sword[31 : 24] = inv_sbox[sword[31 : 24]];
+ assign new_sword[23 : 16] = inv_sbox[sword[23 : 16]];
+ assign new_sword[15 : 08] = inv_sbox[sword[15 : 08]];
+ assign new_sword[07 : 00] = inv_sbox[sword[07 : 00]];
+
+
+ //----------------------------------------------------------------
+ // Creating the contents of the array.
+ //----------------------------------------------------------------
+ assign inv_sbox[8'h00] = 8'h52;
+ assign inv_sbox[8'h01] = 8'h09;
+ assign inv_sbox[8'h02] = 8'h6a;
+ assign inv_sbox[8'h03] = 8'hd5;
+ assign inv_sbox[8'h04] = 8'h30;
+ assign inv_sbox[8'h05] = 8'h36;
+ assign inv_sbox[8'h06] = 8'ha5;
+ assign inv_sbox[8'h07] = 8'h38;
+ assign inv_sbox[8'h08] = 8'hbf;
+ assign inv_sbox[8'h09] = 8'h40;
+ assign inv_sbox[8'h0a] = 8'ha3;
+ assign inv_sbox[8'h0b] = 8'h9e;
+ assign inv_sbox[8'h0c] = 8'h81;
+ assign inv_sbox[8'h0d] = 8'hf3;
+ assign inv_sbox[8'h0e] = 8'hd7;
+ assign inv_sbox[8'h0f] = 8'hfb;
+ assign inv_sbox[8'h10] = 8'h7c;
+ assign inv_sbox[8'h11] = 8'he3;
+ assign inv_sbox[8'h12] = 8'h39;
+ assign inv_sbox[8'h13] = 8'h82;
+ assign inv_sbox[8'h14] = 8'h9b;
+ assign inv_sbox[8'h15] = 8'h2f;
+ assign inv_sbox[8'h16] = 8'hff;
+ assign inv_sbox[8'h17] = 8'h87;
+ assign inv_sbox[8'h18] = 8'h34;
+ assign inv_sbox[8'h19] = 8'h8e;
+ assign inv_sbox[8'h1a] = 8'h43;
+ assign inv_sbox[8'h1b] = 8'h44;
+ assign inv_sbox[8'h1c] = 8'hc4;
+ assign inv_sbox[8'h1d] = 8'hde;
+ assign inv_sbox[8'h1e] = 8'he9;
+ assign inv_sbox[8'h1f] = 8'hcb;
+ assign inv_sbox[8'h20] = 8'h54;
+ assign inv_sbox[8'h21] = 8'h7b;
+ assign inv_sbox[8'h22] = 8'h94;
+ assign inv_sbox[8'h23] = 8'h32;
+ assign inv_sbox[8'h24] = 8'ha6;
+ assign inv_sbox[8'h25] = 8'hc2;
+ assign inv_sbox[8'h26] = 8'h23;
+ assign inv_sbox[8'h27] = 8'h3d;
+ assign inv_sbox[8'h28] = 8'hee;
+ assign inv_sbox[8'h29] = 8'h4c;
+ assign inv_sbox[8'h2a] = 8'h95;
+ assign inv_sbox[8'h2b] = 8'h0b;
+ assign inv_sbox[8'h2c] = 8'h42;
+ assign inv_sbox[8'h2d] = 8'hfa;
+ assign inv_sbox[8'h2e] = 8'hc3;
+ assign inv_sbox[8'h2f] = 8'h4e;
+ assign inv_sbox[8'h30] = 8'h08;
+ assign inv_sbox[8'h31] = 8'h2e;
+ assign inv_sbox[8'h32] = 8'ha1;
+ assign inv_sbox[8'h33] = 8'h66;
+ assign inv_sbox[8'h34] = 8'h28;
+ assign inv_sbox[8'h35] = 8'hd9;
+ assign inv_sbox[8'h36] = 8'h24;
+ assign inv_sbox[8'h37] = 8'hb2;
+ assign inv_sbox[8'h38] = 8'h76;
+ assign inv_sbox[8'h39] = 8'h5b;
+ assign inv_sbox[8'h3a] = 8'ha2;
+ assign inv_sbox[8'h3b] = 8'h49;
+ assign inv_sbox[8'h3c] = 8'h6d;
+ assign inv_sbox[8'h3d] = 8'h8b;
+ assign inv_sbox[8'h3e] = 8'hd1;
+ assign inv_sbox[8'h3f] = 8'h25;
+ assign inv_sbox[8'h40] = 8'h72;
+ assign inv_sbox[8'h41] = 8'hf8;
+ assign inv_sbox[8'h42] = 8'hf6;
+ assign inv_sbox[8'h43] = 8'h64;
+ assign inv_sbox[8'h44] = 8'h86;
+ assign inv_sbox[8'h45] = 8'h68;
+ assign inv_sbox[8'h46] = 8'h98;
+ assign inv_sbox[8'h47] = 8'h16;
+ assign inv_sbox[8'h48] = 8'hd4;
+ assign inv_sbox[8'h49] = 8'ha4;
+ assign inv_sbox[8'h4a] = 8'h5c;
+ assign inv_sbox[8'h4b] = 8'hcc;
+ assign inv_sbox[8'h4c] = 8'h5d;
+ assign inv_sbox[8'h4d] = 8'h65;
+ assign inv_sbox[8'h4e] = 8'hb6;
+ assign inv_sbox[8'h4f] = 8'h92;
+ assign inv_sbox[8'h50] = 8'h6c;
+ assign inv_sbox[8'h51] = 8'h70;
+ assign inv_sbox[8'h52] = 8'h48;
+ assign inv_sbox[8'h53] = 8'h50;
+ assign inv_sbox[8'h54] = 8'hfd;
+ assign inv_sbox[8'h55] = 8'hed;
+ assign inv_sbox[8'h56] = 8'hb9;
+ assign inv_sbox[8'h57] = 8'hda;
+ assign inv_sbox[8'h58] = 8'h5e;
+ assign inv_sbox[8'h59] = 8'h15;
+ assign inv_sbox[8'h5a] = 8'h46;
+ assign inv_sbox[8'h5b] = 8'h57;
+ assign inv_sbox[8'h5c] = 8'ha7;
+ assign inv_sbox[8'h5d] = 8'h8d;
+ assign inv_sbox[8'h5e] = 8'h9d;
+ assign inv_sbox[8'h5f] = 8'h84;
+ assign inv_sbox[8'h60] = 8'h90;
+ assign inv_sbox[8'h61] = 8'hd8;
+ assign inv_sbox[8'h62] = 8'hab;
+ assign inv_sbox[8'h63] = 8'h00;
+ assign inv_sbox[8'h64] = 8'h8c;
+ assign inv_sbox[8'h65] = 8'hbc;
+ assign inv_sbox[8'h66] = 8'hd3;
+ assign inv_sbox[8'h67] = 8'h0a;
+ assign inv_sbox[8'h68] = 8'hf7;
+ assign inv_sbox[8'h69] = 8'he4;
+ assign inv_sbox[8'h6a] = 8'h58;
+ assign inv_sbox[8'h6b] = 8'h05;
+ assign inv_sbox[8'h6c] = 8'hb8;
+ assign inv_sbox[8'h6d] = 8'hb3;
+ assign inv_sbox[8'h6e] = 8'h45;
+ assign inv_sbox[8'h6f] = 8'h06;
+ assign inv_sbox[8'h70] = 8'hd0;
+ assign inv_sbox[8'h71] = 8'h2c;
+ assign inv_sbox[8'h72] = 8'h1e;
+ assign inv_sbox[8'h73] = 8'h8f;
+ assign inv_sbox[8'h74] = 8'hca;
+ assign inv_sbox[8'h75] = 8'h3f;
+ assign inv_sbox[8'h76] = 8'h0f;
+ assign inv_sbox[8'h77] = 8'h02;
+ assign inv_sbox[8'h78] = 8'hc1;
+ assign inv_sbox[8'h79] = 8'haf;
+ assign inv_sbox[8'h7a] = 8'hbd;
+ assign inv_sbox[8'h7b] = 8'h03;
+ assign inv_sbox[8'h7c] = 8'h01;
+ assign inv_sbox[8'h7d] = 8'h13;
+ assign inv_sbox[8'h7e] = 8'h8a;
+ assign inv_sbox[8'h7f] = 8'h6b;
+ assign inv_sbox[8'h80] = 8'h3a;
+ assign inv_sbox[8'h81] = 8'h91;
+ assign inv_sbox[8'h82] = 8'h11;
+ assign inv_sbox[8'h83] = 8'h41;
+ assign inv_sbox[8'h84] = 8'h4f;
+ assign inv_sbox[8'h85] = 8'h67;
+ assign inv_sbox[8'h86] = 8'hdc;
+ assign inv_sbox[8'h87] = 8'hea;
+ assign inv_sbox[8'h88] = 8'h97;
+ assign inv_sbox[8'h89] = 8'hf2;
+ assign inv_sbox[8'h8a] = 8'hcf;
+ assign inv_sbox[8'h8b] = 8'hce;
+ assign inv_sbox[8'h8c] = 8'hf0;
+ assign inv_sbox[8'h8d] = 8'hb4;
+ assign inv_sbox[8'h8e] = 8'he6;
+ assign inv_sbox[8'h8f] = 8'h73;
+ assign inv_sbox[8'h90] = 8'h96;
+ assign inv_sbox[8'h91] = 8'hac;
+ assign inv_sbox[8'h92] = 8'h74;
+ assign inv_sbox[8'h93] = 8'h22;
+ assign inv_sbox[8'h94] = 8'he7;
+ assign inv_sbox[8'h95] = 8'had;
+ assign inv_sbox[8'h96] = 8'h35;
+ assign inv_sbox[8'h97] = 8'h85;
+ assign inv_sbox[8'h98] = 8'he2;
+ assign inv_sbox[8'h99] = 8'hf9;
+ assign inv_sbox[8'h9a] = 8'h37;
+ assign inv_sbox[8'h9b] = 8'he8;
+ assign inv_sbox[8'h9c] = 8'h1c;
+ assign inv_sbox[8'h9d] = 8'h75;
+ assign inv_sbox[8'h9e] = 8'hdf;
+ assign inv_sbox[8'h9f] = 8'h6e;
+ assign inv_sbox[8'ha0] = 8'h47;
+ assign inv_sbox[8'ha1] = 8'hf1;
+ assign inv_sbox[8'ha2] = 8'h1a;
+ assign inv_sbox[8'ha3] = 8'h71;
+ assign inv_sbox[8'ha4] = 8'h1d;
+ assign inv_sbox[8'ha5] = 8'h29;
+ assign inv_sbox[8'ha6] = 8'hc5;
+ assign inv_sbox[8'ha7] = 8'h89;
+ assign inv_sbox[8'ha8] = 8'h6f;
+ assign inv_sbox[8'ha9] = 8'hb7;
+ assign inv_sbox[8'haa] = 8'h62;
+ assign inv_sbox[8'hab] = 8'h0e;
+ assign inv_sbox[8'hac] = 8'haa;
+ assign inv_sbox[8'had] = 8'h18;
+ assign inv_sbox[8'hae] = 8'hbe;
+ assign inv_sbox[8'haf] = 8'h1b;
+ assign inv_sbox[8'hb0] = 8'hfc;
+ assign inv_sbox[8'hb1] = 8'h56;
+ assign inv_sbox[8'hb2] = 8'h3e;
+ assign inv_sbox[8'hb3] = 8'h4b;
+ assign inv_sbox[8'hb4] = 8'hc6;
+ assign inv_sbox[8'hb5] = 8'hd2;
+ assign inv_sbox[8'hb6] = 8'h79;
+ assign inv_sbox[8'hb7] = 8'h20;
+ assign inv_sbox[8'hb8] = 8'h9a;
+ assign inv_sbox[8'hb9] = 8'hdb;
+ assign inv_sbox[8'hba] = 8'hc0;
+ assign inv_sbox[8'hbb] = 8'hfe;
+ assign inv_sbox[8'hbc] = 8'h78;
+ assign inv_sbox[8'hbd] = 8'hcd;
+ assign inv_sbox[8'hbe] = 8'h5a;
+ assign inv_sbox[8'hbf] = 8'hf4;
+ assign inv_sbox[8'hc0] = 8'h1f;
+ assign inv_sbox[8'hc1] = 8'hdd;
+ assign inv_sbox[8'hc2] = 8'ha8;
+ assign inv_sbox[8'hc3] = 8'h33;
+ assign inv_sbox[8'hc4] = 8'h88;
+ assign inv_sbox[8'hc5] = 8'h07;
+ assign inv_sbox[8'hc6] = 8'hc7;
+ assign inv_sbox[8'hc7] = 8'h31;
+ assign inv_sbox[8'hc8] = 8'hb1;
+ assign inv_sbox[8'hc9] = 8'h12;
+ assign inv_sbox[8'hca] = 8'h10;
+ assign inv_sbox[8'hcb] = 8'h59;
+ assign inv_sbox[8'hcc] = 8'h27;
+ assign inv_sbox[8'hcd] = 8'h80;
+ assign inv_sbox[8'hce] = 8'hec;
+ assign inv_sbox[8'hcf] = 8'h5f;
+ assign inv_sbox[8'hd0] = 8'h60;
+ assign inv_sbox[8'hd1] = 8'h51;
+ assign inv_sbox[8'hd2] = 8'h7f;
+ assign inv_sbox[8'hd3] = 8'ha9;
+ assign inv_sbox[8'hd4] = 8'h19;
+ assign inv_sbox[8'hd5] = 8'hb5;
+ assign inv_sbox[8'hd6] = 8'h4a;
+ assign inv_sbox[8'hd7] = 8'h0d;
+ assign inv_sbox[8'hd8] = 8'h2d;
+ assign inv_sbox[8'hd9] = 8'he5;
+ assign inv_sbox[8'hda] = 8'h7a;
+ assign inv_sbox[8'hdb] = 8'h9f;
+ assign inv_sbox[8'hdc] = 8'h93;
+ assign inv_sbox[8'hdd] = 8'hc9;
+ assign inv_sbox[8'hde] = 8'h9c;
+ assign inv_sbox[8'hdf] = 8'hef;
+ assign inv_sbox[8'he0] = 8'ha0;
+ assign inv_sbox[8'he1] = 8'he0;
+ assign inv_sbox[8'he2] = 8'h3b;
+ assign inv_sbox[8'he3] = 8'h4d;
+ assign inv_sbox[8'he4] = 8'hae;
+ assign inv_sbox[8'he5] = 8'h2a;
+ assign inv_sbox[8'he6] = 8'hf5;
+ assign inv_sbox[8'he7] = 8'hb0;
+ assign inv_sbox[8'he8] = 8'hc8;
+ assign inv_sbox[8'he9] = 8'heb;
+ assign inv_sbox[8'hea] = 8'hbb;
+ assign inv_sbox[8'heb] = 8'h3c;
+ assign inv_sbox[8'hec] = 8'h83;
+ assign inv_sbox[8'hed] = 8'h53;
+ assign inv_sbox[8'hee] = 8'h99;
+ assign inv_sbox[8'hef] = 8'h61;
+ assign inv_sbox[8'hf0] = 8'h17;
+ assign inv_sbox[8'hf1] = 8'h2b;
+ assign inv_sbox[8'hf2] = 8'h04;
+ assign inv_sbox[8'hf3] = 8'h7e;
+ assign inv_sbox[8'hf4] = 8'hba;
+ assign inv_sbox[8'hf5] = 8'h77;
+ assign inv_sbox[8'hf6] = 8'hd6;
+ assign inv_sbox[8'hf7] = 8'h26;
+ assign inv_sbox[8'hf8] = 8'he1;
+ assign inv_sbox[8'hf9] = 8'h69;
+ assign inv_sbox[8'hfa] = 8'h14;
+ assign inv_sbox[8'hfb] = 8'h63;
+ assign inv_sbox[8'hfc] = 8'h55;
+ assign inv_sbox[8'hfd] = 8'h21;
+ assign inv_sbox[8'hfe] = 8'h0c;
+ assign inv_sbox[8'hff] = 8'h7d;
+
+endmodule // aes_inv_sbox
+
+//======================================================================
+// EOF aes_inv_sbox.v
+//======================================================================
+
+
+//======================================================================
+//
+// aes_key_mem.v
+// -------------
+// The AES key memory including round key generator.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_key_mem(
+ input wire clk,
+ input wire reset_n,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+ input wire init,
+
+ input wire [3 : 0] round,
+ output wire [127 : 0] round_key,
+ output wire ready,
+
+
+ output wire [31 : 0] sboxw,
+ input wire [31 : 0] new_sboxw
+ );
+
+
+ //----------------------------------------------------------------
+ // Parameters.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES_128_NUM_ROUNDS = 10;
+ localparam AES_256_NUM_ROUNDS = 14;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_GENERATE = 3'h2;
+ localparam CTRL_DONE = 3'h3;
+
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [127 : 0] key_mem [0 : 14];
+ reg [127 : 0] key_mem_new;
+ reg key_mem_we;
+
+ reg [127 : 0] prev_key0_reg;
+ reg [127 : 0] prev_key0_new;
+ reg prev_key0_we;
+
+ reg [127 : 0] prev_key1_reg;
+ reg [127 : 0] prev_key1_new;
+ reg prev_key1_we;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_rst;
+ reg round_ctr_inc;
+ reg round_ctr_we;
+
+ reg [2 : 0] key_mem_ctrl_reg;
+ reg [2 : 0] key_mem_ctrl_new;
+ reg key_mem_ctrl_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [7 : 0] rcon_reg;
+ reg [7 : 0] rcon_new;
+ reg rcon_we;
+ reg rcon_set;
+ reg rcon_next;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_sboxw;
+ reg round_key_update;
+ reg [127 : 0] tmp_round_key;
+
+
+ //----------------------------------------------------------------
+ // Concurrent assignments for ports.
+ //----------------------------------------------------------------
+ assign round_key = tmp_round_key;
+ assign ready = ready_reg;
+ assign sboxw = tmp_sboxw;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i <= AES_256_NUM_ROUNDS ; i = i + 1)
+ key_mem [i] <= 128'h0;
+
+ rcon_reg <= 8'h0;
+ ready_reg <= 1'b0;
+ round_ctr_reg <= 4'h0;
+ key_mem_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (rcon_we)
+ rcon_reg <= rcon_new;
+
+ if (key_mem_we)
+ key_mem[round_ctr_reg] <= key_mem_new;
+
+ if (prev_key0_we)
+ prev_key0_reg <= prev_key0_new;
+
+ if (prev_key1_we)
+ prev_key1_reg <= prev_key1_new;
+
+ if (key_mem_ctrl_we)
+ key_mem_ctrl_reg <= key_mem_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // key_mem_read
+ //
+ // Combinational read port for the key memory.
+ //----------------------------------------------------------------
+ always @*
+ begin : key_mem_read
+ tmp_round_key = key_mem[round];
+ end // key_mem_read
+
+
+ //----------------------------------------------------------------
+ // round_key_gen
+ //
+ // The round key generator logic for AES-128 and AES-256.
+ //----------------------------------------------------------------
+ always @*
+ begin: round_key_gen
+ reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
+ reg [31 : 0] k0, k1, k2, k3;
+ reg [31 : 0] rconw, rotstw, tw, trw;
+
+ // Default assignments.
+ key_mem_new = 128'h0;
+ key_mem_we = 1'b0;
+ prev_key0_new = 128'h0;
+ prev_key0_we = 1'b0;
+ prev_key1_new = 128'h0;
+ prev_key1_we = 1'b0;
+
+ k0 = 32'h0;
+ k1 = 32'h0;
+ k2 = 32'h0;
+ k3 = 32'h0;
+
+ rcon_set = 1'b1;
+ rcon_next = 1'b0;
+
+ // Extract words and calculate intermediate values.
+ // Perform rotation of sbox word etc.
+ w0 = prev_key0_reg[127 : 096];
+ w1 = prev_key0_reg[095 : 064];
+ w2 = prev_key0_reg[063 : 032];
+ w3 = prev_key0_reg[031 : 000];
+
+ w4 = prev_key1_reg[127 : 096];
+ w5 = prev_key1_reg[095 : 064];
+ w6 = prev_key1_reg[063 : 032];
+ w7 = prev_key1_reg[031 : 000];
+
+ rconw = {rcon_reg, 24'h0};
+ tmp_sboxw = w7;
+ rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
+ trw = rotstw ^ rconw;
+ tw = new_sboxw;
+
+ // Generate the specific round keys.
+ if (round_key_update)
+ begin
+ rcon_set = 1'b0;
+ key_mem_we = 1'b1;
+ case (keylen)
+ AES_128_BIT_KEY:
+ begin
+ if (round_ctr_reg == 0)
+ begin
+ key_mem_new = key[255 : 128];
+ prev_key1_new = key[255 : 128];
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ else
+ begin
+ k0 = w4 ^ trw;
+ k1 = w5 ^ w4 ^ trw;
+ k2 = w6 ^ w5 ^ w4 ^ trw;
+ k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
+
+ key_mem_new = {k0, k1, k2, k3};
+ prev_key1_new = {k0, k1, k2, k3};
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ end
+
+ AES_256_BIT_KEY:
+ begin
+ if (round_ctr_reg == 0)
+ begin
+ key_mem_new = key[255 : 128];
+ prev_key0_new = key[255 : 128];
+ prev_key0_we = 1'b1;
+ end
+ else if (round_ctr_reg == 1)
+ begin
+ key_mem_new = key[127 : 0];
+ prev_key1_new = key[127 : 0];
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ else
+ begin
+ if (round_ctr_reg[0] == 0)
+ begin
+ k0 = w0 ^ trw;
+ k1 = w1 ^ w0 ^ trw;
+ k2 = w2 ^ w1 ^ w0 ^ trw;
+ k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
+ end
+ else
+ begin
+ k0 = w0 ^ tw;
+ k1 = w1 ^ w0 ^ tw;
+ k2 = w2 ^ w1 ^ w0 ^ tw;
+ k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
+ rcon_next = 1'b1;
+ end
+
+ // Store the generated round keys.
+ key_mem_new = {k0, k1, k2, k3};
+ prev_key1_new = {k0, k1, k2, k3};
+ prev_key1_we = 1'b1;
+ prev_key0_new = prev_key1_reg;
+ prev_key0_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ end
+ endcase // case (keylen)
+ end
+ end // round_key_gen
+
+
+ //----------------------------------------------------------------
+ // rcon_logic
+ //
+ // Caclulates the rcon value for the different key expansion
+ // iterations.
+ //----------------------------------------------------------------
+ always @*
+ begin : rcon_logic
+ reg [7 : 0] tmp_rcon;
+ rcon_new = 8'h00;
+ rcon_we = 1'b0;
+
+ tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
+
+ if (rcon_set)
+ begin
+ rcon_new = 8'h8d;
+ rcon_we = 1'b1;
+ end
+
+ if (rcon_next)
+ begin
+ rcon_new = tmp_rcon[7 : 0];
+ rcon_we = 1'b1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter logic with increase and reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_rst)
+ begin
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b1;
+ end
+
+ else if (round_ctr_inc)
+ begin
+ round_ctr_new = round_ctr_reg + 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // key_mem_ctrl
+ //
+ //
+ // The FSM that controls the round key generation.
+ //----------------------------------------------------------------
+ always @*
+ begin: key_mem_ctrl
+ reg [3 : 0] num_rounds;
+
+ // Default assignments.
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ round_key_update = 1'b0;
+ round_ctr_rst = 1'b0;
+ round_ctr_inc = 1'b0;
+ key_mem_ctrl_new = CTRL_IDLE;
+ key_mem_ctrl_we = 1'b0;
+
+ if (keylen == AES_128_BIT_KEY)
+ num_rounds = AES_128_NUM_ROUNDS;
+ else
+ num_rounds = AES_256_NUM_ROUNDS;
+
+ case(key_mem_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ key_mem_ctrl_new = CTRL_INIT;
+ key_mem_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ round_ctr_rst = 1'b1;
+ key_mem_ctrl_new = CTRL_GENERATE;
+ key_mem_ctrl_we = 1'b1;
+ end
+
+ CTRL_GENERATE:
+ begin
+ round_ctr_inc = 1'b1;
+ round_key_update = 1'b1;
+ if (round_ctr_reg == num_rounds)
+ begin
+ key_mem_ctrl_new = CTRL_DONE;
+ key_mem_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_DONE:
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ key_mem_ctrl_new = CTRL_IDLE;
+ key_mem_ctrl_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (key_mem_ctrl_reg)
+
+ end // key_mem_ctrl
+endmodule // aes_key_mem
+
+//======================================================================
+// EOF aes_key_mem.v
+//======================================================================
+
+//======================================================================
+//
+// aes_sbox.v
+// ----------
+// The AES S-box. Basically a 256 Byte ROM. This implementation
+// contains four parallel S-boxes to handle a 32 bit word.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_sbox(
+ input wire [31 : 0] sboxw,
+ output wire [31 : 0] new_sboxw
+ );
+
+
+ //----------------------------------------------------------------
+ // The sbox array.
+ //----------------------------------------------------------------
+ wire [7 : 0] sbox [0 : 255];
+
+
+ //----------------------------------------------------------------
+ // Four parallel muxes.
+ //----------------------------------------------------------------
+ assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]];
+ assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]];
+ assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]];
+ assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]];
+
+
+ //----------------------------------------------------------------
+ // Creating the sbox array contents.
+ //----------------------------------------------------------------
+ assign sbox[8'h00] = 8'h63;
+ assign sbox[8'h01] = 8'h7c;
+ assign sbox[8'h02] = 8'h77;
+ assign sbox[8'h03] = 8'h7b;
+ assign sbox[8'h04] = 8'hf2;
+ assign sbox[8'h05] = 8'h6b;
+ assign sbox[8'h06] = 8'h6f;
+ assign sbox[8'h07] = 8'hc5;
+ assign sbox[8'h08] = 8'h30;
+ assign sbox[8'h09] = 8'h01;
+ assign sbox[8'h0a] = 8'h67;
+ assign sbox[8'h0b] = 8'h2b;
+ assign sbox[8'h0c] = 8'hfe;
+ assign sbox[8'h0d] = 8'hd7;
+ assign sbox[8'h0e] = 8'hab;
+ assign sbox[8'h0f] = 8'h76;
+ assign sbox[8'h10] = 8'hca;
+ assign sbox[8'h11] = 8'h82;
+ assign sbox[8'h12] = 8'hc9;
+ assign sbox[8'h13] = 8'h7d;
+ assign sbox[8'h14] = 8'hfa;
+ assign sbox[8'h15] = 8'h59;
+ assign sbox[8'h16] = 8'h47;
+ assign sbox[8'h17] = 8'hf0;
+ assign sbox[8'h18] = 8'had;
+ assign sbox[8'h19] = 8'hd4;
+ assign sbox[8'h1a] = 8'ha2;
+ assign sbox[8'h1b] = 8'haf;
+ assign sbox[8'h1c] = 8'h9c;
+ assign sbox[8'h1d] = 8'ha4;
+ assign sbox[8'h1e] = 8'h72;
+ assign sbox[8'h1f] = 8'hc0;
+ assign sbox[8'h20] = 8'hb7;
+ assign sbox[8'h21] = 8'hfd;
+ assign sbox[8'h22] = 8'h93;
+ assign sbox[8'h23] = 8'h26;
+ assign sbox[8'h24] = 8'h36;
+ assign sbox[8'h25] = 8'h3f;
+ assign sbox[8'h26] = 8'hf7;
+ assign sbox[8'h27] = 8'hcc;
+ assign sbox[8'h28] = 8'h34;
+ assign sbox[8'h29] = 8'ha5;
+ assign sbox[8'h2a] = 8'he5;
+ assign sbox[8'h2b] = 8'hf1;
+ assign sbox[8'h2c] = 8'h71;
+ assign sbox[8'h2d] = 8'hd8;
+ assign sbox[8'h2e] = 8'h31;
+ assign sbox[8'h2f] = 8'h15;
+ assign sbox[8'h30] = 8'h04;
+ assign sbox[8'h31] = 8'hc7;
+ assign sbox[8'h32] = 8'h23;
+ assign sbox[8'h33] = 8'hc3;
+ assign sbox[8'h34] = 8'h18;
+ assign sbox[8'h35] = 8'h96;
+ assign sbox[8'h36] = 8'h05;
+ assign sbox[8'h37] = 8'h9a;
+ assign sbox[8'h38] = 8'h07;
+ assign sbox[8'h39] = 8'h12;
+ assign sbox[8'h3a] = 8'h80;
+ assign sbox[8'h3b] = 8'he2;
+ assign sbox[8'h3c] = 8'heb;
+ assign sbox[8'h3d] = 8'h27;
+ assign sbox[8'h3e] = 8'hb2;
+ assign sbox[8'h3f] = 8'h75;
+ assign sbox[8'h40] = 8'h09;
+ assign sbox[8'h41] = 8'h83;
+ assign sbox[8'h42] = 8'h2c;
+ assign sbox[8'h43] = 8'h1a;
+ assign sbox[8'h44] = 8'h1b;
+ assign sbox[8'h45] = 8'h6e;
+ assign sbox[8'h46] = 8'h5a;
+ assign sbox[8'h47] = 8'ha0;
+ assign sbox[8'h48] = 8'h52;
+ assign sbox[8'h49] = 8'h3b;
+ assign sbox[8'h4a] = 8'hd6;
+ assign sbox[8'h4b] = 8'hb3;
+ assign sbox[8'h4c] = 8'h29;
+ assign sbox[8'h4d] = 8'he3;
+ assign sbox[8'h4e] = 8'h2f;
+ assign sbox[8'h4f] = 8'h84;
+ assign sbox[8'h50] = 8'h53;
+ assign sbox[8'h51] = 8'hd1;
+ assign sbox[8'h52] = 8'h00;
+ assign sbox[8'h53] = 8'hed;
+ assign sbox[8'h54] = 8'h20;
+ assign sbox[8'h55] = 8'hfc;
+ assign sbox[8'h56] = 8'hb1;
+ assign sbox[8'h57] = 8'h5b;
+ assign sbox[8'h58] = 8'h6a;
+ assign sbox[8'h59] = 8'hcb;
+ assign sbox[8'h5a] = 8'hbe;
+ assign sbox[8'h5b] = 8'h39;
+ assign sbox[8'h5c] = 8'h4a;
+ assign sbox[8'h5d] = 8'h4c;
+ assign sbox[8'h5e] = 8'h58;
+ assign sbox[8'h5f] = 8'hcf;
+ assign sbox[8'h60] = 8'hd0;
+ assign sbox[8'h61] = 8'hef;
+ assign sbox[8'h62] = 8'haa;
+ assign sbox[8'h63] = 8'hfb;
+ assign sbox[8'h64] = 8'h43;
+ assign sbox[8'h65] = 8'h4d;
+ assign sbox[8'h66] = 8'h33;
+ assign sbox[8'h67] = 8'h85;
+ assign sbox[8'h68] = 8'h45;
+ assign sbox[8'h69] = 8'hf9;
+ assign sbox[8'h6a] = 8'h02;
+ assign sbox[8'h6b] = 8'h7f;
+ assign sbox[8'h6c] = 8'h50;
+ assign sbox[8'h6d] = 8'h3c;
+ assign sbox[8'h6e] = 8'h9f;
+ assign sbox[8'h6f] = 8'ha8;
+ assign sbox[8'h70] = 8'h51;
+ assign sbox[8'h71] = 8'ha3;
+ assign sbox[8'h72] = 8'h40;
+ assign sbox[8'h73] = 8'h8f;
+ assign sbox[8'h74] = 8'h92;
+ assign sbox[8'h75] = 8'h9d;
+ assign sbox[8'h76] = 8'h38;
+ assign sbox[8'h77] = 8'hf5;
+ assign sbox[8'h78] = 8'hbc;
+ assign sbox[8'h79] = 8'hb6;
+ assign sbox[8'h7a] = 8'hda;
+ assign sbox[8'h7b] = 8'h21;
+ assign sbox[8'h7c] = 8'h10;
+ assign sbox[8'h7d] = 8'hff;
+ assign sbox[8'h7e] = 8'hf3;
+ assign sbox[8'h7f] = 8'hd2;
+ assign sbox[8'h80] = 8'hcd;
+ assign sbox[8'h81] = 8'h0c;
+ assign sbox[8'h82] = 8'h13;
+ assign sbox[8'h83] = 8'hec;
+ assign sbox[8'h84] = 8'h5f;
+ assign sbox[8'h85] = 8'h97;
+ assign sbox[8'h86] = 8'h44;
+ assign sbox[8'h87] = 8'h17;
+ assign sbox[8'h88] = 8'hc4;
+ assign sbox[8'h89] = 8'ha7;
+ assign sbox[8'h8a] = 8'h7e;
+ assign sbox[8'h8b] = 8'h3d;
+ assign sbox[8'h8c] = 8'h64;
+ assign sbox[8'h8d] = 8'h5d;
+ assign sbox[8'h8e] = 8'h19;
+ assign sbox[8'h8f] = 8'h73;
+ assign sbox[8'h90] = 8'h60;
+ assign sbox[8'h91] = 8'h81;
+ assign sbox[8'h92] = 8'h4f;
+ assign sbox[8'h93] = 8'hdc;
+ assign sbox[8'h94] = 8'h22;
+ assign sbox[8'h95] = 8'h2a;
+ assign sbox[8'h96] = 8'h90;
+ assign sbox[8'h97] = 8'h88;
+ assign sbox[8'h98] = 8'h46;
+ assign sbox[8'h99] = 8'hee;
+ assign sbox[8'h9a] = 8'hb8;
+ assign sbox[8'h9b] = 8'h14;
+ assign sbox[8'h9c] = 8'hde;
+ assign sbox[8'h9d] = 8'h5e;
+ assign sbox[8'h9e] = 8'h0b;
+ assign sbox[8'h9f] = 8'hdb;
+ assign sbox[8'ha0] = 8'he0;
+ assign sbox[8'ha1] = 8'h32;
+ assign sbox[8'ha2] = 8'h3a;
+ assign sbox[8'ha3] = 8'h0a;
+ assign sbox[8'ha4] = 8'h49;
+ assign sbox[8'ha5] = 8'h06;
+ assign sbox[8'ha6] = 8'h24;
+ assign sbox[8'ha7] = 8'h5c;
+ assign sbox[8'ha8] = 8'hc2;
+ assign sbox[8'ha9] = 8'hd3;
+ assign sbox[8'haa] = 8'hac;
+ assign sbox[8'hab] = 8'h62;
+ assign sbox[8'hac] = 8'h91;
+ assign sbox[8'had] = 8'h95;
+ assign sbox[8'hae] = 8'he4;
+ assign sbox[8'haf] = 8'h79;
+ assign sbox[8'hb0] = 8'he7;
+ assign sbox[8'hb1] = 8'hc8;
+ assign sbox[8'hb2] = 8'h37;
+ assign sbox[8'hb3] = 8'h6d;
+ assign sbox[8'hb4] = 8'h8d;
+ assign sbox[8'hb5] = 8'hd5;
+ assign sbox[8'hb6] = 8'h4e;
+ assign sbox[8'hb7] = 8'ha9;
+ assign sbox[8'hb8] = 8'h6c;
+ assign sbox[8'hb9] = 8'h56;
+ assign sbox[8'hba] = 8'hf4;
+ assign sbox[8'hbb] = 8'hea;
+ assign sbox[8'hbc] = 8'h65;
+ assign sbox[8'hbd] = 8'h7a;
+ assign sbox[8'hbe] = 8'hae;
+ assign sbox[8'hbf] = 8'h08;
+ assign sbox[8'hc0] = 8'hba;
+ assign sbox[8'hc1] = 8'h78;
+ assign sbox[8'hc2] = 8'h25;
+ assign sbox[8'hc3] = 8'h2e;
+ assign sbox[8'hc4] = 8'h1c;
+ assign sbox[8'hc5] = 8'ha6;
+ assign sbox[8'hc6] = 8'hb4;
+ assign sbox[8'hc7] = 8'hc6;
+ assign sbox[8'hc8] = 8'he8;
+ assign sbox[8'hc9] = 8'hdd;
+ assign sbox[8'hca] = 8'h74;
+ assign sbox[8'hcb] = 8'h1f;
+ assign sbox[8'hcc] = 8'h4b;
+ assign sbox[8'hcd] = 8'hbd;
+ assign sbox[8'hce] = 8'h8b;
+ assign sbox[8'hcf] = 8'h8a;
+ assign sbox[8'hd0] = 8'h70;
+ assign sbox[8'hd1] = 8'h3e;
+ assign sbox[8'hd2] = 8'hb5;
+ assign sbox[8'hd3] = 8'h66;
+ assign sbox[8'hd4] = 8'h48;
+ assign sbox[8'hd5] = 8'h03;
+ assign sbox[8'hd6] = 8'hf6;
+ assign sbox[8'hd7] = 8'h0e;
+ assign sbox[8'hd8] = 8'h61;
+ assign sbox[8'hd9] = 8'h35;
+ assign sbox[8'hda] = 8'h57;
+ assign sbox[8'hdb] = 8'hb9;
+ assign sbox[8'hdc] = 8'h86;
+ assign sbox[8'hdd] = 8'hc1;
+ assign sbox[8'hde] = 8'h1d;
+ assign sbox[8'hdf] = 8'h9e;
+ assign sbox[8'he0] = 8'he1;
+ assign sbox[8'he1] = 8'hf8;
+ assign sbox[8'he2] = 8'h98;
+ assign sbox[8'he3] = 8'h11;
+ assign sbox[8'he4] = 8'h69;
+ assign sbox[8'he5] = 8'hd9;
+ assign sbox[8'he6] = 8'h8e;
+ assign sbox[8'he7] = 8'h94;
+ assign sbox[8'he8] = 8'h9b;
+ assign sbox[8'he9] = 8'h1e;
+ assign sbox[8'hea] = 8'h87;
+ assign sbox[8'heb] = 8'he9;
+ assign sbox[8'hec] = 8'hce;
+ assign sbox[8'hed] = 8'h55;
+ assign sbox[8'hee] = 8'h28;
+ assign sbox[8'hef] = 8'hdf;
+ assign sbox[8'hf0] = 8'h8c;
+ assign sbox[8'hf1] = 8'ha1;
+ assign sbox[8'hf2] = 8'h89;
+ assign sbox[8'hf3] = 8'h0d;
+ assign sbox[8'hf4] = 8'hbf;
+ assign sbox[8'hf5] = 8'he6;
+ assign sbox[8'hf6] = 8'h42;
+ assign sbox[8'hf7] = 8'h68;
+ assign sbox[8'hf8] = 8'h41;
+ assign sbox[8'hf9] = 8'h99;
+ assign sbox[8'hfa] = 8'h2d;
+ assign sbox[8'hfb] = 8'h0f;
+ assign sbox[8'hfc] = 8'hb0;
+ assign sbox[8'hfd] = 8'h54;
+ assign sbox[8'hfe] = 8'hbb;
+ assign sbox[8'hff] = 8'h16;
+
+endmodule // aes_sbox
+
+//======================================================================
+// EOF aes_sbox.v
+//======================================================================
+
+//======================================================================
+//
+// aes_encipher_block.v
+// --------------------
+// The AES encipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// enciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_encipher_block(
+ input wire clk,
+ input wire reset_n,
+
+ input wire next,
+
+ input wire keylen,
+ output wire [3 : 0] round,
+ input wire [127 : 0] round_key,
+
+ output wire [31 : 0] sboxw,
+ input wire [31 : 0] new_sboxw,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] new_block,
+ output wire ready
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES128_ROUNDS = 4'ha;
+ localparam AES256_ROUNDS = 4'he;
+
+ localparam NO_UPDATE = 3'h0;
+ localparam INIT_UPDATE = 3'h1;
+ localparam SBOX_UPDATE = 3'h2;
+ localparam MAIN_UPDATE = 3'h3;
+ localparam FINAL_UPDATE = 3'h4;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_SBOX = 3'h2;
+ localparam CTRL_MAIN = 3'h3;
+ localparam CTRL_FINAL = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Round functions with sub functions.
+ //----------------------------------------------------------------
+ function [7 : 0] gm2(input [7 : 0] op);
+ begin
+ gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+ end
+ endfunction // gm2
+
+ function [7 : 0] gm3(input [7 : 0] op);
+ begin
+ gm3 = gm2(op) ^ op;
+ end
+ endfunction // gm3
+
+ function [31 : 0] mixw(input [31 : 0] w);
+ reg [7 : 0] b0, b1, b2, b3;
+ reg [7 : 0] mb0, mb1, mb2, mb3;
+ begin
+ b0 = w[31 : 24];
+ b1 = w[23 : 16];
+ b2 = w[15 : 08];
+ b3 = w[07 : 00];
+
+ mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
+ mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
+ mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
+ mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
+
+ mixw = {mb0, mb1, mb2, mb3};
+ end
+ endfunction // mixw
+
+ function [127 : 0] mixcolumns(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = mixw(w0);
+ ws1 = mixw(w1);
+ ws2 = mixw(w2);
+ ws3 = mixw(w3);
+
+ mixcolumns = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // mixcolumns
+
+ function [127 : 0] shiftrows(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
+ ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
+ ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
+ ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
+
+ shiftrows = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // shiftrows
+
+ function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+ begin
+ addroundkey = data ^ rkey;
+ end
+ endfunction // addroundkey
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] sword_ctr_reg;
+ reg [1 : 0] sword_ctr_new;
+ reg sword_ctr_we;
+ reg sword_ctr_inc;
+ reg sword_ctr_rst;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_we;
+ reg round_ctr_rst;
+ reg round_ctr_inc;
+
+ reg [127 : 0] block_new;
+ reg [31 : 0] block_w0_reg;
+ reg [31 : 0] block_w1_reg;
+ reg [31 : 0] block_w2_reg;
+ reg [31 : 0] block_w3_reg;
+ reg block_w0_we;
+ reg block_w1_we;
+ reg block_w2_we;
+ reg block_w3_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] enc_ctrl_reg;
+ reg [2 : 0] enc_ctrl_new;
+ reg enc_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [2 : 0] update_type;
+ reg [31 : 0] muxed_sboxw;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign round = round_ctr_reg;
+ assign sboxw = muxed_sboxw;
+ assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ block_w0_reg <= 32'h0;
+ block_w1_reg <= 32'h0;
+ block_w2_reg <= 32'h0;
+ block_w3_reg <= 32'h0;
+ sword_ctr_reg <= 2'h0;
+ round_ctr_reg <= 4'h0;
+ ready_reg <= 1'b1;
+ enc_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (block_w0_we)
+ block_w0_reg <= block_new[127 : 096];
+
+ if (block_w1_we)
+ block_w1_reg <= block_new[095 : 064];
+
+ if (block_w2_we)
+ block_w2_reg <= block_new[063 : 032];
+
+ if (block_w3_we)
+ block_w3_reg <= block_new[031 : 000];
+
+ if (sword_ctr_we)
+ sword_ctr_reg <= sword_ctr_new;
+
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (enc_ctrl_we)
+ enc_ctrl_reg <= enc_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // round_logic
+ //
+ // The logic needed to implement init, main and final rounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_logic
+ reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
+ reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
+
+ block_new = 128'h0;
+ muxed_sboxw = 32'h0;
+ block_w0_we = 1'b0;
+ block_w1_we = 1'b0;
+ block_w2_we = 1'b0;
+ block_w3_we = 1'b0;
+
+ old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ shiftrows_block = shiftrows(old_block);
+ mixcolumns_block = mixcolumns(shiftrows_block);
+ addkey_init_block = addroundkey(block, round_key);
+ addkey_main_block = addroundkey(mixcolumns_block, round_key);
+ addkey_final_block = addroundkey(shiftrows_block, round_key);
+
+ case (update_type)
+ INIT_UPDATE:
+ begin
+ block_new = addkey_init_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ SBOX_UPDATE:
+ begin
+ block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+ case (sword_ctr_reg)
+ 2'h0:
+ begin
+ muxed_sboxw = block_w0_reg;
+ block_w0_we = 1'b1;
+ end
+
+ 2'h1:
+ begin
+ muxed_sboxw = block_w1_reg;
+ block_w1_we = 1'b1;
+ end
+
+ 2'h2:
+ begin
+ muxed_sboxw = block_w2_reg;
+ block_w2_we = 1'b1;
+ end
+
+ 2'h3:
+ begin
+ muxed_sboxw = block_w3_reg;
+ block_w3_we = 1'b1;
+ end
+ endcase // case (sbox_mux_ctrl_reg)
+ end
+
+ MAIN_UPDATE:
+ begin
+ block_new = addkey_main_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ FINAL_UPDATE:
+ begin
+ block_new = addkey_final_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (update_type)
+ end // round_logic
+
+
+ //----------------------------------------------------------------
+ // sword_ctr
+ //
+ // The subbytes word counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : sword_ctr
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b0;
+
+ if (sword_ctr_rst)
+ begin
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b1;
+ end
+ else if (sword_ctr_inc)
+ begin
+ sword_ctr_new = sword_ctr_reg + 1'b1;
+ sword_ctr_we = 1'b1;
+ end
+ end // sword_ctr
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_rst)
+ begin
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b1;
+ end
+ else if (round_ctr_inc)
+ begin
+ round_ctr_new = round_ctr_reg + 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end // round_ctr
+
+
+ //----------------------------------------------------------------
+ // encipher_ctrl
+ //
+ // The FSM that controls the encipher operations.
+ //----------------------------------------------------------------
+ always @*
+ begin: encipher_ctrl
+ reg [3 : 0] num_rounds;
+
+ // Default assignments.
+ sword_ctr_inc = 1'b0;
+ sword_ctr_rst = 1'b0;
+ round_ctr_inc = 1'b0;
+ round_ctr_rst = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ update_type = NO_UPDATE;
+ enc_ctrl_new = CTRL_IDLE;
+ enc_ctrl_we = 1'b0;
+
+ if (keylen == AES_256_BIT_KEY)
+ begin
+ num_rounds = AES256_ROUNDS;
+ end
+ else
+ begin
+ num_rounds = AES128_ROUNDS;
+ end
+
+ case(enc_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (next)
+ begin
+ round_ctr_rst = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ enc_ctrl_new = CTRL_INIT;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ round_ctr_inc = 1'b1;
+ sword_ctr_rst = 1'b1;
+ update_type = INIT_UPDATE;
+ enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_we = 1'b1;
+ end
+
+ CTRL_SBOX:
+ begin
+ sword_ctr_inc = 1'b1;
+ update_type = SBOX_UPDATE;
+ if (sword_ctr_reg == 2'h3)
+ begin
+ enc_ctrl_new = CTRL_MAIN;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_MAIN:
+ begin
+ sword_ctr_rst = 1'b1;
+ round_ctr_inc = 1'b1;
+ if (round_ctr_reg < num_rounds)
+ begin
+ update_type = MAIN_UPDATE;
+ enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_we = 1'b1;
+ end
+ else
+ begin
+ update_type = FINAL_UPDATE;
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ enc_ctrl_new = CTRL_IDLE;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ // Empty. Just here to make the synthesis tool happy.
+ end
+ endcase // case (enc_ctrl_reg)
+ end // encipher_ctrl
+
+endmodule // aes_encipher_block
+
+//======================================================================
+// EOF aes_encipher_block.v
+//======================================================================
+
+
diff --git a/openlane/designs/aes_core/config.tcl b/openlane/designs/aes_core/config.tcl
new file mode 100755
index 0000000..c1be88e
--- /dev/null
+++ b/openlane/designs/aes_core/config.tcl
@@ -0,0 +1,17 @@
+
+# Design
+set ::env(DESIGN_NAME) "aes_core"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/aes.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {60}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/aes_core/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/aes_core/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..c618747
--- /dev/null
+++ b/openlane/designs/aes_core/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "22"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 25
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.25
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/aes_core/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/aes_core/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..aeb0877
--- /dev/null
+++ b/openlane/designs/aes_core/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 25
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "21.28"
diff --git a/openlane/designs/aes_core/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/aes_core/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..aeb0877
--- /dev/null
+++ b/openlane/designs/aes_core/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 25
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "21.28"
diff --git a/openlane/designs/aes_core/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/aes_core/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..aeb0877
--- /dev/null
+++ b/openlane/designs/aes_core/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 25
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "21.28"
diff --git a/openlane/designs/aes_core/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/aes_core/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..aeb0877
--- /dev/null
+++ b/openlane/designs/aes_core/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 25
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "21.28"
diff --git a/openlane/designs/aes_core/src/aes.v b/openlane/designs/aes_core/src/aes.v
new file mode 100644
index 0000000..b2c24ba
--- /dev/null
+++ b/openlane/designs/aes_core/src/aes.v
@@ -0,0 +1,2708 @@
+//======================================================================
+//
+// aes.v
+// --------
+// Top level wrapper for the AES block cipher core.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CTRL_ENCDEC_BIT = 0;
+ localparam CTRL_KEYLEN_BIT = 1;
+
+ localparam ADDR_KEY0 = 8'h10;
+ localparam ADDR_KEY7 = 8'h17;
+
+ localparam ADDR_BLOCK0 = 8'h20;
+ localparam ADDR_BLOCK3 = 8'h23;
+
+ localparam ADDR_RESULT0 = 8'h30;
+ localparam ADDR_RESULT3 = 8'h33;
+
+ localparam CORE_NAME0 = 32'h61657320; // "aes "
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_VERSION = 32'h302e3630; // "0.60"
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg init_reg;
+ reg init_new;
+
+ reg next_reg;
+ reg next_new;
+
+ reg encdec_reg;
+ reg keylen_reg;
+ reg config_we;
+
+ reg [31 : 0] block_reg [0 : 3];
+ reg block_we;
+
+ reg [31 : 0] key_reg [0 : 7];
+ reg key_we;
+
+ reg [127 : 0] result_reg;
+ reg valid_reg;
+ reg ready_reg;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_read_data;
+
+ wire core_encdec;
+ wire core_init;
+ wire core_next;
+ wire core_ready;
+ wire [255 : 0] core_key;
+ wire core_keylen;
+ wire [127 : 0] core_block;
+ wire [127 : 0] core_result;
+ wire core_valid;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+ assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
+ key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
+
+ assign core_block = {block_reg[0], block_reg[1],
+ block_reg[2], block_reg[3]};
+ assign core_init = init_reg;
+ assign core_next = next_reg;
+ assign core_encdec = encdec_reg;
+ assign core_keylen = keylen_reg;
+
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ aes_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .encdec(core_encdec),
+ .init(core_init),
+ .next(core_next),
+ .ready(core_ready),
+
+ .key(core_key),
+ .keylen(core_keylen),
+
+ .block(core_block),
+ .result(core_result),
+ .result_valid(core_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin : reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i < 4 ; i = i + 1)
+ block_reg[i] <= 32'h0;
+
+ for (i = 0 ; i < 8 ; i = i + 1)
+ key_reg[i] <= 32'h0;
+
+ init_reg <= 1'b0;
+ next_reg <= 1'b0;
+ encdec_reg <= 1'b0;
+ keylen_reg <= 1'b0;
+
+ result_reg <= 128'h0;
+ valid_reg <= 1'b0;
+ ready_reg <= 1'b0;
+ end
+ else
+ begin
+ ready_reg <= core_ready;
+ valid_reg <= core_valid;
+ result_reg <= core_result;
+ init_reg <= init_new;
+ next_reg <= next_new;
+
+ if (config_we)
+ begin
+ encdec_reg <= write_data[CTRL_ENCDEC_BIT];
+ keylen_reg <= write_data[CTRL_KEYLEN_BIT];
+ end
+
+ if (key_we)
+ key_reg[address[2 : 0]] <= write_data;
+
+ if (block_we)
+ block_reg[address[1 : 0]] <= write_data;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // api
+ //
+ // The interface command decoding logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : api
+ init_new = 1'b0;
+ next_new = 1'b0;
+ config_we = 1'b0;
+ key_we = 1'b0;
+ block_we = 1'b0;
+ tmp_read_data = 32'h0;
+
+ if (cs)
+ begin
+ if (we)
+ begin
+ if (address == ADDR_CTRL)
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
+
+ if (address == ADDR_CONFIG)
+ config_we = 1'b1;
+
+ if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+ key_we = 1'b1;
+
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+ block_we = 1'b1;
+ end // if (we)
+
+ else
+ begin
+ case (address)
+ ADDR_NAME0: tmp_read_data = CORE_NAME0;
+ ADDR_NAME1: tmp_read_data = CORE_NAME1;
+ ADDR_VERSION: tmp_read_data = CORE_VERSION;
+ ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+ ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
+
+ default:
+ begin
+ end
+ endcase // case (address)
+
+ if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
+ tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
+ end
+ end
+ end // addr_decoder
+endmodule // aes
+
+//======================================================================
+// EOF aes.v
+//======================================================================
+
+
+//======================================================================
+//
+// aes.core.v
+// ----------
+// The AES core. This core supports key size of 128, and 256 bits.
+// Most of the functionality is within the submodules.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_core(
+ input wire clk,
+ input wire reset_n,
+
+ input wire encdec,
+ input wire init,
+ input wire next,
+ output wire ready,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] result,
+ output wire result_valid
+ );
+
+
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam CTRL_IDLE = 2'h0;
+ localparam CTRL_INIT = 2'h1;
+ localparam CTRL_NEXT = 2'h2;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] aes_core_ctrl_reg;
+ reg [1 : 0] aes_core_ctrl_new;
+ reg aes_core_ctrl_we;
+
+ reg result_valid_reg;
+ reg result_valid_new;
+ reg result_valid_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg init_state;
+
+ wire [127 : 0] round_key;
+ wire key_ready;
+
+ reg enc_next;
+ wire [3 : 0] enc_round_nr;
+ wire [127 : 0] enc_new_block;
+ wire enc_ready;
+ wire [31 : 0] enc_sboxw;
+
+ reg dec_next;
+ wire [3 : 0] dec_round_nr;
+ wire [127 : 0] dec_new_block;
+ wire dec_ready;
+
+ reg [127 : 0] muxed_new_block;
+ reg [3 : 0] muxed_round_nr;
+ reg muxed_ready;
+
+ wire [31 : 0] keymem_sboxw;
+
+ reg [31 : 0] muxed_sboxw;
+ wire [31 : 0] new_sboxw;
+
+
+ //----------------------------------------------------------------
+ // Instantiations.
+ //----------------------------------------------------------------
+ aes_encipher_block enc_block(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .next(enc_next),
+
+ .keylen(keylen),
+ .round(enc_round_nr),
+ .round_key(round_key),
+
+ .sboxw(enc_sboxw),
+ .new_sboxw(new_sboxw),
+
+ .block(block),
+ .new_block(enc_new_block),
+ .ready(enc_ready)
+ );
+
+
+ aes_decipher_block dec_block(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .next(dec_next),
+
+ .keylen(keylen),
+ .round(dec_round_nr),
+ .round_key(round_key),
+
+ .block(block),
+ .new_block(dec_new_block),
+ .ready(dec_ready)
+ );
+
+
+ aes_key_mem keymem(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .key(key),
+ .keylen(keylen),
+ .init(init),
+
+ .round(muxed_round_nr),
+ .round_key(round_key),
+ .ready(key_ready),
+
+ .sboxw(keymem_sboxw),
+ .new_sboxw(new_sboxw)
+ );
+
+
+ aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign ready = ready_reg;
+ assign result = muxed_new_block;
+ assign result_valid = result_valid_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ result_valid_reg <= 1'b0;
+ ready_reg <= 1'b1;
+ aes_core_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (result_valid_we)
+ result_valid_reg <= result_valid_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (aes_core_ctrl_we)
+ aes_core_ctrl_reg <= aes_core_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // sbox_mux
+ //
+ // Controls which of the encipher datapath or the key memory
+ // that gets access to the sbox.
+ //----------------------------------------------------------------
+ always @*
+ begin : sbox_mux
+ if (init_state)
+ begin
+ muxed_sboxw = keymem_sboxw;
+ end
+ else
+ begin
+ muxed_sboxw = enc_sboxw;
+ end
+ end // sbox_mux
+
+
+ //----------------------------------------------------------------
+ // encdex_mux
+ //
+ // Controls which of the datapaths that get the next signal, have
+ // access to the memory as well as the block processing result.
+ //----------------------------------------------------------------
+ always @*
+ begin : encdec_mux
+ enc_next = 1'b0;
+ dec_next = 1'b0;
+
+ if (encdec)
+ begin
+ // Encipher operations
+ enc_next = next;
+ muxed_round_nr = enc_round_nr;
+ muxed_new_block = enc_new_block;
+ muxed_ready = enc_ready;
+ end
+ else
+ begin
+ // Decipher operations
+ dec_next = next;
+ muxed_round_nr = dec_round_nr;
+ muxed_new_block = dec_new_block;
+ muxed_ready = dec_ready;
+ end
+ end // encdec_mux
+
+
+ //----------------------------------------------------------------
+ // aes_core_ctrl
+ //
+ // Control FSM for aes core. Basically tracks if we are in
+ // key init, encipher or decipher modes and connects the
+ // different submodules to shared resources and interface ports.
+ //----------------------------------------------------------------
+ always @*
+ begin : aes_core_ctrl
+ init_state = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b0;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b0;
+
+ case (aes_core_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ init_state = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_INIT;
+ aes_core_ctrl_we = 1'b1;
+ end
+ else if (next)
+ begin
+ init_state = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_NEXT;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ init_state = 1'b1;
+
+ if (key_ready)
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_NEXT:
+ begin
+ init_state = 1'b0;
+
+ if (muxed_ready)
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ result_valid_new = 1'b1;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+
+ end
+ endcase // case (aes_core_ctrl_reg)
+
+ end // aes_core_ctrl
+endmodule // aes_core
+
+//======================================================================
+// EOF aes_core.v
+//======================================================================
+
+//======================================================================
+//
+// aes_decipher_block.v
+// --------------------
+// The AES decipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// decciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_decipher_block(
+ input wire clk,
+ input wire reset_n,
+
+ input wire next,
+
+ input wire keylen,
+ output wire [3 : 0] round,
+ input wire [127 : 0] round_key,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] new_block,
+ output wire ready
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES128_ROUNDS = 4'ha;
+ localparam AES256_ROUNDS = 4'he;
+
+ localparam NO_UPDATE = 3'h0;
+ localparam INIT_UPDATE = 3'h1;
+ localparam SBOX_UPDATE = 3'h2;
+ localparam MAIN_UPDATE = 3'h3;
+ localparam FINAL_UPDATE = 3'h4;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_SBOX = 3'h2;
+ localparam CTRL_MAIN = 3'h3;
+ localparam CTRL_FINAL = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Gaolis multiplication functions for Inverse MixColumn.
+ //----------------------------------------------------------------
+ function [7 : 0] gm2(input [7 : 0] op);
+ begin
+ gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+ end
+ endfunction // gm2
+
+ function [7 : 0] gm3(input [7 : 0] op);
+ begin
+ gm3 = gm2(op) ^ op;
+ end
+ endfunction // gm3
+
+ function [7 : 0] gm4(input [7 : 0] op);
+ begin
+ gm4 = gm2(gm2(op));
+ end
+ endfunction // gm4
+
+ function [7 : 0] gm8(input [7 : 0] op);
+ begin
+ gm8 = gm2(gm4(op));
+ end
+ endfunction // gm8
+
+ function [7 : 0] gm09(input [7 : 0] op);
+ begin
+ gm09 = gm8(op) ^ op;
+ end
+ endfunction // gm09
+
+ function [7 : 0] gm11(input [7 : 0] op);
+ begin
+ gm11 = gm8(op) ^ gm2(op) ^ op;
+ end
+ endfunction // gm11
+
+ function [7 : 0] gm13(input [7 : 0] op);
+ begin
+ gm13 = gm8(op) ^ gm4(op) ^ op;
+ end
+ endfunction // gm13
+
+ function [7 : 0] gm14(input [7 : 0] op);
+ begin
+ gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
+ end
+ endfunction // gm14
+
+ function [31 : 0] inv_mixw(input [31 : 0] w);
+ reg [7 : 0] b0, b1, b2, b3;
+ reg [7 : 0] mb0, mb1, mb2, mb3;
+ begin
+ b0 = w[31 : 24];
+ b1 = w[23 : 16];
+ b2 = w[15 : 08];
+ b3 = w[07 : 00];
+
+ mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
+ mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
+ mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
+ mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
+
+ inv_mixw = {mb0, mb1, mb2, mb3};
+ end
+ endfunction // mixw
+
+ function [127 : 0] inv_mixcolumns(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = inv_mixw(w0);
+ ws1 = inv_mixw(w1);
+ ws2 = inv_mixw(w2);
+ ws3 = inv_mixw(w3);
+
+ inv_mixcolumns = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // inv_mixcolumns
+
+ function [127 : 0] inv_shiftrows(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
+ ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
+ ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
+ ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
+
+ inv_shiftrows = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // inv_shiftrows
+
+ function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+ begin
+ addroundkey = data ^ rkey;
+ end
+ endfunction // addroundkey
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] sword_ctr_reg;
+ reg [1 : 0] sword_ctr_new;
+ reg sword_ctr_we;
+ reg sword_ctr_inc;
+ reg sword_ctr_rst;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_we;
+ reg round_ctr_set;
+ reg round_ctr_dec;
+
+ reg [127 : 0] block_new;
+ reg [31 : 0] block_w0_reg;
+ reg [31 : 0] block_w1_reg;
+ reg [31 : 0] block_w2_reg;
+ reg [31 : 0] block_w3_reg;
+ reg block_w0_we;
+ reg block_w1_we;
+ reg block_w2_we;
+ reg block_w3_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] dec_ctrl_reg;
+ reg [2 : 0] dec_ctrl_new;
+ reg dec_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_sboxw;
+ wire [31 : 0] new_sboxw;
+ reg [2 : 0] update_type;
+
+
+ //----------------------------------------------------------------
+ // Instantiations.
+ //----------------------------------------------------------------
+ aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign round = round_ctr_reg;
+ assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with synchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ block_w0_reg <= 32'h0;
+ block_w1_reg <= 32'h0;
+ block_w2_reg <= 32'h0;
+ block_w3_reg <= 32'h0;
+ sword_ctr_reg <= 2'h0;
+ round_ctr_reg <= 4'h0;
+ ready_reg <= 1'b1;
+ dec_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (block_w0_we)
+ block_w0_reg <= block_new[127 : 096];
+
+ if (block_w1_we)
+ block_w1_reg <= block_new[095 : 064];
+
+ if (block_w2_we)
+ block_w2_reg <= block_new[063 : 032];
+
+ if (block_w3_we)
+ block_w3_reg <= block_new[031 : 000];
+
+ if (sword_ctr_we)
+ sword_ctr_reg <= sword_ctr_new;
+
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (dec_ctrl_we)
+ dec_ctrl_reg <= dec_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // round_logic
+ //
+ // The logic needed to implement init, main and final rounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_logic
+ reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
+ reg [127 : 0] addkey_block;
+
+ inv_shiftrows_block = 128'h0;
+ inv_mixcolumns_block = 128'h0;
+ addkey_block = 128'h0;
+ block_new = 128'h0;
+ tmp_sboxw = 32'h0;
+ block_w0_we = 1'b0;
+ block_w1_we = 1'b0;
+ block_w2_we = 1'b0;
+ block_w3_we = 1'b0;
+
+ old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+
+ // Update based on update type.
+ case (update_type)
+ // InitRound
+ INIT_UPDATE:
+ begin
+ old_block = block;
+ addkey_block = addroundkey(old_block, round_key);
+ inv_shiftrows_block = inv_shiftrows(addkey_block);
+ block_new = inv_shiftrows_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ SBOX_UPDATE:
+ begin
+ block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+ case (sword_ctr_reg)
+ 2'h0:
+ begin
+ tmp_sboxw = block_w0_reg;
+ block_w0_we = 1'b1;
+ end
+
+ 2'h1:
+ begin
+ tmp_sboxw = block_w1_reg;
+ block_w1_we = 1'b1;
+ end
+
+ 2'h2:
+ begin
+ tmp_sboxw = block_w2_reg;
+ block_w2_we = 1'b1;
+ end
+
+ 2'h3:
+ begin
+ tmp_sboxw = block_w3_reg;
+ block_w3_we = 1'b1;
+ end
+ endcase // case (sbox_mux_ctrl_reg)
+ end
+
+ MAIN_UPDATE:
+ begin
+ addkey_block = addroundkey(old_block, round_key);
+ inv_mixcolumns_block = inv_mixcolumns(addkey_block);
+ inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
+ block_new = inv_shiftrows_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ FINAL_UPDATE:
+ begin
+ block_new = addroundkey(old_block, round_key);
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (update_type)
+ end // round_logic
+
+
+ //----------------------------------------------------------------
+ // sword_ctr
+ //
+ // The subbytes word counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : sword_ctr
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b0;
+
+ if (sword_ctr_rst)
+ begin
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b1;
+ end
+ else if (sword_ctr_inc)
+ begin
+ sword_ctr_new = sword_ctr_reg + 1'b1;
+ sword_ctr_we = 1'b1;
+ end
+ end // sword_ctr
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_set)
+ begin
+ if (keylen == AES_256_BIT_KEY)
+ begin
+ round_ctr_new = AES256_ROUNDS;
+ end
+ else
+ begin
+ round_ctr_new = AES128_ROUNDS;
+ end
+ round_ctr_we = 1'b1;
+ end
+ else if (round_ctr_dec)
+ begin
+ round_ctr_new = round_ctr_reg - 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end // round_ctr
+
+
+ //----------------------------------------------------------------
+ // decipher_ctrl
+ //
+ // The FSM that controls the decipher operations.
+ //----------------------------------------------------------------
+ always @*
+ begin: decipher_ctrl
+ sword_ctr_inc = 1'b0;
+ sword_ctr_rst = 1'b0;
+ round_ctr_dec = 1'b0;
+ round_ctr_set = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ update_type = NO_UPDATE;
+ dec_ctrl_new = CTRL_IDLE;
+ dec_ctrl_we = 1'b0;
+
+ case(dec_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (next)
+ begin
+ round_ctr_set = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ dec_ctrl_new = CTRL_INIT;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ sword_ctr_rst = 1'b1;
+ update_type = INIT_UPDATE;
+ dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_we = 1'b1;
+ end
+
+ CTRL_SBOX:
+ begin
+ sword_ctr_inc = 1'b1;
+ update_type = SBOX_UPDATE;
+ if (sword_ctr_reg == 2'h3)
+ begin
+ round_ctr_dec = 1'b1;
+ dec_ctrl_new = CTRL_MAIN;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_MAIN:
+ begin
+ sword_ctr_rst = 1'b1;
+ if (round_ctr_reg > 0)
+ begin
+ update_type = MAIN_UPDATE;
+ dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_we = 1'b1;
+ end
+ else
+ begin
+ update_type = FINAL_UPDATE;
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ dec_ctrl_new = CTRL_IDLE;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ // Empty. Just here to make the synthesis tool happy.
+ end
+ endcase // case (dec_ctrl_reg)
+ end // decipher_ctrl
+
+endmodule // aes_decipher_block
+
+//======================================================================
+// EOF aes_decipher_block.v
+//======================================================================
+
+//======================================================================
+//
+// aes_inv_sbox.v
+// --------------
+// The inverse AES S-box. Basically a 256 Byte ROM.
+//
+//
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_inv_sbox(
+ input wire [31 : 0] sword,
+ output wire [31 : 0] new_sword
+ );
+
+
+ //----------------------------------------------------------------
+ // The inverse sbox array.
+ //----------------------------------------------------------------
+ wire [7 : 0] inv_sbox [0 : 255];
+
+
+ //----------------------------------------------------------------
+ // Four parallel muxes.
+ //----------------------------------------------------------------
+ assign new_sword[31 : 24] = inv_sbox[sword[31 : 24]];
+ assign new_sword[23 : 16] = inv_sbox[sword[23 : 16]];
+ assign new_sword[15 : 08] = inv_sbox[sword[15 : 08]];
+ assign new_sword[07 : 00] = inv_sbox[sword[07 : 00]];
+
+
+ //----------------------------------------------------------------
+ // Creating the contents of the array.
+ //----------------------------------------------------------------
+ assign inv_sbox[8'h00] = 8'h52;
+ assign inv_sbox[8'h01] = 8'h09;
+ assign inv_sbox[8'h02] = 8'h6a;
+ assign inv_sbox[8'h03] = 8'hd5;
+ assign inv_sbox[8'h04] = 8'h30;
+ assign inv_sbox[8'h05] = 8'h36;
+ assign inv_sbox[8'h06] = 8'ha5;
+ assign inv_sbox[8'h07] = 8'h38;
+ assign inv_sbox[8'h08] = 8'hbf;
+ assign inv_sbox[8'h09] = 8'h40;
+ assign inv_sbox[8'h0a] = 8'ha3;
+ assign inv_sbox[8'h0b] = 8'h9e;
+ assign inv_sbox[8'h0c] = 8'h81;
+ assign inv_sbox[8'h0d] = 8'hf3;
+ assign inv_sbox[8'h0e] = 8'hd7;
+ assign inv_sbox[8'h0f] = 8'hfb;
+ assign inv_sbox[8'h10] = 8'h7c;
+ assign inv_sbox[8'h11] = 8'he3;
+ assign inv_sbox[8'h12] = 8'h39;
+ assign inv_sbox[8'h13] = 8'h82;
+ assign inv_sbox[8'h14] = 8'h9b;
+ assign inv_sbox[8'h15] = 8'h2f;
+ assign inv_sbox[8'h16] = 8'hff;
+ assign inv_sbox[8'h17] = 8'h87;
+ assign inv_sbox[8'h18] = 8'h34;
+ assign inv_sbox[8'h19] = 8'h8e;
+ assign inv_sbox[8'h1a] = 8'h43;
+ assign inv_sbox[8'h1b] = 8'h44;
+ assign inv_sbox[8'h1c] = 8'hc4;
+ assign inv_sbox[8'h1d] = 8'hde;
+ assign inv_sbox[8'h1e] = 8'he9;
+ assign inv_sbox[8'h1f] = 8'hcb;
+ assign inv_sbox[8'h20] = 8'h54;
+ assign inv_sbox[8'h21] = 8'h7b;
+ assign inv_sbox[8'h22] = 8'h94;
+ assign inv_sbox[8'h23] = 8'h32;
+ assign inv_sbox[8'h24] = 8'ha6;
+ assign inv_sbox[8'h25] = 8'hc2;
+ assign inv_sbox[8'h26] = 8'h23;
+ assign inv_sbox[8'h27] = 8'h3d;
+ assign inv_sbox[8'h28] = 8'hee;
+ assign inv_sbox[8'h29] = 8'h4c;
+ assign inv_sbox[8'h2a] = 8'h95;
+ assign inv_sbox[8'h2b] = 8'h0b;
+ assign inv_sbox[8'h2c] = 8'h42;
+ assign inv_sbox[8'h2d] = 8'hfa;
+ assign inv_sbox[8'h2e] = 8'hc3;
+ assign inv_sbox[8'h2f] = 8'h4e;
+ assign inv_sbox[8'h30] = 8'h08;
+ assign inv_sbox[8'h31] = 8'h2e;
+ assign inv_sbox[8'h32] = 8'ha1;
+ assign inv_sbox[8'h33] = 8'h66;
+ assign inv_sbox[8'h34] = 8'h28;
+ assign inv_sbox[8'h35] = 8'hd9;
+ assign inv_sbox[8'h36] = 8'h24;
+ assign inv_sbox[8'h37] = 8'hb2;
+ assign inv_sbox[8'h38] = 8'h76;
+ assign inv_sbox[8'h39] = 8'h5b;
+ assign inv_sbox[8'h3a] = 8'ha2;
+ assign inv_sbox[8'h3b] = 8'h49;
+ assign inv_sbox[8'h3c] = 8'h6d;
+ assign inv_sbox[8'h3d] = 8'h8b;
+ assign inv_sbox[8'h3e] = 8'hd1;
+ assign inv_sbox[8'h3f] = 8'h25;
+ assign inv_sbox[8'h40] = 8'h72;
+ assign inv_sbox[8'h41] = 8'hf8;
+ assign inv_sbox[8'h42] = 8'hf6;
+ assign inv_sbox[8'h43] = 8'h64;
+ assign inv_sbox[8'h44] = 8'h86;
+ assign inv_sbox[8'h45] = 8'h68;
+ assign inv_sbox[8'h46] = 8'h98;
+ assign inv_sbox[8'h47] = 8'h16;
+ assign inv_sbox[8'h48] = 8'hd4;
+ assign inv_sbox[8'h49] = 8'ha4;
+ assign inv_sbox[8'h4a] = 8'h5c;
+ assign inv_sbox[8'h4b] = 8'hcc;
+ assign inv_sbox[8'h4c] = 8'h5d;
+ assign inv_sbox[8'h4d] = 8'h65;
+ assign inv_sbox[8'h4e] = 8'hb6;
+ assign inv_sbox[8'h4f] = 8'h92;
+ assign inv_sbox[8'h50] = 8'h6c;
+ assign inv_sbox[8'h51] = 8'h70;
+ assign inv_sbox[8'h52] = 8'h48;
+ assign inv_sbox[8'h53] = 8'h50;
+ assign inv_sbox[8'h54] = 8'hfd;
+ assign inv_sbox[8'h55] = 8'hed;
+ assign inv_sbox[8'h56] = 8'hb9;
+ assign inv_sbox[8'h57] = 8'hda;
+ assign inv_sbox[8'h58] = 8'h5e;
+ assign inv_sbox[8'h59] = 8'h15;
+ assign inv_sbox[8'h5a] = 8'h46;
+ assign inv_sbox[8'h5b] = 8'h57;
+ assign inv_sbox[8'h5c] = 8'ha7;
+ assign inv_sbox[8'h5d] = 8'h8d;
+ assign inv_sbox[8'h5e] = 8'h9d;
+ assign inv_sbox[8'h5f] = 8'h84;
+ assign inv_sbox[8'h60] = 8'h90;
+ assign inv_sbox[8'h61] = 8'hd8;
+ assign inv_sbox[8'h62] = 8'hab;
+ assign inv_sbox[8'h63] = 8'h00;
+ assign inv_sbox[8'h64] = 8'h8c;
+ assign inv_sbox[8'h65] = 8'hbc;
+ assign inv_sbox[8'h66] = 8'hd3;
+ assign inv_sbox[8'h67] = 8'h0a;
+ assign inv_sbox[8'h68] = 8'hf7;
+ assign inv_sbox[8'h69] = 8'he4;
+ assign inv_sbox[8'h6a] = 8'h58;
+ assign inv_sbox[8'h6b] = 8'h05;
+ assign inv_sbox[8'h6c] = 8'hb8;
+ assign inv_sbox[8'h6d] = 8'hb3;
+ assign inv_sbox[8'h6e] = 8'h45;
+ assign inv_sbox[8'h6f] = 8'h06;
+ assign inv_sbox[8'h70] = 8'hd0;
+ assign inv_sbox[8'h71] = 8'h2c;
+ assign inv_sbox[8'h72] = 8'h1e;
+ assign inv_sbox[8'h73] = 8'h8f;
+ assign inv_sbox[8'h74] = 8'hca;
+ assign inv_sbox[8'h75] = 8'h3f;
+ assign inv_sbox[8'h76] = 8'h0f;
+ assign inv_sbox[8'h77] = 8'h02;
+ assign inv_sbox[8'h78] = 8'hc1;
+ assign inv_sbox[8'h79] = 8'haf;
+ assign inv_sbox[8'h7a] = 8'hbd;
+ assign inv_sbox[8'h7b] = 8'h03;
+ assign inv_sbox[8'h7c] = 8'h01;
+ assign inv_sbox[8'h7d] = 8'h13;
+ assign inv_sbox[8'h7e] = 8'h8a;
+ assign inv_sbox[8'h7f] = 8'h6b;
+ assign inv_sbox[8'h80] = 8'h3a;
+ assign inv_sbox[8'h81] = 8'h91;
+ assign inv_sbox[8'h82] = 8'h11;
+ assign inv_sbox[8'h83] = 8'h41;
+ assign inv_sbox[8'h84] = 8'h4f;
+ assign inv_sbox[8'h85] = 8'h67;
+ assign inv_sbox[8'h86] = 8'hdc;
+ assign inv_sbox[8'h87] = 8'hea;
+ assign inv_sbox[8'h88] = 8'h97;
+ assign inv_sbox[8'h89] = 8'hf2;
+ assign inv_sbox[8'h8a] = 8'hcf;
+ assign inv_sbox[8'h8b] = 8'hce;
+ assign inv_sbox[8'h8c] = 8'hf0;
+ assign inv_sbox[8'h8d] = 8'hb4;
+ assign inv_sbox[8'h8e] = 8'he6;
+ assign inv_sbox[8'h8f] = 8'h73;
+ assign inv_sbox[8'h90] = 8'h96;
+ assign inv_sbox[8'h91] = 8'hac;
+ assign inv_sbox[8'h92] = 8'h74;
+ assign inv_sbox[8'h93] = 8'h22;
+ assign inv_sbox[8'h94] = 8'he7;
+ assign inv_sbox[8'h95] = 8'had;
+ assign inv_sbox[8'h96] = 8'h35;
+ assign inv_sbox[8'h97] = 8'h85;
+ assign inv_sbox[8'h98] = 8'he2;
+ assign inv_sbox[8'h99] = 8'hf9;
+ assign inv_sbox[8'h9a] = 8'h37;
+ assign inv_sbox[8'h9b] = 8'he8;
+ assign inv_sbox[8'h9c] = 8'h1c;
+ assign inv_sbox[8'h9d] = 8'h75;
+ assign inv_sbox[8'h9e] = 8'hdf;
+ assign inv_sbox[8'h9f] = 8'h6e;
+ assign inv_sbox[8'ha0] = 8'h47;
+ assign inv_sbox[8'ha1] = 8'hf1;
+ assign inv_sbox[8'ha2] = 8'h1a;
+ assign inv_sbox[8'ha3] = 8'h71;
+ assign inv_sbox[8'ha4] = 8'h1d;
+ assign inv_sbox[8'ha5] = 8'h29;
+ assign inv_sbox[8'ha6] = 8'hc5;
+ assign inv_sbox[8'ha7] = 8'h89;
+ assign inv_sbox[8'ha8] = 8'h6f;
+ assign inv_sbox[8'ha9] = 8'hb7;
+ assign inv_sbox[8'haa] = 8'h62;
+ assign inv_sbox[8'hab] = 8'h0e;
+ assign inv_sbox[8'hac] = 8'haa;
+ assign inv_sbox[8'had] = 8'h18;
+ assign inv_sbox[8'hae] = 8'hbe;
+ assign inv_sbox[8'haf] = 8'h1b;
+ assign inv_sbox[8'hb0] = 8'hfc;
+ assign inv_sbox[8'hb1] = 8'h56;
+ assign inv_sbox[8'hb2] = 8'h3e;
+ assign inv_sbox[8'hb3] = 8'h4b;
+ assign inv_sbox[8'hb4] = 8'hc6;
+ assign inv_sbox[8'hb5] = 8'hd2;
+ assign inv_sbox[8'hb6] = 8'h79;
+ assign inv_sbox[8'hb7] = 8'h20;
+ assign inv_sbox[8'hb8] = 8'h9a;
+ assign inv_sbox[8'hb9] = 8'hdb;
+ assign inv_sbox[8'hba] = 8'hc0;
+ assign inv_sbox[8'hbb] = 8'hfe;
+ assign inv_sbox[8'hbc] = 8'h78;
+ assign inv_sbox[8'hbd] = 8'hcd;
+ assign inv_sbox[8'hbe] = 8'h5a;
+ assign inv_sbox[8'hbf] = 8'hf4;
+ assign inv_sbox[8'hc0] = 8'h1f;
+ assign inv_sbox[8'hc1] = 8'hdd;
+ assign inv_sbox[8'hc2] = 8'ha8;
+ assign inv_sbox[8'hc3] = 8'h33;
+ assign inv_sbox[8'hc4] = 8'h88;
+ assign inv_sbox[8'hc5] = 8'h07;
+ assign inv_sbox[8'hc6] = 8'hc7;
+ assign inv_sbox[8'hc7] = 8'h31;
+ assign inv_sbox[8'hc8] = 8'hb1;
+ assign inv_sbox[8'hc9] = 8'h12;
+ assign inv_sbox[8'hca] = 8'h10;
+ assign inv_sbox[8'hcb] = 8'h59;
+ assign inv_sbox[8'hcc] = 8'h27;
+ assign inv_sbox[8'hcd] = 8'h80;
+ assign inv_sbox[8'hce] = 8'hec;
+ assign inv_sbox[8'hcf] = 8'h5f;
+ assign inv_sbox[8'hd0] = 8'h60;
+ assign inv_sbox[8'hd1] = 8'h51;
+ assign inv_sbox[8'hd2] = 8'h7f;
+ assign inv_sbox[8'hd3] = 8'ha9;
+ assign inv_sbox[8'hd4] = 8'h19;
+ assign inv_sbox[8'hd5] = 8'hb5;
+ assign inv_sbox[8'hd6] = 8'h4a;
+ assign inv_sbox[8'hd7] = 8'h0d;
+ assign inv_sbox[8'hd8] = 8'h2d;
+ assign inv_sbox[8'hd9] = 8'he5;
+ assign inv_sbox[8'hda] = 8'h7a;
+ assign inv_sbox[8'hdb] = 8'h9f;
+ assign inv_sbox[8'hdc] = 8'h93;
+ assign inv_sbox[8'hdd] = 8'hc9;
+ assign inv_sbox[8'hde] = 8'h9c;
+ assign inv_sbox[8'hdf] = 8'hef;
+ assign inv_sbox[8'he0] = 8'ha0;
+ assign inv_sbox[8'he1] = 8'he0;
+ assign inv_sbox[8'he2] = 8'h3b;
+ assign inv_sbox[8'he3] = 8'h4d;
+ assign inv_sbox[8'he4] = 8'hae;
+ assign inv_sbox[8'he5] = 8'h2a;
+ assign inv_sbox[8'he6] = 8'hf5;
+ assign inv_sbox[8'he7] = 8'hb0;
+ assign inv_sbox[8'he8] = 8'hc8;
+ assign inv_sbox[8'he9] = 8'heb;
+ assign inv_sbox[8'hea] = 8'hbb;
+ assign inv_sbox[8'heb] = 8'h3c;
+ assign inv_sbox[8'hec] = 8'h83;
+ assign inv_sbox[8'hed] = 8'h53;
+ assign inv_sbox[8'hee] = 8'h99;
+ assign inv_sbox[8'hef] = 8'h61;
+ assign inv_sbox[8'hf0] = 8'h17;
+ assign inv_sbox[8'hf1] = 8'h2b;
+ assign inv_sbox[8'hf2] = 8'h04;
+ assign inv_sbox[8'hf3] = 8'h7e;
+ assign inv_sbox[8'hf4] = 8'hba;
+ assign inv_sbox[8'hf5] = 8'h77;
+ assign inv_sbox[8'hf6] = 8'hd6;
+ assign inv_sbox[8'hf7] = 8'h26;
+ assign inv_sbox[8'hf8] = 8'he1;
+ assign inv_sbox[8'hf9] = 8'h69;
+ assign inv_sbox[8'hfa] = 8'h14;
+ assign inv_sbox[8'hfb] = 8'h63;
+ assign inv_sbox[8'hfc] = 8'h55;
+ assign inv_sbox[8'hfd] = 8'h21;
+ assign inv_sbox[8'hfe] = 8'h0c;
+ assign inv_sbox[8'hff] = 8'h7d;
+
+endmodule // aes_inv_sbox
+
+//======================================================================
+// EOF aes_inv_sbox.v
+//======================================================================
+
+
+//======================================================================
+//
+// aes_key_mem.v
+// -------------
+// The AES key memory including round key generator.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_key_mem(
+ input wire clk,
+ input wire reset_n,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+ input wire init,
+
+ input wire [3 : 0] round,
+ output wire [127 : 0] round_key,
+ output wire ready,
+
+
+ output wire [31 : 0] sboxw,
+ input wire [31 : 0] new_sboxw
+ );
+
+
+ //----------------------------------------------------------------
+ // Parameters.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES_128_NUM_ROUNDS = 10;
+ localparam AES_256_NUM_ROUNDS = 14;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_GENERATE = 3'h2;
+ localparam CTRL_DONE = 3'h3;
+
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [127 : 0] key_mem [0 : 14];
+ reg [127 : 0] key_mem_new;
+ reg key_mem_we;
+
+ reg [127 : 0] prev_key0_reg;
+ reg [127 : 0] prev_key0_new;
+ reg prev_key0_we;
+
+ reg [127 : 0] prev_key1_reg;
+ reg [127 : 0] prev_key1_new;
+ reg prev_key1_we;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_rst;
+ reg round_ctr_inc;
+ reg round_ctr_we;
+
+ reg [2 : 0] key_mem_ctrl_reg;
+ reg [2 : 0] key_mem_ctrl_new;
+ reg key_mem_ctrl_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [7 : 0] rcon_reg;
+ reg [7 : 0] rcon_new;
+ reg rcon_we;
+ reg rcon_set;
+ reg rcon_next;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_sboxw;
+ reg round_key_update;
+ reg [127 : 0] tmp_round_key;
+
+
+ //----------------------------------------------------------------
+ // Concurrent assignments for ports.
+ //----------------------------------------------------------------
+ assign round_key = tmp_round_key;
+ assign ready = ready_reg;
+ assign sboxw = tmp_sboxw;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i <= AES_256_NUM_ROUNDS ; i = i + 1)
+ key_mem [i] <= 128'h0;
+
+ rcon_reg <= 8'h0;
+ ready_reg <= 1'b0;
+ round_ctr_reg <= 4'h0;
+ key_mem_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (rcon_we)
+ rcon_reg <= rcon_new;
+
+ if (key_mem_we)
+ key_mem[round_ctr_reg] <= key_mem_new;
+
+ if (prev_key0_we)
+ prev_key0_reg <= prev_key0_new;
+
+ if (prev_key1_we)
+ prev_key1_reg <= prev_key1_new;
+
+ if (key_mem_ctrl_we)
+ key_mem_ctrl_reg <= key_mem_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // key_mem_read
+ //
+ // Combinational read port for the key memory.
+ //----------------------------------------------------------------
+ always @*
+ begin : key_mem_read
+ tmp_round_key = key_mem[round];
+ end // key_mem_read
+
+
+ //----------------------------------------------------------------
+ // round_key_gen
+ //
+ // The round key generator logic for AES-128 and AES-256.
+ //----------------------------------------------------------------
+ always @*
+ begin: round_key_gen
+ reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
+ reg [31 : 0] k0, k1, k2, k3;
+ reg [31 : 0] rconw, rotstw, tw, trw;
+
+ // Default assignments.
+ key_mem_new = 128'h0;
+ key_mem_we = 1'b0;
+ prev_key0_new = 128'h0;
+ prev_key0_we = 1'b0;
+ prev_key1_new = 128'h0;
+ prev_key1_we = 1'b0;
+
+ k0 = 32'h0;
+ k1 = 32'h0;
+ k2 = 32'h0;
+ k3 = 32'h0;
+
+ rcon_set = 1'b1;
+ rcon_next = 1'b0;
+
+ // Extract words and calculate intermediate values.
+ // Perform rotation of sbox word etc.
+ w0 = prev_key0_reg[127 : 096];
+ w1 = prev_key0_reg[095 : 064];
+ w2 = prev_key0_reg[063 : 032];
+ w3 = prev_key0_reg[031 : 000];
+
+ w4 = prev_key1_reg[127 : 096];
+ w5 = prev_key1_reg[095 : 064];
+ w6 = prev_key1_reg[063 : 032];
+ w7 = prev_key1_reg[031 : 000];
+
+ rconw = {rcon_reg, 24'h0};
+ tmp_sboxw = w7;
+ rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
+ trw = rotstw ^ rconw;
+ tw = new_sboxw;
+
+ // Generate the specific round keys.
+ if (round_key_update)
+ begin
+ rcon_set = 1'b0;
+ key_mem_we = 1'b1;
+ case (keylen)
+ AES_128_BIT_KEY:
+ begin
+ if (round_ctr_reg == 0)
+ begin
+ key_mem_new = key[255 : 128];
+ prev_key1_new = key[255 : 128];
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ else
+ begin
+ k0 = w4 ^ trw;
+ k1 = w5 ^ w4 ^ trw;
+ k2 = w6 ^ w5 ^ w4 ^ trw;
+ k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
+
+ key_mem_new = {k0, k1, k2, k3};
+ prev_key1_new = {k0, k1, k2, k3};
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ end
+
+ AES_256_BIT_KEY:
+ begin
+ if (round_ctr_reg == 0)
+ begin
+ key_mem_new = key[255 : 128];
+ prev_key0_new = key[255 : 128];
+ prev_key0_we = 1'b1;
+ end
+ else if (round_ctr_reg == 1)
+ begin
+ key_mem_new = key[127 : 0];
+ prev_key1_new = key[127 : 0];
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ else
+ begin
+ if (round_ctr_reg[0] == 0)
+ begin
+ k0 = w0 ^ trw;
+ k1 = w1 ^ w0 ^ trw;
+ k2 = w2 ^ w1 ^ w0 ^ trw;
+ k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
+ end
+ else
+ begin
+ k0 = w0 ^ tw;
+ k1 = w1 ^ w0 ^ tw;
+ k2 = w2 ^ w1 ^ w0 ^ tw;
+ k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
+ rcon_next = 1'b1;
+ end
+
+ // Store the generated round keys.
+ key_mem_new = {k0, k1, k2, k3};
+ prev_key1_new = {k0, k1, k2, k3};
+ prev_key1_we = 1'b1;
+ prev_key0_new = prev_key1_reg;
+ prev_key0_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ end
+ endcase // case (keylen)
+ end
+ end // round_key_gen
+
+
+ //----------------------------------------------------------------
+ // rcon_logic
+ //
+ // Caclulates the rcon value for the different key expansion
+ // iterations.
+ //----------------------------------------------------------------
+ always @*
+ begin : rcon_logic
+ reg [7 : 0] tmp_rcon;
+ rcon_new = 8'h00;
+ rcon_we = 1'b0;
+
+ tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
+
+ if (rcon_set)
+ begin
+ rcon_new = 8'h8d;
+ rcon_we = 1'b1;
+ end
+
+ if (rcon_next)
+ begin
+ rcon_new = tmp_rcon[7 : 0];
+ rcon_we = 1'b1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter logic with increase and reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_rst)
+ begin
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b1;
+ end
+
+ else if (round_ctr_inc)
+ begin
+ round_ctr_new = round_ctr_reg + 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // key_mem_ctrl
+ //
+ //
+ // The FSM that controls the round key generation.
+ //----------------------------------------------------------------
+ always @*
+ begin: key_mem_ctrl
+ reg [3 : 0] num_rounds;
+
+ // Default assignments.
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ round_key_update = 1'b0;
+ round_ctr_rst = 1'b0;
+ round_ctr_inc = 1'b0;
+ key_mem_ctrl_new = CTRL_IDLE;
+ key_mem_ctrl_we = 1'b0;
+
+ if (keylen == AES_128_BIT_KEY)
+ num_rounds = AES_128_NUM_ROUNDS;
+ else
+ num_rounds = AES_256_NUM_ROUNDS;
+
+ case(key_mem_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ key_mem_ctrl_new = CTRL_INIT;
+ key_mem_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ round_ctr_rst = 1'b1;
+ key_mem_ctrl_new = CTRL_GENERATE;
+ key_mem_ctrl_we = 1'b1;
+ end
+
+ CTRL_GENERATE:
+ begin
+ round_ctr_inc = 1'b1;
+ round_key_update = 1'b1;
+ if (round_ctr_reg == num_rounds)
+ begin
+ key_mem_ctrl_new = CTRL_DONE;
+ key_mem_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_DONE:
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ key_mem_ctrl_new = CTRL_IDLE;
+ key_mem_ctrl_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (key_mem_ctrl_reg)
+
+ end // key_mem_ctrl
+endmodule // aes_key_mem
+
+//======================================================================
+// EOF aes_key_mem.v
+//======================================================================
+
+//======================================================================
+//
+// aes_sbox.v
+// ----------
+// The AES S-box. Basically a 256 Byte ROM. This implementation
+// contains four parallel S-boxes to handle a 32 bit word.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_sbox(
+ input wire [31 : 0] sboxw,
+ output wire [31 : 0] new_sboxw
+ );
+
+
+ //----------------------------------------------------------------
+ // The sbox array.
+ //----------------------------------------------------------------
+ wire [7 : 0] sbox [0 : 255];
+
+
+ //----------------------------------------------------------------
+ // Four parallel muxes.
+ //----------------------------------------------------------------
+ assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]];
+ assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]];
+ assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]];
+ assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]];
+
+
+ //----------------------------------------------------------------
+ // Creating the sbox array contents.
+ //----------------------------------------------------------------
+ assign sbox[8'h00] = 8'h63;
+ assign sbox[8'h01] = 8'h7c;
+ assign sbox[8'h02] = 8'h77;
+ assign sbox[8'h03] = 8'h7b;
+ assign sbox[8'h04] = 8'hf2;
+ assign sbox[8'h05] = 8'h6b;
+ assign sbox[8'h06] = 8'h6f;
+ assign sbox[8'h07] = 8'hc5;
+ assign sbox[8'h08] = 8'h30;
+ assign sbox[8'h09] = 8'h01;
+ assign sbox[8'h0a] = 8'h67;
+ assign sbox[8'h0b] = 8'h2b;
+ assign sbox[8'h0c] = 8'hfe;
+ assign sbox[8'h0d] = 8'hd7;
+ assign sbox[8'h0e] = 8'hab;
+ assign sbox[8'h0f] = 8'h76;
+ assign sbox[8'h10] = 8'hca;
+ assign sbox[8'h11] = 8'h82;
+ assign sbox[8'h12] = 8'hc9;
+ assign sbox[8'h13] = 8'h7d;
+ assign sbox[8'h14] = 8'hfa;
+ assign sbox[8'h15] = 8'h59;
+ assign sbox[8'h16] = 8'h47;
+ assign sbox[8'h17] = 8'hf0;
+ assign sbox[8'h18] = 8'had;
+ assign sbox[8'h19] = 8'hd4;
+ assign sbox[8'h1a] = 8'ha2;
+ assign sbox[8'h1b] = 8'haf;
+ assign sbox[8'h1c] = 8'h9c;
+ assign sbox[8'h1d] = 8'ha4;
+ assign sbox[8'h1e] = 8'h72;
+ assign sbox[8'h1f] = 8'hc0;
+ assign sbox[8'h20] = 8'hb7;
+ assign sbox[8'h21] = 8'hfd;
+ assign sbox[8'h22] = 8'h93;
+ assign sbox[8'h23] = 8'h26;
+ assign sbox[8'h24] = 8'h36;
+ assign sbox[8'h25] = 8'h3f;
+ assign sbox[8'h26] = 8'hf7;
+ assign sbox[8'h27] = 8'hcc;
+ assign sbox[8'h28] = 8'h34;
+ assign sbox[8'h29] = 8'ha5;
+ assign sbox[8'h2a] = 8'he5;
+ assign sbox[8'h2b] = 8'hf1;
+ assign sbox[8'h2c] = 8'h71;
+ assign sbox[8'h2d] = 8'hd8;
+ assign sbox[8'h2e] = 8'h31;
+ assign sbox[8'h2f] = 8'h15;
+ assign sbox[8'h30] = 8'h04;
+ assign sbox[8'h31] = 8'hc7;
+ assign sbox[8'h32] = 8'h23;
+ assign sbox[8'h33] = 8'hc3;
+ assign sbox[8'h34] = 8'h18;
+ assign sbox[8'h35] = 8'h96;
+ assign sbox[8'h36] = 8'h05;
+ assign sbox[8'h37] = 8'h9a;
+ assign sbox[8'h38] = 8'h07;
+ assign sbox[8'h39] = 8'h12;
+ assign sbox[8'h3a] = 8'h80;
+ assign sbox[8'h3b] = 8'he2;
+ assign sbox[8'h3c] = 8'heb;
+ assign sbox[8'h3d] = 8'h27;
+ assign sbox[8'h3e] = 8'hb2;
+ assign sbox[8'h3f] = 8'h75;
+ assign sbox[8'h40] = 8'h09;
+ assign sbox[8'h41] = 8'h83;
+ assign sbox[8'h42] = 8'h2c;
+ assign sbox[8'h43] = 8'h1a;
+ assign sbox[8'h44] = 8'h1b;
+ assign sbox[8'h45] = 8'h6e;
+ assign sbox[8'h46] = 8'h5a;
+ assign sbox[8'h47] = 8'ha0;
+ assign sbox[8'h48] = 8'h52;
+ assign sbox[8'h49] = 8'h3b;
+ assign sbox[8'h4a] = 8'hd6;
+ assign sbox[8'h4b] = 8'hb3;
+ assign sbox[8'h4c] = 8'h29;
+ assign sbox[8'h4d] = 8'he3;
+ assign sbox[8'h4e] = 8'h2f;
+ assign sbox[8'h4f] = 8'h84;
+ assign sbox[8'h50] = 8'h53;
+ assign sbox[8'h51] = 8'hd1;
+ assign sbox[8'h52] = 8'h00;
+ assign sbox[8'h53] = 8'hed;
+ assign sbox[8'h54] = 8'h20;
+ assign sbox[8'h55] = 8'hfc;
+ assign sbox[8'h56] = 8'hb1;
+ assign sbox[8'h57] = 8'h5b;
+ assign sbox[8'h58] = 8'h6a;
+ assign sbox[8'h59] = 8'hcb;
+ assign sbox[8'h5a] = 8'hbe;
+ assign sbox[8'h5b] = 8'h39;
+ assign sbox[8'h5c] = 8'h4a;
+ assign sbox[8'h5d] = 8'h4c;
+ assign sbox[8'h5e] = 8'h58;
+ assign sbox[8'h5f] = 8'hcf;
+ assign sbox[8'h60] = 8'hd0;
+ assign sbox[8'h61] = 8'hef;
+ assign sbox[8'h62] = 8'haa;
+ assign sbox[8'h63] = 8'hfb;
+ assign sbox[8'h64] = 8'h43;
+ assign sbox[8'h65] = 8'h4d;
+ assign sbox[8'h66] = 8'h33;
+ assign sbox[8'h67] = 8'h85;
+ assign sbox[8'h68] = 8'h45;
+ assign sbox[8'h69] = 8'hf9;
+ assign sbox[8'h6a] = 8'h02;
+ assign sbox[8'h6b] = 8'h7f;
+ assign sbox[8'h6c] = 8'h50;
+ assign sbox[8'h6d] = 8'h3c;
+ assign sbox[8'h6e] = 8'h9f;
+ assign sbox[8'h6f] = 8'ha8;
+ assign sbox[8'h70] = 8'h51;
+ assign sbox[8'h71] = 8'ha3;
+ assign sbox[8'h72] = 8'h40;
+ assign sbox[8'h73] = 8'h8f;
+ assign sbox[8'h74] = 8'h92;
+ assign sbox[8'h75] = 8'h9d;
+ assign sbox[8'h76] = 8'h38;
+ assign sbox[8'h77] = 8'hf5;
+ assign sbox[8'h78] = 8'hbc;
+ assign sbox[8'h79] = 8'hb6;
+ assign sbox[8'h7a] = 8'hda;
+ assign sbox[8'h7b] = 8'h21;
+ assign sbox[8'h7c] = 8'h10;
+ assign sbox[8'h7d] = 8'hff;
+ assign sbox[8'h7e] = 8'hf3;
+ assign sbox[8'h7f] = 8'hd2;
+ assign sbox[8'h80] = 8'hcd;
+ assign sbox[8'h81] = 8'h0c;
+ assign sbox[8'h82] = 8'h13;
+ assign sbox[8'h83] = 8'hec;
+ assign sbox[8'h84] = 8'h5f;
+ assign sbox[8'h85] = 8'h97;
+ assign sbox[8'h86] = 8'h44;
+ assign sbox[8'h87] = 8'h17;
+ assign sbox[8'h88] = 8'hc4;
+ assign sbox[8'h89] = 8'ha7;
+ assign sbox[8'h8a] = 8'h7e;
+ assign sbox[8'h8b] = 8'h3d;
+ assign sbox[8'h8c] = 8'h64;
+ assign sbox[8'h8d] = 8'h5d;
+ assign sbox[8'h8e] = 8'h19;
+ assign sbox[8'h8f] = 8'h73;
+ assign sbox[8'h90] = 8'h60;
+ assign sbox[8'h91] = 8'h81;
+ assign sbox[8'h92] = 8'h4f;
+ assign sbox[8'h93] = 8'hdc;
+ assign sbox[8'h94] = 8'h22;
+ assign sbox[8'h95] = 8'h2a;
+ assign sbox[8'h96] = 8'h90;
+ assign sbox[8'h97] = 8'h88;
+ assign sbox[8'h98] = 8'h46;
+ assign sbox[8'h99] = 8'hee;
+ assign sbox[8'h9a] = 8'hb8;
+ assign sbox[8'h9b] = 8'h14;
+ assign sbox[8'h9c] = 8'hde;
+ assign sbox[8'h9d] = 8'h5e;
+ assign sbox[8'h9e] = 8'h0b;
+ assign sbox[8'h9f] = 8'hdb;
+ assign sbox[8'ha0] = 8'he0;
+ assign sbox[8'ha1] = 8'h32;
+ assign sbox[8'ha2] = 8'h3a;
+ assign sbox[8'ha3] = 8'h0a;
+ assign sbox[8'ha4] = 8'h49;
+ assign sbox[8'ha5] = 8'h06;
+ assign sbox[8'ha6] = 8'h24;
+ assign sbox[8'ha7] = 8'h5c;
+ assign sbox[8'ha8] = 8'hc2;
+ assign sbox[8'ha9] = 8'hd3;
+ assign sbox[8'haa] = 8'hac;
+ assign sbox[8'hab] = 8'h62;
+ assign sbox[8'hac] = 8'h91;
+ assign sbox[8'had] = 8'h95;
+ assign sbox[8'hae] = 8'he4;
+ assign sbox[8'haf] = 8'h79;
+ assign sbox[8'hb0] = 8'he7;
+ assign sbox[8'hb1] = 8'hc8;
+ assign sbox[8'hb2] = 8'h37;
+ assign sbox[8'hb3] = 8'h6d;
+ assign sbox[8'hb4] = 8'h8d;
+ assign sbox[8'hb5] = 8'hd5;
+ assign sbox[8'hb6] = 8'h4e;
+ assign sbox[8'hb7] = 8'ha9;
+ assign sbox[8'hb8] = 8'h6c;
+ assign sbox[8'hb9] = 8'h56;
+ assign sbox[8'hba] = 8'hf4;
+ assign sbox[8'hbb] = 8'hea;
+ assign sbox[8'hbc] = 8'h65;
+ assign sbox[8'hbd] = 8'h7a;
+ assign sbox[8'hbe] = 8'hae;
+ assign sbox[8'hbf] = 8'h08;
+ assign sbox[8'hc0] = 8'hba;
+ assign sbox[8'hc1] = 8'h78;
+ assign sbox[8'hc2] = 8'h25;
+ assign sbox[8'hc3] = 8'h2e;
+ assign sbox[8'hc4] = 8'h1c;
+ assign sbox[8'hc5] = 8'ha6;
+ assign sbox[8'hc6] = 8'hb4;
+ assign sbox[8'hc7] = 8'hc6;
+ assign sbox[8'hc8] = 8'he8;
+ assign sbox[8'hc9] = 8'hdd;
+ assign sbox[8'hca] = 8'h74;
+ assign sbox[8'hcb] = 8'h1f;
+ assign sbox[8'hcc] = 8'h4b;
+ assign sbox[8'hcd] = 8'hbd;
+ assign sbox[8'hce] = 8'h8b;
+ assign sbox[8'hcf] = 8'h8a;
+ assign sbox[8'hd0] = 8'h70;
+ assign sbox[8'hd1] = 8'h3e;
+ assign sbox[8'hd2] = 8'hb5;
+ assign sbox[8'hd3] = 8'h66;
+ assign sbox[8'hd4] = 8'h48;
+ assign sbox[8'hd5] = 8'h03;
+ assign sbox[8'hd6] = 8'hf6;
+ assign sbox[8'hd7] = 8'h0e;
+ assign sbox[8'hd8] = 8'h61;
+ assign sbox[8'hd9] = 8'h35;
+ assign sbox[8'hda] = 8'h57;
+ assign sbox[8'hdb] = 8'hb9;
+ assign sbox[8'hdc] = 8'h86;
+ assign sbox[8'hdd] = 8'hc1;
+ assign sbox[8'hde] = 8'h1d;
+ assign sbox[8'hdf] = 8'h9e;
+ assign sbox[8'he0] = 8'he1;
+ assign sbox[8'he1] = 8'hf8;
+ assign sbox[8'he2] = 8'h98;
+ assign sbox[8'he3] = 8'h11;
+ assign sbox[8'he4] = 8'h69;
+ assign sbox[8'he5] = 8'hd9;
+ assign sbox[8'he6] = 8'h8e;
+ assign sbox[8'he7] = 8'h94;
+ assign sbox[8'he8] = 8'h9b;
+ assign sbox[8'he9] = 8'h1e;
+ assign sbox[8'hea] = 8'h87;
+ assign sbox[8'heb] = 8'he9;
+ assign sbox[8'hec] = 8'hce;
+ assign sbox[8'hed] = 8'h55;
+ assign sbox[8'hee] = 8'h28;
+ assign sbox[8'hef] = 8'hdf;
+ assign sbox[8'hf0] = 8'h8c;
+ assign sbox[8'hf1] = 8'ha1;
+ assign sbox[8'hf2] = 8'h89;
+ assign sbox[8'hf3] = 8'h0d;
+ assign sbox[8'hf4] = 8'hbf;
+ assign sbox[8'hf5] = 8'he6;
+ assign sbox[8'hf6] = 8'h42;
+ assign sbox[8'hf7] = 8'h68;
+ assign sbox[8'hf8] = 8'h41;
+ assign sbox[8'hf9] = 8'h99;
+ assign sbox[8'hfa] = 8'h2d;
+ assign sbox[8'hfb] = 8'h0f;
+ assign sbox[8'hfc] = 8'hb0;
+ assign sbox[8'hfd] = 8'h54;
+ assign sbox[8'hfe] = 8'hbb;
+ assign sbox[8'hff] = 8'h16;
+
+endmodule // aes_sbox
+
+//======================================================================
+// EOF aes_sbox.v
+//======================================================================
+
+//======================================================================
+//
+// aes_encipher_block.v
+// --------------------
+// The AES encipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// enciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_encipher_block(
+ input wire clk,
+ input wire reset_n,
+
+ input wire next,
+
+ input wire keylen,
+ output wire [3 : 0] round,
+ input wire [127 : 0] round_key,
+
+ output wire [31 : 0] sboxw,
+ input wire [31 : 0] new_sboxw,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] new_block,
+ output wire ready
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES128_ROUNDS = 4'ha;
+ localparam AES256_ROUNDS = 4'he;
+
+ localparam NO_UPDATE = 3'h0;
+ localparam INIT_UPDATE = 3'h1;
+ localparam SBOX_UPDATE = 3'h2;
+ localparam MAIN_UPDATE = 3'h3;
+ localparam FINAL_UPDATE = 3'h4;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_SBOX = 3'h2;
+ localparam CTRL_MAIN = 3'h3;
+ localparam CTRL_FINAL = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Round functions with sub functions.
+ //----------------------------------------------------------------
+ function [7 : 0] gm2(input [7 : 0] op);
+ begin
+ gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+ end
+ endfunction // gm2
+
+ function [7 : 0] gm3(input [7 : 0] op);
+ begin
+ gm3 = gm2(op) ^ op;
+ end
+ endfunction // gm3
+
+ function [31 : 0] mixw(input [31 : 0] w);
+ reg [7 : 0] b0, b1, b2, b3;
+ reg [7 : 0] mb0, mb1, mb2, mb3;
+ begin
+ b0 = w[31 : 24];
+ b1 = w[23 : 16];
+ b2 = w[15 : 08];
+ b3 = w[07 : 00];
+
+ mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
+ mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
+ mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
+ mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
+
+ mixw = {mb0, mb1, mb2, mb3};
+ end
+ endfunction // mixw
+
+ function [127 : 0] mixcolumns(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = mixw(w0);
+ ws1 = mixw(w1);
+ ws2 = mixw(w2);
+ ws3 = mixw(w3);
+
+ mixcolumns = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // mixcolumns
+
+ function [127 : 0] shiftrows(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
+ ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
+ ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
+ ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
+
+ shiftrows = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // shiftrows
+
+ function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+ begin
+ addroundkey = data ^ rkey;
+ end
+ endfunction // addroundkey
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] sword_ctr_reg;
+ reg [1 : 0] sword_ctr_new;
+ reg sword_ctr_we;
+ reg sword_ctr_inc;
+ reg sword_ctr_rst;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_we;
+ reg round_ctr_rst;
+ reg round_ctr_inc;
+
+ reg [127 : 0] block_new;
+ reg [31 : 0] block_w0_reg;
+ reg [31 : 0] block_w1_reg;
+ reg [31 : 0] block_w2_reg;
+ reg [31 : 0] block_w3_reg;
+ reg block_w0_we;
+ reg block_w1_we;
+ reg block_w2_we;
+ reg block_w3_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] enc_ctrl_reg;
+ reg [2 : 0] enc_ctrl_new;
+ reg enc_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [2 : 0] update_type;
+ reg [31 : 0] muxed_sboxw;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign round = round_ctr_reg;
+ assign sboxw = muxed_sboxw;
+ assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ block_w0_reg <= 32'h0;
+ block_w1_reg <= 32'h0;
+ block_w2_reg <= 32'h0;
+ block_w3_reg <= 32'h0;
+ sword_ctr_reg <= 2'h0;
+ round_ctr_reg <= 4'h0;
+ ready_reg <= 1'b1;
+ enc_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (block_w0_we)
+ block_w0_reg <= block_new[127 : 096];
+
+ if (block_w1_we)
+ block_w1_reg <= block_new[095 : 064];
+
+ if (block_w2_we)
+ block_w2_reg <= block_new[063 : 032];
+
+ if (block_w3_we)
+ block_w3_reg <= block_new[031 : 000];
+
+ if (sword_ctr_we)
+ sword_ctr_reg <= sword_ctr_new;
+
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (enc_ctrl_we)
+ enc_ctrl_reg <= enc_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // round_logic
+ //
+ // The logic needed to implement init, main and final rounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_logic
+ reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
+ reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
+
+ block_new = 128'h0;
+ muxed_sboxw = 32'h0;
+ block_w0_we = 1'b0;
+ block_w1_we = 1'b0;
+ block_w2_we = 1'b0;
+ block_w3_we = 1'b0;
+
+ old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ shiftrows_block = shiftrows(old_block);
+ mixcolumns_block = mixcolumns(shiftrows_block);
+ addkey_init_block = addroundkey(block, round_key);
+ addkey_main_block = addroundkey(mixcolumns_block, round_key);
+ addkey_final_block = addroundkey(shiftrows_block, round_key);
+
+ case (update_type)
+ INIT_UPDATE:
+ begin
+ block_new = addkey_init_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ SBOX_UPDATE:
+ begin
+ block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+ case (sword_ctr_reg)
+ 2'h0:
+ begin
+ muxed_sboxw = block_w0_reg;
+ block_w0_we = 1'b1;
+ end
+
+ 2'h1:
+ begin
+ muxed_sboxw = block_w1_reg;
+ block_w1_we = 1'b1;
+ end
+
+ 2'h2:
+ begin
+ muxed_sboxw = block_w2_reg;
+ block_w2_we = 1'b1;
+ end
+
+ 2'h3:
+ begin
+ muxed_sboxw = block_w3_reg;
+ block_w3_we = 1'b1;
+ end
+ endcase // case (sbox_mux_ctrl_reg)
+ end
+
+ MAIN_UPDATE:
+ begin
+ block_new = addkey_main_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ FINAL_UPDATE:
+ begin
+ block_new = addkey_final_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (update_type)
+ end // round_logic
+
+
+ //----------------------------------------------------------------
+ // sword_ctr
+ //
+ // The subbytes word counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : sword_ctr
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b0;
+
+ if (sword_ctr_rst)
+ begin
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b1;
+ end
+ else if (sword_ctr_inc)
+ begin
+ sword_ctr_new = sword_ctr_reg + 1'b1;
+ sword_ctr_we = 1'b1;
+ end
+ end // sword_ctr
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_rst)
+ begin
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b1;
+ end
+ else if (round_ctr_inc)
+ begin
+ round_ctr_new = round_ctr_reg + 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end // round_ctr
+
+
+ //----------------------------------------------------------------
+ // encipher_ctrl
+ //
+ // The FSM that controls the encipher operations.
+ //----------------------------------------------------------------
+ always @*
+ begin: encipher_ctrl
+ reg [3 : 0] num_rounds;
+
+ // Default assignments.
+ sword_ctr_inc = 1'b0;
+ sword_ctr_rst = 1'b0;
+ round_ctr_inc = 1'b0;
+ round_ctr_rst = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ update_type = NO_UPDATE;
+ enc_ctrl_new = CTRL_IDLE;
+ enc_ctrl_we = 1'b0;
+
+ if (keylen == AES_256_BIT_KEY)
+ begin
+ num_rounds = AES256_ROUNDS;
+ end
+ else
+ begin
+ num_rounds = AES128_ROUNDS;
+ end
+
+ case(enc_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (next)
+ begin
+ round_ctr_rst = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ enc_ctrl_new = CTRL_INIT;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ round_ctr_inc = 1'b1;
+ sword_ctr_rst = 1'b1;
+ update_type = INIT_UPDATE;
+ enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_we = 1'b1;
+ end
+
+ CTRL_SBOX:
+ begin
+ sword_ctr_inc = 1'b1;
+ update_type = SBOX_UPDATE;
+ if (sword_ctr_reg == 2'h3)
+ begin
+ enc_ctrl_new = CTRL_MAIN;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_MAIN:
+ begin
+ sword_ctr_rst = 1'b1;
+ round_ctr_inc = 1'b1;
+ if (round_ctr_reg < num_rounds)
+ begin
+ update_type = MAIN_UPDATE;
+ enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_we = 1'b1;
+ end
+ else
+ begin
+ update_type = FINAL_UPDATE;
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ enc_ctrl_new = CTRL_IDLE;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ // Empty. Just here to make the synthesis tool happy.
+ end
+ endcase // case (enc_ctrl_reg)
+ end // encipher_ctrl
+
+endmodule // aes_encipher_block
+
+//======================================================================
+// EOF aes_encipher_block.v
+//======================================================================
+
+
diff --git a/openlane/designs/aes_core/src/aes_core.v b/openlane/designs/aes_core/src/aes_core.v
new file mode 100644
index 0000000..b2c24ba
--- /dev/null
+++ b/openlane/designs/aes_core/src/aes_core.v
@@ -0,0 +1,2708 @@
+//======================================================================
+//
+// aes.v
+// --------
+// Top level wrapper for the AES block cipher core.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CTRL_ENCDEC_BIT = 0;
+ localparam CTRL_KEYLEN_BIT = 1;
+
+ localparam ADDR_KEY0 = 8'h10;
+ localparam ADDR_KEY7 = 8'h17;
+
+ localparam ADDR_BLOCK0 = 8'h20;
+ localparam ADDR_BLOCK3 = 8'h23;
+
+ localparam ADDR_RESULT0 = 8'h30;
+ localparam ADDR_RESULT3 = 8'h33;
+
+ localparam CORE_NAME0 = 32'h61657320; // "aes "
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_VERSION = 32'h302e3630; // "0.60"
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg init_reg;
+ reg init_new;
+
+ reg next_reg;
+ reg next_new;
+
+ reg encdec_reg;
+ reg keylen_reg;
+ reg config_we;
+
+ reg [31 : 0] block_reg [0 : 3];
+ reg block_we;
+
+ reg [31 : 0] key_reg [0 : 7];
+ reg key_we;
+
+ reg [127 : 0] result_reg;
+ reg valid_reg;
+ reg ready_reg;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_read_data;
+
+ wire core_encdec;
+ wire core_init;
+ wire core_next;
+ wire core_ready;
+ wire [255 : 0] core_key;
+ wire core_keylen;
+ wire [127 : 0] core_block;
+ wire [127 : 0] core_result;
+ wire core_valid;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+ assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
+ key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
+
+ assign core_block = {block_reg[0], block_reg[1],
+ block_reg[2], block_reg[3]};
+ assign core_init = init_reg;
+ assign core_next = next_reg;
+ assign core_encdec = encdec_reg;
+ assign core_keylen = keylen_reg;
+
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ aes_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .encdec(core_encdec),
+ .init(core_init),
+ .next(core_next),
+ .ready(core_ready),
+
+ .key(core_key),
+ .keylen(core_keylen),
+
+ .block(core_block),
+ .result(core_result),
+ .result_valid(core_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin : reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i < 4 ; i = i + 1)
+ block_reg[i] <= 32'h0;
+
+ for (i = 0 ; i < 8 ; i = i + 1)
+ key_reg[i] <= 32'h0;
+
+ init_reg <= 1'b0;
+ next_reg <= 1'b0;
+ encdec_reg <= 1'b0;
+ keylen_reg <= 1'b0;
+
+ result_reg <= 128'h0;
+ valid_reg <= 1'b0;
+ ready_reg <= 1'b0;
+ end
+ else
+ begin
+ ready_reg <= core_ready;
+ valid_reg <= core_valid;
+ result_reg <= core_result;
+ init_reg <= init_new;
+ next_reg <= next_new;
+
+ if (config_we)
+ begin
+ encdec_reg <= write_data[CTRL_ENCDEC_BIT];
+ keylen_reg <= write_data[CTRL_KEYLEN_BIT];
+ end
+
+ if (key_we)
+ key_reg[address[2 : 0]] <= write_data;
+
+ if (block_we)
+ block_reg[address[1 : 0]] <= write_data;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // api
+ //
+ // The interface command decoding logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : api
+ init_new = 1'b0;
+ next_new = 1'b0;
+ config_we = 1'b0;
+ key_we = 1'b0;
+ block_we = 1'b0;
+ tmp_read_data = 32'h0;
+
+ if (cs)
+ begin
+ if (we)
+ begin
+ if (address == ADDR_CTRL)
+ begin
+ init_new = write_data[CTRL_INIT_BIT];
+ next_new = write_data[CTRL_NEXT_BIT];
+ end
+
+ if (address == ADDR_CONFIG)
+ config_we = 1'b1;
+
+ if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+ key_we = 1'b1;
+
+ if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
+ block_we = 1'b1;
+ end // if (we)
+
+ else
+ begin
+ case (address)
+ ADDR_NAME0: tmp_read_data = CORE_NAME0;
+ ADDR_NAME1: tmp_read_data = CORE_NAME1;
+ ADDR_VERSION: tmp_read_data = CORE_VERSION;
+ ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+ ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
+
+ default:
+ begin
+ end
+ endcase // case (address)
+
+ if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
+ tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
+ end
+ end
+ end // addr_decoder
+endmodule // aes
+
+//======================================================================
+// EOF aes.v
+//======================================================================
+
+
+//======================================================================
+//
+// aes.core.v
+// ----------
+// The AES core. This core supports key size of 128, and 256 bits.
+// Most of the functionality is within the submodules.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_core(
+ input wire clk,
+ input wire reset_n,
+
+ input wire encdec,
+ input wire init,
+ input wire next,
+ output wire ready,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] result,
+ output wire result_valid
+ );
+
+
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam CTRL_IDLE = 2'h0;
+ localparam CTRL_INIT = 2'h1;
+ localparam CTRL_NEXT = 2'h2;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] aes_core_ctrl_reg;
+ reg [1 : 0] aes_core_ctrl_new;
+ reg aes_core_ctrl_we;
+
+ reg result_valid_reg;
+ reg result_valid_new;
+ reg result_valid_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg init_state;
+
+ wire [127 : 0] round_key;
+ wire key_ready;
+
+ reg enc_next;
+ wire [3 : 0] enc_round_nr;
+ wire [127 : 0] enc_new_block;
+ wire enc_ready;
+ wire [31 : 0] enc_sboxw;
+
+ reg dec_next;
+ wire [3 : 0] dec_round_nr;
+ wire [127 : 0] dec_new_block;
+ wire dec_ready;
+
+ reg [127 : 0] muxed_new_block;
+ reg [3 : 0] muxed_round_nr;
+ reg muxed_ready;
+
+ wire [31 : 0] keymem_sboxw;
+
+ reg [31 : 0] muxed_sboxw;
+ wire [31 : 0] new_sboxw;
+
+
+ //----------------------------------------------------------------
+ // Instantiations.
+ //----------------------------------------------------------------
+ aes_encipher_block enc_block(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .next(enc_next),
+
+ .keylen(keylen),
+ .round(enc_round_nr),
+ .round_key(round_key),
+
+ .sboxw(enc_sboxw),
+ .new_sboxw(new_sboxw),
+
+ .block(block),
+ .new_block(enc_new_block),
+ .ready(enc_ready)
+ );
+
+
+ aes_decipher_block dec_block(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .next(dec_next),
+
+ .keylen(keylen),
+ .round(dec_round_nr),
+ .round_key(round_key),
+
+ .block(block),
+ .new_block(dec_new_block),
+ .ready(dec_ready)
+ );
+
+
+ aes_key_mem keymem(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .key(key),
+ .keylen(keylen),
+ .init(init),
+
+ .round(muxed_round_nr),
+ .round_key(round_key),
+ .ready(key_ready),
+
+ .sboxw(keymem_sboxw),
+ .new_sboxw(new_sboxw)
+ );
+
+
+ aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign ready = ready_reg;
+ assign result = muxed_new_block;
+ assign result_valid = result_valid_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ result_valid_reg <= 1'b0;
+ ready_reg <= 1'b1;
+ aes_core_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (result_valid_we)
+ result_valid_reg <= result_valid_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (aes_core_ctrl_we)
+ aes_core_ctrl_reg <= aes_core_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // sbox_mux
+ //
+ // Controls which of the encipher datapath or the key memory
+ // that gets access to the sbox.
+ //----------------------------------------------------------------
+ always @*
+ begin : sbox_mux
+ if (init_state)
+ begin
+ muxed_sboxw = keymem_sboxw;
+ end
+ else
+ begin
+ muxed_sboxw = enc_sboxw;
+ end
+ end // sbox_mux
+
+
+ //----------------------------------------------------------------
+ // encdex_mux
+ //
+ // Controls which of the datapaths that get the next signal, have
+ // access to the memory as well as the block processing result.
+ //----------------------------------------------------------------
+ always @*
+ begin : encdec_mux
+ enc_next = 1'b0;
+ dec_next = 1'b0;
+
+ if (encdec)
+ begin
+ // Encipher operations
+ enc_next = next;
+ muxed_round_nr = enc_round_nr;
+ muxed_new_block = enc_new_block;
+ muxed_ready = enc_ready;
+ end
+ else
+ begin
+ // Decipher operations
+ dec_next = next;
+ muxed_round_nr = dec_round_nr;
+ muxed_new_block = dec_new_block;
+ muxed_ready = dec_ready;
+ end
+ end // encdec_mux
+
+
+ //----------------------------------------------------------------
+ // aes_core_ctrl
+ //
+ // Control FSM for aes core. Basically tracks if we are in
+ // key init, encipher or decipher modes and connects the
+ // different submodules to shared resources and interface ports.
+ //----------------------------------------------------------------
+ always @*
+ begin : aes_core_ctrl
+ init_state = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b0;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b0;
+
+ case (aes_core_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ init_state = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_INIT;
+ aes_core_ctrl_we = 1'b1;
+ end
+ else if (next)
+ begin
+ init_state = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ result_valid_new = 1'b0;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_NEXT;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ init_state = 1'b1;
+
+ if (key_ready)
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_NEXT:
+ begin
+ init_state = 1'b0;
+
+ if (muxed_ready)
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ result_valid_new = 1'b1;
+ result_valid_we = 1'b1;
+ aes_core_ctrl_new = CTRL_IDLE;
+ aes_core_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+
+ end
+ endcase // case (aes_core_ctrl_reg)
+
+ end // aes_core_ctrl
+endmodule // aes_core
+
+//======================================================================
+// EOF aes_core.v
+//======================================================================
+
+//======================================================================
+//
+// aes_decipher_block.v
+// --------------------
+// The AES decipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// decciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_decipher_block(
+ input wire clk,
+ input wire reset_n,
+
+ input wire next,
+
+ input wire keylen,
+ output wire [3 : 0] round,
+ input wire [127 : 0] round_key,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] new_block,
+ output wire ready
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES128_ROUNDS = 4'ha;
+ localparam AES256_ROUNDS = 4'he;
+
+ localparam NO_UPDATE = 3'h0;
+ localparam INIT_UPDATE = 3'h1;
+ localparam SBOX_UPDATE = 3'h2;
+ localparam MAIN_UPDATE = 3'h3;
+ localparam FINAL_UPDATE = 3'h4;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_SBOX = 3'h2;
+ localparam CTRL_MAIN = 3'h3;
+ localparam CTRL_FINAL = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Gaolis multiplication functions for Inverse MixColumn.
+ //----------------------------------------------------------------
+ function [7 : 0] gm2(input [7 : 0] op);
+ begin
+ gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+ end
+ endfunction // gm2
+
+ function [7 : 0] gm3(input [7 : 0] op);
+ begin
+ gm3 = gm2(op) ^ op;
+ end
+ endfunction // gm3
+
+ function [7 : 0] gm4(input [7 : 0] op);
+ begin
+ gm4 = gm2(gm2(op));
+ end
+ endfunction // gm4
+
+ function [7 : 0] gm8(input [7 : 0] op);
+ begin
+ gm8 = gm2(gm4(op));
+ end
+ endfunction // gm8
+
+ function [7 : 0] gm09(input [7 : 0] op);
+ begin
+ gm09 = gm8(op) ^ op;
+ end
+ endfunction // gm09
+
+ function [7 : 0] gm11(input [7 : 0] op);
+ begin
+ gm11 = gm8(op) ^ gm2(op) ^ op;
+ end
+ endfunction // gm11
+
+ function [7 : 0] gm13(input [7 : 0] op);
+ begin
+ gm13 = gm8(op) ^ gm4(op) ^ op;
+ end
+ endfunction // gm13
+
+ function [7 : 0] gm14(input [7 : 0] op);
+ begin
+ gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
+ end
+ endfunction // gm14
+
+ function [31 : 0] inv_mixw(input [31 : 0] w);
+ reg [7 : 0] b0, b1, b2, b3;
+ reg [7 : 0] mb0, mb1, mb2, mb3;
+ begin
+ b0 = w[31 : 24];
+ b1 = w[23 : 16];
+ b2 = w[15 : 08];
+ b3 = w[07 : 00];
+
+ mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
+ mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
+ mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
+ mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
+
+ inv_mixw = {mb0, mb1, mb2, mb3};
+ end
+ endfunction // mixw
+
+ function [127 : 0] inv_mixcolumns(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = inv_mixw(w0);
+ ws1 = inv_mixw(w1);
+ ws2 = inv_mixw(w2);
+ ws3 = inv_mixw(w3);
+
+ inv_mixcolumns = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // inv_mixcolumns
+
+ function [127 : 0] inv_shiftrows(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
+ ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
+ ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
+ ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
+
+ inv_shiftrows = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // inv_shiftrows
+
+ function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+ begin
+ addroundkey = data ^ rkey;
+ end
+ endfunction // addroundkey
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] sword_ctr_reg;
+ reg [1 : 0] sword_ctr_new;
+ reg sword_ctr_we;
+ reg sword_ctr_inc;
+ reg sword_ctr_rst;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_we;
+ reg round_ctr_set;
+ reg round_ctr_dec;
+
+ reg [127 : 0] block_new;
+ reg [31 : 0] block_w0_reg;
+ reg [31 : 0] block_w1_reg;
+ reg [31 : 0] block_w2_reg;
+ reg [31 : 0] block_w3_reg;
+ reg block_w0_we;
+ reg block_w1_we;
+ reg block_w2_we;
+ reg block_w3_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] dec_ctrl_reg;
+ reg [2 : 0] dec_ctrl_new;
+ reg dec_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_sboxw;
+ wire [31 : 0] new_sboxw;
+ reg [2 : 0] update_type;
+
+
+ //----------------------------------------------------------------
+ // Instantiations.
+ //----------------------------------------------------------------
+ aes_inv_sbox inv_sbox_inst(.sword(tmp_sboxw), .new_sword(new_sboxw));
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign round = round_ctr_reg;
+ assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with synchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ block_w0_reg <= 32'h0;
+ block_w1_reg <= 32'h0;
+ block_w2_reg <= 32'h0;
+ block_w3_reg <= 32'h0;
+ sword_ctr_reg <= 2'h0;
+ round_ctr_reg <= 4'h0;
+ ready_reg <= 1'b1;
+ dec_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (block_w0_we)
+ block_w0_reg <= block_new[127 : 096];
+
+ if (block_w1_we)
+ block_w1_reg <= block_new[095 : 064];
+
+ if (block_w2_we)
+ block_w2_reg <= block_new[063 : 032];
+
+ if (block_w3_we)
+ block_w3_reg <= block_new[031 : 000];
+
+ if (sword_ctr_we)
+ sword_ctr_reg <= sword_ctr_new;
+
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (dec_ctrl_we)
+ dec_ctrl_reg <= dec_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // round_logic
+ //
+ // The logic needed to implement init, main and final rounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_logic
+ reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
+ reg [127 : 0] addkey_block;
+
+ inv_shiftrows_block = 128'h0;
+ inv_mixcolumns_block = 128'h0;
+ addkey_block = 128'h0;
+ block_new = 128'h0;
+ tmp_sboxw = 32'h0;
+ block_w0_we = 1'b0;
+ block_w1_we = 1'b0;
+ block_w2_we = 1'b0;
+ block_w3_we = 1'b0;
+
+ old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+
+ // Update based on update type.
+ case (update_type)
+ // InitRound
+ INIT_UPDATE:
+ begin
+ old_block = block;
+ addkey_block = addroundkey(old_block, round_key);
+ inv_shiftrows_block = inv_shiftrows(addkey_block);
+ block_new = inv_shiftrows_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ SBOX_UPDATE:
+ begin
+ block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+ case (sword_ctr_reg)
+ 2'h0:
+ begin
+ tmp_sboxw = block_w0_reg;
+ block_w0_we = 1'b1;
+ end
+
+ 2'h1:
+ begin
+ tmp_sboxw = block_w1_reg;
+ block_w1_we = 1'b1;
+ end
+
+ 2'h2:
+ begin
+ tmp_sboxw = block_w2_reg;
+ block_w2_we = 1'b1;
+ end
+
+ 2'h3:
+ begin
+ tmp_sboxw = block_w3_reg;
+ block_w3_we = 1'b1;
+ end
+ endcase // case (sbox_mux_ctrl_reg)
+ end
+
+ MAIN_UPDATE:
+ begin
+ addkey_block = addroundkey(old_block, round_key);
+ inv_mixcolumns_block = inv_mixcolumns(addkey_block);
+ inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
+ block_new = inv_shiftrows_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ FINAL_UPDATE:
+ begin
+ block_new = addroundkey(old_block, round_key);
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (update_type)
+ end // round_logic
+
+
+ //----------------------------------------------------------------
+ // sword_ctr
+ //
+ // The subbytes word counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : sword_ctr
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b0;
+
+ if (sword_ctr_rst)
+ begin
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b1;
+ end
+ else if (sword_ctr_inc)
+ begin
+ sword_ctr_new = sword_ctr_reg + 1'b1;
+ sword_ctr_we = 1'b1;
+ end
+ end // sword_ctr
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_set)
+ begin
+ if (keylen == AES_256_BIT_KEY)
+ begin
+ round_ctr_new = AES256_ROUNDS;
+ end
+ else
+ begin
+ round_ctr_new = AES128_ROUNDS;
+ end
+ round_ctr_we = 1'b1;
+ end
+ else if (round_ctr_dec)
+ begin
+ round_ctr_new = round_ctr_reg - 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end // round_ctr
+
+
+ //----------------------------------------------------------------
+ // decipher_ctrl
+ //
+ // The FSM that controls the decipher operations.
+ //----------------------------------------------------------------
+ always @*
+ begin: decipher_ctrl
+ sword_ctr_inc = 1'b0;
+ sword_ctr_rst = 1'b0;
+ round_ctr_dec = 1'b0;
+ round_ctr_set = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ update_type = NO_UPDATE;
+ dec_ctrl_new = CTRL_IDLE;
+ dec_ctrl_we = 1'b0;
+
+ case(dec_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (next)
+ begin
+ round_ctr_set = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ dec_ctrl_new = CTRL_INIT;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ sword_ctr_rst = 1'b1;
+ update_type = INIT_UPDATE;
+ dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_we = 1'b1;
+ end
+
+ CTRL_SBOX:
+ begin
+ sword_ctr_inc = 1'b1;
+ update_type = SBOX_UPDATE;
+ if (sword_ctr_reg == 2'h3)
+ begin
+ round_ctr_dec = 1'b1;
+ dec_ctrl_new = CTRL_MAIN;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_MAIN:
+ begin
+ sword_ctr_rst = 1'b1;
+ if (round_ctr_reg > 0)
+ begin
+ update_type = MAIN_UPDATE;
+ dec_ctrl_new = CTRL_SBOX;
+ dec_ctrl_we = 1'b1;
+ end
+ else
+ begin
+ update_type = FINAL_UPDATE;
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ dec_ctrl_new = CTRL_IDLE;
+ dec_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ // Empty. Just here to make the synthesis tool happy.
+ end
+ endcase // case (dec_ctrl_reg)
+ end // decipher_ctrl
+
+endmodule // aes_decipher_block
+
+//======================================================================
+// EOF aes_decipher_block.v
+//======================================================================
+
+//======================================================================
+//
+// aes_inv_sbox.v
+// --------------
+// The inverse AES S-box. Basically a 256 Byte ROM.
+//
+//
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_inv_sbox(
+ input wire [31 : 0] sword,
+ output wire [31 : 0] new_sword
+ );
+
+
+ //----------------------------------------------------------------
+ // The inverse sbox array.
+ //----------------------------------------------------------------
+ wire [7 : 0] inv_sbox [0 : 255];
+
+
+ //----------------------------------------------------------------
+ // Four parallel muxes.
+ //----------------------------------------------------------------
+ assign new_sword[31 : 24] = inv_sbox[sword[31 : 24]];
+ assign new_sword[23 : 16] = inv_sbox[sword[23 : 16]];
+ assign new_sword[15 : 08] = inv_sbox[sword[15 : 08]];
+ assign new_sword[07 : 00] = inv_sbox[sword[07 : 00]];
+
+
+ //----------------------------------------------------------------
+ // Creating the contents of the array.
+ //----------------------------------------------------------------
+ assign inv_sbox[8'h00] = 8'h52;
+ assign inv_sbox[8'h01] = 8'h09;
+ assign inv_sbox[8'h02] = 8'h6a;
+ assign inv_sbox[8'h03] = 8'hd5;
+ assign inv_sbox[8'h04] = 8'h30;
+ assign inv_sbox[8'h05] = 8'h36;
+ assign inv_sbox[8'h06] = 8'ha5;
+ assign inv_sbox[8'h07] = 8'h38;
+ assign inv_sbox[8'h08] = 8'hbf;
+ assign inv_sbox[8'h09] = 8'h40;
+ assign inv_sbox[8'h0a] = 8'ha3;
+ assign inv_sbox[8'h0b] = 8'h9e;
+ assign inv_sbox[8'h0c] = 8'h81;
+ assign inv_sbox[8'h0d] = 8'hf3;
+ assign inv_sbox[8'h0e] = 8'hd7;
+ assign inv_sbox[8'h0f] = 8'hfb;
+ assign inv_sbox[8'h10] = 8'h7c;
+ assign inv_sbox[8'h11] = 8'he3;
+ assign inv_sbox[8'h12] = 8'h39;
+ assign inv_sbox[8'h13] = 8'h82;
+ assign inv_sbox[8'h14] = 8'h9b;
+ assign inv_sbox[8'h15] = 8'h2f;
+ assign inv_sbox[8'h16] = 8'hff;
+ assign inv_sbox[8'h17] = 8'h87;
+ assign inv_sbox[8'h18] = 8'h34;
+ assign inv_sbox[8'h19] = 8'h8e;
+ assign inv_sbox[8'h1a] = 8'h43;
+ assign inv_sbox[8'h1b] = 8'h44;
+ assign inv_sbox[8'h1c] = 8'hc4;
+ assign inv_sbox[8'h1d] = 8'hde;
+ assign inv_sbox[8'h1e] = 8'he9;
+ assign inv_sbox[8'h1f] = 8'hcb;
+ assign inv_sbox[8'h20] = 8'h54;
+ assign inv_sbox[8'h21] = 8'h7b;
+ assign inv_sbox[8'h22] = 8'h94;
+ assign inv_sbox[8'h23] = 8'h32;
+ assign inv_sbox[8'h24] = 8'ha6;
+ assign inv_sbox[8'h25] = 8'hc2;
+ assign inv_sbox[8'h26] = 8'h23;
+ assign inv_sbox[8'h27] = 8'h3d;
+ assign inv_sbox[8'h28] = 8'hee;
+ assign inv_sbox[8'h29] = 8'h4c;
+ assign inv_sbox[8'h2a] = 8'h95;
+ assign inv_sbox[8'h2b] = 8'h0b;
+ assign inv_sbox[8'h2c] = 8'h42;
+ assign inv_sbox[8'h2d] = 8'hfa;
+ assign inv_sbox[8'h2e] = 8'hc3;
+ assign inv_sbox[8'h2f] = 8'h4e;
+ assign inv_sbox[8'h30] = 8'h08;
+ assign inv_sbox[8'h31] = 8'h2e;
+ assign inv_sbox[8'h32] = 8'ha1;
+ assign inv_sbox[8'h33] = 8'h66;
+ assign inv_sbox[8'h34] = 8'h28;
+ assign inv_sbox[8'h35] = 8'hd9;
+ assign inv_sbox[8'h36] = 8'h24;
+ assign inv_sbox[8'h37] = 8'hb2;
+ assign inv_sbox[8'h38] = 8'h76;
+ assign inv_sbox[8'h39] = 8'h5b;
+ assign inv_sbox[8'h3a] = 8'ha2;
+ assign inv_sbox[8'h3b] = 8'h49;
+ assign inv_sbox[8'h3c] = 8'h6d;
+ assign inv_sbox[8'h3d] = 8'h8b;
+ assign inv_sbox[8'h3e] = 8'hd1;
+ assign inv_sbox[8'h3f] = 8'h25;
+ assign inv_sbox[8'h40] = 8'h72;
+ assign inv_sbox[8'h41] = 8'hf8;
+ assign inv_sbox[8'h42] = 8'hf6;
+ assign inv_sbox[8'h43] = 8'h64;
+ assign inv_sbox[8'h44] = 8'h86;
+ assign inv_sbox[8'h45] = 8'h68;
+ assign inv_sbox[8'h46] = 8'h98;
+ assign inv_sbox[8'h47] = 8'h16;
+ assign inv_sbox[8'h48] = 8'hd4;
+ assign inv_sbox[8'h49] = 8'ha4;
+ assign inv_sbox[8'h4a] = 8'h5c;
+ assign inv_sbox[8'h4b] = 8'hcc;
+ assign inv_sbox[8'h4c] = 8'h5d;
+ assign inv_sbox[8'h4d] = 8'h65;
+ assign inv_sbox[8'h4e] = 8'hb6;
+ assign inv_sbox[8'h4f] = 8'h92;
+ assign inv_sbox[8'h50] = 8'h6c;
+ assign inv_sbox[8'h51] = 8'h70;
+ assign inv_sbox[8'h52] = 8'h48;
+ assign inv_sbox[8'h53] = 8'h50;
+ assign inv_sbox[8'h54] = 8'hfd;
+ assign inv_sbox[8'h55] = 8'hed;
+ assign inv_sbox[8'h56] = 8'hb9;
+ assign inv_sbox[8'h57] = 8'hda;
+ assign inv_sbox[8'h58] = 8'h5e;
+ assign inv_sbox[8'h59] = 8'h15;
+ assign inv_sbox[8'h5a] = 8'h46;
+ assign inv_sbox[8'h5b] = 8'h57;
+ assign inv_sbox[8'h5c] = 8'ha7;
+ assign inv_sbox[8'h5d] = 8'h8d;
+ assign inv_sbox[8'h5e] = 8'h9d;
+ assign inv_sbox[8'h5f] = 8'h84;
+ assign inv_sbox[8'h60] = 8'h90;
+ assign inv_sbox[8'h61] = 8'hd8;
+ assign inv_sbox[8'h62] = 8'hab;
+ assign inv_sbox[8'h63] = 8'h00;
+ assign inv_sbox[8'h64] = 8'h8c;
+ assign inv_sbox[8'h65] = 8'hbc;
+ assign inv_sbox[8'h66] = 8'hd3;
+ assign inv_sbox[8'h67] = 8'h0a;
+ assign inv_sbox[8'h68] = 8'hf7;
+ assign inv_sbox[8'h69] = 8'he4;
+ assign inv_sbox[8'h6a] = 8'h58;
+ assign inv_sbox[8'h6b] = 8'h05;
+ assign inv_sbox[8'h6c] = 8'hb8;
+ assign inv_sbox[8'h6d] = 8'hb3;
+ assign inv_sbox[8'h6e] = 8'h45;
+ assign inv_sbox[8'h6f] = 8'h06;
+ assign inv_sbox[8'h70] = 8'hd0;
+ assign inv_sbox[8'h71] = 8'h2c;
+ assign inv_sbox[8'h72] = 8'h1e;
+ assign inv_sbox[8'h73] = 8'h8f;
+ assign inv_sbox[8'h74] = 8'hca;
+ assign inv_sbox[8'h75] = 8'h3f;
+ assign inv_sbox[8'h76] = 8'h0f;
+ assign inv_sbox[8'h77] = 8'h02;
+ assign inv_sbox[8'h78] = 8'hc1;
+ assign inv_sbox[8'h79] = 8'haf;
+ assign inv_sbox[8'h7a] = 8'hbd;
+ assign inv_sbox[8'h7b] = 8'h03;
+ assign inv_sbox[8'h7c] = 8'h01;
+ assign inv_sbox[8'h7d] = 8'h13;
+ assign inv_sbox[8'h7e] = 8'h8a;
+ assign inv_sbox[8'h7f] = 8'h6b;
+ assign inv_sbox[8'h80] = 8'h3a;
+ assign inv_sbox[8'h81] = 8'h91;
+ assign inv_sbox[8'h82] = 8'h11;
+ assign inv_sbox[8'h83] = 8'h41;
+ assign inv_sbox[8'h84] = 8'h4f;
+ assign inv_sbox[8'h85] = 8'h67;
+ assign inv_sbox[8'h86] = 8'hdc;
+ assign inv_sbox[8'h87] = 8'hea;
+ assign inv_sbox[8'h88] = 8'h97;
+ assign inv_sbox[8'h89] = 8'hf2;
+ assign inv_sbox[8'h8a] = 8'hcf;
+ assign inv_sbox[8'h8b] = 8'hce;
+ assign inv_sbox[8'h8c] = 8'hf0;
+ assign inv_sbox[8'h8d] = 8'hb4;
+ assign inv_sbox[8'h8e] = 8'he6;
+ assign inv_sbox[8'h8f] = 8'h73;
+ assign inv_sbox[8'h90] = 8'h96;
+ assign inv_sbox[8'h91] = 8'hac;
+ assign inv_sbox[8'h92] = 8'h74;
+ assign inv_sbox[8'h93] = 8'h22;
+ assign inv_sbox[8'h94] = 8'he7;
+ assign inv_sbox[8'h95] = 8'had;
+ assign inv_sbox[8'h96] = 8'h35;
+ assign inv_sbox[8'h97] = 8'h85;
+ assign inv_sbox[8'h98] = 8'he2;
+ assign inv_sbox[8'h99] = 8'hf9;
+ assign inv_sbox[8'h9a] = 8'h37;
+ assign inv_sbox[8'h9b] = 8'he8;
+ assign inv_sbox[8'h9c] = 8'h1c;
+ assign inv_sbox[8'h9d] = 8'h75;
+ assign inv_sbox[8'h9e] = 8'hdf;
+ assign inv_sbox[8'h9f] = 8'h6e;
+ assign inv_sbox[8'ha0] = 8'h47;
+ assign inv_sbox[8'ha1] = 8'hf1;
+ assign inv_sbox[8'ha2] = 8'h1a;
+ assign inv_sbox[8'ha3] = 8'h71;
+ assign inv_sbox[8'ha4] = 8'h1d;
+ assign inv_sbox[8'ha5] = 8'h29;
+ assign inv_sbox[8'ha6] = 8'hc5;
+ assign inv_sbox[8'ha7] = 8'h89;
+ assign inv_sbox[8'ha8] = 8'h6f;
+ assign inv_sbox[8'ha9] = 8'hb7;
+ assign inv_sbox[8'haa] = 8'h62;
+ assign inv_sbox[8'hab] = 8'h0e;
+ assign inv_sbox[8'hac] = 8'haa;
+ assign inv_sbox[8'had] = 8'h18;
+ assign inv_sbox[8'hae] = 8'hbe;
+ assign inv_sbox[8'haf] = 8'h1b;
+ assign inv_sbox[8'hb0] = 8'hfc;
+ assign inv_sbox[8'hb1] = 8'h56;
+ assign inv_sbox[8'hb2] = 8'h3e;
+ assign inv_sbox[8'hb3] = 8'h4b;
+ assign inv_sbox[8'hb4] = 8'hc6;
+ assign inv_sbox[8'hb5] = 8'hd2;
+ assign inv_sbox[8'hb6] = 8'h79;
+ assign inv_sbox[8'hb7] = 8'h20;
+ assign inv_sbox[8'hb8] = 8'h9a;
+ assign inv_sbox[8'hb9] = 8'hdb;
+ assign inv_sbox[8'hba] = 8'hc0;
+ assign inv_sbox[8'hbb] = 8'hfe;
+ assign inv_sbox[8'hbc] = 8'h78;
+ assign inv_sbox[8'hbd] = 8'hcd;
+ assign inv_sbox[8'hbe] = 8'h5a;
+ assign inv_sbox[8'hbf] = 8'hf4;
+ assign inv_sbox[8'hc0] = 8'h1f;
+ assign inv_sbox[8'hc1] = 8'hdd;
+ assign inv_sbox[8'hc2] = 8'ha8;
+ assign inv_sbox[8'hc3] = 8'h33;
+ assign inv_sbox[8'hc4] = 8'h88;
+ assign inv_sbox[8'hc5] = 8'h07;
+ assign inv_sbox[8'hc6] = 8'hc7;
+ assign inv_sbox[8'hc7] = 8'h31;
+ assign inv_sbox[8'hc8] = 8'hb1;
+ assign inv_sbox[8'hc9] = 8'h12;
+ assign inv_sbox[8'hca] = 8'h10;
+ assign inv_sbox[8'hcb] = 8'h59;
+ assign inv_sbox[8'hcc] = 8'h27;
+ assign inv_sbox[8'hcd] = 8'h80;
+ assign inv_sbox[8'hce] = 8'hec;
+ assign inv_sbox[8'hcf] = 8'h5f;
+ assign inv_sbox[8'hd0] = 8'h60;
+ assign inv_sbox[8'hd1] = 8'h51;
+ assign inv_sbox[8'hd2] = 8'h7f;
+ assign inv_sbox[8'hd3] = 8'ha9;
+ assign inv_sbox[8'hd4] = 8'h19;
+ assign inv_sbox[8'hd5] = 8'hb5;
+ assign inv_sbox[8'hd6] = 8'h4a;
+ assign inv_sbox[8'hd7] = 8'h0d;
+ assign inv_sbox[8'hd8] = 8'h2d;
+ assign inv_sbox[8'hd9] = 8'he5;
+ assign inv_sbox[8'hda] = 8'h7a;
+ assign inv_sbox[8'hdb] = 8'h9f;
+ assign inv_sbox[8'hdc] = 8'h93;
+ assign inv_sbox[8'hdd] = 8'hc9;
+ assign inv_sbox[8'hde] = 8'h9c;
+ assign inv_sbox[8'hdf] = 8'hef;
+ assign inv_sbox[8'he0] = 8'ha0;
+ assign inv_sbox[8'he1] = 8'he0;
+ assign inv_sbox[8'he2] = 8'h3b;
+ assign inv_sbox[8'he3] = 8'h4d;
+ assign inv_sbox[8'he4] = 8'hae;
+ assign inv_sbox[8'he5] = 8'h2a;
+ assign inv_sbox[8'he6] = 8'hf5;
+ assign inv_sbox[8'he7] = 8'hb0;
+ assign inv_sbox[8'he8] = 8'hc8;
+ assign inv_sbox[8'he9] = 8'heb;
+ assign inv_sbox[8'hea] = 8'hbb;
+ assign inv_sbox[8'heb] = 8'h3c;
+ assign inv_sbox[8'hec] = 8'h83;
+ assign inv_sbox[8'hed] = 8'h53;
+ assign inv_sbox[8'hee] = 8'h99;
+ assign inv_sbox[8'hef] = 8'h61;
+ assign inv_sbox[8'hf0] = 8'h17;
+ assign inv_sbox[8'hf1] = 8'h2b;
+ assign inv_sbox[8'hf2] = 8'h04;
+ assign inv_sbox[8'hf3] = 8'h7e;
+ assign inv_sbox[8'hf4] = 8'hba;
+ assign inv_sbox[8'hf5] = 8'h77;
+ assign inv_sbox[8'hf6] = 8'hd6;
+ assign inv_sbox[8'hf7] = 8'h26;
+ assign inv_sbox[8'hf8] = 8'he1;
+ assign inv_sbox[8'hf9] = 8'h69;
+ assign inv_sbox[8'hfa] = 8'h14;
+ assign inv_sbox[8'hfb] = 8'h63;
+ assign inv_sbox[8'hfc] = 8'h55;
+ assign inv_sbox[8'hfd] = 8'h21;
+ assign inv_sbox[8'hfe] = 8'h0c;
+ assign inv_sbox[8'hff] = 8'h7d;
+
+endmodule // aes_inv_sbox
+
+//======================================================================
+// EOF aes_inv_sbox.v
+//======================================================================
+
+
+//======================================================================
+//
+// aes_key_mem.v
+// -------------
+// The AES key memory including round key generator.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_key_mem(
+ input wire clk,
+ input wire reset_n,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+ input wire init,
+
+ input wire [3 : 0] round,
+ output wire [127 : 0] round_key,
+ output wire ready,
+
+
+ output wire [31 : 0] sboxw,
+ input wire [31 : 0] new_sboxw
+ );
+
+
+ //----------------------------------------------------------------
+ // Parameters.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES_128_NUM_ROUNDS = 10;
+ localparam AES_256_NUM_ROUNDS = 14;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_GENERATE = 3'h2;
+ localparam CTRL_DONE = 3'h3;
+
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [127 : 0] key_mem [0 : 14];
+ reg [127 : 0] key_mem_new;
+ reg key_mem_we;
+
+ reg [127 : 0] prev_key0_reg;
+ reg [127 : 0] prev_key0_new;
+ reg prev_key0_we;
+
+ reg [127 : 0] prev_key1_reg;
+ reg [127 : 0] prev_key1_new;
+ reg prev_key1_we;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_rst;
+ reg round_ctr_inc;
+ reg round_ctr_we;
+
+ reg [2 : 0] key_mem_ctrl_reg;
+ reg [2 : 0] key_mem_ctrl_new;
+ reg key_mem_ctrl_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [7 : 0] rcon_reg;
+ reg [7 : 0] rcon_new;
+ reg rcon_we;
+ reg rcon_set;
+ reg rcon_next;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_sboxw;
+ reg round_key_update;
+ reg [127 : 0] tmp_round_key;
+
+
+ //----------------------------------------------------------------
+ // Concurrent assignments for ports.
+ //----------------------------------------------------------------
+ assign round_key = tmp_round_key;
+ assign ready = ready_reg;
+ assign sboxw = tmp_sboxw;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i <= AES_256_NUM_ROUNDS ; i = i + 1)
+ key_mem [i] <= 128'h0;
+
+ rcon_reg <= 8'h0;
+ ready_reg <= 1'b0;
+ round_ctr_reg <= 4'h0;
+ key_mem_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (rcon_we)
+ rcon_reg <= rcon_new;
+
+ if (key_mem_we)
+ key_mem[round_ctr_reg] <= key_mem_new;
+
+ if (prev_key0_we)
+ prev_key0_reg <= prev_key0_new;
+
+ if (prev_key1_we)
+ prev_key1_reg <= prev_key1_new;
+
+ if (key_mem_ctrl_we)
+ key_mem_ctrl_reg <= key_mem_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // key_mem_read
+ //
+ // Combinational read port for the key memory.
+ //----------------------------------------------------------------
+ always @*
+ begin : key_mem_read
+ tmp_round_key = key_mem[round];
+ end // key_mem_read
+
+
+ //----------------------------------------------------------------
+ // round_key_gen
+ //
+ // The round key generator logic for AES-128 and AES-256.
+ //----------------------------------------------------------------
+ always @*
+ begin: round_key_gen
+ reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
+ reg [31 : 0] k0, k1, k2, k3;
+ reg [31 : 0] rconw, rotstw, tw, trw;
+
+ // Default assignments.
+ key_mem_new = 128'h0;
+ key_mem_we = 1'b0;
+ prev_key0_new = 128'h0;
+ prev_key0_we = 1'b0;
+ prev_key1_new = 128'h0;
+ prev_key1_we = 1'b0;
+
+ k0 = 32'h0;
+ k1 = 32'h0;
+ k2 = 32'h0;
+ k3 = 32'h0;
+
+ rcon_set = 1'b1;
+ rcon_next = 1'b0;
+
+ // Extract words and calculate intermediate values.
+ // Perform rotation of sbox word etc.
+ w0 = prev_key0_reg[127 : 096];
+ w1 = prev_key0_reg[095 : 064];
+ w2 = prev_key0_reg[063 : 032];
+ w3 = prev_key0_reg[031 : 000];
+
+ w4 = prev_key1_reg[127 : 096];
+ w5 = prev_key1_reg[095 : 064];
+ w6 = prev_key1_reg[063 : 032];
+ w7 = prev_key1_reg[031 : 000];
+
+ rconw = {rcon_reg, 24'h0};
+ tmp_sboxw = w7;
+ rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
+ trw = rotstw ^ rconw;
+ tw = new_sboxw;
+
+ // Generate the specific round keys.
+ if (round_key_update)
+ begin
+ rcon_set = 1'b0;
+ key_mem_we = 1'b1;
+ case (keylen)
+ AES_128_BIT_KEY:
+ begin
+ if (round_ctr_reg == 0)
+ begin
+ key_mem_new = key[255 : 128];
+ prev_key1_new = key[255 : 128];
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ else
+ begin
+ k0 = w4 ^ trw;
+ k1 = w5 ^ w4 ^ trw;
+ k2 = w6 ^ w5 ^ w4 ^ trw;
+ k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
+
+ key_mem_new = {k0, k1, k2, k3};
+ prev_key1_new = {k0, k1, k2, k3};
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ end
+
+ AES_256_BIT_KEY:
+ begin
+ if (round_ctr_reg == 0)
+ begin
+ key_mem_new = key[255 : 128];
+ prev_key0_new = key[255 : 128];
+ prev_key0_we = 1'b1;
+ end
+ else if (round_ctr_reg == 1)
+ begin
+ key_mem_new = key[127 : 0];
+ prev_key1_new = key[127 : 0];
+ prev_key1_we = 1'b1;
+ rcon_next = 1'b1;
+ end
+ else
+ begin
+ if (round_ctr_reg[0] == 0)
+ begin
+ k0 = w0 ^ trw;
+ k1 = w1 ^ w0 ^ trw;
+ k2 = w2 ^ w1 ^ w0 ^ trw;
+ k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
+ end
+ else
+ begin
+ k0 = w0 ^ tw;
+ k1 = w1 ^ w0 ^ tw;
+ k2 = w2 ^ w1 ^ w0 ^ tw;
+ k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
+ rcon_next = 1'b1;
+ end
+
+ // Store the generated round keys.
+ key_mem_new = {k0, k1, k2, k3};
+ prev_key1_new = {k0, k1, k2, k3};
+ prev_key1_we = 1'b1;
+ prev_key0_new = prev_key1_reg;
+ prev_key0_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ end
+ endcase // case (keylen)
+ end
+ end // round_key_gen
+
+
+ //----------------------------------------------------------------
+ // rcon_logic
+ //
+ // Caclulates the rcon value for the different key expansion
+ // iterations.
+ //----------------------------------------------------------------
+ always @*
+ begin : rcon_logic
+ reg [7 : 0] tmp_rcon;
+ rcon_new = 8'h00;
+ rcon_we = 1'b0;
+
+ tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
+
+ if (rcon_set)
+ begin
+ rcon_new = 8'h8d;
+ rcon_we = 1'b1;
+ end
+
+ if (rcon_next)
+ begin
+ rcon_new = tmp_rcon[7 : 0];
+ rcon_we = 1'b1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter logic with increase and reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_rst)
+ begin
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b1;
+ end
+
+ else if (round_ctr_inc)
+ begin
+ round_ctr_new = round_ctr_reg + 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // key_mem_ctrl
+ //
+ //
+ // The FSM that controls the round key generation.
+ //----------------------------------------------------------------
+ always @*
+ begin: key_mem_ctrl
+ reg [3 : 0] num_rounds;
+
+ // Default assignments.
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ round_key_update = 1'b0;
+ round_ctr_rst = 1'b0;
+ round_ctr_inc = 1'b0;
+ key_mem_ctrl_new = CTRL_IDLE;
+ key_mem_ctrl_we = 1'b0;
+
+ if (keylen == AES_128_BIT_KEY)
+ num_rounds = AES_128_NUM_ROUNDS;
+ else
+ num_rounds = AES_256_NUM_ROUNDS;
+
+ case(key_mem_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ key_mem_ctrl_new = CTRL_INIT;
+ key_mem_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ round_ctr_rst = 1'b1;
+ key_mem_ctrl_new = CTRL_GENERATE;
+ key_mem_ctrl_we = 1'b1;
+ end
+
+ CTRL_GENERATE:
+ begin
+ round_ctr_inc = 1'b1;
+ round_key_update = 1'b1;
+ if (round_ctr_reg == num_rounds)
+ begin
+ key_mem_ctrl_new = CTRL_DONE;
+ key_mem_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_DONE:
+ begin
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ key_mem_ctrl_new = CTRL_IDLE;
+ key_mem_ctrl_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (key_mem_ctrl_reg)
+
+ end // key_mem_ctrl
+endmodule // aes_key_mem
+
+//======================================================================
+// EOF aes_key_mem.v
+//======================================================================
+
+//======================================================================
+//
+// aes_sbox.v
+// ----------
+// The AES S-box. Basically a 256 Byte ROM. This implementation
+// contains four parallel S-boxes to handle a 32 bit word.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_sbox(
+ input wire [31 : 0] sboxw,
+ output wire [31 : 0] new_sboxw
+ );
+
+
+ //----------------------------------------------------------------
+ // The sbox array.
+ //----------------------------------------------------------------
+ wire [7 : 0] sbox [0 : 255];
+
+
+ //----------------------------------------------------------------
+ // Four parallel muxes.
+ //----------------------------------------------------------------
+ assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]];
+ assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]];
+ assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]];
+ assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]];
+
+
+ //----------------------------------------------------------------
+ // Creating the sbox array contents.
+ //----------------------------------------------------------------
+ assign sbox[8'h00] = 8'h63;
+ assign sbox[8'h01] = 8'h7c;
+ assign sbox[8'h02] = 8'h77;
+ assign sbox[8'h03] = 8'h7b;
+ assign sbox[8'h04] = 8'hf2;
+ assign sbox[8'h05] = 8'h6b;
+ assign sbox[8'h06] = 8'h6f;
+ assign sbox[8'h07] = 8'hc5;
+ assign sbox[8'h08] = 8'h30;
+ assign sbox[8'h09] = 8'h01;
+ assign sbox[8'h0a] = 8'h67;
+ assign sbox[8'h0b] = 8'h2b;
+ assign sbox[8'h0c] = 8'hfe;
+ assign sbox[8'h0d] = 8'hd7;
+ assign sbox[8'h0e] = 8'hab;
+ assign sbox[8'h0f] = 8'h76;
+ assign sbox[8'h10] = 8'hca;
+ assign sbox[8'h11] = 8'h82;
+ assign sbox[8'h12] = 8'hc9;
+ assign sbox[8'h13] = 8'h7d;
+ assign sbox[8'h14] = 8'hfa;
+ assign sbox[8'h15] = 8'h59;
+ assign sbox[8'h16] = 8'h47;
+ assign sbox[8'h17] = 8'hf0;
+ assign sbox[8'h18] = 8'had;
+ assign sbox[8'h19] = 8'hd4;
+ assign sbox[8'h1a] = 8'ha2;
+ assign sbox[8'h1b] = 8'haf;
+ assign sbox[8'h1c] = 8'h9c;
+ assign sbox[8'h1d] = 8'ha4;
+ assign sbox[8'h1e] = 8'h72;
+ assign sbox[8'h1f] = 8'hc0;
+ assign sbox[8'h20] = 8'hb7;
+ assign sbox[8'h21] = 8'hfd;
+ assign sbox[8'h22] = 8'h93;
+ assign sbox[8'h23] = 8'h26;
+ assign sbox[8'h24] = 8'h36;
+ assign sbox[8'h25] = 8'h3f;
+ assign sbox[8'h26] = 8'hf7;
+ assign sbox[8'h27] = 8'hcc;
+ assign sbox[8'h28] = 8'h34;
+ assign sbox[8'h29] = 8'ha5;
+ assign sbox[8'h2a] = 8'he5;
+ assign sbox[8'h2b] = 8'hf1;
+ assign sbox[8'h2c] = 8'h71;
+ assign sbox[8'h2d] = 8'hd8;
+ assign sbox[8'h2e] = 8'h31;
+ assign sbox[8'h2f] = 8'h15;
+ assign sbox[8'h30] = 8'h04;
+ assign sbox[8'h31] = 8'hc7;
+ assign sbox[8'h32] = 8'h23;
+ assign sbox[8'h33] = 8'hc3;
+ assign sbox[8'h34] = 8'h18;
+ assign sbox[8'h35] = 8'h96;
+ assign sbox[8'h36] = 8'h05;
+ assign sbox[8'h37] = 8'h9a;
+ assign sbox[8'h38] = 8'h07;
+ assign sbox[8'h39] = 8'h12;
+ assign sbox[8'h3a] = 8'h80;
+ assign sbox[8'h3b] = 8'he2;
+ assign sbox[8'h3c] = 8'heb;
+ assign sbox[8'h3d] = 8'h27;
+ assign sbox[8'h3e] = 8'hb2;
+ assign sbox[8'h3f] = 8'h75;
+ assign sbox[8'h40] = 8'h09;
+ assign sbox[8'h41] = 8'h83;
+ assign sbox[8'h42] = 8'h2c;
+ assign sbox[8'h43] = 8'h1a;
+ assign sbox[8'h44] = 8'h1b;
+ assign sbox[8'h45] = 8'h6e;
+ assign sbox[8'h46] = 8'h5a;
+ assign sbox[8'h47] = 8'ha0;
+ assign sbox[8'h48] = 8'h52;
+ assign sbox[8'h49] = 8'h3b;
+ assign sbox[8'h4a] = 8'hd6;
+ assign sbox[8'h4b] = 8'hb3;
+ assign sbox[8'h4c] = 8'h29;
+ assign sbox[8'h4d] = 8'he3;
+ assign sbox[8'h4e] = 8'h2f;
+ assign sbox[8'h4f] = 8'h84;
+ assign sbox[8'h50] = 8'h53;
+ assign sbox[8'h51] = 8'hd1;
+ assign sbox[8'h52] = 8'h00;
+ assign sbox[8'h53] = 8'hed;
+ assign sbox[8'h54] = 8'h20;
+ assign sbox[8'h55] = 8'hfc;
+ assign sbox[8'h56] = 8'hb1;
+ assign sbox[8'h57] = 8'h5b;
+ assign sbox[8'h58] = 8'h6a;
+ assign sbox[8'h59] = 8'hcb;
+ assign sbox[8'h5a] = 8'hbe;
+ assign sbox[8'h5b] = 8'h39;
+ assign sbox[8'h5c] = 8'h4a;
+ assign sbox[8'h5d] = 8'h4c;
+ assign sbox[8'h5e] = 8'h58;
+ assign sbox[8'h5f] = 8'hcf;
+ assign sbox[8'h60] = 8'hd0;
+ assign sbox[8'h61] = 8'hef;
+ assign sbox[8'h62] = 8'haa;
+ assign sbox[8'h63] = 8'hfb;
+ assign sbox[8'h64] = 8'h43;
+ assign sbox[8'h65] = 8'h4d;
+ assign sbox[8'h66] = 8'h33;
+ assign sbox[8'h67] = 8'h85;
+ assign sbox[8'h68] = 8'h45;
+ assign sbox[8'h69] = 8'hf9;
+ assign sbox[8'h6a] = 8'h02;
+ assign sbox[8'h6b] = 8'h7f;
+ assign sbox[8'h6c] = 8'h50;
+ assign sbox[8'h6d] = 8'h3c;
+ assign sbox[8'h6e] = 8'h9f;
+ assign sbox[8'h6f] = 8'ha8;
+ assign sbox[8'h70] = 8'h51;
+ assign sbox[8'h71] = 8'ha3;
+ assign sbox[8'h72] = 8'h40;
+ assign sbox[8'h73] = 8'h8f;
+ assign sbox[8'h74] = 8'h92;
+ assign sbox[8'h75] = 8'h9d;
+ assign sbox[8'h76] = 8'h38;
+ assign sbox[8'h77] = 8'hf5;
+ assign sbox[8'h78] = 8'hbc;
+ assign sbox[8'h79] = 8'hb6;
+ assign sbox[8'h7a] = 8'hda;
+ assign sbox[8'h7b] = 8'h21;
+ assign sbox[8'h7c] = 8'h10;
+ assign sbox[8'h7d] = 8'hff;
+ assign sbox[8'h7e] = 8'hf3;
+ assign sbox[8'h7f] = 8'hd2;
+ assign sbox[8'h80] = 8'hcd;
+ assign sbox[8'h81] = 8'h0c;
+ assign sbox[8'h82] = 8'h13;
+ assign sbox[8'h83] = 8'hec;
+ assign sbox[8'h84] = 8'h5f;
+ assign sbox[8'h85] = 8'h97;
+ assign sbox[8'h86] = 8'h44;
+ assign sbox[8'h87] = 8'h17;
+ assign sbox[8'h88] = 8'hc4;
+ assign sbox[8'h89] = 8'ha7;
+ assign sbox[8'h8a] = 8'h7e;
+ assign sbox[8'h8b] = 8'h3d;
+ assign sbox[8'h8c] = 8'h64;
+ assign sbox[8'h8d] = 8'h5d;
+ assign sbox[8'h8e] = 8'h19;
+ assign sbox[8'h8f] = 8'h73;
+ assign sbox[8'h90] = 8'h60;
+ assign sbox[8'h91] = 8'h81;
+ assign sbox[8'h92] = 8'h4f;
+ assign sbox[8'h93] = 8'hdc;
+ assign sbox[8'h94] = 8'h22;
+ assign sbox[8'h95] = 8'h2a;
+ assign sbox[8'h96] = 8'h90;
+ assign sbox[8'h97] = 8'h88;
+ assign sbox[8'h98] = 8'h46;
+ assign sbox[8'h99] = 8'hee;
+ assign sbox[8'h9a] = 8'hb8;
+ assign sbox[8'h9b] = 8'h14;
+ assign sbox[8'h9c] = 8'hde;
+ assign sbox[8'h9d] = 8'h5e;
+ assign sbox[8'h9e] = 8'h0b;
+ assign sbox[8'h9f] = 8'hdb;
+ assign sbox[8'ha0] = 8'he0;
+ assign sbox[8'ha1] = 8'h32;
+ assign sbox[8'ha2] = 8'h3a;
+ assign sbox[8'ha3] = 8'h0a;
+ assign sbox[8'ha4] = 8'h49;
+ assign sbox[8'ha5] = 8'h06;
+ assign sbox[8'ha6] = 8'h24;
+ assign sbox[8'ha7] = 8'h5c;
+ assign sbox[8'ha8] = 8'hc2;
+ assign sbox[8'ha9] = 8'hd3;
+ assign sbox[8'haa] = 8'hac;
+ assign sbox[8'hab] = 8'h62;
+ assign sbox[8'hac] = 8'h91;
+ assign sbox[8'had] = 8'h95;
+ assign sbox[8'hae] = 8'he4;
+ assign sbox[8'haf] = 8'h79;
+ assign sbox[8'hb0] = 8'he7;
+ assign sbox[8'hb1] = 8'hc8;
+ assign sbox[8'hb2] = 8'h37;
+ assign sbox[8'hb3] = 8'h6d;
+ assign sbox[8'hb4] = 8'h8d;
+ assign sbox[8'hb5] = 8'hd5;
+ assign sbox[8'hb6] = 8'h4e;
+ assign sbox[8'hb7] = 8'ha9;
+ assign sbox[8'hb8] = 8'h6c;
+ assign sbox[8'hb9] = 8'h56;
+ assign sbox[8'hba] = 8'hf4;
+ assign sbox[8'hbb] = 8'hea;
+ assign sbox[8'hbc] = 8'h65;
+ assign sbox[8'hbd] = 8'h7a;
+ assign sbox[8'hbe] = 8'hae;
+ assign sbox[8'hbf] = 8'h08;
+ assign sbox[8'hc0] = 8'hba;
+ assign sbox[8'hc1] = 8'h78;
+ assign sbox[8'hc2] = 8'h25;
+ assign sbox[8'hc3] = 8'h2e;
+ assign sbox[8'hc4] = 8'h1c;
+ assign sbox[8'hc5] = 8'ha6;
+ assign sbox[8'hc6] = 8'hb4;
+ assign sbox[8'hc7] = 8'hc6;
+ assign sbox[8'hc8] = 8'he8;
+ assign sbox[8'hc9] = 8'hdd;
+ assign sbox[8'hca] = 8'h74;
+ assign sbox[8'hcb] = 8'h1f;
+ assign sbox[8'hcc] = 8'h4b;
+ assign sbox[8'hcd] = 8'hbd;
+ assign sbox[8'hce] = 8'h8b;
+ assign sbox[8'hcf] = 8'h8a;
+ assign sbox[8'hd0] = 8'h70;
+ assign sbox[8'hd1] = 8'h3e;
+ assign sbox[8'hd2] = 8'hb5;
+ assign sbox[8'hd3] = 8'h66;
+ assign sbox[8'hd4] = 8'h48;
+ assign sbox[8'hd5] = 8'h03;
+ assign sbox[8'hd6] = 8'hf6;
+ assign sbox[8'hd7] = 8'h0e;
+ assign sbox[8'hd8] = 8'h61;
+ assign sbox[8'hd9] = 8'h35;
+ assign sbox[8'hda] = 8'h57;
+ assign sbox[8'hdb] = 8'hb9;
+ assign sbox[8'hdc] = 8'h86;
+ assign sbox[8'hdd] = 8'hc1;
+ assign sbox[8'hde] = 8'h1d;
+ assign sbox[8'hdf] = 8'h9e;
+ assign sbox[8'he0] = 8'he1;
+ assign sbox[8'he1] = 8'hf8;
+ assign sbox[8'he2] = 8'h98;
+ assign sbox[8'he3] = 8'h11;
+ assign sbox[8'he4] = 8'h69;
+ assign sbox[8'he5] = 8'hd9;
+ assign sbox[8'he6] = 8'h8e;
+ assign sbox[8'he7] = 8'h94;
+ assign sbox[8'he8] = 8'h9b;
+ assign sbox[8'he9] = 8'h1e;
+ assign sbox[8'hea] = 8'h87;
+ assign sbox[8'heb] = 8'he9;
+ assign sbox[8'hec] = 8'hce;
+ assign sbox[8'hed] = 8'h55;
+ assign sbox[8'hee] = 8'h28;
+ assign sbox[8'hef] = 8'hdf;
+ assign sbox[8'hf0] = 8'h8c;
+ assign sbox[8'hf1] = 8'ha1;
+ assign sbox[8'hf2] = 8'h89;
+ assign sbox[8'hf3] = 8'h0d;
+ assign sbox[8'hf4] = 8'hbf;
+ assign sbox[8'hf5] = 8'he6;
+ assign sbox[8'hf6] = 8'h42;
+ assign sbox[8'hf7] = 8'h68;
+ assign sbox[8'hf8] = 8'h41;
+ assign sbox[8'hf9] = 8'h99;
+ assign sbox[8'hfa] = 8'h2d;
+ assign sbox[8'hfb] = 8'h0f;
+ assign sbox[8'hfc] = 8'hb0;
+ assign sbox[8'hfd] = 8'h54;
+ assign sbox[8'hfe] = 8'hbb;
+ assign sbox[8'hff] = 8'h16;
+
+endmodule // aes_sbox
+
+//======================================================================
+// EOF aes_sbox.v
+//======================================================================
+
+//======================================================================
+//
+// aes_encipher_block.v
+// --------------------
+// The AES encipher round. A pure combinational module that implements
+// the initial round, main round and final round logic for
+// enciper operations.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2013, 2014, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module aes_encipher_block(
+ input wire clk,
+ input wire reset_n,
+
+ input wire next,
+
+ input wire keylen,
+ output wire [3 : 0] round,
+ input wire [127 : 0] round_key,
+
+ output wire [31 : 0] sboxw,
+ input wire [31 : 0] new_sboxw,
+
+ input wire [127 : 0] block,
+ output wire [127 : 0] new_block,
+ output wire ready
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ localparam AES_128_BIT_KEY = 1'h0;
+ localparam AES_256_BIT_KEY = 1'h1;
+
+ localparam AES128_ROUNDS = 4'ha;
+ localparam AES256_ROUNDS = 4'he;
+
+ localparam NO_UPDATE = 3'h0;
+ localparam INIT_UPDATE = 3'h1;
+ localparam SBOX_UPDATE = 3'h2;
+ localparam MAIN_UPDATE = 3'h3;
+ localparam FINAL_UPDATE = 3'h4;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_SBOX = 3'h2;
+ localparam CTRL_MAIN = 3'h3;
+ localparam CTRL_FINAL = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Round functions with sub functions.
+ //----------------------------------------------------------------
+ function [7 : 0] gm2(input [7 : 0] op);
+ begin
+ gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+ end
+ endfunction // gm2
+
+ function [7 : 0] gm3(input [7 : 0] op);
+ begin
+ gm3 = gm2(op) ^ op;
+ end
+ endfunction // gm3
+
+ function [31 : 0] mixw(input [31 : 0] w);
+ reg [7 : 0] b0, b1, b2, b3;
+ reg [7 : 0] mb0, mb1, mb2, mb3;
+ begin
+ b0 = w[31 : 24];
+ b1 = w[23 : 16];
+ b2 = w[15 : 08];
+ b3 = w[07 : 00];
+
+ mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
+ mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
+ mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
+ mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
+
+ mixw = {mb0, mb1, mb2, mb3};
+ end
+ endfunction // mixw
+
+ function [127 : 0] mixcolumns(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = mixw(w0);
+ ws1 = mixw(w1);
+ ws2 = mixw(w2);
+ ws3 = mixw(w3);
+
+ mixcolumns = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // mixcolumns
+
+ function [127 : 0] shiftrows(input [127 : 0] data);
+ reg [31 : 0] w0, w1, w2, w3;
+ reg [31 : 0] ws0, ws1, ws2, ws3;
+ begin
+ w0 = data[127 : 096];
+ w1 = data[095 : 064];
+ w2 = data[063 : 032];
+ w3 = data[031 : 000];
+
+ ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
+ ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
+ ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
+ ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
+
+ shiftrows = {ws0, ws1, ws2, ws3};
+ end
+ endfunction // shiftrows
+
+ function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
+ begin
+ addroundkey = data ^ rkey;
+ end
+ endfunction // addroundkey
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [1 : 0] sword_ctr_reg;
+ reg [1 : 0] sword_ctr_new;
+ reg sword_ctr_we;
+ reg sword_ctr_inc;
+ reg sword_ctr_rst;
+
+ reg [3 : 0] round_ctr_reg;
+ reg [3 : 0] round_ctr_new;
+ reg round_ctr_we;
+ reg round_ctr_rst;
+ reg round_ctr_inc;
+
+ reg [127 : 0] block_new;
+ reg [31 : 0] block_w0_reg;
+ reg [31 : 0] block_w1_reg;
+ reg [31 : 0] block_w2_reg;
+ reg [31 : 0] block_w3_reg;
+ reg block_w0_we;
+ reg block_w1_we;
+ reg block_w2_we;
+ reg block_w3_we;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] enc_ctrl_reg;
+ reg [2 : 0] enc_ctrl_new;
+ reg enc_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [2 : 0] update_type;
+ reg [31 : 0] muxed_sboxw;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign round = round_ctr_reg;
+ assign sboxw = muxed_sboxw;
+ assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ block_w0_reg <= 32'h0;
+ block_w1_reg <= 32'h0;
+ block_w2_reg <= 32'h0;
+ block_w3_reg <= 32'h0;
+ sword_ctr_reg <= 2'h0;
+ round_ctr_reg <= 4'h0;
+ ready_reg <= 1'b1;
+ enc_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (block_w0_we)
+ block_w0_reg <= block_new[127 : 096];
+
+ if (block_w1_we)
+ block_w1_reg <= block_new[095 : 064];
+
+ if (block_w2_we)
+ block_w2_reg <= block_new[063 : 032];
+
+ if (block_w3_we)
+ block_w3_reg <= block_new[031 : 000];
+
+ if (sword_ctr_we)
+ sword_ctr_reg <= sword_ctr_new;
+
+ if (round_ctr_we)
+ round_ctr_reg <= round_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (enc_ctrl_we)
+ enc_ctrl_reg <= enc_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // round_logic
+ //
+ // The logic needed to implement init, main and final rounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_logic
+ reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
+ reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
+
+ block_new = 128'h0;
+ muxed_sboxw = 32'h0;
+ block_w0_we = 1'b0;
+ block_w1_we = 1'b0;
+ block_w2_we = 1'b0;
+ block_w3_we = 1'b0;
+
+ old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
+ shiftrows_block = shiftrows(old_block);
+ mixcolumns_block = mixcolumns(shiftrows_block);
+ addkey_init_block = addroundkey(block, round_key);
+ addkey_main_block = addroundkey(mixcolumns_block, round_key);
+ addkey_final_block = addroundkey(shiftrows_block, round_key);
+
+ case (update_type)
+ INIT_UPDATE:
+ begin
+ block_new = addkey_init_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ SBOX_UPDATE:
+ begin
+ block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
+
+ case (sword_ctr_reg)
+ 2'h0:
+ begin
+ muxed_sboxw = block_w0_reg;
+ block_w0_we = 1'b1;
+ end
+
+ 2'h1:
+ begin
+ muxed_sboxw = block_w1_reg;
+ block_w1_we = 1'b1;
+ end
+
+ 2'h2:
+ begin
+ muxed_sboxw = block_w2_reg;
+ block_w2_we = 1'b1;
+ end
+
+ 2'h3:
+ begin
+ muxed_sboxw = block_w3_reg;
+ block_w3_we = 1'b1;
+ end
+ endcase // case (sbox_mux_ctrl_reg)
+ end
+
+ MAIN_UPDATE:
+ begin
+ block_new = addkey_main_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ FINAL_UPDATE:
+ begin
+ block_new = addkey_final_block;
+ block_w0_we = 1'b1;
+ block_w1_we = 1'b1;
+ block_w2_we = 1'b1;
+ block_w3_we = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (update_type)
+ end // round_logic
+
+
+ //----------------------------------------------------------------
+ // sword_ctr
+ //
+ // The subbytes word counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : sword_ctr
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b0;
+
+ if (sword_ctr_rst)
+ begin
+ sword_ctr_new = 2'h0;
+ sword_ctr_we = 1'b1;
+ end
+ else if (sword_ctr_inc)
+ begin
+ sword_ctr_new = sword_ctr_reg + 1'b1;
+ sword_ctr_we = 1'b1;
+ end
+ end // sword_ctr
+
+
+ //----------------------------------------------------------------
+ // round_ctr
+ //
+ // The round counter with reset and increase logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : round_ctr
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b0;
+
+ if (round_ctr_rst)
+ begin
+ round_ctr_new = 4'h0;
+ round_ctr_we = 1'b1;
+ end
+ else if (round_ctr_inc)
+ begin
+ round_ctr_new = round_ctr_reg + 1'b1;
+ round_ctr_we = 1'b1;
+ end
+ end // round_ctr
+
+
+ //----------------------------------------------------------------
+ // encipher_ctrl
+ //
+ // The FSM that controls the encipher operations.
+ //----------------------------------------------------------------
+ always @*
+ begin: encipher_ctrl
+ reg [3 : 0] num_rounds;
+
+ // Default assignments.
+ sword_ctr_inc = 1'b0;
+ sword_ctr_rst = 1'b0;
+ round_ctr_inc = 1'b0;
+ round_ctr_rst = 1'b0;
+ ready_new = 1'b0;
+ ready_we = 1'b0;
+ update_type = NO_UPDATE;
+ enc_ctrl_new = CTRL_IDLE;
+ enc_ctrl_we = 1'b0;
+
+ if (keylen == AES_256_BIT_KEY)
+ begin
+ num_rounds = AES256_ROUNDS;
+ end
+ else
+ begin
+ num_rounds = AES128_ROUNDS;
+ end
+
+ case(enc_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (next)
+ begin
+ round_ctr_rst = 1'b1;
+ ready_new = 1'b0;
+ ready_we = 1'b1;
+ enc_ctrl_new = CTRL_INIT;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ round_ctr_inc = 1'b1;
+ sword_ctr_rst = 1'b1;
+ update_type = INIT_UPDATE;
+ enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_we = 1'b1;
+ end
+
+ CTRL_SBOX:
+ begin
+ sword_ctr_inc = 1'b1;
+ update_type = SBOX_UPDATE;
+ if (sword_ctr_reg == 2'h3)
+ begin
+ enc_ctrl_new = CTRL_MAIN;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_MAIN:
+ begin
+ sword_ctr_rst = 1'b1;
+ round_ctr_inc = 1'b1;
+ if (round_ctr_reg < num_rounds)
+ begin
+ update_type = MAIN_UPDATE;
+ enc_ctrl_new = CTRL_SBOX;
+ enc_ctrl_we = 1'b1;
+ end
+ else
+ begin
+ update_type = FINAL_UPDATE;
+ ready_new = 1'b1;
+ ready_we = 1'b1;
+ enc_ctrl_new = CTRL_IDLE;
+ enc_ctrl_we = 1'b1;
+ end
+ end
+
+ default:
+ begin
+ // Empty. Just here to make the synthesis tool happy.
+ end
+ endcase // case (enc_ctrl_reg)
+ end // encipher_ctrl
+
+endmodule // aes_encipher_block
+
+//======================================================================
+// EOF aes_encipher_block.v
+//======================================================================
+
+
diff --git a/openlane/designs/blabla/config.tcl b/openlane/designs/blabla/config.tcl
new file mode 100755
index 0000000..cfafc3a
--- /dev/null
+++ b/openlane/designs/blabla/config.tcl
@@ -0,0 +1,15 @@
+set ::env(DESIGN_NAME) "blabla"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/blabla.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+# design has a lot of pins, needs an absolute size
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) {0 0 1200 1200}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/blabla/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/blabla/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..3cc2f3b
--- /dev/null
+++ b/openlane/designs/blabla/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "65.0"
+set ::env(FP_CORE_UTIL) 11
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/blabla/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/blabla/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..15b9444
--- /dev/null
+++ b/openlane/designs/blabla/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 13
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "65.0"
+
diff --git a/openlane/designs/blabla/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/blabla/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..15b9444
--- /dev/null
+++ b/openlane/designs/blabla/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 13
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "65.0"
+
diff --git a/openlane/designs/blabla/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/blabla/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..15b9444
--- /dev/null
+++ b/openlane/designs/blabla/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 13
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "65.0"
+
diff --git a/openlane/designs/blabla/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/blabla/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..15b9444
--- /dev/null
+++ b/openlane/designs/blabla/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 13
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "65.0"
+
diff --git a/openlane/designs/blabla/src/blabla.v b/openlane/designs/blabla/src/blabla.v
new file mode 100644
index 0000000..905ae7e
--- /dev/null
+++ b/openlane/designs/blabla/src/blabla.v
@@ -0,0 +1,775 @@
+//======================================================================
+//
+// blabla_core.v
+// --------------
+// Verilog 2001 implementation of the stream cipher BlaBla.
+// This is the internal core with wide interfaces.
+//
+//
+// Author: Joachim Strömbergson
+// Copyright (c) 2017 Assured AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module blabla(
+ input wire clk,
+ input wire reset_n,
+
+ input wire init,
+ input wire next,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+ input wire [63 : 0] iv,
+ input wire [63 : 0] ctr,
+ input wire [4 : 0] rounds,
+
+ input wire [511 : 0] data_in,
+
+ output wire ready,
+
+ output wire [511 : 0] data_out,
+ output wire data_out_valid
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ // Datapath quartterround states names.
+ localparam QR0 = 0;
+ localparam QR1 = 1;
+
+ localparam NUM_ROUNDS = 4'h8;
+
+ localparam TAU0 = 32'h61707865;
+ localparam TAU1 = 32'h3120646e;
+ localparam TAU2 = 32'h79622d36;
+ localparam TAU3 = 32'h6b206574;
+
+ localparam SIGMA0 = 32'h61707865;
+ localparam SIGMA1 = 32'h3320646e;
+ localparam SIGMA2 = 32'h79622d32;
+ localparam SIGMA3 = 32'h6b206574;
+
+ localparam CTRL_IDLE = 3'h0;
+ localparam CTRL_INIT = 3'h1;
+ localparam CTRL_ROUNDS = 3'h2;
+ localparam CTRL_FINALIZE = 3'h3;
+ localparam CTRL_DONE = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // l2b()
+ //
+ // Swap bytes from little to big endian byte order.
+ //----------------------------------------------------------------
+ function [31 : 0] l2b(input [31 : 0] op);
+ begin
+ l2b = {op[7 : 0], op[15 : 8], op[23 : 16], op[31 : 24]};
+ end
+ endfunction // b2l
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [63 : 0] state_reg [0 : 15];
+ reg [63 : 0] state_new [0 : 15];
+ reg state_we;
+
+ reg [511 : 0] data_out_reg;
+ reg [511 : 0] data_out_new;
+
+ reg data_out_valid_reg;
+ reg data_out_valid_new;
+ reg data_out_valid_we;
+
+ reg qr_ctr_reg;
+ reg qr_ctr_new;
+ reg qr_ctr_we;
+ reg qr_ctr_inc;
+ reg qr_ctr_rst;
+
+ reg [3 : 0] dr_ctr_reg;
+ reg [3 : 0] dr_ctr_new;
+ reg dr_ctr_we;
+ reg dr_ctr_inc;
+ reg dr_ctr_rst;
+
+ reg [31 : 0] block0_ctr_reg;
+ reg [31 : 0] block0_ctr_new;
+ reg block0_ctr_we;
+ reg [31 : 0] block1_ctr_reg;
+ reg [31 : 0] block1_ctr_new;
+ reg block1_ctr_we;
+ reg block_ctr_inc;
+ reg block_ctr_set;
+
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
+ reg [2 : 0] blabla_ctrl_reg;
+ reg [2 : 0] blabla_ctrl_new;
+ reg blabla_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] init_state_word [0 : 15];
+
+ reg init_state;
+ reg update_state;
+ reg update_output;
+
+ reg [63 : 0] qr0_a;
+ reg [63 : 0] qr0_b;
+ reg [63 : 0] qr0_c;
+ reg [63 : 0] qr0_d;
+ wire [63 : 0] qr0_a_prim;
+ wire [63 : 0] qr0_b_prim;
+ wire [63 : 0] qr0_c_prim;
+ wire [63 : 0] qr0_d_prim;
+ reg [63 : 0] qr1_a;
+ reg [63 : 0] qr1_b;
+ reg [63 : 0] qr1_c;
+ reg [63 : 0] qr1_d;
+ wire [63 : 0] qr1_a_prim;
+ wire [63 : 0] qr1_b_prim;
+ wire [63 : 0] qr1_c_prim;
+ wire [63 : 0] qr1_d_prim;
+ reg [63 : 0] qr2_a;
+ reg [63 : 0] qr2_b;
+ reg [63 : 0] qr2_c;
+ reg [63 : 0] qr2_d;
+ wire [63 : 0] qr2_a_prim;
+ wire [63 : 0] qr2_b_prim;
+ wire [63 : 0] qr2_c_prim;
+ wire [63 : 0] qr2_d_prim;
+ reg [63 : 0] qr3_a;
+ reg [63 : 0] qr3_b;
+ reg [63 : 0] qr3_c;
+ reg [63 : 0] qr3_d;
+ wire [63 : 0] qr3_a_prim;
+ wire [63 : 0] qr3_b_prim;
+ wire [63 : 0] qr3_c_prim;
+ wire [63 : 0] qr3_d_prim;
+
+
+ //----------------------------------------------------------------
+ // Instantiation of the qr modules.
+ //----------------------------------------------------------------
+ blabla_qr qr0(
+ .a(qr0_a),
+ .b(qr0_b),
+ .c(qr0_c),
+ .d(qr0_d),
+
+ .a_prim(qr0_a_prim),
+ .b_prim(qr0_b_prim),
+ .c_prim(qr0_c_prim),
+ .d_prim(qr0_d_prim)
+ );
+
+ blabla_qr qr1(
+ .a(qr1_a),
+ .b(qr1_b),
+ .c(qr1_c),
+ .d(qr1_d),
+
+ .a_prim(qr1_a_prim),
+ .b_prim(qr1_b_prim),
+ .c_prim(qr1_c_prim),
+ .d_prim(qr1_d_prim)
+ );
+
+ blabla_qr qr2(
+ .a(qr2_a),
+ .b(qr2_b),
+ .c(qr2_c),
+ .d(qr2_d),
+
+ .a_prim(qr2_a_prim),
+ .b_prim(qr2_b_prim),
+ .c_prim(qr2_c_prim),
+ .d_prim(qr2_d_prim)
+ );
+
+ blabla_qr qr3(
+ .a(qr3_a),
+ .b(qr3_b),
+ .c(qr3_c),
+ .d(qr3_d),
+
+ .a_prim(qr3_a_prim),
+ .b_prim(qr3_b_prim),
+ .c_prim(qr3_c_prim),
+ .d_prim(qr3_d_prim)
+ );
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign data_out = data_out_reg;
+ assign data_out_valid = data_out_valid_reg;
+ assign ready = ready_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with synchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk)
+ begin : reg_update
+ integer i;
+
+ if (!reset_n)
+ begin
+ for (i = 0 ; i < 16 ; i = i + 1)
+ state_reg[i] <= 32'h0;
+
+ data_out_reg <= 512'h0;
+ data_out_valid_reg <= 0;
+ qr_ctr_reg <= QR0;
+ dr_ctr_reg <= 0;
+ block0_ctr_reg <= 32'h0;
+ block1_ctr_reg <= 32'h0;
+ blabla_ctrl_reg <= CTRL_IDLE;
+ ready_reg <= 1;
+ end
+ else
+ begin
+ if (state_we)
+ begin
+ for (i = 0 ; i < 16 ; i = i + 1)
+ state_reg[i] <= state_new[i];
+ end
+
+ if (update_output)
+ data_out_reg <= data_out_new;
+
+ if (data_out_valid_we)
+ data_out_valid_reg <= data_out_valid_new;
+
+ if (qr_ctr_we)
+ qr_ctr_reg <= qr_ctr_new;
+
+ if (dr_ctr_we)
+ dr_ctr_reg <= dr_ctr_new;
+
+ if (block0_ctr_we)
+ block0_ctr_reg <= block0_ctr_new;
+
+ if (block1_ctr_we)
+ block1_ctr_reg <= block1_ctr_new;
+
+ if (ready_we)
+ ready_reg <= ready_new;
+
+ if (blabla_ctrl_we)
+ blabla_ctrl_reg <= blabla_ctrl_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // init_state_logic
+ //
+ // Calculates the initial state for a given block.
+ //----------------------------------------------------------------
+ always @*
+ begin : init_state_logic
+ reg [31 : 0] key0;
+ reg [31 : 0] key1;
+ reg [31 : 0] key2;
+ reg [31 : 0] key3;
+ reg [31 : 0] key4;
+ reg [31 : 0] key5;
+ reg [31 : 0] key6;
+ reg [31 : 0] key7;
+
+ key0 = l2b(key[255 : 224]);
+ key1 = l2b(key[223 : 192]);
+ key2 = l2b(key[191 : 160]);
+ key3 = l2b(key[159 : 128]);
+ key4 = l2b(key[127 : 96]);
+ key5 = l2b(key[95 : 64]);
+ key6 = l2b(key[63 : 32]);
+ key7 = l2b(key[31 : 0]);
+
+ init_state_word[04] = key0;
+ init_state_word[05] = key1;
+ init_state_word[06] = key2;
+ init_state_word[07] = key3;
+ init_state_word[12] = block0_ctr_reg;
+ init_state_word[13] = block1_ctr_reg;
+ init_state_word[14] = l2b(iv[63 : 32]);
+ init_state_word[15] = l2b(iv[31 : 0]);
+
+ if (keylen)
+ begin
+ // 256 bit key.
+ init_state_word[00] = SIGMA0;
+ init_state_word[01] = SIGMA1;
+ init_state_word[02] = SIGMA2;
+ init_state_word[03] = SIGMA3;
+ init_state_word[08] = key4;
+ init_state_word[09] = key5;
+ init_state_word[10] = key6;
+ init_state_word[11] = key7;
+ end
+ else
+ begin
+ // 128 bit key.
+ init_state_word[00] = TAU0;
+ init_state_word[01] = TAU1;
+ init_state_word[02] = TAU2;
+ init_state_word[03] = TAU3;
+ init_state_word[08] = key0;
+ init_state_word[09] = key1;
+ init_state_word[10] = key2;
+ init_state_word[11] = key3;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // state_logic
+ // Logic to init and update the internal state.
+ //----------------------------------------------------------------
+ always @*
+ begin : state_logic
+ integer i;
+
+ for (i = 0 ; i < 16 ; i = i + 1)
+ state_new[i] = 64'h0;
+ state_we = 0;
+
+ qr0_a = 64'h0;
+ qr0_b = 64'h0;
+ qr0_c = 64'h0;
+ qr0_d = 64'h0;
+ qr1_a = 64'h0;
+ qr1_b = 64'h0;
+ qr1_c = 64'h0;
+ qr1_d = 64'h0;
+ qr2_a = 64'h0;
+ qr2_b = 64'h0;
+ qr2_c = 64'h0;
+ qr2_d = 64'h0;
+ qr3_a = 64'h0;
+ qr3_b = 64'h0;
+ qr3_c = 64'h0;
+ qr3_d = 64'h0;
+
+ if (init_state)
+ begin
+ for (i = 0 ; i < 16 ; i = i + 1)
+ state_new[i] = init_state_word[i];
+ state_we = 1;
+ end // if (init_state)
+
+ if (update_state)
+ begin
+ state_we = 1;
+ case (qr_ctr_reg)
+ QR0:
+ begin
+ qr0_a = state_reg[00];
+ qr0_b = state_reg[04];
+ qr0_c = state_reg[08];
+ qr0_d = state_reg[12];
+ qr1_a = state_reg[01];
+ qr1_b = state_reg[05];
+ qr1_c = state_reg[09];
+ qr1_d = state_reg[13];
+ qr2_a = state_reg[02];
+ qr2_b = state_reg[06];
+ qr2_c = state_reg[10];
+ qr2_d = state_reg[14];
+ qr3_a = state_reg[03];
+ qr3_b = state_reg[07];
+ qr3_c = state_reg[11];
+ qr3_d = state_reg[15];
+ state_new[00] = qr0_a_prim;
+ state_new[04] = qr0_b_prim;
+ state_new[08] = qr0_c_prim;
+ state_new[12] = qr0_d_prim;
+ state_new[01] = qr1_a_prim;
+ state_new[05] = qr1_b_prim;
+ state_new[09] = qr1_c_prim;
+ state_new[13] = qr1_d_prim;
+ state_new[02] = qr2_a_prim;
+ state_new[06] = qr2_b_prim;
+ state_new[10] = qr2_c_prim;
+ state_new[14] = qr2_d_prim;
+ state_new[03] = qr3_a_prim;
+ state_new[07] = qr3_b_prim;
+ state_new[11] = qr3_c_prim;
+ state_new[15] = qr3_d_prim;
+ end
+
+ QR1:
+ begin
+ qr0_a = state_reg[00];
+ qr0_b = state_reg[05];
+ qr0_c = state_reg[10];
+ qr0_d = state_reg[15];
+ qr1_a = state_reg[01];
+ qr1_b = state_reg[06];
+ qr1_c = state_reg[11];
+ qr1_d = state_reg[12];
+ qr2_a = state_reg[02];
+ qr2_b = state_reg[07];
+ qr2_c = state_reg[08];
+ qr2_d = state_reg[13];
+ qr3_a = state_reg[03];
+ qr3_b = state_reg[04];
+ qr3_c = state_reg[09];
+ qr3_d = state_reg[14];
+ state_new[00] = qr0_a_prim;
+ state_new[05] = qr0_b_prim;
+ state_new[10] = qr0_c_prim;
+ state_new[15] = qr0_d_prim;
+ state_new[01] = qr1_a_prim;
+ state_new[06] = qr1_b_prim;
+ state_new[11] = qr1_c_prim;
+ state_new[12] = qr1_d_prim;
+ state_new[02] = qr2_a_prim;
+ state_new[07] = qr2_b_prim;
+ state_new[08] = qr2_c_prim;
+ state_new[13] = qr2_d_prim;
+ state_new[03] = qr3_a_prim;
+ state_new[04] = qr3_b_prim;
+ state_new[09] = qr3_c_prim;
+ state_new[14] = qr3_d_prim;
+ end
+ endcase // case (quarterround_select)
+ end // if (update_state)
+ end // state_logic
+
+
+ //----------------------------------------------------------------
+ // data_out_logic
+ // Final output logic that combines the result from state
+ // update with the input block. This adds a 16 rounds and
+ // a final layer of XOR gates.
+ //
+ // Note that we also remap all the words into LSB format.
+ //----------------------------------------------------------------
+ always @*
+ begin : data_out_logic
+ integer i;
+ reg [31 : 0] msb_block_state [0 : 15];
+ reg [31 : 0] lsb_block_state [0 : 15];
+ reg [511 : 0] block_state;
+
+ for (i = 0 ; i < 16 ; i = i + 1)
+ begin
+ msb_block_state[i] = init_state_word[i] + state_reg[i];
+ lsb_block_state[i] = l2b(msb_block_state[i][31 : 0]);
+ end
+
+ block_state = {lsb_block_state[00], lsb_block_state[01],
+ lsb_block_state[02], lsb_block_state[03],
+ lsb_block_state[04], lsb_block_state[05],
+ lsb_block_state[06], lsb_block_state[07],
+ lsb_block_state[08], lsb_block_state[09],
+ lsb_block_state[10], lsb_block_state[11],
+ lsb_block_state[12], lsb_block_state[13],
+ lsb_block_state[14], lsb_block_state[15]};
+
+ data_out_new = data_in ^ block_state;
+ end // data_out_logic
+
+
+ //----------------------------------------------------------------
+ // qr_ctr
+ // Update logic for the quarterround counter, a monotonically
+ // increasing counter with reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : qr_ctr
+ qr_ctr_new = 0;
+ qr_ctr_we = 0;
+
+ if (qr_ctr_rst)
+ begin
+ qr_ctr_new = 0;
+ qr_ctr_we = 1;
+ end
+
+ if (qr_ctr_inc)
+ begin
+ qr_ctr_new = qr_ctr_reg + 1'b1;
+ qr_ctr_we = 1;
+ end
+ end // qr_ctr
+
+
+ //----------------------------------------------------------------
+ // dr_ctr
+ // Update logic for the round counter, a monotonically
+ // increasing counter with reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : dr_ctr
+ dr_ctr_new = 0;
+ dr_ctr_we = 0;
+
+ if (dr_ctr_rst)
+ begin
+ dr_ctr_new = 0;
+ dr_ctr_we = 1;
+ end
+
+ if (dr_ctr_inc)
+ begin
+ dr_ctr_new = dr_ctr_reg + 1'b1;
+ dr_ctr_we = 1;
+ end
+ end // dr_ctr
+
+
+ //----------------------------------------------------------------
+ // block_ctr
+ // Update logic for the 64-bit block counter, a monotonically
+ // increasing counter with reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : block_ctr
+ block0_ctr_new = 32'h0;
+ block1_ctr_new = 32'h0;
+ block0_ctr_we = 0;
+ block1_ctr_we = 0;
+
+ if (block_ctr_set)
+ begin
+ block0_ctr_new = ctr[31 : 00];
+ block1_ctr_new = ctr[63 : 32];
+ block0_ctr_we = 1;
+ block1_ctr_we = 1;
+ end
+
+ if (block_ctr_inc)
+ begin
+ block0_ctr_new = block0_ctr_reg + 1;
+ block0_ctr_we = 1;
+
+ // Avoid chaining the 32-bit adders.
+ if (block0_ctr_reg == 32'hffffffff)
+ begin
+ block1_ctr_new = block1_ctr_reg + 1;
+ block1_ctr_we = 1;
+ end
+ end
+ end // block_ctr
+
+
+ //----------------------------------------------------------------
+ // blabla_ctrl_fsm
+ // Logic for the state machine controlling the core behaviour.
+ //----------------------------------------------------------------
+ always @*
+ begin : blabla_ctrl_fsm
+ init_state = 0;
+ update_state = 0;
+ update_output = 0;
+ qr_ctr_inc = 0;
+ qr_ctr_rst = 0;
+ dr_ctr_inc = 0;
+ dr_ctr_rst = 0;
+ block_ctr_inc = 0;
+ block_ctr_set = 0;
+ ready_new = 0;
+ ready_we = 0;
+ data_out_valid_new = 0;
+ data_out_valid_we = 0;
+ blabla_ctrl_new = CTRL_IDLE;
+ blabla_ctrl_we = 0;
+
+ case (blabla_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (init)
+ begin
+ block_ctr_set = 1;
+ ready_new = 0;
+ ready_we = 1;
+ blabla_ctrl_new = CTRL_INIT;
+ blabla_ctrl_we = 1;
+ end
+ end
+
+ CTRL_INIT:
+ begin
+ init_state = 1;
+ qr_ctr_rst = 1;
+ dr_ctr_rst = 1;
+ blabla_ctrl_new = CTRL_ROUNDS;
+ blabla_ctrl_we = 1;
+ end
+
+ CTRL_ROUNDS:
+ begin
+ update_state = 1;
+ qr_ctr_inc = 1;
+ if (qr_ctr_reg == QR1)
+ begin
+ dr_ctr_inc = 1;
+ if (dr_ctr_reg == (rounds[4 : 1] - 1))
+ begin
+ blabla_ctrl_new = CTRL_FINALIZE;
+ blabla_ctrl_we = 1;
+ end
+ end
+ end
+
+ CTRL_FINALIZE:
+ begin
+ ready_new = 1;
+ ready_we = 1;
+ update_output = 1;
+ data_out_valid_new = 1;
+ data_out_valid_we = 1;
+ blabla_ctrl_new = CTRL_DONE;
+ blabla_ctrl_we = 1;
+ end
+
+ CTRL_DONE:
+ begin
+ if (init)
+ begin
+ ready_new = 0;
+ ready_we = 1;
+ data_out_valid_new = 0;
+ data_out_valid_we = 1;
+ block_ctr_set = 1;
+ blabla_ctrl_new = CTRL_INIT;
+ blabla_ctrl_we = 1;
+ end
+ else if (next)
+ begin
+ ready_new = 0;
+ ready_we = 1;
+ data_out_valid_new = 0;
+ data_out_valid_we = 1;
+ block_ctr_inc = 1;
+ blabla_ctrl_new = CTRL_INIT;
+ blabla_ctrl_we = 1;
+ end
+ end
+
+ default:
+ begin
+
+ end
+ endcase // case (blabla_ctrl_reg)
+ end // blabla_ctrl_fsm
+endmodule // blabla_core
+
+//======================================================================
+// EOF blabla_core.v
+//======================================================================
+
+module blabla_qr(
+ input wire [63 : 0] a,
+ input wire [63 : 0] b,
+ input wire [63 : 0] c,
+ input wire [63 : 0] d,
+
+ output wire [63 : 0] a_prim,
+ output wire [63 : 0] b_prim,
+ output wire [63 : 0] c_prim,
+ output wire [63 : 0] d_prim
+ );
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [63 : 0] internal_a_prim;
+ reg [63 : 0] internal_b_prim;
+ reg [63 : 0] internal_c_prim;
+ reg [63 : 0] internal_d_prim;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports.
+ //----------------------------------------------------------------
+ assign a_prim = internal_a_prim;
+ assign b_prim = internal_b_prim;
+ assign c_prim = internal_c_prim;
+ assign d_prim = internal_d_prim;
+
+
+ //----------------------------------------------------------------
+ // qr
+ //
+ // The actual quarterround function.
+ //----------------------------------------------------------------
+ always @*
+ begin : qr
+ reg [63 : 0] a0;
+ reg [63 : 0] a1;
+ reg [63 : 0] b0;
+ reg [63 : 0] b1;
+ reg [63 : 0] b2;
+ reg [63 : 0] b3;
+ reg [63 : 0] c0;
+ reg [63 : 0] c1;
+ reg [63 : 0] d0;
+ reg [63 : 0] d1;
+ reg [63 : 0] d2;
+ reg [63 : 0] d3;
+
+ a0 = a + b;
+ d0 = d ^ a0;
+ d1 = {d0[15 : 0], d0[31 : 16]};
+ c0 = c + d1;
+ b0 = b ^ c0;
+ b1 = {b0[19 : 0], b0[31 : 20]};
+ a1 = a0 + b1;
+ d2 = d1 ^ a1;
+ d3 = {d2[23 : 0], d2[31 : 24]};
+ c1 = c0 + d3;
+ b2 = b1 ^ c1;
+ b3 = {b2[24 : 0], b2[31 : 25]};
+
+ internal_a_prim = a1;
+ internal_b_prim = b3;
+ internal_c_prim = c1;
+ internal_d_prim = d3;
+ end // qr
+endmodule // blabla_qr
\ No newline at end of file
diff --git a/openlane/designs/caravel_upw/config.tcl b/openlane/designs/caravel_upw/config.tcl
new file mode 100644
index 0000000..3913c74
--- /dev/null
+++ b/openlane/designs/caravel_upw/config.tcl
@@ -0,0 +1,130 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+set script_dir [file dirname [file normalize [info script]]]
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+# Pin Configurations. DON'T TOUCH
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_VOFFSET) 14
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+#section end
+
+# User Configurations
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+ $script_dir/src/defines.v \
+ $script_dir/src/user_project_wrapper.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj1.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+ mprj1 vccd1 vssd1,\
+ mprj2 vccd2 vssd2"
+
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $script_dir/src/defines.v
+ $script_dir/src/user_proj_example.v
+ $script_dir/src/user_proj_example2.v"
+
+set ::env(EXTRA_LEFS) "\
+ $script_dir/macros/user_proj_example.lef
+ $script_dir/macros/user_proj_example2.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/macros/user_proj_example.gds
+ $script_dir/macros/user_proj_example2.gds"
+
+set ::env(RT_MAX_LAYER) {met4}
+
+# disable pdn check nodes becuase it hangs with multiple power domains.
+# any issue with pdn connections will be flagged with LVS so it is not a critical check.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(FILL_INSERTION) 0
+set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/designs/caravel_upw/macro.cfg b/openlane/designs/caravel_upw/macro.cfg
new file mode 100644
index 0000000..17e9019
--- /dev/null
+++ b/openlane/designs/caravel_upw/macro.cfg
@@ -0,0 +1,2 @@
+mprj1 1175 1690 N
+mprj2 1175 400 N
diff --git a/openlane/designs/caravel_upw/macros/user_proj_example.gds b/openlane/designs/caravel_upw/macros/user_proj_example.gds
new file mode 100644
index 0000000..b32ae18
--- /dev/null
+++ b/openlane/designs/caravel_upw/macros/user_proj_example.gds
Binary files differ
diff --git a/openlane/designs/caravel_upw/macros/user_proj_example.lef b/openlane/designs/caravel_upw/macros/user_proj_example.lef
new file mode 100644
index 0000000..0297dcc
--- /dev/null
+++ b/openlane/designs/caravel_upw/macros/user_proj_example.lef
@@ -0,0 +1,5503 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO user_proj_example
+ CLASS BLOCK ;
+ FOREIGN user_proj_example ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 900.000 BY 600.000 ;
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 3.770 596.000 4.050 600.000 ;
+ END
+ END io_in[0]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 240.670 596.000 240.950 600.000 ;
+ END
+ END io_in[10]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 264.130 596.000 264.410 600.000 ;
+ END
+ END io_in[11]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 288.050 596.000 288.330 600.000 ;
+ END
+ END io_in[12]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 311.510 596.000 311.790 600.000 ;
+ END
+ END io_in[13]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 335.430 596.000 335.710 600.000 ;
+ END
+ END io_in[14]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 358.890 596.000 359.170 600.000 ;
+ END
+ END io_in[15]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 382.810 596.000 383.090 600.000 ;
+ END
+ END io_in[16]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 406.270 596.000 406.550 600.000 ;
+ END
+ END io_in[17]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 430.190 596.000 430.470 600.000 ;
+ END
+ END io_in[18]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.650 596.000 453.930 600.000 ;
+ END
+ END io_in[19]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.230 596.000 27.510 600.000 ;
+ END
+ END io_in[1]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 477.570 596.000 477.850 600.000 ;
+ END
+ END io_in[20]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 501.030 596.000 501.310 600.000 ;
+ END
+ END io_in[21]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 524.950 596.000 525.230 600.000 ;
+ END
+ END io_in[22]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 548.410 596.000 548.690 600.000 ;
+ END
+ END io_in[23]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 572.330 596.000 572.610 600.000 ;
+ END
+ END io_in[24]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 595.790 596.000 596.070 600.000 ;
+ END
+ END io_in[25]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 619.710 596.000 619.990 600.000 ;
+ END
+ END io_in[26]
+ PIN io_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 643.170 596.000 643.450 600.000 ;
+ END
+ END io_in[27]
+ PIN io_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 667.090 596.000 667.370 600.000 ;
+ END
+ END io_in[28]
+ PIN io_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 690.550 596.000 690.830 600.000 ;
+ END
+ END io_in[29]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 51.150 596.000 51.430 600.000 ;
+ END
+ END io_in[2]
+ PIN io_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 714.470 596.000 714.750 600.000 ;
+ END
+ END io_in[30]
+ PIN io_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 737.930 596.000 738.210 600.000 ;
+ END
+ END io_in[31]
+ PIN io_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 761.850 596.000 762.130 600.000 ;
+ END
+ END io_in[32]
+ PIN io_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 785.310 596.000 785.590 600.000 ;
+ END
+ END io_in[33]
+ PIN io_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 809.230 596.000 809.510 600.000 ;
+ END
+ END io_in[34]
+ PIN io_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 832.690 596.000 832.970 600.000 ;
+ END
+ END io_in[35]
+ PIN io_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 856.610 596.000 856.890 600.000 ;
+ END
+ END io_in[36]
+ PIN io_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 880.070 596.000 880.350 600.000 ;
+ END
+ END io_in[37]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 74.610 596.000 74.890 600.000 ;
+ END
+ END io_in[3]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.530 596.000 98.810 600.000 ;
+ END
+ END io_in[4]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 121.990 596.000 122.270 600.000 ;
+ END
+ END io_in[5]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 145.910 596.000 146.190 600.000 ;
+ END
+ END io_in[6]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 169.370 596.000 169.650 600.000 ;
+ END
+ END io_in[7]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.290 596.000 193.570 600.000 ;
+ END
+ END io_in[8]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 216.750 596.000 217.030 600.000 ;
+ END
+ END io_in[9]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 11.590 596.000 11.870 600.000 ;
+ END
+ END io_oeb[0]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 248.490 596.000 248.770 600.000 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 271.950 596.000 272.230 600.000 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 295.870 596.000 296.150 600.000 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 319.330 596.000 319.610 600.000 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 343.250 596.000 343.530 600.000 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 366.710 596.000 366.990 600.000 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 390.630 596.000 390.910 600.000 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 414.090 596.000 414.370 600.000 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 438.010 596.000 438.290 600.000 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 461.470 596.000 461.750 600.000 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 35.050 596.000 35.330 600.000 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.390 596.000 485.670 600.000 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 508.850 596.000 509.130 600.000 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 532.770 596.000 533.050 600.000 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 556.230 596.000 556.510 600.000 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 580.150 596.000 580.430 600.000 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 603.610 596.000 603.890 600.000 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 627.530 596.000 627.810 600.000 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 650.990 596.000 651.270 600.000 ;
+ END
+ END io_oeb[27]
+ PIN io_oeb[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 674.910 596.000 675.190 600.000 ;
+ END
+ END io_oeb[28]
+ PIN io_oeb[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 698.370 596.000 698.650 600.000 ;
+ END
+ END io_oeb[29]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 58.970 596.000 59.250 600.000 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 722.290 596.000 722.570 600.000 ;
+ END
+ END io_oeb[30]
+ PIN io_oeb[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 745.750 596.000 746.030 600.000 ;
+ END
+ END io_oeb[31]
+ PIN io_oeb[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 769.670 596.000 769.950 600.000 ;
+ END
+ END io_oeb[32]
+ PIN io_oeb[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 793.130 596.000 793.410 600.000 ;
+ END
+ END io_oeb[33]
+ PIN io_oeb[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 817.050 596.000 817.330 600.000 ;
+ END
+ END io_oeb[34]
+ PIN io_oeb[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 840.510 596.000 840.790 600.000 ;
+ END
+ END io_oeb[35]
+ PIN io_oeb[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 864.430 596.000 864.710 600.000 ;
+ END
+ END io_oeb[36]
+ PIN io_oeb[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 887.890 596.000 888.170 600.000 ;
+ END
+ END io_oeb[37]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 82.430 596.000 82.710 600.000 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 106.350 596.000 106.630 600.000 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 129.810 596.000 130.090 600.000 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 153.730 596.000 154.010 600.000 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 177.190 596.000 177.470 600.000 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 201.110 596.000 201.390 600.000 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 224.570 596.000 224.850 600.000 ;
+ END
+ END io_oeb[9]
+ PIN io_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 19.410 596.000 19.690 600.000 ;
+ END
+ END io_out[0]
+ PIN io_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 256.310 596.000 256.590 600.000 ;
+ END
+ END io_out[10]
+ PIN io_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 279.770 596.000 280.050 600.000 ;
+ END
+ END io_out[11]
+ PIN io_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 303.690 596.000 303.970 600.000 ;
+ END
+ END io_out[12]
+ PIN io_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.150 596.000 327.430 600.000 ;
+ END
+ END io_out[13]
+ PIN io_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.070 596.000 351.350 600.000 ;
+ END
+ END io_out[14]
+ PIN io_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.530 596.000 374.810 600.000 ;
+ END
+ END io_out[15]
+ PIN io_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 398.450 596.000 398.730 600.000 ;
+ END
+ END io_out[16]
+ PIN io_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 421.910 596.000 422.190 600.000 ;
+ END
+ END io_out[17]
+ PIN io_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.830 596.000 446.110 600.000 ;
+ END
+ END io_out[18]
+ PIN io_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.290 596.000 469.570 600.000 ;
+ END
+ END io_out[19]
+ PIN io_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 42.870 596.000 43.150 600.000 ;
+ END
+ END io_out[1]
+ PIN io_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 493.210 596.000 493.490 600.000 ;
+ END
+ END io_out[20]
+ PIN io_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 516.670 596.000 516.950 600.000 ;
+ END
+ END io_out[21]
+ PIN io_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 540.590 596.000 540.870 600.000 ;
+ END
+ END io_out[22]
+ PIN io_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 564.050 596.000 564.330 600.000 ;
+ END
+ END io_out[23]
+ PIN io_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 587.970 596.000 588.250 600.000 ;
+ END
+ END io_out[24]
+ PIN io_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 611.430 596.000 611.710 600.000 ;
+ END
+ END io_out[25]
+ PIN io_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 635.350 596.000 635.630 600.000 ;
+ END
+ END io_out[26]
+ PIN io_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 658.810 596.000 659.090 600.000 ;
+ END
+ END io_out[27]
+ PIN io_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 682.730 596.000 683.010 600.000 ;
+ END
+ END io_out[28]
+ PIN io_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 706.190 596.000 706.470 600.000 ;
+ END
+ END io_out[29]
+ PIN io_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 66.790 596.000 67.070 600.000 ;
+ END
+ END io_out[2]
+ PIN io_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 730.110 596.000 730.390 600.000 ;
+ END
+ END io_out[30]
+ PIN io_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 753.570 596.000 753.850 600.000 ;
+ END
+ END io_out[31]
+ PIN io_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 777.490 596.000 777.770 600.000 ;
+ END
+ END io_out[32]
+ PIN io_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 800.950 596.000 801.230 600.000 ;
+ END
+ END io_out[33]
+ PIN io_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 824.870 596.000 825.150 600.000 ;
+ END
+ END io_out[34]
+ PIN io_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 848.330 596.000 848.610 600.000 ;
+ END
+ END io_out[35]
+ PIN io_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 872.250 596.000 872.530 600.000 ;
+ END
+ END io_out[36]
+ PIN io_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 895.710 596.000 895.990 600.000 ;
+ END
+ END io_out[37]
+ PIN io_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 90.250 596.000 90.530 600.000 ;
+ END
+ END io_out[3]
+ PIN io_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 114.170 596.000 114.450 600.000 ;
+ END
+ END io_out[4]
+ PIN io_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 137.630 596.000 137.910 600.000 ;
+ END
+ END io_out[5]
+ PIN io_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.550 596.000 161.830 600.000 ;
+ END
+ END io_out[6]
+ PIN io_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 185.010 596.000 185.290 600.000 ;
+ END
+ END io_out[7]
+ PIN io_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 208.930 596.000 209.210 600.000 ;
+ END
+ END io_out[8]
+ PIN io_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 232.390 596.000 232.670 600.000 ;
+ END
+ END io_out[9]
+ PIN irq[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 895.250 0.000 895.530 4.000 ;
+ END
+ END irq[0]
+ PIN irq[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 897.090 0.000 897.370 4.000 ;
+ END
+ END irq[1]
+ PIN irq[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 898.930 0.000 899.210 4.000 ;
+ END
+ END irq[2]
+ PIN la_data_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.750 0.000 194.030 4.000 ;
+ END
+ END la_data_in[0]
+ PIN la_data_in[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 741.610 0.000 741.890 4.000 ;
+ END
+ END la_data_in[100]
+ PIN la_data_in[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 747.130 0.000 747.410 4.000 ;
+ END
+ END la_data_in[101]
+ PIN la_data_in[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 752.650 0.000 752.930 4.000 ;
+ END
+ END la_data_in[102]
+ PIN la_data_in[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 758.170 0.000 758.450 4.000 ;
+ END
+ END la_data_in[103]
+ PIN la_data_in[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 763.690 0.000 763.970 4.000 ;
+ END
+ END la_data_in[104]
+ PIN la_data_in[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 769.210 0.000 769.490 4.000 ;
+ END
+ END la_data_in[105]
+ PIN la_data_in[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 774.730 0.000 775.010 4.000 ;
+ END
+ END la_data_in[106]
+ PIN la_data_in[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 780.250 0.000 780.530 4.000 ;
+ END
+ END la_data_in[107]
+ PIN la_data_in[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 785.310 0.000 785.590 4.000 ;
+ END
+ END la_data_in[108]
+ PIN la_data_in[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 790.830 0.000 791.110 4.000 ;
+ END
+ END la_data_in[109]
+ PIN la_data_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 248.490 0.000 248.770 4.000 ;
+ END
+ END la_data_in[10]
+ PIN la_data_in[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 796.350 0.000 796.630 4.000 ;
+ END
+ END la_data_in[110]
+ PIN la_data_in[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 801.870 0.000 802.150 4.000 ;
+ END
+ END la_data_in[111]
+ PIN la_data_in[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 807.390 0.000 807.670 4.000 ;
+ END
+ END la_data_in[112]
+ PIN la_data_in[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 812.910 0.000 813.190 4.000 ;
+ END
+ END la_data_in[113]
+ PIN la_data_in[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 818.430 0.000 818.710 4.000 ;
+ END
+ END la_data_in[114]
+ PIN la_data_in[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 823.950 0.000 824.230 4.000 ;
+ END
+ END la_data_in[115]
+ PIN la_data_in[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 829.470 0.000 829.750 4.000 ;
+ END
+ END la_data_in[116]
+ PIN la_data_in[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 834.990 0.000 835.270 4.000 ;
+ END
+ END la_data_in[117]
+ PIN la_data_in[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 840.510 0.000 840.790 4.000 ;
+ END
+ END la_data_in[118]
+ PIN la_data_in[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 845.570 0.000 845.850 4.000 ;
+ END
+ END la_data_in[119]
+ PIN la_data_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 254.010 0.000 254.290 4.000 ;
+ END
+ END la_data_in[11]
+ PIN la_data_in[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 851.090 0.000 851.370 4.000 ;
+ END
+ END la_data_in[120]
+ PIN la_data_in[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 856.610 0.000 856.890 4.000 ;
+ END
+ END la_data_in[121]
+ PIN la_data_in[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 862.130 0.000 862.410 4.000 ;
+ END
+ END la_data_in[122]
+ PIN la_data_in[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 867.650 0.000 867.930 4.000 ;
+ END
+ END la_data_in[123]
+ PIN la_data_in[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 873.170 0.000 873.450 4.000 ;
+ END
+ END la_data_in[124]
+ PIN la_data_in[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 878.690 0.000 878.970 4.000 ;
+ END
+ END la_data_in[125]
+ PIN la_data_in[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 884.210 0.000 884.490 4.000 ;
+ END
+ END la_data_in[126]
+ PIN la_data_in[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 889.730 0.000 890.010 4.000 ;
+ END
+ END la_data_in[127]
+ PIN la_data_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 259.530 0.000 259.810 4.000 ;
+ END
+ END la_data_in[12]
+ PIN la_data_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 265.050 0.000 265.330 4.000 ;
+ END
+ END la_data_in[13]
+ PIN la_data_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 270.570 0.000 270.850 4.000 ;
+ END
+ END la_data_in[14]
+ PIN la_data_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 276.090 0.000 276.370 4.000 ;
+ END
+ END la_data_in[15]
+ PIN la_data_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 281.610 0.000 281.890 4.000 ;
+ END
+ END la_data_in[16]
+ PIN la_data_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 287.130 0.000 287.410 4.000 ;
+ END
+ END la_data_in[17]
+ PIN la_data_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.650 0.000 292.930 4.000 ;
+ END
+ END la_data_in[18]
+ PIN la_data_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 298.170 0.000 298.450 4.000 ;
+ END
+ END la_data_in[19]
+ PIN la_data_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 199.270 0.000 199.550 4.000 ;
+ END
+ END la_data_in[1]
+ PIN la_data_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 303.230 0.000 303.510 4.000 ;
+ END
+ END la_data_in[20]
+ PIN la_data_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 308.750 0.000 309.030 4.000 ;
+ END
+ END la_data_in[21]
+ PIN la_data_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 314.270 0.000 314.550 4.000 ;
+ END
+ END la_data_in[22]
+ PIN la_data_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 319.790 0.000 320.070 4.000 ;
+ END
+ END la_data_in[23]
+ PIN la_data_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 325.310 0.000 325.590 4.000 ;
+ END
+ END la_data_in[24]
+ PIN la_data_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 330.830 0.000 331.110 4.000 ;
+ END
+ END la_data_in[25]
+ PIN la_data_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 336.350 0.000 336.630 4.000 ;
+ END
+ END la_data_in[26]
+ PIN la_data_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 341.870 0.000 342.150 4.000 ;
+ END
+ END la_data_in[27]
+ PIN la_data_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 347.390 0.000 347.670 4.000 ;
+ END
+ END la_data_in[28]
+ PIN la_data_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 352.910 0.000 353.190 4.000 ;
+ END
+ END la_data_in[29]
+ PIN la_data_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 204.790 0.000 205.070 4.000 ;
+ END
+ END la_data_in[2]
+ PIN la_data_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 358.430 0.000 358.710 4.000 ;
+ END
+ END la_data_in[30]
+ PIN la_data_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 363.490 0.000 363.770 4.000 ;
+ END
+ END la_data_in[31]
+ PIN la_data_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 369.010 0.000 369.290 4.000 ;
+ END
+ END la_data_in[32]
+ PIN la_data_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.530 0.000 374.810 4.000 ;
+ END
+ END la_data_in[33]
+ PIN la_data_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 380.050 0.000 380.330 4.000 ;
+ END
+ END la_data_in[34]
+ PIN la_data_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 385.570 0.000 385.850 4.000 ;
+ END
+ END la_data_in[35]
+ PIN la_data_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 391.090 0.000 391.370 4.000 ;
+ END
+ END la_data_in[36]
+ PIN la_data_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 396.610 0.000 396.890 4.000 ;
+ END
+ END la_data_in[37]
+ PIN la_data_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 402.130 0.000 402.410 4.000 ;
+ END
+ END la_data_in[38]
+ PIN la_data_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 407.650 0.000 407.930 4.000 ;
+ END
+ END la_data_in[39]
+ PIN la_data_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 210.310 0.000 210.590 4.000 ;
+ END
+ END la_data_in[3]
+ PIN la_data_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 413.170 0.000 413.450 4.000 ;
+ END
+ END la_data_in[40]
+ PIN la_data_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 418.690 0.000 418.970 4.000 ;
+ END
+ END la_data_in[41]
+ PIN la_data_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 423.750 0.000 424.030 4.000 ;
+ END
+ END la_data_in[42]
+ PIN la_data_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 429.270 0.000 429.550 4.000 ;
+ END
+ END la_data_in[43]
+ PIN la_data_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.790 0.000 435.070 4.000 ;
+ END
+ END la_data_in[44]
+ PIN la_data_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 440.310 0.000 440.590 4.000 ;
+ END
+ END la_data_in[45]
+ PIN la_data_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.830 0.000 446.110 4.000 ;
+ END
+ END la_data_in[46]
+ PIN la_data_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 451.350 0.000 451.630 4.000 ;
+ END
+ END la_data_in[47]
+ PIN la_data_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 456.870 0.000 457.150 4.000 ;
+ END
+ END la_data_in[48]
+ PIN la_data_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 462.390 0.000 462.670 4.000 ;
+ END
+ END la_data_in[49]
+ PIN la_data_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 215.830 0.000 216.110 4.000 ;
+ END
+ END la_data_in[4]
+ PIN la_data_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 467.910 0.000 468.190 4.000 ;
+ END
+ END la_data_in[50]
+ PIN la_data_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 473.430 0.000 473.710 4.000 ;
+ END
+ END la_data_in[51]
+ PIN la_data_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 478.950 0.000 479.230 4.000 ;
+ END
+ END la_data_in[52]
+ PIN la_data_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 484.010 0.000 484.290 4.000 ;
+ END
+ END la_data_in[53]
+ PIN la_data_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 489.530 0.000 489.810 4.000 ;
+ END
+ END la_data_in[54]
+ PIN la_data_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 495.050 0.000 495.330 4.000 ;
+ END
+ END la_data_in[55]
+ PIN la_data_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 500.570 0.000 500.850 4.000 ;
+ END
+ END la_data_in[56]
+ PIN la_data_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 506.090 0.000 506.370 4.000 ;
+ END
+ END la_data_in[57]
+ PIN la_data_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 511.610 0.000 511.890 4.000 ;
+ END
+ END la_data_in[58]
+ PIN la_data_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 517.130 0.000 517.410 4.000 ;
+ END
+ END la_data_in[59]
+ PIN la_data_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 221.350 0.000 221.630 4.000 ;
+ END
+ END la_data_in[5]
+ PIN la_data_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 522.650 0.000 522.930 4.000 ;
+ END
+ END la_data_in[60]
+ PIN la_data_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 528.170 0.000 528.450 4.000 ;
+ END
+ END la_data_in[61]
+ PIN la_data_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 533.690 0.000 533.970 4.000 ;
+ END
+ END la_data_in[62]
+ PIN la_data_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 539.210 0.000 539.490 4.000 ;
+ END
+ END la_data_in[63]
+ PIN la_data_in[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 544.270 0.000 544.550 4.000 ;
+ END
+ END la_data_in[64]
+ PIN la_data_in[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 549.790 0.000 550.070 4.000 ;
+ END
+ END la_data_in[65]
+ PIN la_data_in[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 555.310 0.000 555.590 4.000 ;
+ END
+ END la_data_in[66]
+ PIN la_data_in[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 560.830 0.000 561.110 4.000 ;
+ END
+ END la_data_in[67]
+ PIN la_data_in[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 566.350 0.000 566.630 4.000 ;
+ END
+ END la_data_in[68]
+ PIN la_data_in[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 571.870 0.000 572.150 4.000 ;
+ END
+ END la_data_in[69]
+ PIN la_data_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 226.870 0.000 227.150 4.000 ;
+ END
+ END la_data_in[6]
+ PIN la_data_in[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 577.390 0.000 577.670 4.000 ;
+ END
+ END la_data_in[70]
+ PIN la_data_in[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 582.910 0.000 583.190 4.000 ;
+ END
+ END la_data_in[71]
+ PIN la_data_in[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 588.430 0.000 588.710 4.000 ;
+ END
+ END la_data_in[72]
+ PIN la_data_in[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 593.950 0.000 594.230 4.000 ;
+ END
+ END la_data_in[73]
+ PIN la_data_in[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 599.470 0.000 599.750 4.000 ;
+ END
+ END la_data_in[74]
+ PIN la_data_in[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 604.530 0.000 604.810 4.000 ;
+ END
+ END la_data_in[75]
+ PIN la_data_in[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 610.050 0.000 610.330 4.000 ;
+ END
+ END la_data_in[76]
+ PIN la_data_in[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 615.570 0.000 615.850 4.000 ;
+ END
+ END la_data_in[77]
+ PIN la_data_in[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 621.090 0.000 621.370 4.000 ;
+ END
+ END la_data_in[78]
+ PIN la_data_in[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 626.610 0.000 626.890 4.000 ;
+ END
+ END la_data_in[79]
+ PIN la_data_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 232.390 0.000 232.670 4.000 ;
+ END
+ END la_data_in[7]
+ PIN la_data_in[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 632.130 0.000 632.410 4.000 ;
+ END
+ END la_data_in[80]
+ PIN la_data_in[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 637.650 0.000 637.930 4.000 ;
+ END
+ END la_data_in[81]
+ PIN la_data_in[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 643.170 0.000 643.450 4.000 ;
+ END
+ END la_data_in[82]
+ PIN la_data_in[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 648.690 0.000 648.970 4.000 ;
+ END
+ END la_data_in[83]
+ PIN la_data_in[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 654.210 0.000 654.490 4.000 ;
+ END
+ END la_data_in[84]
+ PIN la_data_in[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 659.730 0.000 660.010 4.000 ;
+ END
+ END la_data_in[85]
+ PIN la_data_in[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 664.790 0.000 665.070 4.000 ;
+ END
+ END la_data_in[86]
+ PIN la_data_in[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 670.310 0.000 670.590 4.000 ;
+ END
+ END la_data_in[87]
+ PIN la_data_in[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 675.830 0.000 676.110 4.000 ;
+ END
+ END la_data_in[88]
+ PIN la_data_in[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 681.350 0.000 681.630 4.000 ;
+ END
+ END la_data_in[89]
+ PIN la_data_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 237.910 0.000 238.190 4.000 ;
+ END
+ END la_data_in[8]
+ PIN la_data_in[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 686.870 0.000 687.150 4.000 ;
+ END
+ END la_data_in[90]
+ PIN la_data_in[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 692.390 0.000 692.670 4.000 ;
+ END
+ END la_data_in[91]
+ PIN la_data_in[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 697.910 0.000 698.190 4.000 ;
+ END
+ END la_data_in[92]
+ PIN la_data_in[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 703.430 0.000 703.710 4.000 ;
+ END
+ END la_data_in[93]
+ PIN la_data_in[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 708.950 0.000 709.230 4.000 ;
+ END
+ END la_data_in[94]
+ PIN la_data_in[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 714.470 0.000 714.750 4.000 ;
+ END
+ END la_data_in[95]
+ PIN la_data_in[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 719.990 0.000 720.270 4.000 ;
+ END
+ END la_data_in[96]
+ PIN la_data_in[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 725.050 0.000 725.330 4.000 ;
+ END
+ END la_data_in[97]
+ PIN la_data_in[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 730.570 0.000 730.850 4.000 ;
+ END
+ END la_data_in[98]
+ PIN la_data_in[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 736.090 0.000 736.370 4.000 ;
+ END
+ END la_data_in[99]
+ PIN la_data_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 242.970 0.000 243.250 4.000 ;
+ END
+ END la_data_in[9]
+ PIN la_data_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 195.590 0.000 195.870 4.000 ;
+ END
+ END la_data_out[0]
+ PIN la_data_out[100]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 743.450 0.000 743.730 4.000 ;
+ END
+ END la_data_out[100]
+ PIN la_data_out[101]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 748.970 0.000 749.250 4.000 ;
+ END
+ END la_data_out[101]
+ PIN la_data_out[102]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 754.490 0.000 754.770 4.000 ;
+ END
+ END la_data_out[102]
+ PIN la_data_out[103]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 760.010 0.000 760.290 4.000 ;
+ END
+ END la_data_out[103]
+ PIN la_data_out[104]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 765.530 0.000 765.810 4.000 ;
+ END
+ END la_data_out[104]
+ PIN la_data_out[105]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 771.050 0.000 771.330 4.000 ;
+ END
+ END la_data_out[105]
+ PIN la_data_out[106]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 776.570 0.000 776.850 4.000 ;
+ END
+ END la_data_out[106]
+ PIN la_data_out[107]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 781.630 0.000 781.910 4.000 ;
+ END
+ END la_data_out[107]
+ PIN la_data_out[108]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 787.150 0.000 787.430 4.000 ;
+ END
+ END la_data_out[108]
+ PIN la_data_out[109]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 792.670 0.000 792.950 4.000 ;
+ END
+ END la_data_out[109]
+ PIN la_data_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 250.330 0.000 250.610 4.000 ;
+ END
+ END la_data_out[10]
+ PIN la_data_out[110]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 798.190 0.000 798.470 4.000 ;
+ END
+ END la_data_out[110]
+ PIN la_data_out[111]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 803.710 0.000 803.990 4.000 ;
+ END
+ END la_data_out[111]
+ PIN la_data_out[112]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 809.230 0.000 809.510 4.000 ;
+ END
+ END la_data_out[112]
+ PIN la_data_out[113]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 814.750 0.000 815.030 4.000 ;
+ END
+ END la_data_out[113]
+ PIN la_data_out[114]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 820.270 0.000 820.550 4.000 ;
+ END
+ END la_data_out[114]
+ PIN la_data_out[115]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 825.790 0.000 826.070 4.000 ;
+ END
+ END la_data_out[115]
+ PIN la_data_out[116]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 831.310 0.000 831.590 4.000 ;
+ END
+ END la_data_out[116]
+ PIN la_data_out[117]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 836.830 0.000 837.110 4.000 ;
+ END
+ END la_data_out[117]
+ PIN la_data_out[118]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 841.890 0.000 842.170 4.000 ;
+ END
+ END la_data_out[118]
+ PIN la_data_out[119]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 847.410 0.000 847.690 4.000 ;
+ END
+ END la_data_out[119]
+ PIN la_data_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 255.850 0.000 256.130 4.000 ;
+ END
+ END la_data_out[11]
+ PIN la_data_out[120]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 852.930 0.000 853.210 4.000 ;
+ END
+ END la_data_out[120]
+ PIN la_data_out[121]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 858.450 0.000 858.730 4.000 ;
+ END
+ END la_data_out[121]
+ PIN la_data_out[122]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 863.970 0.000 864.250 4.000 ;
+ END
+ END la_data_out[122]
+ PIN la_data_out[123]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 869.490 0.000 869.770 4.000 ;
+ END
+ END la_data_out[123]
+ PIN la_data_out[124]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 875.010 0.000 875.290 4.000 ;
+ END
+ END la_data_out[124]
+ PIN la_data_out[125]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 880.530 0.000 880.810 4.000 ;
+ END
+ END la_data_out[125]
+ PIN la_data_out[126]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 886.050 0.000 886.330 4.000 ;
+ END
+ END la_data_out[126]
+ PIN la_data_out[127]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 891.570 0.000 891.850 4.000 ;
+ END
+ END la_data_out[127]
+ PIN la_data_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 261.370 0.000 261.650 4.000 ;
+ END
+ END la_data_out[12]
+ PIN la_data_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 266.890 0.000 267.170 4.000 ;
+ END
+ END la_data_out[13]
+ PIN la_data_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 272.410 0.000 272.690 4.000 ;
+ END
+ END la_data_out[14]
+ PIN la_data_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 277.930 0.000 278.210 4.000 ;
+ END
+ END la_data_out[15]
+ PIN la_data_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 283.450 0.000 283.730 4.000 ;
+ END
+ END la_data_out[16]
+ PIN la_data_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 288.970 0.000 289.250 4.000 ;
+ END
+ END la_data_out[17]
+ PIN la_data_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 294.490 0.000 294.770 4.000 ;
+ END
+ END la_data_out[18]
+ PIN la_data_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 300.010 0.000 300.290 4.000 ;
+ END
+ END la_data_out[19]
+ PIN la_data_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 201.110 0.000 201.390 4.000 ;
+ END
+ END la_data_out[1]
+ PIN la_data_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 305.070 0.000 305.350 4.000 ;
+ END
+ END la_data_out[20]
+ PIN la_data_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 310.590 0.000 310.870 4.000 ;
+ END
+ END la_data_out[21]
+ PIN la_data_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 316.110 0.000 316.390 4.000 ;
+ END
+ END la_data_out[22]
+ PIN la_data_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 321.630 0.000 321.910 4.000 ;
+ END
+ END la_data_out[23]
+ PIN la_data_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.150 0.000 327.430 4.000 ;
+ END
+ END la_data_out[24]
+ PIN la_data_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 332.670 0.000 332.950 4.000 ;
+ END
+ END la_data_out[25]
+ PIN la_data_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 338.190 0.000 338.470 4.000 ;
+ END
+ END la_data_out[26]
+ PIN la_data_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 343.710 0.000 343.990 4.000 ;
+ END
+ END la_data_out[27]
+ PIN la_data_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 349.230 0.000 349.510 4.000 ;
+ END
+ END la_data_out[28]
+ PIN la_data_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 354.750 0.000 355.030 4.000 ;
+ END
+ END la_data_out[29]
+ PIN la_data_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 206.630 0.000 206.910 4.000 ;
+ END
+ END la_data_out[2]
+ PIN la_data_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 360.270 0.000 360.550 4.000 ;
+ END
+ END la_data_out[30]
+ PIN la_data_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 365.330 0.000 365.610 4.000 ;
+ END
+ END la_data_out[31]
+ PIN la_data_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 370.850 0.000 371.130 4.000 ;
+ END
+ END la_data_out[32]
+ PIN la_data_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 376.370 0.000 376.650 4.000 ;
+ END
+ END la_data_out[33]
+ PIN la_data_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 381.890 0.000 382.170 4.000 ;
+ END
+ END la_data_out[34]
+ PIN la_data_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 387.410 0.000 387.690 4.000 ;
+ END
+ END la_data_out[35]
+ PIN la_data_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 392.930 0.000 393.210 4.000 ;
+ END
+ END la_data_out[36]
+ PIN la_data_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 398.450 0.000 398.730 4.000 ;
+ END
+ END la_data_out[37]
+ PIN la_data_out[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 403.970 0.000 404.250 4.000 ;
+ END
+ END la_data_out[38]
+ PIN la_data_out[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 409.490 0.000 409.770 4.000 ;
+ END
+ END la_data_out[39]
+ PIN la_data_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 212.150 0.000 212.430 4.000 ;
+ END
+ END la_data_out[3]
+ PIN la_data_out[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 415.010 0.000 415.290 4.000 ;
+ END
+ END la_data_out[40]
+ PIN la_data_out[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 420.530 0.000 420.810 4.000 ;
+ END
+ END la_data_out[41]
+ PIN la_data_out[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 425.590 0.000 425.870 4.000 ;
+ END
+ END la_data_out[42]
+ PIN la_data_out[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 431.110 0.000 431.390 4.000 ;
+ END
+ END la_data_out[43]
+ PIN la_data_out[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 436.630 0.000 436.910 4.000 ;
+ END
+ END la_data_out[44]
+ PIN la_data_out[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 442.150 0.000 442.430 4.000 ;
+ END
+ END la_data_out[45]
+ PIN la_data_out[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 447.670 0.000 447.950 4.000 ;
+ END
+ END la_data_out[46]
+ PIN la_data_out[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.190 0.000 453.470 4.000 ;
+ END
+ END la_data_out[47]
+ PIN la_data_out[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 458.710 0.000 458.990 4.000 ;
+ END
+ END la_data_out[48]
+ PIN la_data_out[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 464.230 0.000 464.510 4.000 ;
+ END
+ END la_data_out[49]
+ PIN la_data_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 217.670 0.000 217.950 4.000 ;
+ END
+ END la_data_out[4]
+ PIN la_data_out[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.750 0.000 470.030 4.000 ;
+ END
+ END la_data_out[50]
+ PIN la_data_out[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 475.270 0.000 475.550 4.000 ;
+ END
+ END la_data_out[51]
+ PIN la_data_out[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 480.330 0.000 480.610 4.000 ;
+ END
+ END la_data_out[52]
+ PIN la_data_out[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.850 0.000 486.130 4.000 ;
+ END
+ END la_data_out[53]
+ PIN la_data_out[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 491.370 0.000 491.650 4.000 ;
+ END
+ END la_data_out[54]
+ PIN la_data_out[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 496.890 0.000 497.170 4.000 ;
+ END
+ END la_data_out[55]
+ PIN la_data_out[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 502.410 0.000 502.690 4.000 ;
+ END
+ END la_data_out[56]
+ PIN la_data_out[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 507.930 0.000 508.210 4.000 ;
+ END
+ END la_data_out[57]
+ PIN la_data_out[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 513.450 0.000 513.730 4.000 ;
+ END
+ END la_data_out[58]
+ PIN la_data_out[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 518.970 0.000 519.250 4.000 ;
+ END
+ END la_data_out[59]
+ PIN la_data_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 223.190 0.000 223.470 4.000 ;
+ END
+ END la_data_out[5]
+ PIN la_data_out[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 524.490 0.000 524.770 4.000 ;
+ END
+ END la_data_out[60]
+ PIN la_data_out[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 530.010 0.000 530.290 4.000 ;
+ END
+ END la_data_out[61]
+ PIN la_data_out[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 535.530 0.000 535.810 4.000 ;
+ END
+ END la_data_out[62]
+ PIN la_data_out[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 540.590 0.000 540.870 4.000 ;
+ END
+ END la_data_out[63]
+ PIN la_data_out[64]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 546.110 0.000 546.390 4.000 ;
+ END
+ END la_data_out[64]
+ PIN la_data_out[65]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 551.630 0.000 551.910 4.000 ;
+ END
+ END la_data_out[65]
+ PIN la_data_out[66]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 557.150 0.000 557.430 4.000 ;
+ END
+ END la_data_out[66]
+ PIN la_data_out[67]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 562.670 0.000 562.950 4.000 ;
+ END
+ END la_data_out[67]
+ PIN la_data_out[68]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 568.190 0.000 568.470 4.000 ;
+ END
+ END la_data_out[68]
+ PIN la_data_out[69]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 573.710 0.000 573.990 4.000 ;
+ END
+ END la_data_out[69]
+ PIN la_data_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 228.710 0.000 228.990 4.000 ;
+ END
+ END la_data_out[6]
+ PIN la_data_out[70]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 579.230 0.000 579.510 4.000 ;
+ END
+ END la_data_out[70]
+ PIN la_data_out[71]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 584.750 0.000 585.030 4.000 ;
+ END
+ END la_data_out[71]
+ PIN la_data_out[72]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 590.270 0.000 590.550 4.000 ;
+ END
+ END la_data_out[72]
+ PIN la_data_out[73]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 595.790 0.000 596.070 4.000 ;
+ END
+ END la_data_out[73]
+ PIN la_data_out[74]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 600.850 0.000 601.130 4.000 ;
+ END
+ END la_data_out[74]
+ PIN la_data_out[75]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 606.370 0.000 606.650 4.000 ;
+ END
+ END la_data_out[75]
+ PIN la_data_out[76]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 611.890 0.000 612.170 4.000 ;
+ END
+ END la_data_out[76]
+ PIN la_data_out[77]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 617.410 0.000 617.690 4.000 ;
+ END
+ END la_data_out[77]
+ PIN la_data_out[78]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 622.930 0.000 623.210 4.000 ;
+ END
+ END la_data_out[78]
+ PIN la_data_out[79]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 628.450 0.000 628.730 4.000 ;
+ END
+ END la_data_out[79]
+ PIN la_data_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 234.230 0.000 234.510 4.000 ;
+ END
+ END la_data_out[7]
+ PIN la_data_out[80]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 633.970 0.000 634.250 4.000 ;
+ END
+ END la_data_out[80]
+ PIN la_data_out[81]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 639.490 0.000 639.770 4.000 ;
+ END
+ END la_data_out[81]
+ PIN la_data_out[82]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 645.010 0.000 645.290 4.000 ;
+ END
+ END la_data_out[82]
+ PIN la_data_out[83]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 650.530 0.000 650.810 4.000 ;
+ END
+ END la_data_out[83]
+ PIN la_data_out[84]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 656.050 0.000 656.330 4.000 ;
+ END
+ END la_data_out[84]
+ PIN la_data_out[85]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 661.110 0.000 661.390 4.000 ;
+ END
+ END la_data_out[85]
+ PIN la_data_out[86]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 666.630 0.000 666.910 4.000 ;
+ END
+ END la_data_out[86]
+ PIN la_data_out[87]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 672.150 0.000 672.430 4.000 ;
+ END
+ END la_data_out[87]
+ PIN la_data_out[88]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 677.670 0.000 677.950 4.000 ;
+ END
+ END la_data_out[88]
+ PIN la_data_out[89]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 683.190 0.000 683.470 4.000 ;
+ END
+ END la_data_out[89]
+ PIN la_data_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 239.750 0.000 240.030 4.000 ;
+ END
+ END la_data_out[8]
+ PIN la_data_out[90]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 688.710 0.000 688.990 4.000 ;
+ END
+ END la_data_out[90]
+ PIN la_data_out[91]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 694.230 0.000 694.510 4.000 ;
+ END
+ END la_data_out[91]
+ PIN la_data_out[92]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 699.750 0.000 700.030 4.000 ;
+ END
+ END la_data_out[92]
+ PIN la_data_out[93]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 705.270 0.000 705.550 4.000 ;
+ END
+ END la_data_out[93]
+ PIN la_data_out[94]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 710.790 0.000 711.070 4.000 ;
+ END
+ END la_data_out[94]
+ PIN la_data_out[95]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 716.310 0.000 716.590 4.000 ;
+ END
+ END la_data_out[95]
+ PIN la_data_out[96]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 721.370 0.000 721.650 4.000 ;
+ END
+ END la_data_out[96]
+ PIN la_data_out[97]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 726.890 0.000 727.170 4.000 ;
+ END
+ END la_data_out[97]
+ PIN la_data_out[98]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 732.410 0.000 732.690 4.000 ;
+ END
+ END la_data_out[98]
+ PIN la_data_out[99]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 737.930 0.000 738.210 4.000 ;
+ END
+ END la_data_out[99]
+ PIN la_data_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 244.810 0.000 245.090 4.000 ;
+ END
+ END la_data_out[9]
+ PIN la_oenb[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 197.430 0.000 197.710 4.000 ;
+ END
+ END la_oenb[0]
+ PIN la_oenb[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 745.290 0.000 745.570 4.000 ;
+ END
+ END la_oenb[100]
+ PIN la_oenb[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 750.810 0.000 751.090 4.000 ;
+ END
+ END la_oenb[101]
+ PIN la_oenb[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 756.330 0.000 756.610 4.000 ;
+ END
+ END la_oenb[102]
+ PIN la_oenb[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 761.850 0.000 762.130 4.000 ;
+ END
+ END la_oenb[103]
+ PIN la_oenb[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 767.370 0.000 767.650 4.000 ;
+ END
+ END la_oenb[104]
+ PIN la_oenb[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 772.890 0.000 773.170 4.000 ;
+ END
+ END la_oenb[105]
+ PIN la_oenb[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 778.410 0.000 778.690 4.000 ;
+ END
+ END la_oenb[106]
+ PIN la_oenb[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 783.470 0.000 783.750 4.000 ;
+ END
+ END la_oenb[107]
+ PIN la_oenb[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 788.990 0.000 789.270 4.000 ;
+ END
+ END la_oenb[108]
+ PIN la_oenb[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 794.510 0.000 794.790 4.000 ;
+ END
+ END la_oenb[109]
+ PIN la_oenb[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 252.170 0.000 252.450 4.000 ;
+ END
+ END la_oenb[10]
+ PIN la_oenb[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 800.030 0.000 800.310 4.000 ;
+ END
+ END la_oenb[110]
+ PIN la_oenb[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 805.550 0.000 805.830 4.000 ;
+ END
+ END la_oenb[111]
+ PIN la_oenb[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 811.070 0.000 811.350 4.000 ;
+ END
+ END la_oenb[112]
+ PIN la_oenb[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 816.590 0.000 816.870 4.000 ;
+ END
+ END la_oenb[113]
+ PIN la_oenb[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 822.110 0.000 822.390 4.000 ;
+ END
+ END la_oenb[114]
+ PIN la_oenb[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 827.630 0.000 827.910 4.000 ;
+ END
+ END la_oenb[115]
+ PIN la_oenb[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 833.150 0.000 833.430 4.000 ;
+ END
+ END la_oenb[116]
+ PIN la_oenb[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 838.670 0.000 838.950 4.000 ;
+ END
+ END la_oenb[117]
+ PIN la_oenb[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 843.730 0.000 844.010 4.000 ;
+ END
+ END la_oenb[118]
+ PIN la_oenb[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 849.250 0.000 849.530 4.000 ;
+ END
+ END la_oenb[119]
+ PIN la_oenb[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 257.690 0.000 257.970 4.000 ;
+ END
+ END la_oenb[11]
+ PIN la_oenb[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 854.770 0.000 855.050 4.000 ;
+ END
+ END la_oenb[120]
+ PIN la_oenb[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 860.290 0.000 860.570 4.000 ;
+ END
+ END la_oenb[121]
+ PIN la_oenb[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 865.810 0.000 866.090 4.000 ;
+ END
+ END la_oenb[122]
+ PIN la_oenb[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 871.330 0.000 871.610 4.000 ;
+ END
+ END la_oenb[123]
+ PIN la_oenb[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 876.850 0.000 877.130 4.000 ;
+ END
+ END la_oenb[124]
+ PIN la_oenb[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 882.370 0.000 882.650 4.000 ;
+ END
+ END la_oenb[125]
+ PIN la_oenb[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 887.890 0.000 888.170 4.000 ;
+ END
+ END la_oenb[126]
+ PIN la_oenb[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 893.410 0.000 893.690 4.000 ;
+ END
+ END la_oenb[127]
+ PIN la_oenb[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 263.210 0.000 263.490 4.000 ;
+ END
+ END la_oenb[12]
+ PIN la_oenb[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 268.730 0.000 269.010 4.000 ;
+ END
+ END la_oenb[13]
+ PIN la_oenb[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 274.250 0.000 274.530 4.000 ;
+ END
+ END la_oenb[14]
+ PIN la_oenb[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 279.770 0.000 280.050 4.000 ;
+ END
+ END la_oenb[15]
+ PIN la_oenb[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 285.290 0.000 285.570 4.000 ;
+ END
+ END la_oenb[16]
+ PIN la_oenb[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 290.810 0.000 291.090 4.000 ;
+ END
+ END la_oenb[17]
+ PIN la_oenb[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 296.330 0.000 296.610 4.000 ;
+ END
+ END la_oenb[18]
+ PIN la_oenb[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 301.390 0.000 301.670 4.000 ;
+ END
+ END la_oenb[19]
+ PIN la_oenb[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.950 0.000 203.230 4.000 ;
+ END
+ END la_oenb[1]
+ PIN la_oenb[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 306.910 0.000 307.190 4.000 ;
+ END
+ END la_oenb[20]
+ PIN la_oenb[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 312.430 0.000 312.710 4.000 ;
+ END
+ END la_oenb[21]
+ PIN la_oenb[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 317.950 0.000 318.230 4.000 ;
+ END
+ END la_oenb[22]
+ PIN la_oenb[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 323.470 0.000 323.750 4.000 ;
+ END
+ END la_oenb[23]
+ PIN la_oenb[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 328.990 0.000 329.270 4.000 ;
+ END
+ END la_oenb[24]
+ PIN la_oenb[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 334.510 0.000 334.790 4.000 ;
+ END
+ END la_oenb[25]
+ PIN la_oenb[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 340.030 0.000 340.310 4.000 ;
+ END
+ END la_oenb[26]
+ PIN la_oenb[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.550 0.000 345.830 4.000 ;
+ END
+ END la_oenb[27]
+ PIN la_oenb[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.070 0.000 351.350 4.000 ;
+ END
+ END la_oenb[28]
+ PIN la_oenb[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 356.590 0.000 356.870 4.000 ;
+ END
+ END la_oenb[29]
+ PIN la_oenb[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 208.470 0.000 208.750 4.000 ;
+ END
+ END la_oenb[2]
+ PIN la_oenb[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 361.650 0.000 361.930 4.000 ;
+ END
+ END la_oenb[30]
+ PIN la_oenb[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 367.170 0.000 367.450 4.000 ;
+ END
+ END la_oenb[31]
+ PIN la_oenb[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 372.690 0.000 372.970 4.000 ;
+ END
+ END la_oenb[32]
+ PIN la_oenb[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 378.210 0.000 378.490 4.000 ;
+ END
+ END la_oenb[33]
+ PIN la_oenb[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 383.730 0.000 384.010 4.000 ;
+ END
+ END la_oenb[34]
+ PIN la_oenb[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 389.250 0.000 389.530 4.000 ;
+ END
+ END la_oenb[35]
+ PIN la_oenb[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 394.770 0.000 395.050 4.000 ;
+ END
+ END la_oenb[36]
+ PIN la_oenb[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 400.290 0.000 400.570 4.000 ;
+ END
+ END la_oenb[37]
+ PIN la_oenb[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 405.810 0.000 406.090 4.000 ;
+ END
+ END la_oenb[38]
+ PIN la_oenb[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 411.330 0.000 411.610 4.000 ;
+ END
+ END la_oenb[39]
+ PIN la_oenb[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 213.990 0.000 214.270 4.000 ;
+ END
+ END la_oenb[3]
+ PIN la_oenb[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.850 0.000 417.130 4.000 ;
+ END
+ END la_oenb[40]
+ PIN la_oenb[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 421.910 0.000 422.190 4.000 ;
+ END
+ END la_oenb[41]
+ PIN la_oenb[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 427.430 0.000 427.710 4.000 ;
+ END
+ END la_oenb[42]
+ PIN la_oenb[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 432.950 0.000 433.230 4.000 ;
+ END
+ END la_oenb[43]
+ PIN la_oenb[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 438.470 0.000 438.750 4.000 ;
+ END
+ END la_oenb[44]
+ PIN la_oenb[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 443.990 0.000 444.270 4.000 ;
+ END
+ END la_oenb[45]
+ PIN la_oenb[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 449.510 0.000 449.790 4.000 ;
+ END
+ END la_oenb[46]
+ PIN la_oenb[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 455.030 0.000 455.310 4.000 ;
+ END
+ END la_oenb[47]
+ PIN la_oenb[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 460.550 0.000 460.830 4.000 ;
+ END
+ END la_oenb[48]
+ PIN la_oenb[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 466.070 0.000 466.350 4.000 ;
+ END
+ END la_oenb[49]
+ PIN la_oenb[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 219.510 0.000 219.790 4.000 ;
+ END
+ END la_oenb[4]
+ PIN la_oenb[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 471.590 0.000 471.870 4.000 ;
+ END
+ END la_oenb[50]
+ PIN la_oenb[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 477.110 0.000 477.390 4.000 ;
+ END
+ END la_oenb[51]
+ PIN la_oenb[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 482.170 0.000 482.450 4.000 ;
+ END
+ END la_oenb[52]
+ PIN la_oenb[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 487.690 0.000 487.970 4.000 ;
+ END
+ END la_oenb[53]
+ PIN la_oenb[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 493.210 0.000 493.490 4.000 ;
+ END
+ END la_oenb[54]
+ PIN la_oenb[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 498.730 0.000 499.010 4.000 ;
+ END
+ END la_oenb[55]
+ PIN la_oenb[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 504.250 0.000 504.530 4.000 ;
+ END
+ END la_oenb[56]
+ PIN la_oenb[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 509.770 0.000 510.050 4.000 ;
+ END
+ END la_oenb[57]
+ PIN la_oenb[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 515.290 0.000 515.570 4.000 ;
+ END
+ END la_oenb[58]
+ PIN la_oenb[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 520.810 0.000 521.090 4.000 ;
+ END
+ END la_oenb[59]
+ PIN la_oenb[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 225.030 0.000 225.310 4.000 ;
+ END
+ END la_oenb[5]
+ PIN la_oenb[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 526.330 0.000 526.610 4.000 ;
+ END
+ END la_oenb[60]
+ PIN la_oenb[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 531.850 0.000 532.130 4.000 ;
+ END
+ END la_oenb[61]
+ PIN la_oenb[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 537.370 0.000 537.650 4.000 ;
+ END
+ END la_oenb[62]
+ PIN la_oenb[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 542.430 0.000 542.710 4.000 ;
+ END
+ END la_oenb[63]
+ PIN la_oenb[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 547.950 0.000 548.230 4.000 ;
+ END
+ END la_oenb[64]
+ PIN la_oenb[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 553.470 0.000 553.750 4.000 ;
+ END
+ END la_oenb[65]
+ PIN la_oenb[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 558.990 0.000 559.270 4.000 ;
+ END
+ END la_oenb[66]
+ PIN la_oenb[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 564.510 0.000 564.790 4.000 ;
+ END
+ END la_oenb[67]
+ PIN la_oenb[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 570.030 0.000 570.310 4.000 ;
+ END
+ END la_oenb[68]
+ PIN la_oenb[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 575.550 0.000 575.830 4.000 ;
+ END
+ END la_oenb[69]
+ PIN la_oenb[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 230.550 0.000 230.830 4.000 ;
+ END
+ END la_oenb[6]
+ PIN la_oenb[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 581.070 0.000 581.350 4.000 ;
+ END
+ END la_oenb[70]
+ PIN la_oenb[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 586.590 0.000 586.870 4.000 ;
+ END
+ END la_oenb[71]
+ PIN la_oenb[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 592.110 0.000 592.390 4.000 ;
+ END
+ END la_oenb[72]
+ PIN la_oenb[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 597.630 0.000 597.910 4.000 ;
+ END
+ END la_oenb[73]
+ PIN la_oenb[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 602.690 0.000 602.970 4.000 ;
+ END
+ END la_oenb[74]
+ PIN la_oenb[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 608.210 0.000 608.490 4.000 ;
+ END
+ END la_oenb[75]
+ PIN la_oenb[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 613.730 0.000 614.010 4.000 ;
+ END
+ END la_oenb[76]
+ PIN la_oenb[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 619.250 0.000 619.530 4.000 ;
+ END
+ END la_oenb[77]
+ PIN la_oenb[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 624.770 0.000 625.050 4.000 ;
+ END
+ END la_oenb[78]
+ PIN la_oenb[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 630.290 0.000 630.570 4.000 ;
+ END
+ END la_oenb[79]
+ PIN la_oenb[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 236.070 0.000 236.350 4.000 ;
+ END
+ END la_oenb[7]
+ PIN la_oenb[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 635.810 0.000 636.090 4.000 ;
+ END
+ END la_oenb[80]
+ PIN la_oenb[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 641.330 0.000 641.610 4.000 ;
+ END
+ END la_oenb[81]
+ PIN la_oenb[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 646.850 0.000 647.130 4.000 ;
+ END
+ END la_oenb[82]
+ PIN la_oenb[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 652.370 0.000 652.650 4.000 ;
+ END
+ END la_oenb[83]
+ PIN la_oenb[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 657.890 0.000 658.170 4.000 ;
+ END
+ END la_oenb[84]
+ PIN la_oenb[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 662.950 0.000 663.230 4.000 ;
+ END
+ END la_oenb[85]
+ PIN la_oenb[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 668.470 0.000 668.750 4.000 ;
+ END
+ END la_oenb[86]
+ PIN la_oenb[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 673.990 0.000 674.270 4.000 ;
+ END
+ END la_oenb[87]
+ PIN la_oenb[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 679.510 0.000 679.790 4.000 ;
+ END
+ END la_oenb[88]
+ PIN la_oenb[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 685.030 0.000 685.310 4.000 ;
+ END
+ END la_oenb[89]
+ PIN la_oenb[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 241.130 0.000 241.410 4.000 ;
+ END
+ END la_oenb[8]
+ PIN la_oenb[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 690.550 0.000 690.830 4.000 ;
+ END
+ END la_oenb[90]
+ PIN la_oenb[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 696.070 0.000 696.350 4.000 ;
+ END
+ END la_oenb[91]
+ PIN la_oenb[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 701.590 0.000 701.870 4.000 ;
+ END
+ END la_oenb[92]
+ PIN la_oenb[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 707.110 0.000 707.390 4.000 ;
+ END
+ END la_oenb[93]
+ PIN la_oenb[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 712.630 0.000 712.910 4.000 ;
+ END
+ END la_oenb[94]
+ PIN la_oenb[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 718.150 0.000 718.430 4.000 ;
+ END
+ END la_oenb[95]
+ PIN la_oenb[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 723.210 0.000 723.490 4.000 ;
+ END
+ END la_oenb[96]
+ PIN la_oenb[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 728.730 0.000 729.010 4.000 ;
+ END
+ END la_oenb[97]
+ PIN la_oenb[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 734.250 0.000 734.530 4.000 ;
+ END
+ END la_oenb[98]
+ PIN la_oenb[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 739.770 0.000 740.050 4.000 ;
+ END
+ END la_oenb[99]
+ PIN la_oenb[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 246.650 0.000 246.930 4.000 ;
+ END
+ END la_oenb[9]
+ PIN vccd1
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 21.040 10.640 22.640 587.760 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 97.840 10.640 99.440 587.760 ;
+ END
+ END vssd1
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 0.550 0.000 0.830 4.000 ;
+ END
+ END wb_clk_i
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1.930 0.000 2.210 4.000 ;
+ END
+ END wb_rst_i
+ PIN wbs_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 3.770 0.000 4.050 4.000 ;
+ END
+ END wbs_ack_o
+ PIN wbs_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 11.130 0.000 11.410 4.000 ;
+ END
+ END wbs_adr_i[0]
+ PIN wbs_adr_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 73.230 0.000 73.510 4.000 ;
+ END
+ END wbs_adr_i[10]
+ PIN wbs_adr_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 78.750 0.000 79.030 4.000 ;
+ END
+ END wbs_adr_i[11]
+ PIN wbs_adr_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 84.270 0.000 84.550 4.000 ;
+ END
+ END wbs_adr_i[12]
+ PIN wbs_adr_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 89.790 0.000 90.070 4.000 ;
+ END
+ END wbs_adr_i[13]
+ PIN wbs_adr_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 95.310 0.000 95.590 4.000 ;
+ END
+ END wbs_adr_i[14]
+ PIN wbs_adr_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 100.830 0.000 101.110 4.000 ;
+ END
+ END wbs_adr_i[15]
+ PIN wbs_adr_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 106.350 0.000 106.630 4.000 ;
+ END
+ END wbs_adr_i[16]
+ PIN wbs_adr_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 111.870 0.000 112.150 4.000 ;
+ END
+ END wbs_adr_i[17]
+ PIN wbs_adr_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 117.390 0.000 117.670 4.000 ;
+ END
+ END wbs_adr_i[18]
+ PIN wbs_adr_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 122.450 0.000 122.730 4.000 ;
+ END
+ END wbs_adr_i[19]
+ PIN wbs_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 18.490 0.000 18.770 4.000 ;
+ END
+ END wbs_adr_i[1]
+ PIN wbs_adr_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 127.970 0.000 128.250 4.000 ;
+ END
+ END wbs_adr_i[20]
+ PIN wbs_adr_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 133.490 0.000 133.770 4.000 ;
+ END
+ END wbs_adr_i[21]
+ PIN wbs_adr_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 139.010 0.000 139.290 4.000 ;
+ END
+ END wbs_adr_i[22]
+ PIN wbs_adr_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 144.530 0.000 144.810 4.000 ;
+ END
+ END wbs_adr_i[23]
+ PIN wbs_adr_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 150.050 0.000 150.330 4.000 ;
+ END
+ END wbs_adr_i[24]
+ PIN wbs_adr_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 155.570 0.000 155.850 4.000 ;
+ END
+ END wbs_adr_i[25]
+ PIN wbs_adr_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.090 0.000 161.370 4.000 ;
+ END
+ END wbs_adr_i[26]
+ PIN wbs_adr_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 166.610 0.000 166.890 4.000 ;
+ END
+ END wbs_adr_i[27]
+ PIN wbs_adr_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 172.130 0.000 172.410 4.000 ;
+ END
+ END wbs_adr_i[28]
+ PIN wbs_adr_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 177.650 0.000 177.930 4.000 ;
+ END
+ END wbs_adr_i[29]
+ PIN wbs_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 25.850 0.000 26.130 4.000 ;
+ END
+ END wbs_adr_i[2]
+ PIN wbs_adr_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 182.710 0.000 182.990 4.000 ;
+ END
+ END wbs_adr_i[30]
+ PIN wbs_adr_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 188.230 0.000 188.510 4.000 ;
+ END
+ END wbs_adr_i[31]
+ PIN wbs_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 33.210 0.000 33.490 4.000 ;
+ END
+ END wbs_adr_i[3]
+ PIN wbs_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 40.570 0.000 40.850 4.000 ;
+ END
+ END wbs_adr_i[4]
+ PIN wbs_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 46.090 0.000 46.370 4.000 ;
+ END
+ END wbs_adr_i[5]
+ PIN wbs_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 51.610 0.000 51.890 4.000 ;
+ END
+ END wbs_adr_i[6]
+ PIN wbs_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 57.130 0.000 57.410 4.000 ;
+ END
+ END wbs_adr_i[7]
+ PIN wbs_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 62.190 0.000 62.470 4.000 ;
+ END
+ END wbs_adr_i[8]
+ PIN wbs_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 67.710 0.000 67.990 4.000 ;
+ END
+ END wbs_adr_i[9]
+ PIN wbs_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 5.610 0.000 5.890 4.000 ;
+ END
+ END wbs_cyc_i
+ PIN wbs_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 12.970 0.000 13.250 4.000 ;
+ END
+ END wbs_dat_i[0]
+ PIN wbs_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 75.070 0.000 75.350 4.000 ;
+ END
+ END wbs_dat_i[10]
+ PIN wbs_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 80.590 0.000 80.870 4.000 ;
+ END
+ END wbs_dat_i[11]
+ PIN wbs_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 86.110 0.000 86.390 4.000 ;
+ END
+ END wbs_dat_i[12]
+ PIN wbs_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 91.630 0.000 91.910 4.000 ;
+ END
+ END wbs_dat_i[13]
+ PIN wbs_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 97.150 0.000 97.430 4.000 ;
+ END
+ END wbs_dat_i[14]
+ PIN wbs_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 102.670 0.000 102.950 4.000 ;
+ END
+ END wbs_dat_i[15]
+ PIN wbs_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 108.190 0.000 108.470 4.000 ;
+ END
+ END wbs_dat_i[16]
+ PIN wbs_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 113.710 0.000 113.990 4.000 ;
+ END
+ END wbs_dat_i[17]
+ PIN wbs_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 119.230 0.000 119.510 4.000 ;
+ END
+ END wbs_dat_i[18]
+ PIN wbs_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 124.290 0.000 124.570 4.000 ;
+ END
+ END wbs_dat_i[19]
+ PIN wbs_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 20.330 0.000 20.610 4.000 ;
+ END
+ END wbs_dat_i[1]
+ PIN wbs_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 129.810 0.000 130.090 4.000 ;
+ END
+ END wbs_dat_i[20]
+ PIN wbs_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 135.330 0.000 135.610 4.000 ;
+ END
+ END wbs_dat_i[21]
+ PIN wbs_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 140.850 0.000 141.130 4.000 ;
+ END
+ END wbs_dat_i[22]
+ PIN wbs_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 146.370 0.000 146.650 4.000 ;
+ END
+ END wbs_dat_i[23]
+ PIN wbs_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 151.890 0.000 152.170 4.000 ;
+ END
+ END wbs_dat_i[24]
+ PIN wbs_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 157.410 0.000 157.690 4.000 ;
+ END
+ END wbs_dat_i[25]
+ PIN wbs_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 162.930 0.000 163.210 4.000 ;
+ END
+ END wbs_dat_i[26]
+ PIN wbs_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 168.450 0.000 168.730 4.000 ;
+ END
+ END wbs_dat_i[27]
+ PIN wbs_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 173.970 0.000 174.250 4.000 ;
+ END
+ END wbs_dat_i[28]
+ PIN wbs_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 179.490 0.000 179.770 4.000 ;
+ END
+ END wbs_dat_i[29]
+ PIN wbs_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.690 0.000 27.970 4.000 ;
+ END
+ END wbs_dat_i[2]
+ PIN wbs_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 184.550 0.000 184.830 4.000 ;
+ END
+ END wbs_dat_i[30]
+ PIN wbs_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 190.070 0.000 190.350 4.000 ;
+ END
+ END wbs_dat_i[31]
+ PIN wbs_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 35.050 0.000 35.330 4.000 ;
+ END
+ END wbs_dat_i[3]
+ PIN wbs_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 42.410 0.000 42.690 4.000 ;
+ END
+ END wbs_dat_i[4]
+ PIN wbs_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 47.930 0.000 48.210 4.000 ;
+ END
+ END wbs_dat_i[5]
+ PIN wbs_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 53.450 0.000 53.730 4.000 ;
+ END
+ END wbs_dat_i[6]
+ PIN wbs_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 58.970 0.000 59.250 4.000 ;
+ END
+ END wbs_dat_i[7]
+ PIN wbs_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 64.030 0.000 64.310 4.000 ;
+ END
+ END wbs_dat_i[8]
+ PIN wbs_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 69.550 0.000 69.830 4.000 ;
+ END
+ END wbs_dat_i[9]
+ PIN wbs_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 14.810 0.000 15.090 4.000 ;
+ END
+ END wbs_dat_o[0]
+ PIN wbs_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 76.910 0.000 77.190 4.000 ;
+ END
+ END wbs_dat_o[10]
+ PIN wbs_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 82.430 0.000 82.710 4.000 ;
+ END
+ END wbs_dat_o[11]
+ PIN wbs_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 87.950 0.000 88.230 4.000 ;
+ END
+ END wbs_dat_o[12]
+ PIN wbs_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 93.470 0.000 93.750 4.000 ;
+ END
+ END wbs_dat_o[13]
+ PIN wbs_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.990 0.000 99.270 4.000 ;
+ END
+ END wbs_dat_o[14]
+ PIN wbs_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 104.510 0.000 104.790 4.000 ;
+ END
+ END wbs_dat_o[15]
+ PIN wbs_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 110.030 0.000 110.310 4.000 ;
+ END
+ END wbs_dat_o[16]
+ PIN wbs_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 115.550 0.000 115.830 4.000 ;
+ END
+ END wbs_dat_o[17]
+ PIN wbs_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 120.610 0.000 120.890 4.000 ;
+ END
+ END wbs_dat_o[18]
+ PIN wbs_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 126.130 0.000 126.410 4.000 ;
+ END
+ END wbs_dat_o[19]
+ PIN wbs_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 22.170 0.000 22.450 4.000 ;
+ END
+ END wbs_dat_o[1]
+ PIN wbs_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 131.650 0.000 131.930 4.000 ;
+ END
+ END wbs_dat_o[20]
+ PIN wbs_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 137.170 0.000 137.450 4.000 ;
+ END
+ END wbs_dat_o[21]
+ PIN wbs_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 142.690 0.000 142.970 4.000 ;
+ END
+ END wbs_dat_o[22]
+ PIN wbs_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 148.210 0.000 148.490 4.000 ;
+ END
+ END wbs_dat_o[23]
+ PIN wbs_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 153.730 0.000 154.010 4.000 ;
+ END
+ END wbs_dat_o[24]
+ PIN wbs_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 159.250 0.000 159.530 4.000 ;
+ END
+ END wbs_dat_o[25]
+ PIN wbs_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 164.770 0.000 165.050 4.000 ;
+ END
+ END wbs_dat_o[26]
+ PIN wbs_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 170.290 0.000 170.570 4.000 ;
+ END
+ END wbs_dat_o[27]
+ PIN wbs_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 175.810 0.000 176.090 4.000 ;
+ END
+ END wbs_dat_o[28]
+ PIN wbs_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 180.870 0.000 181.150 4.000 ;
+ END
+ END wbs_dat_o[29]
+ PIN wbs_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 29.530 0.000 29.810 4.000 ;
+ END
+ END wbs_dat_o[2]
+ PIN wbs_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 186.390 0.000 186.670 4.000 ;
+ END
+ END wbs_dat_o[30]
+ PIN wbs_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 191.910 0.000 192.190 4.000 ;
+ END
+ END wbs_dat_o[31]
+ PIN wbs_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 36.890 0.000 37.170 4.000 ;
+ END
+ END wbs_dat_o[3]
+ PIN wbs_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 44.250 0.000 44.530 4.000 ;
+ END
+ END wbs_dat_o[4]
+ PIN wbs_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 49.770 0.000 50.050 4.000 ;
+ END
+ END wbs_dat_o[5]
+ PIN wbs_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 55.290 0.000 55.570 4.000 ;
+ END
+ END wbs_dat_o[6]
+ PIN wbs_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 60.350 0.000 60.630 4.000 ;
+ END
+ END wbs_dat_o[7]
+ PIN wbs_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 65.870 0.000 66.150 4.000 ;
+ END
+ END wbs_dat_o[8]
+ PIN wbs_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 71.390 0.000 71.670 4.000 ;
+ END
+ END wbs_dat_o[9]
+ PIN wbs_sel_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 16.650 0.000 16.930 4.000 ;
+ END
+ END wbs_sel_i[0]
+ PIN wbs_sel_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 24.010 0.000 24.290 4.000 ;
+ END
+ END wbs_sel_i[1]
+ PIN wbs_sel_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 31.370 0.000 31.650 4.000 ;
+ END
+ END wbs_sel_i[2]
+ PIN wbs_sel_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 38.730 0.000 39.010 4.000 ;
+ END
+ END wbs_sel_i[3]
+ PIN wbs_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 7.450 0.000 7.730 4.000 ;
+ END
+ END wbs_stb_i
+ PIN wbs_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 9.290 0.000 9.570 4.000 ;
+ END
+ END wbs_we_i
+ OBS
+ LAYER li1 ;
+ RECT 5.520 6.885 894.240 587.605 ;
+ LAYER met1 ;
+ RECT 0.530 6.160 899.230 587.760 ;
+ LAYER met2 ;
+ RECT 0.560 595.720 3.490 596.090 ;
+ RECT 4.330 595.720 11.310 596.090 ;
+ RECT 12.150 595.720 19.130 596.090 ;
+ RECT 19.970 595.720 26.950 596.090 ;
+ RECT 27.790 595.720 34.770 596.090 ;
+ RECT 35.610 595.720 42.590 596.090 ;
+ RECT 43.430 595.720 50.870 596.090 ;
+ RECT 51.710 595.720 58.690 596.090 ;
+ RECT 59.530 595.720 66.510 596.090 ;
+ RECT 67.350 595.720 74.330 596.090 ;
+ RECT 75.170 595.720 82.150 596.090 ;
+ RECT 82.990 595.720 89.970 596.090 ;
+ RECT 90.810 595.720 98.250 596.090 ;
+ RECT 99.090 595.720 106.070 596.090 ;
+ RECT 106.910 595.720 113.890 596.090 ;
+ RECT 114.730 595.720 121.710 596.090 ;
+ RECT 122.550 595.720 129.530 596.090 ;
+ RECT 130.370 595.720 137.350 596.090 ;
+ RECT 138.190 595.720 145.630 596.090 ;
+ RECT 146.470 595.720 153.450 596.090 ;
+ RECT 154.290 595.720 161.270 596.090 ;
+ RECT 162.110 595.720 169.090 596.090 ;
+ RECT 169.930 595.720 176.910 596.090 ;
+ RECT 177.750 595.720 184.730 596.090 ;
+ RECT 185.570 595.720 193.010 596.090 ;
+ RECT 193.850 595.720 200.830 596.090 ;
+ RECT 201.670 595.720 208.650 596.090 ;
+ RECT 209.490 595.720 216.470 596.090 ;
+ RECT 217.310 595.720 224.290 596.090 ;
+ RECT 225.130 595.720 232.110 596.090 ;
+ RECT 232.950 595.720 240.390 596.090 ;
+ RECT 241.230 595.720 248.210 596.090 ;
+ RECT 249.050 595.720 256.030 596.090 ;
+ RECT 256.870 595.720 263.850 596.090 ;
+ RECT 264.690 595.720 271.670 596.090 ;
+ RECT 272.510 595.720 279.490 596.090 ;
+ RECT 280.330 595.720 287.770 596.090 ;
+ RECT 288.610 595.720 295.590 596.090 ;
+ RECT 296.430 595.720 303.410 596.090 ;
+ RECT 304.250 595.720 311.230 596.090 ;
+ RECT 312.070 595.720 319.050 596.090 ;
+ RECT 319.890 595.720 326.870 596.090 ;
+ RECT 327.710 595.720 335.150 596.090 ;
+ RECT 335.990 595.720 342.970 596.090 ;
+ RECT 343.810 595.720 350.790 596.090 ;
+ RECT 351.630 595.720 358.610 596.090 ;
+ RECT 359.450 595.720 366.430 596.090 ;
+ RECT 367.270 595.720 374.250 596.090 ;
+ RECT 375.090 595.720 382.530 596.090 ;
+ RECT 383.370 595.720 390.350 596.090 ;
+ RECT 391.190 595.720 398.170 596.090 ;
+ RECT 399.010 595.720 405.990 596.090 ;
+ RECT 406.830 595.720 413.810 596.090 ;
+ RECT 414.650 595.720 421.630 596.090 ;
+ RECT 422.470 595.720 429.910 596.090 ;
+ RECT 430.750 595.720 437.730 596.090 ;
+ RECT 438.570 595.720 445.550 596.090 ;
+ RECT 446.390 595.720 453.370 596.090 ;
+ RECT 454.210 595.720 461.190 596.090 ;
+ RECT 462.030 595.720 469.010 596.090 ;
+ RECT 469.850 595.720 477.290 596.090 ;
+ RECT 478.130 595.720 485.110 596.090 ;
+ RECT 485.950 595.720 492.930 596.090 ;
+ RECT 493.770 595.720 500.750 596.090 ;
+ RECT 501.590 595.720 508.570 596.090 ;
+ RECT 509.410 595.720 516.390 596.090 ;
+ RECT 517.230 595.720 524.670 596.090 ;
+ RECT 525.510 595.720 532.490 596.090 ;
+ RECT 533.330 595.720 540.310 596.090 ;
+ RECT 541.150 595.720 548.130 596.090 ;
+ RECT 548.970 595.720 555.950 596.090 ;
+ RECT 556.790 595.720 563.770 596.090 ;
+ RECT 564.610 595.720 572.050 596.090 ;
+ RECT 572.890 595.720 579.870 596.090 ;
+ RECT 580.710 595.720 587.690 596.090 ;
+ RECT 588.530 595.720 595.510 596.090 ;
+ RECT 596.350 595.720 603.330 596.090 ;
+ RECT 604.170 595.720 611.150 596.090 ;
+ RECT 611.990 595.720 619.430 596.090 ;
+ RECT 620.270 595.720 627.250 596.090 ;
+ RECT 628.090 595.720 635.070 596.090 ;
+ RECT 635.910 595.720 642.890 596.090 ;
+ RECT 643.730 595.720 650.710 596.090 ;
+ RECT 651.550 595.720 658.530 596.090 ;
+ RECT 659.370 595.720 666.810 596.090 ;
+ RECT 667.650 595.720 674.630 596.090 ;
+ RECT 675.470 595.720 682.450 596.090 ;
+ RECT 683.290 595.720 690.270 596.090 ;
+ RECT 691.110 595.720 698.090 596.090 ;
+ RECT 698.930 595.720 705.910 596.090 ;
+ RECT 706.750 595.720 714.190 596.090 ;
+ RECT 715.030 595.720 722.010 596.090 ;
+ RECT 722.850 595.720 729.830 596.090 ;
+ RECT 730.670 595.720 737.650 596.090 ;
+ RECT 738.490 595.720 745.470 596.090 ;
+ RECT 746.310 595.720 753.290 596.090 ;
+ RECT 754.130 595.720 761.570 596.090 ;
+ RECT 762.410 595.720 769.390 596.090 ;
+ RECT 770.230 595.720 777.210 596.090 ;
+ RECT 778.050 595.720 785.030 596.090 ;
+ RECT 785.870 595.720 792.850 596.090 ;
+ RECT 793.690 595.720 800.670 596.090 ;
+ RECT 801.510 595.720 808.950 596.090 ;
+ RECT 809.790 595.720 816.770 596.090 ;
+ RECT 817.610 595.720 824.590 596.090 ;
+ RECT 825.430 595.720 832.410 596.090 ;
+ RECT 833.250 595.720 840.230 596.090 ;
+ RECT 841.070 595.720 848.050 596.090 ;
+ RECT 848.890 595.720 856.330 596.090 ;
+ RECT 857.170 595.720 864.150 596.090 ;
+ RECT 864.990 595.720 871.970 596.090 ;
+ RECT 872.810 595.720 879.790 596.090 ;
+ RECT 880.630 595.720 887.610 596.090 ;
+ RECT 888.450 595.720 895.430 596.090 ;
+ RECT 896.270 595.720 899.200 596.090 ;
+ RECT 0.560 4.280 899.200 595.720 ;
+ RECT 1.110 3.670 1.650 4.280 ;
+ RECT 2.490 3.670 3.490 4.280 ;
+ RECT 4.330 3.670 5.330 4.280 ;
+ RECT 6.170 3.670 7.170 4.280 ;
+ RECT 8.010 3.670 9.010 4.280 ;
+ RECT 9.850 3.670 10.850 4.280 ;
+ RECT 11.690 3.670 12.690 4.280 ;
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+ RECT 813.470 3.670 814.470 4.280 ;
+ RECT 815.310 3.670 816.310 4.280 ;
+ RECT 817.150 3.670 818.150 4.280 ;
+ RECT 818.990 3.670 819.990 4.280 ;
+ RECT 820.830 3.670 821.830 4.280 ;
+ RECT 822.670 3.670 823.670 4.280 ;
+ RECT 824.510 3.670 825.510 4.280 ;
+ RECT 826.350 3.670 827.350 4.280 ;
+ RECT 828.190 3.670 829.190 4.280 ;
+ RECT 830.030 3.670 831.030 4.280 ;
+ RECT 831.870 3.670 832.870 4.280 ;
+ RECT 833.710 3.670 834.710 4.280 ;
+ RECT 835.550 3.670 836.550 4.280 ;
+ RECT 837.390 3.670 838.390 4.280 ;
+ RECT 839.230 3.670 840.230 4.280 ;
+ RECT 841.070 3.670 841.610 4.280 ;
+ RECT 842.450 3.670 843.450 4.280 ;
+ RECT 844.290 3.670 845.290 4.280 ;
+ RECT 846.130 3.670 847.130 4.280 ;
+ RECT 847.970 3.670 848.970 4.280 ;
+ RECT 849.810 3.670 850.810 4.280 ;
+ RECT 851.650 3.670 852.650 4.280 ;
+ RECT 853.490 3.670 854.490 4.280 ;
+ RECT 855.330 3.670 856.330 4.280 ;
+ RECT 857.170 3.670 858.170 4.280 ;
+ RECT 859.010 3.670 860.010 4.280 ;
+ RECT 860.850 3.670 861.850 4.280 ;
+ RECT 862.690 3.670 863.690 4.280 ;
+ RECT 864.530 3.670 865.530 4.280 ;
+ RECT 866.370 3.670 867.370 4.280 ;
+ RECT 868.210 3.670 869.210 4.280 ;
+ RECT 870.050 3.670 871.050 4.280 ;
+ RECT 871.890 3.670 872.890 4.280 ;
+ RECT 873.730 3.670 874.730 4.280 ;
+ RECT 875.570 3.670 876.570 4.280 ;
+ RECT 877.410 3.670 878.410 4.280 ;
+ RECT 879.250 3.670 880.250 4.280 ;
+ RECT 881.090 3.670 882.090 4.280 ;
+ RECT 882.930 3.670 883.930 4.280 ;
+ RECT 884.770 3.670 885.770 4.280 ;
+ RECT 886.610 3.670 887.610 4.280 ;
+ RECT 888.450 3.670 889.450 4.280 ;
+ RECT 890.290 3.670 891.290 4.280 ;
+ RECT 892.130 3.670 893.130 4.280 ;
+ RECT 893.970 3.670 894.970 4.280 ;
+ RECT 895.810 3.670 896.810 4.280 ;
+ RECT 897.650 3.670 898.650 4.280 ;
+ LAYER met3 ;
+ RECT 8.345 9.015 867.440 587.685 ;
+ LAYER met4 ;
+ RECT 174.640 9.015 867.440 587.760 ;
+ END
+END user_proj_example
+END LIBRARY
+
diff --git a/openlane/designs/caravel_upw/macros/user_proj_example2.gds b/openlane/designs/caravel_upw/macros/user_proj_example2.gds
new file mode 100644
index 0000000..b32ae18
--- /dev/null
+++ b/openlane/designs/caravel_upw/macros/user_proj_example2.gds
Binary files differ
diff --git a/openlane/designs/caravel_upw/macros/user_proj_example2.lef b/openlane/designs/caravel_upw/macros/user_proj_example2.lef
new file mode 100644
index 0000000..01b703d
--- /dev/null
+++ b/openlane/designs/caravel_upw/macros/user_proj_example2.lef
@@ -0,0 +1,5503 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO user_proj_example2
+ CLASS BLOCK ;
+ FOREIGN user_proj_example2 ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 900.000 BY 600.000 ;
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 3.770 596.000 4.050 600.000 ;
+ END
+ END io_in[0]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 240.670 596.000 240.950 600.000 ;
+ END
+ END io_in[10]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 264.130 596.000 264.410 600.000 ;
+ END
+ END io_in[11]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 288.050 596.000 288.330 600.000 ;
+ END
+ END io_in[12]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 311.510 596.000 311.790 600.000 ;
+ END
+ END io_in[13]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 335.430 596.000 335.710 600.000 ;
+ END
+ END io_in[14]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 358.890 596.000 359.170 600.000 ;
+ END
+ END io_in[15]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 382.810 596.000 383.090 600.000 ;
+ END
+ END io_in[16]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 406.270 596.000 406.550 600.000 ;
+ END
+ END io_in[17]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 430.190 596.000 430.470 600.000 ;
+ END
+ END io_in[18]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.650 596.000 453.930 600.000 ;
+ END
+ END io_in[19]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.230 596.000 27.510 600.000 ;
+ END
+ END io_in[1]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 477.570 596.000 477.850 600.000 ;
+ END
+ END io_in[20]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 501.030 596.000 501.310 600.000 ;
+ END
+ END io_in[21]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 524.950 596.000 525.230 600.000 ;
+ END
+ END io_in[22]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 548.410 596.000 548.690 600.000 ;
+ END
+ END io_in[23]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 572.330 596.000 572.610 600.000 ;
+ END
+ END io_in[24]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 595.790 596.000 596.070 600.000 ;
+ END
+ END io_in[25]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 619.710 596.000 619.990 600.000 ;
+ END
+ END io_in[26]
+ PIN io_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 643.170 596.000 643.450 600.000 ;
+ END
+ END io_in[27]
+ PIN io_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 667.090 596.000 667.370 600.000 ;
+ END
+ END io_in[28]
+ PIN io_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 690.550 596.000 690.830 600.000 ;
+ END
+ END io_in[29]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 51.150 596.000 51.430 600.000 ;
+ END
+ END io_in[2]
+ PIN io_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 714.470 596.000 714.750 600.000 ;
+ END
+ END io_in[30]
+ PIN io_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 737.930 596.000 738.210 600.000 ;
+ END
+ END io_in[31]
+ PIN io_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 761.850 596.000 762.130 600.000 ;
+ END
+ END io_in[32]
+ PIN io_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 785.310 596.000 785.590 600.000 ;
+ END
+ END io_in[33]
+ PIN io_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 809.230 596.000 809.510 600.000 ;
+ END
+ END io_in[34]
+ PIN io_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 832.690 596.000 832.970 600.000 ;
+ END
+ END io_in[35]
+ PIN io_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 856.610 596.000 856.890 600.000 ;
+ END
+ END io_in[36]
+ PIN io_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 880.070 596.000 880.350 600.000 ;
+ END
+ END io_in[37]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 74.610 596.000 74.890 600.000 ;
+ END
+ END io_in[3]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.530 596.000 98.810 600.000 ;
+ END
+ END io_in[4]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 121.990 596.000 122.270 600.000 ;
+ END
+ END io_in[5]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 145.910 596.000 146.190 600.000 ;
+ END
+ END io_in[6]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 169.370 596.000 169.650 600.000 ;
+ END
+ END io_in[7]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.290 596.000 193.570 600.000 ;
+ END
+ END io_in[8]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 216.750 596.000 217.030 600.000 ;
+ END
+ END io_in[9]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 11.590 596.000 11.870 600.000 ;
+ END
+ END io_oeb[0]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 248.490 596.000 248.770 600.000 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 271.950 596.000 272.230 600.000 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 295.870 596.000 296.150 600.000 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 319.330 596.000 319.610 600.000 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 343.250 596.000 343.530 600.000 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 366.710 596.000 366.990 600.000 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 390.630 596.000 390.910 600.000 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 414.090 596.000 414.370 600.000 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 438.010 596.000 438.290 600.000 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 461.470 596.000 461.750 600.000 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 35.050 596.000 35.330 600.000 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.390 596.000 485.670 600.000 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 508.850 596.000 509.130 600.000 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 532.770 596.000 533.050 600.000 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 556.230 596.000 556.510 600.000 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 580.150 596.000 580.430 600.000 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 603.610 596.000 603.890 600.000 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 627.530 596.000 627.810 600.000 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 650.990 596.000 651.270 600.000 ;
+ END
+ END io_oeb[27]
+ PIN io_oeb[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 674.910 596.000 675.190 600.000 ;
+ END
+ END io_oeb[28]
+ PIN io_oeb[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 698.370 596.000 698.650 600.000 ;
+ END
+ END io_oeb[29]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 58.970 596.000 59.250 600.000 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 722.290 596.000 722.570 600.000 ;
+ END
+ END io_oeb[30]
+ PIN io_oeb[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 745.750 596.000 746.030 600.000 ;
+ END
+ END io_oeb[31]
+ PIN io_oeb[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 769.670 596.000 769.950 600.000 ;
+ END
+ END io_oeb[32]
+ PIN io_oeb[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 793.130 596.000 793.410 600.000 ;
+ END
+ END io_oeb[33]
+ PIN io_oeb[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 817.050 596.000 817.330 600.000 ;
+ END
+ END io_oeb[34]
+ PIN io_oeb[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 840.510 596.000 840.790 600.000 ;
+ END
+ END io_oeb[35]
+ PIN io_oeb[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 864.430 596.000 864.710 600.000 ;
+ END
+ END io_oeb[36]
+ PIN io_oeb[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 887.890 596.000 888.170 600.000 ;
+ END
+ END io_oeb[37]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 82.430 596.000 82.710 600.000 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 106.350 596.000 106.630 600.000 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 129.810 596.000 130.090 600.000 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 153.730 596.000 154.010 600.000 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 177.190 596.000 177.470 600.000 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 201.110 596.000 201.390 600.000 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 224.570 596.000 224.850 600.000 ;
+ END
+ END io_oeb[9]
+ PIN io_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 19.410 596.000 19.690 600.000 ;
+ END
+ END io_out[0]
+ PIN io_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 256.310 596.000 256.590 600.000 ;
+ END
+ END io_out[10]
+ PIN io_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 279.770 596.000 280.050 600.000 ;
+ END
+ END io_out[11]
+ PIN io_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 303.690 596.000 303.970 600.000 ;
+ END
+ END io_out[12]
+ PIN io_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.150 596.000 327.430 600.000 ;
+ END
+ END io_out[13]
+ PIN io_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.070 596.000 351.350 600.000 ;
+ END
+ END io_out[14]
+ PIN io_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.530 596.000 374.810 600.000 ;
+ END
+ END io_out[15]
+ PIN io_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 398.450 596.000 398.730 600.000 ;
+ END
+ END io_out[16]
+ PIN io_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 421.910 596.000 422.190 600.000 ;
+ END
+ END io_out[17]
+ PIN io_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.830 596.000 446.110 600.000 ;
+ END
+ END io_out[18]
+ PIN io_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.290 596.000 469.570 600.000 ;
+ END
+ END io_out[19]
+ PIN io_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 42.870 596.000 43.150 600.000 ;
+ END
+ END io_out[1]
+ PIN io_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 493.210 596.000 493.490 600.000 ;
+ END
+ END io_out[20]
+ PIN io_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 516.670 596.000 516.950 600.000 ;
+ END
+ END io_out[21]
+ PIN io_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 540.590 596.000 540.870 600.000 ;
+ END
+ END io_out[22]
+ PIN io_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 564.050 596.000 564.330 600.000 ;
+ END
+ END io_out[23]
+ PIN io_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 587.970 596.000 588.250 600.000 ;
+ END
+ END io_out[24]
+ PIN io_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 611.430 596.000 611.710 600.000 ;
+ END
+ END io_out[25]
+ PIN io_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 635.350 596.000 635.630 600.000 ;
+ END
+ END io_out[26]
+ PIN io_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 658.810 596.000 659.090 600.000 ;
+ END
+ END io_out[27]
+ PIN io_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 682.730 596.000 683.010 600.000 ;
+ END
+ END io_out[28]
+ PIN io_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 706.190 596.000 706.470 600.000 ;
+ END
+ END io_out[29]
+ PIN io_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 66.790 596.000 67.070 600.000 ;
+ END
+ END io_out[2]
+ PIN io_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 730.110 596.000 730.390 600.000 ;
+ END
+ END io_out[30]
+ PIN io_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 753.570 596.000 753.850 600.000 ;
+ END
+ END io_out[31]
+ PIN io_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 777.490 596.000 777.770 600.000 ;
+ END
+ END io_out[32]
+ PIN io_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 800.950 596.000 801.230 600.000 ;
+ END
+ END io_out[33]
+ PIN io_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 824.870 596.000 825.150 600.000 ;
+ END
+ END io_out[34]
+ PIN io_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 848.330 596.000 848.610 600.000 ;
+ END
+ END io_out[35]
+ PIN io_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 872.250 596.000 872.530 600.000 ;
+ END
+ END io_out[36]
+ PIN io_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 895.710 596.000 895.990 600.000 ;
+ END
+ END io_out[37]
+ PIN io_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 90.250 596.000 90.530 600.000 ;
+ END
+ END io_out[3]
+ PIN io_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 114.170 596.000 114.450 600.000 ;
+ END
+ END io_out[4]
+ PIN io_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 137.630 596.000 137.910 600.000 ;
+ END
+ END io_out[5]
+ PIN io_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.550 596.000 161.830 600.000 ;
+ END
+ END io_out[6]
+ PIN io_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 185.010 596.000 185.290 600.000 ;
+ END
+ END io_out[7]
+ PIN io_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 208.930 596.000 209.210 600.000 ;
+ END
+ END io_out[8]
+ PIN io_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 232.390 596.000 232.670 600.000 ;
+ END
+ END io_out[9]
+ PIN irq[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 895.250 0.000 895.530 4.000 ;
+ END
+ END irq[0]
+ PIN irq[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 897.090 0.000 897.370 4.000 ;
+ END
+ END irq[1]
+ PIN irq[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 898.930 0.000 899.210 4.000 ;
+ END
+ END irq[2]
+ PIN la_data_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 193.750 0.000 194.030 4.000 ;
+ END
+ END la_data_in[0]
+ PIN la_data_in[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 741.610 0.000 741.890 4.000 ;
+ END
+ END la_data_in[100]
+ PIN la_data_in[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 747.130 0.000 747.410 4.000 ;
+ END
+ END la_data_in[101]
+ PIN la_data_in[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 752.650 0.000 752.930 4.000 ;
+ END
+ END la_data_in[102]
+ PIN la_data_in[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 758.170 0.000 758.450 4.000 ;
+ END
+ END la_data_in[103]
+ PIN la_data_in[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 763.690 0.000 763.970 4.000 ;
+ END
+ END la_data_in[104]
+ PIN la_data_in[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 769.210 0.000 769.490 4.000 ;
+ END
+ END la_data_in[105]
+ PIN la_data_in[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 774.730 0.000 775.010 4.000 ;
+ END
+ END la_data_in[106]
+ PIN la_data_in[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 780.250 0.000 780.530 4.000 ;
+ END
+ END la_data_in[107]
+ PIN la_data_in[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 785.310 0.000 785.590 4.000 ;
+ END
+ END la_data_in[108]
+ PIN la_data_in[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 790.830 0.000 791.110 4.000 ;
+ END
+ END la_data_in[109]
+ PIN la_data_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 248.490 0.000 248.770 4.000 ;
+ END
+ END la_data_in[10]
+ PIN la_data_in[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 796.350 0.000 796.630 4.000 ;
+ END
+ END la_data_in[110]
+ PIN la_data_in[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 801.870 0.000 802.150 4.000 ;
+ END
+ END la_data_in[111]
+ PIN la_data_in[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 807.390 0.000 807.670 4.000 ;
+ END
+ END la_data_in[112]
+ PIN la_data_in[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 812.910 0.000 813.190 4.000 ;
+ END
+ END la_data_in[113]
+ PIN la_data_in[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 818.430 0.000 818.710 4.000 ;
+ END
+ END la_data_in[114]
+ PIN la_data_in[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 823.950 0.000 824.230 4.000 ;
+ END
+ END la_data_in[115]
+ PIN la_data_in[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 829.470 0.000 829.750 4.000 ;
+ END
+ END la_data_in[116]
+ PIN la_data_in[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 834.990 0.000 835.270 4.000 ;
+ END
+ END la_data_in[117]
+ PIN la_data_in[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 840.510 0.000 840.790 4.000 ;
+ END
+ END la_data_in[118]
+ PIN la_data_in[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 845.570 0.000 845.850 4.000 ;
+ END
+ END la_data_in[119]
+ PIN la_data_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 254.010 0.000 254.290 4.000 ;
+ END
+ END la_data_in[11]
+ PIN la_data_in[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 851.090 0.000 851.370 4.000 ;
+ END
+ END la_data_in[120]
+ PIN la_data_in[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 856.610 0.000 856.890 4.000 ;
+ END
+ END la_data_in[121]
+ PIN la_data_in[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 862.130 0.000 862.410 4.000 ;
+ END
+ END la_data_in[122]
+ PIN la_data_in[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 867.650 0.000 867.930 4.000 ;
+ END
+ END la_data_in[123]
+ PIN la_data_in[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 873.170 0.000 873.450 4.000 ;
+ END
+ END la_data_in[124]
+ PIN la_data_in[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 878.690 0.000 878.970 4.000 ;
+ END
+ END la_data_in[125]
+ PIN la_data_in[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 884.210 0.000 884.490 4.000 ;
+ END
+ END la_data_in[126]
+ PIN la_data_in[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 889.730 0.000 890.010 4.000 ;
+ END
+ END la_data_in[127]
+ PIN la_data_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 259.530 0.000 259.810 4.000 ;
+ END
+ END la_data_in[12]
+ PIN la_data_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 265.050 0.000 265.330 4.000 ;
+ END
+ END la_data_in[13]
+ PIN la_data_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 270.570 0.000 270.850 4.000 ;
+ END
+ END la_data_in[14]
+ PIN la_data_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 276.090 0.000 276.370 4.000 ;
+ END
+ END la_data_in[15]
+ PIN la_data_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 281.610 0.000 281.890 4.000 ;
+ END
+ END la_data_in[16]
+ PIN la_data_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 287.130 0.000 287.410 4.000 ;
+ END
+ END la_data_in[17]
+ PIN la_data_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.650 0.000 292.930 4.000 ;
+ END
+ END la_data_in[18]
+ PIN la_data_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 298.170 0.000 298.450 4.000 ;
+ END
+ END la_data_in[19]
+ PIN la_data_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 199.270 0.000 199.550 4.000 ;
+ END
+ END la_data_in[1]
+ PIN la_data_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 303.230 0.000 303.510 4.000 ;
+ END
+ END la_data_in[20]
+ PIN la_data_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 308.750 0.000 309.030 4.000 ;
+ END
+ END la_data_in[21]
+ PIN la_data_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 314.270 0.000 314.550 4.000 ;
+ END
+ END la_data_in[22]
+ PIN la_data_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 319.790 0.000 320.070 4.000 ;
+ END
+ END la_data_in[23]
+ PIN la_data_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 325.310 0.000 325.590 4.000 ;
+ END
+ END la_data_in[24]
+ PIN la_data_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 330.830 0.000 331.110 4.000 ;
+ END
+ END la_data_in[25]
+ PIN la_data_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 336.350 0.000 336.630 4.000 ;
+ END
+ END la_data_in[26]
+ PIN la_data_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 341.870 0.000 342.150 4.000 ;
+ END
+ END la_data_in[27]
+ PIN la_data_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 347.390 0.000 347.670 4.000 ;
+ END
+ END la_data_in[28]
+ PIN la_data_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 352.910 0.000 353.190 4.000 ;
+ END
+ END la_data_in[29]
+ PIN la_data_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 204.790 0.000 205.070 4.000 ;
+ END
+ END la_data_in[2]
+ PIN la_data_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 358.430 0.000 358.710 4.000 ;
+ END
+ END la_data_in[30]
+ PIN la_data_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 363.490 0.000 363.770 4.000 ;
+ END
+ END la_data_in[31]
+ PIN la_data_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 369.010 0.000 369.290 4.000 ;
+ END
+ END la_data_in[32]
+ PIN la_data_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.530 0.000 374.810 4.000 ;
+ END
+ END la_data_in[33]
+ PIN la_data_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 380.050 0.000 380.330 4.000 ;
+ END
+ END la_data_in[34]
+ PIN la_data_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 385.570 0.000 385.850 4.000 ;
+ END
+ END la_data_in[35]
+ PIN la_data_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 391.090 0.000 391.370 4.000 ;
+ END
+ END la_data_in[36]
+ PIN la_data_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 396.610 0.000 396.890 4.000 ;
+ END
+ END la_data_in[37]
+ PIN la_data_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 402.130 0.000 402.410 4.000 ;
+ END
+ END la_data_in[38]
+ PIN la_data_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 407.650 0.000 407.930 4.000 ;
+ END
+ END la_data_in[39]
+ PIN la_data_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 210.310 0.000 210.590 4.000 ;
+ END
+ END la_data_in[3]
+ PIN la_data_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 413.170 0.000 413.450 4.000 ;
+ END
+ END la_data_in[40]
+ PIN la_data_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 418.690 0.000 418.970 4.000 ;
+ END
+ END la_data_in[41]
+ PIN la_data_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 423.750 0.000 424.030 4.000 ;
+ END
+ END la_data_in[42]
+ PIN la_data_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 429.270 0.000 429.550 4.000 ;
+ END
+ END la_data_in[43]
+ PIN la_data_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.790 0.000 435.070 4.000 ;
+ END
+ END la_data_in[44]
+ PIN la_data_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 440.310 0.000 440.590 4.000 ;
+ END
+ END la_data_in[45]
+ PIN la_data_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.830 0.000 446.110 4.000 ;
+ END
+ END la_data_in[46]
+ PIN la_data_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 451.350 0.000 451.630 4.000 ;
+ END
+ END la_data_in[47]
+ PIN la_data_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 456.870 0.000 457.150 4.000 ;
+ END
+ END la_data_in[48]
+ PIN la_data_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 462.390 0.000 462.670 4.000 ;
+ END
+ END la_data_in[49]
+ PIN la_data_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 215.830 0.000 216.110 4.000 ;
+ END
+ END la_data_in[4]
+ PIN la_data_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 467.910 0.000 468.190 4.000 ;
+ END
+ END la_data_in[50]
+ PIN la_data_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 473.430 0.000 473.710 4.000 ;
+ END
+ END la_data_in[51]
+ PIN la_data_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 478.950 0.000 479.230 4.000 ;
+ END
+ END la_data_in[52]
+ PIN la_data_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 484.010 0.000 484.290 4.000 ;
+ END
+ END la_data_in[53]
+ PIN la_data_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 489.530 0.000 489.810 4.000 ;
+ END
+ END la_data_in[54]
+ PIN la_data_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 495.050 0.000 495.330 4.000 ;
+ END
+ END la_data_in[55]
+ PIN la_data_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 500.570 0.000 500.850 4.000 ;
+ END
+ END la_data_in[56]
+ PIN la_data_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 506.090 0.000 506.370 4.000 ;
+ END
+ END la_data_in[57]
+ PIN la_data_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 511.610 0.000 511.890 4.000 ;
+ END
+ END la_data_in[58]
+ PIN la_data_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 517.130 0.000 517.410 4.000 ;
+ END
+ END la_data_in[59]
+ PIN la_data_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 221.350 0.000 221.630 4.000 ;
+ END
+ END la_data_in[5]
+ PIN la_data_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 522.650 0.000 522.930 4.000 ;
+ END
+ END la_data_in[60]
+ PIN la_data_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 528.170 0.000 528.450 4.000 ;
+ END
+ END la_data_in[61]
+ PIN la_data_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 533.690 0.000 533.970 4.000 ;
+ END
+ END la_data_in[62]
+ PIN la_data_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 539.210 0.000 539.490 4.000 ;
+ END
+ END la_data_in[63]
+ PIN la_data_in[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 544.270 0.000 544.550 4.000 ;
+ END
+ END la_data_in[64]
+ PIN la_data_in[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 549.790 0.000 550.070 4.000 ;
+ END
+ END la_data_in[65]
+ PIN la_data_in[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 555.310 0.000 555.590 4.000 ;
+ END
+ END la_data_in[66]
+ PIN la_data_in[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 560.830 0.000 561.110 4.000 ;
+ END
+ END la_data_in[67]
+ PIN la_data_in[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 566.350 0.000 566.630 4.000 ;
+ END
+ END la_data_in[68]
+ PIN la_data_in[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 571.870 0.000 572.150 4.000 ;
+ END
+ END la_data_in[69]
+ PIN la_data_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 226.870 0.000 227.150 4.000 ;
+ END
+ END la_data_in[6]
+ PIN la_data_in[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 577.390 0.000 577.670 4.000 ;
+ END
+ END la_data_in[70]
+ PIN la_data_in[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 582.910 0.000 583.190 4.000 ;
+ END
+ END la_data_in[71]
+ PIN la_data_in[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 588.430 0.000 588.710 4.000 ;
+ END
+ END la_data_in[72]
+ PIN la_data_in[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 593.950 0.000 594.230 4.000 ;
+ END
+ END la_data_in[73]
+ PIN la_data_in[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 599.470 0.000 599.750 4.000 ;
+ END
+ END la_data_in[74]
+ PIN la_data_in[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 604.530 0.000 604.810 4.000 ;
+ END
+ END la_data_in[75]
+ PIN la_data_in[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 610.050 0.000 610.330 4.000 ;
+ END
+ END la_data_in[76]
+ PIN la_data_in[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 615.570 0.000 615.850 4.000 ;
+ END
+ END la_data_in[77]
+ PIN la_data_in[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 621.090 0.000 621.370 4.000 ;
+ END
+ END la_data_in[78]
+ PIN la_data_in[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 626.610 0.000 626.890 4.000 ;
+ END
+ END la_data_in[79]
+ PIN la_data_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 232.390 0.000 232.670 4.000 ;
+ END
+ END la_data_in[7]
+ PIN la_data_in[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 632.130 0.000 632.410 4.000 ;
+ END
+ END la_data_in[80]
+ PIN la_data_in[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 637.650 0.000 637.930 4.000 ;
+ END
+ END la_data_in[81]
+ PIN la_data_in[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 643.170 0.000 643.450 4.000 ;
+ END
+ END la_data_in[82]
+ PIN la_data_in[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 648.690 0.000 648.970 4.000 ;
+ END
+ END la_data_in[83]
+ PIN la_data_in[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 654.210 0.000 654.490 4.000 ;
+ END
+ END la_data_in[84]
+ PIN la_data_in[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 659.730 0.000 660.010 4.000 ;
+ END
+ END la_data_in[85]
+ PIN la_data_in[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 664.790 0.000 665.070 4.000 ;
+ END
+ END la_data_in[86]
+ PIN la_data_in[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 670.310 0.000 670.590 4.000 ;
+ END
+ END la_data_in[87]
+ PIN la_data_in[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 675.830 0.000 676.110 4.000 ;
+ END
+ END la_data_in[88]
+ PIN la_data_in[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 681.350 0.000 681.630 4.000 ;
+ END
+ END la_data_in[89]
+ PIN la_data_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 237.910 0.000 238.190 4.000 ;
+ END
+ END la_data_in[8]
+ PIN la_data_in[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 686.870 0.000 687.150 4.000 ;
+ END
+ END la_data_in[90]
+ PIN la_data_in[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 692.390 0.000 692.670 4.000 ;
+ END
+ END la_data_in[91]
+ PIN la_data_in[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 697.910 0.000 698.190 4.000 ;
+ END
+ END la_data_in[92]
+ PIN la_data_in[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 703.430 0.000 703.710 4.000 ;
+ END
+ END la_data_in[93]
+ PIN la_data_in[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 708.950 0.000 709.230 4.000 ;
+ END
+ END la_data_in[94]
+ PIN la_data_in[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 714.470 0.000 714.750 4.000 ;
+ END
+ END la_data_in[95]
+ PIN la_data_in[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 719.990 0.000 720.270 4.000 ;
+ END
+ END la_data_in[96]
+ PIN la_data_in[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 725.050 0.000 725.330 4.000 ;
+ END
+ END la_data_in[97]
+ PIN la_data_in[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 730.570 0.000 730.850 4.000 ;
+ END
+ END la_data_in[98]
+ PIN la_data_in[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 736.090 0.000 736.370 4.000 ;
+ END
+ END la_data_in[99]
+ PIN la_data_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 242.970 0.000 243.250 4.000 ;
+ END
+ END la_data_in[9]
+ PIN la_data_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 195.590 0.000 195.870 4.000 ;
+ END
+ END la_data_out[0]
+ PIN la_data_out[100]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 743.450 0.000 743.730 4.000 ;
+ END
+ END la_data_out[100]
+ PIN la_data_out[101]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 748.970 0.000 749.250 4.000 ;
+ END
+ END la_data_out[101]
+ PIN la_data_out[102]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 754.490 0.000 754.770 4.000 ;
+ END
+ END la_data_out[102]
+ PIN la_data_out[103]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 760.010 0.000 760.290 4.000 ;
+ END
+ END la_data_out[103]
+ PIN la_data_out[104]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 765.530 0.000 765.810 4.000 ;
+ END
+ END la_data_out[104]
+ PIN la_data_out[105]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 771.050 0.000 771.330 4.000 ;
+ END
+ END la_data_out[105]
+ PIN la_data_out[106]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 776.570 0.000 776.850 4.000 ;
+ END
+ END la_data_out[106]
+ PIN la_data_out[107]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 781.630 0.000 781.910 4.000 ;
+ END
+ END la_data_out[107]
+ PIN la_data_out[108]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 787.150 0.000 787.430 4.000 ;
+ END
+ END la_data_out[108]
+ PIN la_data_out[109]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 792.670 0.000 792.950 4.000 ;
+ END
+ END la_data_out[109]
+ PIN la_data_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 250.330 0.000 250.610 4.000 ;
+ END
+ END la_data_out[10]
+ PIN la_data_out[110]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 798.190 0.000 798.470 4.000 ;
+ END
+ END la_data_out[110]
+ PIN la_data_out[111]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 803.710 0.000 803.990 4.000 ;
+ END
+ END la_data_out[111]
+ PIN la_data_out[112]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 809.230 0.000 809.510 4.000 ;
+ END
+ END la_data_out[112]
+ PIN la_data_out[113]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 814.750 0.000 815.030 4.000 ;
+ END
+ END la_data_out[113]
+ PIN la_data_out[114]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 820.270 0.000 820.550 4.000 ;
+ END
+ END la_data_out[114]
+ PIN la_data_out[115]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 825.790 0.000 826.070 4.000 ;
+ END
+ END la_data_out[115]
+ PIN la_data_out[116]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 831.310 0.000 831.590 4.000 ;
+ END
+ END la_data_out[116]
+ PIN la_data_out[117]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 836.830 0.000 837.110 4.000 ;
+ END
+ END la_data_out[117]
+ PIN la_data_out[118]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 841.890 0.000 842.170 4.000 ;
+ END
+ END la_data_out[118]
+ PIN la_data_out[119]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 847.410 0.000 847.690 4.000 ;
+ END
+ END la_data_out[119]
+ PIN la_data_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 255.850 0.000 256.130 4.000 ;
+ END
+ END la_data_out[11]
+ PIN la_data_out[120]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 852.930 0.000 853.210 4.000 ;
+ END
+ END la_data_out[120]
+ PIN la_data_out[121]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 858.450 0.000 858.730 4.000 ;
+ END
+ END la_data_out[121]
+ PIN la_data_out[122]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 863.970 0.000 864.250 4.000 ;
+ END
+ END la_data_out[122]
+ PIN la_data_out[123]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 869.490 0.000 869.770 4.000 ;
+ END
+ END la_data_out[123]
+ PIN la_data_out[124]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 875.010 0.000 875.290 4.000 ;
+ END
+ END la_data_out[124]
+ PIN la_data_out[125]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 880.530 0.000 880.810 4.000 ;
+ END
+ END la_data_out[125]
+ PIN la_data_out[126]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 886.050 0.000 886.330 4.000 ;
+ END
+ END la_data_out[126]
+ PIN la_data_out[127]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 891.570 0.000 891.850 4.000 ;
+ END
+ END la_data_out[127]
+ PIN la_data_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 261.370 0.000 261.650 4.000 ;
+ END
+ END la_data_out[12]
+ PIN la_data_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 266.890 0.000 267.170 4.000 ;
+ END
+ END la_data_out[13]
+ PIN la_data_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 272.410 0.000 272.690 4.000 ;
+ END
+ END la_data_out[14]
+ PIN la_data_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 277.930 0.000 278.210 4.000 ;
+ END
+ END la_data_out[15]
+ PIN la_data_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 283.450 0.000 283.730 4.000 ;
+ END
+ END la_data_out[16]
+ PIN la_data_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 288.970 0.000 289.250 4.000 ;
+ END
+ END la_data_out[17]
+ PIN la_data_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 294.490 0.000 294.770 4.000 ;
+ END
+ END la_data_out[18]
+ PIN la_data_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 300.010 0.000 300.290 4.000 ;
+ END
+ END la_data_out[19]
+ PIN la_data_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 201.110 0.000 201.390 4.000 ;
+ END
+ END la_data_out[1]
+ PIN la_data_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 305.070 0.000 305.350 4.000 ;
+ END
+ END la_data_out[20]
+ PIN la_data_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 310.590 0.000 310.870 4.000 ;
+ END
+ END la_data_out[21]
+ PIN la_data_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 316.110 0.000 316.390 4.000 ;
+ END
+ END la_data_out[22]
+ PIN la_data_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 321.630 0.000 321.910 4.000 ;
+ END
+ END la_data_out[23]
+ PIN la_data_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.150 0.000 327.430 4.000 ;
+ END
+ END la_data_out[24]
+ PIN la_data_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 332.670 0.000 332.950 4.000 ;
+ END
+ END la_data_out[25]
+ PIN la_data_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 338.190 0.000 338.470 4.000 ;
+ END
+ END la_data_out[26]
+ PIN la_data_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 343.710 0.000 343.990 4.000 ;
+ END
+ END la_data_out[27]
+ PIN la_data_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 349.230 0.000 349.510 4.000 ;
+ END
+ END la_data_out[28]
+ PIN la_data_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 354.750 0.000 355.030 4.000 ;
+ END
+ END la_data_out[29]
+ PIN la_data_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 206.630 0.000 206.910 4.000 ;
+ END
+ END la_data_out[2]
+ PIN la_data_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 360.270 0.000 360.550 4.000 ;
+ END
+ END la_data_out[30]
+ PIN la_data_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 365.330 0.000 365.610 4.000 ;
+ END
+ END la_data_out[31]
+ PIN la_data_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 370.850 0.000 371.130 4.000 ;
+ END
+ END la_data_out[32]
+ PIN la_data_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 376.370 0.000 376.650 4.000 ;
+ END
+ END la_data_out[33]
+ PIN la_data_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 381.890 0.000 382.170 4.000 ;
+ END
+ END la_data_out[34]
+ PIN la_data_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 387.410 0.000 387.690 4.000 ;
+ END
+ END la_data_out[35]
+ PIN la_data_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 392.930 0.000 393.210 4.000 ;
+ END
+ END la_data_out[36]
+ PIN la_data_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 398.450 0.000 398.730 4.000 ;
+ END
+ END la_data_out[37]
+ PIN la_data_out[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 403.970 0.000 404.250 4.000 ;
+ END
+ END la_data_out[38]
+ PIN la_data_out[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 409.490 0.000 409.770 4.000 ;
+ END
+ END la_data_out[39]
+ PIN la_data_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 212.150 0.000 212.430 4.000 ;
+ END
+ END la_data_out[3]
+ PIN la_data_out[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 415.010 0.000 415.290 4.000 ;
+ END
+ END la_data_out[40]
+ PIN la_data_out[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 420.530 0.000 420.810 4.000 ;
+ END
+ END la_data_out[41]
+ PIN la_data_out[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 425.590 0.000 425.870 4.000 ;
+ END
+ END la_data_out[42]
+ PIN la_data_out[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 431.110 0.000 431.390 4.000 ;
+ END
+ END la_data_out[43]
+ PIN la_data_out[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 436.630 0.000 436.910 4.000 ;
+ END
+ END la_data_out[44]
+ PIN la_data_out[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 442.150 0.000 442.430 4.000 ;
+ END
+ END la_data_out[45]
+ PIN la_data_out[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 447.670 0.000 447.950 4.000 ;
+ END
+ END la_data_out[46]
+ PIN la_data_out[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 453.190 0.000 453.470 4.000 ;
+ END
+ END la_data_out[47]
+ PIN la_data_out[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 458.710 0.000 458.990 4.000 ;
+ END
+ END la_data_out[48]
+ PIN la_data_out[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 464.230 0.000 464.510 4.000 ;
+ END
+ END la_data_out[49]
+ PIN la_data_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 217.670 0.000 217.950 4.000 ;
+ END
+ END la_data_out[4]
+ PIN la_data_out[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.750 0.000 470.030 4.000 ;
+ END
+ END la_data_out[50]
+ PIN la_data_out[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 475.270 0.000 475.550 4.000 ;
+ END
+ END la_data_out[51]
+ PIN la_data_out[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 480.330 0.000 480.610 4.000 ;
+ END
+ END la_data_out[52]
+ PIN la_data_out[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.850 0.000 486.130 4.000 ;
+ END
+ END la_data_out[53]
+ PIN la_data_out[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 491.370 0.000 491.650 4.000 ;
+ END
+ END la_data_out[54]
+ PIN la_data_out[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 496.890 0.000 497.170 4.000 ;
+ END
+ END la_data_out[55]
+ PIN la_data_out[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 502.410 0.000 502.690 4.000 ;
+ END
+ END la_data_out[56]
+ PIN la_data_out[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 507.930 0.000 508.210 4.000 ;
+ END
+ END la_data_out[57]
+ PIN la_data_out[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 513.450 0.000 513.730 4.000 ;
+ END
+ END la_data_out[58]
+ PIN la_data_out[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 518.970 0.000 519.250 4.000 ;
+ END
+ END la_data_out[59]
+ PIN la_data_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 223.190 0.000 223.470 4.000 ;
+ END
+ END la_data_out[5]
+ PIN la_data_out[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 524.490 0.000 524.770 4.000 ;
+ END
+ END la_data_out[60]
+ PIN la_data_out[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 530.010 0.000 530.290 4.000 ;
+ END
+ END la_data_out[61]
+ PIN la_data_out[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 535.530 0.000 535.810 4.000 ;
+ END
+ END la_data_out[62]
+ PIN la_data_out[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 540.590 0.000 540.870 4.000 ;
+ END
+ END la_data_out[63]
+ PIN la_data_out[64]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 546.110 0.000 546.390 4.000 ;
+ END
+ END la_data_out[64]
+ PIN la_data_out[65]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 551.630 0.000 551.910 4.000 ;
+ END
+ END la_data_out[65]
+ PIN la_data_out[66]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 557.150 0.000 557.430 4.000 ;
+ END
+ END la_data_out[66]
+ PIN la_data_out[67]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 562.670 0.000 562.950 4.000 ;
+ END
+ END la_data_out[67]
+ PIN la_data_out[68]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 568.190 0.000 568.470 4.000 ;
+ END
+ END la_data_out[68]
+ PIN la_data_out[69]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 573.710 0.000 573.990 4.000 ;
+ END
+ END la_data_out[69]
+ PIN la_data_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 228.710 0.000 228.990 4.000 ;
+ END
+ END la_data_out[6]
+ PIN la_data_out[70]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 579.230 0.000 579.510 4.000 ;
+ END
+ END la_data_out[70]
+ PIN la_data_out[71]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 584.750 0.000 585.030 4.000 ;
+ END
+ END la_data_out[71]
+ PIN la_data_out[72]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 590.270 0.000 590.550 4.000 ;
+ END
+ END la_data_out[72]
+ PIN la_data_out[73]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 595.790 0.000 596.070 4.000 ;
+ END
+ END la_data_out[73]
+ PIN la_data_out[74]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 600.850 0.000 601.130 4.000 ;
+ END
+ END la_data_out[74]
+ PIN la_data_out[75]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 606.370 0.000 606.650 4.000 ;
+ END
+ END la_data_out[75]
+ PIN la_data_out[76]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 611.890 0.000 612.170 4.000 ;
+ END
+ END la_data_out[76]
+ PIN la_data_out[77]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 617.410 0.000 617.690 4.000 ;
+ END
+ END la_data_out[77]
+ PIN la_data_out[78]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 622.930 0.000 623.210 4.000 ;
+ END
+ END la_data_out[78]
+ PIN la_data_out[79]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 628.450 0.000 628.730 4.000 ;
+ END
+ END la_data_out[79]
+ PIN la_data_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 234.230 0.000 234.510 4.000 ;
+ END
+ END la_data_out[7]
+ PIN la_data_out[80]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 633.970 0.000 634.250 4.000 ;
+ END
+ END la_data_out[80]
+ PIN la_data_out[81]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 639.490 0.000 639.770 4.000 ;
+ END
+ END la_data_out[81]
+ PIN la_data_out[82]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 645.010 0.000 645.290 4.000 ;
+ END
+ END la_data_out[82]
+ PIN la_data_out[83]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 650.530 0.000 650.810 4.000 ;
+ END
+ END la_data_out[83]
+ PIN la_data_out[84]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 656.050 0.000 656.330 4.000 ;
+ END
+ END la_data_out[84]
+ PIN la_data_out[85]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 661.110 0.000 661.390 4.000 ;
+ END
+ END la_data_out[85]
+ PIN la_data_out[86]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 666.630 0.000 666.910 4.000 ;
+ END
+ END la_data_out[86]
+ PIN la_data_out[87]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 672.150 0.000 672.430 4.000 ;
+ END
+ END la_data_out[87]
+ PIN la_data_out[88]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 677.670 0.000 677.950 4.000 ;
+ END
+ END la_data_out[88]
+ PIN la_data_out[89]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 683.190 0.000 683.470 4.000 ;
+ END
+ END la_data_out[89]
+ PIN la_data_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 239.750 0.000 240.030 4.000 ;
+ END
+ END la_data_out[8]
+ PIN la_data_out[90]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 688.710 0.000 688.990 4.000 ;
+ END
+ END la_data_out[90]
+ PIN la_data_out[91]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 694.230 0.000 694.510 4.000 ;
+ END
+ END la_data_out[91]
+ PIN la_data_out[92]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 699.750 0.000 700.030 4.000 ;
+ END
+ END la_data_out[92]
+ PIN la_data_out[93]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 705.270 0.000 705.550 4.000 ;
+ END
+ END la_data_out[93]
+ PIN la_data_out[94]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 710.790 0.000 711.070 4.000 ;
+ END
+ END la_data_out[94]
+ PIN la_data_out[95]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 716.310 0.000 716.590 4.000 ;
+ END
+ END la_data_out[95]
+ PIN la_data_out[96]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 721.370 0.000 721.650 4.000 ;
+ END
+ END la_data_out[96]
+ PIN la_data_out[97]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 726.890 0.000 727.170 4.000 ;
+ END
+ END la_data_out[97]
+ PIN la_data_out[98]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 732.410 0.000 732.690 4.000 ;
+ END
+ END la_data_out[98]
+ PIN la_data_out[99]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 737.930 0.000 738.210 4.000 ;
+ END
+ END la_data_out[99]
+ PIN la_data_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 244.810 0.000 245.090 4.000 ;
+ END
+ END la_data_out[9]
+ PIN la_oenb[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 197.430 0.000 197.710 4.000 ;
+ END
+ END la_oenb[0]
+ PIN la_oenb[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 745.290 0.000 745.570 4.000 ;
+ END
+ END la_oenb[100]
+ PIN la_oenb[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 750.810 0.000 751.090 4.000 ;
+ END
+ END la_oenb[101]
+ PIN la_oenb[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 756.330 0.000 756.610 4.000 ;
+ END
+ END la_oenb[102]
+ PIN la_oenb[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 761.850 0.000 762.130 4.000 ;
+ END
+ END la_oenb[103]
+ PIN la_oenb[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 767.370 0.000 767.650 4.000 ;
+ END
+ END la_oenb[104]
+ PIN la_oenb[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 772.890 0.000 773.170 4.000 ;
+ END
+ END la_oenb[105]
+ PIN la_oenb[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 778.410 0.000 778.690 4.000 ;
+ END
+ END la_oenb[106]
+ PIN la_oenb[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 783.470 0.000 783.750 4.000 ;
+ END
+ END la_oenb[107]
+ PIN la_oenb[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 788.990 0.000 789.270 4.000 ;
+ END
+ END la_oenb[108]
+ PIN la_oenb[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 794.510 0.000 794.790 4.000 ;
+ END
+ END la_oenb[109]
+ PIN la_oenb[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 252.170 0.000 252.450 4.000 ;
+ END
+ END la_oenb[10]
+ PIN la_oenb[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 800.030 0.000 800.310 4.000 ;
+ END
+ END la_oenb[110]
+ PIN la_oenb[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 805.550 0.000 805.830 4.000 ;
+ END
+ END la_oenb[111]
+ PIN la_oenb[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 811.070 0.000 811.350 4.000 ;
+ END
+ END la_oenb[112]
+ PIN la_oenb[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 816.590 0.000 816.870 4.000 ;
+ END
+ END la_oenb[113]
+ PIN la_oenb[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 822.110 0.000 822.390 4.000 ;
+ END
+ END la_oenb[114]
+ PIN la_oenb[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 827.630 0.000 827.910 4.000 ;
+ END
+ END la_oenb[115]
+ PIN la_oenb[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 833.150 0.000 833.430 4.000 ;
+ END
+ END la_oenb[116]
+ PIN la_oenb[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 838.670 0.000 838.950 4.000 ;
+ END
+ END la_oenb[117]
+ PIN la_oenb[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 843.730 0.000 844.010 4.000 ;
+ END
+ END la_oenb[118]
+ PIN la_oenb[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 849.250 0.000 849.530 4.000 ;
+ END
+ END la_oenb[119]
+ PIN la_oenb[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 257.690 0.000 257.970 4.000 ;
+ END
+ END la_oenb[11]
+ PIN la_oenb[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 854.770 0.000 855.050 4.000 ;
+ END
+ END la_oenb[120]
+ PIN la_oenb[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 860.290 0.000 860.570 4.000 ;
+ END
+ END la_oenb[121]
+ PIN la_oenb[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 865.810 0.000 866.090 4.000 ;
+ END
+ END la_oenb[122]
+ PIN la_oenb[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 871.330 0.000 871.610 4.000 ;
+ END
+ END la_oenb[123]
+ PIN la_oenb[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 876.850 0.000 877.130 4.000 ;
+ END
+ END la_oenb[124]
+ PIN la_oenb[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 882.370 0.000 882.650 4.000 ;
+ END
+ END la_oenb[125]
+ PIN la_oenb[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 887.890 0.000 888.170 4.000 ;
+ END
+ END la_oenb[126]
+ PIN la_oenb[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 893.410 0.000 893.690 4.000 ;
+ END
+ END la_oenb[127]
+ PIN la_oenb[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 263.210 0.000 263.490 4.000 ;
+ END
+ END la_oenb[12]
+ PIN la_oenb[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 268.730 0.000 269.010 4.000 ;
+ END
+ END la_oenb[13]
+ PIN la_oenb[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 274.250 0.000 274.530 4.000 ;
+ END
+ END la_oenb[14]
+ PIN la_oenb[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 279.770 0.000 280.050 4.000 ;
+ END
+ END la_oenb[15]
+ PIN la_oenb[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 285.290 0.000 285.570 4.000 ;
+ END
+ END la_oenb[16]
+ PIN la_oenb[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 290.810 0.000 291.090 4.000 ;
+ END
+ END la_oenb[17]
+ PIN la_oenb[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 296.330 0.000 296.610 4.000 ;
+ END
+ END la_oenb[18]
+ PIN la_oenb[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 301.390 0.000 301.670 4.000 ;
+ END
+ END la_oenb[19]
+ PIN la_oenb[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.950 0.000 203.230 4.000 ;
+ END
+ END la_oenb[1]
+ PIN la_oenb[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 306.910 0.000 307.190 4.000 ;
+ END
+ END la_oenb[20]
+ PIN la_oenb[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 312.430 0.000 312.710 4.000 ;
+ END
+ END la_oenb[21]
+ PIN la_oenb[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 317.950 0.000 318.230 4.000 ;
+ END
+ END la_oenb[22]
+ PIN la_oenb[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 323.470 0.000 323.750 4.000 ;
+ END
+ END la_oenb[23]
+ PIN la_oenb[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 328.990 0.000 329.270 4.000 ;
+ END
+ END la_oenb[24]
+ PIN la_oenb[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 334.510 0.000 334.790 4.000 ;
+ END
+ END la_oenb[25]
+ PIN la_oenb[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 340.030 0.000 340.310 4.000 ;
+ END
+ END la_oenb[26]
+ PIN la_oenb[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.550 0.000 345.830 4.000 ;
+ END
+ END la_oenb[27]
+ PIN la_oenb[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.070 0.000 351.350 4.000 ;
+ END
+ END la_oenb[28]
+ PIN la_oenb[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 356.590 0.000 356.870 4.000 ;
+ END
+ END la_oenb[29]
+ PIN la_oenb[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 208.470 0.000 208.750 4.000 ;
+ END
+ END la_oenb[2]
+ PIN la_oenb[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 361.650 0.000 361.930 4.000 ;
+ END
+ END la_oenb[30]
+ PIN la_oenb[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 367.170 0.000 367.450 4.000 ;
+ END
+ END la_oenb[31]
+ PIN la_oenb[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 372.690 0.000 372.970 4.000 ;
+ END
+ END la_oenb[32]
+ PIN la_oenb[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 378.210 0.000 378.490 4.000 ;
+ END
+ END la_oenb[33]
+ PIN la_oenb[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 383.730 0.000 384.010 4.000 ;
+ END
+ END la_oenb[34]
+ PIN la_oenb[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 389.250 0.000 389.530 4.000 ;
+ END
+ END la_oenb[35]
+ PIN la_oenb[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 394.770 0.000 395.050 4.000 ;
+ END
+ END la_oenb[36]
+ PIN la_oenb[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 400.290 0.000 400.570 4.000 ;
+ END
+ END la_oenb[37]
+ PIN la_oenb[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 405.810 0.000 406.090 4.000 ;
+ END
+ END la_oenb[38]
+ PIN la_oenb[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 411.330 0.000 411.610 4.000 ;
+ END
+ END la_oenb[39]
+ PIN la_oenb[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 213.990 0.000 214.270 4.000 ;
+ END
+ END la_oenb[3]
+ PIN la_oenb[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.850 0.000 417.130 4.000 ;
+ END
+ END la_oenb[40]
+ PIN la_oenb[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 421.910 0.000 422.190 4.000 ;
+ END
+ END la_oenb[41]
+ PIN la_oenb[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 427.430 0.000 427.710 4.000 ;
+ END
+ END la_oenb[42]
+ PIN la_oenb[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 432.950 0.000 433.230 4.000 ;
+ END
+ END la_oenb[43]
+ PIN la_oenb[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 438.470 0.000 438.750 4.000 ;
+ END
+ END la_oenb[44]
+ PIN la_oenb[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 443.990 0.000 444.270 4.000 ;
+ END
+ END la_oenb[45]
+ PIN la_oenb[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 449.510 0.000 449.790 4.000 ;
+ END
+ END la_oenb[46]
+ PIN la_oenb[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 455.030 0.000 455.310 4.000 ;
+ END
+ END la_oenb[47]
+ PIN la_oenb[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 460.550 0.000 460.830 4.000 ;
+ END
+ END la_oenb[48]
+ PIN la_oenb[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 466.070 0.000 466.350 4.000 ;
+ END
+ END la_oenb[49]
+ PIN la_oenb[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 219.510 0.000 219.790 4.000 ;
+ END
+ END la_oenb[4]
+ PIN la_oenb[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 471.590 0.000 471.870 4.000 ;
+ END
+ END la_oenb[50]
+ PIN la_oenb[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 477.110 0.000 477.390 4.000 ;
+ END
+ END la_oenb[51]
+ PIN la_oenb[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 482.170 0.000 482.450 4.000 ;
+ END
+ END la_oenb[52]
+ PIN la_oenb[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 487.690 0.000 487.970 4.000 ;
+ END
+ END la_oenb[53]
+ PIN la_oenb[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 493.210 0.000 493.490 4.000 ;
+ END
+ END la_oenb[54]
+ PIN la_oenb[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 498.730 0.000 499.010 4.000 ;
+ END
+ END la_oenb[55]
+ PIN la_oenb[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 504.250 0.000 504.530 4.000 ;
+ END
+ END la_oenb[56]
+ PIN la_oenb[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 509.770 0.000 510.050 4.000 ;
+ END
+ END la_oenb[57]
+ PIN la_oenb[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 515.290 0.000 515.570 4.000 ;
+ END
+ END la_oenb[58]
+ PIN la_oenb[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 520.810 0.000 521.090 4.000 ;
+ END
+ END la_oenb[59]
+ PIN la_oenb[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 225.030 0.000 225.310 4.000 ;
+ END
+ END la_oenb[5]
+ PIN la_oenb[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 526.330 0.000 526.610 4.000 ;
+ END
+ END la_oenb[60]
+ PIN la_oenb[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 531.850 0.000 532.130 4.000 ;
+ END
+ END la_oenb[61]
+ PIN la_oenb[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 537.370 0.000 537.650 4.000 ;
+ END
+ END la_oenb[62]
+ PIN la_oenb[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 542.430 0.000 542.710 4.000 ;
+ END
+ END la_oenb[63]
+ PIN la_oenb[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 547.950 0.000 548.230 4.000 ;
+ END
+ END la_oenb[64]
+ PIN la_oenb[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 553.470 0.000 553.750 4.000 ;
+ END
+ END la_oenb[65]
+ PIN la_oenb[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 558.990 0.000 559.270 4.000 ;
+ END
+ END la_oenb[66]
+ PIN la_oenb[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 564.510 0.000 564.790 4.000 ;
+ END
+ END la_oenb[67]
+ PIN la_oenb[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 570.030 0.000 570.310 4.000 ;
+ END
+ END la_oenb[68]
+ PIN la_oenb[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 575.550 0.000 575.830 4.000 ;
+ END
+ END la_oenb[69]
+ PIN la_oenb[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 230.550 0.000 230.830 4.000 ;
+ END
+ END la_oenb[6]
+ PIN la_oenb[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 581.070 0.000 581.350 4.000 ;
+ END
+ END la_oenb[70]
+ PIN la_oenb[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 586.590 0.000 586.870 4.000 ;
+ END
+ END la_oenb[71]
+ PIN la_oenb[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 592.110 0.000 592.390 4.000 ;
+ END
+ END la_oenb[72]
+ PIN la_oenb[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 597.630 0.000 597.910 4.000 ;
+ END
+ END la_oenb[73]
+ PIN la_oenb[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 602.690 0.000 602.970 4.000 ;
+ END
+ END la_oenb[74]
+ PIN la_oenb[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 608.210 0.000 608.490 4.000 ;
+ END
+ END la_oenb[75]
+ PIN la_oenb[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 613.730 0.000 614.010 4.000 ;
+ END
+ END la_oenb[76]
+ PIN la_oenb[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 619.250 0.000 619.530 4.000 ;
+ END
+ END la_oenb[77]
+ PIN la_oenb[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 624.770 0.000 625.050 4.000 ;
+ END
+ END la_oenb[78]
+ PIN la_oenb[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 630.290 0.000 630.570 4.000 ;
+ END
+ END la_oenb[79]
+ PIN la_oenb[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 236.070 0.000 236.350 4.000 ;
+ END
+ END la_oenb[7]
+ PIN la_oenb[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 635.810 0.000 636.090 4.000 ;
+ END
+ END la_oenb[80]
+ PIN la_oenb[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 641.330 0.000 641.610 4.000 ;
+ END
+ END la_oenb[81]
+ PIN la_oenb[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 646.850 0.000 647.130 4.000 ;
+ END
+ END la_oenb[82]
+ PIN la_oenb[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 652.370 0.000 652.650 4.000 ;
+ END
+ END la_oenb[83]
+ PIN la_oenb[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 657.890 0.000 658.170 4.000 ;
+ END
+ END la_oenb[84]
+ PIN la_oenb[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 662.950 0.000 663.230 4.000 ;
+ END
+ END la_oenb[85]
+ PIN la_oenb[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 668.470 0.000 668.750 4.000 ;
+ END
+ END la_oenb[86]
+ PIN la_oenb[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 673.990 0.000 674.270 4.000 ;
+ END
+ END la_oenb[87]
+ PIN la_oenb[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 679.510 0.000 679.790 4.000 ;
+ END
+ END la_oenb[88]
+ PIN la_oenb[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 685.030 0.000 685.310 4.000 ;
+ END
+ END la_oenb[89]
+ PIN la_oenb[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 241.130 0.000 241.410 4.000 ;
+ END
+ END la_oenb[8]
+ PIN la_oenb[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 690.550 0.000 690.830 4.000 ;
+ END
+ END la_oenb[90]
+ PIN la_oenb[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 696.070 0.000 696.350 4.000 ;
+ END
+ END la_oenb[91]
+ PIN la_oenb[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 701.590 0.000 701.870 4.000 ;
+ END
+ END la_oenb[92]
+ PIN la_oenb[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 707.110 0.000 707.390 4.000 ;
+ END
+ END la_oenb[93]
+ PIN la_oenb[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 712.630 0.000 712.910 4.000 ;
+ END
+ END la_oenb[94]
+ PIN la_oenb[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 718.150 0.000 718.430 4.000 ;
+ END
+ END la_oenb[95]
+ PIN la_oenb[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 723.210 0.000 723.490 4.000 ;
+ END
+ END la_oenb[96]
+ PIN la_oenb[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 728.730 0.000 729.010 4.000 ;
+ END
+ END la_oenb[97]
+ PIN la_oenb[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 734.250 0.000 734.530 4.000 ;
+ END
+ END la_oenb[98]
+ PIN la_oenb[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 739.770 0.000 740.050 4.000 ;
+ END
+ END la_oenb[99]
+ PIN la_oenb[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 246.650 0.000 246.930 4.000 ;
+ END
+ END la_oenb[9]
+ PIN vccd2
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 21.040 10.640 22.640 587.760 ;
+ END
+ END vccd2
+ PIN vssd2
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 97.840 10.640 99.440 587.760 ;
+ END
+ END vssd2
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 0.550 0.000 0.830 4.000 ;
+ END
+ END wb_clk_i
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1.930 0.000 2.210 4.000 ;
+ END
+ END wb_rst_i
+ PIN wbs_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 3.770 0.000 4.050 4.000 ;
+ END
+ END wbs_ack_o
+ PIN wbs_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 11.130 0.000 11.410 4.000 ;
+ END
+ END wbs_adr_i[0]
+ PIN wbs_adr_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 73.230 0.000 73.510 4.000 ;
+ END
+ END wbs_adr_i[10]
+ PIN wbs_adr_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 78.750 0.000 79.030 4.000 ;
+ END
+ END wbs_adr_i[11]
+ PIN wbs_adr_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 84.270 0.000 84.550 4.000 ;
+ END
+ END wbs_adr_i[12]
+ PIN wbs_adr_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 89.790 0.000 90.070 4.000 ;
+ END
+ END wbs_adr_i[13]
+ PIN wbs_adr_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 95.310 0.000 95.590 4.000 ;
+ END
+ END wbs_adr_i[14]
+ PIN wbs_adr_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 100.830 0.000 101.110 4.000 ;
+ END
+ END wbs_adr_i[15]
+ PIN wbs_adr_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 106.350 0.000 106.630 4.000 ;
+ END
+ END wbs_adr_i[16]
+ PIN wbs_adr_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 111.870 0.000 112.150 4.000 ;
+ END
+ END wbs_adr_i[17]
+ PIN wbs_adr_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 117.390 0.000 117.670 4.000 ;
+ END
+ END wbs_adr_i[18]
+ PIN wbs_adr_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 122.450 0.000 122.730 4.000 ;
+ END
+ END wbs_adr_i[19]
+ PIN wbs_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 18.490 0.000 18.770 4.000 ;
+ END
+ END wbs_adr_i[1]
+ PIN wbs_adr_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 127.970 0.000 128.250 4.000 ;
+ END
+ END wbs_adr_i[20]
+ PIN wbs_adr_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 133.490 0.000 133.770 4.000 ;
+ END
+ END wbs_adr_i[21]
+ PIN wbs_adr_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 139.010 0.000 139.290 4.000 ;
+ END
+ END wbs_adr_i[22]
+ PIN wbs_adr_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 144.530 0.000 144.810 4.000 ;
+ END
+ END wbs_adr_i[23]
+ PIN wbs_adr_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 150.050 0.000 150.330 4.000 ;
+ END
+ END wbs_adr_i[24]
+ PIN wbs_adr_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 155.570 0.000 155.850 4.000 ;
+ END
+ END wbs_adr_i[25]
+ PIN wbs_adr_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.090 0.000 161.370 4.000 ;
+ END
+ END wbs_adr_i[26]
+ PIN wbs_adr_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 166.610 0.000 166.890 4.000 ;
+ END
+ END wbs_adr_i[27]
+ PIN wbs_adr_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 172.130 0.000 172.410 4.000 ;
+ END
+ END wbs_adr_i[28]
+ PIN wbs_adr_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 177.650 0.000 177.930 4.000 ;
+ END
+ END wbs_adr_i[29]
+ PIN wbs_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 25.850 0.000 26.130 4.000 ;
+ END
+ END wbs_adr_i[2]
+ PIN wbs_adr_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 182.710 0.000 182.990 4.000 ;
+ END
+ END wbs_adr_i[30]
+ PIN wbs_adr_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 188.230 0.000 188.510 4.000 ;
+ END
+ END wbs_adr_i[31]
+ PIN wbs_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 33.210 0.000 33.490 4.000 ;
+ END
+ END wbs_adr_i[3]
+ PIN wbs_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 40.570 0.000 40.850 4.000 ;
+ END
+ END wbs_adr_i[4]
+ PIN wbs_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 46.090 0.000 46.370 4.000 ;
+ END
+ END wbs_adr_i[5]
+ PIN wbs_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 51.610 0.000 51.890 4.000 ;
+ END
+ END wbs_adr_i[6]
+ PIN wbs_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 57.130 0.000 57.410 4.000 ;
+ END
+ END wbs_adr_i[7]
+ PIN wbs_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 62.190 0.000 62.470 4.000 ;
+ END
+ END wbs_adr_i[8]
+ PIN wbs_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 67.710 0.000 67.990 4.000 ;
+ END
+ END wbs_adr_i[9]
+ PIN wbs_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 5.610 0.000 5.890 4.000 ;
+ END
+ END wbs_cyc_i
+ PIN wbs_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 12.970 0.000 13.250 4.000 ;
+ END
+ END wbs_dat_i[0]
+ PIN wbs_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 75.070 0.000 75.350 4.000 ;
+ END
+ END wbs_dat_i[10]
+ PIN wbs_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 80.590 0.000 80.870 4.000 ;
+ END
+ END wbs_dat_i[11]
+ PIN wbs_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 86.110 0.000 86.390 4.000 ;
+ END
+ END wbs_dat_i[12]
+ PIN wbs_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 91.630 0.000 91.910 4.000 ;
+ END
+ END wbs_dat_i[13]
+ PIN wbs_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 97.150 0.000 97.430 4.000 ;
+ END
+ END wbs_dat_i[14]
+ PIN wbs_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 102.670 0.000 102.950 4.000 ;
+ END
+ END wbs_dat_i[15]
+ PIN wbs_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 108.190 0.000 108.470 4.000 ;
+ END
+ END wbs_dat_i[16]
+ PIN wbs_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 113.710 0.000 113.990 4.000 ;
+ END
+ END wbs_dat_i[17]
+ PIN wbs_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 119.230 0.000 119.510 4.000 ;
+ END
+ END wbs_dat_i[18]
+ PIN wbs_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 124.290 0.000 124.570 4.000 ;
+ END
+ END wbs_dat_i[19]
+ PIN wbs_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 20.330 0.000 20.610 4.000 ;
+ END
+ END wbs_dat_i[1]
+ PIN wbs_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 129.810 0.000 130.090 4.000 ;
+ END
+ END wbs_dat_i[20]
+ PIN wbs_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 135.330 0.000 135.610 4.000 ;
+ END
+ END wbs_dat_i[21]
+ PIN wbs_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 140.850 0.000 141.130 4.000 ;
+ END
+ END wbs_dat_i[22]
+ PIN wbs_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 146.370 0.000 146.650 4.000 ;
+ END
+ END wbs_dat_i[23]
+ PIN wbs_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 151.890 0.000 152.170 4.000 ;
+ END
+ END wbs_dat_i[24]
+ PIN wbs_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 157.410 0.000 157.690 4.000 ;
+ END
+ END wbs_dat_i[25]
+ PIN wbs_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 162.930 0.000 163.210 4.000 ;
+ END
+ END wbs_dat_i[26]
+ PIN wbs_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 168.450 0.000 168.730 4.000 ;
+ END
+ END wbs_dat_i[27]
+ PIN wbs_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 173.970 0.000 174.250 4.000 ;
+ END
+ END wbs_dat_i[28]
+ PIN wbs_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 179.490 0.000 179.770 4.000 ;
+ END
+ END wbs_dat_i[29]
+ PIN wbs_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 27.690 0.000 27.970 4.000 ;
+ END
+ END wbs_dat_i[2]
+ PIN wbs_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 184.550 0.000 184.830 4.000 ;
+ END
+ END wbs_dat_i[30]
+ PIN wbs_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 190.070 0.000 190.350 4.000 ;
+ END
+ END wbs_dat_i[31]
+ PIN wbs_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 35.050 0.000 35.330 4.000 ;
+ END
+ END wbs_dat_i[3]
+ PIN wbs_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 42.410 0.000 42.690 4.000 ;
+ END
+ END wbs_dat_i[4]
+ PIN wbs_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 47.930 0.000 48.210 4.000 ;
+ END
+ END wbs_dat_i[5]
+ PIN wbs_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 53.450 0.000 53.730 4.000 ;
+ END
+ END wbs_dat_i[6]
+ PIN wbs_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 58.970 0.000 59.250 4.000 ;
+ END
+ END wbs_dat_i[7]
+ PIN wbs_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 64.030 0.000 64.310 4.000 ;
+ END
+ END wbs_dat_i[8]
+ PIN wbs_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 69.550 0.000 69.830 4.000 ;
+ END
+ END wbs_dat_i[9]
+ PIN wbs_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 14.810 0.000 15.090 4.000 ;
+ END
+ END wbs_dat_o[0]
+ PIN wbs_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 76.910 0.000 77.190 4.000 ;
+ END
+ END wbs_dat_o[10]
+ PIN wbs_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 82.430 0.000 82.710 4.000 ;
+ END
+ END wbs_dat_o[11]
+ PIN wbs_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 87.950 0.000 88.230 4.000 ;
+ END
+ END wbs_dat_o[12]
+ PIN wbs_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 93.470 0.000 93.750 4.000 ;
+ END
+ END wbs_dat_o[13]
+ PIN wbs_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 98.990 0.000 99.270 4.000 ;
+ END
+ END wbs_dat_o[14]
+ PIN wbs_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 104.510 0.000 104.790 4.000 ;
+ END
+ END wbs_dat_o[15]
+ PIN wbs_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 110.030 0.000 110.310 4.000 ;
+ END
+ END wbs_dat_o[16]
+ PIN wbs_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 115.550 0.000 115.830 4.000 ;
+ END
+ END wbs_dat_o[17]
+ PIN wbs_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 120.610 0.000 120.890 4.000 ;
+ END
+ END wbs_dat_o[18]
+ PIN wbs_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 126.130 0.000 126.410 4.000 ;
+ END
+ END wbs_dat_o[19]
+ PIN wbs_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 22.170 0.000 22.450 4.000 ;
+ END
+ END wbs_dat_o[1]
+ PIN wbs_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 131.650 0.000 131.930 4.000 ;
+ END
+ END wbs_dat_o[20]
+ PIN wbs_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 137.170 0.000 137.450 4.000 ;
+ END
+ END wbs_dat_o[21]
+ PIN wbs_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 142.690 0.000 142.970 4.000 ;
+ END
+ END wbs_dat_o[22]
+ PIN wbs_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 148.210 0.000 148.490 4.000 ;
+ END
+ END wbs_dat_o[23]
+ PIN wbs_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 153.730 0.000 154.010 4.000 ;
+ END
+ END wbs_dat_o[24]
+ PIN wbs_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 159.250 0.000 159.530 4.000 ;
+ END
+ END wbs_dat_o[25]
+ PIN wbs_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 164.770 0.000 165.050 4.000 ;
+ END
+ END wbs_dat_o[26]
+ PIN wbs_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 170.290 0.000 170.570 4.000 ;
+ END
+ END wbs_dat_o[27]
+ PIN wbs_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 175.810 0.000 176.090 4.000 ;
+ END
+ END wbs_dat_o[28]
+ PIN wbs_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 180.870 0.000 181.150 4.000 ;
+ END
+ END wbs_dat_o[29]
+ PIN wbs_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 29.530 0.000 29.810 4.000 ;
+ END
+ END wbs_dat_o[2]
+ PIN wbs_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 186.390 0.000 186.670 4.000 ;
+ END
+ END wbs_dat_o[30]
+ PIN wbs_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 191.910 0.000 192.190 4.000 ;
+ END
+ END wbs_dat_o[31]
+ PIN wbs_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 36.890 0.000 37.170 4.000 ;
+ END
+ END wbs_dat_o[3]
+ PIN wbs_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 44.250 0.000 44.530 4.000 ;
+ END
+ END wbs_dat_o[4]
+ PIN wbs_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 49.770 0.000 50.050 4.000 ;
+ END
+ END wbs_dat_o[5]
+ PIN wbs_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 55.290 0.000 55.570 4.000 ;
+ END
+ END wbs_dat_o[6]
+ PIN wbs_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 60.350 0.000 60.630 4.000 ;
+ END
+ END wbs_dat_o[7]
+ PIN wbs_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 65.870 0.000 66.150 4.000 ;
+ END
+ END wbs_dat_o[8]
+ PIN wbs_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 71.390 0.000 71.670 4.000 ;
+ END
+ END wbs_dat_o[9]
+ PIN wbs_sel_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 16.650 0.000 16.930 4.000 ;
+ END
+ END wbs_sel_i[0]
+ PIN wbs_sel_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 24.010 0.000 24.290 4.000 ;
+ END
+ END wbs_sel_i[1]
+ PIN wbs_sel_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 31.370 0.000 31.650 4.000 ;
+ END
+ END wbs_sel_i[2]
+ PIN wbs_sel_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 38.730 0.000 39.010 4.000 ;
+ END
+ END wbs_sel_i[3]
+ PIN wbs_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 7.450 0.000 7.730 4.000 ;
+ END
+ END wbs_stb_i
+ PIN wbs_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 9.290 0.000 9.570 4.000 ;
+ END
+ END wbs_we_i
+ OBS
+ LAYER li1 ;
+ RECT 5.520 6.885 894.240 587.605 ;
+ LAYER met1 ;
+ RECT 0.530 6.160 899.230 587.760 ;
+ LAYER met2 ;
+ RECT 0.560 595.720 3.490 596.090 ;
+ RECT 4.330 595.720 11.310 596.090 ;
+ RECT 12.150 595.720 19.130 596.090 ;
+ RECT 19.970 595.720 26.950 596.090 ;
+ RECT 27.790 595.720 34.770 596.090 ;
+ RECT 35.610 595.720 42.590 596.090 ;
+ RECT 43.430 595.720 50.870 596.090 ;
+ RECT 51.710 595.720 58.690 596.090 ;
+ RECT 59.530 595.720 66.510 596.090 ;
+ RECT 67.350 595.720 74.330 596.090 ;
+ RECT 75.170 595.720 82.150 596.090 ;
+ RECT 82.990 595.720 89.970 596.090 ;
+ RECT 90.810 595.720 98.250 596.090 ;
+ RECT 99.090 595.720 106.070 596.090 ;
+ RECT 106.910 595.720 113.890 596.090 ;
+ RECT 114.730 595.720 121.710 596.090 ;
+ RECT 122.550 595.720 129.530 596.090 ;
+ RECT 130.370 595.720 137.350 596.090 ;
+ RECT 138.190 595.720 145.630 596.090 ;
+ RECT 146.470 595.720 153.450 596.090 ;
+ RECT 154.290 595.720 161.270 596.090 ;
+ RECT 162.110 595.720 169.090 596.090 ;
+ RECT 169.930 595.720 176.910 596.090 ;
+ RECT 177.750 595.720 184.730 596.090 ;
+ RECT 185.570 595.720 193.010 596.090 ;
+ RECT 193.850 595.720 200.830 596.090 ;
+ RECT 201.670 595.720 208.650 596.090 ;
+ RECT 209.490 595.720 216.470 596.090 ;
+ RECT 217.310 595.720 224.290 596.090 ;
+ RECT 225.130 595.720 232.110 596.090 ;
+ RECT 232.950 595.720 240.390 596.090 ;
+ RECT 241.230 595.720 248.210 596.090 ;
+ RECT 249.050 595.720 256.030 596.090 ;
+ RECT 256.870 595.720 263.850 596.090 ;
+ RECT 264.690 595.720 271.670 596.090 ;
+ RECT 272.510 595.720 279.490 596.090 ;
+ RECT 280.330 595.720 287.770 596.090 ;
+ RECT 288.610 595.720 295.590 596.090 ;
+ RECT 296.430 595.720 303.410 596.090 ;
+ RECT 304.250 595.720 311.230 596.090 ;
+ RECT 312.070 595.720 319.050 596.090 ;
+ RECT 319.890 595.720 326.870 596.090 ;
+ RECT 327.710 595.720 335.150 596.090 ;
+ RECT 335.990 595.720 342.970 596.090 ;
+ RECT 343.810 595.720 350.790 596.090 ;
+ RECT 351.630 595.720 358.610 596.090 ;
+ RECT 359.450 595.720 366.430 596.090 ;
+ RECT 367.270 595.720 374.250 596.090 ;
+ RECT 375.090 595.720 382.530 596.090 ;
+ RECT 383.370 595.720 390.350 596.090 ;
+ RECT 391.190 595.720 398.170 596.090 ;
+ RECT 399.010 595.720 405.990 596.090 ;
+ RECT 406.830 595.720 413.810 596.090 ;
+ RECT 414.650 595.720 421.630 596.090 ;
+ RECT 422.470 595.720 429.910 596.090 ;
+ RECT 430.750 595.720 437.730 596.090 ;
+ RECT 438.570 595.720 445.550 596.090 ;
+ RECT 446.390 595.720 453.370 596.090 ;
+ RECT 454.210 595.720 461.190 596.090 ;
+ RECT 462.030 595.720 469.010 596.090 ;
+ RECT 469.850 595.720 477.290 596.090 ;
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+ RECT 556.790 595.720 563.770 596.090 ;
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+ RECT 580.710 595.720 587.690 596.090 ;
+ RECT 588.530 595.720 595.510 596.090 ;
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+ RECT 338.750 3.670 339.750 4.280 ;
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+ RECT 431.670 3.670 432.670 4.280 ;
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+ RECT 698.470 3.670 699.470 4.280 ;
+ RECT 700.310 3.670 701.310 4.280 ;
+ RECT 702.150 3.670 703.150 4.280 ;
+ RECT 703.990 3.670 704.990 4.280 ;
+ RECT 705.830 3.670 706.830 4.280 ;
+ RECT 707.670 3.670 708.670 4.280 ;
+ RECT 709.510 3.670 710.510 4.280 ;
+ RECT 711.350 3.670 712.350 4.280 ;
+ RECT 713.190 3.670 714.190 4.280 ;
+ RECT 715.030 3.670 716.030 4.280 ;
+ RECT 716.870 3.670 717.870 4.280 ;
+ RECT 718.710 3.670 719.710 4.280 ;
+ RECT 720.550 3.670 721.090 4.280 ;
+ RECT 721.930 3.670 722.930 4.280 ;
+ RECT 723.770 3.670 724.770 4.280 ;
+ RECT 725.610 3.670 726.610 4.280 ;
+ RECT 727.450 3.670 728.450 4.280 ;
+ RECT 729.290 3.670 730.290 4.280 ;
+ RECT 731.130 3.670 732.130 4.280 ;
+ RECT 732.970 3.670 733.970 4.280 ;
+ RECT 734.810 3.670 735.810 4.280 ;
+ RECT 736.650 3.670 737.650 4.280 ;
+ RECT 738.490 3.670 739.490 4.280 ;
+ RECT 740.330 3.670 741.330 4.280 ;
+ RECT 742.170 3.670 743.170 4.280 ;
+ RECT 744.010 3.670 745.010 4.280 ;
+ RECT 745.850 3.670 746.850 4.280 ;
+ RECT 747.690 3.670 748.690 4.280 ;
+ RECT 749.530 3.670 750.530 4.280 ;
+ RECT 751.370 3.670 752.370 4.280 ;
+ RECT 753.210 3.670 754.210 4.280 ;
+ RECT 755.050 3.670 756.050 4.280 ;
+ RECT 756.890 3.670 757.890 4.280 ;
+ RECT 758.730 3.670 759.730 4.280 ;
+ RECT 760.570 3.670 761.570 4.280 ;
+ RECT 762.410 3.670 763.410 4.280 ;
+ RECT 764.250 3.670 765.250 4.280 ;
+ RECT 766.090 3.670 767.090 4.280 ;
+ RECT 767.930 3.670 768.930 4.280 ;
+ RECT 769.770 3.670 770.770 4.280 ;
+ RECT 771.610 3.670 772.610 4.280 ;
+ RECT 773.450 3.670 774.450 4.280 ;
+ RECT 775.290 3.670 776.290 4.280 ;
+ RECT 777.130 3.670 778.130 4.280 ;
+ RECT 778.970 3.670 779.970 4.280 ;
+ RECT 780.810 3.670 781.350 4.280 ;
+ RECT 782.190 3.670 783.190 4.280 ;
+ RECT 784.030 3.670 785.030 4.280 ;
+ RECT 785.870 3.670 786.870 4.280 ;
+ RECT 787.710 3.670 788.710 4.280 ;
+ RECT 789.550 3.670 790.550 4.280 ;
+ RECT 791.390 3.670 792.390 4.280 ;
+ RECT 793.230 3.670 794.230 4.280 ;
+ RECT 795.070 3.670 796.070 4.280 ;
+ RECT 796.910 3.670 797.910 4.280 ;
+ RECT 798.750 3.670 799.750 4.280 ;
+ RECT 800.590 3.670 801.590 4.280 ;
+ RECT 802.430 3.670 803.430 4.280 ;
+ RECT 804.270 3.670 805.270 4.280 ;
+ RECT 806.110 3.670 807.110 4.280 ;
+ RECT 807.950 3.670 808.950 4.280 ;
+ RECT 809.790 3.670 810.790 4.280 ;
+ RECT 811.630 3.670 812.630 4.280 ;
+ RECT 813.470 3.670 814.470 4.280 ;
+ RECT 815.310 3.670 816.310 4.280 ;
+ RECT 817.150 3.670 818.150 4.280 ;
+ RECT 818.990 3.670 819.990 4.280 ;
+ RECT 820.830 3.670 821.830 4.280 ;
+ RECT 822.670 3.670 823.670 4.280 ;
+ RECT 824.510 3.670 825.510 4.280 ;
+ RECT 826.350 3.670 827.350 4.280 ;
+ RECT 828.190 3.670 829.190 4.280 ;
+ RECT 830.030 3.670 831.030 4.280 ;
+ RECT 831.870 3.670 832.870 4.280 ;
+ RECT 833.710 3.670 834.710 4.280 ;
+ RECT 835.550 3.670 836.550 4.280 ;
+ RECT 837.390 3.670 838.390 4.280 ;
+ RECT 839.230 3.670 840.230 4.280 ;
+ RECT 841.070 3.670 841.610 4.280 ;
+ RECT 842.450 3.670 843.450 4.280 ;
+ RECT 844.290 3.670 845.290 4.280 ;
+ RECT 846.130 3.670 847.130 4.280 ;
+ RECT 847.970 3.670 848.970 4.280 ;
+ RECT 849.810 3.670 850.810 4.280 ;
+ RECT 851.650 3.670 852.650 4.280 ;
+ RECT 853.490 3.670 854.490 4.280 ;
+ RECT 855.330 3.670 856.330 4.280 ;
+ RECT 857.170 3.670 858.170 4.280 ;
+ RECT 859.010 3.670 860.010 4.280 ;
+ RECT 860.850 3.670 861.850 4.280 ;
+ RECT 862.690 3.670 863.690 4.280 ;
+ RECT 864.530 3.670 865.530 4.280 ;
+ RECT 866.370 3.670 867.370 4.280 ;
+ RECT 868.210 3.670 869.210 4.280 ;
+ RECT 870.050 3.670 871.050 4.280 ;
+ RECT 871.890 3.670 872.890 4.280 ;
+ RECT 873.730 3.670 874.730 4.280 ;
+ RECT 875.570 3.670 876.570 4.280 ;
+ RECT 877.410 3.670 878.410 4.280 ;
+ RECT 879.250 3.670 880.250 4.280 ;
+ RECT 881.090 3.670 882.090 4.280 ;
+ RECT 882.930 3.670 883.930 4.280 ;
+ RECT 884.770 3.670 885.770 4.280 ;
+ RECT 886.610 3.670 887.610 4.280 ;
+ RECT 888.450 3.670 889.450 4.280 ;
+ RECT 890.290 3.670 891.290 4.280 ;
+ RECT 892.130 3.670 893.130 4.280 ;
+ RECT 893.970 3.670 894.970 4.280 ;
+ RECT 895.810 3.670 896.810 4.280 ;
+ RECT 897.650 3.670 898.650 4.280 ;
+ LAYER met3 ;
+ RECT 8.345 9.015 867.440 587.685 ;
+ LAYER met4 ;
+ RECT 174.640 9.015 867.440 587.760 ;
+ END
+END user_proj_example2
+END LIBRARY
+
diff --git a/openlane/designs/caravel_upw/pin_order.cfg b/openlane/designs/caravel_upw/pin_order.cfg
new file mode 100644
index 0000000..90cde69
--- /dev/null
+++ b/openlane/designs/caravel_upw/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/openlane/designs/caravel_upw/src/defines.v b/openlane/designs/caravel_upw/src/defines.v
new file mode 100644
index 0000000..6213b6c
--- /dev/null
+++ b/openlane/designs/caravel_upw/src/defines.v
@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __GLOBAL_DEFINE_H
+// Global parameters
+`define __GLOBAL_DEFINE_H
+
+`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
+`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
+`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
+
+`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
+`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
+`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
+
+// Analog pads are only used by the "caravan" module and associated
+// modules such as user_analog_project_wrapper and chip_io_alt.
+
+`define ANALOG_PADS_1 5
+`define ANALOG_PADS_2 6
+
+`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
+
+// Size of soc_mem_synth
+
+// Type and size of soc_mem
+// `define USE_OPENRAM
+`define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
+`define MEM_WORDS 256
+
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define DFFRAM_WSIZE 4
+`define DFFRAM_USE_LATCH 0
+
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 1
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
+
+// GPIO control default mode and enable for most I/Os
+// Most I/Os set to be user input pins on startup.
+// NOTE: To be modified, with GPIOs 5 to 35 being set from a build-time-
+// programmable block.
+`define MGMT_INIT 1'b0
+`define OENB_INIT 1'b0
+`define DM_INIT 3'b001
+
+`endif // __GLOBAL_DEFINE_H
diff --git a/openlane/designs/caravel_upw/src/user_proj_example.v b/openlane/designs/caravel_upw/src/user_proj_example.v
new file mode 100644
index 0000000..26081e9
--- /dev/null
+++ b/openlane/designs/caravel_upw/src/user_proj_example.v
@@ -0,0 +1,165 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only). The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project. The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire clk;
+ wire rst;
+
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+ wire [31:0] rdata;
+ wire [31:0] wdata;
+ wire [BITS-1:0] count;
+
+ wire valid;
+ wire [3:0] wstrb;
+ wire [31:0] la_write;
+
+ // WB MI A
+ assign valid = wbs_cyc_i && wbs_stb_i;
+ assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ assign wbs_dat_o = rdata;
+ assign wdata = wbs_dat_i;
+
+ // IO
+ assign io_out = count;
+ assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA
+ assign la_data_out = {{(127-BITS){1'b0}}, count};
+ // Assuming LA probes [63:32] are for controlling the count register
+ assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+ assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+
+ counter #(
+ .BITS(BITS)
+ ) counter(
+ .clk(clk),
+ .reset(rst),
+ .ready(wbs_ack_o),
+ .valid(valid),
+ .rdata(rdata),
+ .wdata(wbs_dat_i),
+ .wstrb(wstrb),
+ .la_write(la_write),
+ .la_input(la_data_in[63:32]),
+ .count(count)
+ );
+
+endmodule
+
+module counter #(
+ parameter BITS = 32
+)(
+ input clk,
+ input reset,
+ input valid,
+ input [3:0] wstrb,
+ input [BITS-1:0] wdata,
+ input [BITS-1:0] la_write,
+ input [BITS-1:0] la_input,
+ output ready,
+ output [BITS-1:0] rdata,
+ output [BITS-1:0] count
+);
+ reg ready;
+ reg [BITS-1:0] count;
+ reg [BITS-1:0] rdata;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 0;
+ ready <= 0;
+ end else begin
+ ready <= 1'b0;
+ if (~|la_write) begin
+ count <= count + 1;
+ end
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ rdata <= count;
+ if (wstrb[0]) count[7:0] <= wdata[7:0];
+ if (wstrb[1]) count[15:8] <= wdata[15:8];
+ if (wstrb[2]) count[23:16] <= wdata[23:16];
+ if (wstrb[3]) count[31:24] <= wdata[31:24];
+ end else if (|la_write) begin
+ count <= la_write & la_input;
+ end
+ end
+ end
+
+endmodule
+`default_nettype wire
diff --git a/openlane/designs/caravel_upw/src/user_proj_example2.v b/openlane/designs/caravel_upw/src/user_proj_example2.v
new file mode 100644
index 0000000..49497b9
--- /dev/null
+++ b/openlane/designs/caravel_upw/src/user_proj_example2.v
@@ -0,0 +1,165 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only). The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project. The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example2 #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vccd2, // User area 1 1.8V supply
+ inout vssd2, // User area 1 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire clk;
+ wire rst;
+
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+ wire [31:0] rdata;
+ wire [31:0] wdata;
+ wire [BITS-1:0] count;
+
+ wire valid;
+ wire [3:0] wstrb;
+ wire [31:0] la_write;
+
+ // WB MI A
+ assign valid = wbs_cyc_i && wbs_stb_i;
+ assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ assign wbs_dat_o = rdata;
+ assign wdata = wbs_dat_i;
+
+ // IO
+ assign io_out = count;
+ assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA
+ assign la_data_out = {{(127-BITS){1'b0}}, count};
+ // Assuming LA probes [63:32] are for controlling the count register
+ assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+ assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+
+ counter #(
+ .BITS(BITS)
+ ) counter(
+ .clk(clk),
+ .reset(rst),
+ .ready(wbs_ack_o),
+ .valid(valid),
+ .rdata(rdata),
+ .wdata(wbs_dat_i),
+ .wstrb(wstrb),
+ .la_write(la_write),
+ .la_input(la_data_in[63:32]),
+ .count(count)
+ );
+
+endmodule
+
+module counter #(
+ parameter BITS = 32
+)(
+ input clk,
+ input reset,
+ input valid,
+ input [3:0] wstrb,
+ input [BITS-1:0] wdata,
+ input [BITS-1:0] la_write,
+ input [BITS-1:0] la_input,
+ output ready,
+ output [BITS-1:0] rdata,
+ output [BITS-1:0] count
+);
+ reg ready;
+ reg [BITS-1:0] count;
+ reg [BITS-1:0] rdata;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 0;
+ ready <= 0;
+ end else begin
+ ready <= 1'b0;
+ if (~|la_write) begin
+ count <= count + 1;
+ end
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ rdata <= count;
+ if (wstrb[0]) count[7:0] <= wdata[7:0];
+ if (wstrb[1]) count[15:8] <= wdata[15:8];
+ if (wstrb[2]) count[23:16] <= wdata[23:16];
+ if (wstrb[3]) count[31:24] <= wdata[31:24];
+ end else if (|la_write) begin
+ count <= la_write & la_input;
+ end
+ end
+ end
+
+endmodule
+`default_nettype wire
diff --git a/openlane/designs/caravel_upw/src/user_project_wrapper.v b/openlane/designs/caravel_upw/src/user_project_wrapper.v
new file mode 100644
index 0000000..5b893a4
--- /dev/null
+++ b/openlane/designs/caravel_upw/src/user_project_wrapper.v
@@ -0,0 +1,159 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_proj_example mprj1 (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+user_proj_example2 mprj2 (
+`ifdef USE_POWER_PINS
+ .vccd2(vccd2), // User area 1 1.8V power
+ .vssd2(vssd2), // User area 1 digital ground
+`endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_project_wrapper
+
+`default_nettype wire
diff --git a/openlane/designs/gcd/asap7_asap7sc7p5t_config.tcl b/openlane/designs/gcd/asap7_asap7sc7p5t_config.tcl
new file mode 100644
index 0000000..c890cc1
--- /dev/null
+++ b/openlane/designs/gcd/asap7_asap7sc7p5t_config.tcl
@@ -0,0 +1,13 @@
+set ::env(RUN_MAGIC) {0}
+set ::env(RUN_MAGIC_DRC) {0}
+set ::env(RUN_LVS) {0}
+set ::env(PRIMARY_SIGNOFF_TOOL) {klayout}
+
+set ::env(CLOCK_PERIOD) "420"
+
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) "0 0 16.2 16.2"
+set ::env(PLACE_DENSITY) 0.35
+
+set ::env(LEFT_MARGIN_MULT) 20
+set ::env(RIGHT_MARGIN_MULT) 20
diff --git a/openlane/designs/gcd/config.tcl b/openlane/designs/gcd/config.tcl
new file mode 100644
index 0000000..ce6211a
--- /dev/null
+++ b/openlane/designs/gcd/config.tcl
@@ -0,0 +1,22 @@
+# Design
+set ::env(DESIGN_NAME) "gcd"
+
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/*.v]
+
+set ::env(CLOCK_PORT) "clk"
+
+# match ORFS
+set ::env(SYNTH_STRATEGY) "DELAY 4"
+set ::env(SYNTH_SHARE_RESOURCES) 0
+
+# Use OR defaults
+set ::env(FP_IO_VLENGTH) ""
+set ::env(FP_IO_HLENGTH) ""
+set ::env(FP_IO_VTHICKNESS_MULT) ""
+set ::env(FP_IO_HTHICKNESS_MULT) ""
+set ::env(FP_IO_MIN_DISTANCE) ""
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/gcd/gcd.v b/openlane/designs/gcd/gcd.v
new file mode 100644
index 0000000..846d233
--- /dev/null
+++ b/openlane/designs/gcd/gcd.v
@@ -0,0 +1,757 @@
+//-----------------------------------------------------------------------------
+// GcdUnit
+//-----------------------------------------------------------------------------
+//
+// Originally Generated from PyMTL with a few modifications to make it more
+// friendly to OpenROAD tools
+//
+// dump-vcd: False
+// verilator-xinit: zeros
+//module GcdUnit
+module gcd
+(
+ input wire clk,
+ input wire [ 31:0] req_msg,
+ output wire req_rdy,
+ input wire req_val,
+ input wire reset,
+ output wire [ 15:0] resp_msg,
+ input wire resp_rdy,
+ output wire resp_val
+);
+
+ // ctrl temporaries
+ wire [ 0:0] ctrl$is_b_zero;
+ wire [ 0:0] ctrl$resp_rdy;
+ wire [ 0:0] ctrl$clk;
+ wire [ 0:0] ctrl$is_a_lt_b;
+ wire [ 0:0] ctrl$req_val;
+ wire [ 0:0] ctrl$reset;
+ wire [ 1:0] ctrl$a_mux_sel;
+ wire [ 0:0] ctrl$resp_val;
+ wire [ 0:0] ctrl$b_mux_sel;
+ wire [ 0:0] ctrl$b_reg_en;
+ wire [ 0:0] ctrl$a_reg_en;
+ wire [ 0:0] ctrl$req_rdy;
+
+ GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e ctrl
+ (
+ .is_b_zero ( ctrl$is_b_zero ),
+ .resp_rdy ( ctrl$resp_rdy ),
+ .clk ( ctrl$clk ),
+ .is_a_lt_b ( ctrl$is_a_lt_b ),
+ .req_val ( ctrl$req_val ),
+ .reset ( ctrl$reset ),
+ .a_mux_sel ( ctrl$a_mux_sel ),
+ .resp_val ( ctrl$resp_val ),
+ .b_mux_sel ( ctrl$b_mux_sel ),
+ .b_reg_en ( ctrl$b_reg_en ),
+ .a_reg_en ( ctrl$a_reg_en ),
+ .req_rdy ( ctrl$req_rdy )
+ );
+
+ // dpath temporaries
+ wire [ 1:0] dpath$a_mux_sel;
+ wire [ 0:0] dpath$clk;
+ wire [ 15:0] dpath$req_msg_b;
+ wire [ 15:0] dpath$req_msg_a;
+ wire [ 0:0] dpath$b_mux_sel;
+ wire [ 0:0] dpath$reset;
+ wire [ 0:0] dpath$b_reg_en;
+ wire [ 0:0] dpath$a_reg_en;
+ wire [ 0:0] dpath$is_b_zero;
+ wire [ 15:0] dpath$resp_msg;
+ wire [ 0:0] dpath$is_a_lt_b;
+
+ GcdUnitDpathRTL_0x4d0fc71ead8d3d9e dpath
+ (
+ .a_mux_sel ( dpath$a_mux_sel ),
+ .clk ( dpath$clk ),
+ .req_msg_b ( dpath$req_msg_b ),
+ .req_msg_a ( dpath$req_msg_a ),
+ .b_mux_sel ( dpath$b_mux_sel ),
+ .reset ( dpath$reset ),
+ .b_reg_en ( dpath$b_reg_en ),
+ .a_reg_en ( dpath$a_reg_en ),
+ .is_b_zero ( dpath$is_b_zero ),
+ .resp_msg ( dpath$resp_msg ),
+ .is_a_lt_b ( dpath$is_a_lt_b )
+ );
+
+ // signal connections
+ assign ctrl$clk = clk;
+ assign ctrl$is_a_lt_b = dpath$is_a_lt_b;
+ assign ctrl$is_b_zero = dpath$is_b_zero;
+ assign ctrl$req_val = req_val;
+ assign ctrl$reset = reset;
+ assign ctrl$resp_rdy = resp_rdy;
+ assign dpath$a_mux_sel = ctrl$a_mux_sel;
+ assign dpath$a_reg_en = ctrl$a_reg_en;
+ assign dpath$b_mux_sel = ctrl$b_mux_sel;
+ assign dpath$b_reg_en = ctrl$b_reg_en;
+ assign dpath$clk = clk;
+ assign dpath$req_msg_a = req_msg[31:16];
+ assign dpath$req_msg_b = req_msg[15:0];
+ assign dpath$reset = reset;
+ assign req_rdy = ctrl$req_rdy;
+ assign resp_msg = dpath$resp_msg;
+ assign resp_val = ctrl$resp_val;
+
+
+
+endmodule // GcdUnit
+
+//-----------------------------------------------------------------------------
+// GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
+//-----------------------------------------------------------------------------
+// dump-vcd: False
+// verilator-xinit: zeros
+module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
+(
+ output reg [ 1:0] a_mux_sel,
+ output reg [ 0:0] a_reg_en,
+ output reg [ 0:0] b_mux_sel,
+ output reg [ 0:0] b_reg_en,
+ input wire [ 0:0] clk,
+ input wire [ 0:0] is_a_lt_b,
+ input wire [ 0:0] is_b_zero,
+ output reg [ 0:0] req_rdy,
+ input wire [ 0:0] req_val,
+ input wire [ 0:0] reset,
+ input wire [ 0:0] resp_rdy,
+ output reg [ 0:0] resp_val
+);
+
+ // register declarations
+ reg [ 1:0] curr_state__0;
+ reg [ 1:0] current_state__1;
+ reg [ 0:0] do_sub;
+ reg [ 0:0] do_swap;
+ reg [ 1:0] next_state__0;
+ reg [ 1:0] state$in_;
+
+ // localparam declarations
+ localparam A_MUX_SEL_B = 2;
+ localparam A_MUX_SEL_IN = 0;
+ localparam A_MUX_SEL_SUB = 1;
+ localparam A_MUX_SEL_X = 0;
+ localparam B_MUX_SEL_A = 0;
+ localparam B_MUX_SEL_IN = 1;
+ localparam B_MUX_SEL_X = 0;
+ localparam STATE_CALC = 1;
+ localparam STATE_DONE = 2;
+ localparam STATE_IDLE = 0;
+
+ // state temporaries
+ wire [ 0:0] state$reset;
+ wire [ 0:0] state$clk;
+ wire [ 1:0] state$out;
+
+ RegRst_0x9f365fdf6c8998a state
+ (
+ .reset ( state$reset ),
+ .in_ ( state$in_ ),
+ .clk ( state$clk ),
+ .out ( state$out )
+ );
+
+ // signal connections
+ assign state$clk = clk;
+ assign state$reset = reset;
+
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def state_transitions():
+ //
+ // curr_state = s.state.out
+ // next_state = s.state.out
+ //
+ // # Transistions out of IDLE state
+ //
+ // if ( curr_state == s.STATE_IDLE ):
+ // if ( s.req_val and s.req_rdy ):
+ // next_state = s.STATE_CALC
+ //
+ // # Transistions out of CALC state
+ //
+ // if ( curr_state == s.STATE_CALC ):
+ // if ( not s.is_a_lt_b and s.is_b_zero ):
+ // next_state = s.STATE_DONE
+ //
+ // # Transistions out of DONE state
+ //
+ // if ( curr_state == s.STATE_DONE ):
+ // if ( s.resp_val and s.resp_rdy ):
+ // next_state = s.STATE_IDLE
+ //
+ // s.state.in_.value = next_state
+
+ // logic for state_transitions()
+ always @ (*) begin
+ curr_state__0 = state$out;
+ next_state__0 = state$out;
+ if ((curr_state__0 == STATE_IDLE)) begin
+ if ((req_val&&req_rdy)) begin
+ next_state__0 = STATE_CALC;
+ end
+ else begin
+ end
+ end
+ else begin
+ end
+ if ((curr_state__0 == STATE_CALC)) begin
+ if ((!is_a_lt_b&&is_b_zero)) begin
+ next_state__0 = STATE_DONE;
+ end
+ else begin
+ end
+ end
+ else begin
+ end
+ if ((curr_state__0 == STATE_DONE)) begin
+ if ((resp_val&&resp_rdy)) begin
+ next_state__0 = STATE_IDLE;
+ end
+ else begin
+ end
+ end
+ else begin
+ end
+ state$in_ = next_state__0;
+ end
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def state_outputs():
+ //
+ // current_state = s.state.out
+ //
+ // # In IDLE state we simply wait for inputs to arrive and latch them
+ //
+ // if current_state == s.STATE_IDLE:
+ // s.req_rdy.value = 1
+ // s.resp_val.value = 0
+ // s.a_mux_sel.value = A_MUX_SEL_IN
+ // s.a_reg_en.value = 1
+ // s.b_mux_sel.value = B_MUX_SEL_IN
+ // s.b_reg_en.value = 1
+ //
+ // # In CALC state we iteratively swap/sub to calculate GCD
+ //
+ // elif current_state == s.STATE_CALC:
+ //
+ // s.do_swap.value = s.is_a_lt_b
+ // s.do_sub.value = ~s.is_b_zero
+ //
+ // s.req_rdy.value = 0
+ // s.resp_val.value = 0
+ // s.a_mux_sel.value = A_MUX_SEL_B if s.do_swap else A_MUX_SEL_SUB
+ // s.a_reg_en.value = 1
+ // s.b_mux_sel.value = B_MUX_SEL_A
+ // s.b_reg_en.value = s.do_swap
+ //
+ // # In DONE state we simply wait for output transaction to occur
+ //
+ // elif current_state == s.STATE_DONE:
+ // s.req_rdy.value = 0
+ // s.resp_val.value = 1
+ // s.a_mux_sel.value = A_MUX_SEL_X
+ // s.a_reg_en.value = 0
+ // s.b_mux_sel.value = B_MUX_SEL_X
+ // s.b_reg_en.value = 0
+ //
+ // # Default case that we should not hit
+ //
+ // else:
+ // s.req_rdy.value = 0
+ // s.resp_val.value = 0
+ // s.a_mux_sel.value = A_MUX_SEL_X
+ // s.a_reg_en.value = 0
+ // s.b_mux_sel.value = B_MUX_SEL_X
+ // s.b_reg_en.value = 0
+
+ // logic for state_outputs()
+ always @ (*) begin
+ current_state__1 = state$out;
+ if ((current_state__1 == STATE_IDLE)) begin
+ req_rdy = 1;
+ resp_val = 0;
+ a_mux_sel = A_MUX_SEL_IN;
+ a_reg_en = 1;
+ b_mux_sel = B_MUX_SEL_IN;
+ b_reg_en = 1;
+ end
+ else begin
+ if ((current_state__1 == STATE_CALC)) begin
+ do_swap = is_a_lt_b;
+ do_sub = ~is_b_zero;
+ req_rdy = 0;
+ resp_val = 0;
+ a_mux_sel = do_swap ? A_MUX_SEL_B : A_MUX_SEL_SUB;
+ a_reg_en = 1;
+ b_mux_sel = B_MUX_SEL_A;
+ b_reg_en = do_swap;
+ end
+ else begin
+ if ((current_state__1 == STATE_DONE)) begin
+ req_rdy = 0;
+ resp_val = 1;
+ a_mux_sel = A_MUX_SEL_X;
+ a_reg_en = 0;
+ b_mux_sel = B_MUX_SEL_X;
+ b_reg_en = 0;
+ end
+ else begin
+ req_rdy = 0;
+ resp_val = 0;
+ a_mux_sel = A_MUX_SEL_X;
+ a_reg_en = 0;
+ b_mux_sel = B_MUX_SEL_X;
+ b_reg_en = 0;
+ end
+ end
+ end
+ end
+
+
+endmodule // GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e
+
+//-----------------------------------------------------------------------------
+// RegRst_0x9f365fdf6c8998a
+//-----------------------------------------------------------------------------
+// dtype: 2
+// reset_value: 0
+// dump-vcd: False
+// verilator-xinit: zeros
+module RegRst_0x9f365fdf6c8998a
+(
+ input wire [ 0:0] clk,
+ input wire [ 1:0] in_,
+ output reg [ 1:0] out,
+ input wire [ 0:0] reset
+);
+
+ // localparam declarations
+ localparam reset_value = 0;
+
+
+
+ // PYMTL SOURCE:
+ //
+ // @s.posedge_clk
+ // def seq_logic():
+ // if s.reset:
+ // s.out.next = reset_value
+ // else:
+ // s.out.next = s.in_
+
+ // logic for seq_logic()
+ always @ (posedge clk) begin
+ if (reset) begin
+ out <= reset_value;
+ end
+ else begin
+ out <= in_;
+ end
+ end
+
+
+endmodule // RegRst_0x9f365fdf6c8998a
+
+//-----------------------------------------------------------------------------
+// GcdUnitDpathRTL_0x4d0fc71ead8d3d9e
+//-----------------------------------------------------------------------------
+// dump-vcd: False
+// verilator-xinit: zeros
+module GcdUnitDpathRTL_0x4d0fc71ead8d3d9e
+(
+ input wire [ 1:0] a_mux_sel,
+ input wire [ 0:0] a_reg_en,
+ input wire [ 0:0] b_mux_sel,
+ input wire [ 0:0] b_reg_en,
+ input wire [ 0:0] clk,
+ output wire [ 0:0] is_a_lt_b,
+ output wire [ 0:0] is_b_zero,
+ input wire [ 15:0] req_msg_a,
+ input wire [ 15:0] req_msg_b,
+ input wire [ 0:0] reset,
+ output wire [ 15:0] resp_msg
+);
+
+ // wire declarations
+ wire [ 15:0] sub_out;
+ wire [ 15:0] b_reg_out;
+
+
+ // a_reg temporaries
+ wire [ 0:0] a_reg$reset;
+ wire [ 15:0] a_reg$in_;
+ wire [ 0:0] a_reg$clk;
+ wire [ 0:0] a_reg$en;
+ wire [ 15:0] a_reg$out;
+
+ RegEn_0x68db79c4ec1d6e5b a_reg
+ (
+ .reset ( a_reg$reset ),
+ .in_ ( a_reg$in_ ),
+ .clk ( a_reg$clk ),
+ .en ( a_reg$en ),
+ .out ( a_reg$out )
+ );
+
+ // a_lt_b temporaries
+ wire [ 0:0] a_lt_b$reset;
+ wire [ 0:0] a_lt_b$clk;
+ wire [ 15:0] a_lt_b$in0;
+ wire [ 15:0] a_lt_b$in1;
+ wire [ 0:0] a_lt_b$out;
+
+ LtComparator_0x422b1f52edd46a85 a_lt_b
+ (
+ .reset ( a_lt_b$reset ),
+ .clk ( a_lt_b$clk ),
+ .in0 ( a_lt_b$in0 ),
+ .in1 ( a_lt_b$in1 ),
+ .out ( a_lt_b$out )
+ );
+
+ // b_zero temporaries
+ wire [ 0:0] b_zero$reset;
+ wire [ 15:0] b_zero$in_;
+ wire [ 0:0] b_zero$clk;
+ wire [ 0:0] b_zero$out;
+
+ ZeroComparator_0x422b1f52edd46a85 b_zero
+ (
+ .reset ( b_zero$reset ),
+ .in_ ( b_zero$in_ ),
+ .clk ( b_zero$clk ),
+ .out ( b_zero$out )
+ );
+
+ // a_mux temporaries
+ wire [ 0:0] a_mux$reset;
+ wire [ 15:0] a_mux$in_$000;
+ wire [ 15:0] a_mux$in_$001;
+ wire [ 15:0] a_mux$in_$002;
+ wire [ 0:0] a_mux$clk;
+ wire [ 1:0] a_mux$sel;
+ wire [ 15:0] a_mux$out;
+
+ Mux_0x683fa1a418b072c9 a_mux
+ (
+ .reset ( a_mux$reset ),
+ .in_$000 ( a_mux$in_$000 ),
+ .in_$001 ( a_mux$in_$001 ),
+ .in_$002 ( a_mux$in_$002 ),
+ .clk ( a_mux$clk ),
+ .sel ( a_mux$sel ),
+ .out ( a_mux$out )
+ );
+
+ // b_mux temporaries
+ wire [ 0:0] b_mux$reset;
+ wire [ 15:0] b_mux$in_$000;
+ wire [ 15:0] b_mux$in_$001;
+ wire [ 0:0] b_mux$clk;
+ wire [ 0:0] b_mux$sel;
+ wire [ 15:0] b_mux$out;
+
+ Mux_0xdd6473406d1a99a b_mux
+ (
+ .reset ( b_mux$reset ),
+ .in_$000 ( b_mux$in_$000 ),
+ .in_$001 ( b_mux$in_$001 ),
+ .clk ( b_mux$clk ),
+ .sel ( b_mux$sel ),
+ .out ( b_mux$out )
+ );
+
+ // sub temporaries
+ wire [ 0:0] sub$reset;
+ wire [ 0:0] sub$clk;
+ wire [ 15:0] sub$in0;
+ wire [ 15:0] sub$in1;
+ wire [ 15:0] sub$out;
+
+ Subtractor_0x422b1f52edd46a85 sub
+ (
+ .reset ( sub$reset ),
+ .clk ( sub$clk ),
+ .in0 ( sub$in0 ),
+ .in1 ( sub$in1 ),
+ .out ( sub$out )
+ );
+
+ // b_reg temporaries
+ wire [ 0:0] b_reg$reset;
+ wire [ 15:0] b_reg$in_;
+ wire [ 0:0] b_reg$clk;
+ wire [ 0:0] b_reg$en;
+ wire [ 15:0] b_reg$out;
+
+ RegEn_0x68db79c4ec1d6e5b b_reg
+ (
+ .reset ( b_reg$reset ),
+ .in_ ( b_reg$in_ ),
+ .clk ( b_reg$clk ),
+ .en ( b_reg$en ),
+ .out ( b_reg$out )
+ );
+
+ // signal connections
+ assign a_lt_b$clk = clk;
+ assign a_lt_b$in0 = a_reg$out;
+ assign a_lt_b$in1 = b_reg$out;
+ assign a_lt_b$reset = reset;
+ assign a_mux$clk = clk;
+ assign a_mux$in_$000 = req_msg_a;
+ assign a_mux$in_$001 = sub_out;
+ assign a_mux$in_$002 = b_reg_out;
+ assign a_mux$reset = reset;
+ assign a_mux$sel = a_mux_sel;
+ assign a_reg$clk = clk;
+ assign a_reg$en = a_reg_en;
+ assign a_reg$in_ = a_mux$out;
+ assign a_reg$reset = reset;
+ assign b_mux$clk = clk;
+ assign b_mux$in_$000 = a_reg$out;
+ assign b_mux$in_$001 = req_msg_b;
+ assign b_mux$reset = reset;
+ assign b_mux$sel = b_mux_sel;
+ assign b_reg$clk = clk;
+ assign b_reg$en = b_reg_en;
+ assign b_reg$in_ = b_mux$out;
+ assign b_reg$reset = reset;
+ assign b_reg_out = b_reg$out;
+ assign b_zero$clk = clk;
+ assign b_zero$in_ = b_reg$out;
+ assign b_zero$reset = reset;
+ assign is_a_lt_b = a_lt_b$out;
+ assign is_b_zero = b_zero$out;
+ assign resp_msg = sub$out;
+ assign sub$clk = clk;
+ assign sub$in0 = a_reg$out;
+ assign sub$in1 = b_reg$out;
+ assign sub$reset = reset;
+ assign sub_out = sub$out;
+
+
+
+endmodule // GcdUnitDpathRTL_0x4d0fc71ead8d3d9e
+
+//-----------------------------------------------------------------------------
+// RegEn_0x68db79c4ec1d6e5b
+//-----------------------------------------------------------------------------
+// dtype: 16
+// dump-vcd: False
+// verilator-xinit: zeros
+module RegEn_0x68db79c4ec1d6e5b
+(
+ input wire [ 0:0] clk,
+ input wire [ 0:0] en,
+ input wire [ 15:0] in_,
+ output reg [ 15:0] out,
+ input wire [ 0:0] reset
+);
+
+
+
+ // PYMTL SOURCE:
+ //
+ // @s.posedge_clk
+ // def seq_logic():
+ // if s.en:
+ // s.out.next = s.in_
+
+ // logic for seq_logic()
+ always @ (posedge clk) begin
+ if (en) begin
+ out <= in_;
+ end
+ else begin
+ end
+ end
+
+
+endmodule // RegEn_0x68db79c4ec1d6e5b
+
+//-----------------------------------------------------------------------------
+// LtComparator_0x422b1f52edd46a85
+//-----------------------------------------------------------------------------
+// nbits: 16
+// dump-vcd: False
+// verilator-xinit: zeros
+module LtComparator_0x422b1f52edd46a85
+(
+ input wire [ 0:0] clk,
+ input wire [ 15:0] in0,
+ input wire [ 15:0] in1,
+ output reg [ 0:0] out,
+ input wire [ 0:0] reset
+);
+
+
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def comb_logic():
+ // s.out.value = s.in0 < s.in1
+
+ // logic for comb_logic()
+ always @ (*) begin
+ out = (in0 < in1);
+ end
+
+
+endmodule // LtComparator_0x422b1f52edd46a85
+
+//-----------------------------------------------------------------------------
+// ZeroComparator_0x422b1f52edd46a85
+//-----------------------------------------------------------------------------
+// nbits: 16
+// dump-vcd: False
+// verilator-xinit: zeros
+module ZeroComparator_0x422b1f52edd46a85
+(
+ input wire [ 0:0] clk,
+ input wire [ 15:0] in_,
+ output reg [ 0:0] out,
+ input wire [ 0:0] reset
+);
+
+
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def comb_logic():
+ // s.out.value = s.in_ == 0
+
+ // logic for comb_logic()
+ always @ (*) begin
+ out = (in_ == 0);
+ end
+
+
+endmodule // ZeroComparator_0x422b1f52edd46a85
+
+//-----------------------------------------------------------------------------
+// Mux_0x683fa1a418b072c9
+//-----------------------------------------------------------------------------
+// dtype: 16
+// nports: 3
+// dump-vcd: False
+// verilator-xinit: zeros
+module Mux_0x683fa1a418b072c9
+(
+ input wire [ 0:0] clk,
+ input wire [ 15:0] in_$000,
+ input wire [ 15:0] in_$001,
+ input wire [ 15:0] in_$002,
+ output reg [ 15:0] out,
+ input wire [ 0:0] reset,
+ input wire [ 1:0] sel
+);
+
+ // localparam declarations
+ localparam nports = 3;
+
+
+ // array declarations
+ wire [ 15:0] in_[0:2];
+ assign in_[ 0] = in_$000;
+ assign in_[ 1] = in_$001;
+ assign in_[ 2] = in_$002;
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def comb_logic():
+ // assert s.sel < nports
+ // s.out.v = s.in_[ s.sel ]
+
+ // logic for comb_logic()
+ always @ (*) begin
+ out = in_[sel];
+ end
+
+
+endmodule // Mux_0x683fa1a418b072c9
+
+//-----------------------------------------------------------------------------
+// Mux_0xdd6473406d1a99a
+//-----------------------------------------------------------------------------
+// dtype: 16
+// nports: 2
+// dump-vcd: False
+// verilator-xinit: zeros
+module Mux_0xdd6473406d1a99a
+(
+ input wire [ 0:0] clk,
+ input wire [ 15:0] in_$000,
+ input wire [ 15:0] in_$001,
+ output reg [ 15:0] out,
+ input wire [ 0:0] reset,
+ input wire [ 0:0] sel
+);
+
+ // localparam declarations
+ localparam nports = 2;
+
+
+ // array declarations
+ wire [ 15:0] in_[0:1];
+ assign in_[ 0] = in_$000;
+ assign in_[ 1] = in_$001;
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def comb_logic():
+ // assert s.sel < nports
+ // s.out.v = s.in_[ s.sel ]
+
+ // logic for comb_logic()
+ always @ (*) begin
+ out = in_[sel];
+ end
+
+
+endmodule // Mux_0xdd6473406d1a99a
+
+//-----------------------------------------------------------------------------
+// Subtractor_0x422b1f52edd46a85
+//-----------------------------------------------------------------------------
+// nbits: 16
+// dump-vcd: False
+// verilator-xinit: zeros
+module Subtractor_0x422b1f52edd46a85
+(
+ input wire [ 0:0] clk,
+ input wire [ 15:0] in0,
+ input wire [ 15:0] in1,
+ output reg [ 15:0] out,
+ input wire [ 0:0] reset
+);
+
+
+
+ // PYMTL SOURCE:
+ //
+ // @s.combinational
+ // def comb_logic():
+ // s.out.value = s.in0 - s.in1
+
+ // logic for comb_logic()
+ always @ (*) begin
+ out = (in0-in1);
+ end
+
+
+endmodule // Subtractor_0x422b1f52edd46a85
+
diff --git a/openlane/designs/gcd/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/gcd/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100644
index 0000000..e4e3cb4
--- /dev/null
+++ b/openlane/designs/gcd/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,14 @@
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) "0 0 279.96 280.128"
+set ::env(PLACE_DENSITY) 0.35
+
+set ::env(LEFT_MARGIN_MULT) 22
+set ::env(RIGHT_MARGIN_MULT) 22
+set ::env(TOP_MARGIN_MULT) 3
+
+set ::env(FP_PDN_VPITCH) 27.14
+set ::env(FP_PDN_HPITCH) 27.20
+set ::env(FP_PDN_VOFFSET) 13.57
+set ::env(FP_PDN_HOFFSET) 13.60
diff --git a/openlane/designs/gcd/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/gcd/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..f11d6e3
--- /dev/null
+++ b/openlane/designs/gcd/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,18 @@
+set ::env(CLOCK_PERIOD) "2.4"
+
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) "0 0 279.96 280.128"
+set ::env(PLACE_DENSITY) 0.35
+
+set ::env(LEFT_MARGIN_MULT) 22
+set ::env(RIGHT_MARGIN_MULT) 22
+set ::env(TOP_MARGIN_MULT) 3
+
+set ::env(FP_PDN_VPITCH) 27.14
+set ::env(FP_PDN_HPITCH) 27.20
+set ::env(FP_PDN_VOFFSET) 13.57
+set ::env(FP_PDN_HOFFSET) 13.60
+
+# hs generates '[ERROR GRT-0069] Diode not found.'
+# remove once fixed
+set ::env(DIODE_INSERTION_STRATEGY) 0
diff --git a/openlane/designs/inverter/config.tcl b/openlane/designs/inverter/config.tcl
new file mode 100755
index 0000000..d61df60
--- /dev/null
+++ b/openlane/designs/inverter/config.tcl
@@ -0,0 +1,28 @@
+# User config
+set ::env(DESIGN_NAME) inverter
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+# turn off clock
+set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(CLOCK_PORT) ""
+
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 34.5 57.12"
+set ::env(PL_TARGET_DENSITY) 0.75
+
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(FP_PDN_VPITCH) 25.0
+set ::env(FP_PDN_HPITCH) 25.0
+set ::env(FP_PDN_VOFFSET) 5.0
+set ::env(FP_PDN_HOFFSET) 5.0
+
+set ::env(DIODE_INSERTION_STRATEGY) 3
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/inverter/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/inverter/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..a2e9cf9
--- /dev/null
+++ b/openlane/designs/inverter/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1 @@
+# SCL Configs
diff --git a/openlane/designs/inverter/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/inverter/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..a2e9cf9
--- /dev/null
+++ b/openlane/designs/inverter/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1 @@
+# SCL Configs
diff --git a/openlane/designs/inverter/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/inverter/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..a2e9cf9
--- /dev/null
+++ b/openlane/designs/inverter/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1 @@
+# SCL Configs
diff --git a/openlane/designs/inverter/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/inverter/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..a2e9cf9
--- /dev/null
+++ b/openlane/designs/inverter/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1 @@
+# SCL Configs
diff --git a/openlane/designs/inverter/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/inverter/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..a2e9cf9
--- /dev/null
+++ b/openlane/designs/inverter/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1 @@
+# SCL Configs
diff --git a/openlane/designs/inverter/src/inverter.v b/openlane/designs/inverter/src/inverter.v
new file mode 100644
index 0000000..6441b4c
--- /dev/null
+++ b/openlane/designs/inverter/src/inverter.v
@@ -0,0 +1,22 @@
+// Copyright 2020 Matt Venn
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`default_nettype none
+module inverter (
+ input wire in,
+ output out );
+
+ assign out = !in;
+
+endmodule
diff --git a/openlane/designs/manual_macro_placement_test/base.sdc b/openlane/designs/manual_macro_placement_test/base.sdc
new file mode 100644
index 0000000..28b28f2
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/base.sdc
@@ -0,0 +1,157 @@
+###############################################################################
+# Created by write_sdc
+# Wed Oct 6 21:55:22 2021
+###############################################################################
+current_design manual_macro_placement_test
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name clk1 -period 100.0000 [get_ports {clk1}]
+create_clock -name clk2 -period 100.0000 [get_ports {clk1}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[0]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[10]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[11]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[12]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[13]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[14]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[15]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[16]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[17]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[18]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[19]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[1]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[20]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[21]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[22]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[23]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[24]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[25]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[26]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[27]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[28]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[29]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[2]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[30]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[31]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[3]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[4]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[5]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[6]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[7]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {x1[8]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x1[9]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[0]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[10]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[11]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[12]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[13]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[14]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[15]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[16]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[17]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[18]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[19]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[1]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[20]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[21]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[22]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[23]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[24]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[25]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[26]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[27]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[28]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[29]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[2]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[30]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[31]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[3]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[4]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[5]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[6]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[7]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[8]}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {x2[9]}]
+set_input_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {y1}]
+set_input_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {y2}]
+set_output_delay 20.0000 -clock [get_clocks clk1] -add_delay [get_ports {p1}]
+set_output_delay 20.0000 -clock [get_clocks clk2] -add_delay [get_ports {p2}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0177 [get_ports {p1}]
+set_load -pin_load 0.0177 [get_ports {p2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {y1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {y2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x1[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {x2[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/openlane/designs/manual_macro_placement_test/config.tcl b/openlane/designs/manual_macro_placement_test/config.tcl
new file mode 100755
index 0000000..9b377f8
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/config.tcl
@@ -0,0 +1,40 @@
+# User config
+set ::env(DESIGN_NAME) manual_macro_placement_test
+
+set ::env(FP_CORE_UTIL) 35
+set ::env(FP_PDN_VOFFSET) 0
+set ::env(FP_PDN_VPITCH) 30
+
+# OpenROAD reports unconnected nodes as a warning.
+# OpenLane typically treats unconnected node warnings
+# as a critical issue, and simply quits.
+#
+# We'll be leaving it up to the designer's discretion to
+# enable/disable this: if LVS passes you're probably fine
+# with this option being turned off.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(PL_TARGET_DENSITY) 0.35
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(CELL_PAD) 0
+
+set ::env(CLOCK_PERIOD) "100"
+set ::env(CLOCK_PORT) "clk1 clk2"
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/macros/lef/*.lef]
+set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/macros/gds/*.gds]
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/manual_macro_placement_test/macro_placement.cfg b/openlane/designs/manual_macro_placement_test/macro_placement.cfg
new file mode 100644
index 0000000..8f8ad59
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/macro_placement.cfg
@@ -0,0 +1,2 @@
+spm_inst_0 5.59000 148.23 N
+spm_inst_1 179.87 148.23 N
\ No newline at end of file
diff --git a/openlane/designs/manual_macro_placement_test/macros/gds/spm.gds b/openlane/designs/manual_macro_placement_test/macros/gds/spm.gds
new file mode 100644
index 0000000..b6c5472
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/macros/gds/spm.gds
Binary files differ
diff --git a/openlane/designs/manual_macro_placement_test/macros/lef/spm.lef b/openlane/designs/manual_macro_placement_test/macros/lef/spm.lef
new file mode 100644
index 0000000..e7b434d
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/macros/lef/spm.lef
@@ -0,0 +1,342 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO spm
+ CLASS BLOCK ;
+ FOREIGN spm ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 120.680 BY 131.400 ;
+ PIN clk
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 94.850 127.400 95.130 131.400 ;
+ END
+ END clk
+ PIN p
+ DIRECTION OUTPUT TRISTATE ;
+ PORT
+ LAYER met2 ;
+ RECT 69.090 0.000 69.370 4.000 ;
+ END
+ END p
+ PIN rst
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 13.890 0.000 14.170 4.000 ;
+ END
+ END rst
+ PIN x[0]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 2.850 0.000 3.130 4.000 ;
+ END
+ END x[0]
+ PIN x[10]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 35.400 4.000 36.000 ;
+ END
+ END x[10]
+ PIN x[11]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 102.210 0.000 102.490 4.000 ;
+ END
+ END x[11]
+ PIN x[12]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 13.640 120.680 14.240 ;
+ END
+ END x[12]
+ PIN x[13]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 35.970 0.000 36.250 4.000 ;
+ END
+ END x[13]
+ PIN x[14]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 50.690 127.400 50.970 131.400 ;
+ END
+ END x[14]
+ PIN x[15]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 17.570 127.400 17.850 131.400 ;
+ END
+ END x[15]
+ PIN x[16]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 72.770 127.400 73.050 131.400 ;
+ END
+ END x[16]
+ PIN x[17]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 68.040 4.000 68.640 ;
+ END
+ END x[17]
+ PIN x[18]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 29.960 120.680 30.560 ;
+ END
+ END x[18]
+ PIN x[19]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 113.250 0.000 113.530 4.000 ;
+ END
+ END x[19]
+ PIN x[1]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 51.720 4.000 52.320 ;
+ END
+ END x[1]
+ PIN x[20]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 24.930 0.000 25.210 4.000 ;
+ END
+ END x[20]
+ PIN x[21]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 111.560 120.680 112.160 ;
+ END
+ END x[21]
+ PIN x[22]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 84.360 4.000 84.960 ;
+ END
+ END x[22]
+ PIN x[23]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 105.890 127.400 106.170 131.400 ;
+ END
+ END x[23]
+ PIN x[24]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 39.650 127.400 39.930 131.400 ;
+ END
+ END x[24]
+ PIN x[25]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 95.240 120.680 95.840 ;
+ END
+ END x[25]
+ PIN x[26]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 91.170 0.000 91.450 4.000 ;
+ END
+ END x[26]
+ PIN x[27]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 100.680 4.000 101.280 ;
+ END
+ END x[27]
+ PIN x[28]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 78.920 120.680 79.520 ;
+ END
+ END x[28]
+ PIN x[29]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 19.080 4.000 19.680 ;
+ END
+ END x[29]
+ PIN x[2]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 58.050 0.000 58.330 4.000 ;
+ END
+ END x[2]
+ PIN x[30]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 46.280 120.680 46.880 ;
+ END
+ END x[30]
+ PIN x[31]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 116.680 62.600 120.680 63.200 ;
+ END
+ END x[31]
+ PIN x[3]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 6.530 127.400 6.810 131.400 ;
+ END
+ END x[3]
+ PIN x[4]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 83.810 127.400 84.090 131.400 ;
+ END
+ END x[4]
+ PIN x[5]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 80.130 0.000 80.410 4.000 ;
+ END
+ END x[5]
+ PIN x[6]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 61.730 127.400 62.010 131.400 ;
+ END
+ END x[6]
+ PIN x[7]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 117.000 4.000 117.600 ;
+ END
+ END x[7]
+ PIN x[8]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 28.610 127.400 28.890 131.400 ;
+ END
+ END x[8]
+ PIN x[9]
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 116.930 127.400 117.210 131.400 ;
+ END
+ END x[9]
+ PIN y
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 47.010 0.000 47.290 4.000 ;
+ END
+ END y
+ PIN VPWR
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 22.965 10.640 24.565 119.920 ;
+ END
+ END VPWR
+ PIN VGND
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 41.215 10.640 42.815 119.920 ;
+ END
+ END VGND
+ OBS
+ LAYER li1 ;
+ RECT 5.520 10.795 115.000 119.765 ;
+ LAYER met1 ;
+ RECT 2.830 10.640 115.000 120.320 ;
+ LAYER met2 ;
+ RECT 2.860 127.120 6.250 127.400 ;
+ RECT 7.090 127.120 17.290 127.400 ;
+ RECT 18.130 127.120 28.330 127.400 ;
+ RECT 29.170 127.120 39.370 127.400 ;
+ RECT 40.210 127.120 50.410 127.400 ;
+ RECT 51.250 127.120 61.450 127.400 ;
+ RECT 62.290 127.120 72.490 127.400 ;
+ RECT 73.330 127.120 83.530 127.400 ;
+ RECT 84.370 127.120 94.570 127.400 ;
+ RECT 95.410 127.120 105.610 127.400 ;
+ RECT 106.450 127.120 116.650 127.400 ;
+ RECT 2.860 4.280 117.210 127.120 ;
+ RECT 3.410 4.000 13.610 4.280 ;
+ RECT 14.450 4.000 24.650 4.280 ;
+ RECT 25.490 4.000 35.690 4.280 ;
+ RECT 36.530 4.000 46.730 4.280 ;
+ RECT 47.570 4.000 57.770 4.280 ;
+ RECT 58.610 4.000 68.810 4.280 ;
+ RECT 69.650 4.000 79.850 4.280 ;
+ RECT 80.690 4.000 90.890 4.280 ;
+ RECT 91.730 4.000 101.930 4.280 ;
+ RECT 102.770 4.000 112.970 4.280 ;
+ RECT 113.810 4.000 117.210 4.280 ;
+ LAYER met3 ;
+ RECT 4.000 118.000 117.235 119.845 ;
+ RECT 4.400 116.600 117.235 118.000 ;
+ RECT 4.000 112.560 117.235 116.600 ;
+ RECT 4.000 111.160 116.280 112.560 ;
+ RECT 4.000 101.680 117.235 111.160 ;
+ RECT 4.400 100.280 117.235 101.680 ;
+ RECT 4.000 96.240 117.235 100.280 ;
+ RECT 4.000 94.840 116.280 96.240 ;
+ RECT 4.000 85.360 117.235 94.840 ;
+ RECT 4.400 83.960 117.235 85.360 ;
+ RECT 4.000 79.920 117.235 83.960 ;
+ RECT 4.000 78.520 116.280 79.920 ;
+ RECT 4.000 69.040 117.235 78.520 ;
+ RECT 4.400 67.640 117.235 69.040 ;
+ RECT 4.000 63.600 117.235 67.640 ;
+ RECT 4.000 62.200 116.280 63.600 ;
+ RECT 4.000 52.720 117.235 62.200 ;
+ RECT 4.400 51.320 117.235 52.720 ;
+ RECT 4.000 47.280 117.235 51.320 ;
+ RECT 4.000 45.880 116.280 47.280 ;
+ RECT 4.000 36.400 117.235 45.880 ;
+ RECT 4.400 35.000 117.235 36.400 ;
+ RECT 4.000 30.960 117.235 35.000 ;
+ RECT 4.000 29.560 116.280 30.960 ;
+ RECT 4.000 20.080 117.235 29.560 ;
+ RECT 4.400 18.680 117.235 20.080 ;
+ RECT 4.000 14.640 117.235 18.680 ;
+ RECT 4.000 13.240 116.280 14.640 ;
+ RECT 4.000 10.715 117.235 13.240 ;
+ LAYER met4 ;
+ RECT 43.215 10.640 97.550 119.920 ;
+ END
+END spm
+END LIBRARY
+
diff --git a/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/manual_macro_placement_test/src/design.v b/openlane/designs/manual_macro_placement_test/src/design.v
new file mode 100644
index 0000000..bdd4bc4
--- /dev/null
+++ b/openlane/designs/manual_macro_placement_test/src/design.v
@@ -0,0 +1,49 @@
+`default_nettype none
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module manual_macro_placement_test(
+ clk1,
+ clk2,
+ rst1,
+ rst2,
+ x1,
+ x2,
+ y1,
+ y2,
+ p1,
+ p2
+);
+ parameter size = 32;
+ input clk1, rst1;
+ input clk2, rst2;
+ input y1;
+ input y2;
+ input[size-1:0] x1;
+ input[size-1:0] x2;
+ output p1;
+ output p2;
+
+ spm spm_inst_0 (.clk(clk1), .rst(rst1), .x(x1), .y(y1), .p(p1));
+ spm spm_inst_1 (.clk(clk2), .rst(rst2), .x(x2), .y(y2), .p(p2));
+endmodule
+
+(* blackbox *)
+module spm(clk, rst, x, y, p);
+ parameter size = 32;
+ input clk, rst;
+ input y;
+ input[size-1:0] x;
+ output p;
+endmodule
diff --git a/openlane/designs/picorv32a/config.tcl b/openlane/designs/picorv32a/config.tcl
new file mode 100755
index 0000000..3649e3a
--- /dev/null
+++ b/openlane/designs/picorv32a/config.tcl
@@ -0,0 +1,15 @@
+
+# Design
+set ::env(DESIGN_NAME) "picorv32a"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/picorv32a.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..650186a
--- /dev/null
+++ b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "24"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..4dd9ee1
--- /dev/null
+++ b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "24.73"
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..4dd9ee1
--- /dev/null
+++ b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "24.73"
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/picorv32a/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..4dd9ee1
--- /dev/null
+++ b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "24.73"
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/picorv32a/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..37a59fa
--- /dev/null
+++ b/openlane/designs/picorv32a/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(CLOCK_PERIOD) "24.73"
+set ::env(FP_CORE_UTIL) 30
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/picorv32a/src/picorv32a.v b/openlane/designs/picorv32a/src/picorv32a.v
new file mode 100644
index 0000000..b93abd6
--- /dev/null
+++ b/openlane/designs/picorv32a/src/picorv32a.v
@@ -0,0 +1,2978 @@
+/*
+ * PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+// `default_nettype none
+// `define DEBUGNETS
+// `define DEBUGREGS
+// `define DEBUGASM
+// `define DEBUG
+
+`ifdef DEBUG
+ `define debug(debug_command) debug_command
+`else
+ `define debug(debug_command)
+`endif
+
+`ifdef FORMAL
+ `define FORMAL_KEEP (* keep *)
+ `define assert(assert_expr) assert(assert_expr)
+`else
+ `ifdef DEBUGNETS
+ `define FORMAL_KEEP (* keep *)
+ `else
+ `define FORMAL_KEEP
+ `endif
+ `define assert(assert_expr) empty_statement
+`endif
+
+// uncomment this for register file in extra module
+// `define PICORV32_REGS picorv32_regs
+
+// this macro can be used to check if the verilog files in your
+// design are read in the correct order.
+`define PICORV32_V
+
+
+/***************************************************************
+ * picorv32
+ ***************************************************************/
+
+module picorv32a #(
+ parameter [ 0:0] ENABLE_COUNTERS = 1,
+ parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+ parameter [ 0:0] ENABLE_REGS_16_31 = 0,
+ parameter [ 0:0] ENABLE_REGS_DUALPORT = 0,
+ parameter [ 0:0] LATCHED_MEM_RDATA = 0,
+ parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+ parameter [ 0:0] BARREL_SHIFTER = 1,
+ parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+ parameter [ 0:0] TWO_CYCLE_ALU = 1,
+ parameter [ 0:0] COMPRESSED_ISA = 0,
+ parameter [ 0:0] CATCH_MISALIGN = 1,
+ parameter [ 0:0] CATCH_ILLINSN = 1,
+ parameter [ 0:0] ENABLE_PCPI = 0,
+ parameter [ 0:0] ENABLE_MUL = 0,
+ parameter [ 0:0] ENABLE_FAST_MUL = 1,
+ parameter [ 0:0] ENABLE_DIV = 0,
+ parameter [ 0:0] ENABLE_IRQ = 1,
+ parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+ parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+ parameter [ 0:0] ENABLE_TRACE = 0,
+ parameter [ 0:0] REGS_INIT_ZERO = 0,
+ parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+ parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+ parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+ parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+ parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+ input clk, resetn,
+ output reg trap,
+
+ output reg mem_valid,
+ output reg mem_instr,
+ input mem_ready,
+
+ output reg [31:0] mem_addr,
+ output reg [31:0] mem_wdata,
+ output reg [ 3:0] mem_wstrb,
+ input [31:0] mem_rdata,
+
+ // Look-Ahead Interface
+ output mem_la_read,
+ output mem_la_write,
+ output [31:0] mem_la_addr,
+ output reg [31:0] mem_la_wdata,
+ output reg [ 3:0] mem_la_wstrb,
+
+ // Pico Co-Processor Interface (PCPI)
+ output reg pcpi_valid,
+ output reg [31:0] pcpi_insn,
+ output [31:0] pcpi_rs1,
+ output [31:0] pcpi_rs2,
+ input pcpi_wr,
+ input [31:0] pcpi_rd,
+ input pcpi_wait,
+ input pcpi_ready,
+
+ // IRQ Interface
+ input [31:0] irq,
+ output reg [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+ output reg rvfi_valid,
+ output reg [63:0] rvfi_order,
+ output reg [31:0] rvfi_insn,
+ output reg rvfi_trap,
+ output reg rvfi_halt,
+ output reg rvfi_intr,
+ output reg [ 4:0] rvfi_rs1_addr,
+ output reg [ 4:0] rvfi_rs2_addr,
+ output reg [31:0] rvfi_rs1_rdata,
+ output reg [31:0] rvfi_rs2_rdata,
+ output reg [ 4:0] rvfi_rd_addr,
+ output reg [31:0] rvfi_rd_wdata,
+ output reg [31:0] rvfi_pc_rdata,
+ output reg [31:0] rvfi_pc_wdata,
+ output reg [31:0] rvfi_mem_addr,
+ output reg [ 3:0] rvfi_mem_rmask,
+ output reg [ 3:0] rvfi_mem_wmask,
+ output reg [31:0] rvfi_mem_rdata,
+ output reg [31:0] rvfi_mem_wdata,
+`endif
+
+ // Trace Interface
+ output reg trace_valid,
+ output reg [35:0] trace_data
+);
+ localparam integer irq_timer = 0;
+ localparam integer irq_ebreak = 1;
+ localparam integer irq_buserror = 2;
+
+ localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
+ localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
+ localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
+
+ localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
+
+ localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
+ localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
+ localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
+
+ reg [63:0] count_cycle, count_instr;
+ reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
+ reg [4:0] reg_sh;
+
+ reg [31:0] next_insn_opcode;
+ reg [31:0] dbg_insn_opcode;
+ reg [31:0] dbg_insn_addr;
+
+ wire dbg_mem_valid = mem_valid;
+ wire dbg_mem_instr = mem_instr;
+ wire dbg_mem_ready = mem_ready;
+ wire [31:0] dbg_mem_addr = mem_addr;
+ wire [31:0] dbg_mem_wdata = mem_wdata;
+ wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
+ wire [31:0] dbg_mem_rdata = mem_rdata;
+
+ assign pcpi_rs1 = reg_op1;
+ assign pcpi_rs2 = reg_op2;
+
+ wire [31:0] next_pc;
+
+ reg irq_delay;
+ reg irq_active;
+ reg [31:0] irq_mask;
+ reg [31:0] irq_pending;
+ reg [31:0] timer;
+
+`ifndef PICORV32_REGS
+ reg [31:0] cpuregs [0:regfile_size-1];
+
+ integer i;
+ initial begin
+ if (REGS_INIT_ZERO) begin
+ for (i = 0; i < regfile_size; i = i+1)
+ cpuregs[i] = 0;
+ end
+ end
+`endif
+
+ task empty_statement;
+ // This task is used by the `assert directive in non-formal mode to
+ // avoid empty statement (which are unsupported by plain Verilog syntax).
+ begin end
+ endtask
+
+`ifdef DEBUGREGS
+ wire [31:0] dbg_reg_x0 = 0;
+ wire [31:0] dbg_reg_x1 = cpuregs[1];
+ wire [31:0] dbg_reg_x2 = cpuregs[2];
+ wire [31:0] dbg_reg_x3 = cpuregs[3];
+ wire [31:0] dbg_reg_x4 = cpuregs[4];
+ wire [31:0] dbg_reg_x5 = cpuregs[5];
+ wire [31:0] dbg_reg_x6 = cpuregs[6];
+ wire [31:0] dbg_reg_x7 = cpuregs[7];
+ wire [31:0] dbg_reg_x8 = cpuregs[8];
+ wire [31:0] dbg_reg_x9 = cpuregs[9];
+ wire [31:0] dbg_reg_x10 = cpuregs[10];
+ wire [31:0] dbg_reg_x11 = cpuregs[11];
+ wire [31:0] dbg_reg_x12 = cpuregs[12];
+ wire [31:0] dbg_reg_x13 = cpuregs[13];
+ wire [31:0] dbg_reg_x14 = cpuregs[14];
+ wire [31:0] dbg_reg_x15 = cpuregs[15];
+ wire [31:0] dbg_reg_x16 = cpuregs[16];
+ wire [31:0] dbg_reg_x17 = cpuregs[17];
+ wire [31:0] dbg_reg_x18 = cpuregs[18];
+ wire [31:0] dbg_reg_x19 = cpuregs[19];
+ wire [31:0] dbg_reg_x20 = cpuregs[20];
+ wire [31:0] dbg_reg_x21 = cpuregs[21];
+ wire [31:0] dbg_reg_x22 = cpuregs[22];
+ wire [31:0] dbg_reg_x23 = cpuregs[23];
+ wire [31:0] dbg_reg_x24 = cpuregs[24];
+ wire [31:0] dbg_reg_x25 = cpuregs[25];
+ wire [31:0] dbg_reg_x26 = cpuregs[26];
+ wire [31:0] dbg_reg_x27 = cpuregs[27];
+ wire [31:0] dbg_reg_x28 = cpuregs[28];
+ wire [31:0] dbg_reg_x29 = cpuregs[29];
+ wire [31:0] dbg_reg_x30 = cpuregs[30];
+ wire [31:0] dbg_reg_x31 = cpuregs[31];
+`endif
+
+ // Internal PCPI Cores
+
+ wire pcpi_mul_wr;
+ wire [31:0] pcpi_mul_rd;
+ wire pcpi_mul_wait;
+ wire pcpi_mul_ready;
+
+ wire pcpi_div_wr;
+ wire [31:0] pcpi_div_rd;
+ wire pcpi_div_wait;
+ wire pcpi_div_ready;
+
+ reg pcpi_int_wr;
+ reg [31:0] pcpi_int_rd;
+ reg pcpi_int_wait;
+ reg pcpi_int_ready;
+
+ generate if (ENABLE_FAST_MUL) begin
+ picorv32_pcpi_fast_mul pcpi_mul (
+ .clk (clk ),
+ .resetn (resetn ),
+ .pcpi_valid(pcpi_valid ),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_mul_wr ),
+ .pcpi_rd (pcpi_mul_rd ),
+ .pcpi_wait (pcpi_mul_wait ),
+ .pcpi_ready(pcpi_mul_ready )
+ );
+ end else if (ENABLE_MUL) begin
+ picorv32_pcpi_mul pcpi_mul (
+ .clk (clk ),
+ .resetn (resetn ),
+ .pcpi_valid(pcpi_valid ),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_mul_wr ),
+ .pcpi_rd (pcpi_mul_rd ),
+ .pcpi_wait (pcpi_mul_wait ),
+ .pcpi_ready(pcpi_mul_ready )
+ );
+ end else begin
+ assign pcpi_mul_wr = 0;
+ assign pcpi_mul_rd = 32'bx;
+ assign pcpi_mul_wait = 0;
+ assign pcpi_mul_ready = 0;
+ end endgenerate
+
+ generate if (ENABLE_DIV) begin
+ picorv32_pcpi_div pcpi_div (
+ .clk (clk ),
+ .resetn (resetn ),
+ .pcpi_valid(pcpi_valid ),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_div_wr ),
+ .pcpi_rd (pcpi_div_rd ),
+ .pcpi_wait (pcpi_div_wait ),
+ .pcpi_ready(pcpi_div_ready )
+ );
+ end else begin
+ assign pcpi_div_wr = 0;
+ assign pcpi_div_rd = 32'bx;
+ assign pcpi_div_wait = 0;
+ assign pcpi_div_ready = 0;
+ end endgenerate
+
+ always @* begin
+ pcpi_int_wr = 0;
+ pcpi_int_rd = 32'bx;
+ pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
+ pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
+
+ (* parallel_case *)
+ case (1'b1)
+ ENABLE_PCPI && pcpi_ready: begin
+ pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
+ pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
+ end
+ (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
+ pcpi_int_wr = pcpi_mul_wr;
+ pcpi_int_rd = pcpi_mul_rd;
+ end
+ ENABLE_DIV && pcpi_div_ready: begin
+ pcpi_int_wr = pcpi_div_wr;
+ pcpi_int_rd = pcpi_div_rd;
+ end
+ endcase
+ end
+
+
+ // Memory Interface
+
+ reg [1:0] mem_state;
+ reg [1:0] mem_wordsize;
+ reg [31:0] mem_rdata_word;
+ reg [31:0] mem_rdata_q;
+ reg mem_do_prefetch;
+ reg mem_do_rinst;
+ reg mem_do_rdata;
+ reg mem_do_wdata;
+
+ wire mem_xfer;
+ reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
+ wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
+ wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
+
+ reg prefetched_high_word;
+ reg clear_prefetched_high_word;
+ reg [15:0] mem_16bit_buffer;
+
+ wire [31:0] mem_rdata_latched_noshuffle;
+ wire [31:0] mem_rdata_latched;
+
+ wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
+ assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
+
+ wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
+ wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
+ (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
+
+ assign mem_la_write = resetn && !mem_state && mem_do_wdata;
+ assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
+ (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
+ assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
+
+ assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
+
+ assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
+ COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
+ COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ mem_la_firstword_reg <= 0;
+ last_mem_valid <= 0;
+ end else begin
+ if (!last_mem_valid)
+ mem_la_firstword_reg <= mem_la_firstword;
+ last_mem_valid <= mem_valid && !mem_ready;
+ end
+ end
+
+ always @* begin
+ (* full_case *)
+ case (mem_wordsize)
+ 0: begin
+ mem_la_wdata = reg_op2;
+ mem_la_wstrb = 4'b1111;
+ mem_rdata_word = mem_rdata;
+ end
+ 1: begin
+ mem_la_wdata = {2{reg_op2[15:0]}};
+ mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
+ case (reg_op1[1])
+ 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
+ 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
+ endcase
+ end
+ 2: begin
+ mem_la_wdata = {4{reg_op2[7:0]}};
+ mem_la_wstrb = 4'b0001 << reg_op1[1:0];
+ case (reg_op1[1:0])
+ 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
+ 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
+ 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
+ 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
+ endcase
+ end
+ endcase
+ end
+
+ always @(posedge clk) begin
+ if (mem_xfer) begin
+ mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+ next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+ end
+
+ if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
+ case (mem_rdata_latched[1:0])
+ 2'b00: begin // Quadrant 0
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.ADDI4SPN
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
+ end
+ 3'b010: begin // C.LW
+ mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ 3'b 110: begin // C.SW
+ {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ endcase
+ end
+ 2'b01: begin // Quadrant 1
+ case (mem_rdata_latched[15:13])
+ 3'b 000: begin // C.ADDI
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ 3'b 010: begin // C.LI
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ 3'b 011: begin
+ if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
+ mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
+ end else begin // C.LUI
+ mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ end
+ 3'b100: begin
+ if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
+ mem_rdata_q[31:25] <= 7'b0000000;
+ mem_rdata_q[14:12] <= 3'b 101;
+ end
+ if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
+ mem_rdata_q[31:25] <= 7'b0100000;
+ mem_rdata_q[14:12] <= 3'b 101;
+ end
+ if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+ mem_rdata_q[14:12] <= 3'b111;
+ mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+ end
+ if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+ if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
+ if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
+ if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
+ if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
+ mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
+ end
+ end
+ 3'b 110: begin // C.BEQZ
+ mem_rdata_q[14:12] <= 3'b000;
+ { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+ $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+ mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+ end
+ 3'b 111: begin // C.BNEZ
+ mem_rdata_q[14:12] <= 3'b001;
+ { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+ $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+ mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+ end
+ endcase
+ end
+ 2'b10: begin // Quadrant 2
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.SLLI
+ mem_rdata_q[31:25] <= 7'b0000000;
+ mem_rdata_q[14:12] <= 3'b 001;
+ end
+ 3'b010: begin // C.LWSP
+ mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ 3'b100: begin
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= 12'b0;
+ end
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:25] <= 7'b0000000;
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:20] <= 12'b0;
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+ mem_rdata_q[14:12] <= 3'b000;
+ mem_rdata_q[31:25] <= 7'b0000000;
+ end
+ end
+ 3'b110: begin // C.SWSP
+ {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
+ mem_rdata_q[14:12] <= 3'b 010;
+ end
+ endcase
+ end
+ endcase
+ end
+ end
+
+ always @(posedge clk) begin
+ if (resetn && !trap) begin
+ if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
+ `assert(!mem_do_wdata);
+
+ if (mem_do_prefetch || mem_do_rinst)
+ `assert(!mem_do_rdata);
+
+ if (mem_do_rdata)
+ `assert(!mem_do_prefetch && !mem_do_rinst);
+
+ if (mem_do_wdata)
+ `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
+
+ if (mem_state == 2 || mem_state == 3)
+ `assert(mem_valid || mem_do_prefetch);
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!resetn || trap) begin
+ if (!resetn)
+ mem_state <= 0;
+ if (!resetn || mem_ready)
+ mem_valid <= 0;
+ mem_la_secondword <= 0;
+ prefetched_high_word <= 0;
+ end else begin
+ if (mem_la_read || mem_la_write) begin
+ mem_addr <= mem_la_addr;
+ mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
+ end
+ if (mem_la_write) begin
+ mem_wdata <= mem_la_wdata;
+ end
+ case (mem_state)
+ 0: begin
+ if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
+ mem_valid <= !mem_la_use_prefetched_high_word;
+ mem_instr <= mem_do_prefetch || mem_do_rinst;
+ mem_wstrb <= 0;
+ mem_state <= 1;
+ end
+ if (mem_do_wdata) begin
+ mem_valid <= 1;
+ mem_instr <= 0;
+ mem_state <= 2;
+ end
+ end
+ 1: begin
+ `assert(mem_wstrb == 0);
+ `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
+ `assert(mem_valid == !mem_la_use_prefetched_high_word);
+ `assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
+ if (mem_xfer) begin
+ if (COMPRESSED_ISA && mem_la_read) begin
+ mem_valid <= 1;
+ mem_la_secondword <= 1;
+ if (!mem_la_use_prefetched_high_word)
+ mem_16bit_buffer <= mem_rdata[31:16];
+ end else begin
+ mem_valid <= 0;
+ mem_la_secondword <= 0;
+ if (COMPRESSED_ISA && !mem_do_rdata) begin
+ if (~&mem_rdata[1:0] || mem_la_secondword) begin
+ mem_16bit_buffer <= mem_rdata[31:16];
+ prefetched_high_word <= 1;
+ end else begin
+ prefetched_high_word <= 0;
+ end
+ end
+ mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
+ end
+ end
+ end
+ 2: begin
+ `assert(mem_wstrb != 0);
+ `assert(mem_do_wdata);
+ if (mem_xfer) begin
+ mem_valid <= 0;
+ mem_state <= 0;
+ end
+ end
+ 3: begin
+ `assert(mem_wstrb == 0);
+ `assert(mem_do_prefetch);
+ if (mem_do_rinst) begin
+ mem_state <= 0;
+ end
+ end
+ endcase
+ end
+
+ if (clear_prefetched_high_word)
+ prefetched_high_word <= 0;
+ end
+
+
+ // Instruction Decoder
+
+ reg instr_lui, instr_auipc, instr_jal, instr_jalr;
+ reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
+ reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
+ reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
+ reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
+ reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
+ reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+ wire instr_trap;
+
+ reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
+ reg [31:0] decoded_imm, decoded_imm_uj;
+ reg decoder_trigger;
+ reg decoder_trigger_q;
+ reg decoder_pseudo_trigger;
+ reg decoder_pseudo_trigger_q;
+ reg compressed_instr;
+
+ reg is_lui_auipc_jal;
+ reg is_lb_lh_lw_lbu_lhu;
+ reg is_slli_srli_srai;
+ reg is_jalr_addi_slti_sltiu_xori_ori_andi;
+ reg is_sb_sh_sw;
+ reg is_sll_srl_sra;
+ reg is_lui_auipc_jal_jalr_addi_add_sub;
+ reg is_slti_blt_slt;
+ reg is_sltiu_bltu_sltu;
+ reg is_beq_bne_blt_bge_bltu_bgeu;
+ reg is_lbu_lhu_lw;
+ reg is_alu_reg_imm;
+ reg is_alu_reg_reg;
+ reg is_compare;
+
+ assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
+ instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
+ instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
+ instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
+ instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
+ instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
+ instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
+
+ wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
+ assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
+
+ reg [63:0] new_ascii_instr;
+ `FORMAL_KEEP reg [63:0] dbg_ascii_instr;
+ `FORMAL_KEEP reg [31:0] dbg_insn_imm;
+ `FORMAL_KEEP reg [4:0] dbg_insn_rs1;
+ `FORMAL_KEEP reg [4:0] dbg_insn_rs2;
+ `FORMAL_KEEP reg [4:0] dbg_insn_rd;
+ `FORMAL_KEEP reg [31:0] dbg_rs1val;
+ `FORMAL_KEEP reg [31:0] dbg_rs2val;
+ `FORMAL_KEEP reg dbg_rs1val_valid;
+ `FORMAL_KEEP reg dbg_rs2val_valid;
+
+ always @* begin
+ new_ascii_instr = "";
+
+ if (instr_lui) new_ascii_instr = "lui";
+ if (instr_auipc) new_ascii_instr = "auipc";
+ if (instr_jal) new_ascii_instr = "jal";
+ if (instr_jalr) new_ascii_instr = "jalr";
+
+ if (instr_beq) new_ascii_instr = "beq";
+ if (instr_bne) new_ascii_instr = "bne";
+ if (instr_blt) new_ascii_instr = "blt";
+ if (instr_bge) new_ascii_instr = "bge";
+ if (instr_bltu) new_ascii_instr = "bltu";
+ if (instr_bgeu) new_ascii_instr = "bgeu";
+
+ if (instr_lb) new_ascii_instr = "lb";
+ if (instr_lh) new_ascii_instr = "lh";
+ if (instr_lw) new_ascii_instr = "lw";
+ if (instr_lbu) new_ascii_instr = "lbu";
+ if (instr_lhu) new_ascii_instr = "lhu";
+ if (instr_sb) new_ascii_instr = "sb";
+ if (instr_sh) new_ascii_instr = "sh";
+ if (instr_sw) new_ascii_instr = "sw";
+
+ if (instr_addi) new_ascii_instr = "addi";
+ if (instr_slti) new_ascii_instr = "slti";
+ if (instr_sltiu) new_ascii_instr = "sltiu";
+ if (instr_xori) new_ascii_instr = "xori";
+ if (instr_ori) new_ascii_instr = "ori";
+ if (instr_andi) new_ascii_instr = "andi";
+ if (instr_slli) new_ascii_instr = "slli";
+ if (instr_srli) new_ascii_instr = "srli";
+ if (instr_srai) new_ascii_instr = "srai";
+
+ if (instr_add) new_ascii_instr = "add";
+ if (instr_sub) new_ascii_instr = "sub";
+ if (instr_sll) new_ascii_instr = "sll";
+ if (instr_slt) new_ascii_instr = "slt";
+ if (instr_sltu) new_ascii_instr = "sltu";
+ if (instr_xor) new_ascii_instr = "xor";
+ if (instr_srl) new_ascii_instr = "srl";
+ if (instr_sra) new_ascii_instr = "sra";
+ if (instr_or) new_ascii_instr = "or";
+ if (instr_and) new_ascii_instr = "and";
+
+ if (instr_rdcycle) new_ascii_instr = "rdcycle";
+ if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
+ if (instr_rdinstr) new_ascii_instr = "rdinstr";
+ if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
+
+ if (instr_getq) new_ascii_instr = "getq";
+ if (instr_setq) new_ascii_instr = "setq";
+ if (instr_retirq) new_ascii_instr = "retirq";
+ if (instr_maskirq) new_ascii_instr = "maskirq";
+ if (instr_waitirq) new_ascii_instr = "waitirq";
+ if (instr_timer) new_ascii_instr = "timer";
+ end
+
+ reg [63:0] q_ascii_instr;
+ reg [31:0] q_insn_imm;
+ reg [31:0] q_insn_opcode;
+ reg [4:0] q_insn_rs1;
+ reg [4:0] q_insn_rs2;
+ reg [4:0] q_insn_rd;
+ reg dbg_next;
+
+ wire launch_next_insn;
+ reg dbg_valid_insn;
+
+ reg [63:0] cached_ascii_instr;
+ reg [31:0] cached_insn_imm;
+ reg [31:0] cached_insn_opcode;
+ reg [4:0] cached_insn_rs1;
+ reg [4:0] cached_insn_rs2;
+ reg [4:0] cached_insn_rd;
+
+ always @(posedge clk) begin
+ q_ascii_instr <= dbg_ascii_instr;
+ q_insn_imm <= dbg_insn_imm;
+ q_insn_opcode <= dbg_insn_opcode;
+ q_insn_rs1 <= dbg_insn_rs1;
+ q_insn_rs2 <= dbg_insn_rs2;
+ q_insn_rd <= dbg_insn_rd;
+ dbg_next <= launch_next_insn;
+
+ if (!resetn || trap)
+ dbg_valid_insn <= 0;
+ else if (launch_next_insn)
+ dbg_valid_insn <= 1;
+
+ if (decoder_trigger_q) begin
+ cached_ascii_instr <= new_ascii_instr;
+ cached_insn_imm <= decoded_imm;
+ if (&next_insn_opcode[1:0])
+ cached_insn_opcode <= next_insn_opcode;
+ else
+ cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
+ cached_insn_rs1 <= decoded_rs1;
+ cached_insn_rs2 <= decoded_rs2;
+ cached_insn_rd <= decoded_rd;
+ end
+
+ if (launch_next_insn) begin
+ dbg_insn_addr <= next_pc;
+ end
+ end
+
+ always @* begin
+ dbg_ascii_instr = q_ascii_instr;
+ dbg_insn_imm = q_insn_imm;
+ dbg_insn_opcode = q_insn_opcode;
+ dbg_insn_rs1 = q_insn_rs1;
+ dbg_insn_rs2 = q_insn_rs2;
+ dbg_insn_rd = q_insn_rd;
+
+ if (dbg_next) begin
+ if (decoder_pseudo_trigger_q) begin
+ dbg_ascii_instr = cached_ascii_instr;
+ dbg_insn_imm = cached_insn_imm;
+ dbg_insn_opcode = cached_insn_opcode;
+ dbg_insn_rs1 = cached_insn_rs1;
+ dbg_insn_rs2 = cached_insn_rs2;
+ dbg_insn_rd = cached_insn_rd;
+ end else begin
+ dbg_ascii_instr = new_ascii_instr;
+ if (&next_insn_opcode[1:0])
+ dbg_insn_opcode = next_insn_opcode;
+ else
+ dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
+ dbg_insn_imm = decoded_imm;
+ dbg_insn_rs1 = decoded_rs1;
+ dbg_insn_rs2 = decoded_rs2;
+ dbg_insn_rd = decoded_rd;
+ end
+ end
+ end
+
+`ifdef DEBUGASM
+ always @(posedge clk) begin
+ if (dbg_next) begin
+ $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
+ end
+ end
+`endif
+
+`ifdef DEBUG
+ always @(posedge clk) begin
+ if (dbg_next) begin
+ if (&dbg_insn_opcode[1:0])
+ $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+ else
+ $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+ end
+ end
+`endif
+
+ always @(posedge clk) begin
+ is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
+ is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
+ is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
+ is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
+ is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
+ is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
+
+ if (mem_do_rinst && mem_done) begin
+ instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
+ instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
+ instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
+ instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
+ instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
+ instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
+
+ is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
+ is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
+ is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
+ is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
+ is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
+
+ { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
+
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[19:15];
+ decoded_rs2 <= mem_rdata_latched[24:20];
+
+ if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
+ decoded_rs1[regindex_bits-1] <= 1; // instr_getq
+
+ if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
+ decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
+
+ compressed_instr <= 0;
+ if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
+ compressed_instr <= 1;
+ decoded_rd <= 0;
+ decoded_rs1 <= 0;
+ decoded_rs2 <= 0;
+
+ { decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
+ decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
+
+ case (mem_rdata_latched[1:0])
+ 2'b00: begin // Quadrant 0
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.ADDI4SPN
+ is_alu_reg_imm <= |mem_rdata_latched[12:5];
+ decoded_rs1 <= 2;
+ decoded_rd <= 8 + mem_rdata_latched[4:2];
+ end
+ 3'b010: begin // C.LW
+ is_lb_lh_lw_lbu_lhu <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rd <= 8 + mem_rdata_latched[4:2];
+ end
+ 3'b110: begin // C.SW
+ is_sb_sh_sw <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+ end
+ endcase
+ end
+ 2'b01: begin // Quadrant 1
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.NOP / C.ADDI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end
+ 3'b001: begin // C.JAL
+ instr_jal <= 1;
+ decoded_rd <= 1;
+ end
+ 3'b 010: begin // C.LI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 0;
+ end
+ 3'b 011: begin
+ if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
+ if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end else begin // C.LUI
+ instr_lui <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 0;
+ end
+ end
+ end
+ 3'b100: begin
+ if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= 8 + mem_rdata_latched[9:7];
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+ end
+ if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+ is_alu_reg_imm <= 1;
+ decoded_rd <= 8 + mem_rdata_latched[9:7];
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ end
+ if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+ is_alu_reg_reg <= 1;
+ decoded_rd <= 8 + mem_rdata_latched[9:7];
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+ end
+ end
+ 3'b101: begin // C.J
+ instr_jal <= 1;
+ end
+ 3'b110: begin // C.BEQZ
+ is_beq_bne_blt_bge_bltu_bgeu <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 0;
+ end
+ 3'b111: begin // C.BNEZ
+ is_beq_bne_blt_bge_bltu_bgeu <= 1;
+ decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+ decoded_rs2 <= 0;
+ end
+ endcase
+ end
+ 2'b10: begin // Quadrant 2
+ case (mem_rdata_latched[15:13])
+ 3'b000: begin // C.SLLI
+ if (!mem_rdata_latched[12]) begin
+ is_alu_reg_imm <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+ end
+ end
+ 3'b010: begin // C.LWSP
+ if (mem_rdata_latched[11:7]) begin
+ is_lb_lh_lw_lbu_lhu <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 2;
+ end
+ end
+ 3'b100: begin
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+ instr_jalr <= 1;
+ decoded_rd <= 0;
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end
+ if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+ is_alu_reg_reg <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= 0;
+ decoded_rs2 <= mem_rdata_latched[6:2];
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+ instr_jalr <= 1;
+ decoded_rd <= 1;
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ end
+ if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+ is_alu_reg_reg <= 1;
+ decoded_rd <= mem_rdata_latched[11:7];
+ decoded_rs1 <= mem_rdata_latched[11:7];
+ decoded_rs2 <= mem_rdata_latched[6:2];
+ end
+ end
+ 3'b110: begin // C.SWSP
+ is_sb_sh_sw <= 1;
+ decoded_rs1 <= 2;
+ decoded_rs2 <= mem_rdata_latched[6:2];
+ end
+ endcase
+ end
+ endcase
+ end
+ end
+
+ if (decoder_trigger && !decoder_pseudo_trigger) begin
+ pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
+
+ instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
+ instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
+ instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
+ instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
+ instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
+ instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
+
+ instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
+ instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
+ instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
+ instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
+ instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
+
+ instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
+ instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
+ instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
+
+ instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
+ instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
+ instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
+ instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
+ instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
+ instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
+
+ instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+
+ instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
+ instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+ instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
+ instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
+
+ instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
+ (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
+ instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
+ (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+ instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
+ instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+
+ instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
+ (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
+
+ instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+ instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+ instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
+ instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
+
+ is_slli_srli_srai <= is_alu_reg_imm && |{
+ mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+ };
+
+ is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
+ mem_rdata_q[14:12] == 3'b000,
+ mem_rdata_q[14:12] == 3'b010,
+ mem_rdata_q[14:12] == 3'b011,
+ mem_rdata_q[14:12] == 3'b100,
+ mem_rdata_q[14:12] == 3'b110,
+ mem_rdata_q[14:12] == 3'b111
+ };
+
+ is_sll_srl_sra <= is_alu_reg_reg && |{
+ mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+ mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+ };
+
+ is_lui_auipc_jal_jalr_addi_add_sub <= 0;
+ is_compare <= 0;
+
+ (* parallel_case *)
+ case (1'b1)
+ instr_jal:
+ decoded_imm <= decoded_imm_uj;
+ |{instr_lui, instr_auipc}:
+ decoded_imm <= mem_rdata_q[31:12] << 12;
+ |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
+ decoded_imm <= $signed(mem_rdata_q[31:20]);
+ is_beq_bne_blt_bge_bltu_bgeu:
+ decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
+ is_sb_sh_sw:
+ decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
+ default:
+ decoded_imm <= 1'bx;
+ endcase
+ end
+
+ if (!resetn) begin
+ is_beq_bne_blt_bge_bltu_bgeu <= 0;
+ is_compare <= 0;
+
+ instr_beq <= 0;
+ instr_bne <= 0;
+ instr_blt <= 0;
+ instr_bge <= 0;
+ instr_bltu <= 0;
+ instr_bgeu <= 0;
+
+ instr_addi <= 0;
+ instr_slti <= 0;
+ instr_sltiu <= 0;
+ instr_xori <= 0;
+ instr_ori <= 0;
+ instr_andi <= 0;
+
+ instr_add <= 0;
+ instr_sub <= 0;
+ instr_sll <= 0;
+ instr_slt <= 0;
+ instr_sltu <= 0;
+ instr_xor <= 0;
+ instr_srl <= 0;
+ instr_sra <= 0;
+ instr_or <= 0;
+ instr_and <= 0;
+ end
+ end
+
+
+ // Main State Machine
+
+ localparam cpu_state_trap = 8'b10000000;
+ localparam cpu_state_fetch = 8'b01000000;
+ localparam cpu_state_ld_rs1 = 8'b00100000;
+ localparam cpu_state_ld_rs2 = 8'b00010000;
+ localparam cpu_state_exec = 8'b00001000;
+ localparam cpu_state_shift = 8'b00000100;
+ localparam cpu_state_stmem = 8'b00000010;
+ localparam cpu_state_ldmem = 8'b00000001;
+
+ reg [7:0] cpu_state;
+ reg [1:0] irq_state;
+
+ `FORMAL_KEEP reg [127:0] dbg_ascii_state;
+
+ always @* begin
+ dbg_ascii_state = "";
+ if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
+ if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
+ if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
+ if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
+ if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
+ if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
+ if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
+ if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
+ end
+
+ reg set_mem_do_rinst;
+ reg set_mem_do_rdata;
+ reg set_mem_do_wdata;
+
+ reg latched_store;
+ reg latched_stalu;
+ reg latched_branch;
+ reg latched_compr;
+ reg latched_trace;
+ reg latched_is_lu;
+ reg latched_is_lh;
+ reg latched_is_lb;
+ reg [regindex_bits-1:0] latched_rd;
+
+ reg [31:0] current_pc;
+ assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
+
+ reg [3:0] pcpi_timeout_counter;
+ reg pcpi_timeout;
+
+ reg [31:0] next_irq_pending;
+ reg do_waitirq;
+
+ reg [31:0] alu_out, alu_out_q;
+ reg alu_out_0, alu_out_0_q;
+ reg alu_wait, alu_wait_2;
+
+ reg [31:0] alu_add_sub;
+ reg [31:0] alu_shl, alu_shr;
+ reg alu_eq, alu_ltu, alu_lts;
+
+ generate if (TWO_CYCLE_ALU) begin
+ always @(posedge clk) begin
+ alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+ alu_eq <= reg_op1 == reg_op2;
+ alu_lts <= $signed(reg_op1) < $signed(reg_op2);
+ alu_ltu <= reg_op1 < reg_op2;
+ alu_shl <= reg_op1 << reg_op2[4:0];
+ alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+ end
+ end else begin
+ always @* begin
+ alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+ alu_eq = reg_op1 == reg_op2;
+ alu_lts = $signed(reg_op1) < $signed(reg_op2);
+ alu_ltu = reg_op1 < reg_op2;
+ alu_shl = reg_op1 << reg_op2[4:0];
+ alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+ end
+ end endgenerate
+
+ always @* begin
+ alu_out_0 = 'bx;
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_beq:
+ alu_out_0 = alu_eq;
+ instr_bne:
+ alu_out_0 = !alu_eq;
+ instr_bge:
+ alu_out_0 = !alu_lts;
+ instr_bgeu:
+ alu_out_0 = !alu_ltu;
+ is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+ alu_out_0 = alu_lts;
+ is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+ alu_out_0 = alu_ltu;
+ endcase
+
+ alu_out = 'bx;
+ (* parallel_case, full_case *)
+ case (1'b1)
+ is_lui_auipc_jal_jalr_addi_add_sub:
+ alu_out = alu_add_sub;
+ is_compare:
+ alu_out = alu_out_0;
+ instr_xori || instr_xor:
+ alu_out = reg_op1 ^ reg_op2;
+ instr_ori || instr_or:
+ alu_out = reg_op1 | reg_op2;
+ instr_andi || instr_and:
+ alu_out = reg_op1 & reg_op2;
+ BARREL_SHIFTER && (instr_sll || instr_slli):
+ alu_out = alu_shl;
+ BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
+ alu_out = alu_shr;
+ endcase
+
+`ifdef RISCV_FORMAL_BLACKBOX_ALU
+ alu_out_0 = $anyseq;
+ alu_out = $anyseq;
+`endif
+ end
+
+ reg clear_prefetched_high_word_q;
+ always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
+
+ always @* begin
+ clear_prefetched_high_word = clear_prefetched_high_word_q;
+ if (!prefetched_high_word)
+ clear_prefetched_high_word = 0;
+ if (latched_branch || irq_state || !resetn)
+ clear_prefetched_high_word = COMPRESSED_ISA;
+ end
+
+ reg cpuregs_write;
+ reg [31:0] cpuregs_wrdata;
+ reg [31:0] cpuregs_rs1;
+ reg [31:0] cpuregs_rs2;
+ reg [regindex_bits-1:0] decoded_rs;
+
+ always @* begin
+ cpuregs_write = 0;
+ cpuregs_wrdata = 'bx;
+
+ if (cpu_state == cpu_state_fetch) begin
+ (* parallel_case *)
+ case (1'b1)
+ latched_branch: begin
+ cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
+ cpuregs_write = 1;
+ end
+ latched_store && !latched_branch: begin
+ cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
+ cpuregs_write = 1;
+ end
+ ENABLE_IRQ && irq_state[0]: begin
+ cpuregs_wrdata = reg_next_pc | latched_compr;
+ cpuregs_write = 1;
+ end
+ ENABLE_IRQ && irq_state[1]: begin
+ cpuregs_wrdata = irq_pending & ~irq_mask;
+ cpuregs_write = 1;
+ end
+ endcase
+ end
+ end
+
+`ifndef PICORV32_REGS
+ always @(posedge clk) begin
+ if (resetn && cpuregs_write && latched_rd)
+ cpuregs[latched_rd] <= cpuregs_wrdata;
+ end
+
+ always @* begin
+ decoded_rs = 'bx;
+ if (ENABLE_REGS_DUALPORT) begin
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+ cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
+ cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
+`else
+ cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
+ cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
+`endif
+ end else begin
+ decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+ cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
+`else
+ cpuregs_rs1 = decoded_rs ? $anyseq : 0;
+`endif
+ cpuregs_rs2 = cpuregs_rs1;
+ end
+ end
+`else
+ wire[31:0] cpuregs_rdata1;
+ wire[31:0] cpuregs_rdata2;
+
+ wire [5:0] cpuregs_waddr = latched_rd;
+ wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
+ wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
+
+ `PICORV32_REGS cpuregs (
+ .clk(clk),
+ .wen(resetn && cpuregs_write && latched_rd),
+ .waddr(cpuregs_waddr),
+ .raddr1(cpuregs_raddr1),
+ .raddr2(cpuregs_raddr2),
+ .wdata(cpuregs_wrdata),
+ .rdata1(cpuregs_rdata1),
+ .rdata2(cpuregs_rdata2)
+ );
+
+ always @* begin
+ decoded_rs = 'bx;
+ if (ENABLE_REGS_DUALPORT) begin
+ cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
+ cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
+ end else begin
+ decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+ cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
+ cpuregs_rs2 = cpuregs_rs1;
+ end
+ end
+`endif
+
+ assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
+
+ always @(posedge clk) begin
+ trap <= 0;
+ reg_sh <= 'bx;
+ reg_out <= 'bx;
+ set_mem_do_rinst = 0;
+ set_mem_do_rdata = 0;
+ set_mem_do_wdata = 0;
+
+ alu_out_0_q <= alu_out_0;
+ alu_out_q <= alu_out;
+
+ alu_wait <= 0;
+ alu_wait_2 <= 0;
+
+ if (launch_next_insn) begin
+ dbg_rs1val <= 'bx;
+ dbg_rs2val <= 'bx;
+ dbg_rs1val_valid <= 0;
+ dbg_rs2val_valid <= 0;
+ end
+
+ if (WITH_PCPI && CATCH_ILLINSN) begin
+ if (resetn && pcpi_valid && !pcpi_int_wait) begin
+ if (pcpi_timeout_counter)
+ pcpi_timeout_counter <= pcpi_timeout_counter - 1;
+ end else
+ pcpi_timeout_counter <= ~0;
+ pcpi_timeout <= !pcpi_timeout_counter;
+ end
+
+ if (ENABLE_COUNTERS) begin
+ count_cycle <= resetn ? count_cycle + 1 : 0;
+ if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
+ end else begin
+ count_cycle <= 'bx;
+ count_instr <= 'bx;
+ end
+
+ next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
+
+ if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
+ if (timer - 1 == 0)
+ next_irq_pending[irq_timer] = 1;
+ timer <= timer - 1;
+ end
+
+ if (ENABLE_IRQ) begin
+ next_irq_pending = next_irq_pending | irq;
+ end
+
+ decoder_trigger <= mem_do_rinst && mem_done;
+ decoder_trigger_q <= decoder_trigger;
+ decoder_pseudo_trigger <= 0;
+ decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
+ do_waitirq <= 0;
+
+ trace_valid <= 0;
+
+ if (!ENABLE_TRACE)
+ trace_data <= 'bx;
+
+ if (!resetn) begin
+ reg_pc <= PROGADDR_RESET;
+ reg_next_pc <= PROGADDR_RESET;
+ if (ENABLE_COUNTERS)
+ count_instr <= 0;
+ latched_store <= 0;
+ latched_stalu <= 0;
+ latched_branch <= 0;
+ latched_trace <= 0;
+ latched_is_lu <= 0;
+ latched_is_lh <= 0;
+ latched_is_lb <= 0;
+ pcpi_valid <= 0;
+ pcpi_timeout <= 0;
+ irq_active <= 0;
+ irq_delay <= 0;
+ irq_mask <= ~0;
+ next_irq_pending = 0;
+ irq_state <= 0;
+ eoi <= 0;
+ timer <= 0;
+ if (~STACKADDR) begin
+ latched_store <= 1;
+ latched_rd <= 2;
+ reg_out <= STACKADDR;
+ end
+ cpu_state <= cpu_state_fetch;
+ end else
+ (* parallel_case, full_case *)
+ case (cpu_state)
+ cpu_state_trap: begin
+ trap <= 1;
+ end
+
+ cpu_state_fetch: begin
+ mem_do_rinst <= !decoder_trigger && !do_waitirq;
+ mem_wordsize <= 0;
+
+ current_pc = reg_next_pc;
+
+ (* parallel_case *)
+ case (1'b1)
+ latched_branch: begin
+ current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
+ `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
+ end
+ latched_store && !latched_branch: begin
+ `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
+ end
+ ENABLE_IRQ && irq_state[0]: begin
+ current_pc = PROGADDR_IRQ;
+ irq_active <= 1;
+ mem_do_rinst <= 1;
+ end
+ ENABLE_IRQ && irq_state[1]: begin
+ eoi <= irq_pending & ~irq_mask;
+ next_irq_pending = next_irq_pending & irq_mask;
+ end
+ endcase
+
+ if (ENABLE_TRACE && latched_trace) begin
+ latched_trace <= 0;
+ trace_valid <= 1;
+ if (latched_branch)
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
+ else
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
+ end
+
+ reg_pc <= current_pc;
+ reg_next_pc <= current_pc;
+
+ latched_store <= 0;
+ latched_stalu <= 0;
+ latched_branch <= 0;
+ latched_is_lu <= 0;
+ latched_is_lh <= 0;
+ latched_is_lb <= 0;
+ latched_rd <= decoded_rd;
+ latched_compr <= compressed_instr;
+
+ if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
+ irq_state <=
+ irq_state == 2'b00 ? 2'b01 :
+ irq_state == 2'b01 ? 2'b10 : 2'b00;
+ latched_compr <= latched_compr;
+ if (ENABLE_IRQ_QREGS)
+ latched_rd <= irqregs_offset | irq_state[0];
+ else
+ latched_rd <= irq_state[0] ? 4 : 3;
+ end else
+ if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
+ if (irq_pending) begin
+ latched_store <= 1;
+ reg_out <= irq_pending;
+ reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+ mem_do_rinst <= 1;
+ end else
+ do_waitirq <= 1;
+ end else
+ if (decoder_trigger) begin
+ `debug($display("-- %-0t", $time);)
+ irq_delay <= irq_active;
+ reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+ if (ENABLE_TRACE)
+ latched_trace <= 1;
+ if (ENABLE_COUNTERS) begin
+ count_instr <= count_instr + 1;
+ if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
+ end
+ if (instr_jal) begin
+ mem_do_rinst <= 1;
+ reg_next_pc <= current_pc + decoded_imm_uj;
+ latched_branch <= 1;
+ end else begin
+ mem_do_rinst <= 0;
+ mem_do_prefetch <= !instr_jalr && !instr_retirq;
+ cpu_state <= cpu_state_ld_rs1;
+ end
+ end
+ end
+
+ cpu_state_ld_rs1: begin
+ reg_op1 <= 'bx;
+ reg_op2 <= 'bx;
+
+ (* parallel_case *)
+ case (1'b1)
+ (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
+ if (WITH_PCPI) begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ if (ENABLE_REGS_DUALPORT) begin
+ pcpi_valid <= 1;
+ `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+ reg_sh <= cpuregs_rs2;
+ reg_op2 <= cpuregs_rs2;
+ dbg_rs2val <= cpuregs_rs2;
+ dbg_rs2val_valid <= 1;
+ if (pcpi_int_ready) begin
+ mem_do_rinst <= 1;
+ pcpi_valid <= 0;
+ reg_out <= pcpi_int_rd;
+ latched_store <= pcpi_int_wr;
+ cpu_state <= cpu_state_fetch;
+ end else
+ if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+ pcpi_valid <= 0;
+ `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+ next_irq_pending[irq_ebreak] = 1;
+ cpu_state <= cpu_state_fetch;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end else begin
+ cpu_state <= cpu_state_ld_rs2;
+ end
+ end else begin
+ `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+ next_irq_pending[irq_ebreak] = 1;
+ cpu_state <= cpu_state_fetch;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end
+ ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_rdcycle:
+ reg_out <= count_cycle[31:0];
+ instr_rdcycleh && ENABLE_COUNTERS64:
+ reg_out <= count_cycle[63:32];
+ instr_rdinstr:
+ reg_out <= count_instr[31:0];
+ instr_rdinstrh && ENABLE_COUNTERS64:
+ reg_out <= count_instr[63:32];
+ endcase
+ latched_store <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ is_lui_auipc_jal: begin
+ reg_op1 <= instr_lui ? 0 : reg_pc;
+ reg_op2 <= decoded_imm;
+ if (TWO_CYCLE_ALU)
+ alu_wait <= 1;
+ else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_out <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ latched_store <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_out <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ latched_rd <= latched_rd | irqregs_offset;
+ latched_store <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && instr_retirq: begin
+ eoi <= 0;
+ irq_active <= 0;
+ latched_branch <= 1;
+ latched_store <= 1;
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && instr_maskirq: begin
+ latched_store <= 1;
+ reg_out <= irq_mask;
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ irq_mask <= cpuregs_rs1 | MASKED_IRQ;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
+ latched_store <= 1;
+ reg_out <= timer;
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ timer <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ is_lb_lh_lw_lbu_lhu && !instr_trap: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ cpu_state <= cpu_state_ldmem;
+ mem_do_rinst <= 1;
+ end
+ is_slli_srli_srai && !BARREL_SHIFTER: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ reg_sh <= decoded_rs2;
+ cpu_state <= cpu_state_shift;
+ end
+ is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
+ if (TWO_CYCLE_ALU)
+ alu_wait <= 1;
+ else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ default: begin
+ `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+ reg_op1 <= cpuregs_rs1;
+ dbg_rs1val <= cpuregs_rs1;
+ dbg_rs1val_valid <= 1;
+ if (ENABLE_REGS_DUALPORT) begin
+ `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+ reg_sh <= cpuregs_rs2;
+ reg_op2 <= cpuregs_rs2;
+ dbg_rs2val <= cpuregs_rs2;
+ dbg_rs2val_valid <= 1;
+ (* parallel_case *)
+ case (1'b1)
+ is_sb_sh_sw: begin
+ cpu_state <= cpu_state_stmem;
+ mem_do_rinst <= 1;
+ end
+ is_sll_srl_sra && !BARREL_SHIFTER: begin
+ cpu_state <= cpu_state_shift;
+ end
+ default: begin
+ if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+ alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+ alu_wait <= 1;
+ end else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ endcase
+ end else
+ cpu_state <= cpu_state_ld_rs2;
+ end
+ endcase
+ end
+
+ cpu_state_ld_rs2: begin
+ `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+ reg_sh <= cpuregs_rs2;
+ reg_op2 <= cpuregs_rs2;
+ dbg_rs2val <= cpuregs_rs2;
+ dbg_rs2val_valid <= 1;
+
+ (* parallel_case *)
+ case (1'b1)
+ WITH_PCPI && instr_trap: begin
+ pcpi_valid <= 1;
+ if (pcpi_int_ready) begin
+ mem_do_rinst <= 1;
+ pcpi_valid <= 0;
+ reg_out <= pcpi_int_rd;
+ latched_store <= pcpi_int_wr;
+ cpu_state <= cpu_state_fetch;
+ end else
+ if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+ pcpi_valid <= 0;
+ `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+ next_irq_pending[irq_ebreak] = 1;
+ cpu_state <= cpu_state_fetch;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end
+ is_sb_sh_sw: begin
+ cpu_state <= cpu_state_stmem;
+ mem_do_rinst <= 1;
+ end
+ is_sll_srl_sra && !BARREL_SHIFTER: begin
+ cpu_state <= cpu_state_shift;
+ end
+ default: begin
+ if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+ alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+ alu_wait <= 1;
+ end else
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_exec;
+ end
+ endcase
+ end
+
+ cpu_state_exec: begin
+ reg_out <= reg_pc + decoded_imm;
+ if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
+ mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
+ alu_wait <= alu_wait_2;
+ end else
+ if (is_beq_bne_blt_bge_bltu_bgeu) begin
+ latched_rd <= 0;
+ latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+ latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+ if (mem_done)
+ cpu_state <= cpu_state_fetch;
+ if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
+ decoder_trigger <= 0;
+ set_mem_do_rinst = 1;
+ end
+ end else begin
+ latched_branch <= instr_jalr;
+ latched_store <= 1;
+ latched_stalu <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ end
+
+ cpu_state_shift: begin
+ latched_store <= 1;
+ if (reg_sh == 0) begin
+ reg_out <= reg_op1;
+ mem_do_rinst <= mem_do_prefetch;
+ cpu_state <= cpu_state_fetch;
+ end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
+ instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
+ instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
+ endcase
+ reg_sh <= reg_sh - 4;
+ end else begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
+ instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
+ instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
+ endcase
+ reg_sh <= reg_sh - 1;
+ end
+ end
+
+ cpu_state_stmem: begin
+ if (ENABLE_TRACE)
+ reg_out <= reg_op2;
+ if (!mem_do_prefetch || mem_done) begin
+ if (!mem_do_wdata) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_sb: mem_wordsize <= 2;
+ instr_sh: mem_wordsize <= 1;
+ instr_sw: mem_wordsize <= 0;
+ endcase
+ if (ENABLE_TRACE) begin
+ trace_valid <= 1;
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+ end
+ reg_op1 <= reg_op1 + decoded_imm;
+ set_mem_do_wdata = 1;
+ end
+ if (!mem_do_prefetch && mem_done) begin
+ cpu_state <= cpu_state_fetch;
+ decoder_trigger <= 1;
+ decoder_pseudo_trigger <= 1;
+ end
+ end
+ end
+
+ cpu_state_ldmem: begin
+ latched_store <= 1;
+ if (!mem_do_prefetch || mem_done) begin
+ if (!mem_do_rdata) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ instr_lb || instr_lbu: mem_wordsize <= 2;
+ instr_lh || instr_lhu: mem_wordsize <= 1;
+ instr_lw: mem_wordsize <= 0;
+ endcase
+ latched_is_lu <= is_lbu_lhu_lw;
+ latched_is_lh <= instr_lh;
+ latched_is_lb <= instr_lb;
+ if (ENABLE_TRACE) begin
+ trace_valid <= 1;
+ trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+ end
+ reg_op1 <= reg_op1 + decoded_imm;
+ set_mem_do_rdata = 1;
+ end
+ if (!mem_do_prefetch && mem_done) begin
+ (* parallel_case, full_case *)
+ case (1'b1)
+ latched_is_lu: reg_out <= mem_rdata_word;
+ latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
+ latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
+ endcase
+ decoder_trigger <= 1;
+ decoder_pseudo_trigger <= 1;
+ cpu_state <= cpu_state_fetch;
+ end
+ end
+ end
+ endcase
+
+ if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
+ if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
+ `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
+ if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+ next_irq_pending[irq_buserror] = 1;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ if (mem_wordsize == 1 && reg_op1[0] != 0) begin
+ `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
+ if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+ next_irq_pending[irq_buserror] = 1;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ end
+ if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
+ `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
+ if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+ next_irq_pending[irq_buserror] = 1;
+ end else
+ cpu_state <= cpu_state_trap;
+ end
+ if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
+ cpu_state <= cpu_state_trap;
+ end
+
+ if (!resetn || mem_done) begin
+ mem_do_prefetch <= 0;
+ mem_do_rinst <= 0;
+ mem_do_rdata <= 0;
+ mem_do_wdata <= 0;
+ end
+
+ if (set_mem_do_rinst)
+ mem_do_rinst <= 1;
+ if (set_mem_do_rdata)
+ mem_do_rdata <= 1;
+ if (set_mem_do_wdata)
+ mem_do_wdata <= 1;
+
+ irq_pending <= next_irq_pending & ~MASKED_IRQ;
+
+ if (!CATCH_MISALIGN) begin
+ if (COMPRESSED_ISA) begin
+ reg_pc[0] <= 0;
+ reg_next_pc[0] <= 0;
+ end else begin
+ reg_pc[1:0] <= 0;
+ reg_next_pc[1:0] <= 0;
+ end
+ end
+ current_pc = 'bx;
+ end
+
+`ifdef RISCV_FORMAL
+ reg dbg_irq_call;
+ reg dbg_irq_enter;
+ reg [31:0] dbg_irq_ret;
+ always @(posedge clk) begin
+ rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
+ rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
+
+ rvfi_insn <= dbg_insn_opcode;
+ rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
+ rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
+ rvfi_pc_rdata <= dbg_insn_addr;
+ rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
+ rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
+ rvfi_trap <= trap;
+ rvfi_halt <= trap;
+ rvfi_intr <= dbg_irq_enter;
+
+ if (!resetn) begin
+ dbg_irq_call <= 0;
+ dbg_irq_enter <= 0;
+ end else
+ if (rvfi_valid) begin
+ dbg_irq_call <= 0;
+ dbg_irq_enter <= dbg_irq_call;
+ end else
+ if (irq_state == 1) begin
+ dbg_irq_call <= 1;
+ dbg_irq_ret <= next_pc;
+ end
+
+ if (!resetn) begin
+ rvfi_rd_addr <= 0;
+ rvfi_rd_wdata <= 0;
+ end else
+ if (cpuregs_write && !irq_state) begin
+ rvfi_rd_addr <= latched_rd;
+ rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
+ end else
+ if (rvfi_valid) begin
+ rvfi_rd_addr <= 0;
+ rvfi_rd_wdata <= 0;
+ end
+
+ casez (dbg_insn_opcode)
+ 32'b 0000000_?????_000??_???_?????_0001011: begin // getq
+ rvfi_rs1_addr <= 0;
+ rvfi_rs1_rdata <= 0;
+ end
+ 32'b 0000001_?????_?????_???_000??_0001011: begin // setq
+ rvfi_rd_addr <= 0;
+ rvfi_rd_wdata <= 0;
+ end
+ 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
+ rvfi_rs1_addr <= 0;
+ rvfi_rs1_rdata <= 0;
+ end
+ endcase
+
+ if (!dbg_irq_call) begin
+ if (dbg_mem_instr) begin
+ rvfi_mem_addr <= 0;
+ rvfi_mem_rmask <= 0;
+ rvfi_mem_wmask <= 0;
+ rvfi_mem_rdata <= 0;
+ rvfi_mem_wdata <= 0;
+ end else
+ if (dbg_mem_valid && dbg_mem_ready) begin
+ rvfi_mem_addr <= dbg_mem_addr;
+ rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
+ rvfi_mem_wmask <= dbg_mem_wstrb;
+ rvfi_mem_rdata <= dbg_mem_rdata;
+ rvfi_mem_wdata <= dbg_mem_wdata;
+ end
+ end
+ end
+
+ always @* begin
+ rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
+ end
+`endif
+
+ // Formal Verification
+`ifdef FORMAL
+ reg [3:0] last_mem_nowait;
+ always @(posedge clk)
+ last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
+
+ // stall the memory interface for max 4 cycles
+ restrict property (|last_mem_nowait || mem_ready || !mem_valid);
+
+ // resetn low in first cycle, after that resetn high
+ restrict property (resetn != $initstate);
+
+ // this just makes it much easier to read traces. uncomment as needed.
+ // assume property (mem_valid || !mem_ready);
+
+ reg ok;
+ always @* begin
+ if (resetn) begin
+ // instruction fetches are read-only
+ if (mem_valid && mem_instr)
+ assert (mem_wstrb == 0);
+
+ // cpu_state must be valid
+ ok = 0;
+ if (cpu_state == cpu_state_trap) ok = 1;
+ if (cpu_state == cpu_state_fetch) ok = 1;
+ if (cpu_state == cpu_state_ld_rs1) ok = 1;
+ if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
+ if (cpu_state == cpu_state_exec) ok = 1;
+ if (cpu_state == cpu_state_shift) ok = 1;
+ if (cpu_state == cpu_state_stmem) ok = 1;
+ if (cpu_state == cpu_state_ldmem) ok = 1;
+ assert (ok);
+ end
+ end
+
+ reg last_mem_la_read = 0;
+ reg last_mem_la_write = 0;
+ reg [31:0] last_mem_la_addr;
+ reg [31:0] last_mem_la_wdata;
+ reg [3:0] last_mem_la_wstrb = 0;
+
+ always @(posedge clk) begin
+ last_mem_la_read <= mem_la_read;
+ last_mem_la_write <= mem_la_write;
+ last_mem_la_addr <= mem_la_addr;
+ last_mem_la_wdata <= mem_la_wdata;
+ last_mem_la_wstrb <= mem_la_wstrb;
+
+ if (last_mem_la_read) begin
+ assert(mem_valid);
+ assert(mem_addr == last_mem_la_addr);
+ assert(mem_wstrb == 0);
+ end
+ if (last_mem_la_write) begin
+ assert(mem_valid);
+ assert(mem_addr == last_mem_la_addr);
+ assert(mem_wdata == last_mem_la_wdata);
+ assert(mem_wstrb == last_mem_la_wstrb);
+ end
+ if (mem_la_read || mem_la_write) begin
+ assert(!mem_valid || mem_ready);
+ end
+ end
+`endif
+endmodule
+
+// This is a simple example implementation of PICORV32_REGS.
+// Use the PICORV32_REGS mechanism if you want to use custom
+// memory resources to implement the processor register file.
+// Note that your implementation must match the requirements of
+// the PicoRV32 configuration. (e.g. QREGS, etc)
+module picorv32_regs (
+ input clk, wen,
+ input [5:0] waddr,
+ input [5:0] raddr1,
+ input [5:0] raddr2,
+ input [31:0] wdata,
+ output [31:0] rdata1,
+ output [31:0] rdata2
+);
+ reg [31:0] regs [0:30];
+
+ always @(posedge clk)
+ if (wen) regs[~waddr[4:0]] <= wdata;
+
+ assign rdata1 = regs[~raddr1[4:0]];
+ assign rdata2 = regs[~raddr2[4:0]];
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_mul
+ ***************************************************************/
+
+module picorv32_pcpi_mul #(
+ parameter STEPS_AT_ONCE = 1,
+ parameter CARRY_CHAIN = 4
+) (
+ input clk, resetn,
+
+ input pcpi_valid,
+ input [31:0] pcpi_insn,
+ input [31:0] pcpi_rs1,
+ input [31:0] pcpi_rs2,
+ output reg pcpi_wr,
+ output reg [31:0] pcpi_rd,
+ output reg pcpi_wait,
+ output reg pcpi_ready
+);
+ reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+ wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+ wire instr_rs2_signed = |{instr_mulh};
+
+ reg pcpi_wait_q;
+ wire mul_start = pcpi_wait && !pcpi_wait_q;
+
+ always @(posedge clk) begin
+ instr_mul <= 0;
+ instr_mulh <= 0;
+ instr_mulhsu <= 0;
+ instr_mulhu <= 0;
+
+ if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+ case (pcpi_insn[14:12])
+ 3'b000: instr_mul <= 1;
+ 3'b001: instr_mulh <= 1;
+ 3'b010: instr_mulhsu <= 1;
+ 3'b011: instr_mulhu <= 1;
+ endcase
+ end
+
+ pcpi_wait <= instr_any_mul;
+ pcpi_wait_q <= pcpi_wait;
+ end
+
+ reg [63:0] rs1, rs2, rd, rdx;
+ reg [63:0] next_rs1, next_rs2, this_rs2;
+ reg [63:0] next_rd, next_rdx, next_rdt;
+ reg [6:0] mul_counter;
+ reg mul_waiting;
+ reg mul_finish;
+ integer i, j;
+
+ // carry save accumulator
+ always @* begin
+ next_rd = rd;
+ next_rdx = rdx;
+ next_rs1 = rs1;
+ next_rs2 = rs2;
+
+ for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
+ this_rs2 = next_rs1[0] ? next_rs2 : 0;
+ if (CARRY_CHAIN == 0) begin
+ next_rdt = next_rd ^ next_rdx ^ this_rs2;
+ next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
+ next_rd = next_rdt;
+ end else begin
+ next_rdt = 0;
+ for (j = 0; j < 64; j = j + CARRY_CHAIN)
+ {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
+ next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
+ next_rdx = next_rdt << 1;
+ end
+ next_rs1 = next_rs1 >> 1;
+ next_rs2 = next_rs2 << 1;
+ end
+ end
+
+ always @(posedge clk) begin
+ mul_finish <= 0;
+ if (!resetn) begin
+ mul_waiting <= 1;
+ end else
+ if (mul_waiting) begin
+ if (instr_rs1_signed)
+ rs1 <= $signed(pcpi_rs1);
+ else
+ rs1 <= $unsigned(pcpi_rs1);
+
+ if (instr_rs2_signed)
+ rs2 <= $signed(pcpi_rs2);
+ else
+ rs2 <= $unsigned(pcpi_rs2);
+
+ rd <= 0;
+ rdx <= 0;
+ mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
+ mul_waiting <= !mul_start;
+ end else begin
+ rd <= next_rd;
+ rdx <= next_rdx;
+ rs1 <= next_rs1;
+ rs2 <= next_rs2;
+
+ mul_counter <= mul_counter - STEPS_AT_ONCE;
+ if (mul_counter[6]) begin
+ mul_finish <= 1;
+ mul_waiting <= 1;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ pcpi_wr <= 0;
+ pcpi_ready <= 0;
+ if (mul_finish && resetn) begin
+ pcpi_wr <= 1;
+ pcpi_ready <= 1;
+ pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
+ end
+ end
+endmodule
+
+module picorv32_pcpi_fast_mul #(
+ parameter EXTRA_MUL_FFS = 0,
+ parameter EXTRA_INSN_FFS = 0,
+ parameter MUL_CLKGATE = 0
+) (
+ input clk, resetn,
+
+ input pcpi_valid,
+ input [31:0] pcpi_insn,
+ input [31:0] pcpi_rs1,
+ input [31:0] pcpi_rs2,
+ output pcpi_wr,
+ output [31:0] pcpi_rd,
+ output pcpi_wait,
+ output pcpi_ready
+);
+ reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+ wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+ wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+ wire instr_rs2_signed = |{instr_mulh};
+
+ reg shift_out;
+ reg [3:0] active;
+ reg [32:0] rs1, rs2, rs1_q, rs2_q;
+ reg [63:0] rd, rd_q;
+
+ wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
+ reg pcpi_insn_valid_q;
+
+ always @* begin
+ instr_mul = 0;
+ instr_mulh = 0;
+ instr_mulhsu = 0;
+ instr_mulhu = 0;
+
+ if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
+ case (pcpi_insn[14:12])
+ 3'b000: instr_mul = 1;
+ 3'b001: instr_mulh = 1;
+ 3'b010: instr_mulhsu = 1;
+ 3'b011: instr_mulhu = 1;
+ endcase
+ end
+ end
+
+ always @(posedge clk) begin
+ pcpi_insn_valid_q <= pcpi_insn_valid;
+ if (!MUL_CLKGATE || active[0]) begin
+ rs1_q <= rs1;
+ rs2_q <= rs2;
+ end
+ if (!MUL_CLKGATE || active[1]) begin
+ rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
+ end
+ if (!MUL_CLKGATE || active[2]) begin
+ rd_q <= rd;
+ end
+ end
+
+ always @(posedge clk) begin
+ if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
+ if (instr_rs1_signed)
+ rs1 <= $signed(pcpi_rs1);
+ else
+ rs1 <= $unsigned(pcpi_rs1);
+
+ if (instr_rs2_signed)
+ rs2 <= $signed(pcpi_rs2);
+ else
+ rs2 <= $unsigned(pcpi_rs2);
+ active[0] <= 1;
+ end else begin
+ active[0] <= 0;
+ end
+
+ active[3:1] <= active;
+ shift_out <= instr_any_mulh;
+
+ if (!resetn)
+ active <= 0;
+ end
+
+ assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
+ assign pcpi_wait = 0;
+ assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
+`ifdef RISCV_FORMAL_ALTOPS
+ assign pcpi_rd =
+ instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
+ instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
+ instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
+ instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
+`else
+ assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
+`endif
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_div
+ ***************************************************************/
+
+module picorv32_pcpi_div (
+ input clk, resetn,
+
+ input pcpi_valid,
+ input [31:0] pcpi_insn,
+ input [31:0] pcpi_rs1,
+ input [31:0] pcpi_rs2,
+ output reg pcpi_wr,
+ output reg [31:0] pcpi_rd,
+ output reg pcpi_wait,
+ output reg pcpi_ready
+);
+ reg instr_div, instr_divu, instr_rem, instr_remu;
+ wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
+
+ reg pcpi_wait_q;
+ wire start = pcpi_wait && !pcpi_wait_q;
+
+ always @(posedge clk) begin
+ instr_div <= 0;
+ instr_divu <= 0;
+ instr_rem <= 0;
+ instr_remu <= 0;
+
+ if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+ case (pcpi_insn[14:12])
+ 3'b100: instr_div <= 1;
+ 3'b101: instr_divu <= 1;
+ 3'b110: instr_rem <= 1;
+ 3'b111: instr_remu <= 1;
+ endcase
+ end
+
+ pcpi_wait <= instr_any_div_rem && resetn;
+ pcpi_wait_q <= pcpi_wait && resetn;
+ end
+
+ reg [31:0] dividend;
+ reg [62:0] divisor;
+ reg [31:0] quotient;
+ reg [31:0] quotient_msk;
+ reg running;
+ reg outsign;
+
+ always @(posedge clk) begin
+ pcpi_ready <= 0;
+ pcpi_wr <= 0;
+ pcpi_rd <= 'bx;
+
+ if (!resetn) begin
+ running <= 0;
+ end else
+ if (start) begin
+ running <= 1;
+ dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
+ divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
+ outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
+ quotient <= 0;
+ quotient_msk <= 1 << 31;
+ end else
+ if (!quotient_msk && running) begin
+ running <= 0;
+ pcpi_ready <= 1;
+ pcpi_wr <= 1;
+`ifdef RISCV_FORMAL_ALTOPS
+ case (1)
+ instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
+ instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
+ instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
+ instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
+ endcase
+`else
+ if (instr_div || instr_divu)
+ pcpi_rd <= outsign ? -quotient : quotient;
+ else
+ pcpi_rd <= outsign ? -dividend : dividend;
+`endif
+ end else begin
+ if (divisor <= dividend) begin
+ dividend <= dividend - divisor;
+ quotient <= quotient | quotient_msk;
+ end
+ divisor <= divisor >> 1;
+`ifdef RISCV_FORMAL_ALTOPS
+ quotient_msk <= quotient_msk >> 5;
+`else
+ quotient_msk <= quotient_msk >> 1;
+`endif
+ end
+ end
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi
+ ***************************************************************/
+
+module picorv32_axi #(
+ parameter [ 0:0] ENABLE_COUNTERS = 1,
+ parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+ parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+ parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+ parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+ parameter [ 0:0] BARREL_SHIFTER = 0,
+ parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+ parameter [ 0:0] TWO_CYCLE_ALU = 0,
+ parameter [ 0:0] COMPRESSED_ISA = 0,
+ parameter [ 0:0] CATCH_MISALIGN = 1,
+ parameter [ 0:0] CATCH_ILLINSN = 1,
+ parameter [ 0:0] ENABLE_PCPI = 0,
+ parameter [ 0:0] ENABLE_MUL = 0,
+ parameter [ 0:0] ENABLE_FAST_MUL = 0,
+ parameter [ 0:0] ENABLE_DIV = 0,
+ parameter [ 0:0] ENABLE_IRQ = 0,
+ parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+ parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+ parameter [ 0:0] ENABLE_TRACE = 0,
+ parameter [ 0:0] REGS_INIT_ZERO = 0,
+ parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+ parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+ parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+ parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+ parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+ input clk, resetn,
+ output trap,
+
+ // AXI4-lite master memory interface
+
+ output mem_axi_awvalid,
+ input mem_axi_awready,
+ output [31:0] mem_axi_awaddr,
+ output [ 2:0] mem_axi_awprot,
+
+ output mem_axi_wvalid,
+ input mem_axi_wready,
+ output [31:0] mem_axi_wdata,
+ output [ 3:0] mem_axi_wstrb,
+
+ input mem_axi_bvalid,
+ output mem_axi_bready,
+
+ output mem_axi_arvalid,
+ input mem_axi_arready,
+ output [31:0] mem_axi_araddr,
+ output [ 2:0] mem_axi_arprot,
+
+ input mem_axi_rvalid,
+ output mem_axi_rready,
+ input [31:0] mem_axi_rdata,
+
+ // Pico Co-Processor Interface (PCPI)
+ output pcpi_valid,
+ output [31:0] pcpi_insn,
+ output [31:0] pcpi_rs1,
+ output [31:0] pcpi_rs2,
+ input pcpi_wr,
+ input [31:0] pcpi_rd,
+ input pcpi_wait,
+ input pcpi_ready,
+
+ // IRQ interface
+ input [31:0] irq,
+ output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+ output rvfi_valid,
+ output [63:0] rvfi_order,
+ output [31:0] rvfi_insn,
+ output rvfi_trap,
+ output rvfi_halt,
+ output rvfi_intr,
+ output [ 4:0] rvfi_rs1_addr,
+ output [ 4:0] rvfi_rs2_addr,
+ output [31:0] rvfi_rs1_rdata,
+ output [31:0] rvfi_rs2_rdata,
+ output [ 4:0] rvfi_rd_addr,
+ output [31:0] rvfi_rd_wdata,
+ output [31:0] rvfi_pc_rdata,
+ output [31:0] rvfi_pc_wdata,
+ output [31:0] rvfi_mem_addr,
+ output [ 3:0] rvfi_mem_rmask,
+ output [ 3:0] rvfi_mem_wmask,
+ output [31:0] rvfi_mem_rdata,
+ output [31:0] rvfi_mem_wdata,
+`endif
+
+ // Trace Interface
+ output trace_valid,
+ output [35:0] trace_data
+);
+ wire mem_valid;
+ wire [31:0] mem_addr;
+ wire [31:0] mem_wdata;
+ wire [ 3:0] mem_wstrb;
+ wire mem_instr;
+ wire mem_ready;
+ wire [31:0] mem_rdata;
+
+ picorv32_axi_adapter axi_adapter (
+ .clk (clk ),
+ .resetn (resetn ),
+ .mem_axi_awvalid(mem_axi_awvalid),
+ .mem_axi_awready(mem_axi_awready),
+ .mem_axi_awaddr (mem_axi_awaddr ),
+ .mem_axi_awprot (mem_axi_awprot ),
+ .mem_axi_wvalid (mem_axi_wvalid ),
+ .mem_axi_wready (mem_axi_wready ),
+ .mem_axi_wdata (mem_axi_wdata ),
+ .mem_axi_wstrb (mem_axi_wstrb ),
+ .mem_axi_bvalid (mem_axi_bvalid ),
+ .mem_axi_bready (mem_axi_bready ),
+ .mem_axi_arvalid(mem_axi_arvalid),
+ .mem_axi_arready(mem_axi_arready),
+ .mem_axi_araddr (mem_axi_araddr ),
+ .mem_axi_arprot (mem_axi_arprot ),
+ .mem_axi_rvalid (mem_axi_rvalid ),
+ .mem_axi_rready (mem_axi_rready ),
+ .mem_axi_rdata (mem_axi_rdata ),
+ .mem_valid (mem_valid ),
+ .mem_instr (mem_instr ),
+ .mem_ready (mem_ready ),
+ .mem_addr (mem_addr ),
+ .mem_wdata (mem_wdata ),
+ .mem_wstrb (mem_wstrb ),
+ .mem_rdata (mem_rdata )
+ );
+
+ picorv32 #(
+ .ENABLE_COUNTERS (ENABLE_COUNTERS ),
+ .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
+ .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
+ .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+ .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
+ .BARREL_SHIFTER (BARREL_SHIFTER ),
+ .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
+ .TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
+ .COMPRESSED_ISA (COMPRESSED_ISA ),
+ .CATCH_MISALIGN (CATCH_MISALIGN ),
+ .CATCH_ILLINSN (CATCH_ILLINSN ),
+ .ENABLE_PCPI (ENABLE_PCPI ),
+ .ENABLE_MUL (ENABLE_MUL ),
+ .ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
+ .ENABLE_DIV (ENABLE_DIV ),
+ .ENABLE_IRQ (ENABLE_IRQ ),
+ .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
+ .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
+ .ENABLE_TRACE (ENABLE_TRACE ),
+ .REGS_INIT_ZERO (REGS_INIT_ZERO ),
+ .MASKED_IRQ (MASKED_IRQ ),
+ .LATCHED_IRQ (LATCHED_IRQ ),
+ .PROGADDR_RESET (PROGADDR_RESET ),
+ .PROGADDR_IRQ (PROGADDR_IRQ ),
+ .STACKADDR (STACKADDR )
+ ) picorv32_core (
+ .clk (clk ),
+ .resetn (resetn),
+ .trap (trap ),
+
+ .mem_valid(mem_valid),
+ .mem_addr (mem_addr ),
+ .mem_wdata(mem_wdata),
+ .mem_wstrb(mem_wstrb),
+ .mem_instr(mem_instr),
+ .mem_ready(mem_ready),
+ .mem_rdata(mem_rdata),
+
+ .pcpi_valid(pcpi_valid),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_wr ),
+ .pcpi_rd (pcpi_rd ),
+ .pcpi_wait (pcpi_wait ),
+ .pcpi_ready(pcpi_ready),
+
+ .irq(irq),
+ .eoi(eoi),
+
+`ifdef RISCV_FORMAL
+ .rvfi_valid (rvfi_valid ),
+ .rvfi_order (rvfi_order ),
+ .rvfi_insn (rvfi_insn ),
+ .rvfi_trap (rvfi_trap ),
+ .rvfi_halt (rvfi_halt ),
+ .rvfi_intr (rvfi_intr ),
+ .rvfi_rs1_addr (rvfi_rs1_addr ),
+ .rvfi_rs2_addr (rvfi_rs2_addr ),
+ .rvfi_rs1_rdata(rvfi_rs1_rdata),
+ .rvfi_rs2_rdata(rvfi_rs2_rdata),
+ .rvfi_rd_addr (rvfi_rd_addr ),
+ .rvfi_rd_wdata (rvfi_rd_wdata ),
+ .rvfi_pc_rdata (rvfi_pc_rdata ),
+ .rvfi_pc_wdata (rvfi_pc_wdata ),
+ .rvfi_mem_addr (rvfi_mem_addr ),
+ .rvfi_mem_rmask(rvfi_mem_rmask),
+ .rvfi_mem_wmask(rvfi_mem_wmask),
+ .rvfi_mem_rdata(rvfi_mem_rdata),
+ .rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+ .trace_valid(trace_valid),
+ .trace_data (trace_data)
+ );
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi_adapter
+ ***************************************************************/
+
+module picorv32_axi_adapter (
+ input clk, resetn,
+
+ // AXI4-lite master memory interface
+
+ output mem_axi_awvalid,
+ input mem_axi_awready,
+ output [31:0] mem_axi_awaddr,
+ output [ 2:0] mem_axi_awprot,
+
+ output mem_axi_wvalid,
+ input mem_axi_wready,
+ output [31:0] mem_axi_wdata,
+ output [ 3:0] mem_axi_wstrb,
+
+ input mem_axi_bvalid,
+ output mem_axi_bready,
+
+ output mem_axi_arvalid,
+ input mem_axi_arready,
+ output [31:0] mem_axi_araddr,
+ output [ 2:0] mem_axi_arprot,
+
+ input mem_axi_rvalid,
+ output mem_axi_rready,
+ input [31:0] mem_axi_rdata,
+
+ // Native PicoRV32 memory interface
+
+ input mem_valid,
+ input mem_instr,
+ output mem_ready,
+ input [31:0] mem_addr,
+ input [31:0] mem_wdata,
+ input [ 3:0] mem_wstrb,
+ output [31:0] mem_rdata
+);
+ reg ack_awvalid;
+ reg ack_arvalid;
+ reg ack_wvalid;
+ reg xfer_done;
+
+ assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
+ assign mem_axi_awaddr = mem_addr;
+ assign mem_axi_awprot = 0;
+
+ assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
+ assign mem_axi_araddr = mem_addr;
+ assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
+
+ assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
+ assign mem_axi_wdata = mem_wdata;
+ assign mem_axi_wstrb = mem_wstrb;
+
+ assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
+ assign mem_axi_bready = mem_valid && |mem_wstrb;
+ assign mem_axi_rready = mem_valid && !mem_wstrb;
+ assign mem_rdata = mem_axi_rdata;
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ ack_awvalid <= 0;
+ end else begin
+ xfer_done <= mem_valid && mem_ready;
+ if (mem_axi_awready && mem_axi_awvalid)
+ ack_awvalid <= 1;
+ if (mem_axi_arready && mem_axi_arvalid)
+ ack_arvalid <= 1;
+ if (mem_axi_wready && mem_axi_wvalid)
+ ack_wvalid <= 1;
+ if (xfer_done || !mem_valid) begin
+ ack_awvalid <= 0;
+ ack_arvalid <= 0;
+ ack_wvalid <= 0;
+ end
+ end
+ end
+endmodule
+
+
+/***************************************************************
+ * picorv32_wb
+ ***************************************************************/
+
+module picorv32_wb #(
+ parameter [ 0:0] ENABLE_COUNTERS = 1,
+ parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+ parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+ parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+ parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+ parameter [ 0:0] BARREL_SHIFTER = 0,
+ parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+ parameter [ 0:0] TWO_CYCLE_ALU = 0,
+ parameter [ 0:0] COMPRESSED_ISA = 0,
+ parameter [ 0:0] CATCH_MISALIGN = 1,
+ parameter [ 0:0] CATCH_ILLINSN = 1,
+ parameter [ 0:0] ENABLE_PCPI = 0,
+ parameter [ 0:0] ENABLE_MUL = 0,
+ parameter [ 0:0] ENABLE_FAST_MUL = 0,
+ parameter [ 0:0] ENABLE_DIV = 0,
+ parameter [ 0:0] ENABLE_IRQ = 0,
+ parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+ parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+ parameter [ 0:0] ENABLE_TRACE = 0,
+ parameter [ 0:0] REGS_INIT_ZERO = 0,
+ parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+ parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+ parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+ parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+ parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+ output trap,
+
+ // Wishbone interfaces
+ input wb_rst_i,
+ input wb_clk_i,
+
+ output reg [31:0] wbm_adr_o,
+ output reg [31:0] wbm_dat_o,
+ input [31:0] wbm_dat_i,
+ output reg wbm_we_o,
+ output reg [3:0] wbm_sel_o,
+ output reg wbm_stb_o,
+ input wbm_ack_i,
+ output reg wbm_cyc_o,
+
+ // Pico Co-Processor Interface (PCPI)
+ output pcpi_valid,
+ output [31:0] pcpi_insn,
+ output [31:0] pcpi_rs1,
+ output [31:0] pcpi_rs2,
+ input pcpi_wr,
+ input [31:0] pcpi_rd,
+ input pcpi_wait,
+ input pcpi_ready,
+
+ // IRQ interface
+ input [31:0] irq,
+ output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+ output rvfi_valid,
+ output [63:0] rvfi_order,
+ output [31:0] rvfi_insn,
+ output rvfi_trap,
+ output rvfi_halt,
+ output rvfi_intr,
+ output [ 4:0] rvfi_rs1_addr,
+ output [ 4:0] rvfi_rs2_addr,
+ output [31:0] rvfi_rs1_rdata,
+ output [31:0] rvfi_rs2_rdata,
+ output [ 4:0] rvfi_rd_addr,
+ output [31:0] rvfi_rd_wdata,
+ output [31:0] rvfi_pc_rdata,
+ output [31:0] rvfi_pc_wdata,
+ output [31:0] rvfi_mem_addr,
+ output [ 3:0] rvfi_mem_rmask,
+ output [ 3:0] rvfi_mem_wmask,
+ output [31:0] rvfi_mem_rdata,
+ output [31:0] rvfi_mem_wdata,
+`endif
+
+ // Trace Interface
+ output trace_valid,
+ output [35:0] trace_data,
+
+ output mem_instr
+);
+ wire mem_valid;
+ wire [31:0] mem_addr;
+ wire [31:0] mem_wdata;
+ wire [ 3:0] mem_wstrb;
+ reg mem_ready;
+ reg [31:0] mem_rdata;
+
+ wire clk;
+ wire resetn;
+
+ assign clk = wb_clk_i;
+ assign resetn = ~wb_rst_i;
+
+ picorv32 #(
+ .ENABLE_COUNTERS (ENABLE_COUNTERS ),
+ .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
+ .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
+ .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+ .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
+ .BARREL_SHIFTER (BARREL_SHIFTER ),
+ .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
+ .TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
+ .COMPRESSED_ISA (COMPRESSED_ISA ),
+ .CATCH_MISALIGN (CATCH_MISALIGN ),
+ .CATCH_ILLINSN (CATCH_ILLINSN ),
+ .ENABLE_PCPI (ENABLE_PCPI ),
+ .ENABLE_MUL (ENABLE_MUL ),
+ .ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
+ .ENABLE_DIV (ENABLE_DIV ),
+ .ENABLE_IRQ (ENABLE_IRQ ),
+ .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
+ .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
+ .ENABLE_TRACE (ENABLE_TRACE ),
+ .REGS_INIT_ZERO (REGS_INIT_ZERO ),
+ .MASKED_IRQ (MASKED_IRQ ),
+ .LATCHED_IRQ (LATCHED_IRQ ),
+ .PROGADDR_RESET (PROGADDR_RESET ),
+ .PROGADDR_IRQ (PROGADDR_IRQ ),
+ .STACKADDR (STACKADDR )
+ ) picorv32_core (
+ .clk (clk ),
+ .resetn (resetn),
+ .trap (trap ),
+
+ .mem_valid(mem_valid),
+ .mem_addr (mem_addr ),
+ .mem_wdata(mem_wdata),
+ .mem_wstrb(mem_wstrb),
+ .mem_instr(mem_instr),
+ .mem_ready(mem_ready),
+ .mem_rdata(mem_rdata),
+
+ .pcpi_valid(pcpi_valid),
+ .pcpi_insn (pcpi_insn ),
+ .pcpi_rs1 (pcpi_rs1 ),
+ .pcpi_rs2 (pcpi_rs2 ),
+ .pcpi_wr (pcpi_wr ),
+ .pcpi_rd (pcpi_rd ),
+ .pcpi_wait (pcpi_wait ),
+ .pcpi_ready(pcpi_ready),
+
+ .irq(irq),
+ .eoi(eoi),
+
+`ifdef RISCV_FORMAL
+ .rvfi_valid (rvfi_valid ),
+ .rvfi_order (rvfi_order ),
+ .rvfi_insn (rvfi_insn ),
+ .rvfi_trap (rvfi_trap ),
+ .rvfi_halt (rvfi_halt ),
+ .rvfi_intr (rvfi_intr ),
+ .rvfi_rs1_addr (rvfi_rs1_addr ),
+ .rvfi_rs2_addr (rvfi_rs2_addr ),
+ .rvfi_rs1_rdata(rvfi_rs1_rdata),
+ .rvfi_rs2_rdata(rvfi_rs2_rdata),
+ .rvfi_rd_addr (rvfi_rd_addr ),
+ .rvfi_rd_wdata (rvfi_rd_wdata ),
+ .rvfi_pc_rdata (rvfi_pc_rdata ),
+ .rvfi_pc_wdata (rvfi_pc_wdata ),
+ .rvfi_mem_addr (rvfi_mem_addr ),
+ .rvfi_mem_rmask(rvfi_mem_rmask),
+ .rvfi_mem_wmask(rvfi_mem_wmask),
+ .rvfi_mem_rdata(rvfi_mem_rdata),
+ .rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+ .trace_valid(trace_valid),
+ .trace_data (trace_data)
+ );
+
+ localparam IDLE = 2'b00;
+ localparam WBSTART = 2'b01;
+ localparam WBEND = 2'b10;
+
+ reg [1:0] state;
+
+ wire we;
+ assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i) begin
+ wbm_adr_o <= 0;
+ wbm_dat_o <= 0;
+ wbm_we_o <= 0;
+ wbm_sel_o <= 0;
+ wbm_stb_o <= 0;
+ wbm_cyc_o <= 0;
+ state <= IDLE;
+ end else begin
+ case (state)
+ IDLE: begin
+ if (mem_valid) begin
+ wbm_adr_o <= mem_addr;
+ wbm_dat_o <= mem_wdata;
+ wbm_we_o <= we;
+ wbm_sel_o <= mem_wstrb;
+
+ wbm_stb_o <= 1'b1;
+ wbm_cyc_o <= 1'b1;
+ state <= WBSTART;
+ end else begin
+ mem_ready <= 1'b0;
+
+ wbm_stb_o <= 1'b0;
+ wbm_cyc_o <= 1'b0;
+ wbm_we_o <= 1'b0;
+ end
+ end
+ WBSTART:begin
+ if (wbm_ack_i) begin
+ mem_rdata <= wbm_dat_i;
+ mem_ready <= 1'b1;
+
+ state <= WBEND;
+
+ wbm_stb_o <= 1'b0;
+ wbm_cyc_o <= 1'b0;
+ wbm_we_o <= 1'b0;
+ end
+ end
+ WBEND: begin
+ mem_ready <= 1'b0;
+
+ state <= IDLE;
+ end
+ default:
+ state <= IDLE;
+ endcase
+ end
+ end
+endmodule
+
diff --git a/openlane/designs/s44/config.tcl b/openlane/designs/s44/config.tcl
new file mode 100755
index 0000000..6fefa50
--- /dev/null
+++ b/openlane/designs/s44/config.tcl
@@ -0,0 +1,19 @@
+# User config
+set ::env(DESIGN_NAME) lut_s44
+
+# Design config
+set ::env(CLOCK_PERIOD) 30
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+set ::env(CLOCK_PORT) "config_clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+# Synthesis config
+
+# Floorplan config
+set ::env(FP_CORE_UTIL) 5
+# Placement config
+set ::env(PL_TARGET_DENSITY) 0.5
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/s44/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/s44/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/s44/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/s44/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/s44/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/s44/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/s44/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/s44/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/s44/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/s44/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/s44/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..e7be618
--- /dev/null
+++ b/openlane/designs/s44/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1 @@
+#init Configs
\ No newline at end of file
diff --git a/openlane/designs/s44/src/lut.v b/openlane/designs/s44/src/lut.v
new file mode 100644
index 0000000..a931176
--- /dev/null
+++ b/openlane/designs/s44/src/lut.v
@@ -0,0 +1,43 @@
+// UC Berkeley CS250
+// Authors: Ryan Thornton (rpthornton@berkeley.edu)
+// Arya Reais-Parsi (aryap@berkeley.edu)
+
+
+///////// BASIC LUT /////////
+// Assumptions:
+// MEM_SIZE is a multiple of CONFIG_WIDTH
+
+module lut #(
+ parameter INPUTS=4, MEM_SIZE=1<<INPUTS, CONFIG_WIDTH=8
+) (
+ // IO
+ input [INPUTS-1:0] addr,
+ output out,
+
+ // Stream Style Configuration
+ input config_clk,
+ input config_en,
+ input [CONFIG_WIDTH-1:0] config_in,
+ output [CONFIG_WIDTH-1:0] config_out
+);
+reg [MEM_SIZE-1:0] mem = 0;
+assign out = mem[addr];
+
+// Stream Style Configuration Logic
+generate
+ genvar i;
+ for (i=1; i<(MEM_SIZE/CONFIG_WIDTH); i=i+1) begin
+ always @(posedge config_clk) begin
+ if (config_en)
+ mem[(i+1)*CONFIG_WIDTH-1:i*CONFIG_WIDTH] <= mem[(i)*CONFIG_WIDTH-1:(i-1)*CONFIG_WIDTH];
+ end
+ end
+ always @(posedge config_clk) begin
+ if (config_en) begin
+ mem[CONFIG_WIDTH-1:0] <= config_in;
+ end
+ end
+ assign config_out = mem[MEM_SIZE-1:MEM_SIZE-CONFIG_WIDTH];
+endgenerate
+endmodule
+
diff --git a/openlane/designs/s44/src/lut_s44.v b/openlane/designs/s44/src/lut_s44.v
new file mode 100644
index 0000000..a8eef5f
--- /dev/null
+++ b/openlane/designs/s44/src/lut_s44.v
@@ -0,0 +1,48 @@
+// UC Berkeley CS250
+// Authors: Ryan Thornton (rpthornton@berkeley.edu)
+// Arya Reais-Parsi (aryap@berkeley.edu)
+//
+// Based on the description in: Wenyi Feng, Jonathan Greene, and Alan
+// Mishchenko. 2018. Improving FPGA Performance with a S44 LUT Structure. In
+// Proceedings of the 2018 ACM/SIGDA International Symposium on
+// Field-Programmable Gate Arrays (FPGA '18). Association for Computing
+// Machinery, New York, NY, USA, 61–66.
+// DOI:https://doi.org/10.1145/3174243.3174272
+
+///////// HARD S44 LUT /////////
+
+module lut_s44 #(
+ parameter CONFIG_WIDTH=8
+) (
+ input [6:0] addr,
+ output out,
+
+ // Stream Style Configuration
+ input config_clk,
+ input config_en,
+ input [CONFIG_WIDTH-1:0] config_in,
+ output [CONFIG_WIDTH-1:0] config_out
+);
+
+wire intermediate;
+wire [CONFIG_WIDTH-1:0] config_in2;
+
+lut #(.INPUTS(4)) first_lut (
+ .addr(addr[6:3]),
+ .out(intermediate),
+ .config_clk(config_clk),
+ .config_en(config_en),
+ .config_in(config_in),
+ .config_out(config_in2)
+);
+
+lut #(.INPUTS(4)) second_lut (
+ .addr({intermediate, addr[2:0]}),
+ .out(out),
+ .config_clk(config_clk),
+ .config_en(config_en),
+ .config_in(config_in2),
+ .config_out(config_out)
+);
+endmodule
+
diff --git a/openlane/designs/salsa20/config.tcl b/openlane/designs/salsa20/config.tcl
new file mode 100755
index 0000000..d027ad6
--- /dev/null
+++ b/openlane/designs/salsa20/config.tcl
@@ -0,0 +1,13 @@
+set ::env(DESIGN_NAME) "salsa20"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/salsa20.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/salsa20/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/salsa20/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..4b2c40e
--- /dev/null
+++ b/openlane/designs/salsa20/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "38"
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.25
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/salsa20/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/salsa20/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..cb18e15
--- /dev/null
+++ b/openlane/designs/salsa20/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "36.73"
diff --git a/openlane/designs/salsa20/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/salsa20/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..cb18e15
--- /dev/null
+++ b/openlane/designs/salsa20/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "36.73"
diff --git a/openlane/designs/salsa20/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/salsa20/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..cb18e15
--- /dev/null
+++ b/openlane/designs/salsa20/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "36.73"
diff --git a/openlane/designs/salsa20/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/salsa20/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..cb18e15
--- /dev/null
+++ b/openlane/designs/salsa20/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 20
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CLOCK_PERIOD) "36.73"
diff --git a/openlane/designs/salsa20/src/salsa20.v b/openlane/designs/salsa20/src/salsa20.v
new file mode 100644
index 0000000..dced448
--- /dev/null
+++ b/openlane/designs/salsa20/src/salsa20.v
@@ -0,0 +1,2309 @@
+//======================================================================
+//
+// salsa20_qr.v
+// -----------
+// Verilog 2001 implementation of the stream cipher Salsa20.
+// This is the combinational QR logic as a separade module to allow
+// us to build versions of the cipher with 1, 2, 4 and even 8
+// parallel qr functions.
+//
+//
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module salsa20_qr(
+ input wire [31 : 0] y0,
+ input wire [31 : 0] y1,
+ input wire [31 : 0] y2,
+ input wire [31 : 0] y3,
+
+ output wire [31 : 0] z0,
+ output wire [31 : 0] z1,
+ output wire [31 : 0] z2,
+ output wire [31 : 0] z3
+ );
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31 : 0] tmp_z0;
+ reg [31 : 0] tmp_z1;
+ reg [31 : 0] tmp_z2;
+ reg [31 : 0] tmp_z3;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports.
+ //----------------------------------------------------------------
+ assign z0 = tmp_z0;
+ assign z1 = tmp_z1;
+ assign z2 = tmp_z2;
+ assign z3 = tmp_z3;
+
+
+ //----------------------------------------------------------------
+ // qr
+ //
+ // The actual quarterround function.
+ //----------------------------------------------------------------
+ always @*
+ begin : qr
+ reg [31 : 0] z0_0;
+ reg [31 : 0] z1_0;
+ reg [31 : 0] z2_0;
+ reg [31 : 0] z3_0;
+
+ z1_0 = (y0 + y3);
+ tmp_z1 = {z1_0[24 : 0], z1_0[31 : 25]} ^ y1;
+
+ z2_0 = (tmp_z1 + y0);
+ tmp_z2 = {z2_0[22 : 0], z2_0[31 : 23]} ^ y2;
+
+ z3_0 = (tmp_z2 + tmp_z1);
+ tmp_z3 = {z3_0[18 : 0], z3_0[31 : 19]} ^ y3;
+
+ z0_0 = (tmp_z3 + tmp_z2);
+ tmp_z0 = {z0_0[13 : 0], z0_0[31 : 14]} ^ y0;
+ end // qr
+endmodule // salsa20_qr
+
+//======================================================================
+// EOF salsa20_qr.v
+//======================================================================
+
+//======================================================================
+//
+// salsa20_core.v
+// --------------
+// Verilog 2001 implementation of the stream cipher Salsa20.
+// This is the internal core with wide interfaces.
+//
+//
+// Copyright (c) 2013 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module salsa20_core(
+ input wire clk,
+ input wire reset_n,
+
+ input wire init,
+ input wire next,
+
+ input wire [255 : 0] key,
+ input wire keylen,
+ input wire [63 : 0] iv,
+ input wire [4 : 0] rounds,
+
+ input wire [511 : 0] data_in,
+
+ output wire ready,
+
+ output wire [511 : 0] data_out,
+ output wire data_out_valid
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ // Datapath quartterround states names.
+ parameter QR0 = 1'b0;
+ parameter QR1 = 1'b1;
+
+ parameter NUM_ROUNDS = 4'h8;
+
+ parameter TAU0 = 32'h61707865;
+ parameter TAU1 = 32'h3120646e;
+ parameter TAU2 = 32'h79622d36;
+ parameter TAU3 = 32'h6b206574;
+
+ parameter SIGMA0 = 32'h61707865;
+ parameter SIGMA1 = 32'h3320646e;
+ parameter SIGMA2 = 32'h79622d32;
+ parameter SIGMA3 = 32'h6b206574;
+
+ parameter CTRL_IDLE = 3'h0;
+ parameter CTRL_INIT = 3'h1;
+ parameter CTRL_ROUNDS = 3'h2;
+ parameter CTRL_FINALIZE = 3'h3;
+ parameter CTRL_DONE = 3'h4;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [31 : 0] key0_reg;
+ reg [31 : 0] key0_new;
+ reg [31 : 0] key1_reg;
+ reg [31 : 0] key1_new;
+ reg [31 : 0] key2_reg;
+ reg [31 : 0] key2_new;
+ reg [31 : 0] key3_reg;
+ reg [31 : 0] key3_new;
+ reg [31 : 0] key4_reg;
+ reg [31 : 0] key4_new;
+ reg [31 : 0] key5_reg;
+ reg [31 : 0] key5_new;
+ reg [31 : 0] key6_reg;
+ reg [31 : 0] key6_new;
+ reg [31 : 0] key7_reg;
+ reg [31 : 0] key7_new;
+
+ reg keylen_reg;
+ reg keylen_new;
+
+ reg [31 : 0] iv0_reg;
+ reg [31 : 0] iv0_new;
+ reg [31 : 0] iv1_reg;
+ reg [31 : 0] iv1_new;
+
+ reg [31 : 0] state0_reg;
+ reg [31 : 0] state0_new;
+ reg [31 : 0] state1_reg;
+ reg [31 : 0] state1_new;
+ reg [31 : 0] state2_reg;
+ reg [31 : 0] state2_new;
+ reg [31 : 0] state3_reg;
+ reg [31 : 0] state3_new;
+ reg [31 : 0] state4_reg;
+ reg [31 : 0] state4_new;
+ reg [31 : 0] state5_reg;
+ reg [31 : 0] state5_new;
+ reg [31 : 0] state6_reg;
+ reg [31 : 0] state6_new;
+ reg [31 : 0] state7_reg;
+ reg [31 : 0] state7_new;
+ reg [31 : 0] state8_reg;
+ reg [31 : 0] state8_new;
+ reg [31 : 0] state9_reg;
+ reg [31 : 0] state9_new;
+ reg [31 : 0] state10_reg;
+ reg [31 : 0] state10_new;
+ reg [31 : 0] state11_reg;
+ reg [31 : 0] state11_new;
+ reg [31 : 0] state12_reg;
+ reg [31 : 0] state12_new;
+ reg [31 : 0] state13_reg;
+ reg [31 : 0] state13_new;
+ reg [31 : 0] state14_reg;
+ reg [31 : 0] state14_new;
+ reg [31 : 0] state15_reg;
+ reg [31 : 0] state15_new;
+ reg state_we;
+
+ reg [31 : 0] x0_reg;
+ reg [31 : 0] x0_new;
+ reg x0_we;
+
+ reg [31 : 0] x1_reg;
+ reg [31 : 0] x1_new;
+ reg x1_we;
+
+ reg [31 : 0] x2_reg;
+ reg [31 : 0] x2_new;
+ reg x2_we;
+
+ reg [31 : 0] x3_reg;
+ reg [31 : 0] x3_new;
+ reg x3_we;
+
+ reg [31 : 0] x4_reg;
+ reg [31 : 0] x4_new;
+ reg x4_we;
+
+ reg [31 : 0] x5_reg;
+ reg [31 : 0] x5_new;
+ reg x5_we;
+
+ reg [31 : 0] x6_reg;
+ reg [31 : 0] x6_new;
+ reg x6_we;
+
+ reg [31 : 0] x7_reg;
+ reg [31 : 0] x7_new;
+ reg x7_we;
+
+ reg [31 : 0] x8_reg;
+ reg [31 : 0] x8_new;
+ reg x8_we;
+
+ reg [31 : 0] x9_reg;
+ reg [31 : 0] x9_new;
+ reg x9_we;
+
+ reg [31 : 0] x10_reg;
+ reg [31 : 0] x10_new;
+ reg x10_we;
+
+ reg [31 : 0] x11_reg;
+ reg [31 : 0] x11_new;
+ reg x11_we;
+
+ reg [31 : 0] x12_reg;
+ reg [31 : 0] x12_new;
+ reg x12_we;
+
+ reg [31 : 0] x13_reg;
+ reg [31 : 0] x13_new;
+ reg x13_we;
+
+ reg [31 : 0] x14_reg;
+ reg [31 : 0] x14_new;
+ reg x14_we;
+
+ reg [31 : 0] x15_reg;
+ reg [31 : 0] x15_new;
+ reg x15_we;
+
+ reg [3 : 0] rounds_reg;
+ reg [3 : 0] rounds_new;
+
+ reg [511 : 0] data_in_reg;
+ reg data_in_we;
+
+ reg [511 : 0] data_out_reg;
+ reg [511 : 0] data_out_new;
+ reg data_out_we;
+
+ reg data_out_valid_reg;
+ reg data_out_valid_new;
+ reg data_out_valid_we;
+
+ reg qr_ctr_reg;
+ reg qr_ctr_new;
+ reg qr_ctr_we;
+ reg qr_ctr_inc;
+ reg qr_ctr_rst;
+
+ reg [3 : 0] dr_ctr_reg;
+ reg [3 : 0] dr_ctr_new;
+ reg dr_ctr_we;
+ reg dr_ctr_inc;
+ reg dr_ctr_rst;
+
+ reg [31 : 0] block0_ctr_reg;
+ reg [31 : 0] block0_ctr_new;
+ reg block0_ctr_we;
+ reg [31 : 0] block1_ctr_reg;
+ reg [31 : 0] block1_ctr_new;
+ reg block1_ctr_we;
+ reg block_ctr_inc;
+ reg block_ctr_rst;
+
+ reg [2 : 0] salsa20_ctrl_reg;
+ reg [2 : 0] salsa20_ctrl_new;
+ reg salsa20_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg sample_params;
+ reg init_state;
+ reg update_state;
+ reg update_output;
+
+ reg [31 : 0] qr0_a;
+ reg [31 : 0] qr0_b;
+ reg [31 : 0] qr0_c;
+ reg [31 : 0] qr0_d;
+ wire [31 : 0] qr0_a_prim;
+ wire [31 : 0] qr0_b_prim;
+ wire [31 : 0] qr0_c_prim;
+ wire [31 : 0] qr0_d_prim;
+
+ reg [31 : 0] qr1_a;
+ reg [31 : 0] qr1_b;
+ reg [31 : 0] qr1_c;
+ reg [31 : 0] qr1_d;
+ wire [31 : 0] qr1_a_prim;
+ wire [31 : 0] qr1_b_prim;
+ wire [31 : 0] qr1_c_prim;
+ wire [31 : 0] qr1_d_prim;
+
+ reg [31 : 0] qr2_a;
+ reg [31 : 0] qr2_b;
+ reg [31 : 0] qr2_c;
+ reg [31 : 0] qr2_d;
+ wire [31 : 0] qr2_a_prim;
+ wire [31 : 0] qr2_b_prim;
+ wire [31 : 0] qr2_c_prim;
+ wire [31 : 0] qr2_d_prim;
+
+ reg [31 : 0] qr3_a;
+ reg [31 : 0] qr3_b;
+ reg [31 : 0] qr3_c;
+ reg [31 : 0] qr3_d;
+ wire [31 : 0] qr3_a_prim;
+ wire [31 : 0] qr3_b_prim;
+ wire [31 : 0] qr3_c_prim;
+ wire [31 : 0] qr3_d_prim;
+
+ reg ready_wire;
+
+
+ //----------------------------------------------------------------
+ // Instantiation of the qr modules.
+ //----------------------------------------------------------------
+ salsa20_qr qr0(
+ .y0(qr0_a),
+ .y1(qr0_b),
+ .y2(qr0_c),
+ .y3(qr0_d),
+
+ .z0(qr0_a_prim),
+ .z1(qr0_b_prim),
+ .z2(qr0_c_prim),
+ .z3(qr0_d_prim)
+ );
+
+ salsa20_qr qr1(
+ .y0(qr1_a),
+ .y1(qr1_b),
+ .y2(qr1_c),
+ .y3(qr1_d),
+
+ .z0(qr1_a_prim),
+ .z1(qr1_b_prim),
+ .z2(qr1_c_prim),
+ .z3(qr1_d_prim)
+ );
+
+ salsa20_qr qr2(
+ .y0(qr2_a),
+ .y1(qr2_b),
+ .y2(qr2_c),
+ .y3(qr2_d),
+
+ .z0(qr2_a_prim),
+ .z1(qr2_b_prim),
+ .z2(qr2_c_prim),
+ .z3(qr2_d_prim)
+ );
+
+ salsa20_qr qr3(
+ .y0(qr3_a),
+ .y1(qr3_b),
+ .y2(qr3_c),
+ .y3(qr3_d),
+
+ .z0(qr3_a_prim),
+ .z1(qr3_b_prim),
+ .z2(qr3_c_prim),
+ .z3(qr3_d_prim)
+ );
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign data_out = data_out_reg;
+
+ assign data_out_valid = data_out_valid_reg;
+
+ assign ready = ready_wire;
+
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with synchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk)
+ begin : reg_update
+ if (!reset_n)
+ begin
+ key0_reg <= 32'h00000000;
+ key1_reg <= 32'h00000000;
+ key2_reg <= 32'h00000000;
+ key3_reg <= 32'h00000000;
+ key4_reg <= 32'h00000000;
+ key5_reg <= 32'h00000000;
+ key6_reg <= 32'h00000000;
+ key7_reg <= 32'h00000000;
+ iv0_reg <= 32'h00000000;
+ iv1_reg <= 32'h00000000;
+ state0_reg <= 32'h00000000;
+ state1_reg <= 32'h00000000;
+ state2_reg <= 32'h00000000;
+ state3_reg <= 32'h00000000;
+ state4_reg <= 32'h00000000;
+ state5_reg <= 32'h00000000;
+ state6_reg <= 32'h00000000;
+ state7_reg <= 32'h00000000;
+ state8_reg <= 32'h00000000;
+ state9_reg <= 32'h00000000;
+ state10_reg <= 32'h00000000;
+ state11_reg <= 32'h00000000;
+ state12_reg <= 32'h00000000;
+ state13_reg <= 32'h00000000;
+ state14_reg <= 32'h00000000;
+ state15_reg <= 32'h00000000;
+ x0_reg <= 32'h00000000;
+ x1_reg <= 32'h00000000;
+ x2_reg <= 32'h00000000;
+ x3_reg <= 32'h00000000;
+ x4_reg <= 32'h00000000;
+ x5_reg <= 32'h00000000;
+ x6_reg <= 32'h00000000;
+ x7_reg <= 32'h00000000;
+ x8_reg <= 32'h00000000;
+ x9_reg <= 32'h00000000;
+ x10_reg <= 32'h00000000;
+ x11_reg <= 32'h00000000;
+ x12_reg <= 32'h00000000;
+ x13_reg <= 32'h00000000;
+ x14_reg <= 32'h00000000;
+ x15_reg <= 32'h00000000;
+ data_in_reg <= 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ data_out_reg <= 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ rounds_reg <= 4'h0;
+ data_out_valid_reg <= 0;
+ qr_ctr_reg <= QR0;
+ dr_ctr_reg <= 0;
+ block0_ctr_reg <= 32'h00000000;
+ block1_ctr_reg <= 32'h00000000;
+ salsa20_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ if (sample_params)
+ begin
+ key0_reg <= key0_new;
+ key1_reg <= key1_new;
+ key2_reg <= key2_new;
+ key3_reg <= key3_new;
+ key4_reg <= key4_new;
+ key5_reg <= key5_new;
+ key6_reg <= key6_new;
+ key7_reg <= key7_new;
+ iv0_reg <= iv0_new;
+ iv1_reg <= iv1_new;
+ rounds_reg <= rounds_new;
+ keylen_reg <= keylen_new;
+ end
+
+ if (data_in_we)
+ begin
+ data_in_reg <= data_in;
+ end
+
+ if (state_we)
+ begin
+ state0_reg <= state0_new;
+ state1_reg <= state1_new;
+ state2_reg <= state2_new;
+ state3_reg <= state3_new;
+ state4_reg <= state4_new;
+ state5_reg <= state5_new;
+ state6_reg <= state6_new;
+ state7_reg <= state7_new;
+ state8_reg <= state8_new;
+ state9_reg <= state9_new;
+ state10_reg <= state10_new;
+ state11_reg <= state11_new;
+ state12_reg <= state12_new;
+ state13_reg <= state13_new;
+ state14_reg <= state14_new;
+ state15_reg <= state15_new;
+ end
+
+ if (x0_we)
+ begin
+ x0_reg <= x0_new;
+ end
+
+ if (x1_we)
+ begin
+ x1_reg <= x1_new;
+ end
+
+ if (x2_we)
+ begin
+ x2_reg <= x2_new;
+ end
+
+ if (x3_we)
+ begin
+ x3_reg <= x3_new;
+ end
+
+ if (x4_we)
+ begin
+ x4_reg <= x4_new;
+ end
+
+ if (x5_we)
+ begin
+ x5_reg <= x5_new;
+ end
+
+ if (x6_we)
+ begin
+ x6_reg <= x6_new;
+ end
+
+ if (x7_we)
+ begin
+ x7_reg <= x7_new;
+ end
+
+ if (x8_we)
+ begin
+ x8_reg <= x8_new;
+ end
+
+ if (x9_we)
+ begin
+ x9_reg <= x9_new;
+ end
+
+ if (x10_we)
+ begin
+ x10_reg <= x10_new;
+ end
+
+ if (x11_we)
+ begin
+ x11_reg <= x11_new;
+ end
+
+ if (x12_we)
+ begin
+ x12_reg <= x12_new;
+ end
+
+ if (x13_we)
+ begin
+ x13_reg <= x13_new;
+ end
+
+ if (x14_we)
+ begin
+ x14_reg <= x14_new;
+ end
+
+ if (x15_we)
+ begin
+ x15_reg <= x15_new;
+ end
+
+ if (data_out_we)
+ begin
+ data_out_reg <= data_out_new;
+ end
+
+ if (data_out_valid_we)
+ begin
+ data_out_valid_reg <= data_out_valid_new;
+ end
+
+ if (qr_ctr_we)
+ begin
+ qr_ctr_reg <= qr_ctr_new;
+ end
+
+ if (dr_ctr_we)
+ begin
+ dr_ctr_reg <= dr_ctr_new;
+ end
+
+ if (block0_ctr_we)
+ begin
+ block0_ctr_reg <= block0_ctr_new;
+ end
+
+ if (block1_ctr_we)
+ begin
+ block1_ctr_reg <= block1_ctr_new;
+ end
+
+ if (salsa20_ctrl_we)
+ begin
+ salsa20_ctrl_reg <= salsa20_ctrl_new;
+ end
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // data_out_logic
+ // Final output logic that combines the result from procceing
+ // with the input word. This adds a final layer of XOR gates.
+ //
+ // Note that we also remap all the words into LSB format.
+ //----------------------------------------------------------------
+ always @*
+ begin : data_out_logic
+ reg [31 : 0] msb_block_state0;
+ reg [31 : 0] msb_block_state1;
+ reg [31 : 0] msb_block_state2;
+ reg [31 : 0] msb_block_state3;
+ reg [31 : 0] msb_block_state4;
+ reg [31 : 0] msb_block_state5;
+ reg [31 : 0] msb_block_state6;
+ reg [31 : 0] msb_block_state7;
+ reg [31 : 0] msb_block_state8;
+ reg [31 : 0] msb_block_state9;
+ reg [31 : 0] msb_block_state10;
+ reg [31 : 0] msb_block_state11;
+ reg [31 : 0] msb_block_state12;
+ reg [31 : 0] msb_block_state13;
+ reg [31 : 0] msb_block_state14;
+ reg [31 : 0] msb_block_state15;
+
+ reg [31 : 0] lsb_block_state0;
+ reg [31 : 0] lsb_block_state1;
+ reg [31 : 0] lsb_block_state2;
+ reg [31 : 0] lsb_block_state3;
+ reg [31 : 0] lsb_block_state4;
+ reg [31 : 0] lsb_block_state5;
+ reg [31 : 0] lsb_block_state6;
+ reg [31 : 0] lsb_block_state7;
+ reg [31 : 0] lsb_block_state8;
+ reg [31 : 0] lsb_block_state9;
+ reg [31 : 0] lsb_block_state10;
+ reg [31 : 0] lsb_block_state11;
+ reg [31 : 0] lsb_block_state12;
+ reg [31 : 0] lsb_block_state13;
+ reg [31 : 0] lsb_block_state14;
+ reg [31 : 0] lsb_block_state15;
+
+ reg [511 : 0] lsb_block_state;
+
+ lsb_block_state = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+
+ data_out_new = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ data_out_we = 0;
+
+ if (update_output)
+ begin
+ msb_block_state0 = state0_reg + x0_reg;
+ msb_block_state1 = state1_reg + x1_reg;
+ msb_block_state2 = state2_reg + x2_reg;
+ msb_block_state3 = state3_reg + x3_reg;
+ msb_block_state4 = state4_reg + x4_reg;
+ msb_block_state5 = state5_reg + x5_reg;
+ msb_block_state6 = state6_reg + x6_reg;
+ msb_block_state7 = state7_reg + x7_reg;
+ msb_block_state8 = state8_reg + x8_reg;
+ msb_block_state9 = state9_reg + x9_reg;
+ msb_block_state10 = state10_reg + x10_reg;
+ msb_block_state11 = state11_reg + x11_reg;
+ msb_block_state12 = state12_reg + x12_reg;
+ msb_block_state13 = state13_reg + x13_reg;
+ msb_block_state14 = state14_reg + x14_reg;
+ msb_block_state15 = state15_reg + x15_reg;
+
+ lsb_block_state0 = {msb_block_state0[7 : 0],
+ msb_block_state0[15 : 8],
+ msb_block_state0[23 : 16],
+ msb_block_state0[31 : 24]};
+
+ lsb_block_state1 = {msb_block_state1[7 : 0],
+ msb_block_state1[15 : 8],
+ msb_block_state1[23 : 16],
+ msb_block_state1[31 : 24]};
+
+ lsb_block_state2 = {msb_block_state2[7 : 0],
+ msb_block_state2[15 : 8],
+ msb_block_state2[23 : 16],
+ msb_block_state2[31 : 24]};
+
+ lsb_block_state3 = {msb_block_state3[7 : 0],
+ msb_block_state3[15 : 8],
+ msb_block_state3[23 : 16],
+ msb_block_state3[31 : 24]};
+
+ lsb_block_state4 = {msb_block_state4[7 : 0],
+ msb_block_state4[15 : 8],
+ msb_block_state4[23 : 16],
+ msb_block_state4[31 : 24]};
+
+ lsb_block_state5 = {msb_block_state5[7 : 0],
+ msb_block_state5[15 : 8],
+ msb_block_state5[23 : 16],
+ msb_block_state5[31 : 24]};
+
+ lsb_block_state6 = {msb_block_state6[7 : 0],
+ msb_block_state6[15 : 8],
+ msb_block_state6[23 : 16],
+ msb_block_state6[31 : 24]};
+
+ lsb_block_state7 = {msb_block_state7[7 : 0],
+ msb_block_state7[15 : 8],
+ msb_block_state7[23 : 16],
+ msb_block_state7[31 : 24]};
+
+ lsb_block_state8 = {msb_block_state8[7 : 0],
+ msb_block_state8[15 : 8],
+ msb_block_state8[23 : 16],
+ msb_block_state8[31 : 24]};
+
+ lsb_block_state9 = {msb_block_state9[7 : 0],
+ msb_block_state9[15 : 8],
+ msb_block_state9[23 : 16],
+ msb_block_state9[31 : 24]};
+
+ lsb_block_state10 = {msb_block_state10[7 : 0],
+ msb_block_state10[15 : 8],
+ msb_block_state10[23 : 16],
+ msb_block_state10[31 : 24]};
+
+ lsb_block_state11 = {msb_block_state11[7 : 0],
+ msb_block_state11[15 : 8],
+ msb_block_state11[23 : 16],
+ msb_block_state11[31 : 24]};
+
+ lsb_block_state12 = {msb_block_state12[7 : 0],
+ msb_block_state12[15 : 8],
+ msb_block_state12[23 : 16],
+ msb_block_state12[31 : 24]};
+
+ lsb_block_state13 = {msb_block_state13[7 : 0],
+ msb_block_state13[15 : 8],
+ msb_block_state13[23 : 16],
+ msb_block_state13[31 : 24]};
+
+ lsb_block_state14 = {msb_block_state14[7 : 0],
+ msb_block_state14[15 : 8],
+ msb_block_state14[23 : 16],
+ msb_block_state14[31 : 24]};
+
+ lsb_block_state15 = {msb_block_state15[7 : 0],
+ msb_block_state15[15 : 8],
+ msb_block_state15[23 : 16],
+ msb_block_state15[31 : 24]};
+
+ lsb_block_state = {lsb_block_state0, lsb_block_state1,
+ lsb_block_state2, lsb_block_state3,
+ lsb_block_state4, lsb_block_state5,
+ lsb_block_state6, lsb_block_state7,
+ lsb_block_state8, lsb_block_state9,
+ lsb_block_state10, lsb_block_state11,
+ lsb_block_state12, lsb_block_state13,
+ lsb_block_state14, lsb_block_state15};
+
+ data_out_new = data_in_reg ^ lsb_block_state;
+ data_out_we = 1;
+ end // if (update_output)
+ end // data_out_logic
+
+
+ //----------------------------------------------------------------
+ // sample_parameters
+ // Logic (wires) that convert parameter input to appropriate
+ // format for processing.
+ //----------------------------------------------------------------
+ always @*
+ begin : sample_parameters
+ key0_new = 32'h00000000;
+ key1_new = 32'h00000000;
+ key2_new = 32'h00000000;
+ key3_new = 32'h00000000;
+ key4_new = 32'h00000000;
+ key5_new = 32'h00000000;
+ key6_new = 32'h00000000;
+ key7_new = 32'h00000000;
+ iv0_new = 32'h00000000;
+ iv1_new = 32'h00000000;
+ rounds_new = 4'h0;
+ keylen_new = 1'b0;
+
+ if (sample_params)
+ begin
+ key0_new = {key[231 : 224], key[239 : 232],
+ key[247 : 240], key[255 : 248]};
+ key1_new = {key[199 : 192], key[207 : 200],
+ key[215 : 208], key[223 : 216]};
+ key2_new = {key[167 : 160], key[175 : 168],
+ key[183 : 176], key[191 : 184]};
+ key3_new = {key[135 : 128], key[143 : 136],
+ key[151 : 144], key[159 : 152]};
+ key4_new = {key[103 : 96], key[111 : 104],
+ key[119 : 112], key[127 : 120]};
+ key5_new = {key[71 : 64], key[79 : 72],
+ key[87 : 80], key[95 : 88]};
+ key6_new = {key[39 : 32], key[47 : 40],
+ key[55 : 48], key[63 : 56]};
+ key7_new = {key[7 : 0], key[15 : 8],
+ key[23 : 16], key[31 : 24]};
+
+ iv0_new = {iv[39 : 32], iv[47 : 40],
+ iv[55 : 48], iv[63 : 56]};
+ iv1_new = {iv[7 : 0], iv[15 : 8],
+ iv[23 : 16], iv[31 : 24]};
+
+ // Div by two since we count double rounds.
+ rounds_new = rounds[4 : 1];
+
+ keylen_new = keylen;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // state_logic
+ // Logic to init and update the internal state.
+ //----------------------------------------------------------------
+ always @*
+ begin : state_logic
+ reg [31 : 0] new_state_word0;
+ reg [31 : 0] new_state_word1;
+ reg [31 : 0] new_state_word2;
+ reg [31 : 0] new_state_word3;
+ reg [31 : 0] new_state_word4;
+ reg [31 : 0] new_state_word5;
+ reg [31 : 0] new_state_word6;
+ reg [31 : 0] new_state_word7;
+ reg [31 : 0] new_state_word8;
+ reg [31 : 0] new_state_word9;
+ reg [31 : 0] new_state_word10;
+ reg [31 : 0] new_state_word11;
+ reg [31 : 0] new_state_word12;
+ reg [31 : 0] new_state_word13;
+ reg [31 : 0] new_state_word14;
+ reg [31 : 0] new_state_word15;
+
+ new_state_word0 = 32'h00000000;
+ new_state_word1 = 32'h00000000;
+ new_state_word2 = 32'h00000000;
+ new_state_word3 = 32'h00000000;
+ new_state_word4 = 32'h00000000;
+ new_state_word5 = 32'h00000000;
+ new_state_word6 = 32'h00000000;
+ new_state_word7 = 32'h00000000;
+ new_state_word8 = 32'h00000000;
+ new_state_word9 = 32'h00000000;
+ new_state_word10 = 32'h00000000;
+ new_state_word11 = 32'h00000000;
+ new_state_word12 = 32'h00000000;
+ new_state_word13 = 32'h00000000;
+ new_state_word14 = 32'h00000000;
+ new_state_word15 = 32'h00000000;
+
+ x0_new = 32'h00000000;
+ x1_new = 32'h00000000;
+ x2_new = 32'h00000000;
+ x3_new = 32'h00000000;
+ x4_new = 32'h00000000;
+ x5_new = 32'h00000000;
+ x6_new = 32'h00000000;
+ x7_new = 32'h00000000;
+ x8_new = 32'h00000000;
+ x9_new = 32'h00000000;
+ x10_new = 32'h00000000;
+ x11_new = 32'h00000000;
+ x12_new = 32'h00000000;
+ x13_new = 32'h00000000;
+ x14_new = 32'h00000000;
+ x15_new = 32'h00000000;
+ x0_we = 0;
+ x1_we = 0;
+ x2_we = 0;
+ x3_we = 0;
+ x4_we = 0;
+ x5_we = 0;
+ x6_we = 0;
+ x7_we = 0;
+ x8_we = 0;
+ x9_we = 0;
+ x10_we = 0;
+ x11_we = 0;
+ x12_we = 0;
+ x13_we = 0;
+ x14_we = 0;
+ x15_we = 0;
+
+ state0_new = 32'h00000000;
+ state1_new = 32'h00000000;
+ state2_new = 32'h00000000;
+ state3_new = 32'h00000000;
+ state4_new = 32'h00000000;
+ state5_new = 32'h00000000;
+ state6_new = 32'h00000000;
+ state7_new = 32'h00000000;
+ state8_new = 32'h00000000;
+ state9_new = 32'h00000000;
+ state10_new = 32'h00000000;
+ state11_new = 32'h00000000;
+ state12_new = 32'h00000000;
+ state13_new = 32'h00000000;
+ state14_new = 32'h00000000;
+ state15_new = 32'h00000000;
+ state_we = 0;
+
+ if (init_state)
+ begin
+ new_state_word4 = key0_reg;
+ new_state_word5 = key1_reg;
+ new_state_word6 = key2_reg;
+ new_state_word7 = key3_reg;
+
+ new_state_word12 = block0_ctr_reg;
+ new_state_word13 = block1_ctr_reg;
+
+ new_state_word14 = iv0_reg;
+ new_state_word15 = iv1_reg;
+
+ if (keylen_reg)
+ begin
+ // 256 bit key.
+ new_state_word0 = SIGMA0;
+ new_state_word1 = SIGMA1;
+ new_state_word2 = SIGMA2;
+ new_state_word3 = SIGMA3;
+ new_state_word8 = key4_reg;
+ new_state_word9 = key5_reg;
+ new_state_word10 = key6_reg;
+ new_state_word11 = key7_reg;
+ end
+ else
+ begin
+ // 128 bit key.
+ new_state_word0 = TAU0;
+ new_state_word1 = TAU1;
+ new_state_word2 = TAU2;
+ new_state_word3 = TAU3;
+ new_state_word8 = key0_reg;
+ new_state_word9 = key1_reg;
+ new_state_word10 = key2_reg;
+ new_state_word11 = key3_reg;
+ end
+
+ x0_new = new_state_word0;
+ x1_new = new_state_word1;
+ x2_new = new_state_word2;
+ x3_new = new_state_word3;
+ x4_new = new_state_word4;
+ x5_new = new_state_word5;
+ x6_new = new_state_word6;
+ x7_new = new_state_word7;
+ x8_new = new_state_word8;
+ x9_new = new_state_word9;
+ x10_new = new_state_word10;
+ x11_new = new_state_word11;
+ x12_new = new_state_word12;
+ x13_new = new_state_word13;
+ x14_new = new_state_word14;
+ x15_new = new_state_word15;
+ x0_we = 1;
+ x1_we = 1;
+ x2_we = 1;
+ x3_we = 1;
+ x4_we = 1;
+ x5_we = 1;
+ x6_we = 1;
+ x7_we = 1;
+ x8_we = 1;
+ x9_we = 1;
+ x10_we = 1;
+ x11_we = 1;
+ x12_we = 1;
+ x13_we = 1;
+ x14_we = 1;
+ x15_we = 1;
+
+ state0_new = new_state_word0;
+ state1_new = new_state_word1;
+ state2_new = new_state_word2;
+ state3_new = new_state_word3;
+ state4_new = new_state_word4;
+ state5_new = new_state_word5;
+ state6_new = new_state_word6;
+ state7_new = new_state_word7;
+ state8_new = new_state_word8;
+ state9_new = new_state_word9;
+ state10_new = new_state_word10;
+ state11_new = new_state_word11;
+ state12_new = new_state_word12;
+ state13_new = new_state_word13;
+ state14_new = new_state_word14;
+ state15_new = new_state_word15;
+ state_we = 1;
+ end // if (init_state)
+
+ else if (update_state)
+ begin
+ case (qr_ctr_reg)
+ QR0:
+ begin
+ x0_new = qr0_a_prim;
+ x4_new = qr0_b_prim;
+ x8_new = qr0_c_prim;
+ x12_new = qr0_d_prim;
+ x0_we = 1;
+ x4_we = 1;
+ x8_we = 1;
+ x12_we = 1;
+
+ x1_new = qr1_a_prim;
+ x5_new = qr1_b_prim;
+ x9_new = qr1_c_prim;
+ x13_new = qr1_d_prim;
+ x1_we = 1;
+ x5_we = 1;
+ x9_we = 1;
+ x13_we = 1;
+
+ x2_new = qr2_a_prim;
+ x6_new = qr2_b_prim;
+ x10_new = qr2_c_prim;
+ x14_new = qr2_d_prim;
+ x2_we = 1;
+ x6_we = 1;
+ x10_we = 1;
+ x14_we = 1;
+
+ x3_new = qr3_a_prim;
+ x7_new = qr3_b_prim;
+ x11_new = qr3_c_prim;
+ x15_new = qr3_d_prim;
+ x3_we = 1;
+ x7_we = 1;
+ x11_we = 1;
+ x15_we = 1;
+ end
+
+ QR1:
+ begin
+ x0_new = qr0_a_prim;
+ x5_new = qr0_b_prim;
+ x10_new = qr0_c_prim;
+ x15_new = qr0_d_prim;
+ x0_we = 1;
+ x5_we = 1;
+ x10_we = 1;
+ x15_we = 1;
+
+ x1_new = qr1_a_prim;
+ x6_new = qr1_b_prim;
+ x11_new = qr1_c_prim;
+ x12_new = qr1_d_prim;
+ x1_we = 1;
+ x6_we = 1;
+ x11_we = 1;
+ x12_we = 1;
+
+ x2_new = qr2_a_prim;
+ x7_new = qr2_b_prim;
+ x8_new = qr2_c_prim;
+ x13_new = qr2_d_prim;
+ x2_we = 1;
+ x7_we = 1;
+ x8_we = 1;
+ x13_we = 1;
+
+ x3_new = qr3_a_prim;
+ x4_new = qr3_b_prim;
+ x9_new = qr3_c_prim;
+ x14_new = qr3_d_prim;
+ x3_we = 1;
+ x4_we = 1;
+ x9_we = 1;
+ x14_we = 1;
+ end
+ endcase // case (quarterround_select)
+ end // if (update_state)
+ end // state_logic
+
+
+ //----------------------------------------------------------------
+ // quarterround_mux
+ // Quarterround muxes that selects operands for quarterrounds.
+ //----------------------------------------------------------------
+ always @*
+ begin : quarterround_mux
+ case (qr_ctr_reg)
+ QR0:
+ begin
+ qr0_a = x0_reg;
+ qr0_b = x4_reg;
+ qr0_c = x8_reg;
+ qr0_d = x12_reg;
+
+ qr1_a = x1_reg;
+ qr1_b = x5_reg;
+ qr1_c = x9_reg;
+ qr1_d = x13_reg;
+
+ qr2_a = x2_reg;
+ qr2_b = x6_reg;
+ qr2_c = x10_reg;
+ qr2_d = x14_reg;
+
+ qr3_a = x3_reg;
+ qr3_b = x7_reg;
+ qr3_c = x11_reg;
+ qr3_d = x15_reg;
+ end
+
+ QR1:
+ begin
+ qr0_a = x0_reg;
+ qr0_b = x5_reg;
+ qr0_c = x10_reg;
+ qr0_d = x15_reg;
+
+ qr1_a = x1_reg;
+ qr1_b = x6_reg;
+ qr1_c = x11_reg;
+ qr1_d = x12_reg;
+
+ qr2_a = x2_reg;
+ qr2_b = x7_reg;
+ qr2_c = x8_reg;
+ qr2_d = x13_reg;
+
+ qr3_a = x3_reg;
+ qr3_b = x4_reg;
+ qr3_c = x9_reg;
+ qr3_d = x14_reg;
+ end
+ endcase // case (quarterround_select)
+ end // quarterround_mux
+
+
+ //----------------------------------------------------------------
+ // qr_ctr
+ // Update logic for the quarterround counter, a monotonically
+ // increasing counter with reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : qr_ctr
+ qr_ctr_new = 0;
+ qr_ctr_we = 0;
+
+ if (qr_ctr_rst)
+ begin
+ qr_ctr_new = 0;
+ qr_ctr_we = 1;
+ end
+
+ if (qr_ctr_inc)
+ begin
+ qr_ctr_new = qr_ctr_reg + 1'b1;
+ qr_ctr_we = 1;
+ end
+ end // qr_ctr
+
+
+ //----------------------------------------------------------------
+ // dr_ctr
+ // Update logic for the round counter, a monotonically
+ // increasing counter with reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : dr_ctr
+ dr_ctr_new = 0;
+ dr_ctr_we = 0;
+
+ if (dr_ctr_rst)
+ begin
+ dr_ctr_new = 0;
+ dr_ctr_we = 1;
+ end
+
+ if (dr_ctr_inc)
+ begin
+ dr_ctr_new = dr_ctr_reg + 1'b1;
+ dr_ctr_we = 1;
+ end
+ end // dr_ctr
+
+
+ //----------------------------------------------------------------
+ // block_ctr
+ // Update logic for the 64-bit block counter, a monotonically
+ // increasing counter with reset.
+ //----------------------------------------------------------------
+ always @*
+ begin : block_ctr
+ // Defult assignments
+ block0_ctr_new = 32'h00000000;
+ block1_ctr_new = 32'h00000000;
+ block0_ctr_we = 0;
+ block1_ctr_we = 0;
+
+ if (block_ctr_rst)
+ begin
+ block0_ctr_we = 1;
+ block1_ctr_we = 1;
+ end
+
+ if (block_ctr_inc)
+ begin
+ block0_ctr_new = block0_ctr_reg + 1;
+ block0_ctr_we = 1;
+
+ // Avoid chaining the 32-bit adders.
+ if (block0_ctr_reg == 32'hffffffff)
+ begin
+ block1_ctr_new = block1_ctr_reg + 1;
+ block1_ctr_we = 1;
+ end
+ end
+ end // block_ctr
+
+
+ //----------------------------------------------------------------
+ // salsa20_ctrl_fsm
+ // Logic for the state machine controlling the core behaviour.
+ //----------------------------------------------------------------
+ always @*
+ begin : salsa20_ctrl_fsm
+ init_state = 0;
+ update_state = 0;
+ sample_params = 0;
+ update_output = 0;
+
+ qr_ctr_inc = 0;
+ qr_ctr_rst = 0;
+
+ dr_ctr_inc = 0;
+ dr_ctr_rst = 0;
+
+ block_ctr_inc = 0;
+ block_ctr_rst = 0;
+
+ data_in_we = 0;
+
+ ready_wire = 0;
+
+ data_out_valid_new = 0;
+ data_out_valid_we = 0;
+
+ salsa20_ctrl_new = CTRL_IDLE;
+ salsa20_ctrl_we = 0;
+
+
+ case (salsa20_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ ready_wire = 1;
+ if (init)
+ begin
+ data_in_we = 1;
+ sample_params = 1;
+ block_ctr_rst = 1;
+ salsa20_ctrl_new = CTRL_INIT;
+ salsa20_ctrl_we = 1;
+ end
+ end
+
+
+ CTRL_INIT:
+ begin
+ init_state = 1;
+ qr_ctr_rst = 1;
+ dr_ctr_rst = 1;
+ salsa20_ctrl_new = CTRL_ROUNDS;
+ salsa20_ctrl_we = 1;
+ end
+
+
+ CTRL_ROUNDS:
+ begin
+ update_state = 1;
+ qr_ctr_inc = 1;
+ if (qr_ctr_reg == QR1)
+ begin
+ dr_ctr_inc = 1;
+ if (dr_ctr_reg == (rounds_reg - 1))
+ begin
+ salsa20_ctrl_new = CTRL_FINALIZE;
+ salsa20_ctrl_we = 1;
+ end
+ end
+ end
+
+
+ CTRL_FINALIZE:
+ begin
+ update_output = 1;
+ data_out_valid_new = 1;
+ data_out_valid_we = 1;
+ salsa20_ctrl_new = CTRL_DONE;
+ salsa20_ctrl_we = 1;
+ end
+
+
+ CTRL_DONE:
+ begin
+ ready_wire = 1;
+ if (init)
+ begin
+ data_out_valid_new = 0;
+ data_out_valid_we = 1;
+ data_in_we = 1;
+ sample_params = 1;
+ block_ctr_rst = 1;
+ salsa20_ctrl_new = CTRL_INIT;
+ salsa20_ctrl_we = 1;
+ end
+ else if (next)
+ begin
+ data_out_valid_new = 0;
+ data_out_valid_we = 1;
+ data_in_we = 1;
+ block_ctr_inc = 1;
+ salsa20_ctrl_new = CTRL_INIT;
+ salsa20_ctrl_we = 1;
+ end
+ end
+ endcase // case (salsa20_ctrl_reg)
+ end // salsa20_ctrl_fsm
+endmodule // salsa20_core
+
+//======================================================================
+// EOF salsa20_core.v
+//======================================================================
+
+//======================================================================
+//
+// salsa20.v
+// --------
+// Top level wrapper for the Salsa20 stream, cipher core providing
+// a simple memory like interface with 32 bit data access.
+//
+//
+// Copyright (c) 2013 Secworks Sweden AB
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module salsa20(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data,
+ output wire error
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter ADDR_CTRL = 8'h00;
+ parameter CTRL_INIT_BIT = 0;
+ parameter CTRL_NEXT_BIT = 1;
+
+ parameter ADDR_STATUS = 8'h01;
+ parameter STATUS_READY_BIT = 0;
+
+ parameter ADDR_KEYLEN = 8'h08;
+ parameter KEYLEN_BIT = 0;
+ parameter ADDR_ROUNDS = 8'h09;
+ parameter ROUNDS_HIGH_BIT = 4;
+ parameter ROUNDS_LOW_BIT = 0;
+
+ parameter ADDR_KEY0 = 8'h10;
+ parameter ADDR_KEY1 = 8'h11;
+ parameter ADDR_KEY2 = 8'h12;
+ parameter ADDR_KEY3 = 8'h13;
+ parameter ADDR_KEY4 = 8'h14;
+ parameter ADDR_KEY5 = 8'h15;
+ parameter ADDR_KEY6 = 8'h16;
+ parameter ADDR_KEY7 = 8'h17;
+
+ parameter ADDR_IV0 = 8'h20;
+ parameter ADDR_IV1 = 8'h21;
+
+ parameter ADDR_DATA_IN0 = 8'h40;
+ parameter ADDR_DATA_IN1 = 8'h41;
+ parameter ADDR_DATA_IN2 = 8'h42;
+ parameter ADDR_DATA_IN3 = 8'h43;
+ parameter ADDR_DATA_IN4 = 8'h44;
+ parameter ADDR_DATA_IN5 = 8'h45;
+ parameter ADDR_DATA_IN6 = 8'h46;
+ parameter ADDR_DATA_IN7 = 8'h47;
+ parameter ADDR_DATA_IN8 = 8'h48;
+ parameter ADDR_DATA_IN9 = 8'h49;
+ parameter ADDR_DATA_IN10 = 8'h4a;
+ parameter ADDR_DATA_IN11 = 8'h4b;
+ parameter ADDR_DATA_IN12 = 8'h4c;
+ parameter ADDR_DATA_IN13 = 8'h4d;
+ parameter ADDR_DATA_IN14 = 8'h4e;
+ parameter ADDR_DATA_IN15 = 8'h4f;
+
+ parameter ADDR_DATA_OUT0 = 8'h80;
+ parameter ADDR_DATA_OUT1 = 8'h81;
+ parameter ADDR_DATA_OUT2 = 8'h82;
+ parameter ADDR_DATA_OUT3 = 8'h83;
+ parameter ADDR_DATA_OUT4 = 8'h84;
+ parameter ADDR_DATA_OUT5 = 8'h85;
+ parameter ADDR_DATA_OUT6 = 8'h86;
+ parameter ADDR_DATA_OUT7 = 8'h87;
+ parameter ADDR_DATA_OUT8 = 8'h88;
+ parameter ADDR_DATA_OUT9 = 8'h89;
+ parameter ADDR_DATA_OUT10 = 8'h8a;
+ parameter ADDR_DATA_OUT11 = 8'h8b;
+ parameter ADDR_DATA_OUT12 = 8'h8c;
+ parameter ADDR_DATA_OUT13 = 8'h8d;
+ parameter ADDR_DATA_OUT14 = 8'h8e;
+ parameter ADDR_DATA_OUT15 = 8'h8f;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg init_reg;
+ reg next_reg;
+ reg ctrl_we;
+
+ reg ready_reg;
+
+ reg keylen_reg;
+ reg keylen_we;
+
+ reg [4 : 0] rounds_reg;
+ reg rounds_we;
+
+ reg data_out_valid_reg;
+
+ reg [31 : 0] key0_reg;
+ reg key0_we;
+ reg [31 : 0] key1_reg;
+ reg key1_we;
+ reg [31 : 0] key2_reg;
+ reg key2_we;
+ reg [31 : 0] key3_reg;
+ reg key3_we;
+ reg [31 : 0] key4_reg;
+ reg key4_we;
+ reg [31 : 0] key5_reg;
+ reg key5_we;
+ reg [31 : 0] key6_reg;
+ reg key6_we;
+ reg [31 : 0] key7_reg;
+ reg key7_we;
+
+ reg [31 : 0] iv0_reg;
+ reg iv0_we;
+ reg [31 : 0] iv1_reg;
+ reg iv1_we;
+
+ reg [31 : 0] data_in0_reg;
+ reg data_in0_we;
+ reg [31 : 0] data_in1_reg;
+ reg data_in1_we;
+ reg [31 : 0] data_in2_reg;
+ reg data_in2_we;
+ reg [31 : 0] data_in3_reg;
+ reg data_in3_we;
+ reg [31 : 0] data_in4_reg;
+ reg data_in4_we;
+ reg [31 : 0] data_in5_reg;
+ reg data_in5_we;
+ reg [31 : 0] data_in6_reg;
+ reg data_in6_we;
+ reg [31 : 0] data_in7_reg;
+ reg data_in7_we;
+ reg [31 : 0] data_in8_reg;
+ reg data_in8_we;
+ reg [31 : 0] data_in9_reg;
+ reg data_in9_we;
+ reg [31 : 0] data_in10_reg;
+ reg data_in10_we;
+ reg [31 : 0] data_in11_reg;
+ reg data_in11_we;
+ reg [31 : 0] data_in12_reg;
+ reg data_in12_we;
+ reg [31 : 0] data_in13_reg;
+ reg data_in13_we;
+ reg [31 : 0] data_in14_reg;
+ reg data_in14_we;
+ reg [31 : 0] data_in15_reg;
+ reg data_in15_we;
+
+ reg [31 : 0] data_out0_reg;
+ reg [31 : 0] data_out0_new;
+ reg [31 : 0] data_out1_reg;
+ reg [31 : 0] data_out1_new;
+ reg [31 : 0] data_out2_reg;
+ reg [31 : 0] data_out2_new;
+ reg [31 : 0] data_out3_reg;
+ reg [31 : 0] data_out3_new;
+ reg [31 : 0] data_out4_reg;
+ reg [31 : 0] data_out4_new;
+ reg [31 : 0] data_out5_reg;
+ reg [31 : 0] data_out5_new;
+ reg [31 : 0] data_out6_reg;
+ reg [31 : 0] data_out6_new;
+ reg [31 : 0] data_out7_reg;
+ reg [31 : 0] data_out7_new;
+ reg [31 : 0] data_out8_reg;
+ reg [31 : 0] data_out8_new;
+ reg [31 : 0] data_out9_reg;
+ reg [31 : 0] data_out9_new;
+ reg [31 : 0] data_out10_reg;
+ reg [31 : 0] data_out10_new;
+ reg [31 : 0] data_out11_reg;
+ reg [31 : 0] data_out11_new;
+ reg [31 : 0] data_out12_reg;
+ reg [31 : 0] data_out12_new;
+ reg [31 : 0] data_out13_reg;
+ reg [31 : 0] data_out13_new;
+ reg [31 : 0] data_out14_reg;
+ reg [31 : 0] data_out14_new;
+ reg [31 : 0] data_out15_reg;
+ reg [31 : 0] data_out15_new;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ wire core_init;
+ wire core_next;
+ wire [255 : 0] core_key;
+ wire core_keylen;
+ wire [4 : 0] core_rounds;
+ wire [63 : 0] core_iv;
+ wire core_ready;
+ wire [511 : 0] core_data_in;
+ wire [511 : 0] core_data_out;
+ wire core_data_out_valid;
+
+ reg [31 : 0] tmp_read_data;
+ reg tmp_error;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign core_init = init_reg;
+
+ assign core_next = next_reg;
+
+ assign core_keylen = keylen_reg;
+
+ assign core_rounds = rounds_reg;
+
+ assign core_key = {key0_reg, key1_reg, key2_reg, key3_reg,
+ key4_reg, key5_reg, key6_reg, key7_reg};
+
+ assign core_iv = {iv0_reg, iv1_reg};
+
+ assign core_data_in = {data_in0_reg, data_in1_reg, data_in2_reg, data_in3_reg,
+ data_in4_reg, data_in5_reg, data_in6_reg, data_in7_reg,
+ data_in8_reg, data_in9_reg, data_in10_reg, data_in11_reg,
+ data_in12_reg, data_in13_reg, data_in14_reg, data_in15_reg};
+
+ assign read_data = tmp_read_data;
+ assign error = tmp_error;
+
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ salsa20_core core (
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .init(core_init),
+ .next(core_next),
+
+ .key(core_key),
+ .keylen(core_keylen),
+ .iv(core_iv),
+ .rounds(core_rounds),
+
+ .data_in(core_data_in),
+
+ .ready(core_ready),
+
+ .data_out(core_data_out),
+ .data_out_valid(core_data_out_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with synchronous
+ // active low reset. All registers have write enable.
+ //----------------------------------------------------------------
+ always @ (posedge clk)
+ begin
+ if (!reset_n)
+ begin
+ init_reg <= 0;
+ next_reg <= 0;
+ ready_reg <= 0;
+ keylen_reg <= 0;
+ rounds_reg <= 5'b00000;
+ data_out_valid_reg <= 0;
+
+ key0_reg <= 32'h00000000;
+ key1_reg <= 32'h00000000;
+ key2_reg <= 32'h00000000;
+ key3_reg <= 32'h00000000;
+ key4_reg <= 32'h00000000;
+ key5_reg <= 32'h00000000;
+ key6_reg <= 32'h00000000;
+ key7_reg <= 32'h00000000;
+
+ iv0_reg <= 32'h00000000;
+ iv1_reg <= 32'h00000000;
+
+ data_in0_reg <= 32'h00000000;
+ data_in1_reg <= 32'h00000000;
+ data_in2_reg <= 32'h00000000;
+ data_in3_reg <= 32'h00000000;
+ data_in4_reg <= 32'h00000000;
+ data_in5_reg <= 32'h00000000;
+ data_in6_reg <= 32'h00000000;
+ data_in7_reg <= 32'h00000000;
+ data_in8_reg <= 32'h00000000;
+ data_in9_reg <= 32'h00000000;
+ data_in10_reg <= 32'h00000000;
+ data_in11_reg <= 32'h00000000;
+ data_in12_reg <= 32'h00000000;
+ data_in13_reg <= 32'h00000000;
+ data_in14_reg <= 32'h00000000;
+ data_in15_reg <= 32'h00000000;
+
+ data_out0_reg <= 32'h00000000;
+ data_out1_reg <= 32'h00000000;
+ data_out2_reg <= 32'h00000000;
+ data_out3_reg <= 32'h00000000;
+ data_out4_reg <= 32'h00000000;
+ data_out5_reg <= 32'h00000000;
+ data_out6_reg <= 32'h00000000;
+ data_out7_reg <= 32'h00000000;
+ data_out8_reg <= 32'h00000000;
+ data_out9_reg <= 32'h00000000;
+ data_out10_reg <= 32'h00000000;
+ data_out11_reg <= 32'h00000000;
+ data_out12_reg <= 32'h00000000;
+ data_out13_reg <= 32'h00000000;
+ data_out14_reg <= 32'h00000000;
+ data_out15_reg <= 32'h00000000;
+ end
+ else
+ begin
+ ready_reg <= core_ready;
+ data_out_valid_reg <= core_data_out_valid;
+
+ if (ctrl_we)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
+ end
+
+ if (keylen_we)
+ begin
+ keylen_reg <= write_data[KEYLEN_BIT];
+ end
+
+ if (rounds_we)
+ begin
+ rounds_reg <= write_data[ROUNDS_HIGH_BIT : ROUNDS_LOW_BIT];
+ end
+
+ if (key0_we)
+ begin
+ key0_reg <= write_data;
+ end
+
+ if (key1_we)
+ begin
+ key1_reg <= write_data;
+ end
+
+ if (key2_we)
+ begin
+ key2_reg <= write_data;
+ end
+
+ if (key3_we)
+ begin
+ key3_reg <= write_data;
+ end
+
+ if (key4_we)
+ begin
+ key4_reg <= write_data;
+ end
+
+ if (key5_we)
+ begin
+ key5_reg <= write_data;
+ end
+
+ if (key6_we)
+ begin
+ key6_reg <= write_data;
+ end
+
+ if (key7_we)
+ begin
+ key7_reg <= write_data;
+ end
+
+ if (iv0_we)
+ begin
+ iv0_reg <= write_data;
+ end
+
+ if (iv1_we)
+ begin
+ iv1_reg <= write_data;
+ end
+
+ if (data_in0_we)
+ begin
+ data_in0_reg <= write_data;
+ end
+
+ if (data_in1_we)
+ begin
+ data_in1_reg <= write_data;
+ end
+
+ if (data_in2_we)
+ begin
+ data_in2_reg <= write_data;
+ end
+
+ if (data_in3_we)
+ begin
+ data_in3_reg <= write_data;
+ end
+
+ if (data_in4_we)
+ begin
+ data_in4_reg <= write_data;
+ end
+
+ if (data_in5_we)
+ begin
+ data_in5_reg <= write_data;
+ end
+
+ if (data_in6_we)
+ begin
+ data_in6_reg <= write_data;
+ end
+
+ if (data_in7_we)
+ begin
+ data_in7_reg <= write_data;
+ end
+
+ if (data_in8_we)
+ begin
+ data_in8_reg <= write_data;
+ end
+
+ if (data_in9_we)
+ begin
+ data_in9_reg <= write_data;
+ end
+
+ if (data_in10_we)
+ begin
+ data_in10_reg <= write_data;
+ end
+
+ if (data_in11_we)
+ begin
+ data_in11_reg <= write_data;
+ end
+
+ if (data_in12_we)
+ begin
+ data_in12_reg <= write_data;
+ end
+
+ if (data_in13_we)
+ begin
+ data_in13_reg <= write_data;
+ end
+
+ if (data_in14_we)
+ begin
+ data_in14_reg <= write_data;
+ end
+
+ if (data_in15_we)
+ begin
+ data_in15_reg <= write_data;
+ end
+
+ if (core_data_out_valid)
+ begin
+ data_out0_reg <= core_data_out[511 : 480];
+ data_out1_reg <= core_data_out[479 : 448];
+ data_out2_reg <= core_data_out[447 : 416];
+ data_out3_reg <= core_data_out[415 : 384];
+ data_out4_reg <= core_data_out[383 : 352];
+ data_out5_reg <= core_data_out[351 : 320];
+ data_out6_reg <= core_data_out[319 : 288];
+ data_out7_reg <= core_data_out[287 : 256];
+ data_out8_reg <= core_data_out[255 : 224];
+ data_out9_reg <= core_data_out[223 : 192];
+ data_out10_reg <= core_data_out[191 : 160];
+ data_out11_reg <= core_data_out[159 : 128];
+ data_out12_reg <= core_data_out[127 : 96];
+ data_out13_reg <= core_data_out[95 : 64];
+ data_out14_reg <= core_data_out[63 : 32];
+ data_out15_reg <= core_data_out[31 : 0];
+ end
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // Address decoder logic.
+ //----------------------------------------------------------------
+ always @*
+ begin : addr_decoder
+ ctrl_we = 0;
+ keylen_we = 0;
+ rounds_we = 0;
+
+ key0_we = 0;
+ key1_we = 0;
+ key2_we = 0;
+ key3_we = 0;
+ key4_we = 0;
+ key5_we = 0;
+ key6_we = 0;
+ key7_we = 0;
+
+ iv0_we = 0;
+ iv1_we = 0;
+
+ data_in0_we = 0;
+ data_in1_we = 0;
+ data_in2_we = 0;
+ data_in3_we = 0;
+ data_in4_we = 0;
+ data_in5_we = 0;
+ data_in6_we = 0;
+ data_in7_we = 0;
+ data_in8_we = 0;
+ data_in9_we = 0;
+ data_in10_we = 0;
+ data_in11_we = 0;
+ data_in12_we = 0;
+ data_in13_we = 0;
+ data_in14_we = 0;
+ data_in15_we = 0;
+
+ tmp_read_data = 32'h00000000;
+ tmp_error = 0;
+
+ if (cs)
+ begin
+ if (we)
+ begin
+ case (address)
+ ADDR_CTRL:
+ begin
+ ctrl_we = 1;
+ end
+
+ ADDR_KEYLEN:
+ begin
+ keylen_we = 1;
+ end
+
+ ADDR_ROUNDS:
+ begin
+ rounds_we = 1;
+ end
+
+ ADDR_KEY0:
+ begin
+ key0_we = 1;
+ end
+
+ ADDR_KEY1:
+ begin
+ key1_we = 1;
+ end
+
+ ADDR_KEY2:
+ begin
+ key2_we = 1;
+ end
+
+ ADDR_KEY3:
+ begin
+ key3_we = 1;
+ end
+
+ ADDR_KEY4:
+ begin
+ key4_we = 1;
+ end
+
+ ADDR_KEY5:
+ begin
+ key5_we = 1;
+ end
+
+ ADDR_KEY6:
+ begin
+ key6_we = 1;
+ end
+
+ ADDR_KEY7:
+ begin
+ key7_we = 1;
+ end
+
+ ADDR_IV0:
+ begin
+ iv0_we = 1;
+ end
+
+ ADDR_IV1:
+ begin
+ iv1_we = 1;
+ end
+
+ ADDR_DATA_IN0:
+ begin
+ data_in0_we = 1;
+ end
+
+ ADDR_DATA_IN1:
+ begin
+ data_in1_we = 1;
+ end
+
+ ADDR_DATA_IN2:
+ begin
+ data_in2_we = 1;
+ end
+
+ ADDR_DATA_IN3:
+ begin
+ data_in3_we = 1;
+ end
+
+ ADDR_DATA_IN4:
+ begin
+ data_in4_we = 1;
+ end
+
+ ADDR_DATA_IN5:
+ begin
+ data_in5_we = 1;
+ end
+
+ ADDR_DATA_IN6:
+ begin
+ data_in6_we = 1;
+ end
+
+ ADDR_DATA_IN7:
+ begin
+ data_in7_we = 1;
+ end
+
+ ADDR_DATA_IN8:
+ begin
+ data_in8_we = 1;
+ end
+
+ ADDR_DATA_IN9:
+ begin
+ data_in9_we = 1;
+ end
+
+ ADDR_DATA_IN10:
+ begin
+ data_in10_we = 1;
+ end
+
+ ADDR_DATA_IN11:
+ begin
+ data_in11_we = 1;
+ end
+
+ ADDR_DATA_IN12:
+ begin
+ data_in12_we = 1;
+ end
+
+ ADDR_DATA_IN13:
+ begin
+ data_in13_we = 1;
+ end
+
+ ADDR_DATA_IN14:
+ begin
+ data_in14_we = 1;
+ end
+
+ ADDR_DATA_IN15:
+ begin
+ data_in15_we = 1;
+ end
+
+ default:
+ begin
+ tmp_error = 1;
+ end
+ endcase // case (address)
+ end // if (we)
+
+ else
+ begin
+ case (address)
+ ADDR_CTRL:
+ begin
+ tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg};
+ end
+
+ ADDR_STATUS:
+ begin
+ tmp_read_data = {28'h0000000, 2'b00,
+ {data_out_valid_reg, ready_reg}};
+ end
+
+ ADDR_KEYLEN:
+ begin
+ tmp_read_data = {28'h0000000, 3'b000, keylen_reg};
+ end
+
+ ADDR_ROUNDS:
+ begin
+ tmp_read_data = {24'h000000, 3'b000, rounds_reg};
+ end
+
+ ADDR_KEY0:
+ begin
+ tmp_read_data = key0_reg;
+ end
+
+ ADDR_KEY1:
+ begin
+ tmp_read_data = key1_reg;
+ end
+
+ ADDR_KEY2:
+ begin
+ tmp_read_data = key2_reg;
+ end
+
+ ADDR_KEY3:
+ begin
+ tmp_read_data = key3_reg;
+ end
+
+ ADDR_KEY4:
+ begin
+ tmp_read_data = key4_reg;
+ end
+
+ ADDR_KEY5:
+ begin
+ tmp_read_data = key5_reg;
+ end
+
+ ADDR_KEY6:
+ begin
+ tmp_read_data = key6_reg;
+ end
+
+ ADDR_KEY7:
+ begin
+ tmp_read_data = key7_reg;
+ end
+
+ ADDR_IV0:
+ begin
+ tmp_read_data = iv0_reg;
+ end
+
+ ADDR_IV1:
+ begin
+ tmp_read_data = iv1_reg;
+ end
+
+ ADDR_DATA_OUT0:
+ begin
+ tmp_read_data = data_out0_reg;
+ end
+
+ ADDR_DATA_OUT1:
+ begin
+ tmp_read_data = data_out1_reg;
+ end
+
+ ADDR_DATA_OUT2:
+ begin
+ tmp_read_data = data_out2_reg;
+ end
+
+ ADDR_DATA_OUT3:
+ begin
+ tmp_read_data = data_out3_reg;
+ end
+
+ ADDR_DATA_OUT4:
+ begin
+ tmp_read_data = data_out4_reg;
+ end
+
+ ADDR_DATA_OUT5:
+ begin
+ tmp_read_data = data_out5_reg;
+ end
+
+ ADDR_DATA_OUT6:
+ begin
+ tmp_read_data = data_out6_reg;
+ end
+
+ ADDR_DATA_OUT7:
+ begin
+ tmp_read_data = data_out7_reg;
+ end
+
+ ADDR_DATA_OUT8:
+ begin
+ tmp_read_data = data_out8_reg;
+ end
+
+ ADDR_DATA_OUT9:
+ begin
+ tmp_read_data = data_out9_reg;
+ end
+
+ ADDR_DATA_OUT10:
+ begin
+ tmp_read_data = data_out10_reg;
+ end
+
+ ADDR_DATA_OUT11:
+ begin
+ tmp_read_data = data_out11_reg;
+ end
+
+ ADDR_DATA_OUT12:
+ begin
+ tmp_read_data = data_out12_reg;
+ end
+
+ ADDR_DATA_OUT13:
+ begin
+ tmp_read_data = data_out13_reg;
+ end
+
+ ADDR_DATA_OUT14:
+ begin
+ tmp_read_data = data_out14_reg;
+ end
+
+ ADDR_DATA_OUT15:
+ begin
+ tmp_read_data = data_out15_reg;
+ end
+
+ default:
+ begin
+ tmp_error = 1;
+ end
+ endcase // case (address)
+ end
+ end
+ end // addr_decoder
+endmodule // salsa20
+
+//======================================================================
+// EOF salsa20.v
+//======================================================================
+
diff --git a/openlane/designs/spm/config.json b/openlane/designs/spm/config.json
new file mode 100644
index 0000000..2bc26a0
--- /dev/null
+++ b/openlane/designs/spm/config.json
@@ -0,0 +1,10 @@
+{
+ "DESIGN_NAME" : "spm",
+ "VERILOG_FILES" : "./designs/spm/src/spm.v",
+ "CLOCK_PERIOD" : 10.000,
+ "CLOCK_PORT" : "clk",
+ "CLOCK_NET" : "clk",
+ "SYNTH_MAX_FANOUT" : 6,
+ "FP_CORE_UTIL" : 65,
+ "PL_TARGET_DENSITY" : 0.70
+}
diff --git a/openlane/designs/spm/config.tcl b/openlane/designs/spm/config.tcl
new file mode 100755
index 0000000..91d9672
--- /dev/null
+++ b/openlane/designs/spm/config.tcl
@@ -0,0 +1,18 @@
+# Design
+set ::env(DESIGN_NAME) "spm"
+
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+set ::env(CLOCK_PERIOD) "10.000"
+set ::env(CLOCK_PORT) "clk"
+
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(FP_PDN_VOFFSET) 7.0
+set ::env(FP_PDN_HOFFSET) 7.0
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
diff --git a/openlane/designs/spm/pin_order.cfg b/openlane/designs/spm/pin_order.cfg
new file mode 100644
index 0000000..192092a
--- /dev/null
+++ b/openlane/designs/spm/pin_order.cfg
@@ -0,0 +1,12 @@
+#N
+x.*
+
+#S
+rst
+
+#E
+clk
+
+#W
+p
+y
diff --git a/openlane/designs/spm/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/spm/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..93e655a
--- /dev/null
+++ b/openlane/designs/spm/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(FP_CORE_UTIL) 45
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/spm/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/spm/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..30e7c8e
--- /dev/null
+++ b/openlane/designs/spm/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(FP_CORE_UTIL) 49
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/spm/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/spm/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..30e7c8e
--- /dev/null
+++ b/openlane/designs/spm/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(FP_CORE_UTIL) 49
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/spm/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/spm/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..30e7c8e
--- /dev/null
+++ b/openlane/designs/spm/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(FP_CORE_UTIL) 49
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/spm/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/spm/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..30e7c8e
--- /dev/null
+++ b/openlane/designs/spm/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(FP_CORE_UTIL) 49
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/spm/src/spm.sdc b/openlane/designs/spm/src/spm.sdc
new file mode 100644
index 0000000..4d778ce
--- /dev/null
+++ b/openlane/designs/spm/src/spm.sdc
@@ -0,0 +1,2 @@
+set_units -time ns
+create_clock [get_ports clk] -name core_clock -period 10
diff --git a/openlane/designs/spm/src/spm.v b/openlane/designs/spm/src/spm.v
new file mode 100644
index 0000000..c7191b1
--- /dev/null
+++ b/openlane/designs/spm/src/spm.v
@@ -0,0 +1,141 @@
+// Copyright 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module spm(clk, rst, x, y, p);
+ parameter size = 32;
+ input clk, rst;
+ input y;
+ input[size-1:0] x;
+ output p;
+
+ wire[size-1:1] pp;
+ wire[size-1:0] xy;
+
+ genvar i;
+
+ CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
+ generate for(i=1; i<size-1; i=i+1) begin
+ CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
+ end endgenerate
+ TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));
+
+endmodule
+
+module TCMP(clk, rst, a, s);
+ input clk, rst;
+ input a;
+ output reg s;
+
+ reg z;
+
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ //Reset logic goes here.
+ s <= 1'b0;
+ z <= 1'b0;
+ end
+ else begin
+ //Sequential logic goes here.
+ z <= a | z;
+ s <= a ^ z;
+ end
+ end
+endmodule
+
+module CSADD(clk, rst, x, y, sum);
+ input clk, rst;
+ input x, y;
+ output reg sum;
+
+ reg sc;
+
+ // Half Adders logic
+ wire hsum1, hco1;
+ assign hsum1 = y ^ sc;
+ assign hco1 = y & sc;
+
+ wire hsum2, hco2;
+ assign hsum2 = x ^ hsum1;
+ assign hco2 = x & hsum1;
+
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ //Reset logic goes here.
+ sum <= 1'b0;
+ sc <= 1'b0;
+ end
+ else begin
+ //Sequential logic goes here.
+ sum <= hsum2;
+ sc <= hco1 ^ hco2;
+ end
+ end
+endmodule
+
+
+/*
+
+module spm_tb;
+
+ //Inputs
+ reg clk;
+ reg rst;
+ reg [7: 0] x;
+
+ reg[7:0] Y;
+ reg[15:0] P;
+
+ //Outputs
+ wire p;
+
+ reg[3:0] cnt;
+
+ //Instantiation of Unit Under Test
+ spm #(8) uut (
+ .clk(clk),
+ .rst(rst),
+ .y(Y[0]),
+ .x(x),
+ .p(p)
+ );
+
+ always #5 clk = ~clk;
+
+ always @ (posedge clk)
+ if(rst) Y = -50;
+ else Y <= {1'b0,Y[7:1]};
+
+ always @ (posedge clk)
+ if(rst) P = 0;
+ else P <= {p, P[15:1]};
+
+ always @ (posedge clk)
+ if(rst) cnt = 0;
+ else cnt <= cnt + 1;
+
+ initial begin
+ //Inputs initialization
+ clk = 0;
+ rst = 0;
+ x = 50;
+
+ //Reset
+ #20 rst = 1;
+ #20 rst = 0;
+ #1000;
+ $finish;
+ end
+
+endmodule
+*/
diff --git a/openlane/designs/usb/config.tcl b/openlane/designs/usb/config.tcl
new file mode 100755
index 0000000..5993678
--- /dev/null
+++ b/openlane/designs/usb/config.tcl
@@ -0,0 +1,13 @@
+
+# Design
+set ::env(DESIGN_NAME) "usb"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/usb2p0_core.v"
+
+set ::env(CLOCK_PORT) "clk_48"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/usb/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/usb/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..91e2d6e
--- /dev/null
+++ b/openlane/designs/usb/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 40
+set ::env(CLOCK_PERIOD) "15.00"
+set ::env(SYNTH_STRATEGY) "DELAY 0"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/usb/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..befc1f2
--- /dev/null
+++ b/openlane/designs/usb/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(CLOCK_PERIOD) "12.55"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/usb/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..befc1f2
--- /dev/null
+++ b/openlane/designs/usb/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(CLOCK_PERIOD) "12.55"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/usb/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..befc1f2
--- /dev/null
+++ b/openlane/designs/usb/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(CLOCK_PERIOD) "12.55"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/usb/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..befc1f2
--- /dev/null
+++ b/openlane/designs/usb/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(CLOCK_PERIOD) "12.55"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb/src/usb2p0_core.v b/openlane/designs/usb/src/usb2p0_core.v
new file mode 100644
index 0000000..738d358
--- /dev/null
+++ b/openlane/designs/usb/src/usb2p0_core.v
@@ -0,0 +1,1311 @@
+/*
+
+Taken from: https://github.com/avakar/usbcorev
+
+No-notice MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+module usb(
+ input rst_n,
+ input clk_48,
+
+ input rx_j,
+ input rx_se0,
+
+ output tx_en,
+ output tx_j,
+ output tx_se0,
+
+ input[6:0] usb_address,
+
+ output usb_rst,
+
+ output reg transaction_active,
+ output reg[3:0] endpoint,
+ output reg direction_in,
+ output reg setup,
+ input data_toggle,
+
+ input[1:0] handshake,
+
+ output reg[7:0] data_out,
+ input[7:0] data_in,
+ input data_in_valid,
+ output reg data_strobe,
+ output reg success
+ );
+
+localparam
+ hs_ack = 2'b00,
+ hs_none = 2'b01,
+ hs_nak = 2'b10,
+ hs_stall = 2'b11;
+
+wire[3:0] recv_pid;
+wire[7:0] recv_data;
+wire recv_packet;
+wire recv_datastrobe;
+wire recv_crc5_ok;
+wire recv_crc16_ok;
+wire recv_short_idle;
+
+usb_recv recv(
+ .rst_n(rst_n),
+ .clk_48(clk_48),
+
+ .rx_j(rx_j),
+ .rx_se0(rx_se0),
+
+ .short_idle(recv_short_idle),
+ .usb_rst(usb_rst),
+
+ .xpid(recv_pid),
+ .xdata(recv_data),
+ .xpacket(recv_packet),
+ .xdatastrobe(recv_datastrobe),
+ .xcrc5_ok(recv_crc5_ok),
+ .xcrc16_ok(recv_crc16_ok)
+ );
+
+reg tx_transmit;
+reg[7:0] tx_data;
+wire tx_data_strobe;
+
+reg tx_enable_crc16;
+wire tx_send_crc16;
+usb_tx tx(
+ .rst_n(rst_n),
+ .clk_48(clk_48),
+
+ .tx_en(tx_en),
+ .tx_j(tx_j),
+ .tx_se0(tx_se0),
+
+ .transmit(tx_transmit),
+ .data(tx_data),
+ .data_strobe(tx_data_strobe),
+
+ .update_crc16(tx_enable_crc16),
+ .send_crc16(tx_send_crc16)
+ );
+
+reg[7:0] recv_queue_0;
+reg[7:0] recv_queue_1;
+reg recv_queue_0_valid;
+reg recv_queue_1_valid;
+
+always @(posedge clk_48) begin
+ if (!recv_packet) begin
+ recv_queue_1_valid <= 1'b0;
+ recv_queue_0_valid <= 1'b0;
+ end else if (recv_datastrobe) begin
+ data_out <= recv_queue_1;
+ recv_queue_1 <= recv_queue_0;
+ recv_queue_0 <= recv_data;
+ recv_queue_1_valid <= recv_queue_0_valid;
+ recv_queue_0_valid <= 1'b1;
+ end
+end
+
+localparam
+ st_idle = 3'b000,
+ st_data = 3'b001,
+ st_err = 3'b010,
+ st_send_handshake = 3'b011,
+ st_in = 3'b100,
+ st_prep_recv_ack = 3'b101,
+ st_recv_ack = 3'b110,
+ st_send_ack = 3'b111;
+
+reg[2:0] state;
+
+assign tx_send_crc16 = state == st_prep_recv_ack;
+
+localparam
+ pt_special = 2'b00,
+ pt_token = 2'b01,
+ pt_handshake = 2'b10,
+ pt_data = 2'b11;
+
+localparam
+ tok_out = 2'b00,
+ tok_sof = 2'b01,
+ tok_in = 2'b10,
+ tok_setup = 2'b11;
+
+// Note that the token is perishable. The standard prescribes at most
+// 7.5 bits of inter-packet idle time. We allow at most 31 bits between
+// token activation and receiving the corresponding DATA packet.
+reg[6:0] token_timeout;
+wire token_active = token_timeout != 1'b0;
+
+reg[1:0] handshake_latch;
+
+always @(posedge clk_48 or negedge rst_n) begin
+ if (!rst_n) begin
+ success <= 1'b0;
+ state <= st_idle;
+ data_strobe <= 1'b0;
+ endpoint <= 1'sbx;
+ direction_in <= 1'bx;
+ setup <= 1'bx;
+ transaction_active <= 1'b0;
+ token_timeout <= 1'b0;
+ tx_transmit <= 1'b0;
+
+ tx_enable_crc16 <= 1'b0;
+ handshake_latch <= 2'bxx;
+ end else begin
+ if (token_timeout != 1'b0)
+ token_timeout <= token_timeout - 1'b1;
+
+ if (!transaction_active) begin
+ endpoint <= 1'sbx;
+ direction_in <= 1'bx;
+ setup <= 1'bx;
+ handshake_latch <= 2'bxx;
+ end
+
+ success <= 1'b0;
+ data_strobe <= 1'b0;
+ tx_transmit <= 1'b0;
+ case (state)
+ st_idle: begin
+ if (!token_active)
+ transaction_active <= 1'b0;
+
+ if (recv_packet) begin
+ if (recv_pid[1:0] == pt_token) begin
+ state <= st_data;
+ end else begin
+ if (recv_pid[1:0] == pt_data && !recv_pid[2] && token_active) begin
+ handshake_latch <= handshake;
+ state <= recv_pid[3] == data_toggle? st_data: st_send_ack;
+ end else begin
+ state <= st_err;
+ end
+ end
+ end
+ end
+ st_data: begin
+ if (!recv_packet) begin
+ state <= st_idle;
+ case (recv_pid[1:0])
+ pt_token: begin
+ if (recv_queue_1_valid && recv_crc5_ok && recv_queue_1[6:0] == usb_address && recv_pid[3:2] != tok_sof) begin
+ token_timeout <= 7'h7f;
+ transaction_active <= 1'b1;
+ endpoint <= { recv_queue_0[2:0], recv_queue_1[7] };
+ case (recv_pid[3:2])
+ tok_in: begin
+ direction_in <= 1'b1;
+ setup <= 1'bx;
+ state <= st_in;
+ end
+ tok_out: begin
+ direction_in <= 1'b0;
+ setup <= 1'b0;
+ end
+ tok_setup: begin
+ direction_in <= 1'b0;
+ setup <= 1'b1;
+ end
+ endcase
+ end else begin
+ transaction_active <= 1'b0;
+ endpoint <= 1'sbx;
+ direction_in <= 1'bx;
+ setup <= 1'bx;
+ end
+ end
+ pt_data: begin
+ if (recv_queue_1_valid && recv_crc16_ok) begin
+ if (handshake_latch == hs_ack || handshake_latch == hs_none)
+ success <= 1'b1;
+ state <= st_send_handshake;
+ end
+ end
+ default: begin
+ endpoint <= 1'sbx;
+ direction_in <= 1'bx;
+ setup <= 1'bx;
+ end
+ endcase
+ end else if (recv_datastrobe) begin
+ case (recv_pid[1:0])
+ pt_token: begin
+ if (recv_queue_1_valid)
+ state <= st_err;
+ end
+ pt_data: begin
+ if (recv_queue_1_valid && (handshake_latch == hs_ack || handshake_latch == hs_none))
+ data_strobe <= 1'b1;
+ end
+ default: begin
+ state <= st_err;
+ end
+ endcase
+ end
+ end
+ st_in: begin
+ tx_transmit <= tx_transmit;
+
+ if (!tx_transmit && recv_short_idle) begin
+ if (handshake != hs_ack && handshake != hs_none) begin
+ handshake_latch <= handshake;
+ state <= st_send_handshake;
+ end else begin
+ tx_data <= { !data_toggle, 3'b100, data_toggle, 3'b011 };
+ tx_transmit <= 1'b1;
+ end
+ end
+
+ if (tx_transmit && tx_data_strobe) begin
+ if (!data_in_valid) begin
+ if (handshake == hs_ack) begin
+ state <= st_prep_recv_ack;
+ end else begin
+ state <= st_err;
+ success <= 1'b1;
+ transaction_active <= 1'b0;
+ end
+ tx_enable_crc16 <= 1'b0;
+ tx_transmit <= 1'b0;
+ end else begin
+ tx_data <= data_in;
+ data_strobe <= 1'b1;
+ tx_enable_crc16 <= 1'b1;
+ end
+ end
+ end
+ st_prep_recv_ack: begin
+ token_timeout <= 7'h7f;
+ if (!tx_en && !recv_packet)
+ state <= st_recv_ack;
+ end
+ st_recv_ack: begin
+ if (recv_packet) begin
+ state <= st_err;
+ if (recv_pid == 4'b0010) begin
+ success <= 1'b1;
+ transaction_active <= 1'b0;
+ end
+ end
+ if (!token_active && !recv_packet)
+ state <= st_idle;
+ end
+ st_send_ack: begin
+ tx_transmit <= tx_transmit;
+
+ if (!tx_transmit && recv_short_idle) begin
+ tx_data <= 8'b11010010; // ACK
+ tx_transmit <= 1'b1;
+
+ end
+
+ if (tx_transmit && tx_data_strobe) begin
+ tx_transmit <= 1'b0;
+ state <= st_err;
+ end
+ end
+ st_send_handshake: begin
+ tx_transmit <= tx_transmit;
+
+ if (!tx_transmit && recv_short_idle) begin
+ case (handshake_latch)
+ hs_none: begin
+ state <= st_idle;
+ end
+ hs_ack: begin
+ tx_data <= 8'b11010010;
+ tx_transmit <= 1'b1;
+ end
+ hs_nak: begin
+ tx_data <= 8'b01011010;
+ tx_transmit <= 1'b1;
+ end
+ hs_stall: begin
+ tx_data <= 8'b00011110;
+ tx_transmit <= 1'b1;
+ end
+ endcase
+ end
+
+ if (tx_transmit && tx_data_strobe) begin
+ tx_transmit <= 1'b0;
+ state <= st_err;
+ end
+ end
+ default: begin
+ transaction_active <= 1'b0;
+ if (!tx_en && !recv_packet)
+ state <= st_idle;
+ end
+ endcase
+ end
+end
+
+endmodule
+module usb_ep(
+ input clk,
+
+ input direction_in,
+ input setup,
+ input success,
+ input[6:0] cnt,
+
+ output reg toggle,
+ output bank_usb,
+ output reg[1:0] handshake,
+ output bank_in,
+ output bank_out,
+ output in_data_valid,
+
+ input ctrl_dir_in,
+ output reg[15:0] ctrl_rd_data,
+ input[15:0] ctrl_wr_data,
+ input[1:0] ctrl_wr_en
+ );
+
+localparam
+ hs_ack = 2'b00,
+ hs_none = 2'b01,
+ hs_nak = 2'b10,
+ hs_stall = 2'b11;
+
+reg ep_setup;
+reg ep_out_full;
+reg ep_out_empty;
+reg ep_in_full;
+reg ep_out_stall;
+reg ep_in_stall;
+reg ep_out_toggle;
+reg ep_in_toggle;
+reg[6:0] ep_in_cnt;
+reg[6:0] ep_out_cnt;
+
+assign in_data_valid = (cnt != ep_in_cnt);
+assign bank_usb = 1'b0;
+assign bank_in = 1'b0;
+assign bank_out = 1'b0;
+
+always @(*) begin
+ if (!direction_in && setup)
+ toggle = 1'b0;
+ else if (ep_setup)
+ toggle = 1'b1;
+ else if (direction_in)
+ toggle = ep_in_toggle;
+ else
+ toggle = ep_out_toggle;
+end
+
+always @(*) begin
+ if (direction_in) begin
+ if (!ep_in_stall && !ep_setup && ep_in_full) begin
+ handshake = hs_ack;
+ end else if (!ep_setup && ep_in_stall) begin
+ handshake = hs_stall;
+ end else begin
+ handshake = hs_nak;
+ end
+ end else begin
+ if (setup || (!ep_out_stall && !ep_setup && ep_out_full)) begin
+ handshake = hs_ack;
+ end else if (!ep_setup && ep_out_stall) begin
+ handshake = hs_stall;
+ end else begin
+ handshake = hs_nak;
+ end
+ end
+end
+
+always @(*) begin
+ if (ctrl_dir_in) begin
+ ctrl_rd_data[15:8] = ep_in_cnt;
+ ctrl_rd_data[7:0] = { ep_in_toggle, ep_in_stall, 1'b0, !ep_in_full, ep_in_full };
+ end else begin
+ ctrl_rd_data[15:8] = ep_out_cnt;
+ ctrl_rd_data[7:0] = { ep_out_toggle, ep_out_stall, ep_setup, ep_out_empty, ep_out_full };
+ end
+end
+
+wire flush = ctrl_wr_data[5] || ctrl_wr_data[4] || ctrl_wr_data[3];
+
+always @(posedge clk) begin
+ if (success) begin
+ if (direction_in) begin
+ ep_in_full <= 1'b0;
+ ep_in_toggle <= !ep_in_toggle;
+ end else begin
+ if (setup)
+ ep_setup <= 1'b1;
+
+ ep_out_toggle <= !ep_out_toggle;
+ ep_out_empty <= 1'b0;
+ ep_out_full <= 1'b0;
+ ep_out_cnt <= cnt;
+ end
+ end
+
+ if (ctrl_wr_en[1] && ctrl_dir_in) begin
+ ep_in_cnt <= ctrl_wr_data[14:8];
+ end
+
+ if (ctrl_wr_en[0] && ctrl_dir_in) begin
+ if (ctrl_wr_data[5]) begin
+ ep_in_toggle <= 1'b0;
+ ep_in_stall <= 1'b0;
+ end
+ if (ctrl_wr_data[4]) begin
+ ep_in_toggle <= 1'b1;
+ ep_in_stall <= 1'b0;
+ end
+ if (ctrl_wr_data[3])
+ ep_in_stall <= 1'b1;
+
+ if (flush)
+ ep_in_full <= 1'b0;
+
+ if (ctrl_wr_data[0])
+ ep_in_full <= 1'b1;
+ end
+
+ if (ctrl_wr_en[0] && !ctrl_dir_in) begin
+ if (ctrl_wr_data[5]) begin
+ ep_out_toggle <= 1'b0;
+ ep_out_stall <= 1'b0;
+ end
+ if (ctrl_wr_data[4]) begin
+ ep_out_toggle <= 1'b1;
+ ep_out_stall <= 1'b0;
+ end
+ if (ctrl_wr_data[3])
+ ep_out_stall <= 1'b1;
+
+ if (flush) begin
+ ep_out_full <= 1'b0;
+ ep_out_empty <= 1'b1;
+ end
+
+ if (ctrl_wr_data[2])
+ ep_setup <= 1'b0;
+ if (ctrl_wr_data[1])
+ ep_out_empty <= 1'b1;
+ if (ctrl_wr_data[0])
+ ep_out_full <= 1'b1;
+ end
+end
+
+endmodule
+module usb_ep_banked(
+ input clk,
+
+ input direction_in,
+ input setup,
+ input success,
+ input[6:0] cnt,
+
+ output reg toggle,
+ output bank_usb,
+ output reg[1:0] handshake,
+ output bank_in,
+ output bank_out,
+ output in_data_valid,
+
+ input ctrl_dir_in,
+ output reg[15:0] ctrl_rd_data,
+ input[15:0] ctrl_wr_data,
+ input[1:0] ctrl_wr_en
+ );
+
+localparam
+ hs_ack = 2'b00,
+ hs_none = 2'b01,
+ hs_nak = 2'b10,
+ hs_stall = 2'b11;
+
+reg ep_setup;
+reg ep_out_full;
+reg ep_out_empty;
+reg ep_in_empty;
+reg ep_out_stall;
+reg ep_in_stall;
+reg ep_out_toggle;
+reg ep_in_toggle;
+reg ep_in_bank;
+reg[6:0] ep_in_cnt_0;
+reg[6:0] ep_in_cnt_1;
+reg[6:0] ep_out_cnt;
+
+assign in_data_valid = (cnt != (ep_in_toggle? ep_in_cnt_1: ep_in_cnt_0));
+assign bank_usb = direction_in? ep_in_toggle: 1'b0;
+assign bank_in = ep_in_bank;
+assign bank_out = 1'b0;
+
+always @(*) begin
+ if (!direction_in && setup)
+ toggle = 1'b0;
+ else if (ep_setup)
+ toggle = 1'b1;
+ else if (direction_in)
+ toggle = ep_in_toggle;
+ else
+ toggle = ep_out_toggle;
+end
+
+always @(*) begin
+ if (direction_in) begin
+ if (!ep_in_stall && !ep_setup && !ep_in_empty) begin
+ handshake = hs_ack;
+ end else if (!ep_setup && ep_in_stall) begin
+ handshake = hs_stall;
+ end else begin
+ handshake = hs_nak;
+ end
+ end else begin
+ if (setup || (!ep_out_stall && !ep_setup && ep_out_full)) begin
+ handshake = hs_ack;
+ end else if (!ep_setup && ep_out_stall) begin
+ handshake = hs_stall;
+ end else begin
+ handshake = hs_nak;
+ end
+ end
+end
+
+always @(*) begin
+ if (ctrl_dir_in) begin
+ ctrl_rd_data[15:8] = ep_in_bank? ep_in_cnt_1: ep_in_cnt_0;
+ ctrl_rd_data[7:0] = { ep_in_bank, ep_in_toggle, ep_in_stall, 1'b0, ep_in_empty, !ep_in_empty && ep_in_toggle == ep_in_bank };
+ end else begin
+ ctrl_rd_data[15:8] = ep_out_cnt;
+ ctrl_rd_data[7:0] = { ep_out_toggle, ep_out_stall, ep_setup, ep_out_empty, ep_out_full };
+ end
+end
+
+wire flush = ctrl_wr_data[5] || ctrl_wr_data[4] || ctrl_wr_data[3];
+
+always @(posedge clk) begin
+ if (success) begin
+ if (direction_in) begin
+ if (ep_in_toggle != ep_in_bank)
+ ep_in_empty <= 1'b1;
+ ep_in_toggle = !ep_in_toggle;
+ end else begin
+ if (setup)
+ ep_setup <= 1'b1;
+
+ ep_out_toggle = !ep_out_toggle;
+ ep_out_empty <= 1'b0;
+ ep_out_cnt <= cnt;
+ end
+ end
+
+ if (ctrl_wr_en[1] && ctrl_dir_in) begin
+ if (ep_in_bank)
+ ep_in_cnt_1 <= ctrl_wr_data[14:8];
+ else
+ ep_in_cnt_0 <= ctrl_wr_data[14:8];
+ end
+
+ if (ctrl_wr_en[0] && ctrl_dir_in) begin
+ if (ctrl_wr_data[5]) begin
+ ep_in_toggle = 1'b0;
+ ep_in_stall <= 1'b0;
+ ep_in_bank <= 1'b0;
+ end
+ if (ctrl_wr_data[4]) begin
+ ep_in_toggle = 1'b1;
+ ep_in_stall <= 1'b0;
+ ep_in_bank <= 1'b1;
+ end
+ if (ctrl_wr_data[3]) begin
+ ep_in_stall <= 1'b1;
+ ep_in_bank <= ep_in_toggle;
+ end
+
+ if (flush) begin
+ ep_in_empty <= 1'b1;
+ end
+
+ if (ctrl_wr_data[0]) begin
+ ep_in_empty <= 1'b0;
+ ep_in_bank <= !ep_in_bank;
+ end
+ end
+
+ if (ctrl_wr_en[0] && !ctrl_dir_in) begin
+ if (ctrl_wr_data[5]) begin
+ ep_out_toggle = 1'b0;
+ ep_out_stall <= 1'b0;
+ end
+ if (ctrl_wr_data[4]) begin
+ ep_out_toggle = 1'b1;
+ ep_out_stall <= 1'b0;
+ end
+ if (ctrl_wr_data[3])
+ ep_out_stall <= 1'b1;
+
+ if (flush) begin
+ ep_out_full <= 1'b0;
+ ep_out_empty <= 1'b1;
+ end
+
+ if (ctrl_wr_data[2])
+ ep_setup <= 1'b0;
+ if (ctrl_wr_data[1]) begin
+ ep_out_empty <= 1'b1;
+ ep_out_full <= 1'b0;
+ end
+ if (ctrl_wr_data[0])
+ ep_out_full <= 1'b1;
+ end
+end
+
+endmodule
+module usb_recv_sm(
+ input rst_n,
+ input clk,
+ input strobe,
+ input din,
+ input sync,
+ input se0,
+
+ output reg[3:0] xpid,
+ output reg[7:0] xdata,
+ output xpacket,
+ output reg xdatastrobe,
+ output reg xcrc5_ok,
+ output reg xcrc16_ok
+ );
+
+reg clear_shift;
+reg[7:0] shift_reg;
+reg[8:0] next_shift;
+
+always @(*) begin
+ if (clear_shift)
+ next_shift = { 7'b1, din };
+ else
+ next_shift = { shift_reg[7:0], din };
+end
+
+always @(posedge clk) begin
+ if (strobe) begin
+ shift_reg <= next_shift[7:0];
+ end
+end
+
+localparam
+ st_idle = 2'b00,
+ st_done = 2'b10,
+ st_pid = 2'b01,
+ st_data = 2'b11;
+
+reg[1:0] state;
+
+wire crc5_valid;
+usb_crc5 crc5(
+ .rst_n(rst_n && xpacket),
+ .clk(clk),
+ .clken(strobe),
+ .d(din),
+ .valid(crc5_valid)
+ );
+
+wire crc16_valid;
+usb_crc16 crc16(
+ .rst_n(rst_n && xpacket),
+ .clk(clk),
+ .clken(strobe),
+ .d(din),
+ .dump(1'b0),
+ .out(),
+ .valid(crc16_valid)
+ );
+
+assign xpacket = (state == st_data);
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ state <= st_idle;
+ clear_shift <= 1'bx;
+
+ xpid <= 1'sbx;
+ xdata <= 1'sbx;
+ xdatastrobe <= 1'b0;
+ xcrc5_ok <= 1'b0;
+ xcrc16_ok <= 1'b0;
+ end else if (strobe) begin
+ clear_shift <= 1'bx;
+ xdatastrobe <= 1'b0;
+
+ case (state)
+ st_idle: begin
+ if (sync && !se0) begin
+ state <= st_pid;
+ clear_shift <= 1'b1;
+ end
+ end
+ st_pid: begin
+ if (se0) begin
+ state <= st_idle;
+ end else begin
+ if (next_shift[8]) begin
+ if (next_shift[7:4] == ~next_shift[3:0]) begin
+ clear_shift <= 1'b1;
+ xpid <= { next_shift[4], next_shift[5], next_shift[6], next_shift[7] };
+ state <= st_data;
+ xcrc5_ok <= 1'b0;
+ xcrc16_ok <= 1'b0;
+ end else begin
+ state <= st_done;
+ end
+ end else begin
+ clear_shift <= 1'b0;
+ end
+ end
+ end
+ st_data: begin
+ if (se0) begin
+ state <= st_idle;
+ end else begin
+ clear_shift <= 1'b0;
+ if (next_shift[8]) begin
+ clear_shift <= 1'b1;
+ xdata <= {
+ next_shift[0], next_shift[1], next_shift[2], next_shift[3],
+ next_shift[4], next_shift[5], next_shift[6], next_shift[7] };
+ xdatastrobe <= 1'b1;
+ xcrc5_ok <= crc5_valid;
+ xcrc16_ok <= crc16_valid;
+ end
+ end
+ end
+ default: begin
+ if (se0)
+ state <= st_idle;
+ end
+ endcase
+ end
+end
+
+endmodule
+
+module usb_recv(
+ input rst_n,
+ input clk_48,
+
+ input rx_j,
+ input rx_se0,
+
+ output short_idle,
+ output usb_rst,
+
+ output[3:0] xpid,
+ output[7:0] xdata,
+ output xpacket,
+ output xdatastrobe,
+ output xcrc5_ok,
+ output xcrc16_ok
+ );
+
+wire j;
+multisample3 d_filter(
+ .clk(clk_48),
+ .in(rx_j),
+ .out(j));
+
+wire se0;
+multisample5 se0_filter(
+ .clk(clk_48),
+ .in(rx_se0),
+ .out(se0));
+
+reg[2:0] short_idle_counter;
+assign short_idle = short_idle_counter == 1'b0;
+always @(posedge clk_48) begin
+ if (se0 || !j || xpacket)
+ short_idle_counter <= 3'b111;
+ else if (short_idle_counter != 1'b0)
+ short_idle_counter <= short_idle_counter - 1'b1;
+end
+
+wire nrzi_strobe;
+usb_clk_recovery clk_rcvr(
+ .rst_n(rst_n),
+ .clk(clk_48),
+ .i(j),
+ .strobe(nrzi_strobe)
+ );
+
+wire d;
+nrzi_decode nrzi_decoder(
+ .clk(clk_48),
+ .clken(nrzi_strobe),
+ .i(j),
+ .o(d));
+
+wire strobe;
+usb_bit_destuff destuffer(
+ .rst_n(rst_n),
+ .clk(clk_48),
+ .clken(nrzi_strobe),
+ .d(d),
+ .strobe(strobe)
+ );
+
+usb_reset_detect reset_detect(
+ .rst_n(rst_n),
+ .clk(clk_48),
+ .se0(se0),
+ .usb_rst(usb_rst));
+
+wire sync_seq;
+usb_sync_detect sync_detect(
+ .rst_n(rst_n),
+ .clk(clk_48),
+ .clken(nrzi_strobe),
+ .j(j),
+ .se0(se0),
+ .sync(sync_seq));
+
+wire strobed_xdatastrobe;
+assign xdatastrobe = strobed_xdatastrobe && strobe;
+
+usb_recv_sm sm(
+ .rst_n(rst_n),
+ .clk(clk_48),
+ .strobe(strobe),
+ .din(d),
+ .sync(sync_seq),
+ .se0(se0),
+
+ .xpid(xpid),
+ .xdata(xdata),
+ .xpacket(xpacket),
+ .xdatastrobe(strobed_xdatastrobe),
+ .xcrc5_ok(xcrc5_ok),
+ .xcrc16_ok(xcrc16_ok)
+ );
+
+endmodule
+module usb_tx(
+ input rst_n,
+ input clk_48,
+
+ output tx_en,
+ output tx_j,
+ output tx_se0,
+
+ input transmit,
+ input[7:0] data,
+ input update_crc16,
+ input send_crc16,
+ output data_strobe
+ );
+
+reg[1:0] tx_clock;
+wire bit_strobe = tx_clock == 2'b00;
+always @(posedge clk_48 or negedge rst_n) begin
+ if (!rst_n) begin
+ tx_clock <= 2'b00;
+ end else begin
+ tx_clock <= tx_clock + 1'b1;
+ end
+end
+
+wire bit_stuff;
+wire tx_strobe = bit_strobe && !bit_stuff;
+
+reg[2:0] state;
+localparam
+ st_idle = 3'b000,
+ st_sync = 3'b101,
+ st_run = 3'b001,
+ st_eop1 = 3'b010,
+ st_eop2 = 3'b011,
+ st_eop3 = 3'b100,
+ st_crc1 = 3'b110,
+ st_crc2 = 3'b111;
+
+assign tx_en = (state != st_idle);
+
+reg[8:0] tx_data;
+reg crc_enabled;
+
+wire dump_crc = state == st_crc1 || state == st_crc2;
+wire crc_out;
+wire d = dump_crc? !crc_out: tx_data[0];
+wire se0 = !bit_stuff && (state == st_eop1 || state == st_eop2);
+
+wire tx_data_empty = (tx_data[8:2] == 1'b0);
+assign data_strobe = transmit && tx_data_empty && tx_strobe;
+
+always @(posedge clk_48 or negedge rst_n) begin
+ if (!rst_n) begin
+ state <= st_idle;
+ end else if (tx_strobe) begin
+ case (state)
+ st_idle: begin
+ if (transmit)
+ state <= st_run;
+ end
+ st_sync: begin
+ if (tx_data_empty)
+ state <= st_run;
+ end
+ st_run: begin
+ if (tx_data_empty && !transmit) begin
+ if (send_crc16)
+ state <= st_crc1;
+ else
+ state <= st_eop1;
+ end
+ end
+ st_crc1: begin
+ if (tx_data_empty)
+ state <= st_crc2;
+ end
+ st_crc2: begin
+ if (tx_data_empty)
+ state <= st_eop1;
+ end
+ st_eop1: begin
+ state <= st_eop2;
+ end
+ st_eop2: begin
+ state <= st_eop3;
+ end
+ st_eop3: begin
+ state <= st_idle;
+ end
+ endcase
+ end
+end
+
+always @(posedge clk_48) begin
+ if (tx_strobe) begin
+ if (!tx_en) begin
+ tx_data <= 9'b110000000; // starting with J, go through KJKJKJKK
+ crc_enabled <= 1'b0;
+ end else if (tx_data_empty) begin
+ tx_data <= { 1'b1, data };
+ crc_enabled <= update_crc16;
+ end else begin
+ tx_data <= { 1'b0, tx_data[8:1] };
+ end
+ end
+end
+
+reg[2:0] bit_stuff_counter;
+assign bit_stuff = bit_stuff_counter == 3'd6;
+always @(posedge clk_48 or negedge rst_n) begin
+ if (!rst_n) begin
+ bit_stuff_counter <= 1'b0;
+ end else if (bit_strobe) begin
+ if (state == st_idle || !d || bit_stuff || se0)
+ bit_stuff_counter <= 1'b0;
+ else
+ bit_stuff_counter <= bit_stuff_counter + 1'b1;
+ end
+end
+
+reg last_j;
+wire j = state == st_idle || state == st_eop3? 1'b1: ((bit_stuff || !d)? !last_j: last_j);
+always @(posedge clk_48) begin
+ if (bit_strobe)
+ last_j <= tx_en? j: 1'b1;
+end
+
+assign tx_j = j;
+assign tx_se0 = se0;
+
+usb_crc16 tx_crc(
+ .rst_n(rst_n && state != st_idle),
+ .clk(clk_48),
+ .clken(tx_strobe && (dump_crc || crc_enabled)),
+ .d(d),
+ .dump(dump_crc),
+ .out(crc_out),
+ .valid()
+ );
+
+endmodule
+module usb_crc5(
+ input rst_n,
+ input clk,
+ input clken,
+ input d,
+ output valid
+ );
+
+reg[4:0] r;
+reg[4:0] next;
+
+wire top = r[4];
+assign valid = (next == 5'b01100);
+
+always @(*) begin
+ if (top == d)
+ next = { r[3], r[2], r[1], r[0], 1'b0 };
+ else
+ next = { r[3], r[2], !r[1], r[0], 1'b1 };
+end
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ r <= 5'b11111;
+ end else if (clken) begin
+ r <= next;
+ end
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module usb_crc16(
+ input rst_n,
+ input clk,
+ input clken,
+ input d,
+
+ input dump,
+ output out,
+ output valid
+ );
+
+reg[15:0] r;
+reg[15:0] next;
+
+assign out = r[15];
+assign valid = (next == 16'b1000000000001101);
+
+always @(*) begin
+ if (dump || out == d)
+ next = { r[14:0], 1'b0 };
+ else
+ next = { !r[14], r[13:2], !r[1], r[0], 1'b1 };
+end
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ r <= 16'hffff;
+ end else if (clken) begin
+ r <= next;
+ end
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module usb_clk_recovery(
+ input rst_n,
+ input clk,
+ input i,
+ output strobe
+ );
+
+reg[1:0] cntr;
+reg prev_i;
+
+assign strobe = cntr == 1'b0;
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ cntr <= 1'b0;
+ prev_i <= 1'b0;
+ end else begin
+ if (i == prev_i) begin
+ cntr <= cntr - 1'b1;
+ end else begin
+ cntr <= 1'b1;
+ end
+ prev_i <= i;
+ end
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module usb_bit_destuff(
+ input rst_n,
+ input clk,
+ input clken,
+ input d,
+ output strobe);
+
+reg[6:0] data;
+assign strobe = clken && (data != 7'b0111111);
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ data <= 7'b0000000;
+ end else if (clken) begin
+ data <= { data[5:0], d };
+ end
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module usb_sync_detect(
+ input rst_n,
+ input clk,
+ input clken,
+ input j,
+ input se0,
+ output sync);
+
+// 3KJ's followed by 2K's
+reg[6:0] data;
+assign sync = (data == 7'b0101010 && !j && !se0);
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ data <= 1'd0;
+ end else if (clken) begin
+ data <= { data[5:0], j || se0 };
+ end
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module usb_reset_detect(
+ input rst_n,
+ input clk,
+ input se0,
+ output usb_rst);
+
+reg[18:0] cntr;
+assign usb_rst = cntr == 1'b0;
+
+always @(posedge clk or negedge rst_n) begin
+ if (!rst_n) begin
+ cntr <= 1'b0;
+ end else begin
+ if (se0) begin
+ if (!usb_rst)
+ cntr <= cntr - 1'b1;
+ end else begin
+ cntr <= 19'd480000;
+ end
+ end
+end
+
+endmodule
+module multisample3(
+ input clk,
+ input in,
+ output reg out
+ );
+
+reg[2:0] r;
+
+always @(r) begin
+ case (r)
+ 3'b000: out = 1'b0;
+ 3'b001: out = 1'b0;
+ 3'b010: out = 1'b0;
+ 3'b011: out = 1'b1;
+ 3'b100: out = 1'b0;
+ 3'b101: out = 1'b1;
+ 3'b110: out = 1'b1;
+ 3'b111: out = 1'b1;
+ endcase
+end
+
+always @(posedge clk) begin
+ r <= { r[1:0], in };
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module multisample5(
+ input clk,
+ input in,
+ output reg out
+ );
+
+reg[4:0] r;
+
+always @(r) begin
+ case (r)
+ 5'b00000: out = 1'b0;
+ 5'b00001: out = 1'b0;
+ 5'b00010: out = 1'b0;
+ 5'b00011: out = 1'b0;
+ 5'b00100: out = 1'b0;
+ 5'b00101: out = 1'b0;
+ 5'b00110: out = 1'b0;
+ 5'b00111: out = 1'b1;
+ 5'b01000: out = 1'b0;
+ 5'b01001: out = 1'b0;
+ 5'b01010: out = 1'b0;
+ 5'b01011: out = 1'b1;
+ 5'b01100: out = 1'b0;
+ 5'b01101: out = 1'b1;
+ 5'b01110: out = 1'b1;
+ 5'b01111: out = 1'b1;
+ 5'b10000: out = 1'b0;
+ 5'b10001: out = 1'b0;
+ 5'b10010: out = 1'b0;
+ 5'b10011: out = 1'b1;
+ 5'b10100: out = 1'b0;
+ 5'b10101: out = 1'b1;
+ 5'b10110: out = 1'b1;
+ 5'b10111: out = 1'b1;
+ 5'b11000: out = 1'b0;
+ 5'b11001: out = 1'b1;
+ 5'b11010: out = 1'b1;
+ 5'b11011: out = 1'b1;
+ 5'b11100: out = 1'b1;
+ 5'b11101: out = 1'b1;
+ 5'b11110: out = 1'b1;
+ 5'b11111: out = 1'b1;
+ endcase
+end
+
+always @(posedge clk) begin
+ r <= { r[3:0], in };
+end
+
+endmodule
+
+//---------------------------------------------------------------------
+module nrzi_decode(
+ input clk,
+ input clken,
+ input i,
+ output o
+ );
+
+reg prev_i;
+assign o = (prev_i == i);
+
+always @(posedge clk) begin
+ if (clken) begin
+ prev_i <= i;
+ end
+end
+
+endmodule
\ No newline at end of file
diff --git a/openlane/designs/usb_cdc_core/config.tcl b/openlane/designs/usb_cdc_core/config.tcl
new file mode 100755
index 0000000..d82c192
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/config.tcl
@@ -0,0 +1,16 @@
+
+# Design
+
+# User config
+set ::env(DESIGN_NAME) usb_cdc_core
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+set ::env(CLOCK_PORT) "clk_i"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..44d10cd
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "15.6"
+set ::env(FP_CORE_UTIL) 30
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) "0.32"
+
diff --git a/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..f98353a
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "15.6"
+set ::env(FP_CORE_UTIL) 45
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..f98353a
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "15.6"
+set ::env(FP_CORE_UTIL) 45
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..f98353a
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "15.6"
+set ::env(FP_CORE_UTIL) 45
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..f98353a
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "15.6"
+set ::env(FP_CORE_UTIL) 45
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/usb_cdc_core/src/usb_cdc_core.v b/openlane/designs/usb_cdc_core/src/usb_cdc_core.v
new file mode 100644
index 0000000..cd310a6
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usb_cdc_core.v
@@ -0,0 +1,1076 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module usb_cdc_core
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input enable_i
+ ,input [ 7:0] utmi_data_in_i
+ ,input utmi_txready_i
+ ,input utmi_rxvalid_i
+ ,input utmi_rxactive_i
+ ,input utmi_rxerror_i
+ ,input [ 1:0] utmi_linestate_i
+ ,input inport_valid_i
+ ,input [ 7:0] inport_data_i
+ ,input outport_accept_i
+
+ // Outputs
+ ,output [ 7:0] utmi_data_out_o
+ ,output utmi_txvalid_o
+ ,output [ 1:0] utmi_op_mode_o
+ ,output [ 1:0] utmi_xcvrselect_o
+ ,output utmi_termselect_o
+ ,output utmi_dppulldown_o
+ ,output utmi_dmpulldown_o
+ ,output inport_accept_o
+ ,output outport_valid_o
+ ,output [ 7:0] outport_data_o
+);
+
+
+
+
+parameter USB_SPEED_HS = "False"; // True or False
+
+//-----------------------------------------------------------------
+// Defines
+//-----------------------------------------------------------------
+// Device class
+`define DEV_CLASS_RESERVED 8'h00
+`define DEV_CLASS_AUDIO 8'h01
+`define DEV_CLASS_COMMS 8'h02
+`define DEV_CLASS_HID 8'h03
+`define DEV_CLASS_MONITOR 8'h04
+`define DEV_CLASS_PHY_IF 8'h05
+`define DEV_CLASS_POWER 8'h06
+`define DEV_CLASS_PRINTER 8'h07
+`define DEV_CLASS_STORAGE 8'h08
+`define DEV_CLASS_HUB 8'h09
+`define DEV_CLASS_TMC 8'hFE
+`define DEV_CLASS_VENDOR_CUSTOM 8'hFF
+
+// Standard requests (via SETUP packets)
+`define REQ_GET_STATUS 8'h00
+`define REQ_CLEAR_FEATURE 8'h01
+`define REQ_SET_FEATURE 8'h03
+`define REQ_SET_ADDRESS 8'h05
+`define REQ_GET_DESCRIPTOR 8'h06
+`define REQ_SET_DESCRIPTOR 8'h07
+`define REQ_GET_CONFIGURATION 8'h08
+`define REQ_SET_CONFIGURATION 8'h09
+`define REQ_GET_INTERFACE 8'h0A
+`define REQ_SET_INTERFACE 8'h0B
+`define REQ_SYNC_FRAME 8'h0C
+
+// Descriptor types
+`define DESC_DEVICE 8'h01
+`define DESC_CONFIGURATION 8'h02
+`define DESC_STRING 8'h03
+`define DESC_INTERFACE 8'h04
+`define DESC_ENDPOINT 8'h05
+`define DESC_DEV_QUALIFIER 8'h06
+`define DESC_OTHER_SPEED_CONF 8'h07
+`define DESC_IF_POWER 8'h08
+
+// Endpoints
+`define ENDPOINT_DIR_MASK 8'h80
+`define ENDPOINT_DIR_R 7
+`define ENDPOINT_DIR_IN 1'b1
+`define ENDPOINT_DIR_OUT 1'b0
+`define ENDPOINT_ADDR_MASK 8'h7F
+`define ENDPOINT_TYPE_MASK 8'h3
+`define ENDPOINT_TYPE_CONTROL 0
+`define ENDPOINT_TYPE_ISO 1
+`define ENDPOINT_TYPE_BULK 2
+`define ENDPOINT_TYPE_INTERRUPT 3
+
+// Device Requests (bmRequestType)
+`define USB_RECIPIENT_MASK 8'h1F
+`define USB_RECIPIENT_DEVICE 8'h00
+`define USB_RECIPIENT_INTERFACE 8'h01
+`define USB_RECIPIENT_ENDPOINT 8'h02
+`define USB_REQUEST_TYPE_MASK 8'h60
+`define USB_STANDARD_REQUEST 8'h00
+`define USB_CLASS_REQUEST 8'h20
+`define USB_VENDOR_REQUEST 8'h40
+
+// USB device addresses are 7-bits
+`define USB_ADDRESS_MASK 8'h7F
+
+// USB Feature Selectors
+`define USB_FEATURE_ENDPOINT_STATE 16'h0000
+`define USB_FEATURE_REMOTE_WAKEUP 16'h0001
+`define USB_FEATURE_TEST_MODE 16'h0002
+
+// String Descriptors
+`define UNICODE_LANGUAGE_STR_ID 8'd0
+`define MANUFACTURER_STR_ID 8'd1
+`define PRODUCT_NAME_STR_ID 8'd2
+`define SERIAL_NUM_STR_ID 8'd3
+
+`define CDC_ENDPOINT_BULK_OUT 1
+`define CDC_ENDPOINT_BULK_IN 2
+`define CDC_ENDPOINT_INTR_IN 3
+
+`define CDC_SEND_ENCAPSULATED_COMMAND 8'h00
+`define CDC_GET_ENCAPSULATED_RESPONSE 8'h01
+`define CDC_GET_LINE_CODING 8'h21
+`define CDC_SET_LINE_CODING 8'h20
+`define CDC_SET_CONTROL_LINE_STATE 8'h22
+`define CDC_SEND_BREAK 8'h23
+
+// Descriptor ROM offsets / sizes
+`define ROM_DESC_DEVICE_ADDR 8'd0
+`define ROM_DESC_DEVICE_SIZE 16'd18
+`define ROM_DESC_CONF_ADDR 8'd18
+`define ROM_DESC_CONF_SIZE 16'd67
+`define ROM_DESC_STR_LANG_ADDR 8'd85
+`define ROM_DESC_STR_LANG_SIZE 16'd4
+`define ROM_DESC_STR_MAN_ADDR 8'd89
+`define ROM_DESC_STR_MAN_SIZE 16'd30
+`define ROM_DESC_STR_PROD_ADDR 8'd119
+`define ROM_DESC_STR_PROD_SIZE 16'd30
+`define ROM_DESC_STR_SERIAL_ADDR 8'd149
+`define ROM_DESC_STR_SERIAL_SIZE 16'd14
+`define ROM_CDC_LINE_CODING_ADDR 8'd163
+`define ROM_CDC_LINE_CODING_SIZE 16'd7
+
+//-----------------------------------------------------------------
+// Wires
+//-----------------------------------------------------------------
+wire usb_reset_w;
+reg [6:0] device_addr_q;
+
+wire usb_ep0_tx_rd_w;
+wire [7:0] usb_ep0_tx_data_w;
+wire usb_ep0_tx_empty_w;
+
+wire usb_ep0_rx_wr_w;
+wire [7:0] usb_ep0_rx_data_w;
+wire usb_ep0_rx_full_w;
+wire usb_ep1_tx_rd_w;
+wire [7:0] usb_ep1_tx_data_w;
+wire usb_ep1_tx_empty_w;
+
+wire usb_ep1_rx_wr_w;
+wire [7:0] usb_ep1_rx_data_w;
+wire usb_ep1_rx_full_w;
+wire usb_ep2_tx_rd_w;
+wire [7:0] usb_ep2_tx_data_w;
+wire usb_ep2_tx_empty_w;
+
+wire usb_ep2_rx_wr_w;
+wire [7:0] usb_ep2_rx_data_w;
+wire usb_ep2_rx_full_w;
+wire usb_ep3_tx_rd_w;
+wire [7:0] usb_ep3_tx_data_w;
+wire usb_ep3_tx_empty_w;
+
+wire usb_ep3_rx_wr_w;
+wire [7:0] usb_ep3_rx_data_w;
+wire usb_ep3_rx_full_w;
+
+// Rx SIE Interface (shared)
+wire rx_strb_w;
+wire [7:0] rx_data_w;
+wire rx_last_w;
+wire rx_crc_err_w;
+
+// EP0 Rx SIE Interface
+wire ep0_rx_space_w;
+wire ep0_rx_valid_w;
+wire ep0_rx_setup_w;
+
+// EP0 Tx SIE Interface
+wire ep0_tx_ready_w;
+wire ep0_tx_data_valid_w;
+wire ep0_tx_data_strb_w;
+wire [7:0] ep0_tx_data_w;
+wire ep0_tx_data_last_w;
+wire ep0_tx_data_accept_w;
+wire ep0_tx_stall_w;
+// EP1 Rx SIE Interface
+wire ep1_rx_space_w;
+wire ep1_rx_valid_w;
+wire ep1_rx_setup_w;
+
+// EP1 Tx SIE Interface
+wire ep1_tx_ready_w;
+wire ep1_tx_data_valid_w;
+wire ep1_tx_data_strb_w;
+wire [7:0] ep1_tx_data_w;
+wire ep1_tx_data_last_w;
+wire ep1_tx_data_accept_w;
+wire ep1_tx_stall_w;
+// EP2 Rx SIE Interface
+wire ep2_rx_space_w;
+wire ep2_rx_valid_w;
+wire ep2_rx_setup_w;
+
+// EP2 Tx SIE Interface
+wire ep2_tx_ready_w;
+wire ep2_tx_data_valid_w;
+wire ep2_tx_data_strb_w;
+wire [7:0] ep2_tx_data_w;
+wire ep2_tx_data_last_w;
+wire ep2_tx_data_accept_w;
+wire ep2_tx_stall_w;
+// EP3 Rx SIE Interface
+wire ep3_rx_space_w;
+wire ep3_rx_valid_w;
+wire ep3_rx_setup_w;
+
+// EP3 Tx SIE Interface
+wire ep3_tx_ready_w;
+wire ep3_tx_data_valid_w;
+wire ep3_tx_data_strb_w;
+wire [7:0] ep3_tx_data_w;
+wire ep3_tx_data_last_w;
+wire ep3_tx_data_accept_w;
+wire ep3_tx_stall_w;
+
+wire utmi_chirp_en_w;
+wire usb_hs_w;
+
+//-----------------------------------------------------------------
+// Transceiver Control (high speed)
+//-----------------------------------------------------------------
+generate
+if (USB_SPEED_HS == "True")
+begin
+
+localparam STATE_W = 3;
+localparam STATE_IDLE = 3'd0;
+localparam STATE_WAIT_RST = 3'd1;
+localparam STATE_SEND_CHIRP_K = 3'd2;
+localparam STATE_WAIT_CHIRP_JK = 3'd3;
+localparam STATE_FULLSPEED = 3'd4;
+localparam STATE_HIGHSPEED = 3'd5;
+reg [STATE_W-1:0] state_q;
+reg [STATE_W-1:0] next_state_r;
+
+// 60MHz clock rate
+`define USB_RST_W 20
+reg [`USB_RST_W-1:0] usb_rst_time_q;
+reg [7:0] chirp_count_q;
+reg [1:0] last_linestate_q;
+
+localparam DETACH_TIME = 20'd60000; // 1ms -> T0
+localparam ATTACH_FS_TIME = 20'd180000; // T0 + 3ms = T1
+localparam CHIRPK_TIME = 20'd246000; // T1 + ~1ms
+localparam HS_RESET_TIME = 20'd600000; // T0 + 10ms = T9
+localparam HS_CHIRP_COUNT = 8'd5;
+
+reg [ 1:0] utmi_op_mode_r;
+reg [ 1:0] utmi_xcvrselect_r;
+reg utmi_termselect_r;
+reg utmi_dppulldown_r;
+reg utmi_dmpulldown_r;
+
+always @ *
+begin
+ next_state_r = state_q;
+
+ // Default - disconnect
+ utmi_op_mode_r = 2'd1;
+ utmi_xcvrselect_r = 2'd0;
+ utmi_termselect_r = 1'b0;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+
+ case (state_q)
+ STATE_IDLE:
+ begin
+ // Detached
+ if (enable_i && usb_rst_time_q >= DETACH_TIME)
+ next_state_r = STATE_WAIT_RST;
+ end
+ STATE_WAIT_RST:
+ begin
+ // Assert FS mode, check for SE0 (T0)
+ utmi_op_mode_r = 2'd0;
+ utmi_xcvrselect_r = 2'd1;
+ utmi_termselect_r = 1'b1;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+
+ // Wait for SE0 (T1), send device chirp K
+ if (usb_rst_time_q >= ATTACH_FS_TIME)
+ next_state_r = STATE_SEND_CHIRP_K;
+ end
+ STATE_SEND_CHIRP_K:
+ begin
+ // Send chirp K
+ utmi_op_mode_r = 2'd2;
+ utmi_xcvrselect_r = 2'd0;
+ utmi_termselect_r = 1'b1;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+
+ // End of device chirp K (T2)
+ if (usb_rst_time_q >= CHIRPK_TIME)
+ next_state_r = STATE_WAIT_CHIRP_JK;
+ end
+ STATE_WAIT_CHIRP_JK:
+ begin
+ // Stop sending chirp K and wait for downstream port chirps
+ utmi_op_mode_r = 2'd2;
+ utmi_xcvrselect_r = 2'd0;
+ utmi_termselect_r = 1'b1;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+
+ // Required number of chirps detected, move to HS mode (T7)
+ if (chirp_count_q >= HS_CHIRP_COUNT)
+ next_state_r = STATE_HIGHSPEED;
+ // Time out waiting for chirps, fallback to FS mode
+ else if (usb_rst_time_q >= HS_RESET_TIME)
+ next_state_r = STATE_FULLSPEED;
+ end
+ STATE_FULLSPEED:
+ begin
+ utmi_op_mode_r = 2'd0;
+ utmi_xcvrselect_r = 2'd1;
+ utmi_termselect_r = 1'b1;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+
+ // USB reset detected...
+ if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
+ next_state_r = STATE_WAIT_RST;
+ end
+ STATE_HIGHSPEED:
+ begin
+ // Enter HS mode
+ utmi_op_mode_r = 2'd0;
+ utmi_xcvrselect_r = 2'd0;
+ utmi_termselect_r = 1'b0;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+
+ // Long SE0 - could be reset or suspend
+ // TODO: Should revert to FS mode and check...
+ if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
+ next_state_r = STATE_WAIT_RST;
+ end
+ default:
+ ;
+ endcase
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ state_q <= STATE_IDLE;
+else
+ state_q <= next_state_r;
+
+// Time since T0 (start of HS reset)
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ usb_rst_time_q <= `USB_RST_W'b0;
+// Entering wait for reset state
+else if (next_state_r == STATE_WAIT_RST && state_q != STATE_WAIT_RST)
+ usb_rst_time_q <= `USB_RST_W'b0;
+// Waiting for reset, reset count on line state toggle
+else if (state_q == STATE_WAIT_RST && (utmi_linestate_i != 2'b00))
+ usb_rst_time_q <= `USB_RST_W'b0;
+else if (usb_rst_time_q != {(`USB_RST_W){1'b1}})
+ usb_rst_time_q <= usb_rst_time_q + `USB_RST_W'd1;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ last_linestate_q <= 2'b0;
+else
+ last_linestate_q <= utmi_linestate_i;
+
+// Chirp counter
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ chirp_count_q <= 8'b0;
+else if (state_q == STATE_SEND_CHIRP_K)
+ chirp_count_q <= 8'b0;
+else if (state_q == STATE_WAIT_CHIRP_JK && (last_linestate_q != utmi_linestate_i) && chirp_count_q != 8'hFF)
+ chirp_count_q <= chirp_count_q + 8'd1;
+
+assign utmi_op_mode_o = utmi_op_mode_r;
+assign utmi_xcvrselect_o = utmi_xcvrselect_r;
+assign utmi_termselect_o = utmi_termselect_r;
+assign utmi_dppulldown_o = utmi_dppulldown_r;
+assign utmi_dmpulldown_o = utmi_dmpulldown_r;
+
+assign utmi_chirp_en_w = (state_q == STATE_SEND_CHIRP_K);
+assign usb_hs_w = (state_q == STATE_HIGHSPEED);
+
+end
+else
+begin
+//-----------------------------------------------------------------
+// Transceiver Control
+//-----------------------------------------------------------------
+reg [ 1:0] utmi_op_mode_r;
+reg [ 1:0] utmi_xcvrselect_r;
+reg utmi_termselect_r;
+reg utmi_dppulldown_r;
+reg utmi_dmpulldown_r;
+
+always @ *
+begin
+ if (enable_i)
+ begin
+ utmi_op_mode_r = 2'd0;
+ utmi_xcvrselect_r = 2'd1;
+ utmi_termselect_r = 1'b1;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+ end
+ else
+ begin
+ utmi_op_mode_r = 2'd1;
+ utmi_xcvrselect_r = 2'd0;
+ utmi_termselect_r = 1'b0;
+ utmi_dppulldown_r = 1'b0;
+ utmi_dmpulldown_r = 1'b0;
+ end
+end
+
+assign utmi_op_mode_o = utmi_op_mode_r;
+assign utmi_xcvrselect_o = utmi_xcvrselect_r;
+assign utmi_termselect_o = utmi_termselect_r;
+assign utmi_dppulldown_o = utmi_dppulldown_r;
+assign utmi_dmpulldown_o = utmi_dmpulldown_r;
+
+assign utmi_chirp_en_w = 1'b0;
+assign usb_hs_w = 1'b0;
+
+end
+endgenerate
+
+//-----------------------------------------------------------------
+// Core
+//-----------------------------------------------------------------
+usbf_device_core
+u_core
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ .intr_o(),
+
+ // UTMI interface
+ .utmi_data_o(utmi_data_out_o),
+ .utmi_data_i(utmi_data_in_i),
+ .utmi_txvalid_o(utmi_txvalid_o),
+ .utmi_txready_i(utmi_txready_i),
+ .utmi_rxvalid_i(utmi_rxvalid_i),
+ .utmi_rxactive_i(utmi_rxactive_i),
+ .utmi_rxerror_i(utmi_rxerror_i),
+ .utmi_linestate_i(utmi_linestate_i),
+
+ .reg_chirp_en_i(utmi_chirp_en_w),
+ .reg_int_en_sof_i(1'b0),
+
+ .reg_dev_addr_i(device_addr_q),
+
+ // Rx SIE Interface (shared)
+ .rx_strb_o(rx_strb_w),
+ .rx_data_o(rx_data_w),
+ .rx_last_o(rx_last_w),
+ .rx_crc_err_o(rx_crc_err_w),
+
+ // EP0 Config
+ .ep0_iso_i(1'b0),
+ .ep0_stall_i(ep0_tx_stall_w),
+ .ep0_cfg_int_rx_i(1'b0),
+ .ep0_cfg_int_tx_i(1'b0),
+
+ // EP0 Rx SIE Interface
+ .ep0_rx_setup_o(ep0_rx_setup_w),
+ .ep0_rx_valid_o(ep0_rx_valid_w),
+ .ep0_rx_space_i(ep0_rx_space_w),
+
+ // EP0 Tx SIE Interface
+ .ep0_tx_ready_i(ep0_tx_ready_w),
+ .ep0_tx_data_valid_i(ep0_tx_data_valid_w),
+ .ep0_tx_data_strb_i(ep0_tx_data_strb_w),
+ .ep0_tx_data_i(ep0_tx_data_w),
+ .ep0_tx_data_last_i(ep0_tx_data_last_w),
+ .ep0_tx_data_accept_o(ep0_tx_data_accept_w),
+
+ // EP1 Config
+ .ep1_iso_i(1'b0),
+ .ep1_stall_i(ep1_tx_stall_w),
+ .ep1_cfg_int_rx_i(1'b0),
+ .ep1_cfg_int_tx_i(1'b0),
+
+ // EP1 Rx SIE Interface
+ .ep1_rx_setup_o(ep1_rx_setup_w),
+ .ep1_rx_valid_o(ep1_rx_valid_w),
+ .ep1_rx_space_i(ep1_rx_space_w),
+
+ // EP1 Tx SIE Interface
+ .ep1_tx_ready_i(ep1_tx_ready_w),
+ .ep1_tx_data_valid_i(ep1_tx_data_valid_w),
+ .ep1_tx_data_strb_i(ep1_tx_data_strb_w),
+ .ep1_tx_data_i(ep1_tx_data_w),
+ .ep1_tx_data_last_i(ep1_tx_data_last_w),
+ .ep1_tx_data_accept_o(ep1_tx_data_accept_w),
+
+ // EP2 Config
+ .ep2_iso_i(1'b0),
+ .ep2_stall_i(ep2_tx_stall_w),
+ .ep2_cfg_int_rx_i(1'b0),
+ .ep2_cfg_int_tx_i(1'b0),
+
+ // EP2 Rx SIE Interface
+ .ep2_rx_setup_o(ep2_rx_setup_w),
+ .ep2_rx_valid_o(ep2_rx_valid_w),
+ .ep2_rx_space_i(ep2_rx_space_w),
+
+ // EP2 Tx SIE Interface
+ .ep2_tx_ready_i(ep2_tx_ready_w),
+ .ep2_tx_data_valid_i(ep2_tx_data_valid_w),
+ .ep2_tx_data_strb_i(ep2_tx_data_strb_w),
+ .ep2_tx_data_i(ep2_tx_data_w),
+ .ep2_tx_data_last_i(ep2_tx_data_last_w),
+ .ep2_tx_data_accept_o(ep2_tx_data_accept_w),
+
+ // EP3 Config
+ .ep3_iso_i(1'b0),
+ .ep3_stall_i(ep3_tx_stall_w),
+ .ep3_cfg_int_rx_i(1'b0),
+ .ep3_cfg_int_tx_i(1'b0),
+
+ // EP3 Rx SIE Interface
+ .ep3_rx_setup_o(ep3_rx_setup_w),
+ .ep3_rx_valid_o(ep3_rx_valid_w),
+ .ep3_rx_space_i(ep3_rx_space_w),
+
+ // EP3 Tx SIE Interface
+ .ep3_tx_ready_i(ep3_tx_ready_w),
+ .ep3_tx_data_valid_i(ep3_tx_data_valid_w),
+ .ep3_tx_data_strb_i(ep3_tx_data_strb_w),
+ .ep3_tx_data_i(ep3_tx_data_w),
+ .ep3_tx_data_last_i(ep3_tx_data_last_w),
+ .ep3_tx_data_accept_o(ep3_tx_data_accept_w),
+
+ // Status
+ .reg_sts_rst_clr_i(1'b1),
+ .reg_sts_rst_o(usb_reset_w),
+ .reg_sts_frame_num_o()
+);
+
+assign ep0_rx_space_w = 1'b1;
+
+//-----------------------------------------------------------------
+// USB: Setup packet capture (limited to 8 bytes for USB-FS)
+//-----------------------------------------------------------------
+reg [7:0] setup_packet_q[0:7];
+reg [2:0] setup_wr_idx_q;
+reg setup_frame_q;
+reg setup_valid_q;
+reg status_ready_q; // STATUS response received
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ setup_packet_q[0] <= 8'b0;
+ setup_packet_q[1] <= 8'b0;
+ setup_packet_q[2] <= 8'b0;
+ setup_packet_q[3] <= 8'b0;
+ setup_packet_q[4] <= 8'b0;
+ setup_packet_q[5] <= 8'b0;
+ setup_packet_q[6] <= 8'b0;
+ setup_packet_q[7] <= 8'b0;
+ setup_wr_idx_q <= 3'b0;
+ setup_valid_q <= 1'b0;
+ setup_frame_q <= 1'b0;
+ status_ready_q <= 1'b0;
+end
+// SETUP token received
+else if (ep0_rx_setup_w)
+begin
+ setup_packet_q[0] <= 8'b0;
+ setup_packet_q[1] <= 8'b0;
+ setup_packet_q[2] <= 8'b0;
+ setup_packet_q[3] <= 8'b0;
+ setup_packet_q[4] <= 8'b0;
+ setup_packet_q[5] <= 8'b0;
+ setup_packet_q[6] <= 8'b0;
+ setup_packet_q[7] <= 8'b0;
+ setup_wr_idx_q <= 3'b0;
+ setup_valid_q <= 1'b0;
+ setup_frame_q <= 1'b1;
+ status_ready_q <= 1'b0;
+end
+// Valid DATA for setup frame
+else if (ep0_rx_valid_w && rx_strb_w)
+begin
+ setup_packet_q[setup_wr_idx_q] <= rx_data_w;
+ setup_wr_idx_q <= setup_wr_idx_q + 3'd1;
+ setup_valid_q <= setup_frame_q && rx_last_w;
+ if (rx_last_w)
+ setup_frame_q <= 1'b0;
+end
+// Detect STATUS stage (ACK for SETUP GET requests)
+// TODO: Not quite correct ....
+else if (ep0_rx_valid_w && !rx_strb_w && rx_last_w)
+begin
+ setup_valid_q <= 1'b0;
+ status_ready_q <= 1'b1;
+end
+else
+ setup_valid_q <= 1'b0;
+
+//-----------------------------------------------------------------
+// SETUP request decode
+//-----------------------------------------------------------------
+wire [7:0] bmRequestType_w = setup_packet_q[0];
+wire [7:0] bRequest_w = setup_packet_q[1];
+wire [15:0] wValue_w = {setup_packet_q[3], setup_packet_q[2]};
+wire [15:0] wIndex_w = {setup_packet_q[5], setup_packet_q[4]};
+wire [15:0] wLength = {setup_packet_q[7], setup_packet_q[6]};
+
+wire setup_get_w = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_IN);
+wire setup_set_w = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_OUT);
+wire setup_no_data_w = setup_set_w && (wLength == 16'b0);
+
+// For REQ_GET_DESCRIPTOR
+wire [7:0] bDescriptorType_w = setup_packet_q[3];
+wire [7:0] bDescriptorIndex_w = setup_packet_q[2];
+
+//-----------------------------------------------------------------
+// Process setup request
+//-----------------------------------------------------------------
+reg ctrl_stall_r; // Send STALL
+reg ctrl_ack_r; // Send STATUS (ZLP)
+reg [15:0] ctrl_get_len_r;
+
+reg [7:0] desc_addr_r;
+
+reg addressed_q;
+reg addressed_r;
+reg [6:0] device_addr_r;
+
+reg configured_q;
+reg configured_r;
+
+always @ *
+begin
+ ctrl_stall_r = 1'b0;
+ ctrl_get_len_r = 16'b0;
+ ctrl_ack_r = 1'b0;
+ desc_addr_r = 8'b0;
+ device_addr_r = device_addr_q;
+ addressed_r = addressed_q;
+ configured_r = configured_q;
+
+ if (setup_valid_q)
+ begin
+ case (bmRequestType_w & `USB_REQUEST_TYPE_MASK)
+ `USB_STANDARD_REQUEST:
+ begin
+ case (bRequest_w)
+ `REQ_GET_STATUS:
+ begin
+ $display("GET_STATUS");
+ end
+ `REQ_CLEAR_FEATURE:
+ begin
+ $display("CLEAR_FEATURE");
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ end
+ `REQ_SET_FEATURE:
+ begin
+ $display("SET_FEATURE");
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ end
+ `REQ_SET_ADDRESS:
+ begin
+ $display("SET_ADDRESS: Set device address %d", wValue_w[6:0]);
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ device_addr_r = wValue_w[6:0];
+ addressed_r = 1'b1;
+ end
+ `REQ_GET_DESCRIPTOR:
+ begin
+ $display("GET_DESCRIPTOR: Type %d", bDescriptorType_w);
+
+ case (bDescriptorType_w)
+ `DESC_DEVICE:
+ begin
+ desc_addr_r = `ROM_DESC_DEVICE_ADDR;
+ ctrl_get_len_r = `ROM_DESC_DEVICE_SIZE;
+ end
+ `DESC_CONFIGURATION:
+ begin
+ desc_addr_r = `ROM_DESC_CONF_ADDR;
+ ctrl_get_len_r = `ROM_DESC_CONF_SIZE;
+ end
+ `DESC_STRING:
+ begin
+ case (bDescriptorIndex_w)
+ `UNICODE_LANGUAGE_STR_ID:
+ begin
+ desc_addr_r = `ROM_DESC_STR_LANG_ADDR;
+ ctrl_get_len_r = `ROM_DESC_STR_LANG_SIZE;
+ end
+ `MANUFACTURER_STR_ID:
+ begin
+ desc_addr_r = `ROM_DESC_STR_MAN_ADDR;
+ ctrl_get_len_r = `ROM_DESC_STR_MAN_SIZE;
+ end
+ `PRODUCT_NAME_STR_ID:
+ begin
+ desc_addr_r = `ROM_DESC_STR_PROD_ADDR;
+ ctrl_get_len_r = `ROM_DESC_STR_PROD_SIZE;
+ end
+ `SERIAL_NUM_STR_ID:
+ begin
+ desc_addr_r = `ROM_DESC_STR_SERIAL_ADDR;
+ ctrl_get_len_r = `ROM_DESC_STR_SERIAL_SIZE;
+ end
+ default:
+ ;
+ endcase
+ end
+ default:
+ ;
+ endcase
+ end
+ `REQ_GET_CONFIGURATION:
+ begin
+ $display("GET_CONF");
+ end
+ `REQ_SET_CONFIGURATION:
+ begin
+ $display("SET_CONF: Configuration %x", wValue_w);
+
+ if (wValue_w == 16'd0)
+ begin
+ configured_r = 1'b0;
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ end
+ // Only support one configuration for now
+ else if (wValue_w == 16'd1)
+ begin
+ configured_r = 1'b1;
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ end
+ else
+ ctrl_stall_r = 1'b1;
+ end
+ `REQ_GET_INTERFACE:
+ begin
+ $display("GET_INTERFACE");
+ ctrl_stall_r = 1'b1;
+ end
+ `REQ_SET_INTERFACE:
+ begin
+ $display("SET_INTERFACE: %x %x", wValue_w, wIndex_w);
+ if (wValue_w == 16'd0 && wIndex_w == 16'd0)
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ else
+ ctrl_stall_r = 1'b1;
+ end
+ default:
+ begin
+ ctrl_stall_r = 1'b1;
+ end
+ endcase
+ end
+ `USB_VENDOR_REQUEST:
+ begin
+ // None supported
+ ctrl_stall_r = 1'b1;
+ end
+ `USB_CLASS_REQUEST:
+ begin
+ case (bRequest_w)
+ `CDC_GET_LINE_CODING:
+ begin
+ $display("CDC_GET_LINE_CODING");
+ desc_addr_r = `ROM_CDC_LINE_CODING_ADDR;
+ ctrl_get_len_r = `ROM_CDC_LINE_CODING_SIZE;
+ end
+ default:
+ ctrl_ack_r = setup_set_w && setup_no_data_w;
+ endcase
+ end
+ default:
+ begin
+ ctrl_stall_r = 1'b1;
+ end
+ endcase
+ end
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ device_addr_q <= 7'b0;
+ addressed_q <= 1'b0;
+ configured_q <= 1'b0;
+end
+else if (usb_reset_w)
+begin
+ device_addr_q <= 7'b0;
+ addressed_q <= 1'b0;
+ configured_q <= 1'b0;
+end
+else
+begin
+ device_addr_q <= device_addr_r;
+ addressed_q <= addressed_r;
+ configured_q <= configured_r;
+end
+
+//-----------------------------------------------------------------
+// SETUP response
+//-----------------------------------------------------------------
+reg ctrl_sending_q;
+reg [15:0] ctrl_send_idx_q;
+reg [15:0] ctrl_send_len_q;
+wire ctrl_send_zlp_w = ctrl_sending_q && (ctrl_send_len_q != wLength);
+
+reg ctrl_sending_r;
+reg [15:0] ctrl_send_idx_r;
+reg [15:0] ctrl_send_len_r;
+
+reg ctrl_txvalid_q;
+reg [7:0] ctrl_txdata_q;
+reg ctrl_txstrb_q;
+reg ctrl_txlast_q;
+reg ctrl_txstall_q;
+
+reg ctrl_txvalid_r;
+reg [7:0] ctrl_txdata_r;
+reg ctrl_txstrb_r;
+reg ctrl_txlast_r;
+reg ctrl_txstall_r;
+
+wire ctrl_send_accept_w = ep0_tx_data_accept_w || !ep0_tx_data_valid_w;
+
+reg [7:0] desc_addr_q;
+wire[7:0] desc_data_w;
+
+always @ *
+begin
+ ctrl_sending_r = ctrl_sending_q;
+ ctrl_send_idx_r = ctrl_send_idx_q;
+ ctrl_send_len_r = ctrl_send_len_q;
+
+ ctrl_txvalid_r = ctrl_txvalid_q;
+ ctrl_txdata_r = ctrl_txdata_q;
+ ctrl_txstrb_r = ctrl_txstrb_q;
+ ctrl_txlast_r = ctrl_txlast_q;
+ ctrl_txstall_r = ctrl_txstall_q;
+
+ // New SETUP request
+ if (setup_valid_q)
+ begin
+ // Send STALL
+ if (ctrl_stall_r)
+ begin
+ ctrl_txvalid_r = 1'b1;
+ ctrl_txstrb_r = 1'b0;
+ ctrl_txlast_r = 1'b1;
+ ctrl_txstall_r = 1'b1;
+ end
+ // Send STATUS response (ZLP)
+ else if (ctrl_ack_r)
+ begin
+ ctrl_txvalid_r = 1'b1;
+ ctrl_txstrb_r = 1'b0;
+ ctrl_txlast_r = 1'b1;
+ ctrl_txstall_r = 1'b0;
+ end
+ else
+ begin
+ ctrl_sending_r = setup_get_w && !ctrl_stall_r;
+ ctrl_send_idx_r = 16'b0;
+ ctrl_send_len_r = ctrl_get_len_r;
+ ctrl_txstall_r = 1'b0;
+ end
+ end
+ // Abort control send when STATUS received
+ else if (status_ready_q)
+ begin
+ ctrl_sending_r = 1'b0;
+ ctrl_send_idx_r = 16'b0;
+ ctrl_send_len_r = 16'b0;
+
+ ctrl_txvalid_r = 1'b0;
+ end
+ else if (ctrl_sending_r && ctrl_send_accept_w)
+ begin
+ // TODO: Send ZLP on exact multiple lengths...
+ ctrl_txvalid_r = 1'b1;
+ ctrl_txdata_r = desc_data_w;
+ ctrl_txstrb_r = 1'b1;
+ ctrl_txlast_r = usb_hs_w ? (ctrl_send_idx_r[5:0] == 6'b111111) : (ctrl_send_idx_r[2:0] == 3'b111);
+
+ // Increment send index
+ ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
+
+ // TODO: Detect need for ZLP
+ if (ctrl_send_idx_r == wLength)
+ begin
+ ctrl_sending_r = 1'b0;
+ ctrl_txlast_r = 1'b1;
+ end
+ end
+ else if (ctrl_send_accept_w)
+ ctrl_txvalid_r = 1'b0;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ ctrl_sending_q <= 1'b0;
+ ctrl_send_idx_q <= 16'b0;
+ ctrl_send_len_q <= 16'b0;
+ ctrl_txvalid_q <= 1'b0;
+ ctrl_txdata_q <= 8'b0;
+ ctrl_txstrb_q <= 1'b0;
+ ctrl_txlast_q <= 1'b0;
+ ctrl_txstall_q <= 1'b0;
+ desc_addr_q <= 8'b0;
+end
+else if (usb_reset_w)
+begin
+ ctrl_sending_q <= 1'b0;
+ ctrl_send_idx_q <= 16'b0;
+ ctrl_send_len_q <= 16'b0;
+ ctrl_txvalid_q <= 1'b0;
+ ctrl_txdata_q <= 8'b0;
+ ctrl_txstrb_q <= 1'b0;
+ ctrl_txlast_q <= 1'b0;
+ ctrl_txstall_q <= 1'b0;
+ desc_addr_q <= 8'b0;
+end
+else
+begin
+ ctrl_sending_q <= ctrl_sending_r;
+ ctrl_send_idx_q <= ctrl_send_idx_r;
+ ctrl_send_len_q <= ctrl_send_len_r;
+ ctrl_txvalid_q <= ctrl_txvalid_r;
+ ctrl_txdata_q <= ctrl_txdata_r;
+ ctrl_txstrb_q <= ctrl_txstrb_r;
+ ctrl_txlast_q <= ctrl_txlast_r;
+ ctrl_txstall_q <= ctrl_txstall_r;
+
+ if (setup_valid_q)
+ desc_addr_q <= desc_addr_r;
+ else if (ctrl_sending_r && ctrl_send_accept_w)
+ desc_addr_q <= desc_addr_q + 8'd1;
+end
+
+assign ep0_tx_ready_w = ctrl_txvalid_q;
+assign ep0_tx_data_valid_w = ctrl_txvalid_q;
+assign ep0_tx_data_strb_w = ctrl_txstrb_q;
+assign ep0_tx_data_w = ctrl_txdata_q;
+assign ep0_tx_data_last_w = ctrl_txlast_q;
+assign ep0_tx_stall_w = ctrl_txstall_q;
+
+//-----------------------------------------------------------------
+// Descriptor ROM
+//-----------------------------------------------------------------
+usb_desc_rom
+u_rom
+(
+ .hs_i(usb_hs_w),
+ .addr_i(desc_addr_q),
+ .data_o(desc_data_w)
+);
+
+//-----------------------------------------------------------------
+// Unused Endpoints
+//-----------------------------------------------------------------
+assign ep1_tx_ready_w = 1'b0;
+assign ep1_tx_data_valid_w = 1'b0;
+assign ep1_tx_data_strb_w = 1'b0;
+assign ep1_tx_data_w = 8'b0;
+assign ep1_tx_data_last_w = 1'b0;
+assign ep1_tx_stall_w = 1'b0;
+assign ep3_tx_ready_w = 1'b0;
+assign ep3_tx_data_valid_w = 1'b0;
+assign ep3_tx_data_strb_w = 1'b0;
+assign ep3_tx_data_w = 8'b0;
+assign ep3_tx_data_last_w = 1'b0;
+assign ep3_tx_stall_w = 1'b0;
+
+assign ep2_rx_space_w = 1'b0;
+assign ep3_rx_space_w = 1'b0;
+
+//-----------------------------------------------------------------
+// Stream I/O
+//-----------------------------------------------------------------
+reg inport_valid_q;
+reg [7:0] inport_data_q;
+wire inport_last_w = !inport_valid_i;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ inport_valid_q <= 1'b0;
+ inport_data_q <= 8'b0;
+end
+else if (inport_accept_o)
+begin
+ inport_valid_q <= inport_valid_i;
+ inport_data_q <= inport_data_i;
+end
+
+assign ep2_tx_data_valid_w = inport_valid_q;
+assign ep2_tx_data_w = inport_data_q;
+assign ep2_tx_ready_w = ep2_tx_data_valid_w;
+assign ep2_tx_data_strb_w = ep2_tx_data_valid_w;
+assign ep2_tx_data_last_w = inport_last_w;
+assign inport_accept_o = !inport_valid_q | ep2_tx_data_accept_w;
+
+assign outport_valid_o = ep1_rx_valid_w && rx_strb_w;
+assign outport_data_o = rx_data_w;
+assign ep1_rx_space_w = outport_accept_i;
+
+
+
+endmodule
diff --git a/openlane/designs/usb_cdc_core/src/usb_desc_rom.v b/openlane/designs/usb_cdc_core/src/usb_desc_rom.v
new file mode 100644
index 0000000..d8afe5e
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usb_desc_rom.v
@@ -0,0 +1,226 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+module usb_desc_rom
+(
+ input hs_i,
+ input [7:0] addr_i,
+ output [7:0] data_o
+);
+
+reg [7:0] desc_rom_r;
+
+always @ *
+begin
+ case (addr_i)
+ 8'd0: desc_rom_r = 8'h12;
+ 8'd1: desc_rom_r = 8'h01;
+ 8'd2: desc_rom_r = 8'h00;
+ 8'd3: desc_rom_r = 8'h02;
+ 8'd4: desc_rom_r = 8'h02;
+ 8'd5: desc_rom_r = 8'h00;
+ 8'd6: desc_rom_r = 8'h00;
+ 8'd7: desc_rom_r = hs_i ? 8'h40 : 8'h08;
+ 8'd8: desc_rom_r = 8'h50; // VID_L
+ 8'd9: desc_rom_r = 8'h1d; // VID_H
+ 8'd10: desc_rom_r = 8'h49; // PID_L
+ 8'd11: desc_rom_r = 8'h61; // PID_H
+ 8'd12: desc_rom_r = 8'h01;
+ 8'd13: desc_rom_r = 8'h01;
+ 8'd14: desc_rom_r = 8'h00;
+ 8'd15: desc_rom_r = 8'h00;
+ 8'd16: desc_rom_r = 8'h00;
+ 8'd17: desc_rom_r = 8'h01;
+ 8'd18: desc_rom_r = 8'h09;
+ 8'd19: desc_rom_r = 8'h02;
+ 8'd20: desc_rom_r = 8'h43;
+ 8'd21: desc_rom_r = 8'h00;
+ 8'd22: desc_rom_r = 8'h02;
+ 8'd23: desc_rom_r = 8'h01;
+ 8'd24: desc_rom_r = 8'h00;
+ 8'd25: desc_rom_r = 8'h80;
+ 8'd26: desc_rom_r = 8'h32;
+ 8'd27: desc_rom_r = 8'h09;
+ 8'd28: desc_rom_r = 8'h04;
+ 8'd29: desc_rom_r = 8'h00;
+ 8'd30: desc_rom_r = 8'h00;
+ 8'd31: desc_rom_r = 8'h01;
+ 8'd32: desc_rom_r = 8'h02;
+ 8'd33: desc_rom_r = 8'h02;
+ 8'd34: desc_rom_r = 8'h01;
+ 8'd35: desc_rom_r = 8'h00;
+ 8'd36: desc_rom_r = 8'h05;
+ 8'd37: desc_rom_r = 8'h24;
+ 8'd38: desc_rom_r = 8'h00;
+ 8'd39: desc_rom_r = 8'h10;
+ 8'd40: desc_rom_r = 8'h01;
+ 8'd41: desc_rom_r = 8'h05;
+ 8'd42: desc_rom_r = 8'h24;
+ 8'd43: desc_rom_r = 8'h01;
+ 8'd44: desc_rom_r = 8'h03;
+ 8'd45: desc_rom_r = 8'h01;
+ 8'd46: desc_rom_r = 8'h04;
+ 8'd47: desc_rom_r = 8'h24;
+ 8'd48: desc_rom_r = 8'h02;
+ 8'd49: desc_rom_r = 8'h06;
+ 8'd50: desc_rom_r = 8'h05;
+ 8'd51: desc_rom_r = 8'h24;
+ 8'd52: desc_rom_r = 8'h06;
+ 8'd53: desc_rom_r = 8'h00;
+ 8'd54: desc_rom_r = 8'h01;
+ 8'd55: desc_rom_r = 8'h07;
+ 8'd56: desc_rom_r = 8'h05;
+ 8'd57: desc_rom_r = 8'h83;
+ 8'd58: desc_rom_r = 8'h03;
+ 8'd59: desc_rom_r = 8'h40;
+ 8'd60: desc_rom_r = 8'h00;
+ 8'd61: desc_rom_r = 8'h02;
+ 8'd62: desc_rom_r = 8'h09;
+ 8'd63: desc_rom_r = 8'h04;
+ 8'd64: desc_rom_r = 8'h01;
+ 8'd65: desc_rom_r = 8'h00;
+ 8'd66: desc_rom_r = 8'h02;
+ 8'd67: desc_rom_r = 8'h0a;
+ 8'd68: desc_rom_r = 8'h00;
+ 8'd69: desc_rom_r = 8'h00;
+ 8'd70: desc_rom_r = 8'h00;
+ 8'd71: desc_rom_r = 8'h07;
+ 8'd72: desc_rom_r = 8'h05;
+ 8'd73: desc_rom_r = 8'h01;
+ 8'd74: desc_rom_r = 8'h02;
+ 8'd75: desc_rom_r = hs_i ? 8'h00 : 8'h40;
+ 8'd76: desc_rom_r = hs_i ? 8'h02 : 8'h00;
+ 8'd77: desc_rom_r = 8'h00;
+ 8'd78: desc_rom_r = 8'h07;
+ 8'd79: desc_rom_r = 8'h05;
+ 8'd80: desc_rom_r = 8'h82;
+ 8'd81: desc_rom_r = 8'h02;
+ 8'd82: desc_rom_r = hs_i ? 8'h00 : 8'h40;
+ 8'd83: desc_rom_r = hs_i ? 8'h02 : 8'h00;
+ 8'd84: desc_rom_r = 8'h00;
+ 8'd85: desc_rom_r = 8'h04;
+ 8'd86: desc_rom_r = 8'h03;
+ 8'd87: desc_rom_r = 8'h09;
+ 8'd88: desc_rom_r = 8'h04;
+ 8'd89: desc_rom_r = 8'h1e;
+ 8'd90: desc_rom_r = 8'h03;
+ 8'd91: desc_rom_r = 8'h55;
+ 8'd92: desc_rom_r = 8'h00;
+ 8'd93: desc_rom_r = 8'h4c;
+ 8'd94: desc_rom_r = 8'h00;
+ 8'd95: desc_rom_r = 8'h54;
+ 8'd96: desc_rom_r = 8'h00;
+ 8'd97: desc_rom_r = 8'h52;
+ 8'd98: desc_rom_r = 8'h00;
+ 8'd99: desc_rom_r = 8'h41;
+ 8'd100: desc_rom_r = 8'h00;
+ 8'd101: desc_rom_r = 8'h2d;
+ 8'd102: desc_rom_r = 8'h00;
+ 8'd103: desc_rom_r = 8'h45;
+ 8'd104: desc_rom_r = 8'h00;
+ 8'd105: desc_rom_r = 8'h4d;
+ 8'd106: desc_rom_r = 8'h00;
+ 8'd107: desc_rom_r = 8'h42;
+ 8'd108: desc_rom_r = 8'h00;
+ 8'd109: desc_rom_r = 8'h45;
+ 8'd110: desc_rom_r = 8'h00;
+ 8'd111: desc_rom_r = 8'h44;
+ 8'd112: desc_rom_r = 8'h00;
+ 8'd113: desc_rom_r = 8'h44;
+ 8'd114: desc_rom_r = 8'h00;
+ 8'd115: desc_rom_r = 8'h45;
+ 8'd116: desc_rom_r = 8'h00;
+ 8'd117: desc_rom_r = 8'h44;
+ 8'd118: desc_rom_r = 8'h00;
+ 8'd119: desc_rom_r = 8'h1e;
+ 8'd120: desc_rom_r = 8'h03;
+ 8'd121: desc_rom_r = 8'h55;
+ 8'd122: desc_rom_r = 8'h00;
+ 8'd123: desc_rom_r = 8'h53;
+ 8'd124: desc_rom_r = 8'h00;
+ 8'd125: desc_rom_r = 8'h42;
+ 8'd126: desc_rom_r = 8'h00;
+ 8'd127: desc_rom_r = 8'h20;
+ 8'd128: desc_rom_r = 8'h00;
+ 8'd129: desc_rom_r = 8'h44;
+ 8'd130: desc_rom_r = 8'h00;
+ 8'd131: desc_rom_r = 8'h45;
+ 8'd132: desc_rom_r = 8'h00;
+ 8'd133: desc_rom_r = 8'h4d;
+ 8'd134: desc_rom_r = 8'h00;
+ 8'd135: desc_rom_r = 8'h4f;
+ 8'd136: desc_rom_r = 8'h00;
+ 8'd137: desc_rom_r = 8'h20;
+ 8'd138: desc_rom_r = 8'h00;
+ 8'd139: desc_rom_r = 8'h20;
+ 8'd140: desc_rom_r = 8'h00;
+ 8'd141: desc_rom_r = 8'h20;
+ 8'd142: desc_rom_r = 8'h00;
+ 8'd143: desc_rom_r = 8'h20;
+ 8'd144: desc_rom_r = 8'h00;
+ 8'd145: desc_rom_r = 8'h20;
+ 8'd146: desc_rom_r = 8'h00;
+ 8'd147: desc_rom_r = 8'h20;
+ 8'd148: desc_rom_r = 8'h00;
+ 8'd149: desc_rom_r = 8'h0e;
+ 8'd150: desc_rom_r = 8'h03;
+ 8'd151: desc_rom_r = 8'h30;
+ 8'd152: desc_rom_r = 8'h00;
+ 8'd153: desc_rom_r = 8'h30;
+ 8'd154: desc_rom_r = 8'h00;
+ 8'd155: desc_rom_r = 8'h30;
+ 8'd156: desc_rom_r = 8'h00;
+ 8'd157: desc_rom_r = 8'h30;
+ 8'd158: desc_rom_r = 8'h00;
+ 8'd159: desc_rom_r = 8'h30;
+ 8'd160: desc_rom_r = 8'h00;
+ 8'd161: desc_rom_r = 8'h30;
+ 8'd162: desc_rom_r = 8'h00;
+ 8'd163: desc_rom_r = 8'h00;
+ 8'd164: desc_rom_r = 8'hc2;
+ 8'd165: desc_rom_r = 8'h01;
+ 8'd166: desc_rom_r = 8'h00;
+ 8'd167: desc_rom_r = 8'h00;
+ 8'd168: desc_rom_r = 8'h00;
+ 8'd169: desc_rom_r = 8'h08;
+ default: desc_rom_r = 8'h00;
+ endcase
+end
+
+assign data_o = desc_rom_r;
+
+endmodule
diff --git a/openlane/designs/usb_cdc_core/src/usbf_crc16.v b/openlane/designs/usb_cdc_core/src/usbf_crc16.v
new file mode 100644
index 0000000..d9c7930
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usbf_crc16.v
@@ -0,0 +1,83 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module usbf_crc16
+(
+ // Inputs
+ input [ 15:0] crc_in_i
+ ,input [ 7:0] din_i
+
+ // Outputs
+ ,output [ 15:0] crc_out_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Logic
+//-----------------------------------------------------------------
+assign crc_out_o[15] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
+ crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
+assign crc_out_o[14] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^
+ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
+assign crc_out_o[13] = din_i[6] ^ din_i[7] ^
+ crc_in_i[7] ^ crc_in_i[6];
+assign crc_out_o[12] = din_i[5] ^ din_i[6] ^
+ crc_in_i[6] ^ crc_in_i[5];
+assign crc_out_o[11] = din_i[4] ^ din_i[5] ^
+ crc_in_i[5] ^ crc_in_i[4];
+assign crc_out_o[10] = din_i[3] ^ din_i[4] ^
+ crc_in_i[4] ^ crc_in_i[3];
+assign crc_out_o[9] = din_i[2] ^ din_i[3] ^
+ crc_in_i[3] ^ crc_in_i[2];
+assign crc_out_o[8] = din_i[1] ^ din_i[2] ^
+ crc_in_i[2] ^ crc_in_i[1];
+assign crc_out_o[7] = din_i[0] ^ din_i[1] ^
+ crc_in_i[15] ^ crc_in_i[1] ^ crc_in_i[0];
+assign crc_out_o[6] = din_i[0] ^
+ crc_in_i[14] ^ crc_in_i[0];
+assign crc_out_o[5] = crc_in_i[13];
+assign crc_out_o[4] = crc_in_i[12];
+assign crc_out_o[3] = crc_in_i[11];
+assign crc_out_o[2] = crc_in_i[10];
+assign crc_out_o[1] = crc_in_i[9];
+assign crc_out_o[0] = din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
+ crc_in_i[8] ^ crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
+
+
+endmodule
diff --git a/openlane/designs/usb_cdc_core/src/usbf_defs.v b/openlane/designs/usb_cdc_core/src/usbf_defs.v
new file mode 100644
index 0000000..cb29274
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usbf_defs.v
@@ -0,0 +1,64 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+//-----------------------------------------------------------------
+// Definitions
+//-----------------------------------------------------------------
+
+// Tokens
+`define PID_OUT 8'hE1
+`define PID_IN 8'h69
+`define PID_SOF 8'hA5
+`define PID_SETUP 8'h2D
+
+// Data
+`define PID_DATA0 8'hC3
+`define PID_DATA1 8'h4B
+`define PID_DATA2 8'h87
+`define PID_MDATA 8'h0F
+
+// Handshake
+`define PID_ACK 8'hD2
+`define PID_NAK 8'h5A
+`define PID_STALL 8'h1E
+`define PID_NYET 8'h96
+
+// Special
+`define PID_PRE 8'h3C
+`define PID_ERR 8'h3C
+`define PID_SPLIT 8'h78
+`define PID_PING 8'hB4
diff --git a/openlane/designs/usb_cdc_core/src/usbf_device_core.v b/openlane/designs/usb_cdc_core/src/usbf_device_core.v
new file mode 100644
index 0000000..14bd339
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usbf_device_core.v
@@ -0,0 +1,1020 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module usbf_device_core
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input [ 7:0] utmi_data_i
+ ,input utmi_txready_i
+ ,input utmi_rxvalid_i
+ ,input utmi_rxactive_i
+ ,input utmi_rxerror_i
+ ,input [ 1:0] utmi_linestate_i
+ ,input ep0_stall_i
+ ,input ep0_iso_i
+ ,input ep0_cfg_int_rx_i
+ ,input ep0_cfg_int_tx_i
+ ,input ep0_rx_space_i
+ ,input ep0_tx_ready_i
+ ,input ep0_tx_data_valid_i
+ ,input ep0_tx_data_strb_i
+ ,input [ 7:0] ep0_tx_data_i
+ ,input ep0_tx_data_last_i
+ ,input ep1_stall_i
+ ,input ep1_iso_i
+ ,input ep1_cfg_int_rx_i
+ ,input ep1_cfg_int_tx_i
+ ,input ep1_rx_space_i
+ ,input ep1_tx_ready_i
+ ,input ep1_tx_data_valid_i
+ ,input ep1_tx_data_strb_i
+ ,input [ 7:0] ep1_tx_data_i
+ ,input ep1_tx_data_last_i
+ ,input ep2_stall_i
+ ,input ep2_iso_i
+ ,input ep2_cfg_int_rx_i
+ ,input ep2_cfg_int_tx_i
+ ,input ep2_rx_space_i
+ ,input ep2_tx_ready_i
+ ,input ep2_tx_data_valid_i
+ ,input ep2_tx_data_strb_i
+ ,input [ 7:0] ep2_tx_data_i
+ ,input ep2_tx_data_last_i
+ ,input ep3_stall_i
+ ,input ep3_iso_i
+ ,input ep3_cfg_int_rx_i
+ ,input ep3_cfg_int_tx_i
+ ,input ep3_rx_space_i
+ ,input ep3_tx_ready_i
+ ,input ep3_tx_data_valid_i
+ ,input ep3_tx_data_strb_i
+ ,input [ 7:0] ep3_tx_data_i
+ ,input ep3_tx_data_last_i
+ ,input reg_chirp_en_i
+ ,input reg_int_en_sof_i
+ ,input reg_sts_rst_clr_i
+ ,input [ 6:0] reg_dev_addr_i
+
+ // Outputs
+ ,output intr_o
+ ,output [ 7:0] utmi_data_o
+ ,output utmi_txvalid_o
+ ,output rx_strb_o
+ ,output [ 7:0] rx_data_o
+ ,output rx_last_o
+ ,output rx_crc_err_o
+ ,output ep0_rx_setup_o
+ ,output ep0_rx_valid_o
+ ,output ep0_tx_data_accept_o
+ ,output ep1_rx_setup_o
+ ,output ep1_rx_valid_o
+ ,output ep1_tx_data_accept_o
+ ,output ep2_rx_setup_o
+ ,output ep2_rx_valid_o
+ ,output ep2_tx_data_accept_o
+ ,output ep3_rx_setup_o
+ ,output ep3_rx_valid_o
+ ,output ep3_tx_data_accept_o
+ ,output reg_sts_rst_o
+ ,output [ 10:0] reg_sts_frame_num_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+`include "usbf_defs.v"
+
+`define USB_RESET_CNT_W 15
+
+localparam STATE_W = 3;
+localparam STATE_RX_IDLE = 3'd0;
+localparam STATE_RX_DATA = 3'd1;
+localparam STATE_RX_DATA_READY = 3'd2;
+localparam STATE_RX_DATA_IGNORE = 3'd3;
+localparam STATE_TX_DATA = 3'd4;
+localparam STATE_TX_DATA_COMPLETE = 3'd5;
+localparam STATE_TX_HANDSHAKE = 3'd6;
+localparam STATE_TX_CHIRP = 3'd7;
+reg [STATE_W-1:0] state_q;
+
+//-----------------------------------------------------------------
+// Reset detection
+//-----------------------------------------------------------------
+reg [`USB_RESET_CNT_W-1:0] se0_cnt_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ se0_cnt_q <= `USB_RESET_CNT_W'b0;
+else if (utmi_linestate_i == 2'b0)
+begin
+ if (!se0_cnt_q[`USB_RESET_CNT_W-1])
+ se0_cnt_q <= se0_cnt_q + `USB_RESET_CNT_W'd1;
+end
+else
+ se0_cnt_q <= `USB_RESET_CNT_W'b0;
+
+wire usb_rst_w = se0_cnt_q[`USB_RESET_CNT_W-1];
+
+//-----------------------------------------------------------------
+// Wire / Regs
+//-----------------------------------------------------------------
+`define USB_FRAME_W 11
+wire [`USB_FRAME_W-1:0] frame_num_w;
+
+wire frame_valid_w;
+
+`define USB_DEV_W 7
+wire [`USB_DEV_W-1:0] token_dev_w;
+
+`define USB_EP_W 4
+wire [`USB_EP_W-1:0] token_ep_w;
+
+`define USB_PID_W 8
+wire [`USB_PID_W-1:0] token_pid_w;
+
+wire token_valid_w;
+
+wire rx_data_valid_w;
+wire rx_data_complete_w;
+
+wire rx_handshake_w;
+
+reg tx_data_valid_r;
+reg tx_data_strb_r;
+reg [7:0] tx_data_r;
+reg tx_data_last_r;
+wire tx_data_accept_w;
+
+reg tx_valid_q;
+reg [7:0] tx_pid_q;
+wire tx_accept_w;
+
+reg rx_space_q;
+reg rx_space_r;
+reg tx_ready_r;
+reg ep_data_bit_r;
+
+reg ep_stall_r;
+reg ep_iso_r;
+
+reg rx_enable_q;
+reg rx_setup_q;
+
+reg ep0_data_bit_q;
+reg ep1_data_bit_q;
+reg ep2_data_bit_q;
+reg ep3_data_bit_q;
+
+wire status_stage_w;
+
+reg [`USB_DEV_W-1:0] current_addr_q;
+
+//-----------------------------------------------------------------
+// SIE - TX
+//-----------------------------------------------------------------
+usbf_sie_tx
+u_sie_tx
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ .enable_i(~usb_rst_w),
+ .chirp_i(reg_chirp_en_i),
+
+ // UTMI Interface
+ .utmi_data_o(utmi_data_o),
+ .utmi_txvalid_o(utmi_txvalid_o),
+ .utmi_txready_i(utmi_txready_i),
+
+ // Request
+ .tx_valid_i(tx_valid_q),
+ .tx_pid_i(tx_pid_q),
+ .tx_accept_o(tx_accept_w),
+
+ // Data
+ .data_valid_i(tx_data_valid_r),
+ .data_strb_i(tx_data_strb_r),
+ .data_i(tx_data_r),
+ .data_last_i(tx_data_last_r),
+ .data_accept_o(tx_data_accept_w)
+);
+
+always @ *
+begin
+ tx_data_valid_r = 1'b0;
+ tx_data_strb_r = 1'b0;
+ tx_data_r = 8'b0;
+ tx_data_last_r = 1'b0;
+
+ case (token_ep_w)
+ 4'd0:
+ begin
+ tx_data_valid_r = ep0_tx_data_valid_i;
+ tx_data_strb_r = ep0_tx_data_strb_i;
+ tx_data_r = ep0_tx_data_i;
+ tx_data_last_r = ep0_tx_data_last_i;
+ end
+ 4'd1:
+ begin
+ tx_data_valid_r = ep1_tx_data_valid_i;
+ tx_data_strb_r = ep1_tx_data_strb_i;
+ tx_data_r = ep1_tx_data_i;
+ tx_data_last_r = ep1_tx_data_last_i;
+ end
+ 4'd2:
+ begin
+ tx_data_valid_r = ep2_tx_data_valid_i;
+ tx_data_strb_r = ep2_tx_data_strb_i;
+ tx_data_r = ep2_tx_data_i;
+ tx_data_last_r = ep2_tx_data_last_i;
+ end
+ 4'd3:
+ begin
+ tx_data_valid_r = ep3_tx_data_valid_i;
+ tx_data_strb_r = ep3_tx_data_strb_i;
+ tx_data_r = ep3_tx_data_i;
+ tx_data_last_r = ep3_tx_data_last_i;
+ end
+ default:
+ ;
+ endcase
+end
+
+assign ep0_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd0);
+assign ep1_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd1);
+assign ep2_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd2);
+assign ep3_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd3);
+
+always @ *
+begin
+ rx_space_r = 1'b0;
+ tx_ready_r = 1'b0;
+ ep_data_bit_r = 1'b0;
+
+ ep_stall_r = 1'b0;
+ ep_iso_r = 1'b0;
+
+ case (token_ep_w)
+ 4'd0:
+ begin
+ rx_space_r = ep0_rx_space_i;
+ tx_ready_r = ep0_tx_ready_i;
+ ep_data_bit_r = ep0_data_bit_q | status_stage_w;
+ ep_stall_r = ep0_stall_i;
+ ep_iso_r = ep0_iso_i;
+ end
+ 4'd1:
+ begin
+ rx_space_r = ep1_rx_space_i;
+ tx_ready_r = ep1_tx_ready_i;
+ ep_data_bit_r = ep1_data_bit_q | status_stage_w;
+ ep_stall_r = ep1_stall_i;
+ ep_iso_r = ep1_iso_i;
+ end
+ 4'd2:
+ begin
+ rx_space_r = ep2_rx_space_i;
+ tx_ready_r = ep2_tx_ready_i;
+ ep_data_bit_r = ep2_data_bit_q | status_stage_w;
+ ep_stall_r = ep2_stall_i;
+ ep_iso_r = ep2_iso_i;
+ end
+ 4'd3:
+ begin
+ rx_space_r = ep3_rx_space_i;
+ tx_ready_r = ep3_tx_ready_i;
+ ep_data_bit_r = ep3_data_bit_q | status_stage_w;
+ ep_stall_r = ep3_stall_i;
+ ep_iso_r = ep3_iso_i;
+ end
+ default:
+ ;
+ endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_space_q <= 1'b0;
+else if (state_q == STATE_RX_IDLE)
+ rx_space_q <= rx_space_r;
+
+//-----------------------------------------------------------------
+// SIE - RX
+//-----------------------------------------------------------------
+usbf_sie_rx
+u_sie_rx
+(
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+
+ .enable_i(~usb_rst_w && ~reg_chirp_en_i),
+
+ // UTMI Interface
+ .utmi_data_i(utmi_data_i),
+ .utmi_rxvalid_i(utmi_rxvalid_i),
+ .utmi_rxactive_i(utmi_rxactive_i),
+
+ .current_addr_i(current_addr_q),
+
+ .pid_o(token_pid_w),
+
+ .frame_valid_o(frame_valid_w),
+ .frame_number_o(reg_sts_frame_num_o),
+
+ .token_valid_o(token_valid_w),
+ .token_addr_o(token_dev_w),
+ .token_ep_o(token_ep_w),
+ .token_crc_err_o(),
+
+ .handshake_valid_o(rx_handshake_w),
+
+ .data_valid_o(rx_data_valid_w),
+ .data_strb_o(rx_strb_o),
+ .data_o(rx_data_o),
+ .data_last_o(rx_last_o),
+
+ .data_complete_o(rx_data_complete_w),
+ .data_crc_err_o(rx_crc_err_o)
+);
+
+assign ep0_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd0);
+assign ep0_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+assign ep1_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd1);
+assign ep1_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+assign ep2_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd2);
+assign ep2_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+assign ep3_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd3);
+assign ep3_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+
+//-----------------------------------------------------------------
+// Next state
+//-----------------------------------------------------------------
+reg [STATE_W-1:0] next_state_r;
+
+always @ *
+begin
+ next_state_r = state_q;
+
+ //-----------------------------------------
+ // State Machine
+ //-----------------------------------------
+ case (state_q)
+
+ //-----------------------------------------
+ // IDLE
+ //-----------------------------------------
+ STATE_RX_IDLE :
+ begin
+ // Token received (OUT, IN, SETUP, PING)
+ if (token_valid_w)
+ begin
+ //-------------------------------
+ // IN transfer (device -> host)
+ //-------------------------------
+ if (token_pid_w == `PID_IN)
+ begin
+ // Stalled endpoint?
+ if (ep_stall_r)
+ next_state_r = STATE_TX_HANDSHAKE;
+ // Some data to TX?
+ else if (tx_ready_r)
+ next_state_r = STATE_TX_DATA;
+ // No data to TX
+ else
+ next_state_r = STATE_TX_HANDSHAKE;
+ end
+ //-------------------------------
+ // PING transfer (device -> host)
+ //-------------------------------
+ else if (token_pid_w == `PID_PING)
+ begin
+ next_state_r = STATE_TX_HANDSHAKE;
+ end
+ //-------------------------------
+ // OUT transfer (host -> device)
+ //-------------------------------
+ else if (token_pid_w == `PID_OUT)
+ begin
+ // Stalled endpoint?
+ if (ep_stall_r)
+ next_state_r = STATE_RX_DATA_IGNORE;
+ // Some space to rx
+ else if (rx_space_r)
+ next_state_r = STATE_RX_DATA;
+ // No rx space, ignore receive
+ else
+ next_state_r = STATE_RX_DATA_IGNORE;
+ end
+ //-------------------------------
+ // SETUP transfer (host -> device)
+ //-------------------------------
+ else if (token_pid_w == `PID_SETUP)
+ begin
+ // Some space to rx
+ if (rx_space_r)
+ next_state_r = STATE_RX_DATA;
+ // No rx space, ignore receive
+ else
+ next_state_r = STATE_RX_DATA_IGNORE;
+ end
+ end
+ else if (reg_chirp_en_i)
+ next_state_r = STATE_TX_CHIRP;
+ end
+
+ //-----------------------------------------
+ // RX_DATA
+ //-----------------------------------------
+ STATE_RX_DATA :
+ begin
+ // TODO: Exit data state handling?
+
+ // TODO: Sort out ISO data bit handling
+ // Check for expected DATAx PID
+ if ((token_pid_w == `PID_DATA0 && ep_data_bit_r && !ep_iso_r) ||
+ (token_pid_w == `PID_DATA1 && !ep_data_bit_r && !ep_iso_r))
+ next_state_r = STATE_RX_DATA_IGNORE;
+ // Receive complete
+ else if (rx_data_valid_w && rx_last_o)
+ next_state_r = STATE_RX_DATA_READY;
+ end
+ //-----------------------------------------
+ // RX_DATA_IGNORE
+ //-----------------------------------------
+ STATE_RX_DATA_IGNORE :
+ begin
+ // Receive complete
+ if (rx_data_valid_w && rx_last_o)
+ next_state_r = STATE_RX_DATA_READY;
+ end
+ //-----------------------------------------
+ // RX_DATA_READY
+ //-----------------------------------------
+ STATE_RX_DATA_READY :
+ begin
+ if (rx_data_complete_w)
+ begin
+ // No response on CRC16 error
+ if (rx_crc_err_o)
+ next_state_r = STATE_RX_IDLE;
+ // ISO endpoint, no response?
+ else if (ep_iso_r)
+ next_state_r = STATE_RX_IDLE;
+ else
+ next_state_r = STATE_TX_HANDSHAKE;
+ end
+ end
+ //-----------------------------------------
+ // TX_DATA
+ //-----------------------------------------
+ STATE_TX_DATA :
+ begin
+ if (!tx_valid_q || tx_accept_w)
+ if (tx_data_valid_r && tx_data_last_r && tx_data_accept_w)
+ next_state_r = STATE_TX_DATA_COMPLETE;
+ end
+ //-----------------------------------------
+ // TX_HANDSHAKE
+ //-----------------------------------------
+ STATE_TX_DATA_COMPLETE :
+ begin
+ next_state_r = STATE_RX_IDLE;
+ end
+ //-----------------------------------------
+ // TX_HANDSHAKE
+ //-----------------------------------------
+ STATE_TX_HANDSHAKE :
+ begin
+ if (tx_accept_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+ //-----------------------------------------
+ // TX_CHIRP
+ //-----------------------------------------
+ STATE_TX_CHIRP :
+ begin
+ if (!reg_chirp_en_i)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ default :
+ ;
+
+ endcase
+
+ //-----------------------------------------
+ // USB Bus Reset (HOST->DEVICE)
+ //-----------------------------------------
+ if (usb_rst_w && !reg_chirp_en_i)
+ next_state_r = STATE_RX_IDLE;
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ state_q <= STATE_RX_IDLE;
+else
+ state_q <= next_state_r;
+
+//-----------------------------------------------------------------
+// Response
+//-----------------------------------------------------------------
+reg tx_valid_r;
+reg [7:0] tx_pid_r;
+
+always @ *
+begin
+ tx_valid_r = 1'b0;
+ tx_pid_r = 8'b0;
+
+ case (state_q)
+ //-----------------------------------------
+ // IDLE
+ //-----------------------------------------
+ STATE_RX_IDLE :
+ begin
+ // Token received (OUT, IN, SETUP, PING)
+ if (token_valid_w)
+ begin
+ //-------------------------------
+ // IN transfer (device -> host)
+ //-------------------------------
+ if (token_pid_w == `PID_IN)
+ begin
+ // Stalled endpoint?
+ if (ep_stall_r)
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_STALL;
+ end
+ // Some data to TX?
+ else if (tx_ready_r)
+ begin
+ tx_valid_r = 1'b1;
+ // TODO: Handle MDATA for ISOs
+ tx_pid_r = ep_data_bit_r ? `PID_DATA1 : `PID_DATA0;
+ end
+ // No data to TX
+ else
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_NAK;
+ end
+ end
+ //-------------------------------
+ // PING transfer (device -> host)
+ //-------------------------------
+ else if (token_pid_w == `PID_PING)
+ begin
+ // Stalled endpoint?
+ if (ep_stall_r)
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_STALL;
+ end
+ // Data ready to RX
+ else if (rx_space_r)
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_ACK;
+ end
+ // No data to TX
+ else
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_NAK;
+ end
+ end
+ end
+ end
+
+ //-----------------------------------------
+ // RX_DATA_READY
+ //-----------------------------------------
+ STATE_RX_DATA_READY :
+ begin
+ // Receive complete
+ if (rx_data_complete_w)
+ begin
+ // No response on CRC16 error
+ if (rx_crc_err_o)
+ ;
+ // ISO endpoint, no response?
+ else if (ep_iso_r)
+ ;
+ // Send STALL?
+ else if (ep_stall_r)
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_STALL;
+ end
+ // DATAx bit mismatch
+ else if ( (token_pid_w == `PID_DATA0 && ep_data_bit_r) ||
+ (token_pid_w == `PID_DATA1 && !ep_data_bit_r) )
+ begin
+ // Ack transfer to resync
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_ACK;
+ end
+ // Send NAK
+ else if (!rx_space_q)
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_NAK;
+ end
+ // TODO: USB 2.0, no more buffer space, return NYET
+ else
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = `PID_ACK;
+ end
+ end
+ end
+
+ //-----------------------------------------
+ // TX_CHIRP
+ //-----------------------------------------
+ STATE_TX_CHIRP :
+ begin
+ tx_valid_r = 1'b1;
+ tx_pid_r = 8'b0;
+ end
+
+ default :
+ ;
+
+ endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ tx_valid_q <= 1'b0;
+else if (!tx_valid_q || tx_accept_w)
+ tx_valid_q <= tx_valid_r;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ tx_pid_q <= 8'b0;
+else if (!tx_valid_q || tx_accept_w)
+ tx_pid_q <= tx_pid_r;
+
+//-----------------------------------------------------------------
+// Receive enable
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_enable_q <= 1'b0;
+else if (usb_rst_w ||reg_chirp_en_i)
+ rx_enable_q <= 1'b0;
+else
+ rx_enable_q <= (state_q == STATE_RX_DATA);
+
+//-----------------------------------------------------------------
+// Receive SETUP: Pulse on SETUP packet receive
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_setup_q <= 1'b0;
+else if (usb_rst_w ||reg_chirp_en_i)
+ rx_setup_q <= 1'b0;
+else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
+ rx_setup_q <= 1'b1;
+else
+ rx_setup_q <= 1'b0;
+
+//-----------------------------------------------------------------
+// Set Address
+//-----------------------------------------------------------------
+reg addr_update_pending_q;
+
+wire ep0_tx_zlp_w = ep0_tx_data_valid_i && (ep0_tx_data_strb_i == 1'b0) &&
+ ep0_tx_data_last_i && ep0_tx_data_accept_o;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ addr_update_pending_q <= 1'b0;
+else if (ep0_tx_zlp_w || usb_rst_w)
+ addr_update_pending_q <= 1'b0;
+// TODO: Use write strobe
+else if (reg_dev_addr_i != current_addr_q)
+ addr_update_pending_q <= 1'b1;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ current_addr_q <= `USB_DEV_W'b0;
+else if (usb_rst_w)
+ current_addr_q <= `USB_DEV_W'b0;
+else if (ep0_tx_zlp_w && addr_update_pending_q)
+ current_addr_q <= reg_dev_addr_i;
+
+//-----------------------------------------------------------------
+// SETUP request tracking
+//-----------------------------------------------------------------
+reg ep0_dir_in_q;
+reg ep0_dir_out_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ ep0_dir_in_q <= 1'b0;
+else if (usb_rst_w ||reg_chirp_en_i)
+ ep0_dir_in_q <= 1'b0;
+else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
+ ep0_dir_in_q <= 1'b0;
+else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_IN) && (token_ep_w == 4'd0))
+ ep0_dir_in_q <= 1'b1;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ ep0_dir_out_q <= 1'b0;
+else if (usb_rst_w ||reg_chirp_en_i)
+ ep0_dir_out_q <= 1'b0;
+else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
+ ep0_dir_out_q <= 1'b0;
+else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_OUT) && (token_ep_w == 4'd0))
+ ep0_dir_out_q <= 1'b1;
+
+assign status_stage_w = ep0_dir_in_q && ep0_dir_out_q && (token_ep_w == 4'd0);
+
+//-----------------------------------------------------------------
+// Endpoint data bit toggle
+//-----------------------------------------------------------------
+reg new_data_bit_r;
+always @ *
+begin
+ new_data_bit_r = ep_data_bit_r;
+
+ case (state_q)
+ //-----------------------------------------
+ // RX_DATA_READY
+ //-----------------------------------------
+ STATE_RX_DATA_READY :
+ begin
+ // Receive complete
+ if (rx_data_complete_w)
+ begin
+ // No toggle on CRC16 error
+ if (rx_crc_err_o)
+ ;
+ // ISO endpoint, no response?
+ else if (ep_iso_r)
+ ; // TODO: HS handling
+ // STALL?
+ else if (ep_stall_r)
+ ;
+ // DATAx bit mismatch
+ else if ( (token_pid_w == `PID_DATA0 && ep_data_bit_r) ||
+ (token_pid_w == `PID_DATA1 && !ep_data_bit_r) )
+ ;
+ // NAKd
+ else if (!rx_space_q)
+ ;
+ // Data accepted - toggle data bit
+ else
+ new_data_bit_r = !ep_data_bit_r;
+ end
+ end
+ //-----------------------------------------
+ // RX_IDLE
+ //-----------------------------------------
+ STATE_RX_IDLE :
+ begin
+ // Token received (OUT, IN, SETUP, PING)
+ if (token_valid_w)
+ begin
+ // SETUP packets always start with DATA0
+ if (token_pid_w == `PID_SETUP)
+ new_data_bit_r = 1'b0;
+ end
+ // ACK received
+ else if (rx_handshake_w && token_pid_w == `PID_ACK)
+ begin
+ new_data_bit_r = !ep_data_bit_r;
+ end
+ end
+ default:
+ ;
+ endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ ep0_data_bit_q <= 1'b0;
+else if (usb_rst_w)
+ ep0_data_bit_q <= 1'b0;
+else if (token_ep_w == 4'd0)
+ ep0_data_bit_q <= new_data_bit_r;
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ ep1_data_bit_q <= 1'b0;
+else if (usb_rst_w)
+ ep1_data_bit_q <= 1'b0;
+else if (token_ep_w == 4'd1)
+ ep1_data_bit_q <= new_data_bit_r;
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ ep2_data_bit_q <= 1'b0;
+else if (usb_rst_w)
+ ep2_data_bit_q <= 1'b0;
+else if (token_ep_w == 4'd2)
+ ep2_data_bit_q <= new_data_bit_r;
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ ep3_data_bit_q <= 1'b0;
+else if (usb_rst_w)
+ ep3_data_bit_q <= 1'b0;
+else if (token_ep_w == 4'd3)
+ ep3_data_bit_q <= new_data_bit_r;
+
+//-----------------------------------------------------------------
+// Reset event
+//-----------------------------------------------------------------
+reg rst_event_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rst_event_q <= 1'b0;
+else if (usb_rst_w)
+ rst_event_q <= 1'b1;
+else if (reg_sts_rst_clr_i)
+ rst_event_q <= 1'b0;
+
+assign reg_sts_rst_o = rst_event_q;
+
+//-----------------------------------------------------------------
+// Interrupts
+//-----------------------------------------------------------------
+reg intr_q;
+
+reg cfg_int_rx_r;
+reg cfg_int_tx_r;
+
+always @ *
+begin
+ cfg_int_rx_r = 1'b0;
+ cfg_int_tx_r = 1'b0;
+
+ case (token_ep_w)
+ 4'd0:
+ begin
+ cfg_int_rx_r = ep0_cfg_int_rx_i;
+ cfg_int_tx_r = ep0_cfg_int_tx_i;
+ end
+ 4'd1:
+ begin
+ cfg_int_rx_r = ep1_cfg_int_rx_i;
+ cfg_int_tx_r = ep1_cfg_int_tx_i;
+ end
+ 4'd2:
+ begin
+ cfg_int_rx_r = ep2_cfg_int_rx_i;
+ cfg_int_tx_r = ep2_cfg_int_tx_i;
+ end
+ 4'd3:
+ begin
+ cfg_int_rx_r = ep3_cfg_int_rx_i;
+ cfg_int_tx_r = ep3_cfg_int_tx_i;
+ end
+ default:
+ ;
+ endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ intr_q <= 1'b0;
+// SOF
+else if (frame_valid_w && reg_int_en_sof_i)
+ intr_q <= 1'b1;
+// Reset event
+else if (!rst_event_q && usb_rst_w)
+ intr_q <= 1'b1;
+// Rx ready
+else if (state_q == STATE_RX_DATA_READY && rx_space_q && cfg_int_rx_r)
+ intr_q <= 1'b1;
+// Tx complete
+else if (state_q == STATE_TX_DATA_COMPLETE && cfg_int_tx_r)
+ intr_q <= 1'b1;
+else
+ intr_q <= 1'b0;
+
+assign intr_o = intr_q;
+
+//-------------------------------------------------------------------
+// Debug
+//-------------------------------------------------------------------
+`ifdef verilator
+/* verilator lint_off WIDTH */
+reg [79:0] dbg_state;
+
+always @ *
+begin
+ dbg_state = "-";
+
+ case (state_q)
+ STATE_RX_IDLE: dbg_state = "IDLE";
+ STATE_RX_DATA: dbg_state = "RX_DATA";
+ STATE_RX_DATA_READY: dbg_state = "RX_DATA_READY";
+ STATE_RX_DATA_IGNORE: dbg_state = "RX_IGNORE";
+ STATE_TX_DATA: dbg_state = "TX_DATA";
+ STATE_TX_DATA_COMPLETE: dbg_state = "TX_DATA_COMPLETE";
+ STATE_TX_HANDSHAKE: dbg_state = "TX_HANDSHAKE";
+ STATE_TX_CHIRP: dbg_state = "CHIRP";
+ endcase
+end
+
+reg [79:0] dbg_pid;
+reg [7:0] dbg_pid_r;
+always @ *
+begin
+ dbg_pid = "-";
+
+ if (tx_valid_q && tx_accept_w)
+ dbg_pid_r = tx_pid_q;
+ else if (token_valid_w || rx_handshake_w || rx_data_valid_w)
+ dbg_pid_r = token_pid_w;
+ else
+ dbg_pid_r = 8'b0;
+
+ case (dbg_pid_r)
+ // Token
+ `PID_OUT:
+ dbg_pid = "OUT";
+ `PID_IN:
+ dbg_pid = "IN";
+ `PID_SOF:
+ dbg_pid = "SOF";
+ `PID_SETUP:
+ dbg_pid = "SETUP";
+ `PID_PING:
+ dbg_pid = "PING";
+ // Data
+ `PID_DATA0:
+ dbg_pid = "DATA0";
+ `PID_DATA1:
+ dbg_pid = "DATA1";
+ `PID_DATA2:
+ dbg_pid = "DATA2";
+ `PID_MDATA:
+ dbg_pid = "MDATA";
+ // Handshake
+ `PID_ACK:
+ dbg_pid = "ACK";
+ `PID_NAK:
+ dbg_pid = "NAK";
+ `PID_STALL:
+ dbg_pid = "STALL";
+ `PID_NYET:
+ dbg_pid = "NYET";
+ // Special
+ `PID_PRE:
+ dbg_pid = "PRE/ERR";
+ `PID_SPLIT:
+ dbg_pid = "SPLIT";
+ default:
+ ;
+ endcase
+end
+/* verilator lint_on WIDTH */
+`endif
+
+
+endmodule
diff --git a/openlane/designs/usb_cdc_core/src/usbf_sie_rx.v b/openlane/designs/usb_cdc_core/src/usbf_sie_rx.v
new file mode 100644
index 0000000..4c367d8
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usbf_sie_rx.v
@@ -0,0 +1,467 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module usbf_sie_rx
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input enable_i
+ ,input [ 7:0] utmi_data_i
+ ,input utmi_rxvalid_i
+ ,input utmi_rxactive_i
+ ,input [ 6:0] current_addr_i
+
+ // Outputs
+ ,output [ 7:0] pid_o
+ ,output frame_valid_o
+ ,output [ 10:0] frame_number_o
+ ,output token_valid_o
+ ,output [ 6:0] token_addr_o
+ ,output [ 3:0] token_ep_o
+ ,output token_crc_err_o
+ ,output handshake_valid_o
+ ,output data_valid_o
+ ,output data_strb_o
+ ,output [ 7:0] data_o
+ ,output data_last_o
+ ,output data_crc_err_o
+ ,output data_complete_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+`include "usbf_defs.v"
+
+localparam STATE_W = 4;
+localparam STATE_RX_IDLE = 4'd0;
+localparam STATE_RX_TOKEN2 = 4'd1;
+localparam STATE_RX_TOKEN3 = 4'd2;
+localparam STATE_RX_TOKEN_COMPLETE = 4'd3;
+localparam STATE_RX_SOF2 = 4'd4;
+localparam STATE_RX_SOF3 = 4'd5;
+localparam STATE_RX_DATA = 4'd6;
+localparam STATE_RX_DATA_COMPLETE = 4'd7;
+localparam STATE_RX_IGNORED = 4'd8;
+reg [STATE_W-1:0] state_q;
+
+//-----------------------------------------------------------------
+// Wire / Regs
+//-----------------------------------------------------------------
+`define USB_FRAME_W 11
+reg [`USB_FRAME_W-1:0] frame_num_q;
+
+`define USB_DEV_W 7
+reg [`USB_DEV_W-1:0] token_dev_q;
+
+`define USB_EP_W 4
+reg [`USB_EP_W-1:0] token_ep_q;
+
+`define USB_PID_W 8
+reg [`USB_PID_W-1:0] token_pid_q;
+
+//-----------------------------------------------------------------
+// Data delay (to strip the CRC16 trailing bytes)
+//-----------------------------------------------------------------
+reg [31:0] data_buffer_q;
+reg [3:0] data_valid_q;
+reg [3:0] rx_active_q;
+
+wire shift_en_w = (utmi_rxvalid_i & utmi_rxactive_i) || !utmi_rxactive_i;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_buffer_q <= 32'b0;
+else if (shift_en_w)
+ data_buffer_q <= {utmi_data_i, data_buffer_q[31:8]};
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_valid_q <= 4'b0;
+else if (shift_en_w)
+ data_valid_q <= {(utmi_rxvalid_i & utmi_rxactive_i), data_valid_q[3:1]};
+else
+ data_valid_q <= {data_valid_q[3:1], 1'b0};
+
+reg [1:0] data_crc_q;
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_crc_q <= 2'b0;
+else if (shift_en_w)
+ data_crc_q <= {!utmi_rxactive_i, data_crc_q[1]};
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ rx_active_q <= 4'b0;
+else
+ rx_active_q <= {utmi_rxactive_i, rx_active_q[3:1]};
+
+wire [7:0] data_w = data_buffer_q[7:0];
+wire data_ready_w = data_valid_q[0];
+wire crc_byte_w = data_crc_q[0];
+wire rx_active_w = rx_active_q[0];
+
+wire address_match_w = (token_dev_q == current_addr_i);
+
+//-----------------------------------------------------------------
+// Next state
+//-----------------------------------------------------------------
+reg [STATE_W-1:0] next_state_r;
+
+always @ *
+begin
+ next_state_r = state_q;
+
+ case (state_q)
+
+ //-----------------------------------------
+ // IDLE
+ //-----------------------------------------
+ STATE_RX_IDLE :
+ begin
+ if (data_ready_w)
+ begin
+ // Decode PID
+ case (data_w)
+
+ `PID_OUT, `PID_IN, `PID_SETUP, `PID_PING:
+ next_state_r = STATE_RX_TOKEN2;
+
+ `PID_SOF:
+ next_state_r = STATE_RX_SOF2;
+
+ `PID_DATA0, `PID_DATA1, `PID_DATA2, `PID_MDATA:
+ begin
+ next_state_r = STATE_RX_DATA;
+ end
+
+ `PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
+ next_state_r = STATE_RX_IDLE;
+
+ default : // SPLIT / ERR
+ next_state_r = STATE_RX_IGNORED;
+ endcase
+ end
+ end
+
+ //-----------------------------------------
+ // RX_IGNORED: Unknown / unsupported
+ //-----------------------------------------
+ STATE_RX_IGNORED :
+ begin
+ // Wait until the end of the packet
+ if (!rx_active_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ //-----------------------------------------
+ // SOF (BYTE 2)
+ //-----------------------------------------
+ STATE_RX_SOF2 :
+ begin
+ if (data_ready_w)
+ next_state_r = STATE_RX_SOF3;
+ else if (!rx_active_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ //-----------------------------------------
+ // SOF (BYTE 3)
+ //-----------------------------------------
+ STATE_RX_SOF3 :
+ begin
+ if (data_ready_w || !rx_active_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ //-----------------------------------------
+ // TOKEN (IN/OUT/SETUP) (Address/Endpoint)
+ //-----------------------------------------
+ STATE_RX_TOKEN2 :
+ begin
+ if (data_ready_w)
+ next_state_r = STATE_RX_TOKEN3;
+ else if (!rx_active_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ //-----------------------------------------
+ // TOKEN (IN/OUT/SETUP) (Endpoint/CRC)
+ //-----------------------------------------
+ STATE_RX_TOKEN3 :
+ begin
+ if (data_ready_w)
+ next_state_r = STATE_RX_TOKEN_COMPLETE;
+ else if (!rx_active_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ //-----------------------------------------
+ // RX_TOKEN_COMPLETE
+ //-----------------------------------------
+ STATE_RX_TOKEN_COMPLETE :
+ begin
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ //-----------------------------------------
+ // RX_DATA
+ //-----------------------------------------
+ STATE_RX_DATA :
+ begin
+ // Receive complete
+ if (crc_byte_w)
+ next_state_r = STATE_RX_DATA_COMPLETE;
+ end
+
+ //-----------------------------------------
+ // RX_DATA_COMPLETE
+ //-----------------------------------------
+ STATE_RX_DATA_COMPLETE :
+ begin
+ if (!rx_active_w)
+ next_state_r = STATE_RX_IDLE;
+ end
+
+ default :
+ ;
+
+ endcase
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ state_q <= STATE_RX_IDLE;
+else if (!enable_i)
+ state_q <= STATE_RX_IDLE;
+else
+ state_q <= next_state_r;
+
+//-----------------------------------------------------------------
+// Handshake:
+//-----------------------------------------------------------------
+reg handshake_valid_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ handshake_valid_q <= 1'b0;
+else if (state_q == STATE_RX_IDLE && data_ready_w)
+begin
+ case (data_w)
+ `PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
+ handshake_valid_q <= address_match_w;
+ default :
+ handshake_valid_q <= 1'b0;
+ endcase
+end
+else
+ handshake_valid_q <= 1'b0;
+
+assign handshake_valid_o = handshake_valid_q;
+
+//-----------------------------------------------------------------
+// SOF: Frame number
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ frame_num_q <= `USB_FRAME_W'b0;
+else if (state_q == STATE_RX_SOF2 && data_ready_w)
+ frame_num_q <= {3'b0, data_w};
+else if (state_q == STATE_RX_SOF3 && data_ready_w)
+ frame_num_q <= {data_w[2:0], frame_num_q[7:0]};
+else if (!enable_i)
+ frame_num_q <= `USB_FRAME_W'b0;
+
+assign frame_number_o = frame_num_q;
+
+reg frame_valid_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ frame_valid_q <= 1'b0;
+else
+ frame_valid_q <= (state_q == STATE_RX_SOF3 && data_ready_w);
+
+assign frame_valid_o = frame_valid_q;
+
+//-----------------------------------------------------------------
+// Token: PID
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ token_pid_q <= `USB_PID_W'b0;
+else if (state_q == STATE_RX_IDLE && data_ready_w)
+ token_pid_q <= data_w;
+else if (!enable_i)
+ token_pid_q <= `USB_PID_W'b0;
+
+assign pid_o = token_pid_q;
+
+reg token_valid_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ token_valid_q <= 1'b0;
+else
+ token_valid_q <= (state_q == STATE_RX_TOKEN_COMPLETE) && address_match_w;
+
+assign token_valid_o = token_valid_q;
+
+//-----------------------------------------------------------------
+// Token: Device Address
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ token_dev_q <= `USB_DEV_W'b0;
+else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
+ token_dev_q <= data_w[6:0];
+else if (!enable_i)
+ token_dev_q <= `USB_DEV_W'b0;
+
+assign token_addr_o = token_dev_q;
+
+//-----------------------------------------------------------------
+// Token: Endpoint
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ token_ep_q <= `USB_EP_W'b0;
+else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
+ token_ep_q[0] <= data_w[7];
+else if (state_q == STATE_RX_TOKEN3 && data_ready_w)
+ token_ep_q[3:1] <= data_w[2:0];
+else if (!enable_i)
+ token_ep_q <= `USB_EP_W'b0;
+
+assign token_ep_o = token_ep_q;
+assign token_crc_err_o = 1'b0;
+
+wire [7:0] input_data_w = data_w;
+wire input_ready_w = state_q == STATE_RX_DATA && data_ready_w && !crc_byte_w;
+
+//-----------------------------------------------------------------
+// CRC16: Generate CRC16 on incoming data bytes
+//-----------------------------------------------------------------
+reg [15:0] crc_sum_q;
+wire [15:0] crc_out_w;
+reg crc_err_q;
+
+usbf_crc16
+u_crc16
+(
+ .crc_in_i(crc_sum_q),
+ .din_i(data_w),
+ .crc_out_o(crc_out_w)
+);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ crc_sum_q <= 16'hFFFF;
+else if (state_q == STATE_RX_IDLE)
+ crc_sum_q <= 16'hFFFF;
+else if (data_ready_w)
+ crc_sum_q <= crc_out_w;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ crc_err_q <= 1'b0;
+else if (state_q == STATE_RX_IDLE)
+ crc_err_q <= 1'b0;
+else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
+ crc_err_q <= (crc_sum_q != 16'hB001);
+
+assign data_crc_err_o = crc_err_q;
+
+reg data_complete_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_complete_q <= 1'b0;
+else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
+ data_complete_q <= 1'b1;
+else
+ data_complete_q <= 1'b0;
+
+assign data_complete_o = data_complete_q;
+
+reg data_zlp_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ data_zlp_q <= 1'b0;
+else if (state_q == STATE_RX_IDLE && next_state_r == STATE_RX_DATA)
+ data_zlp_q <= 1'b1;
+else if (input_ready_w)
+ data_zlp_q <= 1'b0;
+
+//-----------------------------------------------------------------
+// Data Output
+//-----------------------------------------------------------------
+reg valid_q;
+reg last_q;
+reg [7:0] data_q;
+reg mask_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ valid_q <= 1'b0;
+ data_q <= 8'b0;
+ mask_q <= 1'b0;
+ last_q <= 1'b0;
+end
+else
+begin
+ valid_q <= input_ready_w || ((state_q == STATE_RX_DATA) && crc_byte_w && data_zlp_q);
+ data_q <= input_data_w;
+ mask_q <= input_ready_w;
+ last_q <= (state_q == STATE_RX_DATA) && crc_byte_w;
+end
+
+// Data
+assign data_valid_o = valid_q;
+assign data_strb_o = mask_q;
+assign data_o = data_q;
+assign data_last_o = last_q | crc_byte_w;
+
+
+endmodule
diff --git a/openlane/designs/usb_cdc_core/src/usbf_sie_tx.v b/openlane/designs/usb_cdc_core/src/usbf_sie_tx.v
new file mode 100644
index 0000000..ded5d03
--- /dev/null
+++ b/openlane/designs/usb_cdc_core/src/usbf_sie_tx.v
@@ -0,0 +1,354 @@
+//-----------------------------------------------------------------
+// USB CDC Device
+// V0.1
+// Ultra-Embedded.com
+// Copyright 2014-2019
+//
+// Email: admin@ultra-embedded.com
+//
+// License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+// Boston, MA 02111-1307 USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Generated File
+//-----------------------------------------------------------------
+
+module usbf_sie_tx
+(
+ // Inputs
+ input clk_i
+ ,input rst_i
+ ,input enable_i
+ ,input chirp_i
+ ,input utmi_txready_i
+ ,input tx_valid_i
+ ,input [ 7:0] tx_pid_i
+ ,input data_valid_i
+ ,input data_strb_i
+ ,input [ 7:0] data_i
+ ,input data_last_i
+
+ // Outputs
+ ,output [ 7:0] utmi_data_o
+ ,output utmi_txvalid_o
+ ,output tx_accept_o
+ ,output data_accept_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+`include "usbf_defs.v"
+
+localparam STATE_W = 3;
+localparam STATE_TX_IDLE = 3'd0;
+localparam STATE_TX_PID = 3'd1;
+localparam STATE_TX_DATA = 3'd2;
+localparam STATE_TX_CRC1 = 3'd3;
+localparam STATE_TX_CRC2 = 3'd4;
+localparam STATE_TX_DONE = 3'd5;
+localparam STATE_TX_CHIRP = 3'd6;
+
+reg [STATE_W-1:0] state_q;
+reg [STATE_W-1:0] next_state_r;
+
+//-----------------------------------------------------------------
+// Wire / Regs
+//-----------------------------------------------------------------
+reg last_q;
+
+//-----------------------------------------------------------------
+// Request Type
+//-----------------------------------------------------------------
+reg data_pid_q;
+reg data_zlp_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ data_pid_q <= 1'b0;
+ data_zlp_q <= 1'b0;
+end
+else if (!enable_i)
+begin
+ data_pid_q <= 1'b0;
+ data_zlp_q <= 1'b0;
+end
+else if (tx_valid_i && tx_accept_o)
+begin
+ case (tx_pid_i)
+
+ `PID_MDATA, `PID_DATA2, `PID_DATA0, `PID_DATA1:
+ begin
+ data_pid_q <= 1'b1;
+ data_zlp_q <= data_valid_i && (data_strb_i == 1'b0) && data_last_i;
+ end
+
+ default :
+ begin
+ data_pid_q <= 1'b0;
+ data_zlp_q <= 1'b0;
+ end
+ endcase
+end
+else if (next_state_r == STATE_TX_CRC1)
+begin
+ data_pid_q <= 1'b0;
+ data_zlp_q <= 1'b0;
+end
+
+assign tx_accept_o = (state_q == STATE_TX_IDLE);
+
+//-----------------------------------------------------------------
+// Next state
+//-----------------------------------------------------------------
+always @ *
+begin
+ next_state_r = state_q;
+
+ //-----------------------------------------
+ // State Machine
+ //-----------------------------------------
+ case (state_q)
+
+ //-----------------------------------------
+ // IDLE
+ //-----------------------------------------
+ STATE_TX_IDLE :
+ begin
+ if (chirp_i)
+ next_state_r = STATE_TX_CHIRP;
+ else if (tx_valid_i)
+ next_state_r = STATE_TX_PID;
+ end
+
+ //-----------------------------------------
+ // TX_PID
+ //-----------------------------------------
+ STATE_TX_PID :
+ begin
+ // Data accepted
+ if (utmi_txready_i)
+ begin
+ if (data_zlp_q)
+ next_state_r = STATE_TX_CRC1;
+ else if (data_pid_q)
+ next_state_r = STATE_TX_DATA;
+ else
+ next_state_r = STATE_TX_DONE;
+ end
+ end
+
+ //-----------------------------------------
+ // TX_DATA
+ //-----------------------------------------
+ STATE_TX_DATA :
+ begin
+ // Data accepted
+ if (utmi_txready_i)
+ begin
+ // Generate CRC16 at end of packet
+ if (data_last_i)
+ next_state_r = STATE_TX_CRC1;
+ end
+ end
+
+ //-----------------------------------------
+ // TX_CRC1 (first byte)
+ //-----------------------------------------
+ STATE_TX_CRC1 :
+ begin
+ // Data sent?
+ if (utmi_txready_i)
+ next_state_r = STATE_TX_CRC2;
+ end
+
+ //-----------------------------------------
+ // TX_CRC (second byte)
+ //-----------------------------------------
+ STATE_TX_CRC2 :
+ begin
+ // Data sent?
+ if (utmi_txready_i)
+ next_state_r = STATE_TX_DONE;
+ end
+
+ //-----------------------------------------
+ // TX_DONE
+ //-----------------------------------------
+ STATE_TX_DONE :
+ begin
+ // Data sent?
+ if (!utmi_txvalid_o || utmi_txready_i)
+ next_state_r = STATE_TX_IDLE;
+ end
+
+ //-----------------------------------------
+ // TX_CHIRP
+ //-----------------------------------------
+ STATE_TX_CHIRP :
+ begin
+ if (!chirp_i)
+ next_state_r = STATE_TX_IDLE;
+ end
+
+ default :
+ ;
+
+ endcase
+
+ // USB reset but not chirping...
+ if (!enable_i && !chirp_i)
+ next_state_r = STATE_TX_IDLE;
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ state_q <= STATE_TX_IDLE;
+else
+ state_q <= next_state_r;
+
+//-----------------------------------------------------------------
+// Data Input
+//-----------------------------------------------------------------
+reg input_valid_r;
+reg [7:0] input_byte_r;
+reg input_last_r;
+always @ *
+begin
+ input_valid_r = data_strb_i & data_pid_q;
+ input_byte_r = data_i;
+ input_last_r = data_last_i;
+end
+
+reg data_accept_r;
+always @ *
+begin
+ if (state_q == STATE_TX_DATA)
+ data_accept_r = utmi_txready_i;
+ else if (state_q == STATE_TX_PID && data_zlp_q)
+ data_accept_r = utmi_txready_i;
+ else
+ data_accept_r = 1'b0;
+end
+
+assign data_accept_o = data_accept_r;
+
+//-----------------------------------------------------------------
+// CRC16: Generate CRC16 on outgoing data
+//-----------------------------------------------------------------
+reg [15:0] crc_sum_q;
+wire [15:0] crc_out_w;
+reg crc_err_q;
+
+usbf_crc16
+u_crc16
+(
+ .crc_in_i(crc_sum_q),
+ .din_i(utmi_data_o),
+ .crc_out_o(crc_out_w)
+);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+ crc_sum_q <= 16'hFFFF;
+else if (state_q == STATE_TX_IDLE)
+ crc_sum_q <= 16'hFFFF;
+else if (state_q == STATE_TX_DATA && utmi_txvalid_o && utmi_txready_i)
+ crc_sum_q <= crc_out_w;
+
+//-----------------------------------------------------------------
+// Output
+//-----------------------------------------------------------------
+reg valid_q;
+reg [7:0] data_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+ valid_q <= 1'b0;
+ data_q <= 8'b0;
+ last_q <= 1'b0;
+end
+else if (!enable_i)
+begin
+ valid_q <= 1'b0;
+ data_q <= 8'b0;
+ last_q <= 1'b0;
+end
+else if (tx_valid_i && tx_accept_o)
+begin
+ valid_q <= 1'b1;
+ data_q <= tx_pid_i;
+ last_q <= 1'b0;
+end
+else if (utmi_txready_i)
+begin
+ valid_q <= 1'b0;
+ data_q <= 8'b0;
+ last_q <= 1'b0;
+end
+
+reg utmi_txvalid_r;
+reg [7:0] utmi_data_r;
+
+always @ *
+begin
+ if (state_q == STATE_TX_CHIRP)
+ begin
+ utmi_txvalid_r = 1'b1;
+ utmi_data_r = 8'b0;
+ end
+ else if (state_q == STATE_TX_CRC1)
+ begin
+ utmi_txvalid_r = 1'b1;
+ utmi_data_r = crc_sum_q[7:0] ^ 8'hFF;
+ end
+ else if (state_q == STATE_TX_CRC2)
+ begin
+ utmi_txvalid_r = 1'b1;
+ utmi_data_r = crc_sum_q[15:8] ^ 8'hFF;
+ end
+ else if (state_q == STATE_TX_DATA)
+ begin
+ utmi_txvalid_r = data_valid_i;
+ utmi_data_r = data_i;
+ end
+ else
+ begin
+ utmi_txvalid_r = valid_q;
+ utmi_data_r = data_q;
+ end
+end
+
+assign utmi_txvalid_o = utmi_txvalid_r;
+assign utmi_data_o = utmi_data_r;
+
+
+endmodule
diff --git a/openlane/designs/wbqspiflash/config.tcl b/openlane/designs/wbqspiflash/config.tcl
new file mode 100755
index 0000000..570ea67
--- /dev/null
+++ b/openlane/designs/wbqspiflash/config.tcl
@@ -0,0 +1,17 @@
+
+# Design
+
+# User config
+set ::env(DESIGN_NAME) wbqspiflash
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+# Fill this
+set ::env(CLOCK_PORT) "i_clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..dc1e528
--- /dev/null
+++ b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20"
+set ::env(SYNTH_STRATEGY) "DELAY 0"
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(FP_CORE_UTIL) 40
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..6810697
--- /dev/null
+++ b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "18.86"
+set ::env(FP_CORE_UTIL) 40
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..f3f9c89
--- /dev/null
+++ b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "18.86"
+set ::env(FP_CORE_UTIL) 30
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..18f6ea0
--- /dev/null
+++ b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "18.86"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..852d3c8
--- /dev/null
+++ b/openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,15 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "18.86"
+set ::env(FP_CORE_UTIL) 40
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+# Regression
+set ::env(FP_CORE_UTIL) "30"
+
+# Extra
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+
+# Suggested Clock Period:
+set ::env(CLOCK_PERIOD) "18.86"
diff --git a/openlane/designs/wbqspiflash/src/wbqspiflash.v b/openlane/designs/wbqspiflash/src/wbqspiflash.v
new file mode 100644
index 0000000..57dc89c
--- /dev/null
+++ b/openlane/designs/wbqspiflash/src/wbqspiflash.v
@@ -0,0 +1,1768 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: wbspiflash.v
+//
+// Project: A Set of Wishbone Controlled SPI Flash Controllers
+//
+// Purpose: Access a Quad SPI flash via a WISHBONE interface. This
+// includes both read and write (and erase) commands to the SPI
+// flash. All read/write commands are accomplished using the
+// high speed (4-bit) interface. Further, the device will be
+// left/kept in the 4-bit read interface mode between accesses,
+// for a minimum read latency.
+//
+// Wishbone Registers (See spec sheet for more detail):
+// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
+// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
+// { last_erased_sector, 14'h00 } if (WIP)
+// else { current_sector_being_erased, 14'h00 }
+// current if write in progress, last if written
+// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
+// 1: Configuration register
+// 2: Status register (R/w)
+// 3: Read ID (read only)
+// (19 bits): Data (R/w, but expect writes to take a while)
+//
+// This core has been deprecated. All of my new projects are using one of
+// my universal flash controllers now: qflexpress, dualflexpress, or spixpress.
+// These can be found in my https://github.com/ZipCPU/qspiflash repository.
+//
+// Creator: Dan Gisselquist, Ph.D.
+// Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2015-2019, Gisselquist Technology, LLC
+//
+// This file is part of the set of Wishbone controlled SPI flash controllers
+// project
+//
+// The Wishbone SPI flash controller project is free software (firmware):
+// you can redistribute it and/or modify it under the terms of the GNU Lesser
+// General Public License as published by the Free Software Foundation, either
+// version 3 of the License, or (at your option) any later version.
+//
+// The Wishbone SPI flash controller project is distributed in the hope
+// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this program. (It's in the $(ROOT)/doc directory. Run make
+// with no target there if the PDF file isn't present.) If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+//
+// License: LGPL, v3, as defined and found on www.gnu.org,
+// http://www.gnu.org/licenses/lgpl.html
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+//
+`default_nettype none
+//
+`define WBQSPI_RESET 5'd0
+`define WBQSPI_RESET_QUADMODE 5'd1
+`define WBQSPI_IDLE 5'd2
+`define WBQSPI_RDIDLE 5'd3 // Idle, but in fast read mode
+`define WBQSPI_WBDECODE 5'd4
+`define WBQSPI_RD_DUMMY 5'd5
+`define WBQSPI_QRD_ADDRESS 5'd6
+`define WBQSPI_QRD_DUMMY 5'd7
+`define WBQSPI_READ_CMD 5'd8
+`define WBQSPI_READ_DATA 5'd9
+`define WBQSPI_WAIT_TIL_RDIDLE 5'd10
+`define WBQSPI_READ_ID_CMD 5'd11
+`define WBQSPI_READ_ID 5'd12
+`define WBQSPI_READ_STATUS 5'd13
+`define WBQSPI_READ_CONFIG 5'd14
+`define WBQSPI_WAIT_TIL_IDLE 5'd15
+//
+//
+`define WBQSPI_WAIT_WIP_CLEAR 5'd16
+`define WBQSPI_CHECK_WIP_CLEAR 5'd17
+`define WBQSPI_CHECK_WIP_DONE 5'd18
+`define WBQSPI_WEN 5'd19
+`define WBQSPI_PP 5'd20 // Program page
+`define WBQSPI_QPP 5'd21 // Program page, 4 bit mode
+`define WBQSPI_WR_DATA 5'd22
+`define WBQSPI_WR_BUS_CYCLE 5'd23
+`define WBQSPI_WRITE_STATUS 5'd24
+`define WBQSPI_WRITE_CONFIG 5'd25
+`define WBQSPI_ERASE_WEN 5'd26
+`define WBQSPI_ERASE_CMD 5'd27
+`define WBQSPI_ERASE_BLOCK 5'd28
+`define WBQSPI_CLEAR_STATUS 5'd29
+`define WBQSPI_IDLE_CHECK_WIP 5'd30
+//
+module wbqspiflash(i_clk,
+ // Internal wishbone connections
+ i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
+ i_wb_addr, i_wb_data,
+ // Wishbone return values
+ o_wb_ack, o_wb_stall, o_wb_data,
+ // Quad Spi connections to the external device
+ o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
+ o_interrupt);
+ parameter ADDRESS_WIDTH=22;
+ parameter [0:0] OPT_READ_ONLY = 1'b0;
+ localparam AW = ADDRESS_WIDTH-2;
+ input wire i_clk;
+ // Wishbone, inputs first
+ input wire i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
+ input wire [(AW-1):0] i_wb_addr;
+ input wire [31:0] i_wb_data;
+ // then outputs
+ output reg o_wb_ack;
+ output reg o_wb_stall;
+ output reg [31:0] o_wb_data;
+ // Quad SPI control wires
+ output wire o_qspi_sck, o_qspi_cs_n;
+ output wire [1:0] o_qspi_mod;
+ output wire [3:0] o_qspi_dat;
+ input wire [3:0] i_qspi_dat;
+ // Interrupt line
+ output reg o_interrupt;
+ // output wire [31:0] o_debug;
+
+ reg spi_wr, spi_hold, spi_spd, spi_dir;
+ reg [31:0] spi_in;
+ reg [1:0] spi_len;
+ wire [31:0] spi_out;
+ wire spi_valid, spi_busy;
+ wire w_qspi_sck, w_qspi_cs_n;
+ wire [3:0] w_qspi_dat;
+ wire [1:0] w_qspi_mod;
+ // wire [22:0] spi_dbg;
+ llqspi lldriver(i_clk,
+ spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
+ spi_out, spi_valid, spi_busy,
+ w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
+ i_qspi_dat);
+
+ // Erase status tracking
+ reg write_in_progress, write_protect;
+ reg [(ADDRESS_WIDTH-17):0] erased_sector;
+ reg dirty_sector;
+ initial begin
+ write_in_progress = 1'b0;
+ erased_sector = 0;
+ dirty_sector = 1'b1;
+ write_protect = 1'b1;
+ end
+
+ wire [23:0] w_wb_addr;
+ generate
+ if (ADDRESS_WIDTH>=24)
+ assign w_wb_addr = { i_wb_addr[21:0], 2'b00 };
+ else
+ assign w_wb_addr = { {(24-ADDRESS_WIDTH){1'b0}}, i_wb_addr, 2'b00 };
+ endgenerate
+
+ // Repeat for spif_addr
+ reg [(ADDRESS_WIDTH-3):0] spif_addr;
+ wire [23:0] w_spif_addr;
+ generate
+ if (ADDRESS_WIDTH>=24)
+ assign w_spif_addr = { spif_addr[21:0], 2'b00 };
+ else
+ assign w_spif_addr = { {(24-ADDRESS_WIDTH){1'b0}}, spif_addr, 2'b00 };
+ endgenerate
+
+ reg [7:0] last_status;
+ reg [9:0] reset_counter;
+ reg quad_mode_enabled;
+ reg spif_cmd, spif_override;
+ reg [31:0] spif_data;
+ reg [4:0] state;
+ reg spif_ctrl, spif_req;
+ reg alt_cmd, alt_ctrl;
+ wire [(ADDRESS_WIDTH-17):0] spif_sector;
+ assign spif_sector = spif_addr[(AW-1):14];
+
+ // assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
+
+ initial state = `WBQSPI_RESET;
+ initial o_wb_ack = 1'b0;
+ initial o_wb_stall = 1'b1;
+ initial spi_wr = 1'b0;
+ initial spi_len = 2'b00;
+ initial quad_mode_enabled = 1'b0;
+ initial o_interrupt = 1'b0;
+ initial spif_override = 1'b1;
+ initial spif_ctrl = 1'b0;
+ always @(posedge i_clk)
+ begin
+ spif_override <= 1'b0;
+ alt_cmd <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
+ alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
+ if (state == `WBQSPI_RESET)
+ begin
+ // From a reset, we should
+ // Enable the Quad I/O mode
+ // Disable the Write protection bits in the status register
+ // Chip should already be up and running, so we can start
+ // immediately ....
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0;
+ last_status <= 8'h00;
+ state <= `WBQSPI_RESET_QUADMODE;
+ spif_req <= 1'b0;
+ spif_override <= 1'b1;
+ last_status <= 8'h00; //
+ reset_counter <= 10'h3fc; //
+ // This guarantees that we aren't starting in quad
+ // I/O mode, where the FPGA configuration scripts may
+ // have left us.
+ end else if (state == `WBQSPI_RESET_QUADMODE)
+ begin
+ // Okay, so here's the problem: we don't know whether or not
+ // the Xilinx loader started us up in Quad Read I/O idle mode.
+ // So, thus we need to toggle the clock and CS_n, with fewer
+ // clocks than are necessary to transmit a word.
+ //
+ // Not ready to handle the bus yet, so stall any requests
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ // Do something ...
+ if (reset_counter == 10'h00)
+ begin
+ spif_override <= 1'b0;
+ state <= `WBQSPI_IDLE;
+
+ // Find out if we can use Quad I/O mode ...
+ state <= `WBQSPI_READ_CONFIG;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01;
+ spi_in <= { 8'h35, 24'h00};
+
+ end else begin
+ reset_counter <= reset_counter - 10'h1;
+ spif_override <= 1'b1;
+ end
+ end else if (state == `WBQSPI_IDLE)
+ begin
+ o_interrupt <= 1'b0;
+ o_wb_stall <= 1'b0;
+ o_wb_ack <= 1'b0;
+ spif_cmd <= i_wb_we;
+ spif_addr <= i_wb_addr;
+ spif_data <= i_wb_data;
+ spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
+ spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
+ spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
+ spi_hold <= 1'b0;
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
+ // Data register access
+ if (i_wb_data_stb)
+ begin
+
+ if ((OPT_READ_ONLY)&&(i_wb_we)) // Write request
+ begin
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+ end else if (i_wb_we) // Request to write a page
+ begin
+ if((!write_protect)&&(!write_in_progress))
+ begin // 00
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WEN;
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end else if (write_protect)
+ begin // whether or not write-in_progress ...
+ // Do nothing on a write protect
+ // violation
+ //
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+ end else begin // write is in progress, wait
+ // for it to complete
+ state <= `WBQSPI_WAIT_WIP_CLEAR;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ end else if (!write_in_progress)
+ begin // Read access, normal mode(s)
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ spi_wr <= 1'b1; // Write cmd to device
+ if (quad_mode_enabled)
+ begin
+ spi_in <= { 8'heb, w_wb_addr };
+ state <= `WBQSPI_QRD_ADDRESS;
+ spi_len <= 2'b00; // single byte, cmd only
+ end else begin
+ spi_in <= { 8'h0b, w_wb_addr };
+ state <= `WBQSPI_RD_DUMMY;
+ spi_len <= 2'b11; // cmd+addr,32bits
+ end
+ end else if (!OPT_READ_ONLY) begin
+ // A write is in progress ... need to stall
+ // the bus until the write is complete.
+ state <= `WBQSPI_WAIT_WIP_CLEAR;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ end else if ((OPT_READ_ONLY)&&(i_wb_ctrl_stb)&&(i_wb_we))
+ begin
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+ end else if ((i_wb_ctrl_stb)&&(i_wb_we))
+ begin
+ o_wb_stall <= 1'b1;
+ case(i_wb_addr[1:0])
+ 2'b00: begin // Erase command register
+ write_protect <= !i_wb_data[28];
+ o_wb_stall <= 1'b0;
+
+ if((i_wb_data[31])&&(!write_in_progress))
+ begin
+ // Command an erase--ack it immediately
+
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+
+ if ((i_wb_data[31])&&(!write_protect))
+ begin
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00;
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_ERASE_CMD;
+ o_wb_stall <= 1'b1;
+ end
+ end else if (i_wb_data[31])
+ begin
+ state <= `WBQSPI_WAIT_WIP_CLEAR;
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b1;
+ end else begin
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+ end end
+ 2'b01: begin
+ // Write the configuration register
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b1;
+
+ // Need to send a write enable command first
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WRITE_CONFIG;
+ end
+ 2'b10: begin
+ // Write the status register
+ o_wb_ack <= 1'b1; // Ack immediately
+ o_wb_stall <= 1'b1; // Stall other cmds
+ // Need to send a write enable command first
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WRITE_STATUS;
+ end
+ 2'b11: begin // Write the ID register??? makes no sense
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+ end
+ endcase
+ end else if (i_wb_ctrl_stb) // &&(!i_wb_we))
+ begin
+ case(i_wb_addr[1:0])
+ 2'b00: begin // Read local register
+ if (write_in_progress) // Read status
+ begin// register, is write still in progress?
+ state <= `WBQSPI_READ_STATUS;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01;// 8 bits out, 8 bits in
+ spi_in <= { 8'h05, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end else begin // Return w/o talking to device
+ o_wb_ack <= 1'b1;
+ o_wb_stall <= 1'b0;
+ o_wb_data <= { write_in_progress,
+ dirty_sector, spi_busy,
+ ~write_protect,
+ quad_mode_enabled,
+ {(29-ADDRESS_WIDTH){1'b0}},
+ erased_sector, 14'h000 };
+ end end
+ 2'b01: begin // Read configuration register
+ state <= `WBQSPI_READ_CONFIG;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01;
+ spi_in <= { 8'h35, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ 2'b10: begin // Read status register
+ state <= `WBQSPI_READ_STATUS;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01; // 8 bits out, 8 bits in
+ spi_in <= { 8'h05, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ 2'b11: begin // Read ID register
+ state <= `WBQSPI_READ_ID_CMD;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00;
+ spi_in <= { 8'h9f, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ endcase
+ end else if ((!OPT_READ_ONLY)&&(!i_wb_cyc)&&(write_in_progress))
+ begin
+ state <= `WBQSPI_IDLE_CHECK_WIP;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01; // 8 bits out, 8 bits in
+ spi_in <= { 8'h05, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ end else if (state == `WBQSPI_RDIDLE)
+ begin
+ spi_wr <= 1'b0;
+ o_wb_stall <= 1'b0;
+ o_wb_ack <= 1'b0;
+ spif_cmd <= i_wb_we;
+ spif_addr <= i_wb_addr;
+ spif_data <= i_wb_data;
+ spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
+ spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
+ spi_hold <= 1'b0;
+ spi_spd<= 1'b1;
+ spi_dir <= 1'b0; // Write (for now)
+ if ((i_wb_data_stb)&&(!i_wb_we))
+ begin // Continue our read ... send the new address / mode
+ o_wb_stall <= 1'b1;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b10; // Write address, but not mode byte
+ spi_in <= { w_wb_addr, 8'ha0 };
+ state <= `WBQSPI_QRD_DUMMY;
+ end else if((i_wb_ctrl_stb)&&(!i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
+ begin
+ // A local read that doesn't touch the device, so leave
+ // the device in its current state
+ o_wb_stall <= 1'b0;
+ o_wb_ack <= 1'b1;
+ o_wb_data <= { write_in_progress,
+ dirty_sector, spi_busy,
+ ~write_protect,
+ quad_mode_enabled,
+ {(29-ADDRESS_WIDTH){1'b0}},
+ erased_sector, 14'h000 };
+ end else if(((i_wb_ctrl_stb)||(i_wb_data_stb)))
+ begin // Need to release the device from quad mode for all else
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b11;
+ spi_in <= 32'h00;
+ state <= `WBQSPI_WBDECODE;
+ end
+ end else if (state == `WBQSPI_WBDECODE)
+ begin
+ // We were in quad SPI read mode, and had to get out.
+ // Now we've got a command (not data read) to read and
+ // execute. Accomplish what we would've done while in the
+ // IDLE state here, save only that we don't have to worry
+ // about data reads, and we need to operate on a stored
+ // version of the bus command
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
+ spi_hold <= 1'b0;
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // only in full idle ...
+ begin
+ // Data register access
+ if (!spif_ctrl)
+ begin
+ if ((OPT_READ_ONLY)&&(spif_cmd)) // Request to write a page
+ begin
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ state <= `WBQSPI_IDLE;
+ end else if (spif_cmd)
+ begin
+ if((!write_protect)&&(!write_in_progress))
+ begin // 00
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WEN;
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end else if (write_protect)
+ begin // whether or not write-in_progress ...
+ // Do nothing on a write protect
+ // violation
+ //
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ state <= `WBQSPI_IDLE;
+ end else begin // write is in progress, wait
+ // for it to complete
+ state <= `WBQSPI_WAIT_WIP_CLEAR;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ // end else if (!write_in_progress) // always true
+ // but ... we wouldn't get here on a normal read access
+ end else begin
+ // Something's wrong, we should never
+ // get here
+ // Attempt to go to idle to recover
+ state <= `WBQSPI_IDLE;
+ end
+ end else if ((OPT_READ_ONLY)&&(spif_ctrl)&&(spif_cmd))
+ begin
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ state <= `WBQSPI_IDLE;
+ end else if ((spif_ctrl)&&(spif_cmd)) begin
+ o_wb_stall <= 1'b1;
+ case(spif_addr[1:0])
+ 2'b00: begin // Erase command register
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ state <= `WBQSPI_IDLE;
+ write_protect <= ~spif_data[28];
+ // Are we commanding an erase?
+ // We're in read mode, writes cannot
+ // be in progress, so ...
+ if (spif_data[31]) // Command an erase
+ begin
+ // Since we're not going back
+ // to IDLE, we must stall the
+ // bus here
+ o_wb_stall <= 1'b1;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00;
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_ERASE_CMD;
+ end end
+ 2'b01: begin
+ // Write the configuration register
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b1;
+
+ // Need to send a write enable command first
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WRITE_CONFIG;
+ end
+ 2'b10: begin
+ // Write the status register
+ o_wb_ack <= spif_req; // Ack immediately
+ o_wb_stall <= 1'b1; // Stall other cmds
+ // Need to send a write enable command first
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WRITE_STATUS;
+ end
+ 2'b11: begin // Write the ID register??? makes no sense
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ state <= `WBQSPI_IDLE;
+ end
+ endcase
+ end else begin // on (!spif_we)
+ case(spif_addr[1:0])
+ 2'b00: begin // Read local register
+ // Nonsense case--would've done this
+ // already
+ state <= `WBQSPI_IDLE;
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ end
+ 2'b01: begin // Read configuration register
+ state <= `WBQSPI_READ_CONFIG;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01;
+ spi_in <= { 8'h35, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ 2'b10: begin // Read status register
+ state <= `WBQSPI_READ_STATUS;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01; // 8 bits out, 8 bits in
+ spi_in <= { 8'h05, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ 2'b11: begin // Read ID register
+ state <= `WBQSPI_READ_ID_CMD;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00;
+ spi_in <= { 8'h9f, 24'h00};
+
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ endcase
+ end
+ end
+//
+//
+// READ DATA section: for both data and commands
+//
+ end else if (state == `WBQSPI_RD_DUMMY)
+ begin
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ spi_wr <= 1'b1; // Non-stop
+ // Need to read one byte of dummy data,
+ // just to consume 8 clocks
+ spi_in <= { 8'h00, 24'h00 };
+ spi_len <= 2'b00; // Read 8 bits
+ spi_spd <= 1'b0;
+ spi_hold <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+
+ if ((!spi_busy)&&(!o_qspi_cs_n))
+ // Our command was accepted
+ state <= `WBQSPI_READ_CMD;
+ end else if (state == `WBQSPI_QRD_ADDRESS)
+ begin
+ // We come in here immediately upon issuing a QRD read
+ // command (8-bits), but we have to pause to give the
+ // address (24-bits) and mode (8-bits) in quad speed.
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ spi_wr <= 1'b1; // Non-stop
+ spi_in <= { w_spif_addr, 8'ha0 };
+ spi_len <= 2'b10; // Write address, not mode byte
+ spi_spd <= 1'b1;
+ spi_dir <= 1'b0; // Still writing
+ spi_hold <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+
+ if ((!spi_busy)&&(spi_spd))
+ // Our command was accepted
+ state <= `WBQSPI_QRD_DUMMY;
+ end else if (state == `WBQSPI_QRD_DUMMY)
+ begin
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ spi_wr <= 1'b1; // Non-stop
+ spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
+ spi_len <= 2'b10; // Write 24 bits
+ spi_spd <= 1'b1;
+ spi_dir <= 1'b0; // Still writing
+ spi_hold <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+
+ if ((!spi_busy)&&(spi_in[31:28] == 4'ha))
+ // Our command was accepted
+ state <= `WBQSPI_READ_CMD;
+ end else if (state == `WBQSPI_READ_CMD)
+ begin // Issue our first command to read 32 bits.
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ spi_wr <= 1'b1;
+ spi_in <= { 8'hff, 24'h00 }; // Empty
+ spi_len <= 2'b11; // Read 32 bits
+ spi_dir <= 1'b1; // Now reading
+ spi_hold <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if ((spi_valid)&&(spi_len == 2'b11))
+ state <= `WBQSPI_READ_DATA;
+ end else if (state == `WBQSPI_READ_DATA)
+ begin
+ // Pipelined read support
+ spi_wr <=((i_wb_data_stb)&&(!i_wb_we)&&(i_wb_addr== (spif_addr+1)))&&(spif_req);
+ spi_in <= 32'h00;
+ spi_len <= 2'b11;
+ // Don't adjust the speed here, it was set in the setup
+ spi_dir <= 1'b1; // Now we get to read
+ // Don't let the device go to idle until the bus cycle ends.
+ // This actually prevents a *really* nasty race condition,
+ // where the strobe comes in after the lower level device
+ // has decided to stop waiting. The write is then issued,
+ // but no one is listening. By leaving the device open,
+ // the device is kept in a state where a valid strobe
+ // here will be useful. Of course, we don't accept
+ // all commands, just reads. Further, the strobe needs
+ // to be high for two clocks cycles without changing
+ // anything on the bus--one for us to notice it and pull
+ // our head out of the sand, and a second for whoever
+ // owns the bus to realize their command went through.
+ spi_hold <= 1'b1;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if ((spi_valid)&&(!spi_in[31]))
+ begin // Single pulse acknowledge and write data out
+ o_wb_ack <= spif_req;
+ o_wb_stall <= (!spi_wr);
+ // adjust endian-ness to match the PC
+ o_wb_data <= spi_out;
+ state <= (spi_wr)?`WBQSPI_READ_DATA
+ : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
+ spif_req <= spi_wr;
+ spi_hold <= (!spi_wr);
+ if (spi_wr)
+ spif_addr <= i_wb_addr;
+ end else if ((!spif_req)||(!i_wb_cyc))
+ begin // FAIL SAFE: If the bus cycle ends, forget why we're
+ // here, just go back to idle
+ state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
+ spi_hold <= 1'b0;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end else begin
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ end
+ end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
+ begin // Wait 'til idle, but then go to fast read idle instead of full
+ spi_wr <= 1'b0; // idle
+ spi_hold <= 1'b0;
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spif_req <= 1'b0;
+ if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Wait for a full
+ begin // clearing of the SPI port before moving on
+ state <= `WBQSPI_RDIDLE;
+ o_wb_stall <= 1'b0;
+ o_wb_ack <= 1'b0;// Shouldn't be acking anything here
+ end
+ end else if (state == `WBQSPI_READ_ID_CMD)
+ begin // We came into here immediately after issuing a 0x9f command
+ // Now we need to read 32 bits of data. Result should be
+ // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
+ // by the number of extended bytes available 8'h4d).
+ o_wb_ack <= 1'b0;
+ o_wb_stall<= 1'b1;
+
+ spi_wr <= 1'b1; // No data to send, but need four bytes, since
+ spi_len <= 2'b11; // 32 bits of data are ... useful
+ spi_in <= 32'h00; // Irrelevant
+ spi_spd <= 1'b0; // Slow speed
+ spi_dir <= 1'b1; // Reading
+ spi_hold <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+ if ((!spi_busy)&&(!o_qspi_cs_n)&&(spi_len == 2'b11))
+ // Our command was accepted, now go read the result
+ state <= `WBQSPI_READ_ID;
+ end else if (state == `WBQSPI_READ_ID)
+ begin
+ o_wb_ack <= 1'b0; // Assuming we're still waiting
+ o_wb_stall <= 1'b1;
+
+ spi_wr <= 1'b0; // No more writes, we've already written the cmd
+ spi_hold <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+
+ // Here, we just wait until the result comes back
+ // The problem is, the result may be the previous result.
+ // So we use spi_len as an indicator
+ spi_len <= 2'b00;
+ if((spi_valid)&&(spi_len==2'b00))
+ begin // Put the results out as soon as possible
+ o_wb_data <= spi_out[31:0];
+ o_wb_ack <= spif_req;
+ spif_req <= 1'b0;
+ end else if ((!spi_busy)&&(o_qspi_cs_n))
+ begin
+ state <= `WBQSPI_IDLE;
+ o_wb_stall <= 1'b0;
+ end
+ end else if (state == `WBQSPI_READ_STATUS)
+ begin // We enter after the command has been given, for now just
+ // read and return
+ spi_wr <= 1'b0;
+ o_wb_ack <= 1'b0;
+ spi_hold <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+ if (spi_valid)
+ begin
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b1;
+ spif_req <= 1'b0;
+ last_status <= spi_out[7:0];
+ write_in_progress <= spi_out[0];
+ if (spif_addr[1:0] == 2'b00) // Local read, checking
+ begin // status, 'cause we're writing
+ o_wb_data <= { spi_out[0],
+ dirty_sector, spi_busy,
+ ~write_protect,
+ quad_mode_enabled,
+ {(29-ADDRESS_WIDTH){1'b0}},
+ erased_sector, 14'h000 };
+ end else begin
+ o_wb_data <= { 24'h00, spi_out[7:0] };
+ end
+ end
+
+ if ((!spi_busy)&&(!spi_wr))
+ state <= `WBQSPI_IDLE;
+ end else if (state == `WBQSPI_READ_CONFIG)
+ begin // We enter after the command has been given, for now just
+ // read and return
+ spi_wr <= 1'b0;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ spi_hold <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+
+ if (spi_valid)
+ begin
+ o_wb_data <= { 24'h00, spi_out[7:0] };
+ quad_mode_enabled <= spi_out[1];
+ end
+
+ if ((!spi_busy)&&(!spi_wr))
+ begin
+ state <= `WBQSPI_IDLE;
+ o_wb_ack <= spif_req;
+ o_wb_stall <= 1'b0;
+ spif_req <= 1'b0;
+ end
+
+//
+//
+// Write/erase data section
+//
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WAIT_WIP_CLEAR))
+ begin
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spi_wr <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if (!spi_busy)
+ begin
+ spi_wr <= 1'b1;
+ spi_in <= { 8'h05, 24'h0000 };
+ spi_hold <= 1'b1;
+ spi_len <= 2'b01; // 16 bits write, so we can read 8
+ state <= `WBQSPI_CHECK_WIP_CLEAR;
+ spi_spd <= 1'b0; // Slow speed
+ spi_dir <= 1'b0;
+ end
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CHECK_WIP_CLEAR))
+ begin
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ // Repeat as often as necessary until we are clear
+ spi_wr <= 1'b1;
+ spi_in <= 32'h0000; // Values here are actually irrelevant
+ spi_hold <= 1'b1;
+ spi_len <= 2'b00; // One byte at a time
+ spi_spd <= 1'b0; // Slow speed
+ spi_dir <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if ((spi_valid)&&(!spi_out[0]))
+ begin
+ state <= `WBQSPI_CHECK_WIP_DONE;
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+ write_in_progress <= 1'b0;
+ last_status <= spi_out[7:0];
+ end
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CHECK_WIP_DONE))
+ begin
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ // Let's let the SPI port come back to a full idle,
+ // and the chip select line go low before continuing
+ spi_wr <= 1'b0;
+ spi_len <= 2'b00;
+ spi_hold <= 1'b0;
+ spi_spd <= 1'b0; // Slow speed
+ spi_dir <= 1'b0;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if ((o_qspi_cs_n)&&(!spi_busy)) // Chip select line is high, we can continue
+ begin
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+
+ casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
+ 4'b00??: begin // Read data from ... somewhere
+ spi_wr <= 1'b1; // Write cmd to device
+ if (quad_mode_enabled)
+ begin
+ spi_in <= { 8'heb, w_spif_addr };
+ state <= `WBQSPI_QRD_ADDRESS;
+ // spi_len <= 2'b00; // single byte, cmd only
+ end else begin
+ spi_in <= { 8'h0b, w_spif_addr };
+ state <= `WBQSPI_RD_DUMMY;
+ spi_len <= 2'b11; // Send cmd and addr
+ end end
+ 4'b10??: begin // Write data to ... anywhere
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00; // 8 bits
+ // Send a write enable command
+ spi_in <= { 8'h06, 24'h00 };
+ state <= `WBQSPI_WEN;
+ end
+ 4'b0110: begin // Read status register
+ state <= `WBQSPI_READ_STATUS;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b01; // 8 bits out, 8 bits in
+ spi_in <= { 8'h05, 24'h00};
+ end
+ 4'b0111: begin
+ state <= `WBQSPI_READ_ID_CMD;
+ spi_wr <= 1'b1;
+ spi_len <= 2'b00;
+ spi_in <= { 8'h9f, 24'h00};
+ end
+ default: begin //
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= spif_req;
+ state <= `WBQSPI_WAIT_TIL_IDLE;
+ end
+ endcase
+ // spif_cmd <= i_wb_we;
+ // spif_addr <= i_wb_addr;
+ // spif_data <= i_wb_data;
+ // spif_ctrl <= (i_wb_ctrl_stb)&&(!i_wb_data_stb);
+ // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
+ end
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WEN))
+ begin // We came here after issuing a write enable command
+ spi_wr <= 1'b0;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Let's come to a full stop
+ state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
+ // state <= `WBQSPI_PP;
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_PP))
+ begin // We come here under a full stop / full port idle mode
+ // Issue our command immediately
+ spi_wr <= 1'b1;
+ spi_in <= { 8'h02, w_spif_addr };
+ spi_len <= 2'b11;
+ spi_hold <= 1'b1;
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0; // Writing
+ spif_req<= (spif_req) && (i_wb_cyc);
+
+ // Once we get busy, move on
+ if (spi_busy)
+ state <= `WBQSPI_WR_DATA;
+ if (spif_sector == erased_sector)
+ dirty_sector <= 1'b1;
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_QPP))
+ begin // We come here under a full stop / full port idle mode
+ // Issue our command immediately
+ spi_wr <= 1'b1;
+ spi_in <= { 8'h32, w_spif_addr };
+ spi_len <= 2'b11;
+ spi_hold <= 1'b1;
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0; // Writing
+ spif_req<= (spif_req) && (i_wb_cyc);
+
+ // Once we get busy, move on
+ if (spi_busy)
+ begin
+ // spi_wr is irrelevant here ...
+ // Set the speed value once, but wait til we get busy
+ // to do so.
+ spi_spd <= 1'b1;
+ state <= `WBQSPI_WR_DATA;
+ end
+ if (spif_sector == erased_sector)
+ dirty_sector <= 1'b1;
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WR_DATA))
+ begin
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spi_wr <= 1'b1; // write without waiting
+ spi_in <= spif_data;
+ spi_len <= 2'b11; // Write 4 bytes
+ spi_hold <= 1'b1;
+ if (!spi_busy)
+ begin
+ o_wb_ack <= spif_req; // Ack when command given
+ state <= `WBQSPI_WR_BUS_CYCLE;
+ end
+ spif_req<= (spif_req) && (i_wb_cyc);
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WR_BUS_CYCLE))
+ begin
+ o_wb_ack <= 1'b0; // Turn off our ack and stall flags
+ o_wb_stall <= 1'b1;
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b1;
+ write_in_progress <= 1'b1;
+ spif_req<= (spif_req) && (i_wb_cyc);
+ if (!i_wb_cyc)
+ begin
+ state <= `WBQSPI_WAIT_TIL_IDLE;
+ spi_hold <= 1'b0;
+ end else if (spi_wr)
+ begin // Give the SPI a chance to get busy on the last write
+ // Do nothing here.
+ end else if ((spif_req)&&(i_wb_data_stb)&&(i_wb_we)
+ &&(i_wb_addr == (spif_addr+1))
+ &&(i_wb_addr[(AW-1):6]==spif_addr[(AW-1):6]))
+ begin
+ spif_cmd <= 1'b1;
+ spif_data <= i_wb_data;
+ spif_addr <= i_wb_addr;
+ spif_ctrl <= 1'b0;
+ spif_req<= 1'b1;
+ // We'll keep the bus stalled on this request
+ // for a while
+ state <= `WBQSPI_WR_DATA;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b0;
+ end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(!o_wb_ack)) // Writing out of bounds
+ begin
+ spi_hold <= 1'b0;
+ spi_wr <= 1'b0;
+ state <= `WBQSPI_WAIT_TIL_IDLE;
+ end // Otherwise we stay here
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WRITE_CONFIG))
+ begin // We enter immediately after commanding a WEN
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ spi_len <= 2'b10;
+ spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+ if ((!spi_busy)&&(!spi_wr))
+ begin
+ spi_wr <= 1'b1;
+ state <= `WBQSPI_WAIT_TIL_IDLE;
+ write_in_progress <= 1'b1;
+ quad_mode_enabled <= spif_data[1];
+ end
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_WRITE_STATUS))
+ begin // We enter immediately after commanding a WEN
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+
+ spi_len <= 2'b01;
+ spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
+ // last_status <= i_wb_data[7:0]; // We'll read this in a moment
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+ if ((!spi_busy)&&(!spi_wr))
+ begin
+ spi_wr <= 1'b1;
+ last_status <= spif_data[7:0];
+ write_in_progress <= 1'b1;
+ if(((last_status[6])||(last_status[5]))
+ &&((!spif_data[6])&&(!spif_data[5])))
+ state <= `WBQSPI_CLEAR_STATUS;
+ else
+ state <= `WBQSPI_WAIT_TIL_IDLE;
+ end
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_ERASE_CMD))
+ begin // Know that WIP is clear on entry, WEN has just been commanded
+ spi_wr <= 1'b0;
+ o_wb_ack <= 1'b0;
+ o_wb_stall <= 1'b1;
+ spi_hold <= 1'b0;
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+
+ // Here's the erase command
+ spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
+ spi_len <= 2'b11; // 32 bit write
+ // together with setting our copy of the WIP bit
+ write_in_progress <= 1'b1;
+ // keeping track of which sector we just erased
+ erased_sector <= spif_data[(AW-1):14];
+ // and marking this erase sector as no longer dirty
+ dirty_sector <= 1'b0;
+
+ // Wait for a full stop before issuing this command
+ if ((!spi_busy)&&(!spi_wr)&&(o_qspi_cs_n))
+ begin // When our command is accepted, move to the next state
+ spi_wr <= 1'b1;
+ state <= `WBQSPI_ERASE_BLOCK;
+ end
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_ERASE_BLOCK))
+ begin
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+ // When the port clears, we can head back to idle
+ // No ack necessary, we ackd before getting
+ // here.
+ if ((!spi_busy)&&(!spi_wr))
+ state <= `WBQSPI_IDLE;
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_CLEAR_STATUS))
+ begin // Issue a clear status command
+ spi_wr <= 1'b1;
+ spi_hold <= 1'b0;
+ spi_len <= 2'b00; // 8 bit command
+ spi_in <= { 8'h30, 24'h00 };
+ spi_spd <= 1'b0;
+ spi_dir <= 1'b0;
+ last_status[6:5] <= 2'b00;
+ spif_req <= (spif_req) && (i_wb_cyc);
+ if ((spi_wr)&&(!spi_busy))
+ state <= `WBQSPI_WAIT_TIL_IDLE;
+ end else if ((!OPT_READ_ONLY)&&(state == `WBQSPI_IDLE_CHECK_WIP))
+ begin // We are now in read status register mode
+
+ // No bus commands have (yet) been given
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spif_req <= (spif_req) && (i_wb_cyc);
+
+ // Stay in this mode unless/until we get a command, or
+ // the write is over
+ spi_wr <= (((!i_wb_cyc)||((!i_wb_data_stb)&&(!i_wb_ctrl_stb)))
+ &&(write_in_progress));
+ spi_len <= 2'b00; // 8 bit reads
+ spi_spd <= 1'b0; // SPI, not quad
+ spi_dir <= 1'b1; // Read
+ if (spi_valid)
+ begin
+ write_in_progress <= spi_out[0];
+ if ((!spi_out[0])&&(write_in_progress))
+ o_interrupt <= 1'b1;
+ end else
+ o_interrupt <= 1'b0;
+
+ if ((!spi_wr)&&(!spi_busy)&&(o_qspi_cs_n))
+ begin // We can now go to idle and process a command
+ o_wb_stall <= 1'b0;
+ o_wb_ack <= 1'b0;
+ state <= `WBQSPI_IDLE;
+ end
+ end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
+ begin
+ spi_wr <= 1'b0;
+ spi_hold <= 1'b0;
+ o_wb_stall <= 1'b1;
+ o_wb_ack <= 1'b0;
+ spif_req <= 1'b0;
+ if ((!spi_busy)&&(o_qspi_cs_n)&&(!spi_wr)) // Wait for a full
+ begin // clearing of the SPI port before moving on
+ state <= `WBQSPI_IDLE;
+ o_wb_stall <= 1'b0;
+ o_wb_ack <= 1'b0; // Shouldn't be acking anything here
+ end
+ end
+ end
+
+ // Command and control during the reset sequence
+ assign o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
+ assign o_qspi_sck = (spif_override)?alt_ctrl:w_qspi_sck;
+ assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
+ assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
+endmodule
+
+`default_nettype none
+//
+`define QSPI_IDLE 3'h0
+`define QSPI_START 3'h1
+`define QSPI_BITS 3'h2
+`define QSPI_READY 3'h3
+`define QSPI_HOLDING 3'h4
+`define QSPI_STOP 3'h5
+`define QSPI_STOP_B 3'h6
+
+// Modes
+`define QSPI_MOD_SPI 2'b00
+`define QSPI_MOD_QOUT 2'b10
+`define QSPI_MOD_QIN 2'b11
+
+// Which level of formal proofs will we be doing? As a component, or a
+// top-level?
+`ifdef LLQSPI_TOP
+`define ASSUME assume
+`else
+`define ASSUME assert
+`endif
+//
+module llqspi(i_clk,
+ // Module interface
+ i_wr, i_hold, i_word, i_len, i_spd, i_dir,
+ o_word, o_valid, o_busy,
+ // QSPI interface
+ o_sck, o_cs_n, o_mod, o_dat, i_dat);
+ input wire i_clk;
+ // Chip interface
+ // Can send info
+ // i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
+ // i_word = { 1'b0, 32'info to send },
+ // i_len = # of bytes in word-1
+ input wire i_wr, i_hold;
+ input wire [31:0] i_word;
+ input wire [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
+ input wire i_spd; // 0 -> normal QPI, 1 -> QSPI
+ input wire i_dir; // 0 -> read, 1 -> write to SPI
+ output reg [31:0] o_word;
+ output reg o_valid, o_busy;
+ // Interface with the QSPI lines
+ output reg o_sck;
+ output reg o_cs_n;
+ output reg [1:0] o_mod;
+ output reg [3:0] o_dat;
+ input wire [3:0] i_dat;
+
+ // output wire [22:0] o_dbg;
+ // assign o_dbg = { state, spi_len,
+ // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
+
+ // Timing:
+ //
+ // Tick Clk BSY/WR CS_n BIT/MO STATE
+ // 0 1 0/0 1 -
+ // 1 1 0/1 1 -
+ // 2 1 1/0 0 - QSPI_START
+ // 3 0 1/0 0 - QSPI_START
+ // 4 0 1/0 0 0 QSPI_BITS
+ // 5 1 1/0 0 0 QSPI_BITS
+ // 6 0 1/0 0 1 QSPI_BITS
+ // 7 1 1/0 0 1 QSPI_BITS
+ // 8 0 1/0 0 2 QSPI_BITS
+ // 9 1 1/0 0 2 QSPI_BITS
+ // 10 0 1/0 0 3 QSPI_BITS
+ // 11 1 1/0 0 3 QSPI_BITS
+ // 12 0 1/0 0 4 QSPI_BITS
+ // 13 1 1/0 0 4 QSPI_BITS
+ // 14 0 1/0 0 5 QSPI_BITS
+ // 15 1 1/0 0 5 QSPI_BITS
+ // 16 0 1/0 0 6 QSPI_BITS
+ // 17 1 1/1 0 6 QSPI_BITS
+ // 18 0 1/1 0 7 QSPI_READY
+ // 19 1 0/1 0 7 QSPI_READY
+ // 20 0 1/0/V 0 8 QSPI_BITS
+ // 21 1 1/0 0 8 QSPI_BITS
+ // 22 0 1/0 0 9 QSPI_BITS
+ // 23 1 1/0 0 9 QSPI_BITS
+ // 24 0 1/0 0 10 QSPI_BITS
+ // 25 1 1/0 0 10 QSPI_BITS
+ // 26 0 1/0 0 11 QSPI_BITS
+ // 27 1 1/0 0 11 QSPI_BITS
+ // 28 0 1/0 0 12 QSPI_BITS
+ // 29 1 1/0 0 12 QSPI_BITS
+ // 30 0 1/0 0 13 QSPI_BITS
+ // 31 1 1/0 0 13 QSPI_BITS
+ // 32 0 1/0 0 14 QSPI_BITS
+ // 33 1 1/0 0 14 QSPI_BITS
+ // 34 0 1/0 0 15 QSPI_READY
+ // 35 1 1/0 0 15 QSPI_READY
+ // 36 1 1/0/V 0 - QSPI_STOP
+ // 37 1 1/0 0 - QSPI_STOPB
+ // 38 1 1/0 1 - QSPI_IDLE
+ // 39 1 0/0 1 -
+ // Now, let's switch from single bit to quad mode
+ // 40 1 0/0 1 - QSPI_IDLE
+ // 41 1 0/1 1 - QSPI_IDLE
+ // 42 1 1/0 0 - QSPI_START
+ // 43 0 1/0 0 - QSPI_START
+ // 44 0 1/0 0 0 QSPI_BITS
+ // 45 1 1/0 0 0 QSPI_BITS
+ // 46 0 1/0 0 1 QSPI_BITS
+ // 47 1 1/0 0 1 QSPI_BITS
+ // 48 0 1/0 0 2 QSPI_BITS
+ // 49 1 1/0 0 2 QSPI_BITS
+ // 50 0 1/0 0 3 QSPI_BITS
+ // 51 1 1/0 0 3 QSPI_BITS
+ // 52 0 1/0 0 4 QSPI_BITS
+ // 53 1 1/0 0 4 QSPI_BITS
+ // 54 0 1/0 0 5 QSPI_BITS
+ // 55 1 1/0 0 5 QSPI_BITS
+ // 56 0 1/0 0 6 QSPI_BITS
+ // 57 1 1/1/QR 0 6 QSPI_BITS
+ // 58 0 1/1/QR 0 7 QSPI_READY
+ // 59 1 0/1/QR 0 7 QSPI_READY
+ // 60 0 1/0/?/V 0 8-11 QSPI_BITS
+ // 61 1 1/0/? 0 8-11 QSPI_BITS
+ // 62 0 1/0/? 0 12-15 QSPI_BITS
+ // 63 1 1/0/? 0 12-15 QSPI_BITS
+ // 64 1 1/0/?/V 0 - QSPI_STOP
+ // 65 1 1/0/? 0 - QSPI_STOPB
+ // 66 1 1/0/? 1 - QSPI_IDLE
+ // 67 1 0/0 1 - QSPI_IDLE
+ // Now let's try something entirely in Quad read mode, from the
+ // beginning
+ // 68 1 0/1/QR 1 - QSPI_IDLE
+ // 69 1 1/0 0 - QSPI_START
+ // 70 0 1/0 0 - QSPI_START
+ // 71 0 1/0 0 0-3 QSPI_BITS
+ // 72 1 1/0 0 0-3 QSPI_BITS
+ // 73 0 1/1/QR 0 4-7 QSPI_BITS
+ // 74 1 0/1/QR 0 4-7 QSPI_BITS
+ // 75 0 1/?/?/V 0 8-11 QSPI_BITS
+ // 76 1 1/?/? 0 8-11 QSPI_BITS
+ // 77 0 1/1/QR 0 12-15 QSPI_BITS
+ // 78 1 0/1/QR 0 12-15 QSPI_BITS
+ // 79 0 1/?/?/V 0 16-19 QSPI_BITS
+ // 80 1 1/0 0 16-19 QSPI_BITS
+ // 81 0 1/0 0 20-23 QSPI_BITS
+ // 82 1 1/0 0 20-23 QSPI_BITS
+ // 83 1 1/0/V 0 - QSPI_STOP
+ // 84 1 1/0 0 - QSPI_STOPB
+ // 85 1 1/0 1 - QSPI_IDLE
+ // 86 1 0/0 1 - QSPI_IDLE
+
+ wire i_miso;
+ assign i_miso = i_dat[1];
+
+ reg r_spd, r_dir;
+ reg [5:0] spi_len;
+ reg [31:0] r_word;
+ reg [30:0] r_input;
+ reg [2:0] state;
+ initial state = `QSPI_IDLE;
+ initial o_sck = 1'b1;
+ initial o_cs_n = 1'b1;
+ initial o_dat = 4'hd;
+ initial o_valid = 1'b0;
+ initial o_busy = 1'b0;
+ initial r_input = 31'h000;
+ initial o_mod = `QSPI_MOD_SPI;
+ initial o_word = 0;
+ always @(posedge i_clk)
+ if ((state == `QSPI_IDLE)&&(o_sck))
+ begin
+ o_cs_n <= 1'b1;
+ o_valid <= 1'b0;
+ o_busy <= 1'b0;
+ o_mod <= `QSPI_MOD_SPI;
+ r_word <= i_word;
+ r_spd <= i_spd;
+ r_dir <= i_dir;
+ if ((i_wr)&&(!o_busy))
+ begin
+ state <= `QSPI_START;
+ spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
+ o_cs_n <= 1'b0;
+ // o_sck <= 1'b1;
+ o_busy <= 1'b1;
+ end
+ end else if (state == `QSPI_START)
+ begin // We come in here with sck high, stay here 'til sck is low
+ o_sck <= 1'b0;
+ if (o_sck == 1'b0)
+ begin
+ state <= `QSPI_BITS;
+ spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
+ if (r_spd)
+ r_word <= { r_word[27:0], 4'h0 };
+ else
+ r_word <= { r_word[30:0], 1'b0 };
+ end
+ o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
+ o_cs_n <= 1'b0;
+ o_busy <= 1'b1;
+ o_valid <= 1'b0;
+ if (r_spd)
+ o_dat <= r_word[31:28];
+ else
+ o_dat <= { 3'b110, r_word[31] };
+ end else if (!o_sck)
+ begin
+ o_sck <= 1'b1;
+ o_busy <= ((state != `QSPI_READY)||(!i_wr));
+ o_valid <= 1'b0;
+ end else if (state == `QSPI_BITS)
+ begin
+ // Should enter into here with at least a spi_len
+ // of one, perhaps more
+ o_sck <= 1'b0;
+ o_busy <= 1'b1;
+ if (r_spd)
+ begin
+ o_dat <= r_word[31:28];
+ r_word <= { r_word[27:0], 4'h0 };
+ spi_len <= spi_len - 6'h4;
+ if (spi_len == 6'h4)
+ state <= `QSPI_READY;
+ end else begin
+ o_dat <= { 3'b110, r_word[31] };
+ r_word <= { r_word[30:0], 1'b0 };
+ spi_len <= spi_len - 6'h1;
+ if (spi_len == 6'h1)
+ state <= `QSPI_READY;
+ end
+
+ o_valid <= 1'b0;
+ if (!o_mod[1])
+ r_input <= { r_input[29:0], i_miso };
+ else if (o_mod[1])
+ r_input <= { r_input[26:0], i_dat };
+ end else if (state == `QSPI_READY)
+ begin
+ o_valid <= 1'b0;
+ o_cs_n <= 1'b0;
+ o_busy <= 1'b1;
+ // This is the state on the last clock (both low and
+ // high clocks) of the data. Data is valid during
+ // this state. Here we chose to either STOP or
+ // continue and transmit more.
+ o_sck <= (i_hold); // No clocks while holding
+ r_spd <= i_spd;
+ r_dir <= i_dir;
+ if (i_spd)
+ begin
+ r_word <= { i_word[27:0], 4'h0 };
+ spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4;
+ end else begin
+ r_word <= { i_word[30:0], 1'b0 };
+ spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1;
+ end
+ if((!o_busy)&&(i_wr))// Acknowledge a new request
+ begin
+ state <= `QSPI_BITS;
+ o_busy <= 1'b1;
+ o_sck <= 1'b0;
+
+ // Read the new request off the bus
+ // Set up the first bits on the bus
+ o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
+ if (i_spd)
+ o_dat <= i_word[31:28];
+ else
+ o_dat <= { 3'b110, i_word[31] };
+
+ end else begin
+ o_sck <= 1'b1;
+ state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
+ o_busy <= (!i_hold);
+ end
+
+ // Read a bit upon any transition
+ o_valid <= 1'b1;
+ if (!o_mod[1])
+ begin
+ r_input <= { r_input[29:0], i_miso };
+ o_word <= { r_input[30:0], i_miso };
+ end else if (o_mod[1])
+ begin
+ r_input <= { r_input[26:0], i_dat };
+ o_word <= { r_input[27:0], i_dat };
+ end
+ end else if (state == `QSPI_HOLDING)
+ begin
+ // We need this state so that the o_valid signal
+ // can get strobed with our last result. Otherwise
+ // we could just sit in READY waiting for a new command.
+ //
+ // Incidentally, the change producing this state was
+ // the result of a nasty race condition. See the
+ // commends in wbqspiflash for more details.
+ //
+ o_valid <= 1'b0;
+ o_cs_n <= 1'b0;
+ o_busy <= 1'b0;
+ r_spd <= i_spd;
+ r_dir <= i_dir;
+ if (i_spd)
+ begin
+ r_word <= { i_word[27:0], 4'h0 };
+ spi_len<= { 1'b0, i_len, 3'b100 };
+ end else begin
+ r_word <= { i_word[30:0], 1'b0 };
+ spi_len<= { 1'b0, i_len, 3'b111 };
+ end
+ if((!o_busy)&&(i_wr))// Acknowledge a new request
+ begin
+ state <= `QSPI_BITS;
+ o_busy <= 1'b1;
+ o_sck <= 1'b0;
+
+ // Read the new request off the bus
+ // Set up the first bits on the bus
+ o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
+ if (i_spd)
+ o_dat <= i_word[31:28];
+ else
+ o_dat <= { 3'b110, i_word[31] };
+ end else begin
+ o_sck <= 1'b1;
+ state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
+ o_busy <= (!i_hold);
+ end
+ end else if (state == `QSPI_STOP)
+ begin
+ o_sck <= 1'b1; // Stop the clock
+ o_valid <= 1'b0; // Output may have just been valid, but no more
+ o_busy <= 1'b1; // Still busy till port is clear
+ state <= `QSPI_STOP_B;
+ o_mod <= `QSPI_MOD_SPI;
+ end else if (state == `QSPI_STOP_B)
+ begin
+ o_cs_n <= 1'b1;
+ o_sck <= 1'b1;
+ // Do I need this????
+ // spi_len <= 3; // Minimum CS high time before next cmd
+ state <= `QSPI_IDLE;
+ o_valid <= 1'b0;
+ o_busy <= 1'b1;
+ o_mod <= `QSPI_MOD_SPI;
+ end else begin // Invalid states, should never get here
+ state <= `QSPI_STOP;
+ o_valid <= 1'b0;
+ o_busy <= 1'b1;
+ o_cs_n <= 1'b1;
+ o_sck <= 1'b1;
+ o_mod <= `QSPI_MOD_SPI;
+ o_dat <= 4'hd;
+ end
+
+`ifdef FORMAL
+ reg prev_i_clk, past_valid;
+
+ initial `ASSUME(i_clk == 1'b0);
+ initial prev_i_clk = 1;
+ always @($global_clock)
+ begin
+ prev_i_clk <= i_clk;
+ `ASSUME(i_clk != prev_i_clk);
+ end
+
+ reg past_valid;
+ initial past_valid = 1'b0;
+ always @(posedge i_clk)
+ past_valid <= 1'b1;
+
+ /*
+ always @(*)
+ if (!$stable(i_spd))
+ assert($rose(i_clk));
+ */
+
+ always @(posedge i_clk) begin
+ if ((past_valid)&&($past(i_wr))&&($past(o_busy)))
+ begin
+ // any time i_wr and o_busy are true, nothing changes
+ // of spd, len, word or dir
+ `ASSUME(i_wr);
+ `ASSUME(i_spd == $past(i_spd));
+ `ASSUME(i_len == $past(i_len));
+ `ASSUME(i_word == $past(i_word));
+ `ASSUME(i_dir == $past(i_dir));
+ `ASSUME(i_hold == $past(i_hold));
+ end
+ if ((past_valid)&&($past(i_wr))&&($past(o_busy))&&($past(state == `QSPI_IDLE)))
+ assert($past(state)==state);
+ if (i_hold == $past(i_hold))
+ assert($stable(i_hold));
+ end
+
+ always @(*) begin
+ if (o_mod == `QSPI_MOD_QOUT)
+ `ASSUME(i_dat == o_dat);
+ if (o_mod == `QSPI_MOD_SPI)
+ `ASSUME(i_dat[3:2] == 2'b11);
+ if (o_mod == `QSPI_MOD_SPI)
+ `ASSUME(i_dat[0] == o_dat[0]);
+ end
+
+ initial `ASSUME(i_wr == 1'b0);
+ initial `ASSUME(i_word == 0);
+
+ always @($global_clock)
+ if (!$rose(i_clk))
+ begin
+ `ASSUME($stable(i_wr));
+ //
+ `ASSUME($stable(i_len));
+ `ASSUME($stable(i_dir));
+ `ASSUME($stable(i_spd));
+ `ASSUME($stable(i_word));
+ //
+ `ASSUME($stable(i_hold));
+ end
+
+ always @($global_clock)
+ if (!$fell(o_sck))
+ assume($stable(i_dat));
+
+ // This is ... not as believable. There might be a delay here.
+ // For now, we'll just assume (not necessarily true) that the
+ // output
+ always @(posedge i_clk)
+ if (past_valid)
+ `ASSUME( (i_dat == $past(i_dat)) || (o_sck != $past(o_sck)) );
+
+ reg f_last_sck;
+ always @(posedge i_clk)
+ f_last_sck <= o_sck;
+
+ reg [31:0] f_shiftreg, f_goal;
+ initial f_shiftreg = 0;
+ initial f_goal = 0;
+ always @(posedge i_clk)
+ if ((o_sck)&&(!f_last_sck))
+ begin
+ if (o_mod == `QSPI_MOD_QOUT)
+ f_shiftreg <= { f_shiftreg[28:0], o_dat };
+ else if (o_mod == `QSPI_MOD_SPI)
+ f_shiftreg <= { f_shiftreg[30:0], o_dat[0] };
+ end
+
+ reg [5:0] f_nsent, f_vsent;
+ reg [2:0] f_nbits_r;
+ wire [5:0] f_nbits;
+ always @(posedge i_clk)
+ if ((i_wr)&&(!o_busy))
+ begin
+ f_goal <= i_word;
+ f_nbits_r <= { 1'b0, i_len } + 3'h1;
+ end
+ assign f_nbits = { f_nbits_r, 3'b000 };
+ always @(posedge i_clk)
+ if ((!o_sck)||(!o_cs_n))
+ assert(f_nbits != 0);
+
+ always @(posedge i_clk)
+ if (o_cs_n)
+ f_nsent <= 0;
+ else if ((!o_busy)&&(i_wr))
+ f_nsent <= 0;
+ else if ((!f_last_sck)&&(o_sck))
+ begin
+ if (o_mod == `QSPI_MOD_SPI)
+ f_nsent <= f_nsent + 6'h1;
+ else
+ f_nsent <= f_nsent + 6'h4;
+ end
+ always @(posedge i_clk)
+ if (o_cs_n)
+ f_vsent <= 0;
+ else
+ f_vsent <= f_nsent;
+ always @(posedge i_clk)
+ if ((!o_cs_n)&&(state == `QSPI_BITS)&&(!o_sck))
+ begin
+ if (o_mod != `QSPI_MOD_SPI)
+ assert(f_nsent + spi_len + 6'h4 == f_nbits);
+ else
+ assert(f_nsent + spi_len + 6'h1 == f_nbits);
+ end
+
+ always @(posedge i_clk)
+ assert((o_busy)||(f_goal[(f_nbits-1):0] == f_shiftreg[(f_nbits-1):0]));
+
+ always @(posedge i_clk) begin
+ // We are only ever in one of three speed modes, fourth mode
+ // isn't allowed
+ assert( (o_mod == `QSPI_MOD_SPI)
+ ||(o_mod == `QSPI_MOD_QIN)
+ ||(o_mod == `QSPI_MOD_QOUT));
+
+ if ((past_valid)&&($past(i_wr))&&(!$past(o_busy)))
+ begin
+ // Any accepted request leaves us in an active state
+ assert(!o_cs_n);
+
+ // Any accepted request allows us to set our speed
+ assert(r_spd == $past(i_spd));
+ end
+
+ // We're either busy, or idle with the clock high
+ // or pausing (upon a request) mid-transaction
+ assert((o_busy)
+ ||((state == `QSPI_IDLE)&&(o_sck)&&(o_cs_n))
+ ||((state == `QSPI_READY)&&(o_sck)&&(!o_cs_n))
+ ||((state == `QSPI_HOLDING)&&(o_sck)&&(!o_cs_n))
+ );
+
+ // Anytime CS is idle, SCK is high
+ if (o_cs_n)
+ assert(o_sck);
+
+
+ // What can we assert about i_hold?
+
+ // When i_hold is asserted before a transaction completes,
+ // the transaction will "hold" and wait for a next input.
+ // i.e. the clock will stop
+
+ // First assert that o_busy will be deasserted any time the
+ // currently requested word has been sent
+ //
+ //if ((($past(i_wr))||(i_hold))
+ // &&(f_nsent == f_nbits)&&(!o_sck)&&(!o_cs_n))
+ // assert(!o_busy);
+
+
+ // First, assert of i_hold that !o_busy will be set.
+ if ((past_valid)&&($past(i_hold))&&(f_nsent == f_nbits)&&(!o_cs_n))
+ begin
+ assert((!o_busy)||(o_sck));
+ end
+ if ((past_valid)&&($past(i_hold))&&(!$past(i_wr))
+ &&(!$past(o_busy))&&(!$past(o_cs_n)))
+ begin
+ assert(!o_cs_n);
+ assert($past(o_sck)==o_sck);
+ end
+
+ // DATA only changes on the falling edge of SCK
+ if ((past_valid)&&(o_sck))
+ assert(o_dat==$past(o_dat));
+
+ // Valid is only ever true for one clock
+ if ((past_valid)&&(o_valid))
+ assert(!$past(o_valid));
+
+ // Valid is only ever true after receiving a full number of bits
+ if ((past_valid)&&(o_valid))
+ begin
+ if ((!$past(i_wr))||($past(o_busy)))
+ assert(f_nsent == f_nbits);
+ end
+
+ // In SPI mode, the top bits of o_dat are always 3'b110
+ //
+ // This should be true, but there's a problem holding this
+ // true
+ // assert( (o_mod != `QSPI_MOD_SPI)||(o_dat[3:1] == 3'b110) );
+
+ // Either valid is true (this clock), or our output word is
+ // identical to what it was on the last clock
+ if (past_valid)
+ assert((o_valid) || (o_word == $past(o_word)));
+ end
+`endif
+
+endmodule
\ No newline at end of file
diff --git a/openlane/designs/xtea/config.tcl b/openlane/designs/xtea/config.tcl
new file mode 100755
index 0000000..704b02b
--- /dev/null
+++ b/openlane/designs/xtea/config.tcl
@@ -0,0 +1,16 @@
+
+# Design
+
+# Design
+set ::env(DESIGN_NAME) "xtea"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/xtea.v"
+set ::env(SDC_FILE) "$::env(DESIGN_DIR)/src/xtea.sdc"
+
+set ::env(CLOCK_PORT) "clock"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/xtea/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/xtea/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..9b1486c
--- /dev/null
+++ b/openlane/designs/xtea/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "26.03"
+set ::env(FP_CORE_UTIL) 45
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/xtea/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/xtea/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..9b1486c
--- /dev/null
+++ b/openlane/designs/xtea/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "26.03"
+set ::env(FP_CORE_UTIL) 45
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/xtea/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/xtea/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..f53aa9d
--- /dev/null
+++ b/openlane/designs/xtea/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,9 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 35
+
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+
+# Suggested Clock Period:
+set ::env(CLOCK_PERIOD) "26.03"
diff --git a/openlane/designs/xtea/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/xtea/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..6ee7911
--- /dev/null
+++ b/openlane/designs/xtea/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "26.03"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/xtea/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/xtea/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..5969a7c
--- /dev/null
+++ b/openlane/designs/xtea/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,8 @@
+# SCL Configs
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+
+# Suggested Clock Period:
+set ::env(CLOCK_PERIOD) "26.03"
diff --git a/openlane/designs/xtea/src/xtea.sdc b/openlane/designs/xtea/src/xtea.sdc
new file mode 100644
index 0000000..7e112ec
--- /dev/null
+++ b/openlane/designs/xtea/src/xtea.sdc
@@ -0,0 +1,31 @@
+set_units -time ns
+create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
diff --git a/openlane/designs/xtea/src/xtea.v b/openlane/designs/xtea/src/xtea.v
new file mode 100644
index 0000000..90661b5
--- /dev/null
+++ b/openlane/designs/xtea/src/xtea.v
@@ -0,0 +1,192 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// XTEA IP Core ////
+//// ////
+//// This file is part of the xtea project ////
+//// http://www.opencores.org/projects.cgi/web/xtea/overview ////
+//// ////
+//// An implementation of the XTEA encryption algorithm. ////
+//// ////
+//// TODO: ////
+//// * Write a spec ////
+//// * Wishbone compliance ////
+//// ////
+//// Author: David Johnson, dj@david-web.co.uk ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2006 David Johnson ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, write to the ////
+//// Free Software Foundation, Inc., 51 Franklin Street, Fifth ////
+//// Floor, Boston, MA 02110-1301 USA ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module xtea(clock, reset, mode, data_in1, data_in2, key_in, data_out1, data_out2, all_done);
+
+parameter s0 = 8'd0, s1 = 8'd1, s2 = 8'd2, s3 = 8'd3, s4 = 8'd4, s5 = 8'd5, s6 = 8'd6, s7 = 8'd7, s8 = 8'd8, s9 = 8'd9, s10 = 8'd10,
+ s11 = 8'd11, s12 = 8'd12, s13 = 8'd13, s14 = 8'd14, s15 = 8'd15, s16 = 8'd16, s17 = 8'd17;
+
+input clock, reset, mode;
+input[31:0] data_in1, data_in2;
+input[127:0] key_in;
+output[31:0] data_out1, data_out2;
+output all_done;
+
+wire clock, reset;
+wire[31:0] data_in1, data_in2;
+wire[127:0] key_in;
+reg all_done, while_flag, modereg;
+reg[1:0] selectslice;
+reg[7:0] state;
+reg[7:0] x;
+reg[31:0] data_out1, data_out2, sum, workunit1, workunit2, delta;
+
+always @(posedge clock or posedge reset)
+begin
+ if (reset)
+ //reset state
+ state = s0;
+ else begin
+ case (state)
+ s0: state = s1;
+ s1: state = s2;
+ s2: state = s3;
+ s3: state = while_flag ? s4 : s14;
+ s4: state = modereg ? s10 : s5;
+ s5: state = s6;
+ s6: state = s7;
+ s7: state = s8;
+ s8: state = s9;
+ s9: state = s2;
+ s10: state = s11;
+ s11: state = s12;
+ s12: state = s13;
+ s13: state = s14;
+ s14: state = s2;
+ s15: state = s16;
+ s16: state = s17;
+ s17: state = s17;
+ default: state = 4'bxxxx;
+ endcase
+ end
+end
+
+always @(posedge clock or posedge reset)
+begin
+ if (reset) begin
+ //reset all our outputs and registers
+ data_out1 = 32'h00000000;
+ data_out2 = 32'h00000000;
+ x = 8'b00000000;
+ sum = 32'h00000000;
+ while_flag = 1'b0;
+ workunit1 = 32'h00000000;
+ workunit2 = 32'h00000000;
+ selectslice = 1'b0;
+ all_done = 1'b0;
+ delta = 32'h00000000;
+ modereg = 1'b0;
+ end
+ else begin
+ case (state)
+ s1: begin
+ //store input values to registers in case they're not stable
+ workunit1 = data_in1;
+ workunit2 = data_in2;
+ delta = 32'h9E3779B9;
+ sum = 32'hc6ef3720;
+ modereg = mode;
+ end
+ s2: if (x < 8'd32) while_flag = 1'b1; else while_flag = 1'b0;
+ s3: begin
+ //This null state was necessary to fix a timing issue.
+ //s2 sets while_flag and previously the control path read it in the same state
+ //(but in the next clock cycle), however the reg wasn't set when we tried to
+ //read it, so this state was inserted to add a delay. This was when running @25MHz.
+ //FIXME: there's got to be a better solution to this...
+ end
+ s4: begin
+ //This state does nothing in the data path; it's used for an if statement in the
+ //control path.
+ end
+ /* States 5-9 used for decipher operations */
+ s5: selectslice = (sum >> 32'd11 & 32'd3);
+ s6: case (selectslice)
+ 2'b00: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
+ 2'b01: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
+ 2'b10: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
+ 2'b11: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
+ default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
+ endcase
+ s7: sum = sum - delta;
+ s8: selectslice = (sum & 32'd3);
+ s9: begin
+ case (selectslice)
+ 2'b00: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
+ 2'b01: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
+ 2'b10: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
+ 2'b11: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
+ default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
+ endcase
+ x = x + 1'b1;
+ end
+ /* States 10-14 used for encipher operations */
+ s10: selectslice = (sum & 32'd3);
+ s11: case (selectslice)
+ 2'b00: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
+ 2'b01: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
+ 2'b10: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
+ 2'b11: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
+ default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
+ endcase
+ s12: sum = sum + delta;
+ s13: selectslice = (sum >> 32'd11 & 32'd3);
+ s14: begin
+ case (selectslice)
+ 2'b00: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
+ 2'b01: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
+ 2'b10: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
+ 2'b11: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
+ default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
+ endcase
+ x = x + 1'b1;
+ end
+ s15: begin
+ //This state was added to fix a timing issue.
+ //Same issue as above - trying to read workunit1 & workunit2 before they've settled.
+ end
+ s16: begin
+ //set the outputs to the working registers
+ data_out1 = workunit1;
+ data_out2 = workunit2;
+ end
+ s17: all_done = 1'b1;
+ default: begin
+ data_out1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
+ data_out2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
+ end
+ endcase
+ end
+end
+
+endmodule
diff --git a/openlane/designs/y_huff/config.tcl b/openlane/designs/y_huff/config.tcl
new file mode 100755
index 0000000..13ed7f7
--- /dev/null
+++ b/openlane/designs/y_huff/config.tcl
@@ -0,0 +1,17 @@
+
+# Design
+set ::env(DESIGN_NAME) "y_huff"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/y_huff.v"
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+# design has a lot of pins, needs an absolute size
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) {0 0 700 700}
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/y_huff/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/y_huff/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..c4b2891
--- /dev/null
+++ b/openlane/designs/y_huff/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "14"
+set ::env(FP_CORE_UTIL) 40
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/y_huff/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/y_huff/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..7bb0579
--- /dev/null
+++ b/openlane/designs/y_huff/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "11.35"
+set ::env(FP_CORE_UTIL) 40
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/y_huff/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/y_huff/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..42967a0
--- /dev/null
+++ b/openlane/designs/y_huff/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,5 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "11.35"
+set ::env(FP_CORE_UTIL) 30
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
diff --git a/openlane/designs/y_huff/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/y_huff/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..6d59ff1
--- /dev/null
+++ b/openlane/designs/y_huff/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "11.35"
+set ::env(FP_CORE_UTIL) 35
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/y_huff/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/y_huff/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..9e571b5
--- /dev/null
+++ b/openlane/designs/y_huff/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "11.35"
+set ::env(FP_CORE_UTIL) 30
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/y_huff/src/y_huff.v b/openlane/designs/y_huff/src/y_huff.v
new file mode 100644
index 0000000..8ec9533
--- /dev/null
+++ b/openlane/designs/y_huff/src/y_huff.v
@@ -0,0 +1,2253 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// JPEG Encoder Core - Verilog ////
+//// ////
+//// Author: David Lundgren ////
+//// davidklun@gmail.com ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2009 David Lundgren ////
+//// davidklun@gmail.com ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+/* This module is the Huffman encoder. It takes in the quantized outputs
+from the quantizer, and creates the Huffman codes from these value. The
+output from this module is the jpeg code of the actual pixel data. The jpeg
+file headers will need to be generated separately. The Huffman codes are constant,
+and they can be changed by changing the parameters in this module. */
+
+`timescale 1ns / 100ps
+
+module y_huff(clk, rst, enable,
+Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24, Y25, Y26, Y27, Y28,
+Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38, Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48,
+Y51, Y52, Y53, Y54, Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68,
+Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84, Y85, Y86, Y87, Y88,
+JPEG_bitstream, data_ready, output_reg_count, end_of_block_output,
+ end_of_block_empty);
+input clk;
+input rst;
+input enable;
+input [10:0] Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24;
+input [10:0] Y25, Y26, Y27, Y28, Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38;
+input [10:0] Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48, Y51, Y52, Y53, Y54;
+input [10:0] Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68;
+input [10:0] Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84;
+input [10:0] Y85, Y86, Y87, Y88;
+output [31:0] JPEG_bitstream;
+output data_ready;
+output [4:0] output_reg_count;
+output end_of_block_output;
+output end_of_block_empty;
+
+reg [7:0] block_counter;
+reg [11:0] Y11_amp, Y11_1_pos, Y11_1_neg, Y11_diff;
+reg [11:0] Y11_previous, Y11_1;
+reg [10:0] Y12_amp, Y12_pos, Y12_neg;
+reg [10:0] Y21_pos, Y21_neg, Y31_pos, Y31_neg, Y22_pos, Y22_neg;
+reg [10:0] Y13_pos, Y13_neg, Y14_pos, Y14_neg, Y15_pos, Y15_neg;
+reg [10:0] Y16_pos, Y16_neg, Y17_pos, Y17_neg, Y18_pos, Y18_neg;
+reg [10:0] Y23_pos, Y23_neg, Y24_pos, Y24_neg, Y25_pos, Y25_neg;
+reg [10:0] Y26_pos, Y26_neg, Y27_pos, Y27_neg, Y28_pos, Y28_neg;
+reg [10:0] Y32_pos, Y32_neg;
+reg [10:0] Y33_pos, Y33_neg, Y34_pos, Y34_neg, Y35_pos, Y35_neg;
+reg [10:0] Y36_pos, Y36_neg, Y37_pos, Y37_neg, Y38_pos, Y38_neg;
+reg [10:0] Y41_pos, Y41_neg, Y42_pos, Y42_neg;
+reg [10:0] Y43_pos, Y43_neg, Y44_pos, Y44_neg, Y45_pos, Y45_neg;
+reg [10:0] Y46_pos, Y46_neg, Y47_pos, Y47_neg, Y48_pos, Y48_neg;
+reg [10:0] Y51_pos, Y51_neg, Y52_pos, Y52_neg;
+reg [10:0] Y53_pos, Y53_neg, Y54_pos, Y54_neg, Y55_pos, Y55_neg;
+reg [10:0] Y56_pos, Y56_neg, Y57_pos, Y57_neg, Y58_pos, Y58_neg;
+reg [10:0] Y61_pos, Y61_neg, Y62_pos, Y62_neg;
+reg [10:0] Y63_pos, Y63_neg, Y64_pos, Y64_neg, Y65_pos, Y65_neg;
+reg [10:0] Y66_pos, Y66_neg, Y67_pos, Y67_neg, Y68_pos, Y68_neg;
+reg [10:0] Y71_pos, Y71_neg, Y72_pos, Y72_neg;
+reg [10:0] Y73_pos, Y73_neg, Y74_pos, Y74_neg, Y75_pos, Y75_neg;
+reg [10:0] Y76_pos, Y76_neg, Y77_pos, Y77_neg, Y78_pos, Y78_neg;
+reg [10:0] Y81_pos, Y81_neg, Y82_pos, Y82_neg;
+reg [10:0] Y83_pos, Y83_neg, Y84_pos, Y84_neg, Y85_pos, Y85_neg;
+reg [10:0] Y86_pos, Y86_neg, Y87_pos, Y87_neg, Y88_pos, Y88_neg;
+reg [3:0] Y11_bits_pos, Y11_bits_neg, Y11_bits, Y11_bits_1;
+reg [3:0] Y12_bits_pos, Y12_bits_neg, Y12_bits, Y12_bits_1;
+reg [3:0] Y12_bits_2, Y12_bits_3;
+reg Y11_msb, Y12_msb, Y12_msb_1, data_ready;
+reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
+reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12;
+reg enable_13, enable_module, enable_latch_7, enable_latch_8;
+reg Y12_et_zero, rollover, rollover_1, rollover_2, rollover_3;
+reg rollover_4, rollover_5, rollover_6, rollover_7;
+reg Y21_et_zero, Y21_msb, Y31_et_zero, Y31_msb;
+reg Y22_et_zero, Y22_msb, Y13_et_zero, Y13_msb;
+reg Y14_et_zero, Y14_msb, Y15_et_zero, Y15_msb;
+reg Y16_et_zero, Y16_msb, Y17_et_zero, Y17_msb;
+reg Y18_et_zero, Y18_msb;
+reg Y23_et_zero, Y23_msb, Y24_et_zero, Y24_msb;
+reg Y25_et_zero, Y25_msb, Y26_et_zero, Y26_msb;
+reg Y27_et_zero, Y27_msb, Y28_et_zero, Y28_msb;
+reg Y32_et_zero, Y32_msb, Y33_et_zero, Y33_msb;
+reg Y34_et_zero, Y34_msb, Y35_et_zero, Y35_msb;
+reg Y36_et_zero, Y36_msb, Y37_et_zero, Y37_msb;
+reg Y38_et_zero, Y38_msb;
+reg Y41_et_zero, Y41_msb, Y42_et_zero, Y42_msb;
+reg Y43_et_zero, Y43_msb, Y44_et_zero, Y44_msb;
+reg Y45_et_zero, Y45_msb, Y46_et_zero, Y46_msb;
+reg Y47_et_zero, Y47_msb, Y48_et_zero, Y48_msb;
+reg Y51_et_zero, Y51_msb, Y52_et_zero, Y52_msb;
+reg Y53_et_zero, Y53_msb, Y54_et_zero, Y54_msb;
+reg Y55_et_zero, Y55_msb, Y56_et_zero, Y56_msb;
+reg Y57_et_zero, Y57_msb, Y58_et_zero, Y58_msb;
+reg Y61_et_zero, Y61_msb, Y62_et_zero, Y62_msb;
+reg Y63_et_zero, Y63_msb, Y64_et_zero, Y64_msb;
+reg Y65_et_zero, Y65_msb, Y66_et_zero, Y66_msb;
+reg Y67_et_zero, Y67_msb, Y68_et_zero, Y68_msb;
+reg Y71_et_zero, Y71_msb, Y72_et_zero, Y72_msb;
+reg Y73_et_zero, Y73_msb, Y74_et_zero, Y74_msb;
+reg Y75_et_zero, Y75_msb, Y76_et_zero, Y76_msb;
+reg Y77_et_zero, Y77_msb, Y78_et_zero, Y78_msb;
+reg Y81_et_zero, Y81_msb, Y82_et_zero, Y82_msb;
+reg Y83_et_zero, Y83_msb, Y84_et_zero, Y84_msb;
+reg Y85_et_zero, Y85_msb, Y86_et_zero, Y86_msb;
+reg Y87_et_zero, Y87_msb, Y88_et_zero, Y88_msb;
+reg Y12_et_zero_1, Y12_et_zero_2, Y12_et_zero_3, Y12_et_zero_4, Y12_et_zero_5;
+reg [10:0] Y_DC [11:0];
+reg [3:0] Y_DC_code_length [11:0];
+reg [15:0] Y_AC [161:0];
+reg [4:0] Y_AC_code_length [161:0];
+reg [7:0] Y_AC_run_code [250:0];
+reg [10:0] Y11_Huff, Y11_Huff_1, Y11_Huff_2;
+reg [15:0] Y12_Huff, Y12_Huff_1, Y12_Huff_2;
+reg [3:0] Y11_Huff_count, Y11_Huff_shift, Y11_Huff_shift_1, Y11_amp_shift, Y12_amp_shift;
+reg [3:0] Y12_Huff_shift, Y12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3;
+reg [4:0] Y12_Huff_count, Y12_Huff_count_1;
+reg [4:0] output_reg_count, Y11_output_count, old_orc_1, old_orc_2;
+reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Y12_oc_1;
+reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8;
+reg [4:0] Y12_output_count;
+reg [4:0] Y12_edge, Y12_edge_1, Y12_edge_2, Y12_edge_3, Y12_edge_4;
+reg [31:0] JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5;
+reg [31:0] JPEG_Y12_bs, JPEG_Y12_bs_1, JPEG_Y12_bs_2, JPEG_Y12_bs_3, JPEG_Y12_bs_4;
+reg [31:0] JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4;
+reg [21:0] Y11_JPEG_LSBs_3;
+reg [10:0] Y11_JPEG_LSBs, Y11_JPEG_LSBs_1, Y11_JPEG_LSBs_2;
+reg [9:0] Y12_JPEG_LSBs, Y12_JPEG_LSBs_1, Y12_JPEG_LSBs_2, Y12_JPEG_LSBs_3;
+reg [25:0] Y11_JPEG_bits, Y11_JPEG_bits_1, Y12_JPEG_bits, Y12_JPEG_LSBs_4;
+reg [7:0] Y12_code_entry;
+reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s;
+reg eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output;
+reg end_of_block_empty;
+
+wire [7:0] code_index = { zrl_2, Y12_bits };
+
+
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ third_8_all_0s <= 0; fourth_8_all_0s <= 0;
+ fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0;
+ eighth_8_all_0s <= 0;
+ end
+ else if (enable_1) begin
+ third_8_all_0s <= Y25_et_zero & Y34_et_zero & Y43_et_zero & Y52_et_zero
+ & Y61_et_zero & Y71_et_zero & Y62_et_zero & Y53_et_zero;
+ fourth_8_all_0s <= Y44_et_zero & Y35_et_zero & Y26_et_zero & Y17_et_zero
+ & Y18_et_zero & Y27_et_zero & Y36_et_zero & Y45_et_zero;
+ fifth_8_all_0s <= Y54_et_zero & Y63_et_zero & Y72_et_zero & Y81_et_zero
+ & Y82_et_zero & Y73_et_zero & Y64_et_zero & Y55_et_zero;
+ sixth_8_all_0s <= Y46_et_zero & Y37_et_zero & Y28_et_zero & Y38_et_zero
+ & Y47_et_zero & Y56_et_zero & Y65_et_zero & Y74_et_zero;
+ seventh_8_all_0s <= Y83_et_zero & Y84_et_zero & Y75_et_zero & Y66_et_zero
+ & Y57_et_zero & Y48_et_zero & Y58_et_zero & Y67_et_zero;
+ eighth_8_all_0s <= Y76_et_zero & Y85_et_zero & Y86_et_zero & Y77_et_zero
+ & Y68_et_zero & Y78_et_zero & Y87_et_zero & Y88_et_zero;
+ end
+end
+
+
+/* end_of_block checks to see if there are any nonzero elements left in the block
+If there aren't any nonzero elements left, then the last bits in the JPEG stream
+will be the end of block code. The purpose of this register is to determine if the
+zero run length code 15-0 should be used or not. It should be used if there are 15 or more
+zeros in a row, followed by a nonzero value. If there are only zeros left in the block,
+then end_of_block will be 1. If there are any nonzero values left in the block, end_of_block
+will be 0. */
+
+always @(posedge clk)
+begin
+ if (rst)
+ end_of_block <= 0;
+ else if (enable)
+ end_of_block <= 0;
+ else if (enable_module & block_counter < 32)
+ end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s
+ & sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s;
+ else if (enable_module & block_counter < 48)
+ end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s
+ & eighth_8_all_0s;
+ else if (enable_module & block_counter <= 64)
+ end_of_block <= seventh_8_all_0s & eighth_8_all_0s;
+ else if (enable_module & block_counter > 64)
+ end_of_block <= 1;
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ block_counter <= 0;
+ end
+ else if (enable) begin
+ block_counter <= 0;
+ end
+ else if (enable_module) begin
+ block_counter <= block_counter + 1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ output_reg_count <= 0;
+ end
+ else if (end_of_block_output) begin
+ output_reg_count <= 0;
+ end
+ else if (enable_6) begin
+ output_reg_count <= output_reg_count + Y11_output_count;
+ end
+ else if (enable_latch_7) begin
+ output_reg_count <= output_reg_count + Y12_oc_1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ old_orc_1 <= 0;
+ end
+ else if (end_of_block_output) begin
+ old_orc_1 <= 0;
+ end
+ else if (enable_module) begin
+ old_orc_1 <= output_reg_count;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ rollover <= 0; rollover_1 <= 0; rollover_2 <= 0;
+ rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0;
+ rollover_6 <= 0; rollover_7 <= 0;
+ old_orc_2 <= 0;
+ orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0;
+ orc_7 <= 0; orc_8 <= 0; data_ready <= 0;
+ end_of_block_output <= 0; end_of_block_empty <= 0;
+ end
+ else if (enable_module) begin
+ rollover <= (old_orc_1 > output_reg_count);
+ rollover_1 <= rollover;
+ rollover_2 <= rollover_1;
+ rollover_3 <= rollover_2;
+ rollover_4 <= rollover_3;
+ rollover_5 <= rollover_4;
+ rollover_6 <= rollover_5;
+ rollover_7 <= rollover_6;
+ old_orc_2 <= old_orc_1;
+ orc_3 <= old_orc_2;
+ orc_4 <= orc_3; orc_5 <= orc_4;
+ orc_6 <= orc_5; orc_7 <= orc_6;
+ orc_8 <= orc_7;
+ data_ready <= rollover_6 | block_counter == 77;
+ end_of_block_output <= block_counter == 77;
+ end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0;
+ end
+end
+
+
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ JPEG_bs_5 <= 0;
+ end
+ else if (enable_module) begin
+ JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31];
+ JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30];
+ JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29];
+ JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28];
+ JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27];
+ JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26];
+ JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25];
+ JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24];
+ JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23];
+ JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22];
+ JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21];
+ JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20];
+ JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19];
+ JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18];
+ JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17];
+ JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16];
+ JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15];
+ JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14];
+ JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13];
+ JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12];
+ JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11];
+ JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10];
+ JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9];
+ JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8];
+ JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7];
+ JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6];
+ JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5];
+ JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4];
+ JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3];
+ JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2];
+ JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1];
+ JPEG_bs_5[0] <= JPEG_bs_4[0];
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0;
+ end
+ else if (enable_module) begin
+ JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3;
+ JPEG_ro_bs_4 <= (Y12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0;
+ Y12_edge_4 <= 0;
+ end
+ else if (enable_module) begin
+ JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2;
+ old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5;
+ JPEG_ro_bs_3 <= (Y12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2;
+ Y12_edge_4 <= (Y12_edge_3 <= 2) ? Y12_edge_3 : Y12_edge_3 - 2;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0;
+ Y12_edge_3 <= 0;
+ end
+ else if (enable_module) begin
+ JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1;
+ old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4;
+ JPEG_ro_bs_2 <= (Y12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1;
+ Y12_edge_3 <= (Y12_edge_2 <= 4) ? Y12_edge_2 : Y12_edge_2 - 4;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0;
+ Y12_edge_2 <= 0;
+ end
+ else if (enable_module) begin
+ JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs;
+ old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3;
+ JPEG_ro_bs_1 <= (Y12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs;
+ Y12_edge_2 <= (Y12_edge_1 <= 8) ? Y12_edge_1 : Y12_edge_1 - 8;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0;
+ Y12_edge_1 <= 0; Y11_JPEG_bits_1 <= 0;
+ end
+ else if (enable_module) begin
+ JPEG_bs <= (old_orc_2 >= 16) ? Y11_JPEG_bits >> 10 : Y11_JPEG_bits << 6;
+ old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2;
+ JPEG_ro_bs <= (Y12_edge <= 16) ? Y11_JPEG_bits_1 << 16 : Y11_JPEG_bits_1;
+ Y12_edge_1 <= (Y12_edge <= 16) ? Y12_edge : Y12_edge - 16;
+ Y11_JPEG_bits_1 <= Y11_JPEG_bits;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_JPEG_bits <= 0; Y12_edge <= 0;
+ end
+ else if (enable_module) begin
+ Y12_JPEG_bits[25] <= (Y12_Huff_shift_1 >= 16) ? Y12_JPEG_LSBs_4[25] : Y12_Huff_2[15];
+ Y12_JPEG_bits[24] <= (Y12_Huff_shift_1 >= 15) ? Y12_JPEG_LSBs_4[24] : Y12_Huff_2[14];
+ Y12_JPEG_bits[23] <= (Y12_Huff_shift_1 >= 14) ? Y12_JPEG_LSBs_4[23] : Y12_Huff_2[13];
+ Y12_JPEG_bits[22] <= (Y12_Huff_shift_1 >= 13) ? Y12_JPEG_LSBs_4[22] : Y12_Huff_2[12];
+ Y12_JPEG_bits[21] <= (Y12_Huff_shift_1 >= 12) ? Y12_JPEG_LSBs_4[21] : Y12_Huff_2[11];
+ Y12_JPEG_bits[20] <= (Y12_Huff_shift_1 >= 11) ? Y12_JPEG_LSBs_4[20] : Y12_Huff_2[10];
+ Y12_JPEG_bits[19] <= (Y12_Huff_shift_1 >= 10) ? Y12_JPEG_LSBs_4[19] : Y12_Huff_2[9];
+ Y12_JPEG_bits[18] <= (Y12_Huff_shift_1 >= 9) ? Y12_JPEG_LSBs_4[18] : Y12_Huff_2[8];
+ Y12_JPEG_bits[17] <= (Y12_Huff_shift_1 >= 8) ? Y12_JPEG_LSBs_4[17] : Y12_Huff_2[7];
+ Y12_JPEG_bits[16] <= (Y12_Huff_shift_1 >= 7) ? Y12_JPEG_LSBs_4[16] : Y12_Huff_2[6];
+ Y12_JPEG_bits[15] <= (Y12_Huff_shift_1 >= 6) ? Y12_JPEG_LSBs_4[15] : Y12_Huff_2[5];
+ Y12_JPEG_bits[14] <= (Y12_Huff_shift_1 >= 5) ? Y12_JPEG_LSBs_4[14] : Y12_Huff_2[4];
+ Y12_JPEG_bits[13] <= (Y12_Huff_shift_1 >= 4) ? Y12_JPEG_LSBs_4[13] : Y12_Huff_2[3];
+ Y12_JPEG_bits[12] <= (Y12_Huff_shift_1 >= 3) ? Y12_JPEG_LSBs_4[12] : Y12_Huff_2[2];
+ Y12_JPEG_bits[11] <= (Y12_Huff_shift_1 >= 2) ? Y12_JPEG_LSBs_4[11] : Y12_Huff_2[1];
+ Y12_JPEG_bits[10] <= (Y12_Huff_shift_1 >= 1) ? Y12_JPEG_LSBs_4[10] : Y12_Huff_2[0];
+ Y12_JPEG_bits[9:0] <= Y12_JPEG_LSBs_4[9:0];
+ Y12_edge <= old_orc_2 + 26; // 26 is the size of Y11_JPEG_bits
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_JPEG_bits <= 0;
+ end
+ else if (enable_7) begin
+ Y11_JPEG_bits[25] <= (Y11_Huff_shift_1 >= 11) ? Y11_JPEG_LSBs_3[21] : Y11_Huff_2[10];
+ Y11_JPEG_bits[24] <= (Y11_Huff_shift_1 >= 10) ? Y11_JPEG_LSBs_3[20] : Y11_Huff_2[9];
+ Y11_JPEG_bits[23] <= (Y11_Huff_shift_1 >= 9) ? Y11_JPEG_LSBs_3[19] : Y11_Huff_2[8];
+ Y11_JPEG_bits[22] <= (Y11_Huff_shift_1 >= 8) ? Y11_JPEG_LSBs_3[18] : Y11_Huff_2[7];
+ Y11_JPEG_bits[21] <= (Y11_Huff_shift_1 >= 7) ? Y11_JPEG_LSBs_3[17] : Y11_Huff_2[6];
+ Y11_JPEG_bits[20] <= (Y11_Huff_shift_1 >= 6) ? Y11_JPEG_LSBs_3[16] : Y11_Huff_2[5];
+ Y11_JPEG_bits[19] <= (Y11_Huff_shift_1 >= 5) ? Y11_JPEG_LSBs_3[15] : Y11_Huff_2[4];
+ Y11_JPEG_bits[18] <= (Y11_Huff_shift_1 >= 4) ? Y11_JPEG_LSBs_3[14] : Y11_Huff_2[3];
+ Y11_JPEG_bits[17] <= (Y11_Huff_shift_1 >= 3) ? Y11_JPEG_LSBs_3[13] : Y11_Huff_2[2];
+ Y11_JPEG_bits[16] <= (Y11_Huff_shift_1 >= 2) ? Y11_JPEG_LSBs_3[12] : Y11_Huff_2[1];
+ Y11_JPEG_bits[15] <= (Y11_Huff_shift_1 >= 1) ? Y11_JPEG_LSBs_3[11] : Y11_Huff_2[0];
+ Y11_JPEG_bits[14:4] <= Y11_JPEG_LSBs_3[10:0];
+ end
+ else if (enable_latch_8) begin
+ Y11_JPEG_bits <= Y12_JPEG_bits;
+ end
+end
+
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_oc_1 <= 0; Y12_JPEG_LSBs_4 <= 0;
+ Y12_Huff_2 <= 0; Y12_Huff_shift_1 <= 0;
+ end
+ else if (enable_module) begin
+ Y12_oc_1 <= (Y12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 :
+ Y12_bits_3 + Y12_Huff_count_1;
+ Y12_JPEG_LSBs_4 <= Y12_JPEG_LSBs_3 << Y12_Huff_shift;
+ Y12_Huff_2 <= Y12_Huff_1;
+ Y12_Huff_shift_1 <= Y12_Huff_shift;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_JPEG_LSBs_3 <= 0; Y11_Huff_2 <= 0;
+ Y11_Huff_shift_1 <= 0;
+ end
+ else if (enable_6) begin
+ Y11_JPEG_LSBs_3 <= Y11_JPEG_LSBs_2 << Y11_Huff_shift;
+ Y11_Huff_2 <= Y11_Huff_1;
+ Y11_Huff_shift_1 <= Y11_Huff_shift;
+ end
+end
+
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_Huff_shift <= 0;
+ Y12_Huff_1 <= 0; Y12_JPEG_LSBs_3 <= 0; Y12_bits_3 <= 0;
+ Y12_Huff_count_1 <= 0; Y12_et_zero_5 <= 0; code_15_0 <= 0;
+ end
+ else if (enable_module) begin
+ Y12_Huff_shift <= 16 - Y12_Huff_count;
+ Y12_Huff_1 <= Y12_Huff;
+ Y12_JPEG_LSBs_3 <= Y12_JPEG_LSBs_2;
+ Y12_bits_3 <= Y12_bits_2;
+ Y12_Huff_count_1 <= Y12_Huff_count;
+ Y12_et_zero_5 <= Y12_et_zero_4;
+ code_15_0 <= zrl_et_15 & !end_of_block;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_output_count <= 0; Y11_JPEG_LSBs_2 <= 0; Y11_Huff_shift <= 0;
+ Y11_Huff_1 <= 0;
+ end
+ else if (enable_5) begin
+ Y11_output_count <= Y11_bits_1 + Y11_Huff_count;
+ Y11_JPEG_LSBs_2 <= Y11_JPEG_LSBs_1 << Y11_amp_shift;
+ Y11_Huff_shift <= 11 - Y11_Huff_count;
+ Y11_Huff_1 <= Y11_Huff;
+ end
+end
+
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_JPEG_LSBs_2 <= 0;
+ Y12_Huff <= 0; Y12_Huff_count <= 0; Y12_bits_2 <= 0;
+ Y12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0;
+ end
+ else if (enable_module) begin
+ Y12_JPEG_LSBs_2 <= Y12_JPEG_LSBs_1 << Y12_amp_shift;
+ Y12_Huff <= Y_AC[Y12_code_entry];
+ Y12_Huff_count <= Y_AC_code_length[Y12_code_entry];
+ Y12_bits_2 <= Y12_bits_1;
+ Y12_et_zero_4 <= Y12_et_zero_3;
+ zrl_et_15 <= zrl_3 == 15;
+ zrl_3 <= zrl_2;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_Huff <= 0; Y11_Huff_count <= 0; Y11_amp_shift <= 0;
+ Y11_JPEG_LSBs_1 <= 0; Y11_bits_1 <= 0;
+ end
+ else if (enable_4) begin
+ Y11_Huff[10:0] <= Y_DC[Y11_bits];
+ Y11_Huff_count <= Y_DC_code_length[Y11_bits];
+ Y11_amp_shift <= 11 - Y11_bits;
+ Y11_JPEG_LSBs_1 <= Y11_JPEG_LSBs;
+ Y11_bits_1 <= Y11_bits;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_code_entry <= 0; Y12_JPEG_LSBs_1 <= 0; Y12_amp_shift <= 0;
+ Y12_bits_1 <= 0; Y12_et_zero_3 <= 0; zrl_2 <= 0;
+ end
+ else if (enable_module) begin
+ Y12_code_entry <= Y_AC_run_code[code_index];
+ Y12_JPEG_LSBs_1 <= Y12_JPEG_LSBs;
+ Y12_amp_shift <= 10 - Y12_bits;
+ Y12_bits_1 <= Y12_bits;
+ Y12_et_zero_3 <= Y12_et_zero_2;
+ zrl_2 <= zrl_1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_bits <= 0; Y11_JPEG_LSBs <= 0;
+ end
+ else if (enable_3) begin
+ Y11_bits <= Y11_msb ? Y11_bits_neg : Y11_bits_pos;
+ Y11_JPEG_LSBs <= Y11_amp[10:0]; // The top bit of Y11_amp is the sign bit
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_bits <= 0; Y12_JPEG_LSBs <= 0; zrl_1 <= 0;
+ Y12_et_zero_2 <= 0;
+ end
+ else if (enable_module) begin
+ Y12_bits <= Y12_msb_1 ? Y12_bits_neg : Y12_bits_pos;
+ Y12_JPEG_LSBs <= Y12_amp[9:0]; // The top bit of Y12_amp is the sign bit
+ zrl_1 <= block_counter == 62 & Y12_et_zero ? 0 : zero_run_length;
+ Y12_et_zero_2 <= Y12_et_zero_1;
+ end
+end
+
+// Y11_amp is the amplitude that will be represented in bits in the
+// JPEG code, following the run length code
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_amp <= 0;
+ end
+ else if (enable_2) begin
+ Y11_amp <= Y11_msb ? Y11_1_neg : Y11_1_pos;
+ end
+end
+
+
+always @(posedge clk)
+begin
+ if (rst)
+ zero_run_length <= 0;
+ else if (enable)
+ zero_run_length <= 0;
+ else if (enable_module)
+ zero_run_length <= Y12_et_zero ? zero_run_length + 1: 0;
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_amp <= 0;
+ Y12_et_zero_1 <= 0; Y12_msb_1 <= 0;
+ end
+ else if (enable_module) begin
+ Y12_amp <= Y12_msb ? Y12_neg : Y12_pos;
+ Y12_et_zero_1 <= Y12_et_zero;
+ Y12_msb_1 <= Y12_msb;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_1_pos <= 0; Y11_1_neg <= 0; Y11_msb <= 0;
+ Y11_previous <= 0;
+ end
+ else if (enable_1) begin
+ Y11_1_pos <= Y11_diff;
+ Y11_1_neg <= Y11_diff - 1;
+ Y11_msb <= Y11_diff[11];
+ Y11_previous <= Y11_1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y12_pos <= 0; Y12_neg <= 0; Y12_msb <= 0; Y12_et_zero <= 0;
+ Y13_pos <= 0; Y13_neg <= 0; Y13_msb <= 0; Y13_et_zero <= 0;
+ Y14_pos <= 0; Y14_neg <= 0; Y14_msb <= 0; Y14_et_zero <= 0;
+ Y15_pos <= 0; Y15_neg <= 0; Y15_msb <= 0; Y15_et_zero <= 0;
+ Y16_pos <= 0; Y16_neg <= 0; Y16_msb <= 0; Y16_et_zero <= 0;
+ Y17_pos <= 0; Y17_neg <= 0; Y17_msb <= 0; Y17_et_zero <= 0;
+ Y18_pos <= 0; Y18_neg <= 0; Y18_msb <= 0; Y18_et_zero <= 0;
+ Y21_pos <= 0; Y21_neg <= 0; Y21_msb <= 0; Y21_et_zero <= 0;
+ Y22_pos <= 0; Y22_neg <= 0; Y22_msb <= 0; Y22_et_zero <= 0;
+ Y23_pos <= 0; Y23_neg <= 0; Y23_msb <= 0; Y23_et_zero <= 0;
+ Y24_pos <= 0; Y24_neg <= 0; Y24_msb <= 0; Y24_et_zero <= 0;
+ Y25_pos <= 0; Y25_neg <= 0; Y25_msb <= 0; Y25_et_zero <= 0;
+ Y26_pos <= 0; Y26_neg <= 0; Y26_msb <= 0; Y26_et_zero <= 0;
+ Y27_pos <= 0; Y27_neg <= 0; Y27_msb <= 0; Y27_et_zero <= 0;
+ Y28_pos <= 0; Y28_neg <= 0; Y28_msb <= 0; Y28_et_zero <= 0;
+ Y31_pos <= 0; Y31_neg <= 0; Y31_msb <= 0; Y31_et_zero <= 0;
+ Y32_pos <= 0; Y32_neg <= 0; Y32_msb <= 0; Y32_et_zero <= 0;
+ Y33_pos <= 0; Y33_neg <= 0; Y33_msb <= 0; Y33_et_zero <= 0;
+ Y34_pos <= 0; Y34_neg <= 0; Y34_msb <= 0; Y34_et_zero <= 0;
+ Y35_pos <= 0; Y35_neg <= 0; Y35_msb <= 0; Y35_et_zero <= 0;
+ Y36_pos <= 0; Y36_neg <= 0; Y36_msb <= 0; Y36_et_zero <= 0;
+ Y37_pos <= 0; Y37_neg <= 0; Y37_msb <= 0; Y37_et_zero <= 0;
+ Y38_pos <= 0; Y38_neg <= 0; Y38_msb <= 0; Y38_et_zero <= 0;
+ Y41_pos <= 0; Y41_neg <= 0; Y41_msb <= 0; Y41_et_zero <= 0;
+ Y42_pos <= 0; Y42_neg <= 0; Y42_msb <= 0; Y42_et_zero <= 0;
+ Y43_pos <= 0; Y43_neg <= 0; Y43_msb <= 0; Y43_et_zero <= 0;
+ Y44_pos <= 0; Y44_neg <= 0; Y44_msb <= 0; Y44_et_zero <= 0;
+ Y45_pos <= 0; Y45_neg <= 0; Y45_msb <= 0; Y45_et_zero <= 0;
+ Y46_pos <= 0; Y46_neg <= 0; Y46_msb <= 0; Y46_et_zero <= 0;
+ Y47_pos <= 0; Y47_neg <= 0; Y47_msb <= 0; Y47_et_zero <= 0;
+ Y48_pos <= 0; Y48_neg <= 0; Y48_msb <= 0; Y48_et_zero <= 0;
+ Y51_pos <= 0; Y51_neg <= 0; Y51_msb <= 0; Y51_et_zero <= 0;
+ Y52_pos <= 0; Y52_neg <= 0; Y52_msb <= 0; Y52_et_zero <= 0;
+ Y53_pos <= 0; Y53_neg <= 0; Y53_msb <= 0; Y53_et_zero <= 0;
+ Y54_pos <= 0; Y54_neg <= 0; Y54_msb <= 0; Y54_et_zero <= 0;
+ Y55_pos <= 0; Y55_neg <= 0; Y55_msb <= 0; Y55_et_zero <= 0;
+ Y56_pos <= 0; Y56_neg <= 0; Y56_msb <= 0; Y56_et_zero <= 0;
+ Y57_pos <= 0; Y57_neg <= 0; Y57_msb <= 0; Y57_et_zero <= 0;
+ Y58_pos <= 0; Y58_neg <= 0; Y58_msb <= 0; Y58_et_zero <= 0;
+ Y61_pos <= 0; Y61_neg <= 0; Y61_msb <= 0; Y61_et_zero <= 0;
+ Y62_pos <= 0; Y62_neg <= 0; Y62_msb <= 0; Y62_et_zero <= 0;
+ Y63_pos <= 0; Y63_neg <= 0; Y63_msb <= 0; Y63_et_zero <= 0;
+ Y64_pos <= 0; Y64_neg <= 0; Y64_msb <= 0; Y64_et_zero <= 0;
+ Y65_pos <= 0; Y65_neg <= 0; Y65_msb <= 0; Y65_et_zero <= 0;
+ Y66_pos <= 0; Y66_neg <= 0; Y66_msb <= 0; Y66_et_zero <= 0;
+ Y67_pos <= 0; Y67_neg <= 0; Y67_msb <= 0; Y67_et_zero <= 0;
+ Y68_pos <= 0; Y68_neg <= 0; Y68_msb <= 0; Y68_et_zero <= 0;
+ Y71_pos <= 0; Y71_neg <= 0; Y71_msb <= 0; Y71_et_zero <= 0;
+ Y72_pos <= 0; Y72_neg <= 0; Y72_msb <= 0; Y72_et_zero <= 0;
+ Y73_pos <= 0; Y73_neg <= 0; Y73_msb <= 0; Y73_et_zero <= 0;
+ Y74_pos <= 0; Y74_neg <= 0; Y74_msb <= 0; Y74_et_zero <= 0;
+ Y75_pos <= 0; Y75_neg <= 0; Y75_msb <= 0; Y75_et_zero <= 0;
+ Y76_pos <= 0; Y76_neg <= 0; Y76_msb <= 0; Y76_et_zero <= 0;
+ Y77_pos <= 0; Y77_neg <= 0; Y77_msb <= 0; Y77_et_zero <= 0;
+ Y78_pos <= 0; Y78_neg <= 0; Y78_msb <= 0; Y78_et_zero <= 0;
+ Y81_pos <= 0; Y81_neg <= 0; Y81_msb <= 0; Y81_et_zero <= 0;
+ Y82_pos <= 0; Y82_neg <= 0; Y82_msb <= 0; Y82_et_zero <= 0;
+ Y83_pos <= 0; Y83_neg <= 0; Y83_msb <= 0; Y83_et_zero <= 0;
+ Y84_pos <= 0; Y84_neg <= 0; Y84_msb <= 0; Y84_et_zero <= 0;
+ Y85_pos <= 0; Y85_neg <= 0; Y85_msb <= 0; Y85_et_zero <= 0;
+ Y86_pos <= 0; Y86_neg <= 0; Y86_msb <= 0; Y86_et_zero <= 0;
+ Y87_pos <= 0; Y87_neg <= 0; Y87_msb <= 0; Y87_et_zero <= 0;
+ Y88_pos <= 0; Y88_neg <= 0; Y88_msb <= 0; Y88_et_zero <= 0;
+ end
+ else if (enable) begin
+ Y12_pos <= Y12;
+ Y12_neg <= Y12 - 1;
+ Y12_msb <= Y12[10];
+ Y12_et_zero <= !(|Y12);
+ Y13_pos <= Y13;
+ Y13_neg <= Y13 - 1;
+ Y13_msb <= Y13[10];
+ Y13_et_zero <= !(|Y13);
+ Y14_pos <= Y14;
+ Y14_neg <= Y14 - 1;
+ Y14_msb <= Y14[10];
+ Y14_et_zero <= !(|Y14);
+ Y15_pos <= Y15;
+ Y15_neg <= Y15 - 1;
+ Y15_msb <= Y15[10];
+ Y15_et_zero <= !(|Y15);
+ Y16_pos <= Y16;
+ Y16_neg <= Y16 - 1;
+ Y16_msb <= Y16[10];
+ Y16_et_zero <= !(|Y16);
+ Y17_pos <= Y17;
+ Y17_neg <= Y17 - 1;
+ Y17_msb <= Y17[10];
+ Y17_et_zero <= !(|Y17);
+ Y18_pos <= Y18;
+ Y18_neg <= Y18 - 1;
+ Y18_msb <= Y18[10];
+ Y18_et_zero <= !(|Y18);
+ Y21_pos <= Y21;
+ Y21_neg <= Y21 - 1;
+ Y21_msb <= Y21[10];
+ Y21_et_zero <= !(|Y21);
+ Y22_pos <= Y22;
+ Y22_neg <= Y22 - 1;
+ Y22_msb <= Y22[10];
+ Y22_et_zero <= !(|Y22);
+ Y23_pos <= Y23;
+ Y23_neg <= Y23 - 1;
+ Y23_msb <= Y23[10];
+ Y23_et_zero <= !(|Y23);
+ Y24_pos <= Y24;
+ Y24_neg <= Y24 - 1;
+ Y24_msb <= Y24[10];
+ Y24_et_zero <= !(|Y24);
+ Y25_pos <= Y25;
+ Y25_neg <= Y25 - 1;
+ Y25_msb <= Y25[10];
+ Y25_et_zero <= !(|Y25);
+ Y26_pos <= Y26;
+ Y26_neg <= Y26 - 1;
+ Y26_msb <= Y26[10];
+ Y26_et_zero <= !(|Y26);
+ Y27_pos <= Y27;
+ Y27_neg <= Y27 - 1;
+ Y27_msb <= Y27[10];
+ Y27_et_zero <= !(|Y27);
+ Y28_pos <= Y28;
+ Y28_neg <= Y28 - 1;
+ Y28_msb <= Y28[10];
+ Y28_et_zero <= !(|Y28);
+ Y31_pos <= Y31;
+ Y31_neg <= Y31 - 1;
+ Y31_msb <= Y31[10];
+ Y31_et_zero <= !(|Y31);
+ Y32_pos <= Y32;
+ Y32_neg <= Y32 - 1;
+ Y32_msb <= Y32[10];
+ Y32_et_zero <= !(|Y32);
+ Y33_pos <= Y33;
+ Y33_neg <= Y33 - 1;
+ Y33_msb <= Y33[10];
+ Y33_et_zero <= !(|Y33);
+ Y34_pos <= Y34;
+ Y34_neg <= Y34 - 1;
+ Y34_msb <= Y34[10];
+ Y34_et_zero <= !(|Y34);
+ Y35_pos <= Y35;
+ Y35_neg <= Y35 - 1;
+ Y35_msb <= Y35[10];
+ Y35_et_zero <= !(|Y35);
+ Y36_pos <= Y36;
+ Y36_neg <= Y36 - 1;
+ Y36_msb <= Y36[10];
+ Y36_et_zero <= !(|Y36);
+ Y37_pos <= Y37;
+ Y37_neg <= Y37 - 1;
+ Y37_msb <= Y37[10];
+ Y37_et_zero <= !(|Y37);
+ Y38_pos <= Y38;
+ Y38_neg <= Y38 - 1;
+ Y38_msb <= Y38[10];
+ Y38_et_zero <= !(|Y38);
+ Y41_pos <= Y41;
+ Y41_neg <= Y41 - 1;
+ Y41_msb <= Y41[10];
+ Y41_et_zero <= !(|Y41);
+ Y42_pos <= Y42;
+ Y42_neg <= Y42 - 1;
+ Y42_msb <= Y42[10];
+ Y42_et_zero <= !(|Y42);
+ Y43_pos <= Y43;
+ Y43_neg <= Y43 - 1;
+ Y43_msb <= Y43[10];
+ Y43_et_zero <= !(|Y43);
+ Y44_pos <= Y44;
+ Y44_neg <= Y44 - 1;
+ Y44_msb <= Y44[10];
+ Y44_et_zero <= !(|Y44);
+ Y45_pos <= Y45;
+ Y45_neg <= Y45 - 1;
+ Y45_msb <= Y45[10];
+ Y45_et_zero <= !(|Y45);
+ Y46_pos <= Y46;
+ Y46_neg <= Y46 - 1;
+ Y46_msb <= Y46[10];
+ Y46_et_zero <= !(|Y46);
+ Y47_pos <= Y47;
+ Y47_neg <= Y47 - 1;
+ Y47_msb <= Y47[10];
+ Y47_et_zero <= !(|Y47);
+ Y48_pos <= Y48;
+ Y48_neg <= Y48 - 1;
+ Y48_msb <= Y48[10];
+ Y48_et_zero <= !(|Y48);
+ Y51_pos <= Y51;
+ Y51_neg <= Y51 - 1;
+ Y51_msb <= Y51[10];
+ Y51_et_zero <= !(|Y51);
+ Y52_pos <= Y52;
+ Y52_neg <= Y52 - 1;
+ Y52_msb <= Y52[10];
+ Y52_et_zero <= !(|Y52);
+ Y53_pos <= Y53;
+ Y53_neg <= Y53 - 1;
+ Y53_msb <= Y53[10];
+ Y53_et_zero <= !(|Y53);
+ Y54_pos <= Y54;
+ Y54_neg <= Y54 - 1;
+ Y54_msb <= Y54[10];
+ Y54_et_zero <= !(|Y54);
+ Y55_pos <= Y55;
+ Y55_neg <= Y55 - 1;
+ Y55_msb <= Y55[10];
+ Y55_et_zero <= !(|Y55);
+ Y56_pos <= Y56;
+ Y56_neg <= Y56 - 1;
+ Y56_msb <= Y56[10];
+ Y56_et_zero <= !(|Y56);
+ Y57_pos <= Y57;
+ Y57_neg <= Y57 - 1;
+ Y57_msb <= Y57[10];
+ Y57_et_zero <= !(|Y57);
+ Y58_pos <= Y58;
+ Y58_neg <= Y58 - 1;
+ Y58_msb <= Y58[10];
+ Y58_et_zero <= !(|Y58);
+ Y61_pos <= Y61;
+ Y61_neg <= Y61 - 1;
+ Y61_msb <= Y61[10];
+ Y61_et_zero <= !(|Y61);
+ Y62_pos <= Y62;
+ Y62_neg <= Y62 - 1;
+ Y62_msb <= Y62[10];
+ Y62_et_zero <= !(|Y62);
+ Y63_pos <= Y63;
+ Y63_neg <= Y63 - 1;
+ Y63_msb <= Y63[10];
+ Y63_et_zero <= !(|Y63);
+ Y64_pos <= Y64;
+ Y64_neg <= Y64 - 1;
+ Y64_msb <= Y64[10];
+ Y64_et_zero <= !(|Y64);
+ Y65_pos <= Y65;
+ Y65_neg <= Y65 - 1;
+ Y65_msb <= Y65[10];
+ Y65_et_zero <= !(|Y65);
+ Y66_pos <= Y66;
+ Y66_neg <= Y66 - 1;
+ Y66_msb <= Y66[10];
+ Y66_et_zero <= !(|Y66);
+ Y67_pos <= Y67;
+ Y67_neg <= Y67 - 1;
+ Y67_msb <= Y67[10];
+ Y67_et_zero <= !(|Y67);
+ Y68_pos <= Y68;
+ Y68_neg <= Y68 - 1;
+ Y68_msb <= Y68[10];
+ Y68_et_zero <= !(|Y68);
+ Y71_pos <= Y71;
+ Y71_neg <= Y71 - 1;
+ Y71_msb <= Y71[10];
+ Y71_et_zero <= !(|Y71);
+ Y72_pos <= Y72;
+ Y72_neg <= Y72 - 1;
+ Y72_msb <= Y72[10];
+ Y72_et_zero <= !(|Y72);
+ Y73_pos <= Y73;
+ Y73_neg <= Y73 - 1;
+ Y73_msb <= Y73[10];
+ Y73_et_zero <= !(|Y73);
+ Y74_pos <= Y74;
+ Y74_neg <= Y74 - 1;
+ Y74_msb <= Y74[10];
+ Y74_et_zero <= !(|Y74);
+ Y75_pos <= Y75;
+ Y75_neg <= Y75 - 1;
+ Y75_msb <= Y75[10];
+ Y75_et_zero <= !(|Y75);
+ Y76_pos <= Y76;
+ Y76_neg <= Y76 - 1;
+ Y76_msb <= Y76[10];
+ Y76_et_zero <= !(|Y76);
+ Y77_pos <= Y77;
+ Y77_neg <= Y77 - 1;
+ Y77_msb <= Y77[10];
+ Y77_et_zero <= !(|Y77);
+ Y78_pos <= Y78;
+ Y78_neg <= Y78 - 1;
+ Y78_msb <= Y78[10];
+ Y78_et_zero <= !(|Y78);
+ Y81_pos <= Y81;
+ Y81_neg <= Y81 - 1;
+ Y81_msb <= Y81[10];
+ Y81_et_zero <= !(|Y81);
+ Y82_pos <= Y82;
+ Y82_neg <= Y82 - 1;
+ Y82_msb <= Y82[10];
+ Y82_et_zero <= !(|Y82);
+ Y83_pos <= Y83;
+ Y83_neg <= Y83 - 1;
+ Y83_msb <= Y83[10];
+ Y83_et_zero <= !(|Y83);
+ Y84_pos <= Y84;
+ Y84_neg <= Y84 - 1;
+ Y84_msb <= Y84[10];
+ Y84_et_zero <= !(|Y84);
+ Y85_pos <= Y85;
+ Y85_neg <= Y85 - 1;
+ Y85_msb <= Y85[10];
+ Y85_et_zero <= !(|Y85);
+ Y86_pos <= Y86;
+ Y86_neg <= Y86 - 1;
+ Y86_msb <= Y86[10];
+ Y86_et_zero <= !(|Y86);
+ Y87_pos <= Y87;
+ Y87_neg <= Y87 - 1;
+ Y87_msb <= Y87[10];
+ Y87_et_zero <= !(|Y87);
+ Y88_pos <= Y88;
+ Y88_neg <= Y88 - 1;
+ Y88_msb <= Y88[10];
+ Y88_et_zero <= !(|Y88);
+ end
+ else if (enable_module) begin
+ Y12_pos <= Y21_pos;
+ Y12_neg <= Y21_neg;
+ Y12_msb <= Y21_msb;
+ Y12_et_zero <= Y21_et_zero;
+ Y21_pos <= Y31_pos;
+ Y21_neg <= Y31_neg;
+ Y21_msb <= Y31_msb;
+ Y21_et_zero <= Y31_et_zero;
+ Y31_pos <= Y22_pos;
+ Y31_neg <= Y22_neg;
+ Y31_msb <= Y22_msb;
+ Y31_et_zero <= Y22_et_zero;
+ Y22_pos <= Y13_pos;
+ Y22_neg <= Y13_neg;
+ Y22_msb <= Y13_msb;
+ Y22_et_zero <= Y13_et_zero;
+ Y13_pos <= Y14_pos;
+ Y13_neg <= Y14_neg;
+ Y13_msb <= Y14_msb;
+ Y13_et_zero <= Y14_et_zero;
+ Y14_pos <= Y23_pos;
+ Y14_neg <= Y23_neg;
+ Y14_msb <= Y23_msb;
+ Y14_et_zero <= Y23_et_zero;
+ Y23_pos <= Y32_pos;
+ Y23_neg <= Y32_neg;
+ Y23_msb <= Y32_msb;
+ Y23_et_zero <= Y32_et_zero;
+ Y32_pos <= Y41_pos;
+ Y32_neg <= Y41_neg;
+ Y32_msb <= Y41_msb;
+ Y32_et_zero <= Y41_et_zero;
+ Y41_pos <= Y51_pos;
+ Y41_neg <= Y51_neg;
+ Y41_msb <= Y51_msb;
+ Y41_et_zero <= Y51_et_zero;
+ Y51_pos <= Y42_pos;
+ Y51_neg <= Y42_neg;
+ Y51_msb <= Y42_msb;
+ Y51_et_zero <= Y42_et_zero;
+ Y42_pos <= Y33_pos;
+ Y42_neg <= Y33_neg;
+ Y42_msb <= Y33_msb;
+ Y42_et_zero <= Y33_et_zero;
+ Y33_pos <= Y24_pos;
+ Y33_neg <= Y24_neg;
+ Y33_msb <= Y24_msb;
+ Y33_et_zero <= Y24_et_zero;
+ Y24_pos <= Y15_pos;
+ Y24_neg <= Y15_neg;
+ Y24_msb <= Y15_msb;
+ Y24_et_zero <= Y15_et_zero;
+ Y15_pos <= Y16_pos;
+ Y15_neg <= Y16_neg;
+ Y15_msb <= Y16_msb;
+ Y15_et_zero <= Y16_et_zero;
+ Y16_pos <= Y25_pos;
+ Y16_neg <= Y25_neg;
+ Y16_msb <= Y25_msb;
+ Y16_et_zero <= Y25_et_zero;
+ Y25_pos <= Y34_pos;
+ Y25_neg <= Y34_neg;
+ Y25_msb <= Y34_msb;
+ Y25_et_zero <= Y34_et_zero;
+ Y34_pos <= Y43_pos;
+ Y34_neg <= Y43_neg;
+ Y34_msb <= Y43_msb;
+ Y34_et_zero <= Y43_et_zero;
+ Y43_pos <= Y52_pos;
+ Y43_neg <= Y52_neg;
+ Y43_msb <= Y52_msb;
+ Y43_et_zero <= Y52_et_zero;
+ Y52_pos <= Y61_pos;
+ Y52_neg <= Y61_neg;
+ Y52_msb <= Y61_msb;
+ Y52_et_zero <= Y61_et_zero;
+ Y61_pos <= Y71_pos;
+ Y61_neg <= Y71_neg;
+ Y61_msb <= Y71_msb;
+ Y61_et_zero <= Y71_et_zero;
+ Y71_pos <= Y62_pos;
+ Y71_neg <= Y62_neg;
+ Y71_msb <= Y62_msb;
+ Y71_et_zero <= Y62_et_zero;
+ Y62_pos <= Y53_pos;
+ Y62_neg <= Y53_neg;
+ Y62_msb <= Y53_msb;
+ Y62_et_zero <= Y53_et_zero;
+ Y53_pos <= Y44_pos;
+ Y53_neg <= Y44_neg;
+ Y53_msb <= Y44_msb;
+ Y53_et_zero <= Y44_et_zero;
+ Y44_pos <= Y35_pos;
+ Y44_neg <= Y35_neg;
+ Y44_msb <= Y35_msb;
+ Y44_et_zero <= Y35_et_zero;
+ Y35_pos <= Y26_pos;
+ Y35_neg <= Y26_neg;
+ Y35_msb <= Y26_msb;
+ Y35_et_zero <= Y26_et_zero;
+ Y26_pos <= Y17_pos;
+ Y26_neg <= Y17_neg;
+ Y26_msb <= Y17_msb;
+ Y26_et_zero <= Y17_et_zero;
+ Y17_pos <= Y18_pos;
+ Y17_neg <= Y18_neg;
+ Y17_msb <= Y18_msb;
+ Y17_et_zero <= Y18_et_zero;
+ Y18_pos <= Y27_pos;
+ Y18_neg <= Y27_neg;
+ Y18_msb <= Y27_msb;
+ Y18_et_zero <= Y27_et_zero;
+ Y27_pos <= Y36_pos;
+ Y27_neg <= Y36_neg;
+ Y27_msb <= Y36_msb;
+ Y27_et_zero <= Y36_et_zero;
+ Y36_pos <= Y45_pos;
+ Y36_neg <= Y45_neg;
+ Y36_msb <= Y45_msb;
+ Y36_et_zero <= Y45_et_zero;
+ Y45_pos <= Y54_pos;
+ Y45_neg <= Y54_neg;
+ Y45_msb <= Y54_msb;
+ Y45_et_zero <= Y54_et_zero;
+ Y54_pos <= Y63_pos;
+ Y54_neg <= Y63_neg;
+ Y54_msb <= Y63_msb;
+ Y54_et_zero <= Y63_et_zero;
+ Y63_pos <= Y72_pos;
+ Y63_neg <= Y72_neg;
+ Y63_msb <= Y72_msb;
+ Y63_et_zero <= Y72_et_zero;
+ Y72_pos <= Y81_pos;
+ Y72_neg <= Y81_neg;
+ Y72_msb <= Y81_msb;
+ Y72_et_zero <= Y81_et_zero;
+ Y81_pos <= Y82_pos;
+ Y81_neg <= Y82_neg;
+ Y81_msb <= Y82_msb;
+ Y81_et_zero <= Y82_et_zero;
+ Y82_pos <= Y73_pos;
+ Y82_neg <= Y73_neg;
+ Y82_msb <= Y73_msb;
+ Y82_et_zero <= Y73_et_zero;
+ Y73_pos <= Y64_pos;
+ Y73_neg <= Y64_neg;
+ Y73_msb <= Y64_msb;
+ Y73_et_zero <= Y64_et_zero;
+ Y64_pos <= Y55_pos;
+ Y64_neg <= Y55_neg;
+ Y64_msb <= Y55_msb;
+ Y64_et_zero <= Y55_et_zero;
+ Y55_pos <= Y46_pos;
+ Y55_neg <= Y46_neg;
+ Y55_msb <= Y46_msb;
+ Y55_et_zero <= Y46_et_zero;
+ Y46_pos <= Y37_pos;
+ Y46_neg <= Y37_neg;
+ Y46_msb <= Y37_msb;
+ Y46_et_zero <= Y37_et_zero;
+ Y37_pos <= Y28_pos;
+ Y37_neg <= Y28_neg;
+ Y37_msb <= Y28_msb;
+ Y37_et_zero <= Y28_et_zero;
+ Y28_pos <= Y38_pos;
+ Y28_neg <= Y38_neg;
+ Y28_msb <= Y38_msb;
+ Y28_et_zero <= Y38_et_zero;
+ Y38_pos <= Y47_pos;
+ Y38_neg <= Y47_neg;
+ Y38_msb <= Y47_msb;
+ Y38_et_zero <= Y47_et_zero;
+ Y47_pos <= Y56_pos;
+ Y47_neg <= Y56_neg;
+ Y47_msb <= Y56_msb;
+ Y47_et_zero <= Y56_et_zero;
+ Y56_pos <= Y65_pos;
+ Y56_neg <= Y65_neg;
+ Y56_msb <= Y65_msb;
+ Y56_et_zero <= Y65_et_zero;
+ Y65_pos <= Y74_pos;
+ Y65_neg <= Y74_neg;
+ Y65_msb <= Y74_msb;
+ Y65_et_zero <= Y74_et_zero;
+ Y74_pos <= Y83_pos;
+ Y74_neg <= Y83_neg;
+ Y74_msb <= Y83_msb;
+ Y74_et_zero <= Y83_et_zero;
+ Y83_pos <= Y84_pos;
+ Y83_neg <= Y84_neg;
+ Y83_msb <= Y84_msb;
+ Y83_et_zero <= Y84_et_zero;
+ Y84_pos <= Y75_pos;
+ Y84_neg <= Y75_neg;
+ Y84_msb <= Y75_msb;
+ Y84_et_zero <= Y75_et_zero;
+ Y75_pos <= Y66_pos;
+ Y75_neg <= Y66_neg;
+ Y75_msb <= Y66_msb;
+ Y75_et_zero <= Y66_et_zero;
+ Y66_pos <= Y57_pos;
+ Y66_neg <= Y57_neg;
+ Y66_msb <= Y57_msb;
+ Y66_et_zero <= Y57_et_zero;
+ Y57_pos <= Y48_pos;
+ Y57_neg <= Y48_neg;
+ Y57_msb <= Y48_msb;
+ Y57_et_zero <= Y48_et_zero;
+ Y48_pos <= Y58_pos;
+ Y48_neg <= Y58_neg;
+ Y48_msb <= Y58_msb;
+ Y48_et_zero <= Y58_et_zero;
+ Y58_pos <= Y67_pos;
+ Y58_neg <= Y67_neg;
+ Y58_msb <= Y67_msb;
+ Y58_et_zero <= Y67_et_zero;
+ Y67_pos <= Y76_pos;
+ Y67_neg <= Y76_neg;
+ Y67_msb <= Y76_msb;
+ Y67_et_zero <= Y76_et_zero;
+ Y76_pos <= Y85_pos;
+ Y76_neg <= Y85_neg;
+ Y76_msb <= Y85_msb;
+ Y76_et_zero <= Y85_et_zero;
+ Y85_pos <= Y86_pos;
+ Y85_neg <= Y86_neg;
+ Y85_msb <= Y86_msb;
+ Y85_et_zero <= Y86_et_zero;
+ Y86_pos <= Y77_pos;
+ Y86_neg <= Y77_neg;
+ Y86_msb <= Y77_msb;
+ Y86_et_zero <= Y77_et_zero;
+ Y77_pos <= Y68_pos;
+ Y77_neg <= Y68_neg;
+ Y77_msb <= Y68_msb;
+ Y77_et_zero <= Y68_et_zero;
+ Y68_pos <= Y78_pos;
+ Y68_neg <= Y78_neg;
+ Y68_msb <= Y78_msb;
+ Y68_et_zero <= Y78_et_zero;
+ Y78_pos <= Y87_pos;
+ Y78_neg <= Y87_neg;
+ Y78_msb <= Y87_msb;
+ Y78_et_zero <= Y87_et_zero;
+ Y87_pos <= Y88_pos;
+ Y87_neg <= Y88_neg;
+ Y87_msb <= Y88_msb;
+ Y87_et_zero <= Y88_et_zero;
+ Y88_pos <= 0;
+ Y88_neg <= 0;
+ Y88_msb <= 0;
+ Y88_et_zero <= 1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ Y11_diff <= 0; Y11_1 <= 0;
+ end
+ else if (enable) begin // Need to sign extend Y11 to 12 bits
+ Y11_diff <= {Y11[10], Y11} - Y11_previous;
+ Y11_1 <= Y11[10] ? { 1'b1, Y11 } : { 1'b0, Y11 };
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ Y11_bits_pos <= 0;
+ else if (Y11_1_pos[10] == 1)
+ Y11_bits_pos <= 11;
+ else if (Y11_1_pos[9] == 1)
+ Y11_bits_pos <= 10;
+ else if (Y11_1_pos[8] == 1)
+ Y11_bits_pos <= 9;
+ else if (Y11_1_pos[7] == 1)
+ Y11_bits_pos <= 8;
+ else if (Y11_1_pos[6] == 1)
+ Y11_bits_pos <= 7;
+ else if (Y11_1_pos[5] == 1)
+ Y11_bits_pos <= 6;
+ else if (Y11_1_pos[4] == 1)
+ Y11_bits_pos <= 5;
+ else if (Y11_1_pos[3] == 1)
+ Y11_bits_pos <= 4;
+ else if (Y11_1_pos[2] == 1)
+ Y11_bits_pos <= 3;
+ else if (Y11_1_pos[1] == 1)
+ Y11_bits_pos <= 2;
+ else if (Y11_1_pos[0] == 1)
+ Y11_bits_pos <= 1;
+ else
+ Y11_bits_pos <= 0;
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ Y11_bits_neg <= 0;
+ else if (Y11_1_neg[10] == 0)
+ Y11_bits_neg <= 11;
+ else if (Y11_1_neg[9] == 0)
+ Y11_bits_neg <= 10;
+ else if (Y11_1_neg[8] == 0)
+ Y11_bits_neg <= 9;
+ else if (Y11_1_neg[7] == 0)
+ Y11_bits_neg <= 8;
+ else if (Y11_1_neg[6] == 0)
+ Y11_bits_neg <= 7;
+ else if (Y11_1_neg[5] == 0)
+ Y11_bits_neg <= 6;
+ else if (Y11_1_neg[4] == 0)
+ Y11_bits_neg <= 5;
+ else if (Y11_1_neg[3] == 0)
+ Y11_bits_neg <= 4;
+ else if (Y11_1_neg[2] == 0)
+ Y11_bits_neg <= 3;
+ else if (Y11_1_neg[1] == 0)
+ Y11_bits_neg <= 2;
+ else if (Y11_1_neg[0] == 0)
+ Y11_bits_neg <= 1;
+ else
+ Y11_bits_neg <= 0;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst)
+ Y12_bits_pos <= 0;
+ else if (Y12_pos[9] == 1)
+ Y12_bits_pos <= 10;
+ else if (Y12_pos[8] == 1)
+ Y12_bits_pos <= 9;
+ else if (Y12_pos[7] == 1)
+ Y12_bits_pos <= 8;
+ else if (Y12_pos[6] == 1)
+ Y12_bits_pos <= 7;
+ else if (Y12_pos[5] == 1)
+ Y12_bits_pos <= 6;
+ else if (Y12_pos[4] == 1)
+ Y12_bits_pos <= 5;
+ else if (Y12_pos[3] == 1)
+ Y12_bits_pos <= 4;
+ else if (Y12_pos[2] == 1)
+ Y12_bits_pos <= 3;
+ else if (Y12_pos[1] == 1)
+ Y12_bits_pos <= 2;
+ else if (Y12_pos[0] == 1)
+ Y12_bits_pos <= 1;
+ else
+ Y12_bits_pos <= 0;
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ Y12_bits_neg <= 0;
+ else if (Y12_neg[9] == 0)
+ Y12_bits_neg <= 10;
+ else if (Y12_neg[8] == 0)
+ Y12_bits_neg <= 9;
+ else if (Y12_neg[7] == 0)
+ Y12_bits_neg <= 8;
+ else if (Y12_neg[6] == 0)
+ Y12_bits_neg <= 7;
+ else if (Y12_neg[5] == 0)
+ Y12_bits_neg <= 6;
+ else if (Y12_neg[4] == 0)
+ Y12_bits_neg <= 5;
+ else if (Y12_neg[3] == 0)
+ Y12_bits_neg <= 4;
+ else if (Y12_neg[2] == 0)
+ Y12_bits_neg <= 3;
+ else if (Y12_neg[1] == 0)
+ Y12_bits_neg <= 2;
+ else if (Y12_neg[0] == 0)
+ Y12_bits_neg <= 1;
+ else
+ Y12_bits_neg <= 0;
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ enable_module <= 0;
+ end
+ else if (enable) begin
+ enable_module <= 1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ enable_latch_7 <= 0;
+ end
+ else if (block_counter == 68) begin
+ enable_latch_7 <= 0;
+ end
+ else if (enable_6) begin
+ enable_latch_7 <= 1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ enable_latch_8 <= 0;
+ end
+ else if (enable_7) begin
+ enable_latch_8 <= 1;
+ end
+end
+
+always @(posedge clk)
+begin
+ if (rst) begin
+ enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
+ enable_4 <= 0; enable_5 <= 0; enable_6 <= 0;
+ enable_7 <= 0; enable_8 <= 0; enable_9 <= 0;
+ enable_10 <= 0; enable_11 <= 0; enable_12 <= 0;
+ enable_13 <= 0;
+ end
+ else begin
+ enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2;
+ enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5;
+ enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8;
+ enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11;
+ enable_13 <= enable_12;
+ end
+end
+
+/* These Y DC and AC code lengths, run lengths, and bit codes
+were created from the Huffman table entries in the JPEG file header.
+For different Huffman tables for different images, these values
+below will need to be changed. I created a matlab file to automatically
+create these entries from the already encoded JPEG image. This matlab program
+won't be any help if you're starting from scratch with a .tif or other
+raw image file format. The values below come from a Huffman table, they
+do not actually create the Huffman table based on the probabilities of
+each code created from the image data. You will need another program to
+create the optimal Huffman table, or you can go with a generic Huffman table,
+which will have slightly less than the best compression.*/
+
+
+always @(posedge clk)
+begin
+ Y_DC_code_length[0] <= 2;
+Y_DC_code_length[1] <= 2;
+Y_DC_code_length[2] <= 2;
+Y_DC_code_length[3] <= 3;
+Y_DC_code_length[4] <= 4;
+Y_DC_code_length[5] <= 5;
+Y_DC_code_length[6] <= 6;
+Y_DC_code_length[7] <= 7;
+Y_DC_code_length[8] <= 8;
+Y_DC_code_length[9] <= 9;
+Y_DC_code_length[10] <= 10;
+Y_DC_code_length[11] <= 11;
+Y_DC[0] <= 11'b00000000000;
+Y_DC[1] <= 11'b01000000000;
+Y_DC[2] <= 11'b10000000000;
+Y_DC[3] <= 11'b11000000000;
+Y_DC[4] <= 11'b11100000000;
+Y_DC[5] <= 11'b11110000000;
+Y_DC[6] <= 11'b11111000000;
+Y_DC[7] <= 11'b11111100000;
+Y_DC[8] <= 11'b11111110000;
+Y_DC[9] <= 11'b11111111000;
+Y_DC[10] <= 11'b11111111100;
+Y_DC[11] <= 11'b11111111110;
+Y_AC_code_length[0] <= 2;
+Y_AC_code_length[1] <= 2;
+Y_AC_code_length[2] <= 3;
+Y_AC_code_length[3] <= 4;
+Y_AC_code_length[4] <= 4;
+Y_AC_code_length[5] <= 4;
+Y_AC_code_length[6] <= 5;
+Y_AC_code_length[7] <= 5;
+Y_AC_code_length[8] <= 5;
+Y_AC_code_length[9] <= 6;
+Y_AC_code_length[10] <= 6;
+Y_AC_code_length[11] <= 7;
+Y_AC_code_length[12] <= 7;
+Y_AC_code_length[13] <= 7;
+Y_AC_code_length[14] <= 7;
+Y_AC_code_length[15] <= 8;
+Y_AC_code_length[16] <= 8;
+Y_AC_code_length[17] <= 8;
+Y_AC_code_length[18] <= 9;
+Y_AC_code_length[19] <= 9;
+Y_AC_code_length[20] <= 9;
+Y_AC_code_length[21] <= 9;
+Y_AC_code_length[22] <= 9;
+Y_AC_code_length[23] <= 10;
+Y_AC_code_length[24] <= 10;
+Y_AC_code_length[25] <= 10;
+Y_AC_code_length[26] <= 10;
+Y_AC_code_length[27] <= 10;
+Y_AC_code_length[28] <= 11;
+Y_AC_code_length[29] <= 11;
+Y_AC_code_length[30] <= 11;
+Y_AC_code_length[31] <= 11;
+Y_AC_code_length[32] <= 12;
+Y_AC_code_length[33] <= 12;
+Y_AC_code_length[34] <= 12;
+Y_AC_code_length[35] <= 12;
+Y_AC_code_length[36] <= 15;
+Y_AC_code_length[37] <= 16;
+Y_AC_code_length[38] <= 16;
+Y_AC_code_length[39] <= 16;
+Y_AC_code_length[40] <= 16;
+Y_AC_code_length[41] <= 16;
+Y_AC_code_length[42] <= 16;
+Y_AC_code_length[43] <= 16;
+Y_AC_code_length[44] <= 16;
+Y_AC_code_length[45] <= 16;
+Y_AC_code_length[46] <= 16;
+Y_AC_code_length[47] <= 16;
+Y_AC_code_length[48] <= 16;
+Y_AC_code_length[49] <= 16;
+Y_AC_code_length[50] <= 16;
+Y_AC_code_length[51] <= 16;
+Y_AC_code_length[52] <= 16;
+Y_AC_code_length[53] <= 16;
+Y_AC_code_length[54] <= 16;
+Y_AC_code_length[55] <= 16;
+Y_AC_code_length[56] <= 16;
+Y_AC_code_length[57] <= 16;
+Y_AC_code_length[58] <= 16;
+Y_AC_code_length[59] <= 16;
+Y_AC_code_length[60] <= 16;
+Y_AC_code_length[61] <= 16;
+Y_AC_code_length[62] <= 16;
+Y_AC_code_length[63] <= 16;
+Y_AC_code_length[64] <= 16;
+Y_AC_code_length[65] <= 16;
+Y_AC_code_length[66] <= 16;
+Y_AC_code_length[67] <= 16;
+Y_AC_code_length[68] <= 16;
+Y_AC_code_length[69] <= 16;
+Y_AC_code_length[70] <= 16;
+Y_AC_code_length[71] <= 16;
+Y_AC_code_length[72] <= 16;
+Y_AC_code_length[73] <= 16;
+Y_AC_code_length[74] <= 16;
+Y_AC_code_length[75] <= 16;
+Y_AC_code_length[76] <= 16;
+Y_AC_code_length[77] <= 16;
+Y_AC_code_length[78] <= 16;
+Y_AC_code_length[79] <= 16;
+Y_AC_code_length[80] <= 16;
+Y_AC_code_length[81] <= 16;
+Y_AC_code_length[82] <= 16;
+Y_AC_code_length[83] <= 16;
+Y_AC_code_length[84] <= 16;
+Y_AC_code_length[85] <= 16;
+Y_AC_code_length[86] <= 16;
+Y_AC_code_length[87] <= 16;
+Y_AC_code_length[88] <= 16;
+Y_AC_code_length[89] <= 16;
+Y_AC_code_length[90] <= 16;
+Y_AC_code_length[91] <= 16;
+Y_AC_code_length[92] <= 16;
+Y_AC_code_length[93] <= 16;
+Y_AC_code_length[94] <= 16;
+Y_AC_code_length[95] <= 16;
+Y_AC_code_length[96] <= 16;
+Y_AC_code_length[97] <= 16;
+Y_AC_code_length[98] <= 16;
+Y_AC_code_length[99] <= 16;
+Y_AC_code_length[100] <= 16;
+Y_AC_code_length[101] <= 16;
+Y_AC_code_length[102] <= 16;
+Y_AC_code_length[103] <= 16;
+Y_AC_code_length[104] <= 16;
+Y_AC_code_length[105] <= 16;
+Y_AC_code_length[106] <= 16;
+Y_AC_code_length[107] <= 16;
+Y_AC_code_length[108] <= 16;
+Y_AC_code_length[109] <= 16;
+Y_AC_code_length[110] <= 16;
+Y_AC_code_length[111] <= 16;
+Y_AC_code_length[112] <= 16;
+Y_AC_code_length[113] <= 16;
+Y_AC_code_length[114] <= 16;
+Y_AC_code_length[115] <= 16;
+Y_AC_code_length[116] <= 16;
+Y_AC_code_length[117] <= 16;
+Y_AC_code_length[118] <= 16;
+Y_AC_code_length[119] <= 16;
+Y_AC_code_length[120] <= 16;
+Y_AC_code_length[121] <= 16;
+Y_AC_code_length[122] <= 16;
+Y_AC_code_length[123] <= 16;
+Y_AC_code_length[124] <= 16;
+Y_AC_code_length[125] <= 16;
+Y_AC_code_length[126] <= 16;
+Y_AC_code_length[127] <= 16;
+Y_AC_code_length[128] <= 16;
+Y_AC_code_length[129] <= 16;
+Y_AC_code_length[130] <= 16;
+Y_AC_code_length[131] <= 16;
+Y_AC_code_length[132] <= 16;
+Y_AC_code_length[133] <= 16;
+Y_AC_code_length[134] <= 16;
+Y_AC_code_length[135] <= 16;
+Y_AC_code_length[136] <= 16;
+Y_AC_code_length[137] <= 16;
+Y_AC_code_length[138] <= 16;
+Y_AC_code_length[139] <= 16;
+Y_AC_code_length[140] <= 16;
+Y_AC_code_length[141] <= 16;
+Y_AC_code_length[142] <= 16;
+Y_AC_code_length[143] <= 16;
+Y_AC_code_length[144] <= 16;
+Y_AC_code_length[145] <= 16;
+Y_AC_code_length[146] <= 16;
+Y_AC_code_length[147] <= 16;
+Y_AC_code_length[148] <= 16;
+Y_AC_code_length[149] <= 16;
+Y_AC_code_length[150] <= 16;
+Y_AC_code_length[151] <= 16;
+Y_AC_code_length[152] <= 16;
+Y_AC_code_length[153] <= 16;
+Y_AC_code_length[154] <= 16;
+Y_AC_code_length[155] <= 16;
+Y_AC_code_length[156] <= 16;
+Y_AC_code_length[157] <= 16;
+Y_AC_code_length[158] <= 16;
+Y_AC_code_length[159] <= 16;
+Y_AC_code_length[160] <= 16;
+Y_AC_code_length[161] <= 16;
+Y_AC[0] <= 16'b0000000000000000;
+Y_AC[1] <= 16'b0100000000000000;
+Y_AC[2] <= 16'b1000000000000000;
+Y_AC[3] <= 16'b1010000000000000;
+Y_AC[4] <= 16'b1011000000000000;
+Y_AC[5] <= 16'b1100000000000000;
+Y_AC[6] <= 16'b1101000000000000;
+Y_AC[7] <= 16'b1101100000000000;
+Y_AC[8] <= 16'b1110000000000000;
+Y_AC[9] <= 16'b1110100000000000;
+Y_AC[10] <= 16'b1110110000000000;
+Y_AC[11] <= 16'b1111000000000000;
+Y_AC[12] <= 16'b1111001000000000;
+Y_AC[13] <= 16'b1111010000000000;
+Y_AC[14] <= 16'b1111011000000000;
+Y_AC[15] <= 16'b1111100000000000;
+Y_AC[16] <= 16'b1111100100000000;
+Y_AC[17] <= 16'b1111101000000000;
+Y_AC[18] <= 16'b1111101100000000;
+Y_AC[19] <= 16'b1111101110000000;
+Y_AC[20] <= 16'b1111110000000000;
+Y_AC[21] <= 16'b1111110010000000;
+Y_AC[22] <= 16'b1111110100000000;
+Y_AC[23] <= 16'b1111110110000000;
+Y_AC[24] <= 16'b1111110111000000;
+Y_AC[25] <= 16'b1111111000000000;
+Y_AC[26] <= 16'b1111111001000000;
+Y_AC[27] <= 16'b1111111010000000;
+Y_AC[28] <= 16'b1111111011000000;
+Y_AC[29] <= 16'b1111111011100000;
+Y_AC[30] <= 16'b1111111100000000;
+Y_AC[31] <= 16'b1111111100100000;
+Y_AC[32] <= 16'b1111111101000000;
+Y_AC[33] <= 16'b1111111101010000;
+Y_AC[34] <= 16'b1111111101100000;
+Y_AC[35] <= 16'b1111111101110000;
+Y_AC[36] <= 16'b1111111110000000;
+Y_AC[37] <= 16'b1111111110000010;
+Y_AC[38] <= 16'b1111111110000011;
+Y_AC[39] <= 16'b1111111110000100;
+Y_AC[40] <= 16'b1111111110000101;
+Y_AC[41] <= 16'b1111111110000110;
+Y_AC[42] <= 16'b1111111110000111;
+Y_AC[43] <= 16'b1111111110001000;
+Y_AC[44] <= 16'b1111111110001001;
+Y_AC[45] <= 16'b1111111110001010;
+Y_AC[46] <= 16'b1111111110001011;
+Y_AC[47] <= 16'b1111111110001100;
+Y_AC[48] <= 16'b1111111110001101;
+Y_AC[49] <= 16'b1111111110001110;
+Y_AC[50] <= 16'b1111111110001111;
+Y_AC[51] <= 16'b1111111110010000;
+Y_AC[52] <= 16'b1111111110010001;
+Y_AC[53] <= 16'b1111111110010010;
+Y_AC[54] <= 16'b1111111110010011;
+Y_AC[55] <= 16'b1111111110010100;
+Y_AC[56] <= 16'b1111111110010101;
+Y_AC[57] <= 16'b1111111110010110;
+Y_AC[58] <= 16'b1111111110010111;
+Y_AC[59] <= 16'b1111111110011000;
+Y_AC[60] <= 16'b1111111110011001;
+Y_AC[61] <= 16'b1111111110011010;
+Y_AC[62] <= 16'b1111111110011011;
+Y_AC[63] <= 16'b1111111110011100;
+Y_AC[64] <= 16'b1111111110011101;
+Y_AC[65] <= 16'b1111111110011110;
+Y_AC[66] <= 16'b1111111110011111;
+Y_AC[67] <= 16'b1111111110100000;
+Y_AC[68] <= 16'b1111111110100001;
+Y_AC[69] <= 16'b1111111110100010;
+Y_AC[70] <= 16'b1111111110100011;
+Y_AC[71] <= 16'b1111111110100100;
+Y_AC[72] <= 16'b1111111110100101;
+Y_AC[73] <= 16'b1111111110100110;
+Y_AC[74] <= 16'b1111111110100111;
+Y_AC[75] <= 16'b1111111110101000;
+Y_AC[76] <= 16'b1111111110101001;
+Y_AC[77] <= 16'b1111111110101010;
+Y_AC[78] <= 16'b1111111110101011;
+Y_AC[79] <= 16'b1111111110101100;
+Y_AC[80] <= 16'b1111111110101101;
+Y_AC[81] <= 16'b1111111110101110;
+Y_AC[82] <= 16'b1111111110101111;
+Y_AC[83] <= 16'b1111111110110000;
+Y_AC[84] <= 16'b1111111110110001;
+Y_AC[85] <= 16'b1111111110110010;
+Y_AC[86] <= 16'b1111111110110011;
+Y_AC[87] <= 16'b1111111110110100;
+Y_AC[88] <= 16'b1111111110110101;
+Y_AC[89] <= 16'b1111111110110110;
+Y_AC[90] <= 16'b1111111110110111;
+Y_AC[91] <= 16'b1111111110111000;
+Y_AC[92] <= 16'b1111111110111001;
+Y_AC[93] <= 16'b1111111110111010;
+Y_AC[94] <= 16'b1111111110111011;
+Y_AC[95] <= 16'b1111111110111100;
+Y_AC[96] <= 16'b1111111110111101;
+Y_AC[97] <= 16'b1111111110111110;
+Y_AC[98] <= 16'b1111111110111111;
+Y_AC[99] <= 16'b1111111111000000;
+Y_AC[100] <= 16'b1111111111000001;
+Y_AC[101] <= 16'b1111111111000010;
+Y_AC[102] <= 16'b1111111111000011;
+Y_AC[103] <= 16'b1111111111000100;
+Y_AC[104] <= 16'b1111111111000101;
+Y_AC[105] <= 16'b1111111111000110;
+Y_AC[106] <= 16'b1111111111000111;
+Y_AC[107] <= 16'b1111111111001000;
+Y_AC[108] <= 16'b1111111111001001;
+Y_AC[109] <= 16'b1111111111001010;
+Y_AC[110] <= 16'b1111111111001011;
+Y_AC[111] <= 16'b1111111111001100;
+Y_AC[112] <= 16'b1111111111001101;
+Y_AC[113] <= 16'b1111111111001110;
+Y_AC[114] <= 16'b1111111111001111;
+Y_AC[115] <= 16'b1111111111010000;
+Y_AC[116] <= 16'b1111111111010001;
+Y_AC[117] <= 16'b1111111111010010;
+Y_AC[118] <= 16'b1111111111010011;
+Y_AC[119] <= 16'b1111111111010100;
+Y_AC[120] <= 16'b1111111111010101;
+Y_AC[121] <= 16'b1111111111010110;
+Y_AC[122] <= 16'b1111111111010111;
+Y_AC[123] <= 16'b1111111111011000;
+Y_AC[124] <= 16'b1111111111011001;
+Y_AC[125] <= 16'b1111111111011010;
+Y_AC[126] <= 16'b1111111111011011;
+Y_AC[127] <= 16'b1111111111011100;
+Y_AC[128] <= 16'b1111111111011101;
+Y_AC[129] <= 16'b1111111111011110;
+Y_AC[130] <= 16'b1111111111011111;
+Y_AC[131] <= 16'b1111111111100000;
+Y_AC[132] <= 16'b1111111111100001;
+Y_AC[133] <= 16'b1111111111100010;
+Y_AC[134] <= 16'b1111111111100011;
+Y_AC[135] <= 16'b1111111111100100;
+Y_AC[136] <= 16'b1111111111100101;
+Y_AC[137] <= 16'b1111111111100110;
+Y_AC[138] <= 16'b1111111111100111;
+Y_AC[139] <= 16'b1111111111101000;
+Y_AC[140] <= 16'b1111111111101001;
+Y_AC[141] <= 16'b1111111111101010;
+Y_AC[142] <= 16'b1111111111101011;
+Y_AC[143] <= 16'b1111111111101100;
+Y_AC[144] <= 16'b1111111111101101;
+Y_AC[145] <= 16'b1111111111101110;
+Y_AC[146] <= 16'b1111111111101111;
+Y_AC[147] <= 16'b1111111111110000;
+Y_AC[148] <= 16'b1111111111110001;
+Y_AC[149] <= 16'b1111111111110010;
+Y_AC[150] <= 16'b1111111111110011;
+Y_AC[151] <= 16'b1111111111110100;
+Y_AC[152] <= 16'b1111111111110101;
+Y_AC[153] <= 16'b1111111111110110;
+Y_AC[154] <= 16'b1111111111110111;
+Y_AC[155] <= 16'b1111111111111000;
+Y_AC[156] <= 16'b1111111111111001;
+Y_AC[157] <= 16'b1111111111111010;
+Y_AC[158] <= 16'b1111111111111011;
+Y_AC[159] <= 16'b1111111111111100;
+Y_AC[160] <= 16'b1111111111111101;
+Y_AC[161] <= 16'b1111111111111110;
+Y_AC_run_code[1] <= 0;
+Y_AC_run_code[2] <= 1;
+Y_AC_run_code[3] <= 2;
+Y_AC_run_code[0] <= 3;
+Y_AC_run_code[4] <= 4;
+Y_AC_run_code[17] <= 5;
+Y_AC_run_code[5] <= 6;
+Y_AC_run_code[18] <= 7;
+Y_AC_run_code[33] <= 8;
+Y_AC_run_code[49] <= 9;
+Y_AC_run_code[65] <= 10;
+Y_AC_run_code[6] <= 11;
+Y_AC_run_code[19] <= 12;
+Y_AC_run_code[81] <= 13;
+Y_AC_run_code[97] <= 14;
+Y_AC_run_code[7] <= 15;
+Y_AC_run_code[34] <= 16;
+Y_AC_run_code[113] <= 17;
+Y_AC_run_code[20] <= 18;
+Y_AC_run_code[50] <= 19;
+Y_AC_run_code[129] <= 20;
+Y_AC_run_code[145] <= 21;
+Y_AC_run_code[161] <= 22;
+Y_AC_run_code[8] <= 23;
+Y_AC_run_code[35] <= 24;
+Y_AC_run_code[66] <= 25;
+Y_AC_run_code[177] <= 26;
+Y_AC_run_code[193] <= 27;
+Y_AC_run_code[21] <= 28;
+Y_AC_run_code[82] <= 29;
+Y_AC_run_code[209] <= 30;
+Y_AC_run_code[240] <= 31;
+Y_AC_run_code[36] <= 32;
+Y_AC_run_code[51] <= 33;
+Y_AC_run_code[98] <= 34;
+Y_AC_run_code[114] <= 35;
+Y_AC_run_code[130] <= 36;
+Y_AC_run_code[9] <= 37;
+Y_AC_run_code[10] <= 38;
+Y_AC_run_code[22] <= 39;
+Y_AC_run_code[23] <= 40;
+Y_AC_run_code[24] <= 41;
+Y_AC_run_code[25] <= 42;
+Y_AC_run_code[26] <= 43;
+Y_AC_run_code[37] <= 44;
+Y_AC_run_code[38] <= 45;
+Y_AC_run_code[39] <= 46;
+Y_AC_run_code[40] <= 47;
+Y_AC_run_code[41] <= 48;
+Y_AC_run_code[42] <= 49;
+Y_AC_run_code[52] <= 50;
+Y_AC_run_code[53] <= 51;
+Y_AC_run_code[54] <= 52;
+Y_AC_run_code[55] <= 53;
+Y_AC_run_code[56] <= 54;
+Y_AC_run_code[57] <= 55;
+Y_AC_run_code[58] <= 56;
+Y_AC_run_code[67] <= 57;
+Y_AC_run_code[68] <= 58;
+Y_AC_run_code[69] <= 59;
+Y_AC_run_code[70] <= 60;
+Y_AC_run_code[71] <= 61;
+Y_AC_run_code[72] <= 62;
+Y_AC_run_code[73] <= 63;
+Y_AC_run_code[74] <= 64;
+Y_AC_run_code[83] <= 65;
+Y_AC_run_code[84] <= 66;
+Y_AC_run_code[85] <= 67;
+Y_AC_run_code[86] <= 68;
+Y_AC_run_code[87] <= 69;
+Y_AC_run_code[88] <= 70;
+Y_AC_run_code[89] <= 71;
+Y_AC_run_code[90] <= 72;
+Y_AC_run_code[99] <= 73;
+Y_AC_run_code[100] <= 74;
+Y_AC_run_code[101] <= 75;
+Y_AC_run_code[102] <= 76;
+Y_AC_run_code[103] <= 77;
+Y_AC_run_code[104] <= 78;
+Y_AC_run_code[105] <= 79;
+Y_AC_run_code[106] <= 80;
+Y_AC_run_code[115] <= 81;
+Y_AC_run_code[116] <= 82;
+Y_AC_run_code[117] <= 83;
+Y_AC_run_code[118] <= 84;
+Y_AC_run_code[119] <= 85;
+Y_AC_run_code[120] <= 86;
+Y_AC_run_code[121] <= 87;
+Y_AC_run_code[122] <= 88;
+Y_AC_run_code[131] <= 89;
+Y_AC_run_code[132] <= 90;
+Y_AC_run_code[133] <= 91;
+Y_AC_run_code[134] <= 92;
+Y_AC_run_code[135] <= 93;
+Y_AC_run_code[136] <= 94;
+Y_AC_run_code[137] <= 95;
+Y_AC_run_code[138] <= 96;
+Y_AC_run_code[146] <= 97;
+Y_AC_run_code[147] <= 98;
+Y_AC_run_code[148] <= 99;
+Y_AC_run_code[149] <= 100;
+Y_AC_run_code[150] <= 101;
+Y_AC_run_code[151] <= 102;
+Y_AC_run_code[152] <= 103;
+Y_AC_run_code[153] <= 104;
+Y_AC_run_code[154] <= 105;
+Y_AC_run_code[162] <= 106;
+Y_AC_run_code[163] <= 107;
+Y_AC_run_code[164] <= 108;
+Y_AC_run_code[165] <= 109;
+Y_AC_run_code[166] <= 110;
+Y_AC_run_code[167] <= 111;
+Y_AC_run_code[168] <= 112;
+Y_AC_run_code[169] <= 113;
+Y_AC_run_code[170] <= 114;
+Y_AC_run_code[178] <= 115;
+Y_AC_run_code[179] <= 116;
+Y_AC_run_code[180] <= 117;
+Y_AC_run_code[181] <= 118;
+Y_AC_run_code[182] <= 119;
+Y_AC_run_code[183] <= 120;
+Y_AC_run_code[184] <= 121;
+Y_AC_run_code[185] <= 122;
+Y_AC_run_code[186] <= 123;
+Y_AC_run_code[194] <= 124;
+Y_AC_run_code[195] <= 125;
+Y_AC_run_code[196] <= 126;
+Y_AC_run_code[197] <= 127;
+Y_AC_run_code[198] <= 128;
+Y_AC_run_code[199] <= 129;
+Y_AC_run_code[200] <= 130;
+Y_AC_run_code[201] <= 131;
+Y_AC_run_code[202] <= 132;
+Y_AC_run_code[210] <= 133;
+Y_AC_run_code[211] <= 134;
+Y_AC_run_code[212] <= 135;
+Y_AC_run_code[213] <= 136;
+Y_AC_run_code[214] <= 137;
+Y_AC_run_code[215] <= 138;
+Y_AC_run_code[216] <= 139;
+Y_AC_run_code[217] <= 140;
+Y_AC_run_code[218] <= 141;
+Y_AC_run_code[225] <= 142;
+Y_AC_run_code[226] <= 143;
+Y_AC_run_code[227] <= 144;
+Y_AC_run_code[228] <= 145;
+Y_AC_run_code[229] <= 146;
+Y_AC_run_code[230] <= 147;
+Y_AC_run_code[231] <= 148;
+Y_AC_run_code[232] <= 149;
+Y_AC_run_code[233] <= 150;
+Y_AC_run_code[234] <= 151;
+Y_AC_run_code[241] <= 152;
+Y_AC_run_code[242] <= 153;
+Y_AC_run_code[243] <= 154;
+Y_AC_run_code[244] <= 155;
+Y_AC_run_code[245] <= 156;
+Y_AC_run_code[246] <= 157;
+Y_AC_run_code[247] <= 158;
+Y_AC_run_code[248] <= 159;
+Y_AC_run_code[249] <= 160;
+Y_AC_run_code[250] <= 161;
+ Y_AC_run_code[16] <= 0;
+ Y_AC_run_code[32] <= 0;
+ Y_AC_run_code[48] <= 0;
+ Y_AC_run_code[64] <= 0;
+ Y_AC_run_code[80] <= 0;
+ Y_AC_run_code[96] <= 0;
+ Y_AC_run_code[112] <= 0;
+ Y_AC_run_code[128] <= 0;
+ Y_AC_run_code[144] <= 0;
+ Y_AC_run_code[160] <= 0;
+ Y_AC_run_code[176] <= 0;
+ Y_AC_run_code[192] <= 0;
+ Y_AC_run_code[208] <= 0;
+ Y_AC_run_code[224] <= 0;
+end
+
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[31] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[31] <= JPEG_bs_5[31];
+ else if (enable_module && orc_8 == 0)
+ JPEG_bitstream[31] <= JPEG_bs_5[31];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[30] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[30] <= JPEG_bs_5[30];
+ else if (enable_module && orc_8 <= 1)
+ JPEG_bitstream[30] <= JPEG_bs_5[30];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[29] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[29] <= JPEG_bs_5[29];
+ else if (enable_module && orc_8 <= 2)
+ JPEG_bitstream[29] <= JPEG_bs_5[29];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[28] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[28] <= JPEG_bs_5[28];
+ else if (enable_module && orc_8 <= 3)
+ JPEG_bitstream[28] <= JPEG_bs_5[28];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[27] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[27] <= JPEG_bs_5[27];
+ else if (enable_module && orc_8 <= 4)
+ JPEG_bitstream[27] <= JPEG_bs_5[27];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[26] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[26] <= JPEG_bs_5[26];
+ else if (enable_module && orc_8 <= 5)
+ JPEG_bitstream[26] <= JPEG_bs_5[26];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[25] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[25] <= JPEG_bs_5[25];
+ else if (enable_module && orc_8 <= 6)
+ JPEG_bitstream[25] <= JPEG_bs_5[25];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[24] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[24] <= JPEG_bs_5[24];
+ else if (enable_module && orc_8 <= 7)
+ JPEG_bitstream[24] <= JPEG_bs_5[24];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[23] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[23] <= JPEG_bs_5[23];
+ else if (enable_module && orc_8 <= 8)
+ JPEG_bitstream[23] <= JPEG_bs_5[23];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[22] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[22] <= JPEG_bs_5[22];
+ else if (enable_module && orc_8 <= 9)
+ JPEG_bitstream[22] <= JPEG_bs_5[22];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[21] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[21] <= JPEG_bs_5[21];
+ else if (enable_module && orc_8 <= 10)
+ JPEG_bitstream[21] <= JPEG_bs_5[21];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[20] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[20] <= JPEG_bs_5[20];
+ else if (enable_module && orc_8 <= 11)
+ JPEG_bitstream[20] <= JPEG_bs_5[20];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[19] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[19] <= JPEG_bs_5[19];
+ else if (enable_module && orc_8 <= 12)
+ JPEG_bitstream[19] <= JPEG_bs_5[19];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[18] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[18] <= JPEG_bs_5[18];
+ else if (enable_module && orc_8 <= 13)
+ JPEG_bitstream[18] <= JPEG_bs_5[18];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[17] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[17] <= JPEG_bs_5[17];
+ else if (enable_module && orc_8 <= 14)
+ JPEG_bitstream[17] <= JPEG_bs_5[17];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[16] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[16] <= JPEG_bs_5[16];
+ else if (enable_module && orc_8 <= 15)
+ JPEG_bitstream[16] <= JPEG_bs_5[16];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[15] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[15] <= JPEG_bs_5[15];
+ else if (enable_module && orc_8 <= 16)
+ JPEG_bitstream[15] <= JPEG_bs_5[15];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[14] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[14] <= JPEG_bs_5[14];
+ else if (enable_module && orc_8 <= 17)
+ JPEG_bitstream[14] <= JPEG_bs_5[14];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[13] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[13] <= JPEG_bs_5[13];
+ else if (enable_module && orc_8 <= 18)
+ JPEG_bitstream[13] <= JPEG_bs_5[13];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[12] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[12] <= JPEG_bs_5[12];
+ else if (enable_module && orc_8 <= 19)
+ JPEG_bitstream[12] <= JPEG_bs_5[12];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[11] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[11] <= JPEG_bs_5[11];
+ else if (enable_module && orc_8 <= 20)
+ JPEG_bitstream[11] <= JPEG_bs_5[11];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[10] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[10] <= JPEG_bs_5[10];
+ else if (enable_module && orc_8 <= 21)
+ JPEG_bitstream[10] <= JPEG_bs_5[10];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[9] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[9] <= JPEG_bs_5[9];
+ else if (enable_module && orc_8 <= 22)
+ JPEG_bitstream[9] <= JPEG_bs_5[9];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[8] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[8] <= JPEG_bs_5[8];
+ else if (enable_module && orc_8 <= 23)
+ JPEG_bitstream[8] <= JPEG_bs_5[8];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[7] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[7] <= JPEG_bs_5[7];
+ else if (enable_module && orc_8 <= 24)
+ JPEG_bitstream[7] <= JPEG_bs_5[7];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[6] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[6] <= JPEG_bs_5[6];
+ else if (enable_module && orc_8 <= 25)
+ JPEG_bitstream[6] <= JPEG_bs_5[6];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[5] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[5] <= JPEG_bs_5[5];
+ else if (enable_module && orc_8 <= 26)
+ JPEG_bitstream[5] <= JPEG_bs_5[5];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[4] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[4] <= JPEG_bs_5[4];
+ else if (enable_module && orc_8 <= 27)
+ JPEG_bitstream[4] <= JPEG_bs_5[4];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[3] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[3] <= JPEG_bs_5[3];
+ else if (enable_module && orc_8 <= 28)
+ JPEG_bitstream[3] <= JPEG_bs_5[3];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[2] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[2] <= JPEG_bs_5[2];
+ else if (enable_module && orc_8 <= 29)
+ JPEG_bitstream[2] <= JPEG_bs_5[2];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[1] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[1] <= JPEG_bs_5[1];
+ else if (enable_module && orc_8 <= 30)
+ JPEG_bitstream[1] <= JPEG_bs_5[1];
+end
+
+always @(posedge clk)
+begin
+ if (rst)
+ JPEG_bitstream[0] <= 0;
+ else if (enable_module && rollover_7)
+ JPEG_bitstream[0] <= JPEG_bs_5[0];
+ else if (enable_module && orc_8 <= 31)
+ JPEG_bitstream[0] <= JPEG_bs_5[0];
+end
+endmodule
diff --git a/openlane/designs/zipdiv/config.tcl b/openlane/designs/zipdiv/config.tcl
new file mode 100755
index 0000000..d15ae97
--- /dev/null
+++ b/openlane/designs/zipdiv/config.tcl
@@ -0,0 +1,13 @@
+
+# Design
+set ::env(DESIGN_NAME) "zipdiv"
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/zipdiv.v"
+
+set ::env(CLOCK_PORT) "i_clk"
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+ source $filename
+}
\ No newline at end of file
diff --git a/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hd_config.tcl b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hd_config.tcl
new file mode 100755
index 0000000..05141a6
--- /dev/null
+++ b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hd_config.tcl
@@ -0,0 +1,7 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20.00"
+set ::env(SYNTH_STRATEGY) "DELAY 2"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 40
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hdll_config.tcl b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hdll_config.tcl
new file mode 100644
index 0000000..fdeae87
--- /dev/null
+++ b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20.00"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 40
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hs_config.tcl b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hs_config.tcl
new file mode 100644
index 0000000..c770dc4
--- /dev/null
+++ b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_hs_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20.00"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/zipdiv/sky130A_sky130_fd_sc_ls_config.tcl b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_ls_config.tcl
new file mode 100644
index 0000000..fdeae87
--- /dev/null
+++ b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_ls_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20.00"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 40
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/zipdiv/sky130A_sky130_fd_sc_ms_config.tcl b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_ms_config.tcl
new file mode 100644
index 0000000..c770dc4
--- /dev/null
+++ b/openlane/designs/zipdiv/sky130A_sky130_fd_sc_ms_config.tcl
@@ -0,0 +1,6 @@
+# SCL Configs
+set ::env(CLOCK_PERIOD) "20.00"
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 35
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
diff --git a/openlane/designs/zipdiv/src/zipdiv.v b/openlane/designs/zipdiv/src/zipdiv.v
new file mode 100644
index 0000000..552d5cd
--- /dev/null
+++ b/openlane/designs/zipdiv/src/zipdiv.v
@@ -0,0 +1,520 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: div.v
+//
+// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
+//
+// Purpose: Provide an Integer divide capability to the Zip CPU. Provides
+// for both signed and unsigned divide.
+//
+// Steps:
+// i_reset The DIVide unit starts in idle. It can also be placed into an
+// idle by asserting the reset input.
+//
+// i_wr When i_reset is asserted, a divide begins. On the next clock:
+//
+// o_busy is set high so everyone else knows we are at work and they can
+// wait for us to complete.
+//
+// pre_sign is set to true if we need to do a signed divide. In this
+// case, we take a clock cycle to turn the divide into an unsigned
+// divide.
+//
+// o_quotient, a place to store our result, is initialized to all zeros.
+//
+// r_dividend is set to the numerator
+//
+// r_divisor is set to 2^31 * the denominator (shift left by 31, or add
+// 31 zeros to the right of the number.
+//
+// pre_sign When true (clock cycle after i_wr), a clock cycle is used
+// to take the absolute value of the various arguments (r_dividend
+// and r_divisor), and to calculate what sign the output result
+// should be.
+//
+//
+// At this point, the divide is has started. The divide works by walking
+// through every shift of the
+//
+// DIVIDEND over the
+// DIVISOR
+//
+// If the DIVISOR is bigger than the dividend, the divisor is shifted
+// right, and nothing is done to the output quotient.
+//
+// DIVIDEND
+// DIVISOR
+//
+// This repeats, until DIVISOR is less than or equal to the divident, as in
+//
+// DIVIDEND
+// DIVISOR
+//
+// At this point, if the DIVISOR is less than the dividend, the
+// divisor is subtracted from the dividend, and the DIVISOR is again
+// shifted to the right. Further, a '1' bit gets set in the output
+// quotient.
+//
+// Once we've done this for 32 clocks, we've accumulated our answer into
+// the output quotient, and we can proceed to the next step. If the
+// result will be signed, the next step negates the quotient, otherwise
+// it returns the result.
+//
+// On the clock when we are done, o_busy is set to false, and o_valid set
+// to true. (It is a violation of the ZipCPU internal protocol for both
+// busy and valid to ever be true on the same clock. It is also a
+// violation for busy to be false with valid true thereafter.)
+//
+//
+// Creator: Dan Gisselquist, Ph.D.
+// Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2015-2018, Gisselquist Technology, LLC
+//
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
+// target there if the PDF file isn't present.) If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+//
+// License: GPL, v3, as defined and found on www.gnu.org,
+// http://www.gnu.org/licenses/gpl.html
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+`default_nettype none
+//
+// `include "cpudefs.v"
+//
+module zipdiv(i_clk, i_reset, i_wr, i_signed, i_numerator, i_denominator,
+ o_busy, o_valid, o_err, o_quotient, o_flags);
+ parameter BW=32, LGBW = 5;
+ input wire i_clk, i_reset;
+ // Input parameters
+ input wire i_wr, i_signed;
+ input wire [(BW-1):0] i_numerator, i_denominator;
+ // Output parameters
+ output reg o_busy, o_valid, o_err;
+ output reg [(BW-1):0] o_quotient;
+ output wire [3:0] o_flags;
+
+ // r_busy is an internal busy register. It will clear one clock
+ // before we are valid, so it can't be o_busy ...
+ //
+ reg r_busy;
+ reg [(2*BW-2):0] r_divisor;
+ reg [(BW-1):0] r_dividend;
+ wire [(BW):0] diff; // , xdiff[(BW-1):0];
+ assign diff = r_dividend - r_divisor[(BW-1):0];
+
+ reg r_sign, pre_sign, r_z, r_c, last_bit;
+ reg [(LGBW-1):0] r_bit;
+ reg zero_divisor;
+
+ // The Divide logic begins with r_busy. We use r_busy to determine
+ // whether or not the divide is in progress, vs being complete.
+ // Here, we clear r_busy on any reset and set it on i_wr (the request
+ // do to a divide). The divide ends when we are on the last bit,
+ // or equivalently when we discover we are dividing by zero.
+ initial r_busy = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_busy <= 1'b0;
+ else if (i_wr)
+ r_busy <= 1'b1;
+ else if ((last_bit)||(zero_divisor))
+ r_busy <= 1'b0;
+
+ // o_busy is very similar to r_busy, save for some key differences.
+ // Primary among them is that o_busy needs to (possibly) be true
+ // for an extra clock after r_busy clears. This would be that extra
+ // clock where we negate the result (assuming a signed divide, and that
+ // the result is supposed to be negative.) Otherwise, the two are
+ // identical.
+ initial o_busy = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ o_busy <= 1'b0;
+ else if (i_wr)
+ o_busy <= 1'b1;
+ else if (((last_bit)&&(!r_sign))||(zero_divisor))
+ o_busy <= 1'b0;
+ else if (!r_busy)
+ o_busy <= 1'b0;
+
+ // If we are asked to divide by zero, we need to halt. The sooner
+ // we halt and report the error, the better. Hence, here we look
+ // for a zero divisor while being busy. The always above us will then
+ // look at this and halt a divide in the middle if we are trying to
+ // divide by zero.
+ //
+ // Note that this works off of the 2BW-1 length vector. If we can
+ // simplify that, it should simplify our logic as well.
+ initial zero_divisor = 1'b0;
+ always @(posedge i_clk)
+ // zero_divisor <= (r_divisor == 0)&&(r_busy);
+ if (i_reset)
+ zero_divisor <= 1'b0;
+ else if (i_wr)
+ zero_divisor <= (i_denominator == 0);
+ else if (!r_busy)
+ zero_divisor <= 1'b0;
+
+ // o_valid is part of the ZipCPU protocol. It will be set to true
+ // anytime our answer is valid and may be used by the calling module.
+ // Indeed, the ZipCPU will halt (and ignore us) once the i_wr has been
+ // set until o_valid gets set.
+ //
+ // Here, we clear o_valid on a reset, and any time we are on the last
+ // bit while busy (provided the sign is zero, or we are dividing by
+ // zero). Since o_valid is self-clearing, we don't need to clear
+ // it on an i_wr signal.
+ initial o_valid = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ o_valid <= 1'b0;
+ else if (r_busy)
+ begin
+ if ((last_bit)||(zero_divisor))
+ o_valid <= (zero_divisor)||(!r_sign);
+ end else if (r_sign)
+ begin
+ o_valid <= (!zero_divisor); // 1'b1;
+ end else
+ o_valid <= 1'b0;
+
+ // Division by zero error reporting. Anytime we detect a zero divisor,
+ // we set our output error, and then hold it until we are valid and
+ // everything clears.
+ initial o_err = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ o_err <= 1'b0;
+ else if (o_valid)
+ o_err <= 1'b0;
+ else if (((r_busy)||(r_sign))&&(zero_divisor))
+ o_err <= 1'b1;
+ else
+ o_err <= 1'b0;
+
+ // r_bit
+ //
+ // Keep track of which "bit" of our divide we are on. This number
+ // ranges from 31 down to zero. On any write, we set ourselves to
+ // 5'h1f. Otherwise, while we are busy (but not within the pre-sign
+ // adjustment stage), we subtract one from our value on every clock.
+ initial r_bit = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_bit <= 0;
+ else if ((r_busy)&&(!pre_sign))
+ r_bit <= r_bit + 1'b1;
+ else
+ r_bit <= 0;
+
+ // last_bit
+ //
+ // This logic replaces a lot of logic that was inside our giant state
+ // machine with ... something simpler. In particular, we'll use this
+ // logic to determine we are processing our last bit. The only trick
+ // is, this bit needs to be set whenever (r_busy) and (r_bit == 0),
+ // hence we need to set on (r_busy) and (r_bit == 1) so as to be set
+ // when (r_bit == 0).
+ initial last_bit = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ last_bit <= 1'b0;
+ else if (r_busy)
+ last_bit <= (r_bit == {(LGBW){1'b1}}-1'b1);
+ else
+ last_bit <= 1'b0;
+
+ // pre_sign
+ //
+ // This is part of the state machine. pre_sign indicates that we need
+ // a extra clock to take the absolute value of our inputs. It need only
+ // be true for the one clock, and then it must clear itself.
+ initial pre_sign = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ pre_sign <= 1'b0;
+ else if (i_wr)
+ pre_sign <= (i_signed)&&((i_numerator[BW-1])||(i_denominator[BW-1]));
+ else
+ pre_sign <= 1'b0;
+
+ // As a result of our operation, we need to set the flags. The most
+ // difficult of these is the "Z" flag indicating that the result is
+ // zero. Here, we'll use the same logic that sets the low-order
+ // bit to clear our zero flag, and leave the zero flag set in all
+ // other cases. Well ... not quite. If we need to flip the sign of
+ // our value, then we can't quite clear the zero flag ... yet.
+ initial r_z = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_z <= 1'b0;
+ else if((r_busy)&&(r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW]))
+ // If we are busy, the upper bits of our divisor are
+ // zero (i.e., we got the shift right), and the top
+ // (carry) bit of the difference is zero (no overflow),
+ // then we could subtract our divisor from our dividend
+ // and hence we add a '1' to the quotient, while setting
+ // the zero flag to false.
+ r_z <= 1'b0;
+ else if (i_wr)
+ r_z <= 1'b1;
+
+ // r_dividend
+ // This is initially the numerator. On a signed divide, it then becomes
+ // the absolute value of the numerator. We'll subtract from this value
+ // the divisor shifted as appropriate for every output bit we are
+ // looking for--just as with traditional long division.
+ initial r_dividend = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_dividend <= 0;
+ else if (pre_sign)
+ begin
+ // If we are doing a signed divide, then take the
+ // absolute value of the dividend
+ if (r_dividend[BW-1])
+ r_dividend <= -r_dividend;
+ // The begin/end block is important so we don't lose
+ // the fact that on an else we don't do anything.
+ end else if((r_busy)&&(r_divisor[(2*BW-2):(BW)]==0)&&(!diff[BW]))
+ // This is the condition whereby we set a '1' in our
+ // output quotient, and we subtract the (current)
+ // divisor from our dividend. (The difference is
+ // already kept in the diff vector above.)
+ r_dividend <= diff[(BW-1):0];
+ else if (!r_busy)
+ // Once we are done, and r_busy is no longer high, we'll
+ // always accept new values into our dividend. This
+ // guarantees that, when i_wr is set, the new value
+ // is already set as desired.
+ r_dividend <= i_numerator;
+
+ initial r_divisor = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_divisor <= 0;
+ else if (pre_sign)
+ begin
+ if (r_divisor[(2*BW-2)])
+ r_divisor[(2*BW-2):(BW-1)]
+ <= -r_divisor[(2*BW-2):(BW-1)];
+ end else if (r_busy)
+ r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
+ else
+ r_divisor <= { i_denominator, {(BW-1){1'b0}} };
+
+ // r_sign
+ // is a flag for our state machine control(s). r_sign will be set to
+ // true any time we are doing a signed divide and the result must be
+ // negative. In that case, we take a final logic stage at the end of
+ // the divide to negate the output. This flag is what tells us we need
+ // to do that. r_busy will be true during the divide, then when r_busy
+ // goes low, r_sign will be checked, then the idle/reset stage will have
+ // been reached. For this reason, we cannot set r_sign unless we are
+ // up to something.
+ initial r_sign = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_sign <= 1'b0;
+ else if (pre_sign)
+ r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
+ else if (r_busy)
+ r_sign <= (r_sign)&&(!zero_divisor);
+ else
+ r_sign <= 1'b0;
+
+ initial o_quotient = 0;
+ always @(posedge i_clk)
+ if (i_reset)
+ o_quotient <= 0;
+ else if (r_busy)
+ begin
+ o_quotient <= { o_quotient[(BW-2):0], 1'b0 };
+ if ((r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW]))
+ o_quotient[0] <= 1'b1;
+ end else if (r_sign)
+ o_quotient <= -o_quotient;
+ else
+ o_quotient <= 0;
+
+ // Set Carry on an exact divide
+ // Perhaps nothing uses this, but ... well, I suppose we could remove
+ // this logic eventually, just ... not yet.
+ initial r_c = 1'b0;
+ always @(posedge i_clk)
+ if (i_reset)
+ r_c <= 1'b0;
+ else
+ r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
+
+ // The last flag: Negative. This flag is set assuming that the result
+ // of the divide was negative (i.e., the high order bit is set). This
+ // will also be true of an unsigned divide--if the high order bit is
+ // ever set upon completion. Indeed, you might argue that there's no
+ // logic involved.
+ wire w_n;
+ assign w_n = o_quotient[(BW-1)];
+
+ assign o_flags = { 1'b0, w_n, r_c, r_z };
+
+`ifdef FORMAL
+ reg f_past_valid;
+ initial f_past_valid = 0;
+ always @(posedge i_clk)
+ f_past_valid <= 1'b1;
+
+`ifdef DIV
+`define ASSUME assume
+`else
+`define ASSUME assert
+`endif
+
+ initial `ASSUME(i_reset);
+ always @(*)
+ if (!f_past_valid)
+ `ASSUME(i_reset);
+
+ always @(posedge i_clk)
+ if ((!f_past_valid)||($past(i_reset)))
+ begin
+ assert(!o_busy);
+ assert(!o_valid);
+ assert(!o_err);
+ //
+ assert(!r_busy);
+ assert(!zero_divisor);
+ assert(r_bit==0);
+ assert(!last_bit);
+ assert(!pre_sign);
+ assert(!r_z);
+ assert(r_dividend==0);
+ assert(o_quotient==0);
+ assert(!r_c);
+ assert(r_divisor==0);
+
+ `ASSUME(!i_wr);
+ end
+
+ always @(*)
+ if (o_busy)
+ `ASSUME(!i_wr);
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&(!$past(i_reset))&&($past(o_busy))&&(!o_busy))
+ begin
+ assert(o_valid);
+ end
+
+ // A formal methods section
+ //
+ // This section isn't yet complete. For now, it is just
+ // a description of things I think should be in here ... not
+ // yet a description of what it would take to prove
+ // this divide (yet).
+ always @(*)
+ if (o_err)
+ assert(o_valid);
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&(!$past(i_wr)))
+ assert(!pre_sign);
+ always @(posedge i_clk)
+ if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr))&&($past(i_signed))
+ &&(|$past({i_numerator[BW-1],i_denominator[BW-1]})))
+ assert(pre_sign);
+
+ // always @(posedge i_clk)
+ // if ((f_past_valid)&&(!$past(pre_sign)))
+ // assert(!r_sign);
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr)))
+ assert(o_busy);
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&($past(o_valid)))
+ assert(!o_valid);
+
+ always @(*)
+ if ((o_valid)&&(!o_err))
+ assert(r_z == ((o_quotient == 0)? 1'b1:1'b0));
+
+ always @(*)
+ if ((o_valid)&&(!o_err))
+ assert(w_n == o_quotient[BW-1]);
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&(!$past(r_busy))&&(!$past(i_wr)))
+ assert(!o_busy);
+ always @(posedge i_clk)
+ assert((!o_busy)||(!o_valid));
+ always @(posedge i_clk)
+ if(o_busy) `ASSUME(!i_wr);
+ always @(*)
+ if(r_busy) assert(o_busy);
+
+ reg [BW:0] f_bits_set;
+ always @(posedge i_clk)
+ if (i_reset)
+ f_bits_set <= 0;
+ else if (i_wr)
+ f_bits_set <= 0;
+ else if ((r_busy)&&(!pre_sign))
+ f_bits_set <= { f_bits_set[BW-1:0], 1'b1 };
+
+ always @(*)
+ if ((o_valid)&&(!o_err))
+ assert((!f_bits_set[BW])&&(&f_bits_set[BW-1:0]));
+
+
+ always @(posedge i_clk)
+ if ((f_past_valid)&&(!$past(i_reset))&&($past(r_busy))
+ &&($past(r_divisor[2*BW-2:BW])==0))
+ begin
+ if ($past(r_divisor) == 0)
+ assert(o_err);
+ else if ($past(pre_sign))
+ begin
+ if ($past(r_dividend[BW-1]))
+ assert(r_dividend == -$past(r_dividend));
+ if ($past(r_divisor[(2*BW-2)]))
+ begin
+ assert(r_divisor[(2*BW-2):(BW-1)]
+ == -$past(r_divisor[(2*BW-2):(BW-1)]));
+ assert(r_divisor[BW-2:0] == 0);
+ end
+ end else begin
+ if (o_quotient[0])
+ assert(r_dividend == $past(diff));
+ else
+ assert(r_dividend == $past(r_dividend));
+
+ // r_divisor should shift down on every step
+ assert(r_divisor[2*BW-2]==0);
+ assert(r_divisor[2*BW-3:0]==$past(r_divisor[2*BW-2:1]));
+ end
+ if ($past(r_dividend) >= $past(r_divisor[BW-1:0]))
+ assert(o_quotient[0]);
+ else
+ assert(!o_quotient[0]);
+ end
+`endif
+endmodule
diff --git a/openlane/docker/.gitignore b/openlane/docker/.gitignore
new file mode 100644
index 0000000..a4b093f
--- /dev/null
+++ b/openlane/docker/.gitignore
@@ -0,0 +1,5 @@
+build/
+logs/
+*/fetch_submodules_from_tarballs.py
+*/utils.py
+/base/
\ No newline at end of file
diff --git a/openlane/docker/Makefile b/openlane/docker/Makefile
new file mode 100644
index 0000000..ef35167
--- /dev/null
+++ b/openlane/docker/Makefile
@@ -0,0 +1,97 @@
+#DOCKER_BUILD_OPTS ?= --rm --no-cache
+OPENLANE_IMAGE_NAME ?= efabless/openlane:current
+TOOL_REPOSITORY ?= efabless/openlane-tools
+
+OS_NAME ?= centos-7
+OS_IMAGE ?= centos:centos7
+
+DOCKER_BUILD_OPTS ?= --rm
+DOCKER_BUILD_INVOCATION ?= docker build # docker buildx build --platform linux/amd64 --load
+BUILD_COMMAND = $(DOCKER_BUILD_INVOCATION) $(DOCKER_BUILD_OPTS)
+
+NO_PDKS_ARGS =
+NO_PDKS ?= 1
+ifeq ($(NO_PDKS), 1)
+NO_PDKS_ARGS = --no-pdks
+endif
+
+PYTHON_BIN ?= python3
+TOOLS = $(shell $(PYTHON_BIN) ../dependencies/tool.py --containerized $(NO_PDKS_ARGS) .)
+OPENLANE_SKELETON=configuration dependencies designs regression_results scripts AUTHORS.md env.py flow.tcl LICENSE run_designs.py
+TOOL_BUILD_TARGETS = $(foreach tool,$(TOOLS),build-$(tool))
+TOOL_EXPORT_TARGETS = $(foreach tool,$(TOOLS),pull-$(tool))
+
+
+# ==============================================================================
+# Build Tools
+# ==============================================================================
+all: openlane
+
+build-all: $(TOOL_BUILD_TARGETS)
+build_base_image: ./build_base/Dockerfile
+ cat ../dependencies/centos-7/precompile_time.txt > ./build_base/yum_precompile_dependencies.txt
+ cat ../dependencies/centos-7/compile_time.txt > ./build_base/yum_compile_dependencies.txt
+ cat ../dependencies/centos-7/run_time.txt > ./build_base/yum_dependencies.txt
+ cat ../dependencies/python/precompile_time.txt > ./build_base/pip_precompile_dependencies.txt
+ cat ../dependencies/python/compile_time.txt > ./build_base/pip_compile_dependencies.txt
+ cat ../dependencies/python/run_time.txt > ./build_base/pip_dependencies.txt
+ mkdir -p logs
+ $(BUILD_COMMAND) -t openlane-build-base --build-arg OS_IMAGE=$(OS_IMAGE) build_base | tee logs/base.build.txt
+
+run_base_image: ./run_base/Dockerfile
+ cat ../dependencies/python/run_time.txt > ./run_base/pip_dependencies.txt
+ cat ../dependencies/centos-7/precompile_time.txt > ./run_base/yum_repos.txt
+ cat ../dependencies/centos-7/run_time.txt > ./run_base/yum_dependencies.txt
+ mkdir -p logs
+ $(BUILD_COMMAND) -t openlane-run-base --build-arg OS_IMAGE=$(OS_IMAGE) run_base | tee logs/base.run.txt
+
+
+$(TOOL_BUILD_TARGETS): build-% : ./%/Dockerfile build_base_image run_base_image
+ mkdir -p logs
+ cp ./utils.py $*
+ $(BUILD_COMMAND)\
+ $(shell $(PYTHON_BIN) ../dependencies/tool.py --docker-args $*)\
+ --target runnable\
+ -t $(TOOL_REPOSITORY):$(shell $(PYTHON_BIN) ../dependencies/tool.py --docker-tag-for-os=$(OS_NAME) $*)\
+ $* |\
+ tee logs/$*.build.txt
+
+# ==============================================================================
+# Export Tools
+# ==============================================================================
+$(TOOL_EXPORT_TARGETS): pull-% : FORCE
+ $(PYTHON_BIN) ./utils.py pull-if-doesnt-exist --repository $(TOOL_REPOSITORY) --os $(OS_NAME) $*
+
+./tar/openlane: FORCE
+ rm -rf ./tar/openlane
+ mkdir -p ./tar/openlane
+ for file in $(OPENLANE_SKELETON); do \
+ cp -r ../$$file ./tar/openlane/$$file ; \
+ done
+
+.PHONY: merge openlane
+openlane: merge
+merge: run_base_image $(TOOL_EXPORT_TARGETS) ./tar/openlane ../dependencies/tool_metadata.yml
+ cat ../dependencies/tool_metadata.yml > ./tar/tool_metadata.yml
+ printf "$(shell git rev-parse HEAD)" > ./tar/git_version
+ printf "$(shell git rev-parse --short=7 HEAD)" > ./tar/git_version_short
+ $(PYTHON_BIN) ./utils.py process-dockerfile-tpl --repository $(TOOL_REPOSITORY) --os $(OS_NAME) $(TOOLS) > ./openlane/Dockerfile
+ mkdir -p logs/tar
+ $(BUILD_COMMAND)\
+ -t $(OPENLANE_IMAGE_NAME)\
+ -f ./openlane/Dockerfile ./tar\
+ | tee logs/$<.build.txt
+ rm -rf ./tar/openlane
+
+.PHONY: clean
+clean: clean_export clean_merge
+
+.PHONY: clean_merge
+clean_merge:
+ rm -rf ./tar/openlane
+
+.PHONY: clean_export
+clean_export:
+ rm -rf export/*.tar.gz
+
+FORCE:
\ No newline at end of file
diff --git a/openlane/docker/README.md b/openlane/docker/README.md
new file mode 100644
index 0000000..cd969f7
--- /dev/null
+++ b/openlane/docker/README.md
@@ -0,0 +1,72 @@
+# The OpenLane Docker Image
+Note: You probably shouldn't be here.
+
+## Structure
+
+There are two "families" of images: one is for building tools, and the other is for running tools.
+
+The build family has a base image that contains all build dependencies and then a number of subimages named **builders** tasked with downloading all tools from source and building them.
+
+The run family has a base image that contains all the running dependencies. There are a number of subimages named **runnables**, which copy the results from the builders and allows them to be runnable- those images are pushed to Docker Hub in the repository efabless/openlane-tools. Another image in the run family is the final OpenLane image, which has *all* the tools.
+
+```
+openlane-build-base
+L cugr **builder**
+L cvc **builder**
+L openroad_app **builder**
+L [...]
+
+openlane-run-base
+L openlane
+L cugr **runnable**
+L cvc **runnable**
+L openroad_app **runnable**
+```
+
+## Building the OpenLane Image
+```bash
+make # or make openlane # or make merge
+```
+
+## Updating a Tool Binary
+
+You can build a tool runnable using the following command: `make build-<tool_name>`.
+
+When you are doing that, presumably you want to build a different version of the tool than is shipped by default with the OpenLane docker image. For example, suppose we would like to include OpenRoad's version of Yosys rather than one from https://github.com/yosyshq/yosys. We need to modify the file `tool_metadata.yml` that is located in `OpenLane/dependencies`. Here is an example of such a change:
+
+```
+- name: yosys
+ repo: https://github.com/The-OpenROAD-Project/yosys
+ commit: bc027b2cae9a85b887684930705762fac720b529
+ build: |
+ make clean
+ make PREFIX=$PREFIX config-gcc
+ make PREFIX=$PREFIX -j$(nproc)
+ make PREFIX=$PREFIX install
+```
+
+Be alert to the fact that if you mix and match different tool versions (i.e. different git commit hashes), you can possibly run into compatibility issues.
+
+To list the available tools, `python3 ../dependencies/tool.py --containerized`, which is just essentially listing the contents of `tool_metadata.yml`.
+
+Be sure to `make openlane` **in the `docker/` folder** after building any tool, which will create the final OpenLane image. This will create a new Docker image tagged, by default, `efabless/openlane:current`. You can override the name as follows (again, **in the `docker/` folder**):
+
+```sh
+ make openlane OPENLANE_IMAGE_NAME=whatever/whatever:whatever
+```
+
+## Running the newly created Docker image
+OpenLane scripts depend upon a variety of different shell environment variables in order to run correctly. They are all conveniently set by using the `make mount` command at the root of the repository. However, if you just do that, it will spin up the original image and not the one you just created. In order to use your new Docker image, first set the shell varialble `OPENLANE_IMAGE_NAME` to the newly created image as follows (**in the root of the repository**):
+
+```sh
+ make mount OPENLANE_IMAGE_NAME=whatever/whatever:whatever
+```
+
+## Running as root
+* For security reasons, we don't recommend the default root Docker installation. See https://docs.docker.com/engine/security/rootless/ for a safer Docker installation also supported by OpenLane.
+
+By default `make mount` logs into the image with the user ID that is currently active. If you are running as an unprivileged user, you can use `make mount` to log in as root to the Docker image, but you will need to use `sudo` to do this. But, if you are depending on shell environment variables that you may have set during the current session they will be dropped by the `sudo` command. One way to pass those on to the sudo shell is to use the `-E` option. The following shows how you can do that:
+
+```
+ sudo -E make mount
+```
diff --git a/openlane/docker/build_base/.gitignore b/openlane/docker/build_base/.gitignore
new file mode 100644
index 0000000..314f02b
--- /dev/null
+++ b/openlane/docker/build_base/.gitignore
@@ -0,0 +1 @@
+*.txt
\ No newline at end of file
diff --git a/openlane/docker/build_base/Dockerfile b/openlane/docker/build_base/Dockerfile
new file mode 100644
index 0000000..6661a02
--- /dev/null
+++ b/openlane/docker/build_base/Dockerfile
@@ -0,0 +1,52 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+ARG OS_IMAGE="centos:centos7"
+FROM ${OS_IMAGE}
+
+# Install Yum Dependencies
+COPY ./yum_precompile_dependencies.txt /yum_precompile_dependencies.txt
+COPY ./yum_compile_dependencies.txt /yum_compile_dependencies.txt
+COPY ./yum_dependencies.txt /yum_dependencies.txt
+RUN yum install --setopt=skip_missing_names_on_install=False -y $(cat /yum_precompile_dependencies.txt | tr '\n' ' ') && \
+ yum install --setopt=skip_missing_names_on_install=False -y $(cat /yum_compile_dependencies.txt | tr '\n' ' ') && \
+ yum install --setopt=skip_missing_names_on_install=False -y $(cat /yum_dependencies.txt | tr '\n' ' ') && \
+ yum clean all && \
+ rm -rf /var/cache/yum
+
+RUN alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 60
+
+# Configure Git
+RUN git config --global user.name "OpenLane User"
+RUN git config --global user.email "openlane.user@localhost"
+
+# Install Python Dependencies
+## Wheel Build Dependencies
+RUN python3 -m pip install --no-cache-dir --upgrade pip
+COPY ./pip_compile_dependencies.txt /pip_compile_dependencies.txt
+COPY ./pip_dependencies.txt /pip_dependencies.txt
+RUN python3 -m pip install --no-cache-dir -r /pip_compile_dependencies.txt
+RUN python3 -m pip install --no-cache-dir -r /pip_dependencies.txt
+
+# Update Certs
+RUN yum update -y ca-certificates
+
+# Environment Configuration
+ENV CC=/opt/rh/devtoolset-8/root/usr/bin/gcc \
+ CPP=/opt/rh/devtoolset-8/root/usr/bin/cpp \
+ CXX=/opt/rh/devtoolset-8/root/usr/bin/g++ \
+ PATH=/opt/rh/devtoolset-8/root/usr/bin:$PATH \
+ LD_LIBRARY_PATH=/opt/rh/devtoolset-8/root/usr/lib64:/opt/rh/devtoolset-8/root/usr/lib:/opt/rh/devtoolset-8/root/usr/lib64/dyninst:/opt/rh/devtoolset-8/root/usr/lib/dyninst:/opt/rh/devtoolset-8/root/usr/lib64:/opt/rh/devtoolset-8/root/usr/lib:$LD_LIBRARY_PATH
+
+ENV LD_LIBRARY_PATH=/opt/rh/llvm-toolset-7.0/root/usr/lib64:/opt/rh/llvm-toolset-7.0/root/usr/lib:/opt/rh/llvm-toolset-7.0/root/usr/lib64/dyninst:/opt/rh/llvm-toolset-7.0/root/usr/lib/dyninst:/opt/rh/llvm-toolset-7.0/root/usr/lib64:/opt/rh/llvm-toolset-7.0/root/usr/lib:$LD_LIBRARY_PATH
diff --git a/openlane/docker/cugr/Dockerfile b/openlane/docker/cugr/Dockerfile
new file mode 100644
index 0000000..f045819
--- /dev/null
+++ b/openlane/docker/cugr/Dockerfile
@@ -0,0 +1,47 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+# Installing boost for build dependency
+RUN curl -L https://sourceforge.net/projects/boost/files/boost/1.72.0/boost_1_72_0.tar.bz2/download | tar --strip-components=1 -xjC . && \
+ ./bootstrap.sh && \
+ ./b2 install --with-iostreams --with-test --with-serialization --with-system --with-filesystem --with-thread --with-program_options -j $(nproc)
+
+# needed to get the xxd binaries needed to package the *.dat files
+# into C arrays to be linked directly into the executable
+RUN yum -y install vim-common
+
+ARG CUGR_REPO
+ARG CUGR_COMMIT
+
+WORKDIR /cugr
+RUN curl -L ${CUGR_REPO}/tarball/${CUGR_COMMIT} | tar -xzC . --strip-components=1
+
+RUN python scripts/build.py -o release -t iccad19gr
+
+RUN mkdir -p /build/bin/ && \
+ cp run/iccad19gr /build/bin/cugr
+
+RUN mkdir -p /build/version
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/cugr.version
+RUN echo ${CUGR_COMMIT} >> /build/version/cugr.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/cvc/Dockerfile b/openlane/docker/cvc/Dockerfile
new file mode 100644
index 0000000..4dcdcf5
--- /dev/null
+++ b/openlane/docker/cvc/Dockerfile
@@ -0,0 +1,40 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+FROM openlane-build-base AS builder
+
+ARG CVC_REPO
+ARG CVC_COMMIT
+
+# Build
+WORKDIR /cvc
+RUN curl -L ${CVC_REPO}/tarball/${CVC_COMMIT} | tar -xzC . --strip-components=1 &&\
+ autoreconf -i && \
+ autoconf && \
+ ./configure --disable-nls --prefix=/build && \
+ make install
+
+RUN mkdir -p /build/version/
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/cvc.version
+RUN echo ${CVC_COMMIT} >> /build/version/cvc.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
+
diff --git a/openlane/docker/drcu/Dockerfile b/openlane/docker/drcu/Dockerfile
new file mode 100644
index 0000000..9ff2d47
--- /dev/null
+++ b/openlane/docker/drcu/Dockerfile
@@ -0,0 +1,47 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+# Installing boost for build dependency
+RUN curl -L https://sourceforge.net/projects/boost/files/boost/1.72.0/boost_1_72_0.tar.bz2/download | tar --strip-components=1 -xjC . && \
+ ./bootstrap.sh && \
+ ./b2 install --with-iostreams --with-test --with-serialization --with-system --with-filesystem --with-thread --with-program_options link=static -j $(nproc)
+
+# needed to get the xxd binaries needed to package the *.dat files
+# into C arrays to be linked directly into the executable
+RUN yum -y install vim-common
+
+ARG DRCU_REPO
+ARG DRCU_COMMIT
+
+WORKDIR /drcu
+RUN curl -L ${DRCU_REPO}/tarball/${DRCU_COMMIT} | tar -xzC . --strip-components=1
+
+RUN python scripts/build.py -o release -t ispd19dr
+
+RUN mkdir -p /build/bin/ && \
+ cp run/ispd19dr /build/bin/drcu
+
+RUN mkdir -p /build/version
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/drcu.version
+RUN echo ${DRCU_COMMIT} >> /build/version/drcu.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/git/Dockerfile b/openlane/docker/git/Dockerfile
new file mode 100644
index 0000000..25c7278
--- /dev/null
+++ b/openlane/docker/git/Dockerfile
@@ -0,0 +1,38 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+ARG GIT_REPO
+ARG GIT_COMMIT
+
+WORKDIR /git
+RUN curl -L ${GIT_REPO}/tarball/${GIT_COMMIT} |\
+ tar -xzC . --strip-components=1 &&\
+ make configure &&\
+ ./configure --prefix=/build &&\
+ make -j$(nproc)&&\
+ make install
+
+RUN mkdir -p /build/version/
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/git.version
+RUN echo ${GIT_COMMIT} >> /build/version/git.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/klayout/Dockerfile b/openlane/docker/klayout/Dockerfile
new file mode 100644
index 0000000..b3e4aca
--- /dev/null
+++ b/openlane/docker/klayout/Dockerfile
@@ -0,0 +1,44 @@
+# This file is unused. Building Klayout simply takes too damn long.
+
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+FROM openlane-build-base AS builder
+
+# git clone yosys
+ARG KLAYOUT_REPO
+ARG KLAYOUT_COMMIT
+
+RUN mkdir -p /build
+
+WORKDIR /klayout
+RUN curl -L ${KLAYOUT_REPO}/tarball/${KLAYOUT_COMMIT} | tar -xzC . --strip-components=1
+
+COPY ./build_klayout.sh ./build_klayout.sh
+
+RUN bash ./build_klayout.sh
+
+RUN mkdir -p /build/version/
+
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/klayout.version
+RUN echo ${KLAYOUT_COMMIT} >> /build/version/klayout.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/klayout/build_klayout.sh b/openlane/docker/klayout/build_klayout.sh
new file mode 100644
index 0000000..83ca2f9
--- /dev/null
+++ b/openlane/docker/klayout/build_klayout.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+set -e
+set -x
+
+bininstdir="./tmp/bin"
+builddir="./tmp/build"
+
+# destination folders
+bindir="/build/bin"
+libdir="/build/lib/klayout"
+
+distpackdir="/build/lib/python3/dist-packages"
+pylibdir="$distpackdir/klayout"
+
+# clean bin directory
+rm -rf $bininstdir
+
+sed -i 's/-O2 -g/-O2/' /usr/lib64/qt5/mkspecs/linux-g++/qmake.conf
+
+# do the actual build
+./build.sh\
+ -qt5 \
+ -j$(nproc) \
+ -without-qtbinding \
+ -bin $bininstdir \
+ -build $builddir \
+ -rpath $libdir
+
+echo "Copying files..."
+
+mkdir -p ${libdir}/db_plugins
+mkdir -p ${libdir}/lay_plugins
+mkdir -p ${pylibdir}
+mkdir -p ${bindir}
+
+cp -pd $bininstdir/strm* ${bindir}
+cp -pd $bininstdir/klayout ${bindir}
+cp -pd $bininstdir/lib*so* ${libdir}
+cp -pd $bininstdir/db_plugins/lib*so* ${libdir}/db_plugins
+cp -pd $bininstdir/lay_plugins/lib*so* ${libdir}/lay_plugins
+cp -pd $bininstdir/pymod/klayout/*so ${pylibdir}
+cp -pd $bininstdir/pymod/klayout/*py ${pylibdir}
+for d in db tl rdb lib; do
+ mkdir -p ${pylibdir}/$d
+ cp -pd $bininstdir/pymod/klayout/$d/*py ${pylibdir}/$d
+done
+
+echo "Stripping..."
+strip ${bindir}/*
+strip ${pylibdir}/*.so
+strip ${libdir}/db_plugins/*.so*
+strip ${libdir}/lay_plugins/*.so*
\ No newline at end of file
diff --git a/openlane/docker/magic/Dockerfile b/openlane/docker/magic/Dockerfile
new file mode 100644
index 0000000..a791fd2
--- /dev/null
+++ b/openlane/docker/magic/Dockerfile
@@ -0,0 +1,37 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+# Upstream is git://opencircuitdesign.com/magic, but servers are not stable enough for CI.
+ARG MAGIC_REPO
+ARG MAGIC_COMMIT
+
+WORKDIR /magic
+RUN curl -L ${MAGIC_REPO}/tarball/${MAGIC_COMMIT} | tar -xzC . --strip-components=1 && \
+ ./configure --prefix=/build && \
+ make -j$(nproc) && \
+ make install
+
+RUN mkdir -p /build/version/
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/magic.version
+RUN echo ${MAGIC_COMMIT} >> /build/version/magic.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
\ No newline at end of file
diff --git a/openlane/docker/netgen/Dockerfile b/openlane/docker/netgen/Dockerfile
new file mode 100644
index 0000000..a8fa239
--- /dev/null
+++ b/openlane/docker/netgen/Dockerfile
@@ -0,0 +1,37 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+# Upstream is git://opencircuitdesign.com/netgen, but servers are not stable enough for CI.
+ARG NETGEN_REPO
+ARG NETGEN_COMMIT
+
+WORKDIR /netgen
+
+RUN curl -L ${NETGEN_REPO}/tarball/${NETGEN_COMMIT} | tar -xzC . --strip-components=1 && \
+ ./configure CFLAGS="-O2 -g" --prefix=/build && \
+ make -j$(nproc) && \
+ make install
+
+RUN mkdir -p /build/version/
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/netgen.version
+RUN echo ${NETGEN_COMMIT} >> /build/version/netgen.version
+RUN tar -czf /build.tar.gz /build
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/open_pdks/Dockerfile b/openlane/docker/open_pdks/Dockerfile
new file mode 100644
index 0000000..c4b65f6
--- /dev/null
+++ b/openlane/docker/open_pdks/Dockerfile
@@ -0,0 +1,102 @@
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# WIP, probably will never make it to the image because it's taking forever to build
+
+FROM openlane-build-base AS builder
+
+ARG SKY130_REPO
+ARG SKY130_COMMIT
+
+ENV PDK_ROOT /build/pdk
+ENV LANG en_US.UTF-8
+ENV LC_ALL en_US.UTF-8
+ENV LC_CTYPE en_US.UTF-8
+
+WORKDIR ${PDK_ROOT}
+RUN git clone ${SKY130_REPO}
+WORKDIR ${PDK_ROOT}/skywater-pdk
+RUN git checkout main &&\
+ git submodule init &&\
+ git pull --no-recurse-submodules &&\
+ git checkout -qf ${SKY130_COMMIT}
+RUN git submodule update --init libraries/sky130_fd_sc_hd/latest &&\
+ git submodule update --init libraries/sky130_fd_sc_hs/latest &&\
+ git submodule update --init libraries/sky130_fd_sc_hdll/latest &&\
+ git submodule update --init libraries/sky130_fd_sc_ms/latest &&\
+ git submodule update --init libraries/sky130_fd_sc_ls/latest &&\
+ git submodule update --init libraries/sky130_fd_sc_hvl/latest &&\
+ git submodule update --init libraries/sky130_fd_io/latest &&\
+ git submodule update --init libraries/sky130_fd_pr/latest
+RUN python3 -m pip install -e scripts/python-skywater-pdk
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hd/latest
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hd/latest all
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hd/latest all --ccsnoise
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hdll/latest
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hdll/latest all
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hdll/latest all --ccsnoise
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hs/latest
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hs/latest all
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hs/latest all --ccsnoise
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hvl/latest
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hvl/latest all
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_hvl/latest all --ccsnoise
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ls/latest
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ls/latest all
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ls/latest all --ccsnoise
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ms/latest all --leakage
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ms/latest
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ms/latest all
+RUN python3 -m skywater_pdk.liberty libraries/sky130_fd_sc_ms/latest all --ccsnoise
+
+ARG MAGIC_REPO
+ARG MAGIC_COMMIT
+
+WORKDIR /magic
+RUN curl -L ${MAGIC_REPO}/tarball/${MAGIC_COMMIT} | tar -xzC . --strip-components=1 && \
+ ./configure --prefix=/usr && \
+ make -j$(nproc) && \
+ make install
+
+ARG OPEN_PDKS_REPO
+ARG OPEN_PDKS_COMMIT
+
+WORKDIR ${PDK_ROOT}
+RUN git clone ${OPEN_PDKS_REPO}
+WORKDIR ${PDK_ROOT}/open_pdks
+RUN git checkout master &&\
+ git checkout -qf ${OPEN_PDKS_COMMIT}
+RUN ./configure --enable-sky130-pdk=${PDK_ROOT}/skywater-pdk/libraries --enable-sram-sky130
+WORKDIR ${PDK_ROOT}/open_pdks/sky130
+RUN make alpha-repo xschem-repo sram-repo 2>&1 | tee /build/pdk_prereq.log
+RUN make 2>&1 | tee /build/pdk.log
+RUN make SHARED_PDKS_PATH=${PDK_ROOT} install
+
+RUN printf "skywater-pdk ${SKY130_COMMIT}" > ${PDK_ROOT}/sky130A/SOURCES
+RUN printf "magic ${MAGIC_COMMIT}" >> ${PDK_ROOT}/sky130A/SOURCES
+RUN printf "open_pdks ${OPEN_PDKS_COMMIT}" >> ${PDK_ROOT}/sky130A/SOURCES
+
+RUN rm -rf ${PDK_ROOT}/skywater-pdk
+RUN rm -rf ${PDK_ROOT}/open_pdks
+
+
+RUN tar -c /build | gzip -1 > /build.tar.gz
+
+# ---
+# pdk can't really be runnable, might as well shed a few layers
+FROM centos:centos7 as runnable
+
+COPY --from=builder /build.tar.gz /build.tar.gz
+
+
diff --git a/openlane/docker/openlane/.gitignore b/openlane/docker/openlane/.gitignore
new file mode 100644
index 0000000..51cc96c
--- /dev/null
+++ b/openlane/docker/openlane/.gitignore
@@ -0,0 +1 @@
+/Dockerfile
\ No newline at end of file
diff --git a/openlane/docker/openlane/Dockerfile.tpl b/openlane/docker/openlane/Dockerfile.tpl
new file mode 100644
index 0000000..e415730
--- /dev/null
+++ b/openlane/docker/openlane/Dockerfile.tpl
@@ -0,0 +1,56 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# <from>
+FROM openlane-run-base
+
+# Environment Configuration
+ENV OPENLANE_ROOT=/openlane
+ENV OPENROAD_BIN openroad
+
+ENV OPENROAD=/build/
+ENV PATH=$OPENLANE_ROOT:$OPENLANE_ROOT/scripts:$OPENROAD/bin:$OPENROAD/bin/Linux-x86_64:$OPENROAD/pdn/scripts:$PATH
+ENV LD_LIBRARY_PATH=$OPENROAD/lib:$OPENROAD/lib/Linux-x86_64:$LD_LIBRARY_PATH
+ENV MANPATH=$OPENROAD/share/man:$MANPATH
+ENV LANG en_US.UTF-8
+ENV LC_ALL en_US.UTF-8
+ENV LC_CTYPE en_US.UTF-8
+ENV PDK_ROOT /build/pdk
+
+# Tools
+## Qt Thing
+RUN dbus-uuidgen --ensure
+
+## Copy manifest
+ADD ./tool_metadata.yml /tool_metadata.yml
+
+## Copy Version
+ADD ./git_version /git_version
+ADD ./git_version_short /git_version_short
+
+## Artifacts
+COPY ./openlane /openlane
+# <copy>
+
+## Tclsh RC
+COPY ./.tclshrc /.tclshrc
+COPY ./.tclshrc /root/.tclshrc
+
+## Bash RC
+COPY ./.bashrc /.bashrc
+COPY ./.bashrc /root/.bashrc
+
+WORKDIR $OPENLANE_ROOT
+
+CMD /bin/bash
diff --git a/openlane/docker/openroad_app/Dockerfile b/openlane/docker/openroad_app/Dockerfile
new file mode 100644
index 0000000..59d738a
--- /dev/null
+++ b/openlane/docker/openroad_app/Dockerfile
@@ -0,0 +1,85 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+FROM openlane-build-base AS builder
+
+# Build Boost
+WORKDIR /boost
+RUN curl -L https://sourceforge.net/projects/boost/files/boost/1.76.0/boost_1_76_0.tar.bz2/download | tar --strip-components=1 -xjC . && \
+ ./bootstrap.sh && \
+ ./b2 install --with-iostreams --with-test --with-serialization --with-system --with-thread -j $(nproc)
+
+# Build Eigen
+WORKDIR /eigen
+RUN curl -L https://gitlab.com/libeigen/eigen/-/archive/3.3/eigen-3.3.tar.gz | tar --strip-components=1 -xzC . && \
+ mkdir build && \
+ cd build && \
+ cmake .. && \
+ make -j$(nproc) && \
+ make install
+
+# Build Lemon
+WORKDIR /lemon
+RUN curl -L http://lemon.cs.elte.hu/pub/sources/lemon-1.3.1.tar.gz | tar --strip-components=1 -xzC . && \
+ cmake -B build . && \
+ cmake --build build -j $(nproc) --target install
+
+# Build Spdlog
+WORKDIR /spdlog
+RUN curl -L https://github.com/gabime/spdlog/archive/refs/tags/v1.8.1.tar.gz | tar --strip-components=1 -xzC . && \
+ mkdir build && \
+ cd build && \
+ cmake .. && \
+ make install -j $(nproc)
+
+# Build Swig
+RUN yum remove -y swig3
+WORKDIR /swig
+RUN curl -L https://github.com/swig/swig/archive/refs/tags/v4.0.1.tar.gz | tar --strip-components=1 -xzC . && \
+ ./autogen.sh && \
+ ./configure --prefix=/usr && \
+ make -j $(nproc) && \
+ make install
+
+ARG OPENROAD_APP_REPO
+ARG OPENROAD_APP_COMMIT
+
+ENV LANG en_US.UTF-8
+ENV LC_ALL en_US.UTF-8
+ENV LC_CTYPE en_US.UTF-8
+
+WORKDIR /openroad
+RUN curl -L ${OPENROAD_APP_REPO}/tarball/${OPENROAD_APP_COMMIT} | tar -xzC . --strip-components=1
+COPY ./utils.py .
+RUN python3 ./utils.py fetch-submodules-from-tarballs ${OPENROAD_APP_REPO} ${OPENROAD_APP_COMMIT}
+
+# Build OpenROAD
+RUN sed -i "s/GITDIR-NOTFOUND/${OPENROAD_APP_COMMIT}/" cmake/GetGitRevisionDescription.cmake
+RUN mkdir build && mkdir -p /build/version && mkdir install
+RUN cd build && cmake -DCMAKE_INSTALL_PREFIX=$(pwd)/install ..
+RUN cd build && make -j$(nproc)
+RUN cd build && make install
+RUN cp -r build/install/bin /build/
+
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/openroad.version
+RUN echo ${OPENROAD_APP_COMMIT} >> /build/version/openroad.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/padring/Dockerfile b/openlane/docker/padring/Dockerfile
new file mode 100644
index 0000000..fdbd0d9
--- /dev/null
+++ b/openlane/docker/padring/Dockerfile
@@ -0,0 +1,38 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+ARG PADRING_REPO
+ARG PADRING_COMMIT
+WORKDIR /padring
+
+RUN curl -L ${PADRING_REPO}/tarball/${PADRING_COMMIT} | tar -xzC . --strip-components=1 && \
+ ./bootstrap.sh && \
+ cd build/ && \
+ ninja-build && \
+ mkdir /build/bin/ -p && \
+ cp padring /build/bin
+
+RUN mkdir -p /build/version
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/padring.version
+RUN echo ${PADRING_COMMIT} >> /build/version/padring.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/run_base/.gitignore b/openlane/docker/run_base/.gitignore
new file mode 100644
index 0000000..bbb69ec
--- /dev/null
+++ b/openlane/docker/run_base/.gitignore
@@ -0,0 +1,5 @@
+/*.tar.gz
+/*.yml
+/*.txt
+/git_version
+/git_version_short
\ No newline at end of file
diff --git a/openlane/docker/run_base/Dockerfile b/openlane/docker/run_base/Dockerfile
new file mode 100644
index 0000000..1accf5e
--- /dev/null
+++ b/openlane/docker/run_base/Dockerfile
@@ -0,0 +1,37 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+ARG OS_IMAGE="centos:centos7"
+FROM ${OS_IMAGE}
+
+# Install Yum Dependencies
+COPY ./yum_dependencies.txt /yum_dependencies.txt
+COPY ./yum_repos.txt /yum_repos.txt
+RUN yum install --setopt=skip_missing_names_on_install=False -y $(cat /yum_repos.txt) && \
+ yum install --setopt=skip_missing_names_on_install=False -y $(cat /yum_dependencies.txt) && \
+ yum clean all && \
+ rm -rf /var/cache/yum
+
+RUN alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 60
+
+# Configure Git
+RUN git config --global user.name "OpenLane User"
+RUN git config --global user.email "openlane.user@localhost"
+
+# Install Python Dependencies
+## Wheel Build Dependencies
+RUN python3 -m pip install --no-cache-dir --upgrade pip
+COPY ./pip_dependencies.txt /pip_dependencies.txt
+RUN python3 -m pip install --no-cache-dir -r /pip_dependencies.txt
\ No newline at end of file
diff --git a/openlane/docker/tar/.bashrc b/openlane/docker/tar/.bashrc
new file mode 100644
index 0000000..5ae4520
--- /dev/null
+++ b/openlane/docker/tar/.bashrc
@@ -0,0 +1,7 @@
+# OpenLane .bashrc file
+# Source global definitions
+alias ll='ls -lAFh';
+
+export OL_GIT_VERSION=$(cat /git_version_short);
+
+export PS1="\[\033[1;31m\]OpenLane Container ($OL_GIT_VERSION)\[\033[0m\]:\[\033[4;32m\]\w\[\033[0m\]$ ";
\ No newline at end of file
diff --git a/openlane/docker/tar/.gitignore b/openlane/docker/tar/.gitignore
new file mode 100644
index 0000000..8040e62
--- /dev/null
+++ b/openlane/docker/tar/.gitignore
@@ -0,0 +1,7 @@
+/*.tar.gz
+/*.yml
+/*.txt
+/git_version
+/git_version_short
+/build
+/openlane
\ No newline at end of file
diff --git a/openlane/docker/tar/.tclshrc b/openlane/docker/tar/.tclshrc
new file mode 100644
index 0000000..3eb5255
--- /dev/null
+++ b/openlane/docker/tar/.tclshrc
@@ -0,0 +1,3 @@
+if { [info exists ::env(OPENLANE_ROOT)] } {
+ package require openlane
+}
diff --git a/openlane/docker/utils.py b/openlane/docker/utils.py
new file mode 100644
index 0000000..31ec5da
--- /dev/null
+++ b/openlane/docker/utils.py
@@ -0,0 +1,247 @@
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import re
+import os
+import sys
+import json
+import click
+import shutil
+import pathlib
+import tempfile
+import subprocess
+import urllib.parse
+
+
+@click.group()
+def cli():
+ pass
+
+
+@click.command()
+@click.option("-r", "--repository", required=True)
+@click.option(
+ "-o", "--os", "operating_system", required=True, type=click.Choice(["centos-7"])
+)
+@click.argument("tool")
+def pull_if_doesnt_exist(repository, operating_system, tool):
+ image_tag = (
+ subprocess.check_output(
+ [
+ "python3",
+ "../dependencies/tool.py",
+ f"--docker-tag-for-os={operating_system}",
+ tool,
+ ]
+ )
+ .decode("utf8")
+ .rstrip()
+ )
+ image = f"{repository}:{image_tag}"
+ images = (
+ subprocess.check_output(["docker", "images", image])
+ .decode("utf8")
+ .rstrip()
+ .split("\n")[1:]
+ )
+ if len(images) < 1:
+ print(f"{image} not found, pulling...")
+ try:
+ subprocess.check_call(["docker", "pull", image])
+ print(f"Pulled {image}.")
+ except Exception as e:
+ if os.getenv("BUILD_IF_CANT_PULL") == "1":
+ print(f"{image} not found in the repository, building...")
+ subprocess.check_call(["make", f"build-{tool}"])
+ print(f"Built {image}.")
+ if os.getenv("BUILD_IF_CANT_PULL_THEN_PUSH") == "1":
+ print(f"Pushing {image} to the container repository...")
+ subprocess.check_call(["docker", "push", image])
+ print(f"Pushed {image}.")
+ else:
+ raise e
+
+
+cli.add_command(pull_if_doesnt_exist)
+
+
+@click.command()
+@click.option("-r", "--repository", required=True)
+@click.option(
+ "-o", "--os", "operating_system", required=True, type=click.Choice(["centos-7"])
+)
+@click.argument("tools", nargs=-1)
+def process_dockerfile_tpl(repository, operating_system, tools):
+ image_tags = [
+ (
+ subprocess.check_output(
+ [
+ "python3",
+ "../dependencies/tool.py",
+ f"--docker-tag-for-os={operating_system}",
+ tool,
+ ]
+ )
+ .decode("utf8")
+ .rstrip()
+ )
+ for tool in tools
+ ]
+
+ image_names = [f"{repository}:{tag}" for tag in image_tags]
+
+ from_lines = [f"FROM {name} as container{i}" for i, name in enumerate(image_names)]
+
+ copy_lines = [
+ f"COPY --from=container{i} /build /build" for i, _ in enumerate(image_names)
+ ]
+
+ template = open("./openlane/Dockerfile.tpl").read()
+
+ parts = template.split("# <from>")
+ parts.insert(1, "\n".join(from_lines))
+
+ from_filled = "\n".join(parts)
+
+ parts = from_filled.split("# <copy>")
+ parts.insert(1, "\n".join(copy_lines))
+
+ final = "\n".join(parts)
+ print(final)
+
+
+cli.add_command(process_dockerfile_tpl)
+
+
+@click.command()
+@click.option(
+ "--filter", default=".", help="regular expression to match submodule paths"
+)
+@click.argument("repository")
+@click.argument("commit")
+def fetch_submodules_from_tarballs(filter, repository, commit):
+ """
+ Must be run from inside an extracted repository tarball.
+
+ Given the repository's URL and commit, which are available, a table of the
+ git submodules with their repositories, commits and paths is constructed and
+ then promptly downloaded and extracted using only the GitHub APIs (and curl),
+ no git involved.
+
+ This makes things much faster than having to clone an repo's entire history then
+ its submodule's entire history.
+ """
+
+ repository_path_info: urllib.parse.SplitResult = urllib.parse.urlsplit(repository)
+
+ # 1. Get Commits Of Submodules
+ api_result = None
+
+ try:
+ api_result = subprocess.check_output(
+ [
+ "curl",
+ "--fail",
+ "-s",
+ "-L",
+ "-H",
+ "Accept: application/vnd.github.v3+json",
+ f"https://api.github.com/repos{repository_path_info.path}/git/trees/{commit}?recursive=True",
+ ]
+ )
+ except Exception as e:
+ print(e, file=sys.stderr)
+ sys.exit(os.EX_DATAERR)
+
+ api_result_parsed = json.loads(api_result)
+ api_result_tree = api_result_parsed["tree"]
+ submodules = [element for element in api_result_tree if element["type"] == "commit"]
+ shas_by_path = {submodule["path"]: submodule["sha"] for submodule in submodules}
+
+ # 2. Get Submodule Manifest
+ api_result = None
+
+ try:
+ api_result = subprocess.check_output(
+ [
+ "curl",
+ "--fail",
+ "-s",
+ "-L",
+ f"https://raw.githubusercontent.com/{repository_path_info.path}/{commit}/.gitmodules",
+ ]
+ )
+ except Exception as e:
+ print(e, file=sys.stderr)
+ sys.exit(os.EX_DATAERR)
+
+ gitmodules = api_result.decode("utf8")
+
+ section_line_rx = re.compile(r"\[\s*submodule\s+\"([\w\-\.\/]+)\"\]")
+ key_value_line_rx = re.compile(r"(\w+)\s*=\s*(.+)")
+
+ submodules_by_name = {}
+ current = {} # First one is discarded
+ for line in gitmodules.split("\n"):
+ section_match = section_line_rx.search(line)
+ if section_match is not None:
+ name = section_match[1]
+ submodules_by_name[name] = {}
+ current = submodules_by_name[name]
+
+ kvl_match = key_value_line_rx.search(line)
+ if kvl_match is not None:
+ key, value = kvl_match[1], kvl_match[2]
+ current[key] = value
+
+ for name, submodule in submodules_by_name.items():
+ submodule["commit"] = shas_by_path.get(submodule["path"])
+ if submodule["url"].endswith(".git"):
+ submodule["url"] = submodule["url"][:-4]
+
+ # 3. Extract Submodules
+ temp_dir = tempfile.gettempdir()
+ filter_rx = re.compile(filter, flags=re.I)
+ for (name, values) in submodules_by_name.items():
+ path = values["path"]
+
+ if filter_rx.match(path) is None:
+ print(f"Skipping {path}...", flush=True)
+ continue
+ else:
+ print(f"Expanding {path}...", flush=True)
+
+ name_fs = re.sub(r"\/", "_", name)
+ tarball = os.path.join(temp_dir, f"{name_fs}.tar.gz")
+
+ url = values["url"]
+ commit = values["commit"]
+
+ url = os.path.join(url, "tarball", commit)
+
+ print(f"Downloading {url} to {path}...", file=sys.stderr)
+ subprocess.check_call(["curl", "-sL", "-o", tarball, url])
+
+ shutil.rmtree(path, ignore_errors=True)
+
+ pathlib.Path(path).mkdir(parents=True, exist_ok=True)
+
+ subprocess.check_call(
+ ["tar", "-xzf", tarball, "--strip-components=1", "-C", path]
+ )
+
+
+cli.add_command(fetch_submodules_from_tarballs)
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/docker/vlogtoverilog/Dockerfile b/openlane/docker/vlogtoverilog/Dockerfile
new file mode 100644
index 0000000..01feb04
--- /dev/null
+++ b/openlane/docker/vlogtoverilog/Dockerfile
@@ -0,0 +1,38 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+FROM openlane-build-base AS builder
+
+ARG VLOGTOVERILOG_REPO
+ARG VLOGTOVERILOG_COMMIT
+
+WORKDIR /qflow
+RUN curl -L ${VLOGTOVERILOG_REPO}/tarball/${VLOGTOVERILOG_COMMIT} | tar -xzC . --strip-components=1 && \
+ ./configure && \
+ cd src && \
+ make vlog2Verilog
+
+RUN mkdir -p /build/bin && cp /qflow/src/vlog2Verilog /build/bin/
+
+RUN mkdir -p /build/version/
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/vlog2Verilog.version
+RUN echo ${VLOGTOVERILOG_COMMIT} >> /build/version/vlog2Verilog.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docker/yosys/Dockerfile b/openlane/docker/yosys/Dockerfile
new file mode 100644
index 0000000..5f5c9dc
--- /dev/null
+++ b/openlane/docker/yosys/Dockerfile
@@ -0,0 +1,40 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# syntax = docker/dockerfile:1.0-experimental
+FROM openlane-build-base AS builder
+
+# git clone yosys
+ARG YOSYS_REPO
+ARG YOSYS_COMMIT
+
+WORKDIR /yosys
+RUN curl -L ${YOSYS_REPO}/tarball/${YOSYS_COMMIT} | tar -xzC . --strip-components=1 && \
+ make PREFIX=/build config-gcc &&\
+ make PREFIX=/build -j$(nproc) &&\
+ make PREFIX=/build install
+
+
+RUN mkdir -p /build/version
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/yosys.version
+RUN echo ${YOSYS_COMMIT} >> /build/version/yosys.version
+RUN tar -czf /build.tar.gz /build
+
+# ---
+FROM openlane-run-base AS runnable
+
+ENV PATH /build/bin:$PATH
+
+COPY --from=builder /build /build
+COPY --from=builder /build.tar.gz /build.tar.gz
diff --git a/openlane/docs/Makefile b/openlane/docs/Makefile
new file mode 100644
index 0000000..bbe6232
--- /dev/null
+++ b/openlane/docs/Makefile
@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = ..
+BUILDDIR = _build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
diff --git a/openlane/docs/_ext/image_links.py b/openlane/docs/_ext/image_links.py
new file mode 100644
index 0000000..a91452f
--- /dev/null
+++ b/openlane/docs/_ext/image_links.py
@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import re
+from util import debug
+
+
+def setup(app):
+ app.connect("source-read", process_image_links)
+ return {"version": "1.0", "parallel_read_safe": True}
+
+
+def process_image_links(app, docname, source):
+ """
+ Converts image links in markdown files
+ from ./..../imagename.png to _static/imagename.png
+ This function is called by sphinx for each document.
+ `source` is a 1-item list.
+ """
+
+ linkexp = r'<img src=".*"\s*>'
+
+ for m in re.finditer(linkexp, source[0]):
+ link = m.group(0).split('"')
+ if len(link) == 3 and link[1].startswith("."):
+ link[1] = "_static/" + link[1].rpartition("/")[2]
+ link = '"'.join(link)
+ debug(f"[IMG] {docname}: {link}")
+
+ source[0] = source[0][: m.start()] + link + source[0][m.end() :]
diff --git a/openlane/docs/_ext/markdown_code_links.py b/openlane/docs/_ext/markdown_code_links.py
new file mode 100644
index 0000000..4bdcabf
--- /dev/null
+++ b/openlane/docs/_ext/markdown_code_links.py
@@ -0,0 +1,109 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import re
+import os.path as path
+from util import debug
+
+
+def setup(app):
+ app.add_config_value(
+ "markdown_code_links_githubrepo", "https://github.com/name/repo", "html"
+ )
+ app.add_config_value("markdown_code_links_githubbranch", "blob/master", "html")
+ app.add_config_value(
+ "markdown_code_links_codefileextensions", [".c", ".cpp"], "html"
+ )
+ app.connect("source-read", process_image_links)
+ return {"version": "1.0", "parallel_read_safe": False}
+
+
+def local_link_to_github(link, docname, githublink):
+ # get source document dir
+ path = docname.rpartition("/")[0]
+ # remove './'
+ if link.startswith("./"):
+ link = link[2:]
+ # move up if necessary
+ while link.startswith("../"):
+ link = link.partition("/")[2]
+ path = path.rpartition("/")[0]
+ # combine with repo path
+ if len(path):
+ link = path.rstrip("/") + "/" + link.lstrip("/")
+ # combine with repo link
+ link = githublink.rstrip("/") + "/" + link.lstrip("/")
+ return link
+
+
+def process_image_links(app, docname, source):
+ """
+ Converts local code links (specific file types) in markdown files
+ to github links to the same repo
+ from: [link_name](./dir1/dir2.../file.ext)
+ to: [link_name(https:gihtub.com/repo/dir1/dir2.../file.ext)
+ This function is called by sphinx for each document.
+ `source` is a 1-item list.
+ """
+
+ githublink = app.config.markdown_code_links_githubrepo.rstrip("/") + "/"
+ githublink += app.config.markdown_code_links_githubbranch.rstrip("/")
+ codefileextensions = app.config.markdown_code_links_codefileextensions
+ fulldocname = path.join(app.srcdir, docname)
+ fulldocdir = path.dirname(fulldocname)
+
+ # case 1 [name](./dir/file) or [name](../dir/file)
+ linknameexp1 = r"\[[\/\.\w]*\]"
+ linktargetexp1 = r"\(\.[\/\.\w]*{fileext}\)"
+
+ # case 2 [tag]
+ linknameexp2 = r"\[[0-9]*\]\:\s*"
+ linktargetexp2 = r"\.[\/\.\w]*{fileext}\s*\n"
+
+ # directory links don't need to end with '/', but will be verified as dirs
+ if "/" in codefileextensions:
+ codefileextensions.append("")
+
+ for fileext in codefileextensions:
+ if fileext.startswith(".") or fileext.startswith("/"):
+ fileext = "\\" + fileext
+
+ linkexp = linknameexp1 + linktargetexp1.format(fileext=fileext)
+ for m in reversed(list(re.finditer(linkexp, source[0]))):
+ debug(f"[CL] {docname}: {m.group(0)}")
+ # strip link
+ link = m.group(0).partition("(")[2].rpartition(")")[0]
+ # dirs require verification
+ if fileext not in ("\\/", "") or path.isdir(path.join(fulldocdir, link)):
+ link = local_link_to_github(link, docname, githublink)
+ # combine with rest of markdown link
+ link = m.group(0).partition("(")[0] + "(" + link + ")"
+ debug(link)
+ source[0] = source[0][: m.start()] + link + source[0][m.end() :]
+
+ linkexp = linknameexp2 + linktargetexp2.format(fileext=fileext)
+ for m in reversed(list(re.finditer(linkexp, source[0]))):
+ debug(f"[CL] {docname}: {m.group(0).strip()}")
+ # strip link
+ link = m.group(0).rpartition(":")[2].strip()
+ # dirs require verification
+ if fileext not in ("\\/", "") or path.isdir(path.join(fulldocdir, link)):
+ link = local_link_to_github(link, docname, githublink)
+ # combine with rest of markdown link
+ link = m.group(0).partition(":")[0] + ": " + link.strip() + "\n"
+ debug(link)
+ source[0] = source[0][: m.start()] + link + source[0][m.end() :]
diff --git a/openlane/docs/_ext/markdown_cross_doc_section_links.py b/openlane/docs/_ext/markdown_cross_doc_section_links.py
new file mode 100644
index 0000000..f60288c
--- /dev/null
+++ b/openlane/docs/_ext/markdown_cross_doc_section_links.py
@@ -0,0 +1,52 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import re
+from util import debug
+
+
+def setup(app):
+ app.connect("source-read", process_markdown_crosslinks)
+ return {"version": "1.0", "parallel_read_safe": True}
+
+
+def process_markdown_crosslinks(app, docname, source):
+ """
+ Converts markdown links to another doc's section:
+ [link name](./path/doc.md#section)
+ which are not supported by recommonmark
+ to a format recognized by autosectionlabel:
+ [link name](<path/doc:section>)
+ Requires:
+ recommonmark
+ sphinx.ext.autosectionlabel
+ autosectionlabel_prefix_document = True
+ """
+
+ # MD cross-section tag [tag](./dir/file.md#section)
+ linknameexp = r"\[[\/\.\w]*\]"
+ linktargetexp = r"\(\.[\/\.\w]*\.md#\w*\)"
+ linkexp = linknameexp + linktargetexp
+
+ for m in reversed(list(re.finditer(linkexp, source[0]))):
+ link = m.group(0)
+ link = link.replace("(./", "(") # remove './' if present
+ link = link.replace("(", "(<") # change parenthesis
+ link = link.replace(")", ">)") # change parenthesis
+ link = link.replace(".md#", ":") # change section symbol
+ debug(f"[CDL] {docname}: {m.group(0)} to {link}")
+ source[0] = source[0][: m.start()] + link + source[0][m.end() :]
diff --git a/openlane/docs/_ext/toc_from_markdown.py b/openlane/docs/_ext/toc_from_markdown.py
new file mode 100644
index 0000000..b4956b9
--- /dev/null
+++ b/openlane/docs/_ext/toc_from_markdown.py
@@ -0,0 +1,124 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import re
+import os
+import os.path as path
+from util import debug
+
+cleanup_on_finish_files = []
+
+
+def setup(app):
+ app.add_event("create_index_softlink")
+ app.connect("create_index_softlink", index_softlink)
+ app.add_event("toc_from_markdown")
+ app.connect("toc_from_markdown", auto_generate_toc)
+ app.connect("build-finished", after_build_cleanup)
+ return {"version": "1.0", "parallel_read_safe": True}
+
+
+def after_build_cleanup(app, exception):
+ for f in cleanup_on_finish_files:
+ os.remove(path.join(app.srcdir, f))
+ debug(f"[TOC] Deleted {f}.")
+
+
+def extract_markdown_links(file):
+ """Extracts list of local markdown links from markdown file"""
+ # two formats for local markdown file links
+ linknameexp1 = r"\[[\/\.\w]*\]"
+ linktargetexp1 = r"\(\.[\/\.\w]*{fileext}\)"
+ linkexp1 = linknameexp1 + linktargetexp1.format(fileext=r"\.md")
+
+ # case 2 [tag] link
+ linknameexp2 = r"\[[0-9]*\]\:\s*"
+ linktargetexp2 = r"\.[\/\.\w]*{fileext}\s*\n"
+ linkexp2 = linknameexp2 + linktargetexp2.format(fileext=r"\.md")
+
+ links = []
+ try:
+ with open(file, "r") as f:
+ block = f.read()
+ for m in re.finditer(linkexp1, block):
+ link = m.group(0).partition("(")[2].rpartition(")")[0].strip()
+ links.append(link)
+ for m in re.finditer(linkexp2, block):
+ link = m.group(0).rpartition(":")[2].strip()
+ links.append(link)
+ except Exception:
+ debug(f"[TOC] Warning: Failed to process {file}.")
+
+ return links
+
+
+def auto_generate_toc(app, master, tocname, cleanup=False, hidden=True, maxdepth=3):
+ """
+ Automaticaly generate rst file with hidden toc'
+ """
+ global cleanup_on_finish_files
+
+ if cleanup:
+ cleanup_on_finish_files.append(tocname)
+
+ master = path.join(app.srcdir, master)
+ tocname = path.join(app.srcdir, path.basename(tocname))
+ links = [master]
+
+ while maxdepth:
+ newlinks = []
+ for file in links:
+ fromfile = extract_markdown_links(file)
+ newlinks += [
+ path.normpath(path.join(os.path.dirname(file), file_link))
+ for file_link in fromfile
+ ]
+ newlinks = [newlink for newlink in set(newlinks) if newlink not in links]
+ if not len(newlinks):
+ break
+ links += newlinks
+ maxdepth -= 1
+
+ links = [os.path.relpath(abslink, os.path.dirname(tocname)) for abslink in links]
+ links.sort()
+
+ with open(tocname, "w") as f:
+ indent = " "
+ f.write(":orphan:\n\n")
+ f.write(".. toctree::\n")
+ if hidden:
+ f.write(indent + ":hidden:\n")
+ f.write("\n")
+ for link in links:
+ f.write(indent + link + "\n")
+
+
+def index_softlink(app, master, cleanup=False):
+ global cleanup_on_finish_files
+
+ softlink = "index." + master.rpartition(".")[2]
+ if cleanup:
+ cleanup_on_finish_files.append(softlink)
+
+ master = path.join(app.srcdir, master)
+ softlink = path.join(app.srcdir, softlink)
+
+ try:
+ os.symlink(master, softlink)
+ except FileExistsError:
+ os.remove(softlink)
+ os.symlink(master, softlink)
diff --git a/openlane/docs/_ext/util.py b/openlane/docs/_ext/util.py
new file mode 100644
index 0000000..2535369
--- /dev/null
+++ b/openlane/docs/_ext/util.py
@@ -0,0 +1,6 @@
+import os
+
+
+def debug(*args, **kwargs):
+ if os.getenv("SPHINX_BUILD_SILENT") != "1":
+ print(*args, **kwargs)
diff --git a/openlane/docs/_static/eco_flow.png b/openlane/docs/_static/eco_flow.png
new file mode 100644
index 0000000..5986d7f
--- /dev/null
+++ b/openlane/docs/_static/eco_flow.png
Binary files differ
diff --git a/openlane/docs/_static/eco_results.png b/openlane/docs/_static/eco_results.png
new file mode 100644
index 0000000..6da1a23
--- /dev/null
+++ b/openlane/docs/_static/eco_results.png
Binary files differ
diff --git a/openlane/docs/_static/openlane.flow.1.png b/openlane/docs/_static/openlane.flow.1.png
new file mode 100644
index 0000000..a93f715
--- /dev/null
+++ b/openlane/docs/_static/openlane.flow.1.png
Binary files differ
diff --git a/openlane/docs/_static/striVe.jpeg b/openlane/docs/_static/striVe.jpeg
new file mode 100644
index 0000000..6f0066e
--- /dev/null
+++ b/openlane/docs/_static/striVe.jpeg
Binary files differ
diff --git a/openlane/docs/environment.yml b/openlane/docs/environment.yml
new file mode 100644
index 0000000..b247c1a
--- /dev/null
+++ b/openlane/docs/environment.yml
@@ -0,0 +1,22 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+name: openlane-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r ./requirements.txt
diff --git a/openlane/docs/requirements.txt b/openlane/docs/requirements.txt
new file mode 100644
index 0000000..efeed76
--- /dev/null
+++ b/openlane/docs/requirements.txt
@@ -0,0 +1,6 @@
+furo
+docutils
+sphinx
+sphinx-autobuild
+recommonmark
+sphinx_markdown_tables
diff --git a/openlane/docs/source/advanced_power_grid_control.md b/openlane/docs/source/advanced_power_grid_control.md
new file mode 100644
index 0000000..3fe4c6c
--- /dev/null
+++ b/openlane/docs/source/advanced_power_grid_control.md
@@ -0,0 +1,142 @@
+# Power Grid (pdn)
+
+In this document we will discuss the advanced controls for power grid, and how to utilize the already existing [common_pdn.tcl](https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/common_pdn.tcl) for the skywater libraries to automatically power a complex design without the need to write a custom `pdn.tcl` script or learning pdngen syntax.
+
+The power decision flow in this document will go top to bottom, meaning that we will start at the chip level and then go down to the internal macros.
+
+An example utilizing the controls and logic provided in this documentation is the [Caravel Project, version mpw-one-b](https://github.com/efabless/caravel/tree/mpw-one-b).
+
+> **Note**: When we say "your configurations" in this documentation we are refering to the `config.tcl` for that specific block at that specific section.
+
+## Chip Level:
+
+According to the current methodology of [OpenLane Chip Integration][0], the process goes as follows:
+1. Hardening the hard/internal macros.
+2. Hardening the core with the hard macros inside it.
+3. Hardening the full chip with the padframe and the chip core.
+
+Therefore at the top level typically you only have the core block. All you need to do in that step is to verify that the power pads are in the middle of each padframe side, and then add this line to your interactive script: `power_routing` After legalization and before signal routing. However, this only supports a single power domain. Otherwise, you need to manually connect the power pads to the core ring of your core module.
+
+## Core Level:
+
+Let's clarify here, before delving into details, that with each hierarchy level you lose one routing metal layer. For example, in the skywater pdk the metal stack has 5 layers, thus for the core level you can use all layers up to met5; however, if you have another macro inside your core, that macro can only use up to met4, and so forth.
+
+The first decision to make at the core level is the core ring. So first, you need to know how many power domains do you need to use, and so how many core rings do you require. This can be easily set by the following configurations:
+
+```tcl
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+```
+
+Here we're requiring 4 power domains. For each `VDD_NETS` there is a corresponding `GND_NETS`. Those net names must also exist in the RTL and must be connected to each hard macro inside your core explicitly in the RTL, and those must be guarded with the value given to `SYNTH_USE_PG_PINS_DEFINES`. If the internal modules are going to be flattened, then there is no need to reflect this connection in the RTL for those modules that will be flattened with the core module. For the example above, Here is the required RTL reflection:
+
+```verilog
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+```
+
+Then for the hard macro instatiations:
+
+```verilog
+`ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+```
+Note that net and pin names must be matching.
+
+By simply adding these you should now have 8 core rings, 4 for power and 4 for ground. To control the spacing and the power grid for these by changing the following:
+
+```tcl
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3 # The vertical sides width of the core rings
+set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH) # The horizontal sides width of the core rings
+set ::env(FP_PDN_CORE_RING_VOFFSET) 14 # The vertical sides offset from the design boundaries for the core rings
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET) # The horizontal sides offset from the design boundaries for the core rings
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 # The vertical spacing between the core ring straps
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING) # The horizontal spacing between the core ring straps
+```
+
+The next values should be added as-is to control the starting point for looping over the core rings and recalculating the new offset for each core ring:
+
+```tcl
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+```
+
+The next step is to control the internal power grid by changing the following variables:
+
+```tcl
+set ::env(FP_PDN_VWIDTH) 3 # The width of the vertical straps
+set ::env(FP_PDN_HWIDTH) 3 # The width of the horizontal straps
+set ::env(FP_PDN_VOFFSET) 0 # The vertical offset for the straps
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET) # The horizontal offset for the straps
+set ::env(FP_PDN_VPITCH) 180 # The pitch between the vertical straps
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH) # The pitch between the horizontal straps
+```
+
+All values above are given in microns.
+
+At this stage you have automated the power grid generation for the Core Module.
+
+
+## Macro Level
+
+For the skywater libraries the hierarchy typically can go one level down at most otherwise you will only have two routing layers, which is usually not recommended. Therefore, although it's supported, your macros will typically have no nested macros inside them.
+
+To begin the configurations for your macro, you want to announce that the design is a macro inside the core, and that it doesn't have a core ring. Also, prohibit the router from using metal 5 by setting the maximum routing layer to met4. This is done by setting the following configs:
+
+```tcl
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(RT_MAX_LAYER) "met4"
+```
+
+Then, you should use the same `VDD_NETS` and `GND_NETS` set in the core level by adding these two lines to your `config.tcl`:
+
+```tcl
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+```
+
+This should also reflected in the module declaration in that macro's RTL in the same manner as follows:
+
+```verilog
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+```
+
+These should match the names used in your core level. You don't need to use all the nets, the first two nets are used by default to power the digital cells. So you may want to only include a subset of these connections, this should be reflected in the configuartions as well as the RTL.
+
+- The height of each macro must be greater than or equal to the value of `$::env(FP_PDN_HPITCH)` to allow at least two metal 5 straps on the core level to cross it and all the dropping of a via from met5 to met4 connecting the vertical straps of the macro to the horizontal straps of the core and so connect the power grid of the macro to the outer core ring.
+
+
+
+At this stage, hardening the macros first, followed by the core, and finally connecting the core rings to the power pads, your power grids and connections should be complete.
+
+
+[0]: ./chip_integration.md
diff --git a/openlane/docs/source/advanced_readme.md b/openlane/docs/source/advanced_readme.md
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+## Interactive Mode
+You may run the flow interactively by using the `-interactive` option:
+
+```
+./flow.tcl -interactive
+```
+
+A tcl shell will be opened where the openlane package is automatically sourced:
+```
+% package require openlane
+```
+
+Then, you should be able to run the following main commands:
+
+0. Any tcl command.
+1. `prep -design <design> -tag <tag> -config <config> -init_design_config -overwrite` similar to the command line arguments, design is required and the rest is optional
+2. `run_synthesis`
+3. `run_floorplan`
+4. `run_placement`
+5. `run_cts`
+6. `run_routing`
+7. `write_powered_verilog` followed by `set_netlist $::env(routing_logs)/$::env(DESIGN_NAME).powered.v`
+8. `run_magic`
+9. `run_magic_spice_export`
+10. `run_magic_drc`
+11. `run_lvs`
+12. `run_antenna_check`
+
+
+The above commands can also be written in a file and passed to `flow.tcl`:
+
+```
+./flow.tcl -interactive -file <file>
+```
+
+A more detailed list of all the commands supported by openlane could be found [here][0].
+
+**Note 1:** Currently, configuration variables have higher priority over the above commands so if `RUN_MAGIC` is 0, command `run_magic` will have no effect.
+
+**Note 2:** Currently, most of these commands must be run in the flow sequence and no steps should be skipped.
+
+**Note 3:** You can pass the -design, -tag, etc.. flags to ```./flow.tcl -interactive``` directly without the need of entering the interactive mode and then executing the prep command.
+
+[0]:./openlane_commands.md
+
diff --git a/openlane/docs/source/chip_integration.md b/openlane/docs/source/chip_integration.md
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+++ b/openlane/docs/source/chip_integration.md
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+**DISCLAIMER: THIS PAGE IS STILL UNDER DEVELOPMENT.**
+**THE INFORMATION HERE MIGHT BE INCORRECT OR OUTDATED.**
+
+# Chip Integration
+
+Using openlane, you can produce a GDSII from a chip RTL.
+
+
+## The current Methodology
+
+The current methodology views the chip using the following hierarchy:
+- Chip Core
+ - The hard macros
+ - The rest of the design
+- Chip IO
+ - IO Pads
+ - Power Pads
+ - Corener Pads
+
+The current methodology goes as follows:
+1. Hardening the hard macros.
+2. Hardening the core with the hard macros inside it.
+3. Hardening the padframe
+4. Hardening the full chip with the padframe.
+
+
+## Hardening The Macros
+
+This is discussed in more detail [here][8].
+
+## Hardening The Core
+
+The chip core would usually have other macros inside it.
+
+You need to set the following environment variables in your `config.tcl` file for the chip core:
+- `::env(VERILOG_FILES)` To point at the used verilog files; those that were not previously hardened.
+- `::env(VERILOG_FILES_BLACKBOX)` To point at the blackboxes (the hardened macros).
+- `::env(EXTRA_LEFS)` To point at the LEF files of the hardened macros.
+- `::env(EXTRA_GDS_FILES)` To point at the GDS files of the hardened macros.
+
+Therefore, the verilog files shouldn't have any includes in any of your verilog files. But use `::env(VERILOG_FILES)` and `::env(VERILOG_FILES_BLACKBOX)` for that purpose.
+
+Add `set ::env(SYNTH_READ_BLACKBOX_LIB) 1`, if you have std cells hard coded in your RTL.
+
+You can follow the same instructions provided [here][8] for the rest of the hardenning steps.
+
+In case you want to manually place the macros in specific locations, [this][9] should provide a good example on how to do it. This is done by creating a configuration file containing an endline separated list of `instance_name X_pos Y_pos Orientation` and pointing to it with this configuartion: `::env(MACRO_PLACEMENT_CFG)`.
+
+[Here][0] you can find a list of all the available OpenLane configuartions.
+
+Check this [section](#power-routing) for more details on power routing setup.
+
+## Hardening The Full Chip
+
+
+The full chip requires an [interactive script][2] to harden. You could take this [full chip][5] as an example.
+
+First you need to harden the padframe as a separate macro, check [this flow][4] as an example on how to do so.
+
+You need to set the following environment variables in your `config.tcl` file for the chip:
+- `::env(VERILOG_FILES)` To point at the used verilog files; those that were not previously hardened. Ideally, this should be only one file.
+- `::env(VERILOG_FILES_BLACKBOX)` To point at the blackboxes (the hardened macros). Ideally, this should include all the other verilog files.
+- `::env(EXTRA_LEFS)` To point at the LEF files of the hardened core macro.
+- `::env(EXTRA_GDS_FILES)` To point at the GDS files of the hardened core macro.
+
+Therefore, the verilog files shouldn't have any includes in any of your verilog files. But use `::env(VERILOG_FILES)` and `::env(VERILOG_FILES_BLACKBOX)` for that purpose.
+
+Add `set ::env(SYNTH_READ_BLACKBOX_LIB) 1`, if you have std cells hard coded in your RTL.
+
+Add `set ::env(SYNTH_FLAT_TOP) 1` to your `config.tcl`. To flatten the padframe, if it's presented in a `chip_io` module, otherwise you can harden it separately as indicated in [this flow][4].
+
+The following inputs are provided to produce the final GDSII:
+
+1. Padframe cfg file (provided by the user or generated by padring). [Here][6] is an example. Or a hardened chip_io.gds and chip_io.lef following [this][4].
+2. Hardened lef & GDS-II for the core module, generated [here](#hardening-the-core)
+3. Top level netlist instantiating pads and core module (Could be provided by the user or generated by [topModuleGen][7])
+
+[The interactive script for the IOs][4] does the following:
+- Sources configurations.
+- Elaborates the verilog.
+- Runs floorplan.
+- Uses padringer.py to generate the padframe.
+- Adds the obstructions to the core area, and removes core nets and pins.
+- Routes.
+- Streams out the GDS-II and the LEFv view.
+
+Given these inputs the following [interactive script][5] script. Mainly, it does the following steps:
+- Runs the top level netlist through yosys.
+- Runs floorplan.
+- Performs manual placement of the core macros, this sample has many cores, however for full automation you should have only a single core.
+- legalize the placement.
+- Removes Nets and Pins to a different file.
+- This stages is skipped because the design has many cores and so fully automated power routing is not possible. However if you only have a single core, you can perform automatic power routing by adding `power_routing` at this stage in your interactive script.
+- Route the design.
+- Perform power routing.
+- Generate a GDSII file of the routed design.
+- Run DRC and LVS checks [here][11].
+
+## Power_routing
+
+### Macros:
+
+This is discussed in detail [here][8].
+
+### Core:
+
+It should have an `stdcell` section that includes a `core_ring` on met4 and met5. It should use met5 and met4 for the straps, and met1 for the rails. Thus, make sure to add these to your config file:
+
+```tcl
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 1
+```
+
+You can automate the power routing process in the core and macro level by reading [this documentation][10]. Otherwise, refer to [this][3] for more details about the syntax. In case you needed to create your own `pdn.tcl` then point to it using `PDN_CFG`.
+
+When you use the `power_routing` command in the chip interactive script, the power pads will be connected to the core ring, and thus the whole chip would be powered.
+
+## General Notes:
+
+[This][2] includes more guidance on how to create an interactive script.
+
+[This][0] documents all OpenLane configurations.
+
+[This][1] has a description for all OpenLane commands.
+
+[0]: ./../../configuration/README.md
+[1]: ./openlane_commands.md
+[2]: ./advanced_readme.md
+[3]: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/doc/PDN.md
+[4]: https://github.com/efabless/caravel/blob/mpw-one-b/openlane/chip_io/interactive.tcl
+[5]: https://github.com/efabless/caravel/blob/mpw-one-b/openlane/caravel/interactive.tcl
+[6]: https://github.com/efabless/caravel/blob/mpw-one-b/openlane/chip_io/padframe.cfg
+[7]: ./../../scripts/topModuleGen/README.md
+[8]: ./hardening_macros.md
+[9]: https://github.com/efabless/openlane/tree/master/designs/manual_macro_placement_test
+[10]: ./advanced_power_grid_control.md
+[11]: https://github.com/efabless/caravel/blob/mpw-one-b/openlane/caravel/interactive.lvs.tcl
diff --git a/openlane/docs/source/eco_flow.md b/openlane/docs/source/eco_flow.md
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+# The ECO Flow (Alpha)
+The ECO flow starts from checking the report generated in the route step. A python script is used to check the report, insert buffers, and do the resize. Inside the ECO loop, the python script, cts and route step are called sequentially. The reports are generated each time, and the loop stops until no hold time violations are found. See overview diagram below:
+
+
+
+# Flow to Insert Buffer
+1. Run the OL flow
+2. Hold violations will be present in the log files
+3. Run gen_insert_buffer.py, using regex to get the `pinname`
+4. Generate the command `insert_buffer {pin_name master_name net_name inst_name}`
+5. Generate the command `size_cell {inst_name new_master_name}` to adjust the path delay. (`sky130_fd_sc_hd__dlygate4sd3_1` is the master with the longest delay, larger number at the end means shorter delay)
+6. Rerun the STA and route step
+7. Repeat 1-6 till all hold violations are solved.
+Given a routing report, we first parse the reports into several sections. Each section contains one path. Then, regular expressions are used to detect if the path is `VIOLATED`. If the path has hold time violations, we save the slack and corresponding startpoint into a vector. The type of the buffer is `sky130_fd_sc_hd__dlygate4sd3_1`, so the number of the buffer to be inserted should be the minimum slack divided by FO1 delay. Finally, we dump all the `insert_buffer `commands into a tcl file.
+
+# Insert Buffer Command
+1. Find the violation’s startpoint
+2. Create the buffer and nets
+3. Disconnect the original nets (slightly different for reg-to-reg and pin-to-reg cases)
+4. Place the buffer
+5. Connect new nets (slightly different for reg-to-reg and pin-to-reg cases)
+We realize all the operations with OpenDB commands. When we insert the buffer, we move the old net together with the startpoint, - the net name should be the same with the pin name and cannot be changed. In OpenDB. `connect` and `disconnect` functions are `class static` for `reg` cases and regular member methods for pin cases. For `reg ` cases, we also need to specify which port (input or output) to disconnect the line from.
+
+# Testcase Results
+We tested the latest OpenLane with ECO on the LiteX Management Core [rc-8 ](https://github.com/efabless/caravel_mgmt_soc_litex/releases/tag/rc-8) release. All the timing reports are generated by OpenSTA.
+
+For the 1st iteration, the design has 131 hold violations with a -1.48 worst case slack. Our ECO inserts 219 buffers into the block, which greatly reduces the number of violations. After 10 iterations, all the violations are solved and setup time is not influenced during this process.
+The following table shows the timing results of the ECO flow for each ECO iteration:
+
+
+
+
+
+# How to enable the ECO flow
+If the user would like to enable this step, they would have to set the ECO_ENABLE environment variable to 1 as follows:
+
+```tcl
+ set ::env(ECO_ENABLE) {1}
+```
+
+Or they can invoke OpenLane with the option `-override_env ECO_ENABLE=1`.
diff --git a/openlane/docs/source/hardening_macros.md b/openlane/docs/source/hardening_macros.md
new file mode 100644
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+++ b/openlane/docs/source/hardening_macros.md
@@ -0,0 +1,239 @@
+# Hardening Macros
+
+Using openlane, you can produce a GDSII from an RTL for macros, and then use these macros to create your chip. Check [this][4] for more details about chip integration.
+
+In this document we will go through the hardening steps and discuss in some detail what considerations should be made when hardening your macro.
+
+**NOTE:** For all the configurations mentioned in this documentation and any other openlane configurations, you can use the exploration script `run_designs.py` to find the optimal value for each configuration for your design. Read more [here][6].
+
+## Base Requirements:
+
+You should start by setting the basic configuration file for your design. Check [this][5] for how to add your new design.
+
+The basic configurations `config.tcl` should at least contain:
+```tcl
+set ::env(DESIGN_NAME) <the name of the design>
+
+set ::env(VERILOG_FILES) <pointer to the verilog source(s) of the design>
+set ::env(CLOCK_PORT) <list of clock ports in the design rtl>
+set ::env(DESIGN_IS_CORE) 0 # Since you are hardening a macro.
+```
+
+If you are hardening the chip core. Then make sure to set `::env(DESIGN_IS_CORE)` to `1` and check [this][4] for more details about chip integration.
+
+In case your design doesn't have a clock port, then you can either omit ::env(CLOCK_PORT) or give it an empty string.
+
+These configurations should get you through the flow with the all other configurations using openlane default values, read about those [here][0]. However, in the coming sections we will take a closer look on how to determine the best values for most of the other configurations.
+
+## Synthesis
+
+The first decision in synthesis is determining the optimal synthesis strategy `::env(SYNTH_STRATEGY)` for your design. For that purpose there is a flag in the `flow.tcl` script, `-synth_explore` that runs a synthesis strategy exploration and reports the results in a table under `<run_path>/reports/`.
+
+Then you need to consider the best values for the `SYNTH_MAX_FANOUT`.
+
+If your macro is huge (200k+ cells), then you might want to try setting `SYNTH_NO_FLAT` to `1`, which will postpone the flattening of the design during synthesis until the very end.
+
+Other configurations like `SYNTH_SIZING`, `SYNTH_BUFFERING`, and other synthesis configurations don't have to be changed. However, the advanced user can check [this][0] documentation for more details about those configurations and their values.
+
+## Static Timing Analysis
+
+Static Timing Analysis happens multiple times during the flow. However, they all use the same base.sdc file. You can control the outcome of the static timing analysis by setting those values:
+
+1. The clock ports in the design, explained in the base requirements section `CLOCK_PORT`.
+
+2. The clock period that you prefer the design to run with. This could be set using `::env(CLOCK_PERIOD)` and the unit is ns. It's important to note that the flow will use this value to calculate the worst and total negative slack, also if timing optimizations are enabled, it will try to optimize for it and give suggested clock period at the end of the run in `<run-path>/reports/metrics.csv` This value should be used in the future to speed up the optimization process and it will be the estimated value at which the design should run.
+
+3. The IO delay percentage from the clock period `IO_PCT`. More about that [here][0].
+
+4. You may want to write a custom SDC file to be used in STA and CTS. The default SDC file in the flow is [this file][11]. However, you can change that by pointing to a new file with the environment variable `BASE_SDC_FILE`. More about that [here][0].
+
+Other values are set based on the (PDK, STD_CELL_LIBRARY) used. You can read more about those configurations [here][0].
+
+Static Timing Analysis are done after:
+
+1. Synthesis using the verilog netlist.
+
+2. Placement using OpenROAD's estimate_parasitics.
+
+3. Timing optimizations using the verilog netlist.
+
+4. Global Routing using OpenROAD's estimate_parasitics.
+
+5. Detailed Routing using SPEF extraction and the verilog netlist.
+
+For SPEF extraction, you can control the wire model and the edge capacitance factor through these variables `SPEF_WIRE_MODEL` and `SPEF_EDGE_CAP_FACTOR`.
+
+More about that [here][0].
+
+## Floorplan
+
+During Floor plan, you have one of three options:
+
+1. Let the tools determine the area relative to the size and number of cells. This is done by setting `FP_SIZING` to `relative` (the default value), and setting `FP_CORE_UTIL` as the core utilization percentage. Also, you can change the aspect ratio by changing `FP_ASPECT_RATIO`.
+
+2. Set a specific DIE AREA by making `FP_SIZING` set to `absolute` and then giving the size as four coordinates to `DIE_AREA`.
+
+3. Use a template DEF and apply the same DIE AREA and dimensions of that DEF. Note that this option will also force the flow to use the same PIN locations and PIN names (they are copied over from the template DEF). To use this option set: `FP_DEF_TEMPLATE` to point to that DEF file.
+
+You can read more about how to control these variables [here][0].
+
+
+## IO Placement
+
+For IO placement, you currently have four options:
+
+1. Using a template DEF file and applying the same PIN locations and PIN names (they are copied over from the template DEF). Note that this will force the flow to apply the same exact DIE AREA and dimensions of the template DEF. To use that option set: `FP_DEF_TEMPLATE` to point to that DEF file.
+
+2. Manually setting the direction of each pin using a configuration file such as [this one][7]. Then you need to set `FP_PIN_ORDER_CFG` to point to that file.
+
+3. Using contextualized pin placement, which will automatically optimize the placement of the pins based on their context in the larger design that includes them. This relevant for macros since they will be included inside a core, and also relevant for the core since it will be part of a bigger chip. For this to happen, you need to point to the LEF and DEF of the container/parent design using these two variables: `FP_CONTEXT_DEF` and `FP_CONTEXT_LEF`. Note that currently this script can only handle the existance of a single instance of that macro.
+
+4. To let the tool randomly assign IOs using the random equidistant mode. This is the default way.
+
+The options are prioritized based on the order mentioned above. This means that if you set a value for `FP_DEF_TEMPLATE` it will be used and the rest - if they exist - will be ignored.
+
+You can read more about those configurations [here][0].
+
+## Placement
+
+Placement is done in three steps: Global Placement, Optimizations, and Detailed Placement.
+
+### Global Placement:
+
+For Global Placement, the most important value would be `PL_TARGET_DENSITY` which should be easy to set.
+
+- If your design is not a tiny design, then `PL_TARGET_DENSITY` should have a value that is `FP_CORE_UTIL` + 1~5%. Note that `FP_CORE_UTIL` has a value from 0 to 100, while `PL_TARGET_DENSITY` has a value from 0 to 1.0.
+
+- If your design is a tiny design, then you may need to set `PL_RANDOM_GLB_PLACEMENT` to `1` or `PL_RANDOM_INITIAL_PLACEMENT` to 1. Also, `PL_TARGET_DENSITY` should have high value, while `FP_CORE_UTIL` should have a low value. (i.e `PL_TARGET_DENSITY` set to 0.5 and `FP_CORE_UTIL` set to 5). In very tiny designs (i.e. 1 std cell designs), the approximated DIE AREA in the floorplan stage may not leave enough room to insert tap cells in the design. Thus, it's recommended to use `FP_SIZING` as `absolute` and manually setting an appropriate `DIE_AREA`, check [the floorplan section](#floorplan) for more details. You may also want to reduce the values for `FP_PDN_HORIZONTAL_HALO` and `FP_PDN_VERTICAL_HALO`. You can read more about those [here][0].
+
+Other values to be considered are `PL_BASIC_PLACEMENT` and `PL_SKIP_INITIAL_PLACEMENT`, you can read more about those [here][0].
+
+### Optimizations:
+
+For this step we rely on Resizer and OpenPhySyn.
+
+#### Resizer optimizations:
+
+The only optimization we use from resizer is the wire length optimization which is used to reduce the antenna violations. This is disabled by default since the diode insertion strategies should cover that purpose.
+
+However, you can enable that by setting `PL_RESIZER_OVERBUFFER` to `1` and then determine the maximum wire length by setting this value `MAX_WIRE_LENGTH`.
+
+### Detailed Placement:
+
+The only value to consider here is the `CELL_PAD` which is usually selected for each (PDK,STD_CELL_LIBRARY) and should mostly be left as is. However, typically for the skywater libraries the value should be 4~6.
+
+You can read more about that [here][0].
+
+## Clock Tree Synthesis
+
+Most of the values for clock tree synthesis are (PDK, STD_CELL_LIBRARY) specific and you can read more about those [here][8].
+
+You can disable it by setting `CLOCK_TREE_SYNTH` to `0`.
+
+If you don't want all the clock ports to be used in clock tree synthesis, then you can use set `CLOCK_NET` to specify those ports. Otherwise, `CLOCK_NET` will be defaulted to the value of `CLOCK_PORT`.
+
+## Power Grid (pdn)
+
+You can skip reading this section and jump ahead to reading the advanced power grid controls to get an overall vision of how the whole chip would be powered and as such make a more educated decision in this stage. This detailed documentation exists [here][9].
+
+Each macro in your design should configure the `common_pdn.tcl` for it's use. Generally, you want to announce that the design is a macro inside the core, and that it doesn't have a core ring. Also, prohibit the router from using metal 5 by setting the maximum routing layer to met4. This is done by setting the following configs:
+
+```tcl
+set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(RT_MAX_LAYER) "met4"
+```
+
+Pdngen configs for macros contain a special stdcell section, instead of the one used for the core in the `common_pdn.tcl`. The purpose of this is to prohibit the use of metal 5 in the power grid of the macros and use it exclusively for the core and top level.
+
+If your macro contains other macros inside it, then make sure to check the `macro` section and see if it requires any modifications for each of them depending on their special configs. The following example is using default `connect` section but a different `straps` section:
+```tcl
+pdngen::specify_grid macro {
+ orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
+ power_pins "vpwr"
+ ground_pins "vgnd"
+ straps {
+ met1 {width 0.74 pitch 3.56 offset 0}
+ met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ }
+ connect {{met1 met4}}
+}
+```
+
+**WARNING:** only use met1 and met4 for rails and straps.
+
+Refer to [this][3] for more details about the syntax in case you needed to create your own `pdn.tcl` and then point to it using `::env(PDN_CFG)`.
+
+- The height of each macro must be greater than or equal to the value of `$::env(FP_PDN_HPITCH)` to allow at least two metal 5 straps on the core level to cross it and all the dropping of a via from met5 to met4 connecting the vertical straps of the macro to the horizontal straps of the core and so connect the power grid of the macro to the outer core ring.
+
+If your design is a core, then check the power routing section in the [chip integration documentation][4]. However, the basic thing you'll need to do is to announce that your design is a chip core and that it should have a core ring. This is done by setting the following values:
+
+```tcl
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 1
+```
+
+For more details about power grid control automation at the core and macro level and using multiple power domains please check [this documentation][9].
+
+## Diode Insertion
+
+Here, you have four options to choose from and they are controlled by setting `DIODE_INSERTION_STRATEGY` to one of the following values: (0, 1, 2, 3, 4, 5)
+
+0. No diode insertion is done.
+
+1. A diode is inserted for each PIN and connected to it.
+
+2. A fake diode is inserted for each PIN and connected to it, then after an antenna check is run and the fake diodes are replaced with real ones if the pin is violated.
+
+3. Rely on OpenROAD:FastRoute antenna avoidance flow to insert the diodes during global routing by using the Antenna Rule Checker and fixing violations. You can execute this iteratively by setting `GLB_RT_MAX_DIODE_INS_ITERS`, it is capable to detect any divergence, so, you'll probably end up with the lowest # of Antenna violations possible.
+
+4. A smarter version of strategy 1 that attempts to reduce the number of inserted diodes and places a diode at each design pin.
+
+5. A variant of 2 utilizing the script used in strategy 4.
+
+You can read more about those configurations [here][0].
+
+## Routing
+
+The configurations here were optimized based on a large design set and are best left as is, however the advanced user could refer to [this documentation][0] to learn more about each used configuration and how to change it.
+
+You are advised to change `ROUTING_CORES` based on your CPU capacity to specify the number of threads that TritonRoute can run with to perform Detailed Routing in the least runtime possible.
+
+## GDS Streaming
+
+The configurations here were selected based on a large design test set and the consulation of the magic sources; therefore they are best left as is. However, for the curious user, refer to [this documentation][0] to learn more about each used configuration and how to change it.
+
+## Final Reports and Checks
+
+Finally, the flow ends with physical verification. This begins by streaming out the GDS followed by running DRC, LVS, and Antenna checks on the design. Then, it produces a final summary report in csv format to summarize all the reports.
+
+You can control whether the magic DRC should be done on GDS-II or on LEF/DEF abstract views. We recommend using GDS-II on macros while using LEF/DEF on the chip level. This should speed up the run process and still give results as accurate as possible. This is controlled by `MAGIC_DRC_USE_GDS`.
+
+You can run Antenna Checks using OpenROAD ARC or magic. This is controlled by `USE_ARC_ANTENNA_CHECK`. The magic antenna checker was more reliable at the time of writing this documentation but it comes with a huge runtime trade-off and the accuracy gain is not significant enough to accept that tradeoff; thus, the default is OpenROAD's ARC.
+
+You can control whether LVS should be run down to the device level or the cell level based on the type of the extraction. If you perform extraction on GDS-II then it's going to be down to the device/transistor level, otherwise using the LEF/DEF views then it's going to be down to the cell/block level. This is controlloed by `MAGIC_EXT_USE_GDS`.
+
+You can enable LEC on the different netlists by setting `LEC_ENABLE` to one, which should run logic verification after writing each intermediate netlist.
+
+A final summary report is produced by default as `<run-path>/reports/metrics.csv`, for more details about the contents of the report check [this documentation][10].
+
+A final manufacturability report is produced by default as `<run-path>/reports/manufacturability_report.csv`, this report contains the magic DRC, the LVS, and the antenna violations summaries.
+
+The final GDS-II should be found under `<run-path>/results/magic/`.
+
+To integrate that macro into a core or a chip, check this [documentation on chip integration][4].
+
+If you want to create further tweaks in the flow that the abundant configurations don't allow, make sure to check [this][2] for more details about the interactive mode of the OpenLane flow.
+
+[0]: ./../../configuration/README.md
+[1]: ./openlane_commands.md
+[2]: ./advanced_readme.md
+[3]: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/doc/PDN.md
+[4]: ./chip_integration.md
+[5]: ./../../designs/README.md
+[6]: ./../../regression_results/README.md
+[7]: https://github.com/efabless/openlane/blob/master/designs/spm/pin_order.cfg
+[8]: ./PDK_STRUCTURE.md
+[9]: ./advanced_power_grid_control.md
+[10]: ./../../regression_results/columns_defintions.md
+[11]: ./../../scripts/base.sdc
diff --git a/openlane/docs/source/issue_regression_tests.md b/openlane/docs/source/issue_regression_tests.md
new file mode 100644
index 0000000..36a3b4b
--- /dev/null
+++ b/openlane/docs/source/issue_regression_tests.md
@@ -0,0 +1,8 @@
+# Issue regression tests
+Issue regression tests are used to test issues that happened in the past, that might return by changes introduced in the future. Regression testing also allows to extend the options/configs that is not covered currently. To run issue regression flow execute `make issue_regression_all` outside of docker image.
+
+# Issue regression tests flow
+
+Another type of checks is intentionally broken test cases which test the OpenLane's ability to warn user about possible issues. Example issue is: `issue_912_def_test_missaligned`. Entry point is `run_issue_regressions.py` which will run all designs matching `designs/issue_*` pattern. After the run was compeleted with or without errors or fails, then for that design `issue_regression.py` is ran in OpenROAD Python environment. If flow failed and `issue_regression.py` does not exist, then issue regression failed. As `-run_hooks` will run only after successful flow, but the `issue_regression.py` will be ran in both failed and successful case. OpenLane users may want to use `-run_hooks`, while issue_regression is designed to be used only by regression flow.
+
+If `-run_hooks` is specified, after a successful flow run `hooks/post_run.py` script is run. Script may contain any checks required. Multiple issues can be covered by single script. As a reference `issue_892_def_test` can be used.
diff --git a/openlane/docs/source/local_installs.md b/openlane/docs/source/local_installs.md
new file mode 100644
index 0000000..d43657a
--- /dev/null
+++ b/openlane/docs/source/local_installs.md
@@ -0,0 +1,27 @@
+**NOTE: It is more complex to set up OpenLane without a Docker container. If you are a novice user, it is recommended to use the Docker container.**
+
+# Using OpenLane without Docker
+At its core, OpenLane is a set of scripts working with a set of tools. If you'd like to avoid using a Docker container, you can, but you will have to set up all of the tools required by OpenLane on your computer. We do provide a script to assist you with that.
+
+# Base Requirements
+* Python 3.6+ with PIP
+* pyyaml, venv: `python3 -m pip install pyyaml venv`
+
+# Tool Library
+You can run `python3 ./env.py tool-list` for a list. There are at least a dozen tools to install here. Luckily, you don't have to install them all one-by-one: There is an installation script that installs most of them.
+
+You can invoke `python3 ./env.py local-install`. This tool copies the skeleton and installs all the tools to `$OPENLANE_ROOT_DIR/install`. Furthermore, if you are on CentOS 7, macOS or Ubuntu 20.04, the installer will offer to install all the required apt, yum or brew packages for you.
+
+The tools will all be installed with `./install` as a prefix. You'll find all the repos in `./install/build/repos` and a list of versions in `./install/build/versions`.
+
+**DO NOTE:** We expect you to get some tools on your own, because said tools are too complex to build in an automated fashion. Namely:
+* OpenROAD
+* Klayout
+* Git 2.34+
+
+After the installer is done, you can simply invoke `./flow.tcl` outside of Docker and it should work okay.
+
+# More about how this works
+`flow.tcl` looks for a file called `./install/env.tcl` before it does anything. If it finds it, it sources it. The `./install` directory is aliased in Docker environments, which already have the proper tools installed.
+
+`./install/env.tcl` contains the necessary environment variables to add the installed tools to PATH and activate the Python virtual environment.
\ No newline at end of file
diff --git a/openlane/docs/source/manual_pdk_installation.md b/openlane/docs/source/manual_pdk_installation.md
new file mode 100644
index 0000000..96b2c5a
--- /dev/null
+++ b/openlane/docs/source/manual_pdk_installation.md
@@ -0,0 +1,58 @@
+**DISCLAIMER: The following sections are to give you an understanding of what happens under the hood in the Makefile.**
+
+# Prerequisites
+
+ - [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) is needed to run open_pdks -- version >= 8.3.60*
+
+# Setting up the PDK: skywater-pdk
+
+- Clone and build at least one [skywater-pdk](https://github.com/google/skywater-pdk) standard cell Library inside the pdks directory:
+ - To setup one standard cell library only
+
+ ```bash
+ export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>
+ cd $PDK_ROOT
+ git clone https://github.com/google/skywater-pdk.git
+ cd skywater-pdk
+ git checkout 00bdbcf4a3aa922cc1f4a0d0cd8b80dbd73149d3
+ git submodule update --init libraries/sky130_fd_sc_hd/latest
+ git submodule update --init libraries/sky130_fd_sc_hvl/latest
+ git submodule update --init libraries/sky130_fd_io/latest
+ make timing
+ ```
+ - To setup other SCLs:
+ - replace sky130_fd_sc_hd with any of the following list:
+ - sky130_fd_sc_hs
+ - sky130_fd_sc_ms
+ - sky130_fd_sc_ls
+ - sky130_fd_sc_hdll
+
+- Setup the configurations and tech files for Magic, Netgen, OpenLane using [open_pdks](https://github.com/RTimothyEdwards/open_pdks):
+
+ ```bash
+ cd $PDK_ROOT
+ git clone git://opencircuitdesign.com/open_pdks
+ cd open_pdks
+ git checkout d8c159536699c9b4a08b650bddf791a9d48152f9
+ ./configure --enable-sky130-pdk=$PDK_ROOT/skywater-pdk/libraries --with-sky130-local-path=$PDK_ROOT --enable-sram-sky130=disabled
+ cd sky130
+ make
+ make install-local
+ ```
+
+**Note**: You can use different directories for sky130-source and local-path. However, in the instructions we are using $PDK_ROOT to facilitate the installation process
+
+**WARNING**: Please, don't move `sky130A` from the installed directory because the generated .mag files contain absolute paths. Moving it will result in producing an invalid GDS.
+
+ - To set the STD_CELL_LIBRARY (the default value is set to sky130_fd_sc_hd)
+ - Open [configuration/general.tcl](../../configuration/general.tcl)
+ - set STD_CELL_LIBRARY to one of the following:
+
+ - sky130_fd_sc_hs
+ - sky130_fd_sc_ms
+ - sky130_fd_sc_ls
+ - sky130_fd_sc_hdll
+
+Refer to [this][1] for more details on the structure.
+
+[1]: ./PDK_STRUCTURE.md
diff --git a/openlane/docs/source/openlane_commands.md b/openlane/docs/source/openlane_commands.md
new file mode 100644
index 0000000..7a49df6
--- /dev/null
+++ b/openlane/docs/source/openlane_commands.md
@@ -0,0 +1,369 @@
+# OpenLane Interactive Mode Commands
+
+This page describes the list of commands available in openlane, their functionality, and their expected inputs and outputs.
+
+**NOTE:** You must run the `prep` command before running any of the other commands, in order to have the necessary files and configurations loaded.
+
+The Following list is available in the interactive mode: `./flow.tcl -interactive` and under:
+```
+% package require openlane 0.9
+```
+Which runs automatically when you enter the interactive mode.
+
+
+## General Commands
+
+Most of the following commands' implementation exists in this [file][0]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `set_netlist <netlist>` | | Sets the current netlist used by the flow to `<netlist>` |
+| | `[-lec]` | Runs logic verification for the new netlist against the previous netlist. <br> Optional flag. |
+| `set_def <def>` | | Sets the current def file used by the flow to `<def>` |
+| `prep_lefs` | | prepares the used lef files by the flow. This process includes merging the techlef and cells lef, generated a merged.lef and a merged_unpadded.lef. Both to be used by different stages of the flow.|
+| `trim_lib` | | prepares a liberty file (i.e. `LIB_SYNTH`) by trimming the `NO_SYNTH_CELL_LIST` and `DRC_EXCLUDE_CELL_LIST` from another input liberty file (i.e. `$::env(LIB_SYNTH_COMPLETE)`). |
+| | `[-output <lib_file>]` | The lib file to output the trimmed liberty into. <br> Default: `$::env(LIB_SYNTH)` <br> Optional flag. |
+| | `[-input <lib_file>]` | The input liberty file to trim the cells from. <br> Default: `$::env(LIB_SYNTH_COMPLETE)` <br> Optional flag. |
+| | `[-drc_exclude_only]` | If provided, it will only use `DRC_EXCLUDE_CELL_LIST` to create the exclude list. <br> Optional flag. |
+| `gen_exclude_list` | | generates an exclude list file for a liberty file (i.e. `LIB_SYNTH`) by concatenating the `NO_SYNTH_CELL_LIST` and `DRC_EXCLUDE_CELL_LIST` into the output file. |
+| | `-lib <lib_file_path>` | The lib file that the list will be trimmed from. This will general a `<-lib>.exclude.list` |
+| | `[-drc_exclude_only]` | If provided, it will only use `DRC_EXCLUDE_CELL_LIST` to create the exclude list. <br> Optional flag. |
+| | `[-create_dont_use_list]` | If provided, it will create an environment variable with the file content. The variable will be named `DONT_USE_CELLS`. <br> Optional flag. |
+| `source_config <config_file>` | | Sources the configurations inside `<config_file>`, whether it is a tcl file or a json file.|
+| `prep` | | Prepares a run in openlane or loads a previously stopped run in order to proceed with it. It calls `trim_lib`, `prep_lefs`, `source_config`, and other procs to set all the needed environment variables.<br> It has similar flags to ./flow.tcl. |
+| | `-design <design_name>` | Specifies the design folder. A design folder should contain a config.tcl definig the design parameters. <br> If the folder is not found, ./designs directory is searched.|
+| | `[-overwrite]` | Flag to overwirte an existing run with the same tag. <br> Optional flag. |
+| | `[-run_path <path>]` | Specifies a <code>path</code> to save the run in. By default the run is in <code>design_path/</code>, where the design path is the one passed to <code>-design</code> <br> Optional flag. |
+| | `[-tag <tag>]` | Specifies a <code>name</code> for a specific run. If the tag is not specified, a timestamp is generated for identification of that run. <br> Can Specify the configuration file name in case of using <code>-init_design_config</code>. <br> Optional flag. |
+| | `[-init_design_config]` | Creates a tcl configuration file for a design. <code>-tag <name></code> can be added to rename the config file to <code><name>.tcl</code>. <br> Optional flag.|
+| | `[-src <verilog_source>]` | Sets the verilog source code file(s) in case of using `-init_design_config`. The default is that the source code files are under <code>design_path/src/</code>, where the design path is the one passed to <code>-design</code>. <br> Optional flag. |
+| | `[-config_tag <config_tag>]` | Specifies the design's configuration file for running the flow. <br> For example, to run the flow using <code>designs/spm/config2.tcl</code> <br> Use run <code>./flow.tcl -design spm -config_tag config2.tcl</code> <br> By default <code>config.tcl</code> is used. <br> Optional flag. |
+| | `[-config_file <config_file>]` | Specifies the design's configuration file for running the flow. <br> For example, to run the flow using <code>/spm/config2.tcl</code> <br> Use run <code>./flow.tcl -design /spm -config_file /spm/config2.tcl</code> <br> By default <code>config.tcl</code> is used. <br> Optional flag. |
+| | `[-verbose <level>]` | Sets a verbose output level. 0 disables verbose information and tool outputs. 1 enables verbose information but disables tool outputs. 2 and greater outputs everything. More verbose levels may be added over time, so if you want absolutely all output, set it to something like 99.|
+| | `[-disable_output]` | **Removed: Default Behavior** Disables outputing to the terminal. <br> Optional flag.|
+| `padframe_gen` | | Generates the padframe for a design based on the files and configurations under `padframe_folder`. Also, it generates a padframe.cfg if it's not present. The padframe.cfg is a file that describes the order of the pads and their relative location on the chip.|
+| | `-folder <padframe_folder>` | specifies the `<padframe_folder>` for the padframe generator. The folder should contain the following: `./mag/<mag files>`, `./verilog/<verilog files>`, and optionally `./mag/padframe.cfg`|
+| `save_views` | | Saves the views of a given `run_tag` into the specifies `path`(s).|
+| | `[-lef_path <path>]` | Changes the save path for the lef files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
+| | `[-mag_path <path>]` | Changes the save path for the mag files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
+| | `[-def_path <path>]` | Changes the save path for the def files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
+| | `[-gds_path <path>]` | Changes the save path for the gds files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
+| | `[-verilog_path <path>]` | Changes the save path for the verilog files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
+| | `[-spice_path <path>]` | Changes the save path for the spice files to `<path>`. <br> The default is the `<run_path>` under the `<design_path>` specified by the `<run_tag>` and the processed `design` <br> Optional flag.|
+| | `[-save_path <path>]` | Changes the save path for the save path for all the types of files to `<path>`. <br> The default is the `<run_path>/results/final`.<br> Optional flag.|
+| | `-tag <run_tag>` | **Removed:** Specifies the `<run_tag>` from which the views were generated.|
+| `widen_site_width` | | generates two new lef files (merged_wider.lef and merged_unpadded_wider.lef) with a widened site width based on the values of `WIDEN_SITE_IS_FACTOR` and `WIDEN_SITE`, more about those in the [configurations/readme.md][13].|
+| `use_widened_lefs` | | Switches to using the lef files with the widened site width in the flow.|
+| `use_original_lefs` | | Switches to using the normal lef files in the flow.|
+| `label_macro_pins ` | | Labels the pins of a given macro def according to the netlist for lvs.|
+| | `-lef <lef_file>` | LEF file needed to have a proper view of the netlist AND the input DEF.|
+| | `-netlist_def <def_file>` | DEF view of the design that has the connectivity information.|
+| | `-pad_pin_name <pad_pin_name>` | Name of the pin of the pad as it appears in the netlist def. |
+| | `[-output <output_def>]` | Output labeled def file. <br> Defaults to the `CURRENT_DEF`. <br> Optional flag.|
+| | `[-extra_args <extra_args>]` | Gives extra control on the rest of the flags of the labeling script. For more information on the other args that the script supports, run: `python3 $OPENLANE_ROOT/scripts/label_macro_pins.py -h`. <br> Optional flag.|
+| `write_verilog <filename>` | | Generates a verilog netlist from a given def file. Stores the resulting netlist in `<filename>`, and sets the generated netlist as the `CURRENT_NETLIST` used by the flow.|
+| | `[-def <def_file>]` | DEF view of the design from which to generate the netlist. <br> Defaults to the `CURRENT_DEF`. <br> Optional flag.|
+| `add_macro_obs` | |Creates and obstruction in def and lef files.|
+| | `-defFile <def_file>` | DEF view of the design to write the obstruction into.|
+| | `-lefFile <lef_file>` | LEF file of the design to write the obstruction into.|
+| | ` -obstruction <obstruction_name> ` | Name of obstruction.|
+| | `[-placementX <base_x_coordinate>]` | X coordinate to place the obstruction. <br> Defaults to 0. <br> Optional flag.|
+| | `[-placementY <base_y_coordinate>]` | Y coordinate to place the obstruction. <br> Defaults to 0. <br> Optional flag.|
+| | `-sizeWidth <width>` | The width of the obstruction.|
+| | `-sizeHeight <height>` | The height of the macro obstruction.|
+| | `-fixed <val>` | if `<val>` is 1, then the macro is set as FIXED, else it's set as PLACED in the def file.|
+| | `[-dbunit <val>]` | `<val>` reflects the value of the data base unit. <br> Defaults to 1000. <br> Optional flag.|
+| | `-layerNames <list_of_layer_names>` | the list of layer names on which to place the obstruction. |
+| `set_layer_tracks ` | | sets the tracks on a layer to specific value.|
+| | `-defFile <def_file>` | DEF view of the design in which to edit the tracks values.|
+| | `-layer <layer_name>` | layer to change.|
+| | `-valuesFile <file>` | tmp file to read the new track values from.|
+| | `-originalFile <file>` | tmp file to store the original value.|
+| `padframe_extract_area` | | Returns the Diearea extracted from the given padframe configuration file. |
+| | `-cfg <padframe_configurations_file>` | The file containing the padframe information. |
+| `set_core_dims` | | Extracts the core dimensions based on the existing set environment variables. The results are set into `CORE_WIDTH` and `CORE_HEIGHT`. |
+| | `-log_path <path>` | The path to write the logs into. |
+| `run_spef_extraction` | | Runs SPEF extraction on the `::env(CURRENT_DEF)` file followed by Static Timing Analysis using OpenSTA. The results are reported under `<run_path>/reports/<step>/opensta_spef_*`. |
+| `run_antenna_check` | | Runs antenna checks based on the value of `::env(USE_ARC_ANTENNA_CHECK)` either calling `run_or_antenna_check` or `run_magic_antenna_check`. |
+| `run_or_antenna_check` | | Runs antenna checks using OpenROAD's Antenna Rule Checker on the `::env(CURRENT_DEF)`, the result is saved in `<run_path>/reports/signoff/antenna.rpt`|
+| `save_state` | | Saves environment variables to `<run_path>/config.tcl`, needed for -from -to|
+| `run_sta` | | Runs OpenSTA timing analysis on the current design, and produces a log under `/<run_path>/logs/<step>/` and timing reports under `/<run_path>/reports/<step>/`. |
+
+## Checker Commands
+
+Most of the following commands' implementation exists in this [file][1]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `check_synthesis_failure` | | Checks if any cells were unmapped or any latches were produced in the generated netlist by yosys. |
+| `check_assign_statements` | | Checks if the netlist generated by yosys contains any assign statements. |
+| `check_floorplan_missing_lef` | | Checks if the LEF was properly read in the floorplan stage. This is to detect if EXTRA_LEFS isn't set correctly. |
+| `check_floorplan_missing_pins` | | Checks if the LEF contains all pins, and that EXTRA_LEFS was set correctly. |
+| `check_cts_clock_nets` | | Checks if clock tree synthesis was successful and clock nets were added. |
+| `check_replace_divergence` | | Catches replace divergence and exits the flow because global placement failed. |
+| `check_macro_placer_num_solns` | | Checks if macro placment was successful using basic placement. |
+| `quit_on_tr_drc` | | Checks for DRC violations after routing and exits the flow if any was found. Controlled by `QUIT_ON_TR_DRC`. |
+| `quit_on_magic_drc` | | Checks for DRC violations after magic DRC is executed and exits the flow if any was found. Controlled by `QUIT_ON_MAGIC_DRC`. |
+| `quit_on_lvs_error` | | Checks for LVS errors after netgen LVS is executed and exits the flow if any was found. Controlled by `QUIT_ON_LVS_ERROR`. |
+| | `-log <file_parsed.log>` | The parsed LVS log, generated at the end of running LVS. The reason why this is passed over is because there are two types of LVS and each produces a different report, and this might be expanded later. |
+| `quit_on_illegal_overlaps` | | Checks for illegal overlaps during magic extraction. In some cases, these imply existing undetected shorts in the design. It also exits the flow if any was found. Controlled by `QUIT_ON_ILLEGAL_OVERLAPS`. |
+| | `-log <magic_ext_feedback.log>` | The magic extraction feedback log, generated at the end of running Magic extractions. |
+
+
+## Synthesis/Verilog Commands
+
+Most of the following commands' implementation exists in this [file][9]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `run_yosys` | | Runs yosys synthesis on the design processed in the flow (the design is set by the `prep` command). if `LEC_ENABLE` is set to 1, a logic verification will be run after generating the new netlist vs the previous netlist if it exists. |
+| | `[-output <output_file>]` | Sets the outputfile from yosys synthesis. <br> Defaults to `/<run_path>/results/synthesis/<design_name>.synthesis.v` <br> Optional flag. |
+| `run_synthesis` | | Runs yosys synthesis on the current design as well as OpenSTA timing analysis on the generated netlist. The logs are produced under `/<run_path>/logs/synthesis/`, the timing reports are under `/<run_path>/reports/synthesis/`, and the synthesized netlist under `/<run_path>/results/synthesis/`. |
+| `run_synth_exploration` | | Runs synthesis exploration, which will try out the available synthesis strategies against the input design. The output will be the four possible gate level netlists under `<run_path>/results/synthesis` and a summary report under `<run_path>/reports` that compares the 4 outputs. |
+| `verilog_elaborate <optional args>` | | Runs on structural verilog (top-level netlists) and elaborates it. The `<optional args>` are used to control what is passed to `run_yosys` |
+| `yosys_rewrite_verilog <filename>` | | Runs yosys to rewrite the verilog given in `<filename>` into the already set environment variable `SAVE_NETLIST`. Mainly used to generate explicit wire declarations |
+| `logic_equiv_check` | | Runs logic verification using yosys between the two given netlists. |
+| | `-lhs <verilog_netlist_file>` | The first netlist (lefthand-side) in the logic verification comparison. |
+| | `-rhs <verilog_netlist_file>` | The second netlist (righthand-side) in the logic verification comparison. |
+| `verilog_to_verilogPower` | | Adds the power pins and connections to a verilog file. |
+| | `-input <verilog_netlist_file>` | The input verilog that doesn't contain the power pins and connections. |
+| | `-output <verilog_netlist_file>` | The output verilog file. |
+| | `-lef <lef_file>` | The LEF view with the power pins information. |
+| | `-power <power_pin>` | The name of the power pin. |
+| | `-ground <ground_pin>` | The name of the ground pin. |
+| `write_powered_verilog` | | writes a verilog file that contains the power pins and connections from a DEF file. It stores the result in `/<run_path>/results/lvs` |
+| | `[-def <def_file>]` | The input DEF file. <br> Defaults to the `CURRENT_DEF` of the processed design. |
+| | `[-output_def <def_file>]` | The output DEF file. <br> Defaults to `/<run_path>/tmp/routing/<design_name>.powered.def` |
+| | `[-output_verilog <verilog_netlist_file>]` | The output verilog file. <br> Defaults to `/<run_path>/results/lvs/<design_name>.powered.v` |
+| | `[-lef <lef_file>]` | The LEF view with the power pins information. <br> Defaults to the `MERGED_LEF` |
+| | `[-power <power_pin>]` | The name of the power pin. <br> Defaults to `VDD_PIN` |
+| | `[-ground <ground_pin>]` | The name of the ground pin. <br> Defaults to `GND_PIN` |
+| | `[-powered_netlist <verilog_netlist_file>]` | The verilog netlist parsed from yosys that contains the internal power connections in case the design has internal macros file. <br> Defaults to `/<run_path>/tmp/synthesis/synthesis.pg_define.v` if `::env(SYNTH_USE_PG_PINS_DEFINES)` is defined, and to empty string otherwise. |
+| `get_yosys_bin` | | **Deprecated** Returns the used binary for yosys. |
+
+
+## Floorplan Commands
+
+Most of the following commands' implementation exists in this [file][3]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `init_floorplan` | | Runs floorplanning on the processed design using the openroad app. The resulting file is under `/<run_path>/tmp/floorplan/` . |
+| `place_io` | | Runs io placement on the design processed using the openroad app. The resulting file is under `/<run_path>/tmp/floorplan/` . |
+| `place_io_ol` | | Runs IO placement based on an input configuration file to place the pins in the orientation and order requiered by the user. |
+| | `[-lef <lef_file>]` | LEF file to be used. It must also include the technology information. <br> Defaults to `::env(MERGED_LEF)`. |
+| | `[-def <def_file>]` | DEF file to be used. <br> Defaults to `::env(CURRENT_DEF)`. |
+| | `[-cfg <cfg_file>]` | configuration file containing the list of desired pin order. An example could be found [here][14]. The file should contain `#orientation` followed by the pin names each in a new line in the desired order. Between each orientation section there should be a new empty line. <br> Defaults to `::env(FP_PIN_ORDER_CFG)`. |
+| | `[-horizontal_layer <val>]` | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br> Defaults to `::env(FP_IO_HMETAL)`. |
+| | `[-vertical_layer <val>]` | The metal layer on which to place the io pins vertically (left and right of the die). <br> Defaults to `::env(FP_IO_VMETAL)`. |
+| | `[-vertical_mult <val>]` | A multiplier for vertical pin thickness. Base thickness is the pins layer minwidth. <br> Defaults to `::env(FP_IO_VTHICKNESS_MULT)`. |
+| | `[-horizontal_mult <val>]` | A multiplier for horizontal pin thickness. Base thickness is the pins layer minwidth. <br> Defaults to `::env(FP_IO_HTHICKNESS_MULT)`. |
+| | `[-vertical_ext <val>]` | Extends the vertical io pins outside of the die by the specified units. <br> Defaults to `::env(FP_IO_VEXTEND)`. |
+| | `[-horizontal_ext <val>]` | Extends the horizontal io pins outside of the die by the specified units. <br> Defaults to `::env(FP_IO_HEXTEND)`. |
+| | `[-length <val>]` | IO length to be used. <br> Defaults to maximum of `::env(FP_IO_VLENGTH)` and `::env(FP_IO_HLENGTH)`. |
+| | `[-output_def <def_file>]` | output DEF file to be written. <br> Defaults to `<run_path>/tmp/floorplan/ioplacer.def`. |
+| `place_contextualized_io` | | contextualizes io placement on a given macro (the processed design) with the context of the higher macro that contains it. This allows the io pins to be placed in location closer to what they will be connected with on the bigger macro. The resuls are saved under `/<run_path>/tmp/floorplan/` . |
+| | `-lef <lef_file>` | LEF file needed to have a proper view of the top-level DEF |
+| | `-def <def_file>` | DEF view of the top-level design where the macro is instantiated. |
+| `tap_decap_or` | | Runs tap/decap placement on the design processed using the openroad app. The resulting file is under `/<run_path>/tmp/floorplan/` . |
+| `chip_floorplan` | | Runs floorplanning on a chip removing pins section and other empty sections from the def. The resulting file is under `/<run_path>/tmp/floorplan/` . |
+| `run_floorplan` | | Runs `init_floorplan`, followed by one of the io placement functions: if `::env(FP_PIN_ORDER_CFG)` is defined then `place_io_ol` is run; otherwise, if `::env(FP_CONTEXT_DEF)` and `::env(FP_CONTEXT_LEF)` are defined it runs `place_contextualized_io`, if nothing of those is defined then it runs the vanilla `place_io`. Then it runs `tap_decap_or` on the processed design. Finally, power grid is generated utilizing `::env(VDD_NETS)`, `::env(GND_NETS)`, and `::env(SYNTH_USE_PG_PINS_DEFINES)` if they are defined, otherwise vanilla gen_pdn is used. The resulting files are under `/<run_path>/tmp/floorplan/` and `/<run_path>/results/floorplan/`. |
+| `apply_def_template` | | Applies the DIE_AREA, pin names, and pin locations excluding power and ground pins from `::env(FP_DEF_TEMPLATE)` to the `::env(CURRENT_DEF)`. |
+
+## Placement Commands
+
+Most of the following commands' implementation exists in this [file][7]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `global_placement_or` | | Runs global placement on the processed design using OpenROAD. The resulting file is under `/<run_path>/tmp/placement/` . |
+| `global_placement` | Alias for `global_placement_or`. |
+| `random_global_placement` | | Runs random global placement using a custom OpenROAD-based script. Useful for tiny designs. The resulting file is under `/<run_path>/tmp/placement/`. |
+| `detailed_placement_or` | | Runs detailed placement on the processed design using OpenROAD. The resulting file is under `/<run_path>/results/placement/` . |
+| `detailed_placement` | | Alias for `detailed_placement_or`. |
+| `add_macro_placement <macro_name> <x_coordinate> <y_coordinate> [<orientation>]` | | Writes a configuration file to be processed by `manual_macro_placement` by setting the initial placement of the macro `<macro_name>` to location (`<x_coordinate>`,`<y_coordinate>`) on the chip with the option of specifying the `<orientation>` as well. The line written will be appened to this configuration file `/run_path/tmp/macro_placements.cfg`. |
+| `manual_macro_placement [f]` | | Uses the configuration file generated by `add_macro_placement` (`/run_path/tmp/macro_placements.cfg`) to manually initialize the placement of the macros to the locations determined in the file. It works on the currently processed design and it overwrites the `CURRENT_DEF`. if `f` is passed as the first argument, the placement will be fixed and final, and the placement tools will not be allowed to change it.|
+| `basic_macro_placement` | | Runs basic macro placement on the chip level using the openroad app, and it writes into `::env(CURRENT_DEF).macro_placement.def`. |
+| `run_resizer_design` | | Runs resizer design optimizations to insert buffers on nets to repair max slew, max capacitance, max fanout violations, and on long wires to reduce RC delay in the wire. It also resizes cells. |
+| `run_placement`| | Runs global placement (`global_placement_or` or `random_global_placement` based on the value of `PL_RANDOM_GLB_PLACEMENT`), then applies the optional optimizations `repair_wire_length` followed by `run_openPhySyn` if enabled, then runs the detailed placement (`detailed_placement_or`). |
+
+## CTS Commands
+
+Most of the following commands' implementation exists in this [file][2]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `simple_cts` | | Runs clock tree synthesis using the simple cts application. The resulting file is under `/<run_path>/results/cts/` . <br> Not Advised to use. Legacy Command.|
+| | `-verilog <file>` | The input verilog file. |
+| | `-fanout <val>` | The maximum fanout value. |
+| | `-clk_net <name>` | Clock net name. |
+| | `-root_clk_buf <name>` | Root clk buffer name. |
+| | `-clk_buf <list>` | List of the other clock buffers. |
+| | `-clk_buf_input <pin_name>` | Clock buffer input pin name. |
+| | `-clk_buf_output <pin_name>` | Clock buffer output pin name. |
+| | `-cell_clk_port <name>` | Clock buffer port name. |
+| | `-output <output_file>` | Output file path. |
+| `run_cts` | | Runs clock tree synthesis using the openroad app on the processed design. The resulting file is under `/<run_path>/results/cts/`. It also generates a the updated netlist using yosys and stores the results under `/<run_path>/results/cts` and runs yosys logic verification if enabled. |
+| `run_resizer_timing` | | Runs resizer timing optimizations which repairs setup and hold violations. |
+
+
+## Fill Insertion/Diode Insertion Commands
+
+Most of the following commands' implementation exists in this [file][8]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `ins_fill_cells` | | Runs fill insertion on the processed design using the openroad app. The resulting file is under `/<run_path>/tmp/routing/`. |
+| `ins_diode_cells_1` | | Runs diode insertion on the processed design using an opendb custom script following diode insertion strategies 1 and 2. The resulting file is under `/<run_path>/tmp/placement/` . It also generates a the updated netlist using yosys and stores the results under `/<run_path>/results/synthesis` and runs yosys logic verification if enabled. |
+| `ins_diode_cells_4` | | Runs diode insertion on the processed design using an opendb custom script following diode insertion strategies 4 and 5. The resulting file is under `/<run_path>/tmp/placement/` . It also generates a the updated netlist using yosys and stores the results under `/<run_path>/results/synthesis` and runs yosys logic verification if enabled. |
+| `heal_antenna_violators` | | Replaces the not needed diodes with fake diodes based on the magic antenna report. Therefore, magic antenna check should be run before this step (`run_magic_antenna_check`). <br> Runs only if `DIODE_INSERTION_STRATEGY` is set to `2`|
+
+
+## PDN Generation Commands
+
+Most of the following commands' implementation exists in this [file][8]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `gen_pdn` | | Runs basic power grid generation on the processed design using the openroad app. The resulting file is under `/<run_path>/tmp/floorplan/` . |
+| `power_routing` | | Performs power routing on a chip level design. More details in [Chip Integration][15]. |
+| | `[-def <def_file>]` | The input DEF file. <br> Defaults to `CURRENT_DEF`. |
+| | `[-lef <lef_file>]` | The input LEF file. <br> Defaults to `MERGED_LEF`. |
+| | `[-power <power_pin>]` | The name of the power pin. <br> Defaults to `VDD_PIN` |
+| | `[-ground <ground_pin>]` | The name of the ground pin. <br> Defaults to `GND_PIN` |
+| | `[-output_def <output_def_file>]` | The output DEF file path. <br> Defaults to `<run_path>/tmp/routing/$::env(DESIGN_NAME).power_routed.def` |
+| `run_power_grid_generation` | | Runs power grid generation with the advanced control options, `VDD_NETS`, `GND_NETS`, etc... This proc is capable of generating multiple power grid. Check [this documentation][16] for more details about controlling this command.
+
+## Routing Commands
+
+Most of the following commands' implementation exists in this [file][8]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `global_routing` | | Runs global routing on the processed design using either the openroad app's fastroute or cugr based on the value of `GLOBAL_ROUTER`. The resulting file is under `/<run_path>/tmp/routing/` . |
+| `global_routing_fastroute` | | Runs global routing on the processed design using the openroad app's fastroute. The resulting file is under `/<run_path>/tmp/routing/` . |
+| `global_routing_cugr` | | Runs global routing on the processed design using cugr. The resulting file is under `/<run_path>/tmp/routing/` . |
+| `detailed_routing` | | Runs detailed routing on the processed design using OpenROAD TritonRoute, or DRCU based onthe value of `DETAILED_ROUTER`. The resulting file is under `/<run_path>/results/routing/` . |
+| `detailed_routing_tritonroute` | | Runs detailed routing on the processed design using OpenROAD TritonRoute based on the value of `DETAILED_ROUTER`. The resulting file is under `/<run_path>/results/routing/` . |
+| `detailed_routing_drcu` | | Runs detailed routing on the processed design using DRCU. The resulting file is under `/<run_path>/results/routing/` . |
+| `apply_route_obs`| | Uses `GLB_RT_OBS` to insert obstruction for each macro in order to prevent routing for each specified layer on each macro. Check `GLB_RT_OBS` in the configurations documentation for more details.|
+| `add_route_obs`| | Uses `GLB_RT_OBS` to call `apply_route_obs`, then calls `apply_route_obs` again to apply obstructions over the whole die area based on the value of `GLB_RT_MAXLAYER` up to the highest available metal layer.|
+| `run_routing` | | Runs diode insertion based on the strategy, then adds the routing obstructions, followed by `global_routing`, then `ins_fill_cells`, `detailed_routing`, and finally SPEF extraction on the processed design. The resulting file is under `/<run_path>/results/routing/`. It also generates a pre_route netlist using yosys and stores the results under `/<run_path>/results/synthesis`, and it runs yosys logic verification if enabled. |
+
+## Magic Commands
+
+Most of the following commands' implementation exists in this [file][6]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `run_magic` | | Streams the final GDS and a mag view + a PNG screenshot of the layout. This is controlled by `RUN_MAGIC` and `TAKE_LAYOUT_SCROT`. The resulting file is under `/<run_path>/results/magic/` . |
+| `run_magic_drc` | | Runs a drc check on the `CURRENT_DEF` or the `CURRENT_GDS` based on the value of `MAGIC_DRC_USE_GDS`. The resulting file is under `/<run_path>/logs/magic/magic.drc` . |
+| `run_magic_spice_export` | | Runs spice extractions on the processed design. Based on the value of `MAGIC_EXT_USE_GDS` either the GDS or the DEF/LEF is used for the extraction. The resulting file is under `/<run_path>/results/magic/` . |
+| `export_magic_view` | | Export a mag view of a given def file. |
+| | `-def <def_file>` | The input DEF file. |
+| | `-output <output_file>` | The output mag file path. |
+| `run_magic_antenna_check` | | Runs spice extractions on the processed design and performs antenna checks. The resulting file is under `/<run_path>/results/magic/` and `/<run_path>/reports/magic/` . |
+
+## Klayout Commands
+
+Most of the following commands' implementation exists in this [file][17]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `run_klayout` | | Streams the back-up final GDS-II, generates a PNG screenshot, then runs Klayout DRC deck on it. This is controlled by `RUN_KLAYOUT`, `TAKE_LAYOUT_SCROT` ,and `KLAYOUT_DRC_KLAYOUT_GDS`. The resulting file is under `/<run_path>/results/klayout/` . |
+| `scrot_klayout` | | Export a PNG view of a given GDS-II or DEF file. This is controlled by `TAKE_LAYOUT_SCROT`. |
+| | `[-log <log_file>]` | Output log file. |
+| | `[-layout <layout_file>]` | The input GDS or DEF file, the default is `::env(CURRENT_GDS)`. |
+| `run_klayout_drc` | | Runs Klayout DRC on a given GDS-II file. This is controlled by `RUN_KLAYOUT_DRC`. |
+| | `[-gds <gds_file>]` | The input GDS file, the default is `::env(CURRENT_GDS)`. |
+| | `[-stage <stage>]` | The output stage using the DRC, the default is `magic`. The `magic` implies that the drc was run on the default GDS which is produced by magic. |
+| `run_klayout_gds_xor` | | Runs Klayout XOR on 2 GDS-IIs. This is controlled by `RUN_KLAYOUT_XOR` and `KLAYOUT_XOR_GDS` and `KLAYOUT_XOR_XML`. |
+| | `[-layout1 <gds_file>]` | The input GDS file, the default is the magic generated GDS-II under `<run_path>/results/magic/<design_name>.gds`. |
+| | `[-layout2 <gds_file>]` | The input GDS file, the default is the klayout generated GDS-II under `<run_path>/results/klayout/<design_name>.gds`. |
+| | `[-output_gds <gds_file>]` | The output GDS file with the xor result, the default under `<run_path>/results/klayout/<design_name>.xor.gds`. |
+| | `[-output_xml <xml_file>]` | The output XML file with the xor result, the default under `<run_path>/results/klayout/<design_name>.xor.xml`. |
+| `open_in_klayout` | | Opens a design in the Klayout GUI with MERGED_LEF for the cell/macro definitions. Useful as it works around Klayout's LEF import peculiarities. |
+| | `[-layout <def_file>]` | The input DEF file, the default is `::env(CURRENT_DEF)`. |
+
+## LVS Commands
+
+Most of the following commands' implementation exists in this [file][5]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `run_lvs` | | Runs an lvs check between an extracted spice netlist `EXT_NETLIST` (so `run_magic_spice_export` should be run before it.) and the current verilog netlist of the processed design `CURRENT_NETLIST`. The resulting file is under `/<run_path>/results/lvs/` and `/<run_path>/reports/lvs/`. The LVS could be on the block/cell level or on the device/transistor level, this is controlled by the extraction type set by `MAGIC_EXT_USE_GDS`. If the GDS is used in extraction then the LVS will be run down to the device/transistor level, otherwise it will be run on the block/cell level which is the default behavior in OpenLane. |
+
+## CVC Commands
+
+Most of the following commands' implementation exists in this [file][18]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `run_lef_cvc` | | Runs CVC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. The output files exist under `<run-path>/results/cvc/`. It is controlled by `::env(RUN_CVC)`.|
+
+## Utility Commands
+
+Most of the following commands' implementation exists in these files: [deflef][10] and [general][12]
+
+| Command | Flags | Description |
+|---------------|------------------------|-----------------------------------------|
+| `generate_final_summary_report` | | Generates a final summary csv report of the most important statistics and configurations in the run as well as a manufacturability report with the sumamry of DRC, LVS, and Antenna violations. This command is controlled by the flag `$::env(GENERATE_FINAL_SUMMARY_REPORT)`. |
+| | `[-output_file <output_file>]` | The ouput final summary csv report file path. <br> Defaults to being generated under `<run_path>/reports/metrics.csv`. |
+| | `[-man_report <man_report>]` | The ouput manufacturability report file path. <br> Defaults to being generated under `<run_path>/reports/manufacturability.rpt`. |
+| `remove_pins` | | Removes the pins' section from a given DEF file. |
+| | `-input <def_file>` | The input DEF file. |
+| `remove_empty_nets` | | Removes the empty nets from a given DEF file. |
+| | `-input <def_file>` | The input DEF file. |
+| `resize_die` | | Resizes the DIEAREA in a given DEF file to the given size. |
+| | `-def <def_file>` | The input DEF file. |
+| | `-area <list>` | The new coordinates of the DIEARA listed as (llx, lly, urx, ury). |
+| `get_instance_position` | | Returns the position of a given instance from the DEF view file. |
+| | `-instance <instance_name>` | The name of the instance. |
+| | `[-def <def_file>]` | The input DEF file. <br> Defaults to `CURRENT_DEF` of the currently processed design. <br> Optional Flag. |
+| `add_lefs` | | Merges the given `<-src>` LEF files to the existing processed LEF files. |
+| | `-src <lef_files>` | The input LEF files. |
+| `merge_components` | | Merges the components section of two DEF files. |
+| | `-input1 <def_file>` | The first DEF file. |
+| | `-input2 <def_file>` | The second DEF file. |
+| | `-output <def_file>` | The output DEF file. |
+| `move_pins` | | Moves the PINS section from one DEF file to another. |
+| | `-from <def_file>` | The input DEF file. |
+| | `-to <def_file>` | The target DEF file. |
+| `zeroize_origin_lef` | | Zeroizes the origin of all views in a LEF file. |
+| | `-file <lef_file>` | The input LEF file. |
+| `fake_display_buffer` | | Runs a fake display buffer for the pad generator. |
+| `kill_display_buffer` | | Kills the fake display buffer. |
+| `set_if_unset <var> <default_value>` | | If `<var>` doesn't exist/have a value, it will be set to `<default_value>`. |
+| `try_catch <command>` | | A minimal try_catch block to execute the `<command>`. |
+| `puts_err <text>` | | Prints `[ERROR]: ` followed by the `<text>` in red. |
+| `puts_success <text>` | | Prints `[SUCCESS]: ` followed by the `<text>` in green. |
+| `puts_warn <text>` | | Prints `[WARNING]: ` followed by the `<text>` in yellow. |
+| `puts_info <text>` | | Prints `[INFO]: ` followed by the `<text>` in cyan. |
+| `copy_gds_properties <arg_1.mag> <arg2.mag>` | | copies the GDS properties from `<arg_1.mag>` to `<arg2.mag>`. |
+| `increment_index` | | Increments `CURRENT_INDEX` by 1. |
+| `index_file <file>` | | Adds an index prefix to the file name keeping it's path. The prefix is `CURRENT_INDEX`. The current value of the `CURRENT_INDEX` could be found in `<run_path>/config.tcl`. |
+| `calc_total_runtime` | | Finalizes the generated `runtime.yaml` file for the design followed with the total runtime from the beginning of the flow. |
+| | `[-status <status>]` | The status message printed in the file. <br> Defaults to `flow completed`. |
+| `flow_fail` | | Calls `generate_final_summary_report`, calls `calc_total_runtime` with status `flow failed`, and finally prints `Flow Failed` to the terminal. |
+| `find_all <ext>` | | Print a sorted list of *.ext files that are found in the current run directory. |
+
+
+[0]: ./../../scripts/tcl_commands/all.tcl
+[1]: ./../../scripts/tcl_commands/checkers.tcl
+[2]: ./../../scripts/tcl_commands/cts.tcl
+[3]: ./../../scripts/tcl_commands/floorplan.tcl
+[4]: ./../../scripts/tcl_commands/init_design.tcl
+[5]: ./../../scripts/tcl_commands/lvs.tcl
+[6]: ./../../scripts/tcl_commands/magic.tcl
+[7]: ./../../scripts/tcl_commands/placement.tcl
+[8]: ./../../scripts/tcl_commands/routing.tcl
+[9]: ./../../scripts/tcl_commands/synthesis.tcl
+[10]: ./../../scripts/utils/deflef_utils.tcl
+[11]: ./../../scripts/utils/fake_display_buffer.tcl
+[12]: ./../../scripts/utils/utils.tcl
+[13]: ./../../configuration/README.md
+[14]: https://github.com/efabless/openlane/blob/master/designs/spm/pin_order.cfg
+[15]: ./chip_integration.md
+[16]: ./advanced_power_grid_control.md
+[17]: ./../../scripts/tcl_commands/klayout.tcl
+[18]: ./../../scripts/tcl_commands/cvc.tcl
diff --git a/openlane/docs/source/pdk_structure.md b/openlane/docs/source/pdk_structure.md
new file mode 100644
index 0000000..fb32086
--- /dev/null
+++ b/openlane/docs/source/pdk_structure.md
@@ -0,0 +1,157 @@
+# Porting a PDK
+
+This readme describes how to port a PDK to openlane.
+
+## Folder structure
+This is the expected folder structure for a PDK:
+
+- <pdk_name>
+ - libs.tech
+ - openlane
+ - config.tcl
+ - common_pdn.tcl
+ - `<standard cell library>`
+ - config.tcl
+ - tracks.info
+ - no_synth.cells
+ - drc_exclude.cells
+ - libs.ref
+ - lef
+ - techLEF
+ - lib
+
+## Configuration files
+- `config.tcl` PDK configuration file contains common information for all standard cell libraries under this PDK
+- `common_pdn.tcl` Pdn configuration file. Refer to PDN configuration [section](#pdn-configuration-file).
+- `<standard cell library>/config.tcl` standard cell library configuration file which contains information specific to that SCL. It can override PDK configuration file.
+- `<standard cell library>/tracks.info` Contains information about the metal layers offsets and pitches. Refer to tracks configuration file [section](#tracks-info-file)
+- `<standard cell library>/no_synth.cells` that should contain the list of newline-separated cell names to trim during synthesis (to not use them in synthesis). More in this [section](#no-synthesis-cells-file).
+
+
+## PDK Variables
+
+This section defines the neccessary variables for PDK configuration file. Note that all defaults are for sky130A.
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `DEF_UNITS_PER_MICRON` | Defines the unit distance microns. Used during floorplanning for proper def file generation. |
+| `VDD_PIN` | Defines the power pin of the cells. |
+| `GND_PIN` | Defines the ground pin of the cells. |
+| `TRACKS_INFO_FILE` | Points to the path of the tracks file. Used by the floorplanner to generate tracks |
+| `TECH_LEF_MIN` | Points to the path of the tech lef used for minimum corner extraction. (Optional) |
+| `TECH_LEF` | Points to the path of the tech lef used for nominal corner extraction. |
+| `TECH_LEF_MAX` | Points to the path of the tech lef used for maximum corner extraction. (Optional) |
+| `CELLS_LEF` | A list of paths to the cells lef views. Recommended to use wild card to catch all the files as follows: `[glob "$::env(PDK_ROOT)/sky130A/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]` |
+| `GDS_FILES` | A list of paths to the cells GDS-II views. Recommended to use wild card to catch all the files as follows: `[glob "$::env(PDK_ROOT)/sky130A/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"]` |
+| `MAGIC_TECH_FILE` | Points to the magic tech file which mainly has drc rules. |
+| `KLAYOUT_TECH` | Points to the klayout tech file (.lyt). |
+| `KLAYOUT_PROPERTIES` | Points to the klayout properties file (.lyp). |
+| `MAGIC_MAGICRC` | Points to the magicrc file that is sourced while running magic in the flow. |
+| `GPIO_PADS_LEF` | A list of the pads lef views. For example:`[glob "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef"]` |
+| `NETGEN_SETUP_FILE` | Points to the setup file for netgen(lvs), that can exclude certain cells etc.. |
+| `FP_TAPCELL_DIST` | The distance between tapcell columns. Used in floorplanning in tapcell insertion. |
+| `DEFAULT_MAX_TRAN` | Defines the default maximum transition value, used in CTS & synthesis. |
+| `FP_PDN_RAIL_OFFSET` | Defines the rail offset for met1 used in PDN. <br> Default: `0`. |
+| `FP_PDN_VWIDTH` | Defines the strap width for the vertical layer used in PDN. <br> Default: `1.6`. |
+| `FP_PDN_HWIDTH` | Defines the strap width for the horizontal layer used in PDN. <br> Default: `1.6`. |
+| `FP_PDN_CORE_RING_VWIDTH` | Defines the vertical width for the vertical layer used to create the core ring in the PDN. <br> Default: `20`. |
+| `FP_PDN_CORE_RING_HWIDTH` | Defines the horizontal width for the horizontal layer used to create the core ring in the PDN. <br> Default: `20`. |
+| `FP_PDN_CORE_RING_VSPACING` | Defines the spacing for the vertical layer used to create the core ring in the PDN. <br> Default: `5`. |
+| `FP_PDN_CORE_RING_HSPACING` | Defines the spacing for the horizontal layer used to create the core ring in the PDN. <br> Default: `5`. |
+| `FP_PDN_CORE_RING_VOFFSET` | Defines the offset for the vertical layer used to create the core ring in the PDN. <br> Default: `20`. |
+| `FP_PDN_CORE_RING_HOFFSET` | Defines the offset for the horizontal layer used to create the core ring in the PDN. <br> Default: `20`. |
+| `WIRE_RC_LAYER` | The metal layer used in estimate parastics `set_wire_rc`. <br> Default: `met1`.|
+| `GLB_RT_LAYER_ADJUSTMENTS` | Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 to 1. <br> (Default: `0.99,0,0,0,0,0`)
+| `FP_IO_HLAYER` | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br>(Default: `met3`)|
+| `FP_IO_VLAYER` | The metal layer on which to place the io pins vertically (sides of the die) <br> (Default: `met2`)|
+| `RT_MIN_LAYER` | The lowest metal layer to route on. <br>(Default: `met1`)|
+| `RT_MAX_LAYER` | The highest metal layer to route on. <br> (Default: `met5`)|
+| `RCX_RULES_MIN` | OpenRCX rules at the minimum corner. (Optional) |
+| `RCX_RULES` | OpenRCX rules at the nominal corner. |
+| `RCX_RULES_MAX` | OpenRCX rules at the maximum corner. (Optional) |
+
+
+## Standard cell library-specific variables
+
+This section defines the necessary variables to configure a standard cell library for use with OpenLane:
+
+| Variable | Description |
+|---------------|---------------------------------------------------------------|
+| `LIB_SYNTH` | Points to the lib file used during synthesis. |
+| `LIB_SLOWEST` | Points to the lib file, corresponding to the slowest corner, for max delay calculation during STA. |
+| `LIB_FASTEST` | Points to the lib file, corresponding to the fastest corner, for min delay calculation during STA. |
+| `LIB_TYPICAL` | Points to the lib file for typical delay calculation during STA. |
+| `NO_SYNTH_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
+| `PLACE_SITE` | Defines the main site used by the cells. Used during floorplanning to generate the rows. |
+| `PLACE_SITE_WIDTH` | Defines the main site width. Used during floorplanning to generate the rows. |
+| `PLACE_SITE_HEIGHT` | Defines the main site height. Used during floorplanning to generate the rows. |
+| `FP_WELLTAP_CELL` | Defines the tapcell to be used in tapcell insertion. <br> If this is not defined then tapcell insertion will be skipped but the flow will resume normally |
+| `FP_ENDCAP_CELL` | Defines the decapcell. Inserted during floorplanning at the sides of the design. |
+| `SYNTH_DRIVING_CELL` | Defines the cell to drive the input ports. Used in synthesis |
+| `SYNTH_DRIVING_CELL_PIN` | Defines the driving cell output pin. Used in synthesis |
+| `SYNTH_CAP_LOAD` | Defines the capacitive load on the output ports in femtofarads. Used in synthesis |
+| `SYNTH_MIN_BUF_PORT` | Defines the buffer, followed by its input port and output port to be used by `ins_buf` statements by yosys. It inserts buffer cells into the design for directly connected wires. Example: `sky130_fd_sc_hd__buf_2 A X` |
+| `SYNTH_TIEHI_PORT` | Defines the tie high cell followed by the port that implements the tie high functionality. Used in synthesis. Example: `sky130_fd_sc_hd__conb_1 HI` |
+| `SYNTH_TIELO_PORT` | Defines the tie low cell followed by the port that implements the tie high functionality. Used in synthesis. Example: `sky130_fd_sc_hd__conb_1 LO` |
+| `CELL_CLK_PORT` | Defines the name of clk port of the flip flops and other cells. Used in CTS. |
+| `PL_LIB` | Points to the lib view used in time driven placement. |
+| `FILL_CELL` | Defines the fill cell. Used in fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
+| `DECAP_CELL` | Defines the decap cell used for fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
+| `CELL_PAD` | Defines the number of sites to pad the cells lef views with. |
+| `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding. |
+| `CTS_ROOT_BUFFER` | Defines the cell inserted at the root of the clock tree. Used in CTS. |
+| `CLK_BUFFER` | Defines the clock buffer cell. Used in CTS. |
+| `CLK_BUFFER_INPUT` | Defines the clock buffer cell input port. Used in CTS. |
+| `CLK_BUFFER_OUTPUT` | Defines the clock buffer cell output port. Used in CTS. |
+| `CTS_CLK_BUFFER_LIST` | Defines the list of clock buffers to be used in CTS. |
+| `CTS_MAX_CAP` | Defines the maximum capacitance, used in CTS. |
+| `FP_PDN_RAIL_WIDTH` | Defines the rail width for met1 used in PDN. |
+| `SYNTH_LATCH_MAP` | A pointer for the file contianing the latch mapping for yosys. |
+| `TRISTATE_BUFFER_MAP` | A pointer for the file containing the tri-state buffer mapping for yosys. |
+| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
+| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells` and if it's not found, then the original liberty will be used as is. In other words, `DRC_EXCLUDE_CELL_LIST` contain the only excluded cell list in timing optimizations. |
+
+## Tracks Info File
+
+The tracks files defines the metal layers pitches and offsets. This information should be extracted from the PDK's tech lef. The following is the format of the files
+
+```
+<layer name> X|Y <offset> <pitch>
+```
+
+
+## PDN Configuration File
+
+A sample PDN configuration file exists [here](https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/common_pdn.tcl).
+
+More on the structure of the file [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/doc/PDN.md)
+
+## No Synthesis Cells File
+
+There are some cell types that you don't want to use in synthesis like, for example, delay cells and clock buffers (since CTS is a separate step that would insert the clock buffers).
+
+Also, other cells don't have a default mapping in yosys, so they were excluded to reduce the liberty file size until we add a tech mapping file for each.
+
+The smallest sizes of the cells were also removed to prevent the synthesizer from using them, which allows for a larger floorplan. These cells however are accessible by the optimizer which will in turn replace the bigger cells with these smaller sizes when needed. Eventually, this process will produce clean routing without forcing the users of OpenLane to re-configure their designs with smaller `FP_CORE_UTIL` and `PL_TARGET_DENSITY` values. Nonetheless, this change will come some time in the future.
+
+However, this list is likely over-constraining, and if you have done experiments allowing smaller sizes incrementally and still got clean routed layouts, please let us know your findings, or better yet, submit a pull request at [open_pdks](https://github.com/RTimothyEdwards/open_pdks) with a suggested no_synth list.
+
+
+This list is only used during synthesis.
+
+You can also point your custom no_synth.cells by setting the value for `NO_SYNTH_CELL_LIST` to point to it.
+
+
+## DRC Exclude Cells File
+
+Some of the cells, back when this list was created, had hard-to-access pin shapes, so the detailed router didn't manage to do routing cleanly.
+
+Others had DRC violations within the cell definitions.
+
+We excluded all cells of size _0 for the same reasons explained in the previous section.
+
+The lpflow cells were also excluded because the flow is still unable to deal with them and connect a KAPWR supply.
+
+This list is used for both synthesis and timing optimizations.
+
+You can also point your custom no_synth.cells by setting the value for `DRC_EXCLUDE_CELL_LIST` to point to it.
diff --git a/openlane/docs/source/using_or_issue.md b/openlane/docs/source/using_or_issue.md
new file mode 100644
index 0000000..caa049f
--- /dev/null
+++ b/openlane/docs/source/using_or_issue.md
@@ -0,0 +1,56 @@
+# `or_issue.py`
+This script creates a reproducible, self-contained package of files to demonstrate OpenROAD behavior in a vaccum, suitable for filing issues.
+
+It creates a folder with all the needed files that you can inspect, then zip or tarball and pass on to https://github.com/The-OpenROAD-Project/OpenROAD.
+
+# Warning about proprietary files
+When working with a proprietary PDK, also inspect the folder and ensure no proprietary data resulting ends up in there. This is *critical*, if something leaks, this scripts' authors take no responsibility and you are very much on your own. We will try our best to output warnings for your own good if something looks like a part of a proprietary PDK, but the absence of this message does not necessarily indicate that your folder is free of confidential material.
+
+# Usage
+If you're using OpenLane 2021.12.17_05.07.41 or later, chances are, `or_issue.py` was automatically run for you if OpenROAD failed. You'll find a message in the log that says something along the lines of: `Reproducible packaged: Please tarball and upload <PATH> if you're going to submit an issue.` The path will be under the current run_path, i.e., ./designs/<design>/runs/<run_tag>/openroad_issue_reproducible. You can then tarball/zip and upload that file.
+
+## Running or_issue.py manually
+You'll have to extract three key elements from the **verbose** logs (i.e. ./flow.tcl must be run with `-verbose`):
+* The Script Where The Failure Occurred -> script
+* The Final Layout Before The Failure Occurred -> input
+* The Run Path -> run_path
+ * The run path can be derived from the input, so typically, you do not have to explicitly specify it.
+
+***You must run or_issue.py from the same filesystem you've run OpenLane with. i.e., if you ran it inside the Docker container, you need to `make mount` first.***
+
+As a practical example, for this log from openlane.log:
+
+```log
+[INFO]: Changing layout to designs/spm/runs/RUN_2022.03.01_19.21.10/tmp/routing/17-fill.def
+[...]
+[INFO]: Running Detailed Routing...
+[INFO]: Running OpenROAD script scripts/openroad/droute.tcl...
+```
+
+The three elements would be:
+* input: `designs/spm/runs/RUN_2022.03.01_19.21.10/tmp/routing/17-fill.def`
+* script: `scripts/openroad/droute.tcl`
+* run_path: `designs/spm/runs/RUN_2022.03.01_19.21.10`
+
+Then you'd want to run this script as follows, from the root of the OpenLane Repo:
+```sh
+ python3 ./scripts/or_issue.py\
+ -s ./scripts/openroad/droute.tcl\
+ designs/spm/runs/RUN_2022.03.01_19.21.10/tmp/routing/17-fill.def
+ # run path is implicitly specified by input def
+```
+
+Which will create a folder called `_build`, with a single subfolder. Ensure that you inspect this folder manually and the output of this script. This script only attempts a best effort, and it is very likely that it might miss something, in which case, feel free to file an issue.
+
+You can then verify that the script worked by running:
+```sh
+ cd _build/<name of folder>
+ ./run
+```
+
+You can override the OpenROAD binary used as follows:
+
+```sh
+ cd _build/config_TEST_fastestTestSet1_or_groute_packaged
+ OPENROAD_BIN=/usr/local/bin/whatever ./run
+```
diff --git a/openlane/env.py b/openlane/env.py
new file mode 100755
index 0000000..ef625bc
--- /dev/null
+++ b/openlane/env.py
@@ -0,0 +1,257 @@
+#!/usr/bin/env python3
+
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Note to maintainers/contributors:
+#
+# Ensure you don't use f strings, non-comment type hints or any other features
+# that wouldn't work on Python 3.3
+#
+# Inevitably, some people won't read the Readme and then complain that the issue
+# survey doesn't work on their older Python versions. As long as it's compatible
+# with Python 3.3, this script will tell them that their python version is
+# below the minimum supported.
+
+import io
+import os
+import sys
+import getpass
+import textwrap
+import subprocess
+from os.path import abspath, dirname
+
+openlane_dir = dirname(abspath(__file__))
+is_root = os.geteuid() == 0
+
+# Commands
+def tool_list():
+ from dependencies.tool import Tool
+
+ tools = Tool.from_metadata_yaml(open("./dependencies/tool_metadata.yml").read())
+ for tool in tools.values():
+ print("%s %s" % (tool.name, tool.version_string))
+
+
+def local_install():
+ from dependencies.installer import Installer
+
+ installer = Installer()
+ installer.run()
+
+
+def docker_config():
+ from dependencies.env_info import ContainerInfo
+
+ cinfo = ContainerInfo.get()
+
+ if cinfo.engine == "docker":
+ if cinfo.rootless:
+ print("-u 0", end="")
+ else:
+ uid = (
+ subprocess.check_output(["id", "-u", getpass.getuser()])
+ .decode("utf8")
+ .strip()
+ )
+ gid = (
+ subprocess.check_output(["id", "-g", getpass.getuser()])
+ .decode("utf8")
+ .strip()
+ )
+ print("--user %s:%s" % (uid, gid), end="")
+
+
+def issue_survey():
+ sys.path.append(os.path.dirname(__file__))
+ from dependencies.env_info import OSInfo
+ from dependencies.version import parse as vp
+
+ alerts = open(os.devnull, "w")
+
+ final_report = ""
+
+ os_info = OSInfo.get()
+ final_report += textwrap.dedent(
+ """\
+ Kernel: %s v%s
+ """
+ % (os_info.kernel, os_info.kernel_version)
+ )
+
+ if os_info.distro is not None:
+ final_report += textwrap.dedent(
+ """\
+ Distribution: %s %s
+ """
+ % (os_info.distro, (os_info.distro_version or ""))
+ )
+
+ python_version = vp(os_info.python_version)
+ minimum_python_version = vp("3.6")
+ python_message = "OK"
+ python_ok = True
+ if python_version < minimum_python_version:
+ python_message = "BELOW MINIMUM: UPDATE PYTHON"
+ python_ok = False
+
+ final_report += textwrap.dedent(
+ """\
+ Python: v%s (%s)
+ """
+ % (python_version, python_message)
+ )
+
+ if os_info.container_info is not None:
+ container_version = vp(os_info.container_info.version)
+
+ container_message = "UNSUPPORTED"
+ if "docker" in os_info.container_info.engine:
+ container_message = "OK"
+ minimum_docker_version = vp("19.03.12")
+ if container_version < minimum_docker_version:
+ container_message = "BELOW MINIMUM: UPDATE DOCKER"
+
+ final_report += textwrap.dedent(
+ """\
+ Container Engine: %s v%s (%s)
+ """
+ % (os_info.container_info.engine, container_version, container_message)
+ )
+ elif os.path.exists(
+ "/git_version"
+ ): # i.e. if running inside the OpenLane container
+ print("Alert: Running in container.", file=alerts)
+ final_report = (
+ textwrap.dedent(
+ """\
+ WARNING: issue-survey appears to be running inside the OpenLane
+ container.
+
+ This makes it difficult to rule out issues with your
+ environment.
+
+ Unless instructed specifically to do so, please run this command
+ outside the OpenLane container.
+ ---\n
+ """
+ )
+ + final_report
+ )
+ else:
+ alert = (
+ "Critical Alert: No Docker or Docker-compatible container engine was found."
+ )
+ final_report += "%s\n" % alert
+ print(alert, file=alerts)
+
+ if python_ok:
+ from dependencies.get_tag import get_tag
+
+ final_report += textwrap.dedent(
+ """\
+ OpenLane Git Version: %s
+ """
+ % get_tag()
+ )
+
+ pip_ok = True
+ try:
+ import pip # noqa F401
+ except ImportError:
+ pip_ok = False
+
+ alert = (
+ "pip: " + "INSTALLED"
+ if pip_ok
+ else "NOT FOUND: Please install pip using your operating system's package manager."
+ )
+
+ final_report += "%s\n" % alert
+ print(alert, file=alerts)
+
+ if pip_ok:
+ venv_ok = True
+ try:
+ import venv # noqa F401
+ except ImportError:
+ venv_ok = False
+
+ alert = (
+ "pip:venv: " + "INSTALLED"
+ if venv_ok
+ else "NOT FOUND: needed for containerless installs"
+ )
+ final_report += "%s\n" % alert
+ print(alert, file=alerts)
+
+ if python_ok:
+ from dependencies.verify_versions import verify_versions
+
+ with io.StringIO() as f:
+ status = "OK"
+ try:
+ mismatches = verify_versions(
+ no_tools=True, report_file=f, pdk="sky130A"
+ )
+ if mismatches:
+ status = "MISMATCH"
+ except Exception:
+ status = "FAILED"
+ f.write("Failed to verify sky130A.")
+ f.write("\n")
+ final_report += "---\nPDK Version Verification Status: %s\n%s" % (
+ status,
+ f.getvalue(),
+ )
+
+ try:
+ git_log = subprocess.check_output(
+ [
+ "git",
+ "log",
+ r"--format=%h %cI %s - %an - %gs (%D)",
+ "-n",
+ "3",
+ ]
+ ).decode("utf8")
+
+ final_report += "---\nGit Log (Last 3 Commits)\n\n" + git_log
+ except subprocess.CalledProcessError:
+ pass
+
+ print(final_report, end="")
+
+
+# Entry Point
+def main():
+ args = sys.argv[1:]
+ commands = {
+ "tool-list": tool_list,
+ "local-install": local_install,
+ "docker-config": docker_config,
+ "issue-survey": issue_survey,
+ }
+
+ if len(args) < 1 or args[0] not in commands.keys():
+ print(
+ "Usage: %s (%s)" % (sys.argv[0], "|".join(commands.keys())), file=sys.stderr
+ )
+ sys.exit(os.EX_USAGE)
+
+ commands[args[0]]()
+
+
+if __name__ == "__main__":
+ main()
diff --git a/openlane/flow.tcl b/openlane/flow.tcl
new file mode 100755
index 0000000..d55bbe8
--- /dev/null
+++ b/openlane/flow.tcl
@@ -0,0 +1,449 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+set ::env(OPENLANE_ROOT) [file dirname [file normalize [info script]]]
+set ::env(SCRIPTS_DIR) "$::env(OPENLANE_ROOT)/scripts"
+
+if { [file exists $::env(OPENLANE_ROOT)/install/env.tcl ] } {
+ source $::env(OPENLANE_ROOT)/install/env.tcl
+}
+
+if { ! [info exists ::env(OPENROAD_BIN) ] } {
+ set ::env(OPENROAD_BIN) openroad
+}
+lappend ::auto_path "$::env(OPENLANE_ROOT)/scripts/"
+package require openlane; # provides the utils as well
+
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ run_routing
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) } {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc save_final_views {args} {
+ set options {
+ {-save_path optional}
+ }
+ set flags {}
+ parse_key_args "save_final_views" args arg_values $options flags_map $flags
+
+ set arg_list [list]
+
+ # If they don't exist, save_views will simply not copy them
+ lappend arg_list -lef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef
+ lappend arg_list -gds_path $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ lappend arg_list -mag_path $::env(signoff_results)/$::env(DESIGN_NAME).mag
+ lappend arg_list -maglef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef.mag
+ lappend arg_list -spice_path $::env(signoff_results)/$::env(DESIGN_NAME).spice
+
+ # Guaranteed to have default values
+ lappend arg_list -def_path $::env(CURRENT_DEF)
+ lappend arg_list -verilog_path $::env(CURRENT_NETLIST)
+
+ # Not guaranteed to have default values
+ if { [info exists ::env(CURRENT_SPEF)] } {
+ lappend arg_list -spef_path $::env(CURRENT_SPEF)
+ }
+ if { [info exists ::env(CURRENT_SDF)] } {
+ lappend arg_list -sdf_path $::env(CURRENT_SDF)
+ }
+ if { [info exists ::env(CURRENT_SDC)] } {
+ lappend arg_list -sdc_path $::env(CURRENT_SDC)
+ }
+
+ # Add the path if it exists...
+ if { [info exists arg_values(-save_path) ] } {
+ lappend arg_list -save_path $arg_values(-save_path)
+ }
+
+ # Aaand fire!
+ save_views {*}$arg_list
+
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_non_interactive_mode {args} {
+ set options {
+ {-design required}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ set env_overrides [split $arg_values(-override_env) ',']
+ foreach override $env_overrides {
+ set kva [split $override '=']
+ set key [lindex $kva 0]
+ set value [lindex $kva 1]
+ set ::env(${key}) $value
+ }
+ }
+
+ set LVS_ENABLED [expr ![info exists flags_map(-no_lvs)] ]
+ set DRC_ENABLED [expr ![info exists flags_map(-no_drc)] ]
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ set_if_unset arg_values(-to) "cvc";
+
+ if { [info exists ::env(CURRENT_STEP) ] } {
+ puts "\[INFO\]:Picking up where last execution left off"
+ puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+ } else {
+ set ::env(CURRENT_STEP) "synthesis";
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ if { $::env(SAVE_FINAL_VIEWS) == "1" } {
+ save_final_views
+ }
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+proc run_interactive_mode {args} {
+ set options {
+ {-design optional}
+ }
+ set flags {}
+ parse_key_args "run_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ if { [info exists arg_values(-design)] } {
+ prep {*}$args
+ }
+
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh >&@stdout
+}
+
+proc run_magic_drc_batch {args} {
+ set options {
+ {-magicrc optional}
+ {-tech optional}
+ {-report required}
+ {-design required}
+ {-gds required}
+ }
+ set flags {}
+ parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+ if { [info exists arg_values(-magicrc)] } {
+ set magicrc [file normalize $arg_values(-magicrc)]
+ }
+ if { [info exists arg_values(-tech)] } {
+ set ::env(TECH) [file normalize $arg_values(-tech)]
+ }
+ set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+ set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+ set ::env(DESIGN_NAME) $arg_values(-design)
+
+ if { [info exists magicrc] } {
+ exec magic \
+ -noconsole \
+ -dnull \
+ -rcfile $magicrc \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ } else {
+ exec magic \
+ -noconsole \
+ -dnull \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ }
+}
+
+proc run_lvs_batch {args} {
+ # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+ # extracts gds only if EXT_NETLIST does not exist
+ set options {
+ {-design required}
+ {-gds optional}
+ {-net optional}
+ }
+ set flags {}
+ parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+ prep {*}$args
+
+ if { [info exists arg_values(-gds)] } {
+ set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+ } else {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ }
+ if { [info exists arg_values(-net)] } {
+ set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ }
+ if { ! [file exists $::env(CURRENT_GDS) ] } {
+ puts_err "Could not find GDS file \"$::env(CURRENT_GDS)\""
+ exit 1
+ }
+ if { ! [file exists $::env(CURRENT_NETLIST) ] } {
+ puts_err "Could not find NET file \"$::env(CURRENT_NETLIST)\""
+ exit 1
+ }
+
+ set ::env(MAGIC_EXT_USE_GDS) 1
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+ if { [file exists $::env(EXT_NETLIST)] } {
+ puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+ } else {
+ run_magic_spice_export
+ }
+
+ run_lvs
+}
+
+
+proc run_file {args} {
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh {*}$args >&@stdout
+}
+
+set options {
+ {-file optional}
+}
+
+set flags {-interactive -it -drc -lvs -synth_explore -run_hooks}
+
+parse_key_args "flow.tcl" argv arg_values $options flags_map $flags -no_consume
+
+if {[catch {exec cat $::env(OPENLANE_ROOT)/install/installed_version} ::env(OPENLANE_VERSION)]} {
+ if {[catch {exec git --git-dir $::env(OPENLANE_ROOT)/.git rev-parse HEAD} ::env(OPENLANE_VERSION)]} {
+ if {[catch {exec cat /git_version} ::env(OPENLANE_VERSION)]} {
+ set ::env(OPENLANE_VERSION) "N/A"
+ }
+ }
+}
+
+puts "OpenLane $::env(OPENLANE_VERSION)"
+puts "All rights reserved. (c) 2020-2022 Efabless Corporation and contributors."
+puts "Available under the Apache License, version 2.0. See the LICENSE file for more details."
+puts ""
+
+if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
+ if { [info exists arg_values(-file)] } {
+ run_file [file normalize $arg_values(-file)] {*}$argv
+ } else {
+ run_interactive_mode {*}$argv
+ }
+} elseif { [info exists flags_map(-drc)] } {
+ run_magic_drc_batch {*}$argv
+} elseif { [info exists flags_map(-lvs)] } {
+ run_lvs_batch {*}$argv
+} elseif { [info exists flags_map(-synth_explore)] } {
+ prep {*}$argv
+ run_synth_exploration
+} else {
+ run_non_interactive_mode {*}$argv
+}
diff --git a/openlane/regression_results/.gitignore b/openlane/regression_results/.gitignore
new file mode 100644
index 0000000..3c75298
--- /dev/null
+++ b/openlane/regression_results/.gitignore
@@ -0,0 +1,12 @@
+*.rpt
+*.log
+*.csv
+*.html
+*.xlsx
+*/*.rpt
+*/*.log
+*/*.csv
+*/*.html
+*/*.xlsx
+*/*.yml
+!benchmark_results/*
\ No newline at end of file
diff --git a/openlane/regression_results/README.md b/openlane/regression_results/README.md
new file mode 100644
index 0000000..fa9d9f5
--- /dev/null
+++ b/openlane/regression_results/README.md
@@ -0,0 +1,123 @@
+# Regression & Exploration
+
+
+
+
+## Overview
+OpenLane provides `run_designs.py`, a script that can do multiple runs in a parallel using different configurations. A run consists of a set of designs and a configuration file that contains the configuration values. It is useful to explore the design implementation using different configurations to figure out the best one(s). For examples, check the [Usage](#usage) section.
+
+Also, it can be used for testing the flow by running the flow against several designs using their best configurations. For example the following has two runs: spm and xtea using their default configuration files `config.tcl.` :
+```
+python3 run_designs.py --tag test --threads 3 spm xtea des aes256
+```
+## Default Test Set Results:
+
+You can view the results of the run against some designs (more [here](#usage)) against any of the 5 sky130 standard cell libraries through these sheets:
+
+- [sky130_fd_sc_hd](https://github.com/efabless/openlane/blob/master/regression_results/benchmark_results/SW_HD.csv)
+- [sky130_fd_sc_hs](https://github.com/efabless/openlane/blob/master/regression_results/benchmark_results/SW_HS.csv)
+- [sky130_fd_sc_ms](https://github.com/efabless/openlane/blob/master/regression_results/benchmark_results/SW_MS.csv)
+- [sky130_fd_sc_ls](https://github.com/efabless/openlane/blob/master/regression_results/benchmark_results/SW_LS.csv)
+- [sky130_fd_sc_hdll](https://github.com/efabless/openlane/blob/master/regression_results/benchmark_results/SW_HDLL.csv)
+
+**Note**: `flow_failed` under `flow_status` implies that the run had failed.
+
+## Usage
+
+- The list of flags that could be used with run_designs.py is described here [Command line arguments](#command-line-arguments). Check [columns_defintions.md][21] for more details on the reported configuration parameters.
+
+The script can be used in two ways
+
+1. Running one or more designs.
+
+ ```bash
+ python3 run_designs.py --threads 4 spm xtea PPU APU
+ ```
+
+ You can run the default test set consisting of all designs under [./designs](../designs/) through running the following command along with any of the flags:
+
+ ```bash
+ python3 run_design.py --defaultTestSet
+ ```
+
+2. An exploration run that generates configuration files of all possible combinations of the passed regression file and runs them on the provided designs.
+
+ ```bash
+ python3 run_designs.py --regression ./scripts/config/regression.config --threads 2 spm xtea
+ ```
+
+ These parameters must be provided in the file passed to `--regression`. Any file can be used. The file used above is just an example
+
+ - Basic Regression Script:
+
+ The parameters that have multiple values inside the brackets will form the combinations. So here all combinations of GLB_RT_ADJUSTMENT and FP_CORE_UTIL will be tried.
+
+ ```
+ GLB_RT_ADJUSTMENT=(0.1,0.15)
+ FP_CORE_UTIL=(40,50)
+ PL_TARGET_DENSITY=(0.4)
+ SYNTH_STRATEGY=(1,3)
+ FP_PDN_VPITCH=(153.6)
+ FP_PDN_HPITCH=(153.18)
+ FP_ASPECT_RATIO=(1)
+ SYNTH_MAX_FANOUT=(5)
+
+ ```
+
+ - Complex Expressions:
+
+ In addition, `extra` is appended to every configuration file generated. So it is used to add some configurations specific to this regression run. The file could also contain non-white-space-separated expressions of one or more configuration variables or alternatively this could be specified in the extra section:
+
+ ```
+ FP_CORE_UTIL=(40,50)
+ PL_TARGET_DENSITY=(FP_CORE_UTIL*0.01-0.1,0.4)
+
+ extra="
+ set ::env(SYNTH_MAX_FANOUT) { $::env(FP_ASPECT_RATIO) * 5 }
+ "
+ ```
+
+ - SCL-specific section
+
+ You can use this section to specify information that you would like to be sourced before sourcing SCL-specific information:
+
+ ```
+ FP_CORE_UTIL=(40,50)
+ PL_TARGET_DENSITY=(FP_CORE_UTIL*0.01-0.1,0.4)
+
+ extra="
+ set ::env(SYNTH_MAX_FANOUT) { $::env(FP_ASPECT_RATIO) * 5 }
+ "
+
+ std_cell_library="
+ set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hd
+ set ::env(SYNTH_STRATEGY) 1
+ "
+ ```
+ In the example above, SYNTH_STRATEGY and STD_CELL_LIBRARY will be set before sourcing the SCL-specific information, and thus if SYNTH_STRATEGY is already specified under the configurations, the old value will override the value specified here.
+
+ This can also be used to control the used PDK and its SCL, since it is set before sourcing the SCL-specific information, so this will override the SCL set in general.tcl and allow for more control on different standard cell libraries under the same design.
+
+
+ It's important to note that the used configuration in the expression should be assigned a value or a range of values preceding its use in the file.
+
+
+**Important Note:** *If you are going to launch two or more separate regression runs that include same design(s), make sure to set different tags for them using the `--tag` option. Also, put memory management into consideration while running multiple threads to avoid running out of memory to avoid any invalid pointer access.*
+
+## Output
+- In addition to files produced inside `designs/<design>/runs/config_<tag>_<timestamp>` for each run on a design, three files are produced:
+ 1. `regression_results/<tag>_<timestamp>/<tag>_<timestamp>.log` A log file that describes start and stopping time of a given run.
+ 2. `regression_results/<tag>_<timestamp>/<tag>_<timestamp>.csv` A report file that provides a summary of each run. The summary contains some metrics and the configuration of that run
+ 3. `regression_results/<tag>_<timestamp>/<tag>_<timestamp>_best.csv` A report file that selects the best configuration per design based on number of violations
+
+- If a file is provided to the --benchmark flag, the following files will also be generated:
+
+ 6. `regression_results/<tag>_<timestamp>/<tag>_<timestamp>.rpt.yml` An incrementaly generated list of all designs in this run compared to the benchmark results and whether they PASSED or FAILED the regression test.
+ 7. `regression_results/<tag>_<timestamp>/<tag>_<timestamp>.rpt` A detailed report pointing out the differences between this run of the test set and the benchmark results. It divides them into three categories: Critical, Note-worthy, and Configurations.
+ 8. `regression_results/<tag>_<timestamp>/<tag>_<timestamp>.rpt.xlsx` A design to design comparison between benchmark results and this run of the test set. It includes whether or not a design failed or passed the test and it highlights the differences.
+
+
+## Command line arguments
+`python3 ./run_designs.py --help`
+
+[21]: ./columns_defintions.md
diff --git a/openlane/regression_results/benchmark_results/SW_HD.csv b/openlane/regression_results/benchmark_results/SW_HD.csv
new file mode 100644
index 0000000..3a58a87
--- /dev/null
+++ b/openlane/regression_results/benchmark_results/SW_HD.csv
@@ -0,0 +1,45 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,inverter,inverter,config_SW_HD_Benchmark,flow_completed,0h1m39s,0h1m19s,1089.3246187363834,0.001836,544.6623093681917,2,383.95,1,0,0,0,0,0,0,0,0,0,0,-1,74,10,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,0.74,1.39,0.0,0.0,0.0,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,1,1,1,24,7,0,31,100.0,10.0,10.0,AREA 0,5,50,1,153.6,153.18,0.75,0.0,sky130_fd_sc_hd,4,3
+1,manual_macro_placement_test,manual_macro_placement_test,config_SW_HD_Benchmark,flow_completed,0h2m31s,0h1m47s,56.8789388665165,0.100464,19.907628603280774,0,418.32,2,0,0,0,0,0,0,0,10,0,-1,-1,21631,544,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,4.4,4.74,2.55,4.21,2.35,10,72,10,72,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,220,673,0,893,10.0,100.0,100.0,AREA 0,5,35,1,30.0,153.18,0.35,0.0,sky130_fd_sc_hd,0,0
+2,digital_pll_sky130_fd_sc_hd,digital_pll,config_SW_HD_Benchmark,flow_completed,0h3m5s,0h2m41s,71071.06244777354,0.009476,34824.82059940903,51,436.93,330,0,0,0,0,0,0,0,1,0,0,-1,10237,2522,-4.49,-4.49,0.0,0.0,0.0,-8.49,-8.49,0.0,0.0,0.0,5855971,0.0,24.87,23.35,0.56,0.0,0.0,310,345,134,169,0,0,0,330,5,0,16,11,323,19,12,20,34,76,22,58,91,1,150,63.291139240506325,15.8,15.8,AREA 0,6,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_hd,4,3
+3,s44,lut_s44,config_SW_HD_Benchmark,flow_completed,0h5m28s,0h5m1s,59600.6144393241,0.03255,2980.030721966205,5,414.86,97,0,0,0,0,0,0,0,1,0,0,-1,5581,949,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4595182,0.0,3.37,4.07,0.0,0.0,0.0,94,114,38,58,0,0,0,97,0,0,0,0,0,0,0,32,41,32,4,120,372,0,492,33.333333333333336,30.0,30.0,AREA 0,5,5,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hd,4,3
+4,spm,spm,config_SW_HD_Benchmark,flow_completed,0h5m35s,0h5m8s,59656.619084949314,0.009476,29231.743351625162,51,422.94,277,0,0,0,0,0,0,0,0,0,0,-1,6698,2084,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4345922,0.0,16.51,17.85,0.0,0.0,0.0,281,312,39,70,0,0,0,277,32,0,31,31,1,63,31,0,97,128,4,60,94,0,154,100.0,10.0,10.0,AREA 0,5,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_hd,4,3
+5,usb,usb,config_SW_HD_Benchmark,flow_completed,0h7m4s,0h6m13s,70841.55161078238,0.03042,28336.620644312956,41,479.9,862,0,0,0,0,0,0,0,0,0,0,-1,26194,6777,-0.13,-0.13,0.0,0.0,0.0,-0.13,-0.13,0.0,0.0,0.0,16935276,0.0,19.47,20.14,0.0,0.0,0.0,861,885,200,224,0,0,0,862,22,8,43,40,206,49,6,176,242,251,12,116,330,0,446,79.6812749003984,12.55,12.55,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_hd,4,3
+6,cic_decimator,cic_decimator,config_SW_HD_Benchmark,flow_completed,0h7m39s,0h6m49s,85749.2430840695,0.021432,38587.15938783128,45,482.44,827,0,0,0,0,0,0,0,0,0,0,-1,24930,6484,-0.09,-0.09,0.0,0.0,0.0,-0.09,-0.09,0.0,0.0,0.0,16717654,0.0,28.08,24.93,0.0,0.0,0.0,816,849,119,152,0,0,0,827,15,0,21,51,90,92,51,220,131,112,16,96,225,0,321,100.0,10.0,10.0,AREA 0,6,45,1,15.0,15.0,0.5,0.0,sky130_fd_sc_hd,4,3
+7,zipdiv,zipdiv,config_SW_HD_Benchmark,flow_completed,0h7m52s,0h6m46s,84946.23655913977,0.03255,33978.49462365591,42,507.94,1106,0,0,0,0,0,0,0,1,0,0,-1,40784,9134,-1.86,-1.86,0.0,0.0,0.0,-8.06,-8.06,0.0,0.0,0.0,30272301,0.0,33.42,32.73,1.87,0.0,0.0,1078,1174,118,214,0,0,0,1106,46,0,3,43,165,146,14,241,273,273,30,120,372,4,496,52.38344683080147,19.09,19.09,AREA 0,6,40,1,153.6,153.18,0.45,0.15,sky130_fd_sc_hd,4,3
+8,usb_cdc_core,usb_cdc_core,config_SW_HD_Benchmark,flow_completed,0h10m32s,0h8m28s,89258.41101210142,0.051959000000000005,40166.28495544564,45,561.83,2087,0,0,0,0,0,0,0,2,0,0,-1,68654,15752,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,45658946,0.0,29.43,29.36,0.57,0.0,0.0,2083,2114,314,345,0,0,0,2087,99,0,110,89,676,130,41,252,365,683,20,154,630,1,785,64.1025641025641,15.6,15.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hd,4,3
+9,xtea,xtea,config_SW_HD_Benchmark,flow_completed,0h12m43s,0h10m10s,96573.42336135224,0.058055999999999996,43458.04051260851,47,586.82,2523,0,0,0,0,0,0,0,19,0,0,-1,125690,22256,-3.65,-3.65,-0.54,-2.17,-0.9,-26.13,-26.13,-0.93,-0.93,-2.75,90862040,0.0,52.18,54.05,6.88,7.78,0.0,2467,2718,123,374,0,0,0,2523,16,0,54,226,390,436,121,174,468,615,28,164,712,29,905,37.13330857779428,26.93,26.03,AREA 0,6,45,1,153.6,153.18,0.5,0.15,sky130_fd_sc_hd,4,3
+10,APU,APU,config_SW_HD_Benchmark,flow_completed,0h13m36s,0h10m2s,84799.788962288,0.103976,29679.9261368008,37,568.47,3086,0,0,0,0,0,0,0,3,0,0,-1,123845,26118,-3.15,-3.15,0.0,-0.79,0.0,-47.86,-47.86,0.0,0.0,0.0,82939701,0.0,25.92,25.87,0.0,0.0,0.0,3059,3118,380,439,0,0,0,3086,86,28,103,170,344,251,52,709,683,867,29,224,1309,14,1547,58.8235294117647,17.0,17.0,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hd,4,3
+11,wbqspiflash,wbqspiflash,config_SW_HD_Benchmark,flow_completed,0h15m16s,0h12m41s,90644.01622718052,0.070992,36257.60649087221,42,559.17,2574,0,0,0,0,0,0,0,5,0,0,-1,115295,21643,-5.51,-5.51,-1.99,-3.71,-3.19,-10.92,-10.92,-1.99,-1.99,-3.61,83439425,0.0,36.26,35.26,0.95,1.49,0.0,2547,2635,264,352,0,0,0,2574,55,1,147,155,796,79,6,376,656,885,19,184,846,14,1044,45.35147392290249,22.05,18.86,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_hd,4,3
+12,synth_ram,synth_ram,config_SW_HD_Benchmark,flow_completed,0h26m7s,0h16m48s,67575.69348544603,0.214344,30409.062068450712,45,665.52,6518,0,0,0,0,0,0,0,21,0,0,-1,333483,60794,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,219109921,0.0,30.33,35.19,1.96,0.01,0.0,6492,6578,2054,2140,0,0,0,6518,8,0,2,1,81,0,0,2080,2155,2080,8,328,2739,45,3112,20.0,50.0,50.0,AREA 0,5,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hd,4,3
+13,ocs_blitter,ocs_blitter,config_SW_HD_Benchmark,flow_completed,0h26m14s,0h18m19s,87644.91422852509,0.231812,30675.71997998378,37,654.26,7111,0,0,0,0,0,0,0,25,0,0,-1,351244,63164,-33.5,-33.5,-12.68,-14.69,-13.44,-4571.92,-4571.92,-409.21,-409.21,-444.11,240666100,0.0,31.26,33.95,0.99,0.83,0.0,7059,7203,439,583,0,0,0,7111,164,0,189,595,1116,745,127,471,962,1734,29,342,3025,92,3459,31.605562579013906,31.64,18.2,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hd,4,3
+14,md5,md5,config_SW_HD_Benchmark,flow_completed,0h30m2s,0h20m45s,88105.7268722467,0.201122,30837.00440528634,37,647.73,6202,0,0,0,0,0,0,0,18,0,0,-1,348946,55166,-6.19,-6.19,0.0,0.0,0.0,-117.94,-117.94,0.0,0.0,0.0,261756077,0.0,36.14,36.16,3.27,2.47,0.0,6080,6334,1175,1429,0,0,0,6202,80,0,137,240,1477,396,213,650,1208,1399,43,318,2576,127,3021,26.990553306342782,37.05,37.05,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hd,4,3
+15,PPU,PPU,config_SW_HD_Benchmark,flow_completed,0h38m59s,0h23m13s,70032.01548656094,0.67155,14006.403097312188,20,748.29,9406,0,0,0,0,0,0,0,55,0,0,-1,658021,89403,-9.19,-9.19,-1.97,-3.69,-2.41,-1332.77,-1332.77,-16.95,-16.95,-21.25,429708916,0.0,22.15,21.6,0.21,0.03,0.0,9347,9430,2898,2981,0,0,0,9406,53,8,55,72,460,113,21,2942,3193,3308,16,590,9056,216,9862,48.99559039686428,20.41,18.0,AREA 0,8,20,1,153.6,153.18,0.25,0.05,sky130_fd_sc_hd,4,3
+16,des,des,config_SW_HD_Benchmark,flow_completed,0h44m17s,0h27m38s,91791.09304790077,0.47262600000000005,32126.882566765264,37,812.27,15184,0,0,0,0,0,0,0,84,0,0,-1,694806,127332,0.0,0.0,0.0,-0.68,0.0,0.0,0.0,0.0,0.0,0.0,548942493,0.0,35.97,35.21,2.18,1.79,0.0,15125,15306,1957,2138,0,0,0,15184,432,1984,48,448,12688,1792,256,768,1792,512,12,492,6322,427,7241,50.0,20.0,20.0,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hd,4,3
+17,genericfir,genericfir,config_SW_HD_Benchmark,flow_completed,0h44m54s,0h35m19s,68734.43047267525,0.306332,30930.49371270386,46,711.79,9475,0,0,0,0,0,0,0,8,0,0,-1,356182,84654,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,216988395,0.0,28.8,28.52,0.1,0.12,0.0,12499,12551,6835,6887,0,0,0,9475,0,0,2001,3390,4008,3000,750,7560,3782,3780,6,394,3980,16,4390,100.0,10.0,10.0,AREA 0,7,45,1,153.6,153.18,0.5,0.1,sky130_fd_sc_hd,4,3
+18,BM64,BM64,config_SW_HD_Benchmark,flow_completed,0h45m57s,0h27m26s,93419.19912137334,0.5119100000000001,16815.4558418472,20,747.96,8608,0,0,0,0,0,0,0,143,0,0,-1,946689,89065,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,841797806,0.0,35.34,41.88,2.61,0.6,0.0,8102,9123,785,1806,0,0,0,8608,26,0,12,341,2174,989,307,2573,1801,1293,37,514,6861,519,7894,50.0,20.0,20.0,AREA 0,6,18,1,153.6,153.18,0.23,0.0,sky130_fd_sc_hd,4,3
+19,sha3,sha3,config_SW_HD_Benchmark,flow_completed,0h51m56s,0h34m22s,86988.79840061154,0.46646400000000005,30446.07944021404,34,822.65,14202,0,0,0,0,0,0,0,63,0,0,-1,786047,127999,-3.63,-3.63,-1.77,-3.82,-1.47,-2024.08,-2024.08,-287.4,-287.4,-117.36,542133676,0.0,36.86,41.14,2.54,2.66,0.0,14177,14246,3031,3100,0,0,0,14202,911,0,893,238,878,848,435,3088,3162,3709,21,490,6173,91,6754,70.5218617771509,14.180000000000001,12.71,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hd,4,3
+20,y_huff,y_huff,config_SW_HD_Benchmark,flow_completed,0h52m2s,0h38m4s,82424.00923432091,0.324875,32969.603693728364,43,808.24,10711,0,0,0,0,0,0,0,196,0,0,-1,898142,121091,-2.43,-2.43,-4.65,-7.36,-2.86,-2948.28,-2948.28,-1558.71,-1558.71,-622.06,620568195,0.0,55.05,61.41,20.6,27.05,0.0,10743,11418,2383,3058,0,0,0,10711,237,0,146,384,1310,575,87,4679,4830,3153,18,406,4303,469,5178,70.37297677691767,14.209999999999999,11.35,AREA 0,6,40,1,153.6,153.18,0.45,0.15,sky130_fd_sc_hd,4,3
+21,picorv32a,picorv32a,config_SW_HD_Benchmark,flow_completed,0h55m21s,0h36m53s,95973.57436403637,0.44286000000000003,33590.75102741273,36,826.8,14876,0,0,0,0,0,0,0,154,0,0,-1,966049,138230,-24.89,-24.89,-13.65,-16.57,-14.94,-759.46,-759.46,-332.55,-332.55,-372.22,733911173,0.0,45.06,44.88,11.76,7.11,0.0,14596,14978,1565,1947,0,0,0,14876,1159,227,896,560,2391,2462,615,1664,2132,2900,72,476,5878,466,6820,25.207965717166623,39.67,24.73,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hd,4,3
+22,usbf_device,usbf_device,config_SW_HD_Benchmark,flow_completed,0h59m58s,0h42m58s,95940.40000433139,0.430962,43173.18000194913,45,875.01,18606,0,0,0,0,0,0,0,45,0,0,-1,815607,151815,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,561580637,0.0,41.41,37.67,4.41,1.56,0.0,18581,18727,3775,3921,0,0,0,18606,675,0,362,157,4505,280,61,3692,4004,4615,13,470,5686,140,6296,68.4931506849315,14.6,14.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hd,4,3
+23,chacha,chacha,config_SW_HD_Benchmark,flow_completed,1h3m47s,0h44m58s,97627.13859099403,0.67977,24406.784647748507,26,892.07,16591,0,0,0,0,0,0,0,245,0,0,-1,1425054,158788,-20.47,-20.47,-3.25,-7.36,-4.71,-7439.91,-7439.91,-355.66,-355.66,-557.29,1111475850,0.0,40.0,46.02,8.55,8.88,0.0,16566,16635,2389,2458,0,0,0,16591,605,5,604,825,810,2011,971,3036,3035,3673,60,594,9117,629,10340,32.55208333333333,30.720000000000002,26.01,AREA 0,6,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hd,4,3
+24,ldpcenc,ldpcenc,config_SW_HD_Benchmark,flow_completed,1h8m50s,0h47m57s,86617.65355885256,0.814476,21654.41338971314,26,945.47,17637,0,0,0,0,0,0,0,286,0,0,-1,1570885,181212,-23.66,-23.66,-2.82,-5.72,0.0,-15964.85,-15964.85,-620.31,-620.31,0.0,1297612011,0.0,36.21,40.09,5.17,5.26,0.0,17618,17673,1527,1582,0,0,0,17637,103,94,990,79,2098,1958,84,1265,2487,2565,13,650,10952,1066,12668,77.51937984496124,12.9,12.9,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,3
+25,aes_cipher,aes_cipher,config_SW_HD_Benchmark,flow_completed,1h9m6s,0h55m27s,116509.43207745449,0.500526,29127.358019363623,28,858.09,14579,0,0,0,0,0,0,0,109,0,0,-1,1097710,145973,-2.12,-2.12,-0.1,-1.2,-0.73,-122.9,-122.9,-0.23,-0.23,-12.1,921209003,0.0,40.9,44.72,6.55,6.51,0.0,14459,14840,411,792,0,0,0,14579,461,386,73,357,18246,848,301,148,659,660,18,508,6654,935,8097,92.42144177449168,10.82,10.09,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,3
+26,blabla,blabla,config_SW_HD_Benchmark,flow_completed,1h9m47s,0h34m31s,104444.474594142,1.1256959999999998,11488.89220535562,14,894.43,12933,0,0,0,0,0,0,0,391,0,0,-1,2346631,139770,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2071365234,0.0,40.54,50.74,6.44,5.43,0.0,12432,13839,1105,2512,0,0,0,12933,654,5,575,813,507,2076,906,2190,2894,2059,58,768,15245,1546,17559,15.384615384615385,65.0,65.0,AREA 0,5,11,1,153.6,153.18,0.16,0.1,sky130_fd_sc_hd,4,3
+27,aes,aes,config_SW_HD_Benchmark,flow_completed,1h16m8s,0h52m36s,91164.13861141942,1.13526,18232.827722283884,21,1014.56,20699,0,0,0,0,0,0,0,153,0,0,-1,1575813,193809,-2.0,-2.0,0.0,0.0,0.0,-5454.14,-5454.14,0.0,0.0,0.0,1196363692,0.0,28.81,29.07,1.13,0.88,0.0,20674,20743,3136,3205,0,0,0,20699,219,0,88,346,8956,2179,691,3103,4034,4222,20,770,15284,585,16639,38.610038610038615,25.9,25.9,AREA 0,8,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hd,4,3
+28,salsa20,salsa20,config_SW_HD_Benchmark,flow_completed,1h22m21s,0h58m49s,90581.50183150184,1.092,18116.30036630037,22,1010.73,19783,0,0,0,0,0,0,0,402,0,0,-1,1971245,201286,-8.14,-8.14,0.0,0.0,0.0,-747.25,-747.25,0.0,0.0,0.0,1623499578,0.0,32.38,38.39,4.74,2.96,0.0,19758,19827,4073,4142,0,0,0,19783,518,5,615,755,1608,2268,769,7341,5004,4742,61,756,14818,835,16409,27.225701061802344,36.73,36.73,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hd,4,3
+29,aes_core,aes_core,config_SW_HD_Benchmark,flow_completed,1h24m51s,1h3m9s,96082.08512918261,0.843612,24020.521282295653,27,1003.32,20264,0,0,0,0,0,0,0,176,0,0,-1,1794903,205745,-1.3,-1.3,0.0,0.0,0.0,-3079.71,-3079.71,0.0,0.0,0.0,1445312835,0.0,41.14,42.75,7.62,1.83,0.0,20145,20654,2490,2999,0,0,0,20264,303,0,175,343,8961,2035,834,2717,3710,3696,19,662,11320,1093,13075,46.992481203007515,21.28,21.28,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,3
+30,sha512,sha512,config_SW_HD_Benchmark,flow_completed,1h26m10s,0h58m28s,88922.06994207404,1.1278190000000001,22230.51748551851,26,1118.28,25072,0,0,0,0,0,0,0,287,0,0,-1,2149091,252330,-25.33,-25.33,0.0,0.0,0.0,-25652.12,-25652.12,0.0,0.0,0.0,1511892178,0.0,33.98,47.9,3.46,6.32,0.0,25047,25116,5703,5772,0,0,0,25072,624,0,429,1853,4118,1682,1301,3667,6372,7289,44,768,15245,596,16609,25.464731347084285,39.27,39.27,AREA 0,10,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hd,4,3
+31,aes128,aes128,config_SW_HD_Benchmark,flow_completed,1h44m9s,1h0m54s,97350.40931495882,1.84821,24337.602328739704,25,1404.88,44981,0,0,0,0,0,0,0,268,0,0,-1,2415004,362906,-3.98,-3.98,-4.33,-5.8,-4.73,-3912.1,-3912.1,-4142.77,-4142.77,-4395.04,2047468727,0.0,30.26,29.48,5.22,0.04,0.0,44857,45238,10452,10833,0,0,0,44981,0,5568,65,1223,1198,17800,6545,800,6496,6736,32,986,25241,2934,29161,61.88118811881188,16.16,11.43,AREA 0,7,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hd,4,3
+32,des3,des3,config_SW_HD_Benchmark,flow_completed,2h3m7s,1h8m25s,88665.06562723612,2.7307259999999998,17733.013125447225,21,1728.34,48424,0,0,0,0,0,0,0,370,0,0,-1,2576662,408579,-15.64,-15.64,-12.75,-15.41,-13.02,-23792.2,-23792.2,-11662.8,-11662.8,-11862.81,2002372144,0.0,20.73,23.51,1.64,1.38,0.0,48367,48658,8959,9250,0,0,0,48424,1344,8808,144,1344,38112,5376,768,2416,5376,1536,12,1202,37382,2245,40829,48.5201358563804,20.61,7.59,AREA 0,7,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_hd,4,3
+33,aes192,aes192,config_SW_HD_Benchmark,flow_completed,2h3m55s,1h5m39s,92108.95856966764,2.7274220000000002,18421.79171393353,20,1682.87,50244,0,0,0,0,0,0,0,392,0,0,-1,3127590,405919,-3.51,-3.51,-3.83,-5.25,-4.18,-4114.38,-4114.38,-3841.14,-3841.14,-4224.96,2703601053,0.0,25.52,28.07,2.69,0.3,0.0,50120,50565,13036,13481,0,0,0,50244,14,7968,55,1831,1158,19939,7390,684,7660,6689,36,1202,37382,3206,41790,60.42296072507554,16.549999999999997,12.37,AREA 0,9,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_hd,4,3
+34,aes256,aes256,config_SW_HD_Benchmark,flow_completed,2h20m29s,1h15m7s,91778.95687801404,2.35773,27533.68706340421,30,1752.91,64917,0,0,0,0,0,0,0,466,0,0,-1,3664353,516992,0.0,0.0,-0.31,-2.01,-0.82,0.0,0.0,-14.34,-14.34,-53.88,3112794441,0.0,28.97,40.42,1.06,2.26,0.0,64793,65302,17643,18152,0,0,0,64917,0,11072,77,1733,1656,24387,9321,1104,9232,9031,32,1116,32196,3776,37088,63.21112515802781,15.82,15.0,AREA 0,9,30,1,153.6,153.18,0.35,0.05,sky130_fd_sc_hd,4,3
+35,point_add,point_add,config_SW_HD_Benchmark,flow_completed,2h26m30s,1h29m2s,105428.0961801557,2.03202,26357.024045038925,26,1685.63,53558,0,0,0,0,0,0,0,517,0,0,-1,4212562,517367,-32.02,-32.02,-5.19,-7.84,-7.02,-65089.45,-65089.45,-1312.35,-1312.35,-4762.78,3068587526,0.0,39.79,43.97,15.63,20.14,0.0,53180,54338,6131,7289,0,0,0,53558,857,1149,640,3041,18519,579,3,6546,10796,12400,18,1036,27816,6552,35404,58.75440658049354,17.02,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.15,sky130_fd_sc_hd,4,3
+36,point_scalar_mult,point_scalar_mult,config_SW_HD_Benchmark,flow_completed,2h29m51s,1h28m19s,103072.6351022115,2.257476,25768.158775552874,26,1728.67,58171,0,0,0,0,0,0,0,552,0,0,-1,4078523,522357,-32.02,-32.02,-6.11,-8.8,-5.21,-68945.45,-68945.45,-5481.93,-5481.93,-4761.83,3302617755,0.0,36.81,40.73,5.52,1.21,0.0,57791,58713,7456,8378,0,0,0,58171,253,1149,788,3213,18054,582,0,8651,12661,13726,17,1092,30958,5058,37108,65.74621959237344,15.21,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.05,sky130_fd_sc_hd,4,3
+37,jpeg_encoder,jpeg_encoder,config_SW_HD_Benchmark,flow_completed,2h51m25s,1h46m21s,102853.31262482454,2.8510020000000003,20570.662524964908,21,1828.09,58647,0,0,0,0,0,0,0,915,0,0,-1,4589927,543242,-16.95,-16.95,-0.75,-4.77,-3.16,-23777.33,-23777.33,-8.95,-8.95,-340.21,3786392644,0.0,30.01,32.92,5.35,3.59,0.0,58632,58668,4381,4417,0,0,0,58647,3839,1,2296,5188,7634,15175,5614,4439,6723,6061,39,1230,39175,3056,43461,52.79831045406548,18.939999999999998,15.78,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hd,4,3
+38,y_dct,y_dct,config_SW_HD_Benchmark,flow_completed,3h16m45s,1h28m59s,89170.44352686108,4.405776,17834.088705372218,23,2746.59,78573,0,0,0,0,0,0,0,367,0,0,-1,5639856,573185,-0.13,-0.13,-0.63,-4.19,-2.35,-0.3,-0.3,-2.35,-2.35,-86.44,5002767725,0.0,25.92,28.6,1.83,0.48,0.0,101044,101691,4703,5350,0,0,0,78573,3238,72,1227,3318,3941,3531,161,10172,31779,27586,21,1530,60589,3271,65390,43.72540445999125,22.87,20.52,AREA 0,5,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hd,4,3
+39,151,riscv_top,config_SW_HD_Benchmark,flow_completed,3h22m59s,1h44m32s,70475.45031292013,4.14323,17618.862578230033,26,2672.64,72999,0,0,0,0,0,0,0,728,0,0,-1,5563267,644915,-105.58,-105.58,0.0,-1.38,0.0,-1543243.25,-1543243.25,0.0,0.0,0.0,3984826472,0.0,26.06,29.51,0.57,2.42,0.0,72802,73137,23324,23659,0,0,0,72999,109,2216,286,1088,3839,426,120,20245,24812,25565,21,1484,56912,2142,60538,20.0,50.0,50.0,DELAY 1,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,3
+40,ldpc_decoder_802_3an,ldpc_decoder_802_3an,config_SW_HD_Benchmark,flow_failed,5h59m10s,-1,-902110000000.0,-1e-06,-90211000000.0,17,-1.0,90211,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,27588874469,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,88168,92262,2054,6148,0,0,0,90211,0,0,32,0,6519,19649,4544,2048,4098,6146,26,2106,114987,0,117093,12.987012987012987,77.0,77.0,DELAY 0,6,10,1,153.6,153.18,0.15,0.0,sky130_fd_sc_hd,4,3
+41,sound,sound,config_SW_HD_Benchmark,flow_completed,9h30m5s,2h45m45s,95249.57190255319,10.66346,19049.91438051064,20,6296.64,203138,0,0,0,0,0,0,0,803,0,0,-1,10904125,1757298,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,7986888128,0.0,20.88,21.88,0.47,0.07,0.0,203103,203220,203103,203220,0,0,0,203138,11691,1896,10906,21307,46996,25037,13741,15776,1102,1650,29,2388,147698,2508,152594,7.308338814587444,136.83,136.83,AREA 0,9,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hd,4,3
+42,gcd,gcd,UNKNOWN,flow completed,0h1m51s0ms,0h1m28s0ms,-2.0,0.0784251948,-1,5.11,732.7,-1,0,0,0,0,0,0,0,1,0,0,-1,17778,2526,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,14671323.0,0.0,6.1,7.5,0.74,0.43,0.0,347,1106,140,899,0,0,0,293,6,3,2,6,41,25,6,32,70,52,12,190,970,0,1160,100.0,10.0,10,DELAY 4,5,50,1,27.14,27.2,0.55,0.3,sky130_fd_sc_hd,4,3
+43,caravel_upw,user_project_wrapper,UNKNOWN,flow completed,0h5m16s0ms,0h2m8s0ms,-2.0,-1,-1,-1,476.77,1,0,0,0,0,0,0,0,0,0,-1,-1,1384300,1975,0.0,-1,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,-1,0.0,1.93,6.55,0.45,0.34,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/openlane/regression_results/benchmark_results/SW_HDLL.csv b/openlane/regression_results/benchmark_results/SW_HDLL.csv
new file mode 100644
index 0000000..5c8c9fd
--- /dev/null
+++ b/openlane/regression_results/benchmark_results/SW_HDLL.csv
@@ -0,0 +1,43 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,digital_pll_sky130_fd_sc_hd,digital_pll,config_SW_HDLL_Benchmark,flow_failed,0h0m2s,-1,2040816.3265306123,-1e-06,1000000.0,-1,-1.0,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,59.52380952380952,16.8,15.8,AREA 0,6,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_hdll,4,3
+1,y_dct,y_dct,config_SW_HDLL_Benchmark,flow_failed,0h8m28s,-1,-417360000000.0,-1e-06,-83472000000.0,-1,-1.0,83472,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,105943,106590,4703,5350,0,0,0,83472,3238,72,1227,3318,3941,3531,161,10172,31779,32925,20,0,0,0,0,48.732943469785575,20.52,20.52,AREA 0,5,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hdll,4,3
+2,inverter,inverter,config_SW_HDLL_Benchmark,flow_completed,0h9m3s,0h8m51s,1089.3246187363834,0.001836,544.6623093681917,2,383.4,1,0,0,0,0,0,0,0,0,0,0,-1,71,12,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,0.74,1.39,0.0,0.0,0.0,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,1,1,1,24,7,0,31,100.0,10.0,10.0,AREA 0,5,50,1,153.6,153.18,0.75,0.0,sky130_fd_sc_hdll,4,3
+3,manual_macro_placement_test,manual_macro_placement_test,config_SW_HDLL_Benchmark,flow_completed,0h9m52s,0h9m20s,56.8789388665165,0.100464,19.907628603280774,1,423.5,2,0,0,0,0,0,0,0,8,0,-1,-1,21633,530,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,4.54,4.94,2.33,3.85,2.35,10,72,10,72,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,220,673,0,893,10.0,100.0,100.0,AREA 0,5,35,1,30.0,153.18,0.35,0.0,sky130_fd_sc_hdll,0,0
+4,spm,spm,config_SW_HDLL_Benchmark,flow_completed,0h12m16s,0h12m1s,54712.15034686441,0.011526,26808.95366996356,52,405.0,309,0,0,0,0,0,0,0,0,0,-1,-1,7675,2160,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4932790,0.0,16.03,15.71,0.0,0.0,0.0,313,344,39,70,0,0,0,309,32,0,31,31,1,63,31,0,97,128,6,66,105,0,171,100.0,10.0,10.0,AREA 0,5,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_hdll,4,3
+5,cic_decimator,cic_decimator,config_SW_HDLL_Benchmark,flow_completed,0h12m19s,0h11m45s,69272.27382749514,0.030251,31172.523222372813,52,482.38,943,0,0,0,0,0,0,0,0,0,-1,-1,27658,6646,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,20182417,0.0,22.48,20.86,0.0,0.0,0.0,932,965,119,152,0,0,0,943,15,0,21,51,90,92,51,220,131,222,16,116,330,0,446,100.0,10.0,10.0,AREA 0,6,45,1,15.0,15.0,0.5,0.0,sky130_fd_sc_hdll,4,3
+6,s44,lut_s44,config_SW_HDLL_Benchmark,flow_completed,0h12m39s,0h12m18s,68260.94923950889,0.043656,3413.0474619754445,6,423.21,149,0,0,0,0,0,0,0,0,0,-1,-1,6293,1107,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5501065,0.0,2.92,3.42,0.0,0.0,0.0,146,166,38,58,0,0,0,149,0,0,0,0,0,0,0,32,41,64,4,140,504,0,644,33.333333333333336,30.0,30.0,AREA 0,5,5,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hdll,4,3
+7,usb,usb,config_SW_HDLL_Benchmark,flow_completed,0h13m4s,0h12m28s,57194.423699278064,0.04017,22877.769479711227,43,474.09,919,0,0,0,0,0,0,0,1,0,-1,-1,30458,7191,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,20013483,0.0,16.99,18.17,0.0,0.0,0.0,918,942,200,224,0,0,0,919,22,8,43,40,206,49,6,176,242,316,11,134,448,0,582,79.6812749003984,12.55,12.55,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_hdll,4,3
+8,zipdiv,zipdiv,config_SW_HDLL_Benchmark,flow_completed,0h13m26s,0h12m44s,69047.61904761905,0.0462,27619.047619047622,46,483.72,1276,0,0,0,0,0,0,0,2,0,-1,-1,49416,9847,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,37521280,0.0,28.42,30.26,0.54,0.0,0.0,1248,1344,118,214,0,0,0,1276,46,0,3,43,165,146,14,241,273,415,25,146,560,13,719,52.38344683080147,19.09,19.09,AREA 0,6,40,1,153.6,153.18,0.45,0.15,sky130_fd_sc_hdll,4,3
+9,usb_cdc_core,usb_cdc_core,config_SW_HDLL_Benchmark,flow_completed,0h13m38s,0h12m32s,67871.4479452487,0.07046000000000001,30542.151575361913,50,508.41,2152,0,0,0,0,0,0,0,2,0,-1,-1,78135,16004,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,54667049,0.0,25.07,25.61,0.0,0.0,0.0,2148,2179,314,345,0,0,0,2152,99,0,110,89,676,130,41,252,365,683,15,182,837,1,1020,64.1025641025641,15.6,15.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hdll,4,3
+10,xtea,xtea,config_SW_HDLL_Benchmark,flow_completed,0h14m36s,0h13m6s,65415.24459613197,0.089072,29436.860068259386,47,536.14,2622,0,0,0,0,0,0,0,12,0,-1,-1,143890,21325,-2.82,-2.82,-1.02,-2.3,-1.05,-13.91,-13.91,-2.75,-2.75,-3.93,111411052,0.0,41.68,43.87,3.68,0.79,0.0,2566,2817,123,374,0,0,0,2622,16,0,54,226,390,436,121,174,468,615,29,206,1102,18,1326,36.92762186115214,27.080000000000002,26.03,AREA 0,6,45,1,153.6,153.18,0.5,0.15,sky130_fd_sc_hdll,4,3
+11,wbqspiflash,wbqspiflash,config_SW_HDLL_Benchmark,flow_completed,0h16m23s,0h14m26s,63609.70196575778,0.113544,25443.88078630311,41,527.48,2889,0,0,0,0,0,0,0,6,0,-1,-1,143307,22673,-6.89,-6.89,-4.65,-6.15,-5.76,-14.87,-14.87,-7.75,-7.75,-12.75,107586920,0.0,26.93,29.09,0.86,0.0,0.0,2862,2950,264,352,0,0,0,2889,55,1,147,155,796,79,6,376,656,1165,19,236,1438,18,1692,40.61738424045492,24.619999999999997,18.86,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_hdll,4,3
+12,APU,APU,config_SW_HDLL_Benchmark,flow_completed,0h16m45s,0h14m10s,71588.8449620686,0.14974400000000002,25056.095736724008,39,557.3,3752,0,0,0,0,0,0,0,7,0,-1,-1,149264,28644,-3.89,-3.89,0.0,-1.2,-0.41,-68.97,-68.97,0.0,0.0,-3.55,108713601,0.0,22.41,22.05,0.0,0.0,0.0,3725,3784,380,439,0,0,0,3752,86,28,103,170,344,251,52,709,683,1253,29,272,1930,13,2215,57.43825387708213,17.41,17.0,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hdll,4,3
+13,md5,md5,config_SW_HDLL_Benchmark,flow_completed,0h23m3s,0h16m20s,54784.78740510826,0.320892,19174.67559178789,35,624.93,6153,0,0,0,0,0,0,0,19,0,-1,-1,418144,53003,-5.21,-5.21,0.0,-2.47,-0.35,-62.86,-62.86,0.0,0.0,-0.35,318144665,0.0,26.29,30.16,1.14,0.59,0.0,6031,6285,1175,1429,0,0,0,6153,80,0,137,240,1477,396,213,650,1208,1399,42,404,4182,96,4682,26.737967914438503,37.4,37.05,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hdll,4,3
+14,ocs_blitter,ocs_blitter,config_SW_HDLL_Benchmark,flow_completed,0h23m52s,0h16m33s,66123.99849764118,0.339276,23143.399474174414,37,644.0,7852,0,0,0,0,0,0,0,31,0,-1,-1,436623,67085,-58.38,-58.38,-16.86,-19.73,-16.87,-11540.28,-11540.28,-711.82,-711.82,-726.19,300945835,0.0,27.25,29.72,0.34,0.0,0.0,7800,7944,439,583,0,0,0,7852,164,0,189,595,1116,745,127,471,962,1734,28,416,4513,54,4983,28.5143997718848,35.07,18.2,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hdll,4,3
+15,synth_ram,synth_ram,config_SW_HDLL_Benchmark,flow_completed,0h26m8s,0h17m42s,47652.06637370027,0.44419200000000003,21443.42986816512,32,683.21,9525,0,0,0,0,0,0,0,10,0,-1,-1,445289,66508,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,291676900,0.0,22.03,21.23,0.8,0.45,0.0,9499,9585,2054,2140,0,0,0,9525,8,0,2,1,81,0,0,2080,2155,4160,7,478,5902,43,6423,20.0,50.0,50.0,AREA 0,5,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hdll,4,3
+16,BM64,BM64,config_SW_HDLL_Benchmark,flow_completed,0h38m15s,0h22m26s,68757.84682988074,0.79296,12376.412429378533,19,761.74,9814,0,0,0,0,0,0,0,100,0,-1,-1,1206249,92412,-0.72,-0.72,0.0,-0.55,0.0,-4.61,-4.61,0.0,0.0,0.0,1085481097,0.0,29.56,35.3,1.03,0.56,0.0,9308,10329,785,1806,0,0,0,9814,26,0,12,341,2174,989,307,2573,1801,2580,34,642,10657,468,11767,50.0,20.0,20.0,AREA 0,6,18,1,153.6,153.18,0.23,0.0,sky130_fd_sc_hdll,4,3
+17,sha3,sha3,config_SW_HDLL_Benchmark,flow_completed,0h38m34s,0h23m50s,73190.84980031493,0.669912,25616.797430110226,41,846.69,17161,0,0,0,0,0,0,0,59,0,-1,-1,910488,138539,-7.63,-7.63,-7.31,-9.73,-7.09,-5326.56,-5326.56,-6672.09,-6672.09,-5763.11,686581152,0.0,32.04,36.22,0.4,1.35,0.0,17136,17205,3031,3100,0,0,0,17161,911,0,893,238,878,848,435,3088,3162,5251,23,590,9056,109,9755,50.505050505050505,19.8,12.71,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hdll,4,3
+18,PPU,PPU,config_SW_HDLL_Benchmark,flow_completed,0h39m31s,0h20m16s,50369.12521645312,1.342092,10073.825043290624,16,821.18,13520,0,0,0,0,0,0,0,52,0,-1,-1,868220,96331,-25.23,-25.23,-3.36,-5.34,-4.26,-6335.97,-6335.97,-43.3,-43.3,-61.9,591027194,0.0,14.66,14.8,0.0,0.0,0.0,13461,13544,2898,2981,0,0,0,13520,53,8,55,72,460,113,21,2942,3193,6203,16,840,18353,120,19313,44.92362982929021,22.259999999999998,18.0,AREA 0,8,20,1,153.6,153.18,0.25,0.05,sky130_fd_sc_hdll,4,3
+19,des,des,config_SW_HDLL_Benchmark,flow_completed,0h39m44s,0h24m56s,65819.07782180754,0.74733,23036.67723763264,40,815.91,17216,0,0,0,0,0,0,0,98,0,-1,-1,845901,134662,0.0,0.0,-4.65,-7.11,-3.84,0.0,0.0,-305.23,-305.23,-194.23,683223550,0.0,28.54,28.13,1.15,0.82,0.0,17157,17338,1957,2138,0,0,0,17216,432,1984,48,448,12688,1792,256,768,1792,2496,12,622,10014,323,10959,41.946308724832214,23.84,20.0,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hdll,4,3
+20,picorv32a,picorv32a,config_SW_HDLL_Benchmark,flow_completed,0h40m36s,0h25m31s,70119.44344682971,0.6905359999999999,24541.8052063904,37,850.27,16947,0,0,0,0,0,0,0,67,0,-1,-1,1075476,139471,-0.16,-0.16,-1.21,-4.45,-1.99,-0.16,-0.16,-4.38,-4.38,-9.65,866995035,0.0,36.69,36.13,6.34,0.49,0.0,16667,17049,1565,1947,0,0,0,16947,1159,227,896,560,2391,2462,615,1664,2132,4513,55,598,9327,232,10157,37.4251497005988,26.72,24.73,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hdll,4,3
+21,genericfir,genericfir,config_SW_HDLL_Benchmark,flow_completed,0h40m39s,0h32m40s,72009.06430603444,0.40893,32404.078937715498,45,739.36,13251,0,0,0,0,0,0,0,8,0,-1,-1,411848,96997,0.0,0.0,-0.11,-1.45,-0.35,0.0,0.0,-2.32,-2.32,-6.9,254709948,0.0,25.89,24.64,0.12,0.0,0.0,16275,16327,6835,6887,0,0,0,13251,0,0,2001,3390,4008,3000,750,7560,3782,7560,6,458,5426,11,5895,96.61835748792271,10.35,10.0,AREA 0,7,45,1,153.6,153.18,0.5,0.1,sky130_fd_sc_hdll,4,3
+22,y_huff,y_huff,config_SW_HDLL_Benchmark,flow_completed,0h41m41s,0h28m35s,72331.90196899875,0.458304,28932.760787599498,46,817.08,13260,0,0,0,0,0,0,0,49,0,-1,-1,1027789,131546,-4.68,-4.68,-6.41,-8.24,-6.7,-6526.76,-6526.76,-7021.5,-7021.5,-7449.31,756014871,0.0,54.84,55.16,11.25,6.8,0.0,13292,13967,2383,3058,0,0,0,13260,237,0,146,384,1310,575,87,4679,4830,5504,16,486,6123,138,6747,55.40166204986149,18.05,11.35,AREA 0,6,40,1,153.6,153.18,0.45,0.15,sky130_fd_sc_hdll,4,3
+23,usbf_device,usbf_device,config_SW_HDLL_Benchmark,flow_completed,0h42m8s,0h25m46s,55366.78977008435,0.8217120000000001,24915.05539653796,34,872.36,20473,0,0,0,0,0,0,0,56,0,-1,-1,1028805,143111,0.0,0.0,0.0,-0.31,0.0,0.0,0.0,0.0,0.0,0.0,777273839,0.0,26.9,26.87,0.74,0.66,0.0,20448,20594,3775,3921,0,0,0,20473,675,0,362,157,4505,280,61,3692,4004,7815,13,654,11019,133,11806,68.4931506849315,14.6,14.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hdll,4,3
+24,chacha,chacha,config_SW_HDLL_Benchmark,flow_completed,0h49m56s,0h30m56s,79357.94963932865,0.975126,19839.487409832163,31,932.55,19346,0,0,0,0,0,0,0,176,0,-1,-1,1729016,171352,-26.21,-26.21,-8.32,-12.17,-9.46,-9827.01,-9827.01,-1553.31,-1553.31,-1865.91,1396588291,0.0,37.76,40.57,7.11,3.78,0.0,19321,19390,2389,2458,0,0,0,19346,605,5,604,825,810,2011,971,3036,3035,5613,70,714,13101,294,14109,28.192839018889202,35.47,26.01,AREA 0,6,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hdll,4,3
+25,ldpcenc,ldpcenc,config_SW_HDLL_Benchmark,flow_completed,0h50m36s,0h30m5s,73759.52013493412,1.074302,18439.88003373353,31,962.21,19810,0,0,0,0,0,0,0,93,0,-1,-1,1716871,183394,-80.29,-80.29,-16.92,-20.38,-17.2,-56529.54,-56529.54,-4955.14,-4955.14,-4732.44,1410742057,0.0,31.86,34.44,2.75,2.38,0.0,19791,19846,1527,1582,0,0,0,19810,103,94,990,79,2098,1958,84,1265,2487,2659,13,750,14512,577,15839,33.222591362126245,30.1,12.9,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hdll,4,3
+26,aes_cipher,aes_cipher,config_SW_HDLL_Benchmark,flow_completed,0h53m20s,0h32m27s,62918.66944458115,1.097226,15729.667361145288,33,947.21,17259,0,0,0,0,0,0,0,107,0,-1,-1,1674689,171890,-7.35,-7.35,-4.44,-5.88,-5.26,-1480.33,-1480.33,-759.27,-759.27,-985.79,1471017688,0.0,31.01,34.36,1.89,1.52,0.0,17139,17520,411,792,0,0,0,17259,461,386,73,357,18246,848,301,148,659,1190,18,758,14857,846,16461,65.14657980456026,15.35,10.09,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hdll,4,3
+27,blabla,blabla,config_SW_HDLL_Benchmark,flow_completed,0h56m37s,0h28m49s,83817.7043573278,1.315584,10896.301566452616,19,950.34,14335,0,0,0,0,0,0,0,264,0,-1,-1,2484936,146214,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2237428856,0.0,39.02,48.64,5.0,1.19,0.0,13834,15241,1105,2512,0,0,0,14335,654,5,575,813,507,2076,906,2190,2894,3159,67,830,17927,644,19401,15.384615384615385,65.0,65.0,AREA 0,5,13,1,153.6,153.18,0.18,0.1,sky130_fd_sc_hdll,4,3
+28,aes_core,aes_core,config_SW_HDLL_Benchmark,flow_completed,1h3m19s,0h37m47s,60274.08957008069,1.4053799999999999,15068.522392520172,26,1053.68,21177,0,0,0,0,0,0,0,124,0,-1,-1,2201237,208929,-6.86,-6.86,-2.84,-5.99,-4.1,-19420.39,-19420.39,-1485.89,-1485.89,-3836.57,1790749269,0.0,31.41,32.88,3.24,1.41,0.0,21058,21567,2490,2999,0,0,0,21177,303,0,175,343,8961,2035,834,2717,3710,3952,19,858,19175,785,20818,39.40110323089046,25.380000000000003,21.28,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hdll,4,3
+29,salsa20,salsa20,config_SW_HDLL_Benchmark,flow_completed,1h3m56s,0h37m57s,79726.94108169018,1.494476,15945.388216338037,24,1070.36,23830,0,0,0,0,0,0,0,212,0,-1,-1,2244910,212193,-15.09,-15.09,0.0,-0.64,0.0,-2434.17,-2434.17,0.0,0.0,0.0,1893829070,0.0,29.37,32.96,1.5,2.85,0.0,23805,23874,4073,4142,0,0,0,23830,518,5,615,755,1608,2268,769,7341,5004,8419,70,886,20245,598,21729,27.225701061802344,36.73,36.73,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hdll,4,3
+30,sha512,sha512,config_SW_HDLL_Benchmark,flow_completed,1h4m34s,0h33m53s,62417.84850582089,1.6486310000000002,15604.462126455222,25,1123.58,25726,0,0,0,0,0,0,0,159,0,-1,-1,2339152,235582,-112.01,-112.01,0.0,-0.15,0.0,-127998.87,-127998.87,0.0,0.0,0.0,1700344637,0.0,28.63,39.25,1.31,2.06,0.0,25701,25770,5703,5772,0,0,0,25726,624,0,429,1853,4118,1682,1301,3667,6372,7289,51,932,22460,434,23826,25.464731347084285,39.27,39.27,AREA 0,10,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hdll,4,3
+31,aes,aes,config_SW_HDLL_Benchmark,flow_completed,1h5m14s,0h35m36s,56745.024463819296,1.9571759999999998,11349.00489276386,20,1123.2,22212,0,0,0,0,0,0,0,105,0,-1,-1,1964324,202237,-7.41,-7.41,-2.6,-7.54,0.0,-27456.94,-27456.94,-141.36,-141.36,0.0,1529964784,0.0,20.41,22.11,0.77,0.28,0.0,22187,22256,3136,3205,0,0,0,22212,219,0,88,346,8956,2179,691,3103,4034,4478,19,1016,26771,270,28057,38.610038610038615,25.9,25.9,AREA 0,8,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hdll,4,3
+32,aes128,aes128,config_SW_HDLL_Benchmark,flow_completed,1h35m12s,0h45m36s,82475.69443592192,2.444502,20618.92360898048,28,1564.17,50403,0,0,0,0,0,0,0,266,0,-1,-1,2763448,375728,-5.61,-5.61,-5.69,-7.0,-5.82,-6370.39,-6370.39,-6264.44,-6264.44,-6327.39,2358427338,0.0,27.52,25.56,3.01,0.04,0.0,50279,50660,10452,10833,0,0,0,50403,0,5568,65,1223,1198,17800,6545,800,6496,12304,34,1136,33341,2554,37031,57.971014492753625,17.25,11.43,AREA 0,7,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hdll,4,3
+33,aes192,aes192,config_SW_HDLL_Benchmark,flow_completed,2h3m5s,0h49m44s,79539.12559175715,3.591,15907.825118351433,22,2222.52,57125,0,0,0,0,0,0,0,392,0,-1,-1,3615547,422198,-4.81,-4.81,-5.39,-7.36,-5.89,-6351.29,-6351.29,-6504.87,-6504.87,-7037.22,3154591713,0.0,25.38,23.11,0.82,0.0,0.0,57001,57446,13036,13481,0,0,0,57125,14,7968,55,1831,1158,19939,7390,684,7660,14657,32,1380,49472,2801,53653,54.7645125958379,18.259999999999998,12.37,AREA 0,9,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_hdll,4,3
+34,des3,des3,config_SW_HDLL_Benchmark,flow_completed,2h15m29s,0h53m12s,66910.86304106982,4.291082,13382.172608213965,23,2519.46,57424,0,0,0,0,0,0,0,395,0,-1,-1,3275298,441461,-21.83,-21.83,-21.37,-24.51,-21.25,-33722.27,-33722.27,-18036.93,-18036.93,-18661.03,2668122139,0.0,17.63,20.19,0.14,0.05,0.0,57367,57658,8959,9250,0,0,0,57424,1344,8808,144,1344,38112,5376,768,2416,5376,10344,13,1510,59040,1305,61855,34.674063800277395,28.84,7.59,AREA 0,7,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_hdll,4,3
+35,point_add,point_add,config_SW_HDLL_Benchmark,flow_completed,2h19m51s,0h57m33s,78933.68167688716,3.141726,19733.42041922179,30,2088.29,61997,0,0,0,0,0,0,0,371,0,-1,-1,4877254,527306,-44.11,-44.11,-10.52,-13.82,-13.38,-99520.61,-99520.61,-11728.54,-11728.54,-18092.9,3983160227,0.0,37.07,41.13,4.39,3.21,0.0,61619,62777,6131,7289,0,0,0,61997,857,1149,640,3041,18519,579,3,6546,10796,18519,17,1290,43021,1661,45972,42.771599657827196,23.380000000000003,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.15,sky130_fd_sc_hdll,4,3
+36,aes256,aes256,config_SW_HDLL_Benchmark,flow_completed,2h21m38s,0h58m8s,80123.44200310824,3.1559220000000003,24037.03260093247,33,2134.52,75859,0,0,0,0,0,0,0,416,0,-1,-1,4188694,542840,-1.84,-1.84,-1.92,-3.33,-2.48,-1263.02,-1263.02,-1259.66,-1259.66,-1364.59,3586519480,0.0,24.88,35.48,0.7,2.35,0.0,75735,76244,17643,18152,0,0,0,75859,0,11072,77,1733,1656,24387,9321,1104,9232,20103,34,1294,43477,2674,47445,57.20823798627002,17.48,15.0,AREA 0,9,30,1,153.6,153.18,0.35,0.05,sky130_fd_sc_hdll,4,3
+37,point_scalar_mult,point_scalar_mult,config_SW_HDLL_Benchmark,flow_completed,2h28m2s,1h0m30s,78748.75707043539,3.435432,19687.189267608846,29,2221.5,67634,0,0,0,0,0,0,0,466,0,-1,-1,4898419,539778,-44.1,-44.1,-8.38,-11.37,-8.94,-109108.28,-109108.28,-13936.8,-13936.8,-19183.25,4068309731,0.0,31.28,33.62,2.64,0.0,0.0,67254,68176,7456,8378,0,0,0,67634,253,1149,788,3213,18054,582,0,8651,12661,21169,17,1350,47384,2743,51477,52.79831045406548,18.939999999999998,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.05,sky130_fd_sc_hdll,4,3
+38,jpeg_encoder,jpeg_encoder,config_SW_HDLL_Benchmark,flow_completed,2h55m20s,1h18m11s,77326.5108080614,4.26626,15465.30216161228,24,2570.96,65979,0,0,0,0,0,0,0,486,0,-1,-1,6360849,614801,-24.71,-24.71,-9.5,-18.52,-16.62,-44635.71,-44635.71,-2970.26,-2970.26,-6154.72,5089147897,0.0,27.27,31.16,3.92,2.57,0.0,65964,66000,4381,4417,0,0,0,65979,3839,1,2296,5188,7634,15175,5614,4439,6723,10455,40,1506,58884,1124,61514,30.8641975308642,32.4,15.78,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hdll,4,3
+39,151,riscv_top,config_SW_HDLL_Benchmark,flow_completed,5h7m23s,1h27m46s,53528.461764775966,8.099691,13382.115441193992,20,4582.41,108391,0,0,0,0,0,0,0,462,0,-1,-1,7797806,784667,-256.71,-256.71,-4.7,-13.29,-4.51,-4460414.0,-4460414.0,-11907.09,-11907.09,-10559.66,5680004802,0.0,20.58,19.78,1.24,0.05,0.03,108194,108529,23324,23659,0,0,0,108391,109,2216,286,1088,3839,426,120,20245,24812,47704,20,2080,112009,2798,116887,18.3452577508714,54.51,50.0,DELAY 1,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hdll,4,3
+40,ldpc_decoder_802_3an,ldpc_decoder_802_3an,config_SW_HDLL_Benchmark,flow_failed,8h47m28s,-1,-941910000000.0,-1e-06,-94191000000.0,23,-1.0,94191,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,36949483489,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,92148,96242,2054,6148,0,0,0,94191,0,0,32,0,6519,19649,4544,2048,4098,6146,25,2514,163662,0,166176,12.987012987012987,77.0,77.0,DELAY 0,6,10,1,153.6,153.18,0.15,0.0,sky130_fd_sc_hdll,4,3
+41,sound,sound,config_SW_HDLL_Benchmark,flow_completed,10h47m8s,2h1m10s,68255.90934324119,12.759159,17063.977335810298,27,7018.92,217722,0,0,0,0,0,0,0,605,0,-1,-1,12569252,1839178,-10.59,-10.59,0.0,0.0,0.0,-129970.02,-129970.02,0.0,0.0,0.0,9186909932,0.0,21.01,21.05,0.4,0.04,0.0,217687,217804,217687,217804,0,0,0,217722,11691,1896,10906,21307,46996,25037,13741,15776,1102,1650,30,2614,177359,1796,181769,7.308338814587444,136.83,136.83,AREA 0,9,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hdll,4,3
diff --git a/openlane/regression_results/benchmark_results/SW_HS.csv b/openlane/regression_results/benchmark_results/SW_HS.csv
new file mode 100644
index 0000000..5ccaa23
--- /dev/null
+++ b/openlane/regression_results/benchmark_results/SW_HS.csv
@@ -0,0 +1,43 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,digital_pll_sky130_fd_sc_hd,digital_pll,config_TEST_SW_HS,flow_failed,0h0m36s,-1,2040816.3265306123,-1e-06,1000000.0,-1,-1.0,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,59.52380952380952,16.8,15.8,AREA 0,6,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_hs,4,4
+1,inverter,inverter,config_TEST_SW_HS,flow_completed,0h5m55s,0h5m14s,1089.3246187363834,0.001836,544.6623093681917,4,382.66,1,0,0,0,0,0,0,0,0,0,-1,-1,76,13,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.13,0.97,0.0,0.0,0.0,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,1,1,1,16,5,0,21,100.0,10.0,10.0,AREA 0,5,50,1,153.6,153.18,0.75,0.0,sky130_fd_sc_hs,4,4
+2,manual_macro_placement_test,manual_macro_placement_test,config_TEST_SW_HS,flow_completed,0h6m56s,0h5m12s,56.009230321156934,0.102024,19.603230612404925,1,419.47,2,0,0,0,0,0,0,0,2,0,-1,-1,20078,488,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,3.64,4.62,3.39,4.6,0.05,10,72,10,72,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,180,563,0,743,10.0,100.0,100.0,AREA 0,5,35,1,30.0,153.18,0.35,0.0,sky130_fd_sc_hs,0,0
+3,zipdiv,zipdiv,config_HS_first_rerun,flow_completed,0h7m29s,0h6m41s,63539.12951392566,0.048563999999999996,22238.69532987398,44,527.65,1080,0,0,0,0,0,0,0,1,0,-1,-1,49545,10065,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,36926298,0.0,33.03,29.53,1.28,0.0,0.0,1052,1148,118,214,0,0,0,1080,46,0,3,43,165,146,14,241,273,273,31,120,463,0,583,52.38344683080147,19.09,19.09,AREA 0,6,35,1,153.6,153.18,0.4,0.15,sky130_fd_sc_hs,4,4
+4,xtea,xtea,config_HS_first_rerun,flow_completed,0h8m41s,0h6m55s,70333.42932188454,0.098226,24616.700262659586,45,576.07,2418,0,0,0,0,0,0,0,6,0,-1,-1,147446,23652,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,116491155,0.0,46.4,43.96,2.94,1.25,0.0,2362,2613,123,374,0,0,0,2418,16,0,54,226,390,436,121,174,468,615,28,176,988,0,1164,38.417210910487896,26.03,26.03,AREA 0,6,35,1,153.6,153.18,0.4,0.15,sky130_fd_sc_hs,4,4
+5,s44,lut_s44,config_TEST_SW_HS,flow_completed,0h13m26s,0h12m12s,44683.98747005712,0.043416,2234.1993735028564,7,415.36,97,0,0,0,0,0,0,0,0,0,-1,-1,6663,1044,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5279922,0.0,3.91,3.65,0.0,0.0,0.0,94,114,38,58,0,0,0,97,0,0,0,0,0,0,0,32,41,32,4,114,411,0,525,33.333333333333336,30.0,30.0,AREA 0,5,5,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hs,4,4
+6,spm,spm,config_TEST_SW_HS,flow_completed,0h16m33s,0h15m31s,42597.40259740259,0.01375,20872.727272727272,54,444.0,287,0,0,0,0,0,0,0,0,0,-1,-1,9122,2215,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5730580,0.0,18.4,16.17,0.0,0.0,0.0,291,322,39,70,0,0,0,287,32,0,31,31,1,63,31,0,97,128,4,58,108,0,166,100.0,10.0,10.0,AREA 0,5,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_hs,4,4
+7,cic_decimator,cic_decimator,config_TEST_SW_HS,flow_completed,0h18m30s,0h16m28s,62959.818902093946,0.031806,25183.92756083758,48,498.91,801,0,0,0,0,0,0,0,0,0,-1,-1,30591,7001,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,19857159,0.0,28.08,22.4,0.21,0.0,0.0,790,823,119,152,0,0,0,801,15,0,21,51,90,92,51,220,131,112,16,94,269,0,363,100.0,10.0,10.0,AREA 0,6,40,1,15.0,15.0,0.45,0.0,sky130_fd_sc_hs,4,4
+8,usb,usb,config_TEST_SW_HS,flow_completed,0h19m58s,0h17m34s,50597.25311925719,0.041356,20238.901247702877,46,492.91,837,0,0,0,0,0,0,0,0,0,-1,-1,31610,7220,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,19723971,0.0,20.67,18.76,0.0,0.0,0.0,836,860,200,224,0,0,0,837,22,8,43,40,206,49,6,176,242,251,12,110,370,0,480,79.6812749003984,12.55,12.55,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_hs,4,4
+9,usb_cdc_core,usb_cdc_core,config_TEST_SW_HS,flow_completed,0h36m47s,0h31m18s,63659.16168324744,0.072574,28646.622757461348,51,555.52,2079,0,0,0,0,0,0,0,1,0,-1,-1,78605,16243,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,52298687,0.0,30.02,25.69,0.87,0.0,0.0,2075,2106,314,345,0,0,0,2079,99,0,110,89,676,130,41,252,365,683,19,150,693,0,843,64.1025641025641,15.6,15.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hs,4,4
+10,APU,APU,config_TEST_SW_HS,flow_completed,0h41m20s,0h29m9s,64099.112346379596,0.137956,22434.689321232858,44,575.89,3095,0,0,0,0,0,0,0,1,0,-1,-1,146362,28916,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,94677735,0.0,28.89,25.77,0.06,0.0,0.0,3068,3127,380,439,0,0,0,3095,86,28,103,170,344,251,52,709,683,867,26,212,1404,0,1616,58.8235294117647,17.0,17.0,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hs,4,4
+11,wbqspiflash,wbqspiflash,config_TEST_SW_HS,flow_completed,0h53m51s,0h43m37s,69700.39477779416,0.12209400000000001,20910.118433338248,41,572.12,2553,0,0,0,0,0,0,0,2,0,-1,-1,146343,25031,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,106634042,0.0,33.93,27.36,0.55,0.14,0.0,2526,2614,264,352,0,0,0,2553,55,1,147,155,796,79,6,376,656,885,20,198,1212,0,1410,53.022269353128316,18.86,18.86,AREA 0,6,30,1,153.6,153.18,0.35,0.0,sky130_fd_sc_hs,4,4
+12,synth_ram,synth_ram,config_TEST_SW_HS,flow_completed,1h11m43s,0h40m44s,51091.51479521851,0.2835,22991.18165784833,56,670.1,6518,0,0,0,0,0,0,0,3,0,-1,-1,456582,70287,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,250011549,0.0,45.76,35.41,1.71,0.77,0.0,6492,6578,2054,2140,0,0,0,6518,8,0,2,1,81,0,0,2080,2155,2080,8,308,2964,0,3272,20.0,50.0,50.0,AREA 0,5,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_hs,4,4
+13,point_scalar_mult,point_scalar_mult,config_HS_first_rerun,flow_completed,3h13m43s,1h7m53s,75755.58111687611,3.6461339999999995,15151.116223375224,27,1918.27,55243,0,0,0,0,0,0,946,75,0,-1,-1,4846268,518607,-21.64,-21.64,-0.33,-3.15,0.0,-46555.95,-46555.95,-6.32,-6.32,0.0,4051500631,0.0,36.83,32.87,5.98,0.17,0.0,54863,55785,7456,8378,0,0,0,55243,253,1149,788,3213,18054,582,0,8651,12661,13726,17,1134,40677,0,41811,100.0,10.0,10.0,AREA 0,5,20,1,153.6,153.18,0.25,0.05,sky130_fd_sc_hs,4,4
+14,y_dct,y_dct,config_HS_first_rerun,flow_completed,5h41m7s,1h27m11s,63922.10893726463,8.16525,9588.316340589694,20,3662.27,78291,0,0,0,0,0,0,48,113,0,-1,-1,7407274,631109,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,6689631501,0.0,25.46,21.61,0.96,0.11,0.0,100762,101409,4703,5350,0,0,0,78291,3238,72,1227,3318,3941,3531,161,10172,31779,27586,20,1704,91372,0,93076,48.732943469785575,20.52,20.52,AREA 0,5,15,1,153.6,153.18,0.2,0.0,sky130_fd_sc_hs,4,4
+15,ocs_blitter,ocs_blitter,config_TEST_SW_HS,flow_completed,1h28m5s,0h53m8s,65731.12250266835,0.304096,23005.89287593392,49,694.32,6996,0,0,0,0,0,0,0,6,0,-1,-1,458272,74664,-18.79,-18.79,0.0,-1.3,0.0,-2661.43,-2661.43,0.0,0.0,0.0,276392798,0.0,40.98,35.34,1.62,0.09,0.0,6944,7088,439,583,0,0,0,6996,164,0,189,595,1116,745,127,471,962,1734,27,318,3218,0,3536,54.94505494505495,18.2,18.2,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hs,4,4
+16,md5,md5,config_TEST_SW_HS,flow_completed,1h36m27s,1h9m24s,60802.48652406428,0.268786,21280.870283422497,47,668.08,5720,0,0,0,0,0,0,0,6,0,-1,-1,415257,60337,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,297487632,0.0,41.35,33.27,5.24,1.47,0.44,5598,5852,1175,1429,0,0,0,5720,80,0,137,240,1477,396,213,650,1208,1399,38,300,2812,0,3112,26.990553306342782,37.05,37.05,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_hs,4,4
+17,ldpc_decoder_802_3an,ldpc_decoder_802_3an,config_TEST_SW_HS,flow_failed,1h52m10s,-1,-922790000000.0,-1e-06,-92279000000.0,18,-1.0,92279,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-24.93,-24.93,-24.93,-24.93,-24.93,-51051.49,-51051.49,-51051.49,-51051.49,-51051.49,34340189885,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,90236,94330,2054,6148,0,0,0,92279,0,0,32,0,6519,19649,4544,2048,4098,6146,22,1980,123496,0,125476,9.810654370646521,101.93,77.0,DELAY 0,6,10,1,153.6,153.18,0.15,0.0,sky130_fd_sc_hs,4,4
+18,151,riscv_top,config_HS_first_rerun,flow_completed,6h18m4s,2h21m6s,51387.22475844128,7.120836,10277.444951688258,27,3504.43,73184,0,0,0,0,0,0,11,120,0,-1,-1,6881756,743020,-179.09,-179.09,0.0,0.0,0.0,-2901186.25,-2901186.25,0.0,0.0,0.0,5095497474,0.0,25.87,22.71,1.37,0.83,0.0,72987,73322,23324,23659,0,0,0,73184,109,2216,286,1088,3839,426,120,20245,24812,25565,22,1590,79694,0,81284,20.0,50.0,50.0,DELAY 1,5,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hs,4,4
+19,PPU,PPU,config_TEST_SW_HS,flow_completed,2h7m20s,0h55m43s,53353.710461596456,0.880726,10670.742092319291,28,790.63,9398,0,0,0,0,0,0,0,10,0,-1,-1,750221,104523,-10.16,-10.16,0.0,0.0,0.0,-1844.88,-1844.88,0.0,0.0,0.0,486061374,0.0,27.23,19.94,0.37,0.09,0.0,9339,9422,2898,2981,0,0,0,9398,53,8,55,72,460,113,21,2942,3193,3308,15,552,9589,0,10141,55.55555555555556,18.0,18.0,AREA 0,8,20,1,153.6,153.18,0.25,0.05,sky130_fd_sc_hs,4,4
+20,genericfir,genericfir,config_TEST_SW_HS,flow_completed,2h41m41s,2h8m50s,49309.74167940392,0.42700600000000005,22189.383755731767,50,720.74,9475,0,0,0,0,0,0,0,3,0,-1,-1,398743,86811,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,255052655,0.0,30.61,24.87,0.29,0.09,0.0,12499,12551,6835,6887,0,0,0,9475,0,0,2001,3390,4008,3000,750,7560,3782,3780,6,380,4512,0,4892,100.0,10.0,10.0,AREA 0,7,45,1,153.6,153.18,0.5,0.1,sky130_fd_sc_hs,4,4
+21,BM64,BM64,config_TEST_SW_HS,flow_completed,2h56m31s,1h34m42s,66654.02009860548,0.706384,11997.723617748987,27,770.57,8475,0,0,0,0,0,0,0,19,0,-1,-1,1117332,98915,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,993562777,0.0,39.9,38.35,3.26,0.62,0.0,7969,8990,785,1806,0,0,0,8475,26,0,12,341,2174,989,307,2573,1801,1293,33,492,7684,0,8176,50.0,20.0,20.0,AREA 0,6,18,1,153.6,153.18,0.23,0.0,sky130_fd_sc_hs,4,4
+22,y_huff,y_huff,config_TEST_SW_HS,flow_completed,3h11m0s,2h6m22s,60858.34695106217,0.58135,18257.50408531865,40,801.75,10614,0,0,0,0,0,0,4,13,0,-1,-1,986233,114787,-1.08,-1.08,0.0,0.0,0.0,-1336.91,-1336.91,0.0,0.0,0.0,818611577,0.0,52.13,48.03,7.63,1.1,0.0,10646,11321,2383,3058,0,0,0,10614,237,0,146,384,1310,575,87,4679,4830,3153,16,446,6298,0,6744,88.1057268722467,11.35,11.35,AREA 0,6,30,1,153.6,153.18,0.35,0.15,sky130_fd_sc_hs,4,4
+23,des,des,config_TEST_SW_HS,flow_completed,3h12m14s,2h15m6s,73760.61336606245,0.618526,25816.214678121854,40,845.79,15968,0,0,0,0,0,0,2,21,0,-1,-1,772248,134391,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,626055829,0.0,38.27,32.83,4.39,0.43,0.0,15909,16090,1957,2138,0,0,0,15968,432,1984,48,448,12688,1792,256,768,1792,512,13,460,6610,0,7070,50.0,20.0,20.0,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hs,4,4
+24,picorv32a,picorv32a,config_TEST_SW_HS,flow_completed,3h18m57s,2h8m39s,70840.84534519963,0.5828760000000001,24794.295870819868,47,869.55,14452,0,0,0,0,0,0,0,8,0,-1,-1,1118361,149464,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,785596635,0.0,54.06,47.45,13.16,6.03,0.0,14172,14554,1565,1947,0,0,0,14452,1159,227,896,560,2391,2462,615,1664,2132,2900,134,446,6298,0,6744,40.43671653861706,24.73,24.73,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hs,4,4
+25,chacha,chacha,config_TEST_SW_HS,flow_completed,3h33m32s,1h57m26s,73441.85612208147,0.899596,18360.46403052037,36,955.29,16517,0,0,0,0,0,0,0,11,0,-1,-1,1585656,175128,-8.85,-8.85,0.0,0.0,0.0,-2412.74,-2412.74,0.0,0.0,0.0,1302910180,0.0,46.98,44.39,16.0,5.49,0.0,16492,16561,2389,2458,0,0,0,16517,605,5,604,825,810,2011,971,3036,3035,3673,57,558,9833,0,10391,38.446751249519416,26.01,26.01,AREA 0,6,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hs,4,4
+26,usbf_device,usbf_device,config_TEST_SW_HS,flow_completed,3h53m19s,3h8m52s,63137.71013794133,0.609897,25255.084055176532,48,874.93,15403,0,0,0,0,0,0,0,5,0,-1,-1,939257,146158,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,656374352,0.0,39.89,36.62,2.27,0.76,0.0,15378,15524,3775,3921,0,0,0,15403,675,0,362,157,4505,280,61,3692,4004,4615,14,456,6553,0,7009,68.4931506849315,14.6,14.6,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_hs,4,4
+27,ldpcenc,ldpcenc,config_TEST_SW_HS,flow_completed,3h53m37s,2h13m50s,65395.085241789384,1.07635,16348.771310447346,38,1029.18,17597,0,0,0,0,0,0,0,64,0,-1,-1,1823802,207324,-33.26,-33.26,0.0,-0.66,0.0,-22744.2,-22744.2,0.0,0.0,0.0,1479233557,0.0,41.66,38.5,7.74,1.77,0.0,17578,17633,1527,1582,0,0,0,17597,103,94,990,79,2098,1958,84,1265,2487,2565,13,610,11664,0,12274,77.51937984496124,12.9,12.9,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hs,4,4
+28,sha3,sha3,config_TEST_SW_HS,flow_completed,3h56m13s,3h13m38s,65164.22261072658,0.628785,22807.4779137543,45,884.91,14341,0,0,0,0,0,0,0,13,0,-1,-1,973196,147618,-2.06,-2.06,-1.24,-4.52,0.0,-60.62,-60.62,-66.37,-66.37,0.0,630279903,0.0,44.88,39.91,7.08,3.82,0.25,14316,14385,3031,3100,0,0,0,14341,911,0,893,238,878,848,435,3088,3162,3709,23,464,6784,0,7248,78.67820613690007,12.71,12.71,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_hs,4,4
+29,blabla,blabla,config_TEST_SW_HS,flow_completed,4h5m58s,1h53m58s,77823.52137431077,1.268946,10117.0577786604,22,935.21,12838,0,0,0,0,0,0,0,41,0,-1,-1,2377113,152135,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2185686505,0.0,48.92,49.82,14.93,4.89,0.0,12337,13744,1105,2512,0,0,0,12838,654,5,575,813,507,2076,906,2190,2894,2059,58,664,13859,0,14523,15.384615384615385,65.0,65.0,AREA 0,5,13,1,153.6,153.18,0.18,0.1,sky130_fd_sc_hs,4,4
+30,aes_cipher,aes_cipher,config_TEST_SW_HS,flow_completed,4h11m32s,3h27m45s,87607.93116348673,0.66825,21901.982790871683,36,915.18,14636,0,0,0,0,0,0,75,6,0,-1,-1,1267730,166675,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1050991121,0.0,46.83,43.0,7.66,2.01,0.0,14516,14897,411,792,0,0,0,14636,461,386,73,357,18246,848,301,148,659,660,18,478,7228,0,7706,99.10802775024777,10.09,10.09,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hs,4,4
+31,aes,aes,config_TEST_SW_HS,flow_completed,4h29m28s,3h5m57s,63387.451214559114,1.487124,12677.490242911823,29,1120.23,18853,0,0,0,0,0,0,0,27,0,-1,-1,1788919,222940,-0.16,-0.16,0.0,0.0,0.0,-423.86,-423.86,0.0,0.0,0.0,1309171269,0.0,33.54,26.77,2.09,0.23,0.2,18828,18897,3136,3205,0,0,0,18853,219,0,88,346,8956,2179,691,3103,4034,4222,18,720,16288,0,17008,38.610038610038615,25.9,25.9,AREA 0,8,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hs,4,4
+32,aes_core,aes_core,config_TEST_SW_HS,flow_completed,4h31m51s,3h21m8s,66708.18980310406,1.101394,16677.047450776015,38,1080.71,18368,0,0,0,0,0,0,0,32,0,-1,-1,2039979,230309,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1614988012,0.0,47.29,40.6,9.74,1.05,0.0,18249,18758,2490,2999,0,0,0,18368,303,0,175,343,8961,2035,834,2717,3710,3696,19,618,11971,0,12589,46.992481203007515,21.28,21.28,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hs,4,4
+33,sha512,sha512,config_TEST_SW_HS,flow_completed,4h33m45s,2h37m9s,63354.798248759274,1.511614,15838.699562189819,37,1219.99,23942,0,0,0,0,0,0,0,37,0,-1,-1,2378232,285269,-33.84,-33.84,0.0,0.0,0.0,-34419.98,-34419.98,0.0,0.0,0.0,1707843573,0.0,43.15,44.48,5.44,3.92,0.0,23917,23986,5703,5772,0,0,0,23942,624,0,429,1853,4118,1682,1301,3667,6372,7289,43,726,16603,0,17329,25.464731347084285,39.27,39.27,AREA 0,10,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hs,4,4
+34,salsa20,salsa20,config_TEST_SW_HS,flow_completed,4h34m47s,3h22m32s,66309.70544950872,1.478592,13261.941089901746,29,1087.31,19609,0,0,0,0,0,0,2,41,0,-1,-1,2223446,220131,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1884297670,0.0,39.36,32.93,6.6,0.96,0.0,19584,19653,4073,4142,0,0,0,19609,518,5,615,755,1608,2268,769,7341,5004,4742,60,718,16241,0,16959,27.225701061802344,36.73,36.73,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hs,4,4
+35,aes128,aes128,config_TEST_SW_HS,flow_completed,4h54m45s,3h0m27s,68252.09376377477,2.431984,17063.023440943693,30,1412.33,41497,0,0,0,0,0,0,317,52,0,-1,-1,2597497,332924,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2293628181,0.0,34.59,26.32,5.53,0.07,0.0,41373,41754,10452,10833,0,0,0,41497,0,5568,65,1223,1198,17800,6545,800,6496,6736,29,924,26908,0,27832,87.48906386701663,11.43,11.43,AREA 0,7,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_hs,4,4
+36,aes192,aes192,config_TEST_SW_HS,flow_completed,5h38m19s,3h37m1s,64932.29093955046,3.5815,12986.458187910093,25,1736.87,46511,0,0,0,0,0,0,720,72,0,-1,-1,3405410,378950,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,3044031058,0.0,30.75,24.23,3.9,0.13,0.0,46387,46832,13036,13481,0,0,0,46511,14,7968,55,1831,1158,19939,7390,684,7660,6689,31,1124,39758,0,40882,80.84074373484236,12.37,12.37,AREA 0,9,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_hs,4,4
+37,aes256,aes256,config_TEST_SW_HS,flow_completed,5h54m50s,3h49m15s,64481.40577537214,3.113404,19344.42173261164,36,1789.38,60227,0,0,0,0,0,0,657,93,0,-1,-1,4028307,478989,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,3532346146,0.0,31.59,37.6,1.85,1.38,0.0,60103,60612,17643,18152,0,0,0,60227,0,11072,77,1733,1656,24387,9321,1104,9232,9031,29,1048,34710,0,35758,66.66666666666667,15.0,15.0,AREA 0,9,30,1,153.6,153.18,0.35,0.05,sky130_fd_sc_hs,4,4
+38,des3,des3,config_TEST_SW_HS,flow_completed,6h14m46s,4h42m31s,70663.75259706432,3.5588260000000003,14132.750519412864,24,1790.59,50296,0,0,0,0,0,0,1012,65,0,-1,-1,2847695,431599,-12.35,-12.35,-9.54,-12.61,-8.35,-19384.8,-19384.8,-6670.48,-6670.48,-5608.64,2273959018,0.0,24.28,21.91,1.91,0.6,0.0,50239,50530,8959,9250,0,0,0,50296,1344,8808,144,1344,38112,5376,768,2416,5376,1536,14,1120,39615,0,40735,62.73525721455458,15.94,7.59,AREA 0,7,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_hs,4,4
+39,point_add,point_add,config_TEST_SW_HS,flow_completed,6h18m24s,4h32m54s,77397.15332780207,2.613016,19349.288331950516,34,1708.94,50560,0,0,0,0,0,0,1576,56,0,-1,-1,4546028,489989,-21.64,-21.64,0.0,-1.28,0.0,-45871.29,-45871.29,0.0,0.0,0.0,3458780408,0.0,48.08,42.66,16.2,17.5,0.66,50182,51340,6131,7289,0,0,0,50560,857,1149,640,3041,18519,579,3,6546,10796,12400,17,958,28856,0,29814,100.0,10.0,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.15,sky130_fd_sc_hs,4,4
+40,jpeg_encoder,jpeg_encoder,config_TEST_SW_HS,flow_completed,7h11m39s,4h57m16s,76947.72442822355,3.7888059999999997,15389.544885644711,26,1986.16,58308,0,0,0,0,0,0,15,88,21,-1,-1,5128099,570992,-14.11,-14.11,0.0,0.0,0.0,-20573.37,-20573.37,0.0,0.0,0.0,4234532953,0.0,34.1,30.34,5.74,2.12,0.0,58293,58329,4381,4417,0,0,0,58308,3839,1,2296,5188,7634,15175,5614,4439,6723,6061,37,1156,42046,0,43202,63.37135614702155,15.78,15.78,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_hs,4,4
+41,sound,sound,config_TEST_SW_HS,flow_completed,23h43m18s,8h47m10s,70442.28806499652,11.387194000000001,17610.57201624913,34,6350.41,200535,0,0,0,0,0,0,9,136,0,-1,-1,12005488,2072390,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,8298960128,0.0,30.11,23.65,0.69,0.05,0.0,200500,200617,200500,200617,0,0,0,200535,11691,1896,10906,21307,46996,25037,13741,15776,1102,1650,30,2014,128133,0,130147,7.308338814587444,136.83,136.83,AREA 0,9,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hs,4,4
diff --git a/openlane/regression_results/benchmark_results/SW_LS.csv b/openlane/regression_results/benchmark_results/SW_LS.csv
new file mode 100644
index 0000000..cf7ff04
--- /dev/null
+++ b/openlane/regression_results/benchmark_results/SW_LS.csv
@@ -0,0 +1,43 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,digital_pll_sky130_fd_sc_hd,digital_pll,config_TEST_SW_LS,flow_failed,0h0m42s,-1,2040816.3265306123,-1e-06,1000000.0,-1,-1.0,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,59.52380952380952,16.8,15.8,AREA 0,6,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_ls,4,4
+1,inverter,inverter,config_TEST_SW_LS,flow_completed,0h6m56s,0h6m15s,1089.3246187363834,0.001836,544.6623093681917,4,380.54,1,0,0,0,0,0,0,0,0,0,0,-1,75,13,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.13,1.21,0.0,0.0,0.0,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,1,1,1,16,5,0,21,100.0,10.0,10.0,AREA 0,5,50,1,153.6,153.18,0.75,0.0,sky130_fd_sc_ls,4,4
+2,manual_macro_placement_test,manual_macro_placement_test,config_TEST_SW_LS,flow_completed,0h8m56s,0h6m45s,56.009230321156934,0.102024,19.603230612404925,1,420.12,2,0,0,0,0,0,0,0,2,0,-1,-1,20081,498,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,3.64,4.62,3.38,4.6,0.05,10,72,10,72,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,180,563,0,743,10.0,100.0,100.0,AREA 0,5,35,1,30.0,153.18,0.35,0.0,sky130_fd_sc_ls,0,0
+3,cic_decimator,cic_decimator,config_ls_first_rerun,flow_completed,0h7m39s,0h7m13s,62959.818902093946,0.031806,25183.92756083758,48,498.89,801,0,0,0,0,0,0,0,0,0,0,-1,31136,7163,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,20226572,0.0,27.83,23.16,0.04,0.0,0.0,790,823,119,152,0,0,0,801,15,0,21,51,90,92,51,220,131,112,16,94,269,0,363,100.0,10.0,10.0,AREA 0,6,40,1,15.0,15.0,0.45,0.0,sky130_fd_sc_ls,4,4
+4,wbqspiflash,wbqspiflash,config_ls_first_rerun,flow_completed,0h11m17s,0h9m54s,69100.19528316059,0.10556099999999999,24185.068349106205,47,584.73,2553,0,0,0,0,0,0,0,2,0,0,-1,151457,25406,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,99369767,0.0,40.11,32.14,1.27,0.23,0.0,2526,2614,264,352,0,0,0,2553,55,1,147,155,796,79,6,376,656,885,21,184,1079,0,1263,53.022269353128316,18.86,18.86,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ls,4,4
+4,xtea,xtea,config_ls_second_rerun,flow_completed,0h10m5s,0h8m17s,70333.42932188454,0.098226,24616.700262659586,45,586.81,2418,0,0,0,0,0,0,0,3,0,0,-1,148019,23636,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,116283445,0.0,47.0,43.67,2.85,0.89,0.0,2362,2613,123,374,0,0,0,2418,16,0,54,226,390,436,121,174,468,615,28,176,988,0,1164,38.417210910487896,26.03,26.03,AREA 0,6,35,1,153.6,153.18,0.4,0.15,sky130_fd_sc_ls,4,4
+6,s44,lut_s44,config_TEST_SW_LS,flow_completed,0h21m5s,0h19m32s,44683.98747005712,0.043416,2234.1993735028564,7,415.36,97,0,0,0,0,0,0,0,0,0,0,-1,6676,1043,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5279922,0.0,3.91,3.65,0.0,0.0,0.0,94,114,38,58,0,0,0,97,0,0,0,0,0,0,0,32,41,32,4,114,411,0,525,33.333333333333336,30.0,30.0,AREA 0,5,5,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ls,4,4
+7,spm,spm,config_TEST_SW_LS,flow_completed,0h22m41s,0h21m30s,42597.40259740259,0.01375,20872.727272727272,54,442.45,287,0,0,0,0,0,0,0,0,0,0,-1,9112,2196,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5730580,0.0,18.05,16.17,0.0,0.0,0.0,291,322,39,70,0,0,0,287,32,0,31,31,1,63,31,0,97,128,4,58,108,0,166,100.0,10.0,10.0,AREA 0,5,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_ls,4,4
+8,y_huff,y_huff,config_ls_first_rerun,flow_completed,0h31m5s,0h21m29s,60590.83773369488,0.5005,21206.79320679321,51,815.16,10614,0,0,0,0,0,0,0,13,0,0,-1,1025203,125431,-5.32,-5.32,-5.11,-7.91,-3.78,-7300.75,-7300.75,-3686.48,-3686.48,-2058.48,760865184,0.0,58.65,55.02,14.41,8.17,0.0,10646,11321,2383,3058,0,0,0,10614,237,0,146,384,1310,575,87,4679,4830,3153,16,412,5304,0,5716,66.09385327164574,15.129999999999999,11.35,AREA 0,6,35,1,153.6,153.18,0.4,0.15,sky130_fd_sc_ls,4,4
+9,usb,usb,config_TEST_SW_LS,flow_completed,0h27m12s,0h24m44s,50657.703839829774,0.041356,20263.08153593191,45,495.16,838,0,0,0,0,0,0,0,0,0,0,-1,31071,7088,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,19627152,0.0,20.34,18.34,0.09,0.0,0.0,837,861,200,224,0,0,0,838,22,8,43,40,206,49,6,176,242,251,12,110,370,0,480,79.6812749003984,12.55,12.55,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_ls,4,4
+10,zipdiv,zipdiv,config_TEST_SW_LS,flow_completed,0h29m10s,0h26m13s,62790.69767441861,0.043,25116.279069767446,50,520.77,1080,0,0,0,0,0,0,0,0,0,0,-1,49798,10061,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,34898285,0.0,37.92,33.62,1.52,0.0,0.0,1052,1148,118,214,0,0,0,1080,46,0,3,43,165,146,14,241,273,273,31,112,404,0,516,52.38344683080147,19.09,19.09,AREA 0,6,40,1,153.6,153.18,0.45,0.15,sky130_fd_sc_ls,4,4
+11,usb_cdc_core,usb_cdc_core,config_TEST_SW_LS,flow_completed,0h38m4s,0h31m50s,63689.781770637186,0.072574,28660.401796786733,51,547.68,2080,0,0,0,0,0,0,0,3,0,0,-1,79282,16356,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,52246240,0.0,30.38,26.08,0.36,0.0,0.0,2076,2107,314,345,0,0,0,2080,99,0,110,89,676,130,41,252,365,683,19,150,693,0,843,64.1025641025641,15.6,15.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ls,4,4
+12,APU,APU,config_TEST_SW_LS,flow_completed,0h50m45s,0h36m41s,64099.112346379596,0.137956,22434.689321232858,44,575.71,3095,0,0,0,0,0,0,0,2,0,0,-1,147078,28982,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,93970224,0.0,29.0,25.77,0.07,0.0,0.0,3068,3127,380,439,0,0,0,3095,86,28,103,170,344,251,52,709,683,867,26,212,1404,0,1616,58.8235294117647,17.0,17.0,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ls,4,4
+13,synth_ram,synth_ram,config_TEST_SW_LS,flow_completed,1h27m5s,0h49m36s,51091.51479521851,0.2835,22991.18165784833,56,661.34,6518,0,0,0,0,0,0,0,9,0,0,-1,466775,70936,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,250943518,0.0,46.66,36.32,1.95,0.56,0.0,6492,6578,2054,2140,0,0,0,6518,8,0,2,1,81,0,0,2080,2155,2080,8,308,2964,0,3272,20.0,50.0,50.0,AREA 0,5,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ls,4,4
+14,ocs_blitter,ocs_blitter,config_TEST_SW_LS,flow_completed,1h50m48s,1h9m7s,65731.12250266835,0.304096,23005.89287593392,49,701.21,6996,0,0,0,0,0,0,0,5,0,0,-1,465255,75484,-33.81,-33.81,-6.51,-9.67,-6.1,-5887.58,-5887.58,-132.95,-132.95,-118.28,275266344,0.0,42.03,35.69,1.23,0.22,0.0,6944,7088,439,583,0,0,0,6996,164,0,189,595,1116,745,127,471,962,1734,27,318,3218,0,3536,41.1522633744856,24.299999999999997,18.2,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ls,4,4
+15,md5,md5,config_TEST_SW_LS,flow_completed,1h52m25s,1h17m25s,60813.11632940067,0.268786,21284.590715290233,47,671.64,5721,0,0,0,0,0,0,0,4,0,0,-1,412325,60225,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,297365406,0.0,41.71,33.22,4.24,1.54,0.0,5599,5853,1175,1429,0,0,0,5721,80,0,137,240,1477,396,213,650,1208,1399,38,300,2812,0,3112,26.990553306342782,37.05,37.05,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ls,4,4
+16,PPU,PPU,config_TEST_SW_LS,flow_completed,2h43m12s,1h10m18s,53353.710461596456,0.880726,10670.742092319291,28,795.14,9398,0,0,0,0,0,0,0,17,0,0,-1,763760,105403,-20.93,-20.93,0.0,-1.71,0.0,-5037.73,-5037.73,0.0,0.0,0.0,491276864,0.0,27.33,20.62,0.37,0.09,0.0,9339,9422,2898,2981,0,0,0,9398,53,8,55,72,460,113,21,2942,3193,3308,15,552,9589,0,10141,55.55555555555556,18.0,18.0,AREA 0,8,20,1,153.6,153.18,0.25,0.05,sky130_fd_sc_ls,4,4
+17,genericfir,genericfir,config_TEST_SW_LS,flow_completed,3h4m35s,2h26m49s,49309.74167940392,0.42700600000000005,22189.383755731767,50,715.54,9475,0,0,0,0,0,0,0,1,0,0,-1,405850,87048,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,253238877,0.0,30.38,25.85,0.24,0.02,0.0,12499,12551,6835,6887,0,0,0,9475,0,0,2001,3390,4008,3000,750,7560,3782,3780,6,380,4512,0,4892,100.0,10.0,10.0,AREA 0,7,45,1,153.6,153.18,0.5,0.1,sky130_fd_sc_ls,4,4
+18,BM64,BM64,config_TEST_SW_LS,flow_completed,3h14m46s,1h40m24s,66661.88487973806,0.706384,11999.13927835285,28,785.94,8476,0,0,0,0,0,0,0,22,0,0,-1,1130217,101322,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,998818790,0.0,39.82,38.72,4.32,0.36,0.0,7970,8991,785,1806,0,0,0,8476,26,0,12,341,2174,989,307,2573,1801,1293,34,492,7684,0,8176,50.0,20.0,20.0,AREA 0,6,18,1,153.6,153.18,0.23,0.0,sky130_fd_sc_ls,4,4
+19,des,des,config_TEST_SW_LS,flow_completed,3h32m47s,2h39m17s,73760.61336606245,0.618526,25816.214678121854,40,854.71,15968,0,0,0,0,0,0,0,21,0,0,-1,774799,135009,0.0,0.0,-3.28,-7.28,-1.23,0.0,0.0,-116.46,-116.46,-18.71,626592590,0.0,38.06,33.04,4.8,0.58,0.0,15909,16090,1957,2138,0,0,0,15968,432,1984,48,448,12688,1792,256,768,1792,512,13,460,6610,0,7070,47.103155911446066,21.23,20.0,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_ls,4,4
+20,picorv32a,picorv32a,config_TEST_SW_LS,flow_completed,3h34m18s,2h26m20s,70840.84534519963,0.5828760000000001,24794.295870819868,47,877.34,14452,0,0,0,0,0,0,0,13,0,0,-1,1110638,149802,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,778729960,0.0,54.82,46.5,14.18,3.58,0.0,14172,14554,1565,1947,0,0,0,14452,1159,227,896,560,2391,2462,615,1664,2132,2900,134,446,6298,0,6744,40.43671653861706,24.73,24.73,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_ls,4,4
+21,usbf_device,usbf_device,config_TEST_SW_LS,flow_completed,3h54m28s,3h6m53s,62938.10589112603,0.54385,28322.147651006715,54,884.18,15403,0,0,0,0,0,0,0,15,0,0,-1,1150849,157393,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,622942032,0.0,50.64,50.53,5.08,5.27,0.0,15378,15524,3775,3921,0,0,0,15403,675,0,362,157,4505,280,61,3692,4004,4615,14,430,5857,0,6287,68.4931506849315,14.6,14.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ls,4,4
+22,chacha,chacha,config_TEST_SW_LS,flow_completed,3h58m44s,2h32m27s,73441.85612208147,0.899596,18360.46403052037,37,967.33,16517,0,0,0,0,0,0,0,32,0,0,-1,1603897,179383,-24.41,-24.41,-5.4,-10.26,-5.37,-9415.42,-9415.42,-805.44,-805.44,-765.99,1310766065,0.0,48.39,44.31,15.69,6.11,0.0,16492,16561,2389,2458,0,0,0,16517,605,5,604,825,810,2011,971,3036,3035,3673,57,558,9833,0,10391,31.867431485022305,31.380000000000003,26.01,AREA 0,6,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_ls,4,4
+23,sha3,sha3,config_TEST_SW_LS,flow_completed,4h13m22s,3h31m9s,65164.22261072658,0.628785,22807.4779137543,45,889.39,14341,0,0,0,0,0,0,0,9,0,0,-1,995752,149259,-6.02,-6.02,-6.08,-10.78,-3.81,-9055.87,-9055.87,-1084.5,-1084.5,-563.87,634099099,0.0,46.68,40.8,5.53,4.69,0.9,14316,14385,3031,3100,0,0,0,14341,911,0,893,238,878,848,435,3088,3162,3709,23,464,6784,0,7248,60.53268765133172,16.52,12.71,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_ls,4,4
+24,ldpcenc,ldpcenc,config_TEST_SW_LS,flow_completed,4h19m58s,2h57m20s,65406.23403168115,1.07635,16351.558507920288,38,1027.26,17600,0,0,0,0,0,0,0,38,0,0,-1,1823750,207378,-52.63,-52.63,-4.2,-5.88,-4.25,-41625.77,-41625.77,-464.3,-464.3,-213.69,1480195009,0.0,41.04,38.42,8.42,2.14,0.0,17581,17636,1527,1582,0,0,0,17600,103,94,990,79,2098,1958,84,1265,2487,2565,13,610,11664,0,12274,58.30903790087464,17.15,12.9,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ls,4,4
+25,blabla,blabla,config_TEST_SW_LS,flow_completed,4h22m35s,2h4m48s,77823.52137431077,1.268946,10117.0577786604,22,966.26,12838,0,0,0,0,0,0,0,35,0,0,-1,2391557,156180,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2195298746,0.0,49.59,50.44,13.7,5.24,0.0,12337,13744,1105,2512,0,0,0,12838,654,5,575,813,507,2076,906,2190,2894,2059,57,664,13859,0,14523,15.384615384615385,65.0,65.0,AREA 0,5,13,1,153.6,153.18,0.18,0.1,sky130_fd_sc_ls,4,4
+26,aes_cipher,aes_cipher,config_TEST_SW_LS,flow_completed,4h32m2s,3h46m55s,87613.91694725027,0.66825,21903.479236812567,37,940.12,14637,0,0,0,0,0,0,0,2,0,0,-1,1287806,170445,0.0,0.0,0.0,-0.04,0.0,0.0,0.0,0.0,0.0,0.0,1052178226,0.0,47.59,42.97,8.97,2.0,0.0,14517,14898,411,792,0,0,0,14637,461,386,73,357,18246,848,301,148,659,660,18,478,7228,0,7706,99.10802775024777,10.09,10.09,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ls,4,4
+27,salsa20,salsa20,config_TEST_SW_LS,flow_completed,4h48m46s,3h29m15s,66309.70544950872,1.478592,13261.941089901746,29,1098.79,19609,0,0,0,0,0,0,0,46,0,0,-1,2215859,220692,-10.39,-10.39,0.0,0.0,0.0,-1464.66,-1464.66,0.0,0.0,0.0,1882514707,0.0,39.17,33.01,6.28,1.23,0.0,19584,19653,4073,4142,0,0,0,19609,518,5,615,755,1608,2268,769,7341,5004,4742,60,718,16241,0,16959,27.225701061802344,36.73,36.73,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ls,4,4
+28,aes,aes,config_TEST_SW_LS,flow_completed,4h54m24s,3h37m45s,63387.451214559114,1.487124,12677.490242911823,29,1129.2,18853,0,0,0,0,0,0,0,27,0,0,-1,1792468,224821,-10.15,-10.15,-2.13,-7.56,0.0,-27753.22,-27753.22,-129.6,-129.6,0.0,1314099158,0.0,33.46,27.22,1.6,0.13,0.11,18828,18897,3136,3205,0,0,0,18853,219,0,88,346,8956,2179,691,3103,4034,4222,18,720,16288,0,17008,38.610038610038615,25.9,25.9,AREA 0,8,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ls,4,4
+29,sha512,sha512,config_TEST_SW_LS,flow_completed,4h58m8s,3h10m39s,63354.798248759274,1.511614,15838.699562189819,37,1238.04,23942,0,0,0,0,0,0,0,35,0,0,-1,2374473,284679,-71.79,-71.79,0.0,-5.69,0.0,-109347.12,-109347.12,0.0,0.0,0.0,1742444839,0.0,41.6,45.51,4.87,5.2,0.0,23917,23986,5703,5772,0,0,0,23942,624,0,429,1853,4118,1682,1301,3667,6372,7289,43,726,16603,0,17329,25.464731347084285,39.27,39.27,AREA 0,10,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_ls,4,4
+30,aes_core,aes_core,config_TEST_SW_LS,flow_completed,5h3m44s,3h56m14s,66708.18980310406,1.101394,16677.047450776015,38,1093.71,18368,0,0,0,0,0,0,0,28,0,0,-1,2057892,233852,-8.09,-8.09,-1.57,-5.46,0.0,-19861.81,-19861.81,-99.6,-99.6,0.0,1623846359,0.0,47.9,40.39,10.24,1.35,0.0,18249,18758,2490,2999,0,0,0,18368,303,0,175,343,8961,2035,834,2717,3710,3696,19,618,11971,0,12589,46.992481203007515,21.28,21.28,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ls,4,4
+31,aes128,aes128,config_TEST_SW_LS,flow_completed,5h23m45s,3h21m23s,68253.7385114376,2.431984,17063.4346278594,30,1439.8,41498,0,0,0,0,0,0,0,72,0,0,-1,2605123,336879,-1.26,-1.26,-0.96,-2.48,-1.14,-589.0,-589.0,-255.71,-255.71,-252.16,2292105682,0.0,34.62,26.41,5.6,0.06,0.0,41374,41755,10452,10833,0,0,0,41498,0,5568,65,1223,1198,17800,6545,800,6496,6736,29,924,26908,0,27832,79.55449482895783,12.57,11.43,AREA 0,7,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_ls,4,4
+32,aes192,aes192,config_TEST_SW_LS,flow_completed,6h16m52s,4h11m32s,64932.29093955046,3.5815,12986.458187910093,25,2012.96,46511,0,0,0,0,0,0,0,78,0,0,-1,3434798,385119,-1.41,-1.41,-0.91,-2.78,-1.41,-474.49,-474.49,-205.06,-205.06,-236.16,3044031058,0.0,30.71,24.4,4.37,0.21,0.0,46387,46832,13036,13481,0,0,0,46511,14,7968,55,1831,1158,19939,7390,684,7660,6689,31,1124,39758,0,40882,72.5689404934688,13.78,12.37,AREA 0,9,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_ls,4,4
+33,ldpc_decoder_802_3an,ldpc_decoder_802_3an,config_TEST_SW_LS,flow_failed,6h40m24s,-1,-902260000000.0,-1e-06,-90226000000.0,23,-1.0,90226,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-71.14,-71.14,0.0,0.0,0.0,-145691.72,-145691.72,0.0,0.0,0.0,33432627469,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,88183,92277,2054,6148,0,0,0,90226,0,0,32,0,6519,19649,4544,2048,4098,6146,23,1972,122504,0,124476,12.987012987012987,77.0,77.0,DELAY 0,6,10,1,153.6,153.18,0.15,0.0,sky130_fd_sc_ls,4,4
+34,aes256,aes256,config_TEST_SW_LS,flow_completed,6h40m25s,4h38m28s,64481.40577537214,3.113404,19344.42173261164,36,1845.42,60227,0,0,0,0,0,0,0,94,0,0,-1,4061674,485975,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,3532346146,0.0,32.29,37.71,1.62,1.26,0.0,60103,60612,17643,18152,0,0,0,60227,0,11072,77,1733,1656,24387,9321,1104,9232,9031,29,1048,34710,0,35758,66.66666666666667,15.0,15.0,AREA 0,9,30,1,153.6,153.18,0.35,0.05,sky130_fd_sc_ls,4,4
+35,des3,des3,config_TEST_SW_LS,flow_completed,6h46m57s,5h7m57s,70663.75259706432,3.5588260000000003,14132.750519412864,25,1909.71,50296,0,0,0,0,0,0,0,87,0,0,-1,2873899,436785,-20.18,-20.18,-13.24,-17.31,-12.6,-31789.96,-31789.96,-12686.0,-12686.0,-12494.05,2271976339,0.0,24.53,22.25,1.8,0.34,0.0,50239,50530,8959,9250,0,0,0,50296,1344,8808,144,1344,38112,5376,768,2416,5376,1536,14,1120,39615,0,40735,49.52947003467064,20.189999999999998,7.59,AREA 0,7,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_ls,4,4
+36,point_add,point_add,config_TEST_SW_LS,flow_completed,6h56m50s,5h4m40s,77397.15332780207,2.613016,19349.288331950516,35,1758.94,50560,0,0,0,0,0,0,0,71,0,0,-1,4402686,503550,-35.84,-35.84,-5.03,-8.44,-5.13,-79510.91,-79510.91,-1349.47,-1349.47,-1244.5,3450464157,0.0,46.8,42.88,15.24,13.27,0.36,50182,51340,6131,7289,0,0,0,50560,857,1149,640,3041,18519,579,3,6546,10796,12400,17,958,28856,0,29814,66.09385327164574,15.129999999999999,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.15,sky130_fd_sc_ls,4,4
+37,point_scalar_mult,point_scalar_mult,config_TEST_SW_LS,flow_completed,7h26m6s,5h30m30s,75526.5138490796,2.925754,18881.6284622699,34,1850.97,55243,0,0,0,0,0,0,0,87,0,0,-1,4501528,529651,-35.84,-35.84,-6.3,-11.37,-5.83,-87583.84,-87583.84,-3126.92,-3126.92,-5495.51,3689955299,0.0,41.8,37.92,7.67,0.94,0.0,54863,55785,7456,8378,0,0,0,55243,253,1149,788,3213,18054,582,0,8651,12661,13726,17,1014,32317,0,33331,63.171193935565384,15.83,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.05,sky130_fd_sc_ls,4,4
+38,jpeg_encoder,jpeg_encoder,config_TEST_SW_LS,flow_failed,7h38m18s,6h7m40s,76947.72442822355,3.7888059999999997,15389.544885644711,26,2123.56,58308,0,0,0,0,0,0,-1,-1,14,-1,-1,5088886,574432,-26.88,-26.88,0.0,-4.41,-1.4,-44009.05,-44009.05,0.0,0.0,-18.38,4191127761,0.0,33.86,30.24,5.75,1.72,0.0,58293,58329,4381,4417,0,0,0,58308,3839,1,2296,5188,7634,15175,5614,4439,6723,6061,37,1156,42046,0,43202,58.20721769499418,17.18,15.78,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ls,4,4
+39,y_dct,y_dct,config_TEST_SW_LS,flow_completed,8h53m19s,5h14m56s,63827.69530585051,6.132996,12765.539061170102,26,3080.96,78291,0,0,0,0,0,0,0,122,0,0,-1,6660107,637586,0.0,0.0,0.0,-2.67,-1.45,0.0,0.0,0.0,0.0,-20.97,5951174263,0.0,29.49,26.17,1.61,0.34,0.0,100762,101409,4703,5350,0,0,0,78291,3238,72,1227,3318,3941,3531,161,10172,31779,27586,20,1476,68812,0,70288,45.51661356395084,21.97,20.52,AREA 0,5,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ls,4,4
+40,151,riscv_top,config_TEST_SW_LS,flow_completed,10h1m22s,6h27m49s,51277.5387230152,5.7048760000000005,12819.3846807538,33,3112.68,73133,0,0,0,0,0,0,0,106,0,0,-1,6393411,745926,-278.01,-278.01,0.0,-5.79,0.0,-4530327.0,-4530327.0,0.0,0.0,0.0,4681113643,0.0,29.84,26.07,1.42,1.94,0.0,72936,73271,23324,23659,0,0,0,73133,109,2216,286,1088,3839,426,120,20245,24812,25565,22,1422,63807,0,65229,20.0,50.0,50.0,DELAY 1,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ls,4,4
+41,sound,sound,config_TEST_SW_LS,flow_completed,23h56m11s,9h36m21s,70458.09529546964,11.387194000000001,17614.52382386741,34,6853.71,200580,0,0,0,0,0,0,0,129,0,0,-1,12114822,2076534,-27.97,-27.97,0.0,0.0,0.0,-343476.47,-343476.47,0.0,0.0,0.0,8414083629,0.0,30.34,23.92,0.69,0.05,0.0,200545,200662,200545,200662,0,0,0,200580,11691,1896,10906,21307,46996,25037,13741,15776,1102,1650,30,2014,128133,0,130147,7.308338814587444,136.83,136.83,AREA 0,9,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ls,4,4
diff --git a/openlane/regression_results/benchmark_results/SW_MS.csv b/openlane/regression_results/benchmark_results/SW_MS.csv
new file mode 100644
index 0000000..bbbf034
--- /dev/null
+++ b/openlane/regression_results/benchmark_results/SW_MS.csv
@@ -0,0 +1,43 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,digital_pll_sky130_fd_sc_hd,digital_pll,config_TEST_SW_MS,flow_failed,0h0m18s,-1,2040816.3265306123,-1e-06,1000000.0,-1,-1.0,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,-1,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,59.52380952380952,16.8,15.8,AREA 0,6,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_ms,4,4
+1,inverter,inverter,config_TEST_SW_MS,flow_completed,0h3m34s,0h3m9s,1089.3246187363834,0.001836,544.6623093681917,5,380.31,1,0,0,0,0,0,0,0,0,0,-1,-1,75,13,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.13,0.97,0.0,0.0,0.0,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,1,1,1,16,5,0,21,100.0,10.0,10.0,AREA 0,5,50,1,153.6,153.18,0.75,0.0,sky130_fd_sc_ms,4,4
+2,manual_macro_placement_test,manual_macro_placement_test,config_TEST_SW_MS,flow_completed,0h4m20s,0h3m23s,56.009230321156934,0.102024,19.603230612404925,1,419.59,2,0,0,0,0,0,0,0,1,0,-1,-1,20071,494,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,3.64,4.62,3.38,4.6,0.05,10,72,10,72,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,180,563,0,743,10.0,100.0,100.0,AREA 0,5,35,1,30.0,153.18,0.35,0.0,sky130_fd_sc_ms,0,0
+3,zipdiv,zipdiv,config_ms_first_rerun,flow_completed,0h5m50s,0h5m16s,63539.12951392566,0.048563999999999996,22238.69532987398,45,532.21,1080,0,0,0,0,0,0,0,0,0,-1,-1,49792,10082,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,36935915,0.0,33.18,29.54,1.45,0.37,1.12,1052,1148,118,214,0,0,0,1080,46,0,3,43,165,146,14,241,273,273,31,120,463,0,583,52.38344683080147,19.09,19.09,AREA 0,6,35,1,153.6,153.18,0.4,0.15,sky130_fd_sc_ms,4,4
+4,xtea,xtea,config_ms_first_rerun,flow_completed,0h7m11s,0h5m47s,70333.42932188454,0.098226,24616.700262659586,46,555.43,2418,0,0,0,0,0,0,0,0,0,-1,-1,148457,23757,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,116170275,0.0,46.95,43.85,2.94,0.8,0.0,2362,2613,123,374,0,0,0,2418,16,0,54,226,390,436,121,174,468,615,28,176,988,0,1164,38.417210910487896,26.03,26.03,AREA 0,6,35,1,153.6,153.18,0.4,0.15,sky130_fd_sc_ms,4,4
+5,s44,lut_s44,config_TEST_SW_MS,flow_completed,0h7m38s,0h6m55s,44683.98747005712,0.043416,2234.1993735028564,7,415.57,97,0,0,0,0,0,0,0,0,0,-1,-1,6635,1047,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5279922,0.0,3.92,3.65,0.0,0.0,0.0,94,114,38,58,0,0,0,97,0,0,0,0,0,0,0,32,41,32,4,114,411,0,525,33.333333333333336,30.0,30.0,AREA 0,5,5,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ms,4,4
+6,usb,usb,config_TEST_SW_MS,flow_completed,0h10m42s,0h9m20s,50657.703839829774,0.041356,20263.08153593191,46,474.92,838,0,0,0,0,0,0,0,0,0,-1,-1,31480,7252,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,19648073,0.0,21.43,18.15,0.0,0.0,0.0,837,861,200,224,0,0,0,838,22,8,43,40,206,49,6,176,242,251,12,110,370,0,480,79.6812749003984,12.55,12.55,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_ms,4,4
+7,usbf_device,usbf_device,config_ms_first_rerun,flow_completed,0h32m4s,0h21m30s,63137.71013794133,0.609897,25255.084055176532,48,864.05,15403,0,0,0,0,0,0,0,4,0,-1,-1,942002,146576,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,655577528,0.0,39.61,36.82,2.71,0.99,0.0,15378,15524,3775,3921,0,0,0,15403,675,0,362,157,4505,280,61,3692,4004,4615,14,456,6553,0,7009,68.4931506849315,14.6,14.6,AREA 0,6,40,1,153.6,153.18,0.45,0.0,sky130_fd_sc_ms,4,4
+8,picorv32a,picorv32a,config_ms_first_rerun,flow_completed,0h29m7s,0h17m3s,71042.05500892697,0.678096,21312.616502678087,41,865.31,14452,0,0,0,0,0,0,0,13,0,-1,-1,1059842,144473,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,837264100,0.0,46.02,40.22,8.81,1.47,0.0,14172,14554,1565,1947,0,0,0,14452,1159,227,896,560,2391,2462,615,1664,2132,2900,134,482,7288,0,7770,40.43671653861706,24.73,24.73,AREA 0,6,30,1,153.6,153.18,0.35,0.1,sky130_fd_sc_ms,4,4
+9,cic_decimator,cic_decimator,config_TEST_SW_MS,flow_completed,0h11m16s,0h9m43s,62959.818902093946,0.031806,25183.92756083758,49,492.05,801,0,0,0,0,0,0,0,0,0,-1,-1,31216,7115,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,20078090,0.0,27.47,23.58,0.62,0.0,0.0,790,823,119,152,0,0,0,801,15,0,21,51,90,92,51,220,131,112,16,94,269,0,363,100.0,10.0,10.0,AREA 0,6,40,1,15.0,15.0,0.45,0.0,sky130_fd_sc_ms,4,4
+10,spm,spm,config_TEST_SW_MS,flow_completed,0h11m26s,0h10m46s,42597.40259740259,0.01375,20872.727272727272,54,474.69,287,0,0,0,0,0,0,0,0,0,-1,-1,8827,2179,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,5805510,0.0,17.17,16.28,0.0,0.0,0.0,291,322,39,70,0,0,0,287,32,0,31,31,1,63,31,0,97,128,4,58,108,0,166,100.0,10.0,10.0,AREA 0,5,49,1,153.6,153.18,0.54,0.0,sky130_fd_sc_ms,4,4
+11,usb_cdc_core,usb_cdc_core,config_TEST_SW_MS,flow_completed,0h23m39s,0h18m14s,63689.781770637186,0.072574,28660.401796786733,52,539.7,2080,0,0,0,0,0,0,0,1,0,-1,-1,79946,16384,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,52392919,0.0,31.18,25.45,0.36,0.03,0.0,2076,2107,314,345,0,0,0,2080,99,0,110,89,676,130,41,252,365,683,19,150,693,0,843,64.1025641025641,15.6,15.6,AREA 0,6,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ms,4,4
+12,wbqspiflash,wbqspiflash,config_TEST_SW_MS,flow_completed,0h26m2s,0h17m1s,69700.39477779416,0.12209400000000001,20910.118433338248,41,562.64,2553,0,0,0,0,0,0,0,0,0,-1,-1,148278,25066,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,106595018,0.0,34.15,27.83,0.99,0.0,0.0,2526,2614,264,352,0,0,0,2553,55,1,147,155,796,79,6,376,656,885,20,198,1212,0,1410,53.022269353128316,18.86,18.86,AREA 0,6,30,1,153.6,153.18,0.35,0.0,sky130_fd_sc_ms,4,4
+13,APU,APU,config_TEST_SW_MS,flow_completed,0h28m2s,0h17m23s,64099.112346379596,0.137956,22434.689321232858,45,589.04,3095,0,0,0,0,0,0,0,0,0,-1,-1,148444,29191,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,95159893,0.0,30.15,25.07,0.39,0.0,0.0,3068,3127,380,439,0,0,0,3095,86,28,103,170,344,251,52,709,683,867,26,212,1404,0,1616,58.8235294117647,17.0,17.0,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ms,4,4
+14,synth_ram,synth_ram,config_TEST_SW_MS,flow_completed,0h56m27s,0h28m28s,51091.51479521851,0.2835,22991.18165784833,56,675.84,6518,0,0,0,0,0,0,0,3,0,-1,-1,461671,70347,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,250011549,0.0,46.6,35.65,1.75,0.47,0.0,6492,6578,2054,2140,0,0,0,6518,8,0,2,1,81,0,0,2080,2155,2080,8,308,2964,0,3272,20.0,50.0,50.0,AREA 0,5,45,1,153.6,153.18,0.5,0.0,sky130_fd_sc_ms,4,4
+15,ocs_blitter,ocs_blitter,config_TEST_SW_MS,flow_completed,1h10m5s,0h38m25s,65731.12250266835,0.304096,23005.89287593392,50,696.52,6996,0,0,0,0,0,0,0,10,0,-1,-1,461217,74948,-25.46,-25.46,-0.95,-3.35,-0.62,-4017.66,-4017.66,-1.49,-1.49,-0.83,275586619,0.0,41.77,34.98,1.94,0.18,0.0,6944,7088,439,583,0,0,0,6996,164,0,189,595,1116,745,127,471,962,1734,27,318,3218,0,3536,53.13496280552604,18.82,18.2,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ms,4,4
+16,md5,md5,config_TEST_SW_MS,flow_completed,1h13m59s,0h47m46s,60813.11632940067,0.268786,21284.590715290233,48,679.65,5721,0,0,0,0,0,0,0,2,0,-1,-1,422229,60549,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,297801918,0.0,42.27,33.77,4.36,2.41,1.04,5599,5853,1175,1429,0,0,0,5721,80,0,137,240,1477,396,213,650,1208,1399,38,300,2812,0,3112,26.990553306342782,37.05,37.05,AREA 0,6,35,1,153.6,153.18,0.4,0.0,sky130_fd_sc_ms,4,4
+17,PPU,PPU,config_TEST_SW_MS,flow_completed,1h50m33s,0h41m44s,53353.710461596456,0.880726,10670.742092319291,29,781.84,9398,0,0,0,0,0,0,0,15,0,-1,-1,757554,105130,-14.41,-14.41,0.0,0.0,0.0,-3097.04,-3097.04,0.0,0.0,0.0,490897042,0.0,27.13,20.61,0.27,0.0,0.0,9339,9422,2898,2981,0,0,0,9398,53,8,55,72,460,113,21,2942,3193,3308,15,552,9589,0,10141,55.55555555555556,18.0,18.0,AREA 0,8,20,1,153.6,153.18,0.25,0.05,sky130_fd_sc_ms,4,4
+18,151,riscv_top,config_ms_first_rerun,flow_completed,5h55m7s,1h58m5s,51306.30314103015,7.1155,10261.26062820603,27,3516.29,73014,0,0,0,0,0,0,0,104,0,-1,-1,6946346,745081,-218.52,-218.52,0.0,-4.36,0.0,-3584012.0,-3584012.0,0.0,0.0,0.0,5144219293,0.0,26.64,22.33,2.16,0.25,0.0,72817,73152,23324,23659,0,0,0,73014,109,2216,286,1088,3839,426,120,20245,24812,25565,22,1590,79692,0,81282,20.0,50.0,50.0,DELAY 1,5,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ms,4,4
+19,BM64,BM64,config_TEST_SW_MS,flow_completed,2h12m29s,0h58m46s,66654.02009860548,0.706384,11997.723617748987,28,772.67,8475,0,0,0,0,0,0,0,15,0,-1,-1,1118414,99877,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,992708780,0.0,39.57,38.65,3.38,0.64,0.0,7969,8990,785,1806,0,0,0,8475,26,0,12,341,2174,989,307,2573,1801,1293,33,492,7684,0,8176,50.0,20.0,20.0,AREA 0,6,18,1,153.6,153.18,0.23,0.0,sky130_fd_sc_ms,4,4
+20,genericfir,genericfir,config_TEST_SW_MS,flow_completed,2h15m51s,1h41m26s,49309.74167940392,0.42700600000000005,22189.383755731767,50,716.95,9475,0,0,0,0,0,0,0,1,0,-1,-1,404944,86906,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,253238877,0.0,30.39,25.74,0.17,0.04,0.0,12499,12551,6835,6887,0,0,0,9475,0,0,2001,3390,4008,3000,750,7560,3782,3780,6,380,4512,0,4892,100.0,10.0,10.0,AREA 0,7,45,1,153.6,153.18,0.5,0.1,sky130_fd_sc_ms,4,4
+21,y_huff,y_huff,config_TEST_SW_MS,flow_completed,2h42m30s,1h35m37s,60858.34695106217,0.58135,18257.50408531865,41,812.84,10614,0,0,0,0,0,0,0,15,0,-1,-1,1102653,119310,-3.05,-3.05,-0.26,-2.15,0.0,-4110.01,-4110.01,-4.11,-4.11,0.0,821915534,0.0,56.47,53.66,9.92,3.26,0.0,10646,11321,2383,3058,0,0,0,10614,237,0,146,384,1310,575,87,4679,4830,3153,16,446,6298,0,6744,88.1057268722467,11.35,11.35,AREA 0,6,30,1,153.6,153.18,0.35,0.15,sky130_fd_sc_ms,4,4
+22,des,des,config_TEST_SW_MS,flow_completed,2h50m6s,1h53m20s,73760.61336606245,0.618526,25816.214678121854,41,847.07,15968,0,0,0,0,0,0,0,16,0,-1,-1,775009,134488,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,625707695,0.0,38.63,32.8,4.37,0.57,0.0,15909,16090,1957,2138,0,0,0,15968,432,1984,48,448,12688,1792,256,768,1792,512,13,460,6610,0,7070,50.0,20.0,20.0,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_ms,4,4
+23,chacha,chacha,config_TEST_SW_MS,flow_completed,3h32m32s,1h58m52s,73441.85612208147,0.899596,18360.46403052037,37,960.43,16517,0,0,0,0,0,0,0,12,0,-1,-1,1593367,177597,-16.31,-16.31,0.0,-1.93,0.0,-5744.67,-5744.67,0.0,0.0,0.0,1301387439,0.0,48.09,43.66,15.45,7.03,0.0,16492,16561,2389,2458,0,0,0,16517,605,5,604,825,810,2011,971,3036,3035,3673,57,558,9833,0,10391,38.446751249519416,26.01,26.01,AREA 0,6,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_ms,4,4
+24,sha3,sha3,config_TEST_SW_MS,flow_completed,3h45m37s,2h48m38s,65164.22261072658,0.628785,22807.4779137543,46,879.33,14341,0,0,0,0,0,0,0,6,0,-1,-1,996805,147774,-3.81,-3.81,-0.83,-2.29,-1.05,-2173.91,-2173.91,-6.41,-6.41,-7.99,630411467,0.0,45.72,40.28,9.18,3.53,0.0,14316,14385,3031,3100,0,0,0,14341,911,0,893,238,878,848,435,3088,3162,3709,23,464,6784,0,7248,72.67441860465115,13.760000000000002,12.71,AREA 0,6,35,1,153.6,153.18,0.4,0.1,sky130_fd_sc_ms,4,4
+25,ldpcenc,ldpcenc,config_TEST_SW_MS,flow_completed,3h48m18s,1h59m23s,65395.085241789384,1.07635,16348.771310447346,39,1018.78,17597,0,0,0,0,0,0,0,37,0,-1,-1,1823259,206440,-43.49,-43.49,0.0,-1.34,0.0,-31647.8,-31647.8,0.0,0.0,0.0,1479133895,0.0,41.56,38.49,8.0,1.48,0.0,17578,17633,1527,1582,0,0,0,17597,103,94,990,79,2098,1958,84,1265,2487,2565,13,610,11664,0,12274,77.51937984496124,12.9,12.9,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ms,4,4
+26,blabla,blabla,config_TEST_SW_MS,flow_completed,4h2m49s,1h29m48s,77823.52137431077,1.268946,10117.0577786604,23,950.33,12838,0,0,0,0,0,0,0,25,0,-1,-1,2386137,154714,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2190273557,0.0,49.17,50.56,14.26,4.56,0.0,12337,13744,1105,2512,0,0,0,12838,654,5,575,813,507,2076,906,2190,2894,2059,57,664,13859,0,14523,15.384615384615385,65.0,65.0,AREA 0,5,13,1,153.6,153.18,0.18,0.1,sky130_fd_sc_ms,4,4
+27,aes_cipher,aes_cipher,config_TEST_SW_MS,flow_completed,4h7m23s,3h3m21s,87607.93116348673,0.66825,21901.982790871683,37,923.2,14636,0,0,0,0,0,0,0,7,0,-1,-1,1283599,167888,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1051940191,0.0,47.16,42.81,8.83,3.0,0.0,14516,14897,411,792,0,0,0,14636,461,386,73,357,18246,848,301,148,659,660,18,478,7228,0,7706,99.10802775024777,10.09,10.09,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ms,4,4
+28,salsa20,salsa20,config_TEST_SW_MS,flow_completed,4h32m49s,2h43m1s,66309.70544950872,1.478592,13261.941089901746,29,1087.98,19609,0,0,0,0,0,0,0,41,0,-1,-1,2226775,218972,-2.89,-2.89,0.0,0.0,0.0,-121.11,-121.11,0.0,0.0,0.0,1893451890,0.0,38.72,32.56,7.38,2.29,0.0,19584,19653,4073,4142,0,0,0,19609,518,5,615,755,1608,2268,769,7341,5004,4742,60,718,16241,0,16959,27.225701061802344,36.73,36.73,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ms,4,4
+29,aes,aes,config_TEST_SW_MS,flow_completed,4h42m9s,2h56m26s,63387.451214559114,1.487124,12677.490242911823,30,1112.72,18853,0,0,0,0,0,0,0,14,0,-1,-1,1795038,223448,-4.22,-4.22,-1.13,-5.37,0.0,-11535.69,-11535.69,-49.18,-49.18,0.0,1313885597,0.0,33.33,27.31,1.82,0.23,0.05,18828,18897,3136,3205,0,0,0,18853,219,0,88,346,8956,2179,691,3103,4034,4222,18,720,16288,0,17008,38.610038610038615,25.9,25.9,AREA 0,8,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ms,4,4
+30,sha512,sha512,config_TEST_SW_MS,flow_completed,4h45m34s,2h17m47s,63368.029139714235,1.511614,15842.007284928559,37,1223.31,23947,0,0,0,0,0,0,0,21,0,-1,-1,2365626,284200,-62.23,-62.23,0.0,0.0,0.0,-70592.38,-70592.38,0.0,0.0,0.0,1734123324,0.0,42.52,44.03,3.67,7.71,0.0,23922,23991,5703,5772,0,0,0,23947,624,0,429,1853,4118,1682,1301,3667,6372,7289,44,726,16603,0,17329,25.464731347084285,39.27,39.27,AREA 0,10,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_ms,4,4
+31,aes_core,aes_core,config_TEST_SW_MS,flow_completed,4h52m1s,3h26m32s,66708.18980310406,1.101394,16677.047450776015,38,1085.06,18368,0,0,0,0,0,0,0,28,0,-1,-1,2043650,231553,-3.26,-3.26,0.0,-1.36,0.0,-7218.86,-7218.86,0.0,0.0,0.0,1614448438,0.0,47.8,40.17,9.63,1.47,0.0,18249,18758,2490,2999,0,0,0,18368,303,0,175,343,8961,2035,834,2717,3710,3696,19,618,11971,0,12589,46.992481203007515,21.28,21.28,AREA 0,6,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ms,4,4
+32,aes128,aes128,config_TEST_SW_MS,flow_completed,5h9m38s,2h36m15s,68253.7385114376,2.431984,17063.4346278594,31,1411.49,41498,0,0,0,0,0,0,0,58,0,-1,-1,2604503,334548,0.0,0.0,0.0,-0.08,0.0,0.0,0.0,0.0,0.0,0.0,2291469759,0.0,34.97,26.44,5.12,0.03,0.0,41374,41755,10452,10833,0,0,0,41498,0,5568,65,1223,1198,17800,6545,800,6496,6736,29,924,26908,0,27832,87.48906386701663,11.43,11.43,AREA 0,7,25,1,153.6,153.18,0.3,0.1,sky130_fd_sc_ms,4,4
+33,aes192,aes192,config_TEST_SW_MS,flow_completed,5h55m41s,3h21m32s,64932.29093955046,3.5815,12986.458187910093,26,1743.54,46511,0,0,0,0,0,0,0,51,0,-1,-1,3416413,380386,0.0,0.0,0.0,-0.09,0.0,0.0,0.0,0.0,0.0,0.0,3044031058,0.0,30.64,24.34,4.15,0.18,0.0,46387,46832,13036,13481,0,0,0,46511,14,7968,55,1831,1158,19939,7390,684,7660,6689,31,1124,39758,0,40882,80.84074373484236,12.37,12.37,AREA 0,9,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_ms,4,4
+34,aes256,aes256,config_TEST_SW_MS,flow_completed,6h14m22s,3h46m40s,64481.40577537214,3.113404,19344.42173261164,36,1773.87,60227,0,0,0,0,0,0,0,83,0,-1,-1,4025054,480295,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,3532346146,0.0,32.28,36.12,1.15,4.37,0.0,60103,60612,17643,18152,0,0,0,60227,0,11072,77,1733,1656,24387,9321,1104,9232,9031,29,1048,34710,0,35758,66.66666666666667,15.0,15.0,AREA 0,9,30,1,153.6,153.18,0.35,0.05,sky130_fd_sc_ms,4,4
+35,point_add,point_add,config_TEST_SW_MS,flow_completed,6h40m46s,4h47m34s,77397.15332780207,2.613016,19349.288331950516,35,1727.14,50560,0,0,0,0,0,0,0,43,0,-1,-1,4442831,493596,-26.98,-26.98,-1.02,-2.87,-0.35,-60175.49,-60175.49,-5.27,-5.27,-0.53,3444457827,0.0,48.35,42.02,13.85,16.08,0.22,50182,51340,6131,7289,0,0,0,50560,857,1149,640,3041,18519,579,3,6546,10796,12400,17,958,28856,0,29814,96.61835748792271,10.35,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.15,sky130_fd_sc_ms,4,4
+36,point_scalar_mult,point_scalar_mult,config_TEST_SW_MS,flow_completed,6h49m21s,4h45m49s,75526.5138490796,2.925754,18881.6284622699,35,1814.84,55243,0,0,0,0,0,0,0,66,0,-1,-1,4515721,523586,-26.98,-26.98,-2.52,-5.68,-1.76,-64180.44,-64180.44,-298.98,-298.98,-171.14,3739646447,0.0,42.02,37.94,7.78,0.95,0.0,54863,55785,7456,8378,0,0,0,55243,253,1149,788,3213,18054,582,0,8651,12661,13726,17,1014,32317,0,33331,85.03401360544218,11.76,10.0,AREA 0,5,25,1,153.6,153.18,0.3,0.05,sky130_fd_sc_ms,4,4
+37,jpeg_encoder,jpeg_encoder,config_TEST_SW_MS,flow_completed,7h50m53s,5h35m28s,76947.72442822355,3.7888059999999997,15389.544885644711,26,1985.55,58308,0,0,0,0,0,0,0,91,19,-1,-1,5106939,573412,-19.99,-19.99,0.0,-0.61,0.0,-31249.91,-31249.91,0.0,0.0,0.0,4224431012,0.0,34.71,29.75,5.77,1.66,0.0,58293,58329,4381,4417,0,0,0,58308,3839,1,2296,5188,7634,15175,5614,4439,6723,6061,37,1156,42046,0,43202,63.37135614702155,15.78,15.78,AREA 0,6,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ms,4,4
+38,y_dct,y_dct,config_TEST_SW_MS,flow_completed,8h49m56s,4h59m8s,63827.69530585051,6.132996,12765.539061170102,27,3022.7,78291,0,0,0,0,0,0,0,85,0,-1,-1,6663424,635607,0.0,0.0,0.0,-0.06,0.0,0.0,0.0,0.0,0.0,0.0,5953132013,0.0,29.53,26.21,1.56,0.32,0.0,100762,101409,4703,5350,0,0,0,78291,3238,72,1227,3318,3941,3531,161,10172,31779,27586,20,1476,68812,0,70288,48.732943469785575,20.52,20.52,AREA 0,5,20,1,153.6,153.18,0.25,0.0,sky130_fd_sc_ms,4,4
+39,ldpc_decoder_802_3an,ldpc_decoder_802_3an,config_TEST_SW_MS,flow_failed,12h38m18s,-1,-961830000000.0,-1e-06,-96183000000.0,23,-1.0,96183,-1,-1,-1,-1,-1,-1,-1,-1,0,-1,-1,-1,-1,-49.11,-49.11,0.0,0.0,0.0,-100572.38,-100572.38,0.0,0.0,0.0,34191408588,-1.0,-1.0,-1.0,-1.0,-1.0,-1.0,94140,98234,2054,6148,0,0,0,96183,0,0,32,0,6519,19649,4544,2048,4098,6146,22,1998,125617,0,127615,12.987012987012987,77.0,77.0,DELAY 0,6,10,1,153.6,153.18,0.15,0.0,sky130_fd_sc_ms,4,4
+40,sound,sound,config_TEST_SW_MS,flow_completed,24h7m15s,9h10m48s,70464.76945944717,11.387194000000001,17616.192364861792,35,6386.77,200599,0,0,0,0,0,0,0,105,0,-1,-1,12019007,2071395,-1.65,-1.65,0.0,0.0,0.0,-20262.3,-20262.3,0.0,0.0,0.0,8273946298,0.0,30.1,23.76,0.65,0.03,0.0,200564,200681,200564,200681,0,0,0,200599,11691,1896,10906,21307,46996,25037,13741,15776,1102,1650,30,2014,128133,0,130147,7.308338814587444,136.83,136.83,AREA 0,9,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_ms,4,4
+41,des3,des3,config_TEST_SW_MS,flow_failed,45h47m6s,4h49m50s,70663.75259706432,3.5588260000000003,14132.750519412864,25,1798.6,50296,0,0,0,0,0,0,-1,-1,0,-1,-1,2860419,432922,-16.14,-16.14,-15.75,-20.83,-14.0,-25364.54,-25364.54,-11820.63,-11820.63,-9982.6,2274053744,0.0,24.27,21.81,2.1,1.01,0.03,50239,50530,8959,9250,0,0,0,50296,1344,8808,144,1344,38112,5376,768,2416,5376,1536,14,1120,39615,0,40735,46.317739694302915,21.59,7.59,AREA 0,7,20,1,153.6,153.18,0.25,0.1,sky130_fd_sc_ms,4,4
diff --git a/openlane/regression_results/datapoint_definitions.md b/openlane/regression_results/datapoint_definitions.md
new file mode 100644
index 0000000..27c1332
--- /dev/null
+++ b/openlane/regression_results/datapoint_definitions.md
@@ -0,0 +1,96 @@
+# Datapoint Definitions
+***NOTE:** The value `-1`, if not meaningful, indicates that the report/log from which the information is extracted wasn't found (the stage responsible for it was skipped or failed).
+
+## Default Printed Information Variables
+
+| Variable | Description |
+|---------------|-------------------------------------------------------|
+| `design` | The directory of the design |
+| `design_name` | The name of the top level module of the design |
+| `config` | The name of the configurations file of the design |
+| `flow_status` | The status of the flow at the end of the run. Extracted from total_runtime.txt |
+| `total_runtime` | The total runtime of running the process on the design. Extracted from total_runtime.txt |
+| `routed_runtime` | The runtime of running the process up to (including) detailed routing on the design. Extracted from routed_runtime.txt |
+| `DIEAREA_mm^2` | The diearea in mm<sup>2</sup> as reported from the def file. |
+| `CellPer_mm^2` | The number of cells in the design as reported by yosys divided by the diearea in mm<sup>2</sup>. |
+| `(Cell/mm^2)/Core_Util` | The number of cells in the design as reported by yosys divided by the diearea in mm<sup>2</sup>, all divided by the FP_CORE_UTIL configuration parameter. |
+| `OpenDP_Util` | The core utilization of the design. Extracted from openDP logs. |
+| `Peak_Memory_Usage_MB` | The peak memory usage of Tritonroute during optimization iterations. Extracted from tritonRoute logs. |
+| `cell_count` | The number of cells in the design. Extracted from yosys logs. |
+| `tritonRoute_Violations` | The total number of violations from running TritonRoute. Extracted from tritonRoute logs. |
+| `Short_Violations` | The total number of shorts violations from running TritonRoute. Extracted from tritonRoute drc. |
+| `MetSpc_violations` | The total number of MetSpc violations from running TritonRoute. Extracted from tritonRoute drc. |
+| `OffGrid_violations` | The total number of off-grid violations from running TritonRoute. Extracted from tritonRoute drc. |
+| `MinHole_violations` | The total number of MinHole violations from running TritonRoute. Extracted from tritonRoute drc. |
+| `Other_violations` | The total number of other types of violations from running TritonRoute. Extracted from tritonRoute drc. |
+| `Magic_violations` | The total number of magic drc violations in the design. Extracted from Magic drc. |
+| `antenna_violations` | The total number of antenna violations in the design. Extracted from Magic antenna check or OpenROAD ARC. |
+| `lvs_total_errors` | The total number of mismatches and differences between the final layout and the netlist of the design. Extracted from Netgen LVS report. |
+| `cvc_total_errors` | The total number of electric errors detected by CVC. Extracted from CVC report. |
+| `klayout_violations` | The total number of klayout drc violations in the design. Extracted from klayout drc report ran on the magic generated GDS-II. |
+| `wire_length` | The total wire length in the design. Extracted from tritonRoute logs. |
+| `vias` | The number of vias in the final design. Extracted from tritonRoute logs. |
+| `wns` | Worst Negative Slack. Reported after Synthesis. Extracted from OpenSTA. |
+| `pl_wns` | Worst Negative Slack. Reported after global placement and before optimizations using estimate parasitics. Extracted from RePlAce/OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `opt_wns` | Worst Negative Slack. Extracted from OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `fastroute_tns` | Worst Negative Slack. Reported after global routing using estimate parasitics. Extracted from FastRoute/OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `spef_wns` | Worst Negative Slack. Reported after routing and spef extraction. Extracted from OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `tns` | Total Negative Slack. Reported after Synthesis. Extracted from OpenSTA. |
+| `pl_tns` | Total Negative Slack. Reported after global placement and before optimizations using estimate parasitics. Extracted from RePlAce/OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `opt_tns` | Total Negative Slack. Reported after OpenPhySyn optimizations. Extracted from OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `fastroute_tns` | Total Negative Slack. Reported after global routing using estimate parasitics. Extracted from FastRoute/OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `spef_tns` | Total Negative Slack. Reported after routing and spef extraction. Extracted from OpenSTA. If the report wasn't found, the value from the previous STA report is used. |
+| `HPWL` | Final value for the half-perimeter wire length. Extracted from RePlace logs. |
+| `routing_layer1_pct` | The percentage usage of routing resources on layer 1 in global routing. Extracted from fastroute log. |
+| `routing_layer2_pct` | The percentage usage of routing resources on layer 2 in global routing. Extracted from fastroute log. |
+| `routing_layer3_pct` | The percentage usage of routing resources on layer 3 in global routing. Extracted from fastroute log. |
+| `routing_layer4_pct` | The percentage usage of routing resources on layer 4 in global routing. Extracted from fastroute log. |
+| `routing_layer5_pct` | The percentage usage of routing resources on layer 5 in global routing. Extracted from fastroute log. |
+| `routing_layer6_pct` | The percentage usage of routing resources on layer 6 in global routing. Extracted from fastroute log. |
+| `wires_count` | The number of wires in the design. Extracted from yosys logs. |
+| `wire_bits` | The number of wire bits in the design. Extracted from yosys logs. |
+| `public_wires_count` | The number of public wires in the design. Extracted from yosys logs. |
+| `public_wire_bits` | The number of public wire bits in the design. Extracted from yosys logs. |
+| `memories_count` | The number of memories in the design. Extracted from yosys logs. |
+| `memory_bits` | The number of memory bits in the design. Extracted from yosys logs. |
+| `cells_pre_abc` | The number of cells before ABC. Extracted from yosys logs. |
+| `AND` | The number of AND gates in the design. Extracted from yosys logs. |
+| `DFF` | The number of flip flops in the design. Extracted from yosys logs. |
+| `NAND` | The number of NAND gates in the design. Extracted from yosys logs. |
+| `NOR` | The number of NOR gates in the design. Extracted from yosys logs. |
+| `OR` | The number of OR gates in the design. Extracted from yosys logs. |
+| `XOR` | The number of XOR gates in the design. Extracted from yosys logs. |
+| `XNOR` | The number of XNOR gates in the design. Extracted from yosys logs. |
+| `MUX` | The number of multiplexers in the design. Extracted from yosys logs. |
+| `inputs` | The number of inputs in the design. Extracted from yosys logs. |
+| `outputs` | The number of outputs in the design. Extracted from yosys logs. |
+| `level` | The number of levels in the final design. Extracted from yosys logs. |
+| `EndCaps` | The number of endcaps in the final design. Extracted from tapcell log. |
+| `TapCells` | The number of tapcells in the final design. Extracted from tapcell log. |
+| `Diodes` | The number of diodes in the final design. Extracted from diode logs or Fastroute log based on the used diode insertion strategy. |
+| `Total_Physical_Cells` | The sum of endcaps, tapcells, and diodes in the final design. |
+| `suggested_clock_frequency` | The suggested clock frequency to be used with the design. Calculated based on the value of `spef_wns`, and reported in `MHz`. |
+| `suggested_clock_period` | TThe suggested clock period to be used with the design. Calculated based on the value of `spef_wns`, and reported in `ns`. |
+
+
+## Default Printed Configuration Variables
+
+| Variable | Description |
+|---------------|-------------------------------------------------------|
+| `CLOCK_PERIOD` | The clock period for the design in ns |
+| `SYNTH_STRATEGY` | Strategies for abc logic synthesis and technology mapping <br> Possible values are "DELAY|AREA 0-3|0-2"; the first part refers to the optimization target of the synthesis strategy (area vs. delay) and the second one is an index. <br> (Default: `AREA 0`)|
+| `SYNTH_MAX_FANOUT` | The max load that the output ports can drive. <br> (Default: `5` cells) |
+| `FP_CORE_UTIL` | The core utilization percentage. <br> (Default: `50` percent)|
+| `FP_ASPECT_RATIO` | The core's aspect ratio (height / width). <br> (Default: `1`)|
+| `FP_PDN_VPITCH` | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
+| `FP_PDN_HPITCH` | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
+| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `0.55`)|
+| `GLB_RT_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. <br> 1 = most reduction, 0 = least reduction <br> (Default: `0.2`)|
+| `STD_CELL_LIBRARY` | Specifies the standard cell library used. <br> (Default: `sky130_fd_sc_hd` )|
+| `CELL_PAD` | Cell padding; increases the width of cells. <br> (Default: `2` microns -- 2 sites)|
+
+
+
+## Optional variables
+
+These variables are optional that can be specified in the configuration parameters file. Please refere to this [file](../configuration/README.md) for the full list of configurations.
diff --git a/openlane/requirements.txt b/openlane/requirements.txt
new file mode 100644
index 0000000..f8faac9
--- /dev/null
+++ b/openlane/requirements.txt
@@ -0,0 +1,2 @@
+-r ./dependencies/python/precompile_time.txt
+-r ./dependencies/python/run_time.txt
\ No newline at end of file
diff --git a/openlane/requirements_dev.txt b/openlane/requirements_dev.txt
new file mode 100644
index 0000000..13504bc
--- /dev/null
+++ b/openlane/requirements_dev.txt
@@ -0,0 +1,4 @@
+-r ./dependencies/requirements_lint.txt
+-r ./dependencies/python/precompile_time.txt
+-r ./dependencies/python/compile_time.txt
+-r ./requirements.txt
diff --git a/openlane/requirements_lint.txt b/openlane/requirements_lint.txt
new file mode 100644
index 0000000..d42acbe
--- /dev/null
+++ b/openlane/requirements_lint.txt
@@ -0,0 +1,2 @@
+black~=22.3.0
+flake8~=4.0.1
\ No newline at end of file
diff --git a/openlane/run_designs.py b/openlane/run_designs.py
new file mode 100755
index 0000000..43cb869
--- /dev/null
+++ b/openlane/run_designs.py
@@ -0,0 +1,433 @@
+#!/usr/bin/env python3
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import click
+import queue
+import shutil
+import logging
+import datetime
+import threading
+import subprocess
+
+from scripts.report.report import Report
+from scripts.config.config import ConfigHandler
+import scripts.utils.utils as utils
+
+
+@click.command()
+@click.option("-c", "--config_tag", default="config", help="Configuration file")
+@click.option("-r", "--regression", default=None, help="Regression file")
+@click.option("-t", "--tag", default="regression", help="Tag for the log file")
+@click.option(
+ "-j", "--threads", default=1, type=int, help="Number of designs in parallel"
+)
+@click.option(
+ "-p",
+ "--configuration_parameters",
+ default=None,
+ help="File containing configuration parameters to append to report: You can also put 'all' to report all possible configurations",
+)
+@click.option(
+ "-e",
+ "--excluded_designs",
+ default="",
+ help="Exclude the following comma,delimited,designs from the run",
+)
+@click.option(
+ "-b", "--benchmark", default=None, help="Benchmark report file to compare with."
+)
+@click.option(
+ "-p",
+ "--print_rem",
+ default=0,
+ help="If provided with a number >0, a list of remaining designs is printed every <print_rem> seconds.",
+)
+@click.option(
+ "--enable_timestamp/--disable_timestamp",
+ default=True,
+ help="Enables or disables appending the timestamp to the file names and tags.",
+)
+@click.option(
+ "--append_configurations/--dont_append_configurations",
+ default=False,
+ help="Append configuration parameters provided to the existing default printed configurations",
+)
+@click.option(
+ "--delete/--retain",
+ default=False,
+ help="Delete the entire run directory upon completion, leaving only the final_report.txt file.",
+)
+@click.option(
+ "--show_output/--hide_output",
+ default=False,
+ help="Enables showing the output from flow invocations into stdout. Will be forced to be false if more than one design is specified.",
+)
+@click.argument("designs", nargs=-1)
+def cli(
+ config_tag,
+ regression,
+ tag,
+ threads,
+ configuration_parameters,
+ excluded_designs,
+ benchmark,
+ print_rem,
+ enable_timestamp,
+ append_configurations,
+ delete,
+ show_output,
+ designs,
+):
+ """
+ Run multiple designs in parallel, for testing or exploration.
+ """
+
+ designs = list(designs)
+ excluded_designs = excluded_designs.split(",")
+
+ for excluded_design in excluded_designs:
+ if excluded_design in designs:
+ designs.remove(excluded_design)
+
+ show_log_output = show_output and (len(designs) == 1) and (regression is None)
+
+ if print_rem is not None and not show_log_output:
+ if float(print_rem) > 0:
+ mutex = threading.Lock()
+ print_rem_time = float(print_rem)
+ else:
+ print_rem_time = None
+ else:
+ print_rem_time = None
+
+ if print_rem_time is not None:
+ rem_designs = dict.fromkeys(designs, 1)
+
+ num_workers = threads
+ config = config_tag
+
+ if regression is not None:
+ regressionConfigurationsList = []
+ regressionFileOpener = open(regression, "r")
+ regressionFileContent = regressionFileOpener.read().split()
+ regressionFileOpener.close()
+ for k in regressionFileContent:
+ if k.find("=") == -1:
+ continue
+
+ if k.find("extra") != -1:
+ break
+ else:
+ regressionConfigurationsList.append(k.split("=")[0])
+ if len(regressionConfigurationsList):
+ ConfigHandler.update_configuration_values(
+ regressionConfigurationsList, True
+ )
+
+ if configuration_parameters is not None:
+ if configuration_parameters == "all":
+ ConfigHandler.update_configuration_values_to_all(append_configurations)
+ else:
+ try:
+ with open(configuration_parameters, "r") as f:
+ configuration_parameters = f.read().split(",")
+ ConfigHandler.update_configuration_values(
+ configuration_parameters, append_configurations
+ )
+ except OSError:
+ print("Could not open/read file:", configuration_parameters)
+ sys.exit()
+
+ store_dir = ""
+ report_file_name = ""
+ if enable_timestamp:
+ store_dir = "./regression_results/{tag}_{date}/".format(
+ tag=tag, date=datetime.datetime.now().strftime("%d_%m_%Y_%H_%M")
+ )
+ report_file_name = "{store_dir}/{tag}_{date}".format(
+ store_dir=store_dir,
+ tag=tag,
+ date=datetime.datetime.now().strftime("%d_%m_%Y_%H_%M"),
+ )
+ else:
+ store_dir = "./regression_results/{tag}/".format(tag=tag)
+ report_file_name = "{store_dir}/{tag}".format(store_dir=store_dir, tag=tag)
+
+ if not os.path.exists(store_dir):
+ os.makedirs(store_dir, exist_ok=True)
+
+ log = logging.getLogger("log")
+ log_formatter = logging.Formatter("[%(asctime)s - %(levelname)5s] %(message)s")
+ handler1 = logging.FileHandler(
+ "{report_file_name}.log".format(report_file_name=report_file_name), "w"
+ )
+ handler1.setFormatter(log_formatter)
+ log.addHandler(handler1)
+ handler2 = logging.StreamHandler()
+ handler2.setFormatter(log_formatter)
+ log.addHandler(handler2)
+ log.setLevel(logging.INFO)
+
+ report_log = logging.getLogger("report_log")
+ report_formatter = logging.Formatter("%(message)s")
+ report_handler = logging.FileHandler(
+ "{report_file_name}.csv".format(report_file_name=report_file_name), "w"
+ )
+ report_handler.setFormatter(report_formatter)
+ report_log.addHandler(report_handler)
+ report_log.setLevel(logging.INFO)
+
+ report_log.info(Report.get_header() + "," + ConfigHandler.get_header())
+
+ allow_print_rem_designs = False
+
+ def printRemDesignList():
+ t = threading.Timer(print_rem_time, printRemDesignList)
+ t.start()
+ if allow_print_rem_designs:
+ print("Remaining designs (design, # of times): ", rem_designs)
+ if len(rem_designs) == 0:
+ t.cancel()
+
+ def rmDesignFromPrintList(design):
+ if design in rem_designs.keys():
+ mutex.acquire()
+ try:
+ rem_designs[design] -= 1
+ if rem_designs[design] == 0:
+ rem_designs.pop(design)
+ finally:
+ mutex.release()
+
+ if print_rem_time is not None:
+ printRemDesignList()
+ allow_print_rem_designs = True
+
+ def update(status: str, design: str, message: str = None, error: bool = False):
+ str = "[%-5s] %-20s" % (status, design)
+ if message is not None:
+ str += f": {message}"
+
+ if error:
+ log.error(str)
+ else:
+ log.info(str)
+
+ flow_failure_flag = False
+ design_failure_flag = False
+
+ def run_design(designs_queue):
+ nonlocal design_failure_flag, flow_failure_flag
+ while not designs_queue.empty():
+ design, config, tag, design_name = designs_queue.get(
+ timeout=3
+ ) # 3s timeout
+ run_path = utils.get_run_path(design=design, tag=tag)
+ update("START", design)
+ command = [
+ os.getenv("OPENLANE_ENTRY") or "./flow.tcl",
+ "-design",
+ design,
+ "-tag",
+ tag,
+ "-config_tag",
+ config,
+ "-overwrite",
+ "-no_save",
+ "-run_hooks",
+ ] + (["-verbose", "1"] if show_log_output else [])
+ skip_rm_from_rems = False
+ try:
+ if show_log_output:
+ subprocess.check_call(command)
+ else:
+ subprocess.check_output(command, stderr=subprocess.PIPE)
+ except subprocess.CalledProcessError:
+ if print_rem_time is not None:
+ rmDesignFromPrintList(design)
+ skip_rm_from_rems = True
+ run_path_relative = os.path.relpath(run_path, ".")
+ update(
+ "FAIL",
+ design,
+ f"Check {run_path_relative}/openlane.log",
+ error=True,
+ )
+ design_failure_flag = True
+
+ if print_rem_time is not None and not skip_rm_from_rems:
+ rmDesignFromPrintList(design)
+
+ update("DONE", design, "Writing report...")
+ params = ConfigHandler.get_config(design, tag)
+
+ report = Report(design, tag, design_name, params).get_report()
+ report_log.info(report)
+
+ with open(f"{run_path}/report.csv", "w") as report_file:
+ report_file.write(
+ Report.get_header() + "," + ConfigHandler.get_header()
+ )
+ report_file.write("\n")
+ report_file.write(report)
+
+ if benchmark is not None:
+ try:
+ update("DONE", design, "Comparing with benchmark results...")
+ subprocess.check_output(
+ [
+ "python3",
+ "./scripts/compare_regression_design.py",
+ "--output-report",
+ f"{report_file_name}.rpt.yml",
+ "--benchmark",
+ benchmark,
+ "--design",
+ design,
+ "--run-path",
+ run_path,
+ f"{report_file_name}.csv",
+ ],
+ stderr=subprocess.PIPE,
+ )
+ except subprocess.CalledProcessError as e:
+ error_msg = e.stderr.decode("utf8")
+ update(
+ "ERROR",
+ design,
+ f"Failed to compare with benchmark: {error_msg}",
+ )
+ flow_failure_flag = True
+
+ if delete:
+ try:
+ update("DONE", design, "Deleting run directory...")
+ shutil.rmtree(run_path)
+ update("DONE", design, "Deleted run directory.")
+ except FileNotFoundError:
+ pass
+ except Exception:
+ update(
+ "ERROR", design, "Failed to delete run directory.", error=True
+ )
+ flow_failure_flag = True
+
+ q = queue.Queue()
+ total_runs = 0
+ if regression is not None:
+ regression_file = os.path.join(os.getcwd(), regression)
+ number_of_configs = 0
+ for design in designs:
+ base_path = utils.get_design_path(design=design)
+ if base_path is None:
+ update("ERROR", design, "Cannot run: Not found", error=True)
+ if print_rem_time is not None:
+ if design in rem_designs.keys():
+ rem_designs.pop(design)
+ continue
+ err, design_name = utils.get_design_name(design, config)
+ if err is not None:
+ update("ERROR", design, f"Cannot run: {err}", error=True)
+ continue
+ base_config_path = base_path + "base_config.tcl"
+
+ ConfigHandler.gen_base_config(design, base_config_path)
+
+ number_of_configs = subprocess.check_output(
+ [
+ "python3",
+ "./scripts/config/generate_config.py",
+ f"{base_path}/config_{tag}_",
+ base_config_path,
+ regression_file,
+ ]
+ )
+
+ number_of_configs = int(number_of_configs.decode(sys.getdefaultencoding()))
+ total_runs = total_runs + number_of_configs
+ if print_rem_time is not None:
+ rem_designs[design] = number_of_configs
+ for i in range(number_of_configs):
+ config_tag = f"config_{tag}_{i}"
+ q.put((design, config_tag, config_tag, design_name))
+ else:
+ for design in designs:
+ base_path = utils.get_design_path(design=design)
+ if base_path is None:
+ update("ALERT", design, "Not found, skipping...")
+ if print_rem_time is not None:
+ if design in rem_designs.keys():
+ rem_designs.pop(design)
+ continue
+ default_config_tag = "config_{tag}".format(tag=tag)
+ err, design_name = utils.get_design_name(design, config)
+ if err is not None:
+ update("ERROR", design, f"Cannot run: {err}")
+ continue
+ q.put((design, config, default_config_tag, design_name))
+
+ workers = []
+ for i in range(num_workers):
+ workers.append(threading.Thread(target=run_design, args=(q,)))
+ workers[i].start()
+
+ for i in range(num_workers):
+ while workers[i].is_alive():
+ workers[i].join(100)
+ log.info(f"Exiting thread {i}...")
+
+ log.info("Getting top results...")
+ subprocess.check_output(
+ [
+ "python3",
+ "./scripts/report/get_best.py",
+ "-i",
+ report_handler.baseFilename,
+ "-o",
+ f"{report_file_name}_best.csv",
+ ]
+ )
+
+ utils.add_computed_statistics(report_file_name + ".csv")
+ utils.add_computed_statistics(report_file_name + "_best.csv")
+
+ if benchmark is not None:
+ log.info("Benchmarking...")
+ full_benchmark_comp_cmd = [
+ "python3",
+ "./scripts/compare_regression_reports.py",
+ "--no-full-benchmark",
+ "--benchmark",
+ benchmark,
+ "--output-report",
+ f"{report_file_name}.rpt",
+ "--output-xlsx",
+ f"{report_file_name}.rpt.xlsx",
+ f"{report_file_name}.csv",
+ ]
+ subprocess.check_output(full_benchmark_comp_cmd)
+
+ log.info("Done.")
+
+ if design_failure_flag:
+ exit(2)
+ if flow_failure_flag:
+ exit(1)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/run_issue_regressions.py b/openlane/run_issue_regressions.py
new file mode 100755
index 0000000..2f29c42
--- /dev/null
+++ b/openlane/run_issue_regressions.py
@@ -0,0 +1,157 @@
+#!/usr/bin/env python3
+#
+# Copyright 2022 Arman Avetisyan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os # For checking if file exists
+import json # To serialize the matrix for the CI
+import click # For command line parsing
+import subprocess # For running the flow
+
+# TODO: If command is get designs
+# print(json.dumps({"design": designs}))
+# else if design specified
+#
+
+
+def get_test_cases():
+ openlane_dir_relative = os.path.dirname(os.path.relpath(__file__))
+ test_dir_relative = os.path.join(openlane_dir_relative, "tests")
+ retval = []
+ for file in os.listdir(test_dir_relative):
+ test_path = os.path.join(test_dir_relative, file)
+ if os.path.isdir(test_path):
+ retval.append(test_path)
+ return retval
+
+
+@click.group()
+def cli():
+ pass
+
+
+# Note: Following command is executed outside of OpenRoad, so you can't run the ./flow.tcl
+@click.command("get_matrix")
+def get_matrix():
+ print(json.dumps({"design": get_test_cases()}))
+
+
+cli.add_command(get_matrix)
+
+
+@click.command("run")
+@click.argument("test_case")
+def run_test_case_cmd(test_case):
+ run_test_case(test_case)
+
+
+cli.add_command(run_test_case_cmd)
+
+
+@click.command("run_all")
+def run_all():
+ for test_case in get_test_cases():
+ run_test_case(test_case)
+ print("Done.")
+
+
+cli.add_command(run_all)
+
+
+def run_test_case(test_case):
+ # test_case is the path to design
+ # test_case_name is name of design to test
+ # It is assumed that every test case is inside designs path
+
+ # -------------------------------
+ # 0. Calculate names
+ # -------------------------------
+ result = ""
+ test_case_issue_regression_script = test_case + "/issue_regression.py"
+ script_exists = os.path.isfile(test_case_issue_regression_script)
+ (_, test_case_name) = os.path.split(test_case)
+ # print("test_case_name", test_case_name)
+ logpath = "./regression_results/issue_regression_" + test_case_name + ".log"
+ logpath_check = (
+ "./regression_results/issue_regression_" + test_case_name + "_check.log"
+ )
+ # -------------------------------
+ # 1. Run the flow
+ # -------------------------------
+ try:
+ logfile = open(logpath, "w")
+ print(f"Running test case: {test_case_name} (logging to {logpath})")
+ interactive = []
+ interactive_file = os.path.join(test_case, "interactive.tcl")
+ if os.path.exists(interactive_file):
+ interactive = ["-it", "-file", interactive_file]
+ result = subprocess.run(
+ [
+ "./flow.tcl",
+ "-design",
+ test_case,
+ "-tag",
+ "issue_regression_run",
+ "-run_hooks",
+ "-overwrite",
+ ]
+ + interactive,
+ stdout=logfile,
+ stderr=subprocess.STDOUT,
+ check=True,
+ )
+ except subprocess.CalledProcessError as err:
+ # -------------------------------
+ # 2.1 If run was not successful, then run the issue_regression.py which
+ # will check if the fail was expected or not and it will also check the logs
+ # for errors to match
+ # 2.2 If issue_regression.py does not exist then it's enough for this design to pass LVS
+ # -------------------------------
+ if script_exists:
+ result = err
+ else:
+ print(
+ f"./flow.tcl failed and issue_regression.py does not exist, therefore test case {test_case} failed."
+ )
+ raise err
+ # -------------------------------
+ # 3. Run the issue_regression.py.
+ # -------------------------------
+ if script_exists:
+ print("Running post-run hook...")
+ logfile_check = open(logpath_check, "w")
+ try:
+ subprocess.run(
+ [
+ "openroad",
+ "-python",
+ test_case_issue_regression_script,
+ test_case + "/runs/issue_regression_run",
+ str(result.returncode),
+ ],
+ check=True,
+ stdout=logfile_check,
+ stderr=subprocess.STDOUT,
+ )
+ except subprocess.CalledProcessError as err:
+ # -------------------------------
+ # 4. Run the issue_regression.py. If it errors out, log it and then raise an error
+ # -------------------------------
+ print(f"{test_case_name} failed: see '{logpath_check}'.")
+ raise err
+ print(f"{test_case_name} completed successfully.")
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/add_def_obstructions.py b/openlane/scripts/add_def_obstructions.py
new file mode 100644
index 0000000..fbe8af6
--- /dev/null
+++ b/openlane/scripts/add_def_obstructions.py
@@ -0,0 +1,100 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import argparse
+import re
+import odb
+
+parser = argparse.ArgumentParser(description="Creates obstructions in def files.")
+
+parser.add_argument(
+ "--lef",
+ "-l",
+ nargs="+",
+ type=str,
+ default=None,
+ required=True,
+ help="LEF file needed to have a proper view of the DEF files.",
+)
+
+parser.add_argument(
+ "--input-def",
+ "-id",
+ required=True,
+ help="DEF view of the design that needs to be obstructed.",
+)
+
+parser.add_argument(
+ "--obstructions",
+ "-obs",
+ required=True,
+ help="Format: layer llx lly urx ury, ... (in microns)",
+)
+
+parser.add_argument("--output", "-o", required=True, help="Output DEF file.")
+
+args = parser.parse_args()
+
+input_lef_file_names = args.lef
+input_def_file_name = args.input_def
+obs_args = args.obstructions
+output_def_file_name = args.output
+
+RE_NUMBER = r"[\-]?[0-9]+(\.[0-9]+)?"
+RE_OBS = (
+ r"(?P<layer>\S+)\s+"
+ + r"(?P<bbox>"
+ + RE_NUMBER
+ + r"\s+"
+ + RE_NUMBER
+ + r"\s+"
+ + RE_NUMBER
+ + r"\s+"
+ + RE_NUMBER
+ + r")"
+)
+
+obses = obs_args.split(",")
+obs_list = []
+for obs in obses:
+ obs = obs.strip()
+ m = re.match(RE_OBS, obs)
+ assert (
+ m
+ ), "Incorrectly formatted input (%s).\n Format: layer llx lly urx ury, ..." % (obs)
+ layer = m.group("layer")
+ bbox = [float(x) for x in m.group("bbox").split()]
+ obs_list.append((layer, bbox))
+
+design_db = odb.dbDatabase.create()
+
+for lef in input_lef_file_names:
+ odb.read_lef(design_db, lef)
+
+odb.read_def(design_db, input_def_file_name)
+
+design_chip = design_db.getChip()
+design_block = design_chip.getBlock()
+design_insts = design_block.getInsts()
+design_tech = design_db.getTech()
+
+for obs in obs_list:
+ layer = obs[0]
+ bbox = obs[1]
+ dbu = design_tech.getDbUnitsPerMicron()
+ bbox = [int(x * dbu) for x in bbox]
+ print("Creating an obstruction on", layer, "at", *bbox, "(DBU)")
+ odb.dbObstruction_create(design_block, design_tech.findLayer(layer), *bbox)
+
+odb.write_def(design_block, output_def_file_name)
diff --git a/openlane/scripts/apply_def_template.py b/openlane/scripts/apply_def_template.py
new file mode 100644
index 0000000..1d430c5
--- /dev/null
+++ b/openlane/scripts/apply_def_template.py
@@ -0,0 +1,50 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import click
+import shutil
+import defutil
+
+
+@click.command()
+@click.option("-t", "--def-template", "templatedef", required=True, help="Template DEF")
+@click.option("-l", "--lef", "lef", required=True, help="LEF file")
+@click.option("-lg", "--log", "logfile", required=True, help="Log output file")
+@click.argument("userdef")
+def cli(templatedef, userdef, lef, logfile):
+ userDEF = userdef
+ templateDEF = templatedef
+
+ # Removed section to remove the power/ground pins as defutil:replace_pins implements this
+
+ defutil.replace_pins(
+ input_lef=lef,
+ logpath=logfile,
+ template_def=templateDEF,
+ source_def=userDEF,
+ output_def=f"{userDEF}.replace_pins.tmp",
+ )
+
+ # Call defutil to move die area
+ defutil.move_diearea(
+ template_def=templateDEF,
+ output_def=f"{userDEF}.replace_pins.tmp",
+ input_lef=lef,
+ )
+ shutil.copy(f"{userDEF}.replace_pins.tmp", userDEF)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/base.sdc b/openlane/scripts/base.sdc
new file mode 100644
index 0000000..9e965a8
--- /dev/null
+++ b/openlane/scripts/base.sdc
@@ -0,0 +1,40 @@
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+ create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+} else {
+ create_clock -name __VIRTUAL_CLK__ -period $::env(CLOCK_PERIOD)
+ set ::env(CLOCK_PORT) __VIRTUAL_CLK__
+}
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+
+# correct resetn
+set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
\ No newline at end of file
diff --git a/openlane/scripts/compare_regression_design.py b/openlane/scripts/compare_regression_design.py
new file mode 100644
index 0000000..06d999f
--- /dev/null
+++ b/openlane/scripts/compare_regression_design.py
@@ -0,0 +1,193 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import yaml
+import click
+
+
+@click.command()
+@click.option(
+ "--benchmark",
+ "-b",
+ "benchmark_file",
+ required=True,
+ help="The csv file from which to extract the benchmark results",
+)
+@click.option(
+ "--design",
+ "-d",
+ required=True,
+ help="The design to compare for between the two scripts. Same as -design in flow.tcl",
+)
+@click.option(
+ "--run-path",
+ "-p",
+ required=True,
+ help="The run path, will be used to search for any missing files.",
+)
+@click.option(
+ "--output-report",
+ "-o",
+ "output_report_file",
+ required=True,
+ help="The file to print the final report in",
+)
+@click.argument("regression_results_file")
+def cli(benchmark_file, design, run_path, output_report_file, regression_results_file):
+ tolerance = {
+ "general_tolerance": 1,
+ "tritonRoute_violations": 2,
+ "Magic_violations": 10,
+ "antenna_violations": 10,
+ "lvs_total_errors": 0,
+ }
+
+ critical_statistics = [
+ "tritonRoute_violations",
+ "Magic_violations",
+ "antenna_violations",
+ "lvs_total_errors",
+ ]
+
+ magic_file_extensions = ["gds", "mag", "lef", "spice"]
+
+ def compare_vals(benchmark_value, regression_value, param):
+ if str(benchmark_value) == "-1":
+ return True
+ if str(regression_value) == "-1":
+ return False
+ tol = 0 - tolerance["general_tolerance"]
+ if param in tolerance.keys():
+ tol = 0 - tolerance[param]
+ if float(benchmark_value) - float(regression_value) >= tol:
+ return True
+ else:
+ return False
+
+ def parse_csv(csv_file):
+ def get_csv_index(header, label):
+ for i in range(len(header)):
+ if label == header[i]:
+ return i
+ else:
+ return -1
+
+ design_out = dict()
+ csv_opener = open(csv_file, "r")
+ csv_data = csv_opener.read().split("\n")
+ header_info = csv_data[0].split(",")
+ designPathIdx = get_csv_index(header_info, "design")
+ if designPathIdx == -1:
+ print("invalid report. No design paths.")
+ for i in range(1, len(csv_data)):
+ if not len(csv_data[i]):
+ continue
+ entry = csv_data[i].split(",")
+ designPath = entry[designPathIdx]
+ if designPath == design:
+ for idx in range(len(header_info)):
+ if idx != designPathIdx:
+ design_out[header_info[idx]] = entry[idx]
+ break
+ return design_out
+
+ def critical_mismatch(benchmark, regression_result):
+ if len(benchmark):
+ return False, "The design is not benchmarked"
+ for stat in critical_statistics:
+ if compare_vals(benchmark[stat], regression_result[stat], stat):
+ continue
+ else:
+ if str(regression_result[stat]) == "-1":
+ return (
+ True,
+ "The test didn't pass the stage responsible for " + stat,
+ )
+ else:
+ return (
+ True,
+ "The results of " + stat + " mismatched with the benchmark",
+ )
+ return False, "The test passed"
+
+ def compare_status(benchmark, regression_result):
+ if len(benchmark) == 0:
+ return False, "The design is not benchmarked"
+ elif "fail" in str(regression_result["flow_status"]):
+ if "fail" in str(benchmark["flow_status"]):
+ return (
+ False,
+ "The OpenLane flow failed, but the benchmark never saw it succeed",
+ )
+ else:
+ return True, "The OpenLane flow failed outright, check the logs"
+ else:
+ return False, "The test passed"
+
+ def missing_resulting_files(design):
+ search_prefix = os.path.join(
+ run_path, "results", "signoff", str(design["design_name"])
+ )
+ for ext in magic_file_extensions:
+ required_result = f"{search_prefix}.{ext}"
+ if not os.path.isfile(required_result):
+ return (
+ True,
+ f"File {required_result} is missing from the results directory",
+ )
+ return False, "The test passed"
+
+ benchmark = parse_csv(benchmark_file)
+ regression_result = parse_csv(regression_results_file)
+
+ did_pass = True
+ notes = None
+
+ failure, reason = compare_status(benchmark, regression_result)
+ if failure:
+ did_pass = False
+ notes = notes or reason
+
+ failure, reason = critical_mismatch(benchmark, regression_result)
+ if failure:
+ did_pass = False
+ notes = notes or reason
+
+ failure, reason = missing_resulting_files(regression_result)
+ if failure:
+ did_pass = False
+ notes = notes or reason
+
+ design_report = {"pass": did_pass, "notes": notes}
+
+ current_yaml_str = "{}"
+ try:
+ current_yaml_str = open(output_report_file).read()
+ except FileNotFoundError:
+ pass
+
+ current_yaml = yaml.safe_load(current_yaml_str)
+ current_yaml[design] = design_report
+
+ current_yaml_str = yaml.safe_dump(current_yaml, sort_keys=False)
+ import sys
+
+ print(output_report_file, file=sys.stderr)
+ with open(output_report_file, "w") as f:
+ f.write(current_yaml_str)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/compare_regression_reports.py b/openlane/scripts/compare_regression_reports.py
new file mode 100644
index 0000000..2af2a6b
--- /dev/null
+++ b/openlane/scripts/compare_regression_reports.py
@@ -0,0 +1,622 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import click
+import xlsxwriter
+
+
+@click.command()
+@click.option(
+ "--benchmark",
+ "-b",
+ "benchmark_file",
+ required=True,
+ help="The csv file from which to extract the benchmark results",
+)
+@click.option(
+ "--full-benchmark/--no-full-benchmark",
+ default=True,
+ help="If no, use the regression results instead of the benchmark as the design list, i.e., don't look for *every* design in the benchmark.",
+)
+@click.option(
+ "--output-report",
+ "-o",
+ "output_report_file",
+ required=True,
+ help="The file to print the final report in",
+)
+@click.option(
+ "--output-xlsx",
+ "-x",
+ "output_xlsx_file",
+ required=False,
+ help="The csv file to print a merged csv file benchmark vs regression_script in",
+)
+@click.argument("regression_results_file")
+def cli(
+ benchmark_file,
+ full_benchmark,
+ output_report_file,
+ output_xlsx_file,
+ regression_results_file,
+):
+ not_full_benchmark = not full_benchmark
+
+ benchmark = dict()
+ regression_results = dict()
+
+ output_report_list = []
+
+ testFail = False
+
+ configuration_mismatches = []
+ critical_mismatches = []
+
+ missing_configs = []
+
+ base_configs = [
+ "CLOCK_PERIOD",
+ "SYNTH_STRATEGY",
+ "SYNTH_MAX_FANOUT",
+ "FP_CORE_UTIL",
+ "FP_ASPECT_RATIO",
+ "FP_PDN_VPITCH",
+ "FP_PDN_HPITCH",
+ "PL_TARGET_DENSITY",
+ "GLB_RT_ADJUSTMENT",
+ "STD_CELL_LIBRARY",
+ "CELL_PAD",
+ "DIODE_INSERTION_STRATEGY",
+ ]
+
+ tolerance = {
+ "general_tolerance": 1,
+ "tritonRoute_violations": 2,
+ "Magic_violations": 10,
+ "antenna_violations": 10,
+ "lvs_total_errors": 0,
+ }
+
+ critical_statistics = [
+ "tritonRoute_violations",
+ "Magic_violations",
+ "antenna_violations",
+ "lvs_total_errors",
+ ]
+
+ note_worthy_statistics = []
+
+ ignore_list = ["", "design", "design_name", "config"]
+
+ def compare_vals(benchmark_value, regression_value, param):
+ if str(benchmark_value) == "-1":
+ return True
+ if str(regression_value) == "-1":
+ return False
+ tol = 0 - tolerance["general_tolerance"]
+ if param in tolerance.keys():
+ tol = 0 - tolerance[param]
+ if float(benchmark_value) - float(regression_value) >= tol:
+ return True
+ else:
+ return False
+
+ def findIdx(header, label):
+ for idx in range(len(header)):
+ if label == header[idx]:
+ return idx
+ else:
+ return -1
+
+ def diff_list(l1, l2):
+ return [x for x in l1 if x not in l2]
+
+ def parseCSV(csv_file, isBenchmark):
+ nonlocal note_worthy_statistics
+ map_out = dict()
+ csvOpener = open(csv_file, "r")
+ csvData = csvOpener.read().split("\n")
+ headerInfo = csvData[0].split(",")
+ designNameIdx = findIdx(headerInfo, "design")
+ if isBenchmark:
+ note_worthy_statistics = diff_list(
+ diff_list(diff_list(headerInfo, ignore_list), critical_statistics),
+ base_configs,
+ )
+
+ remover = 0
+ size = len(base_configs)
+ while remover < size:
+ if base_configs[remover] not in headerInfo:
+ missing_configs.append(base_configs[remover])
+ base_configs.pop(remover)
+ remover -= 1
+ size -= 1
+ remover += 1
+
+ if designNameIdx == -1:
+ print("Invalid report. No design name was found.")
+ exit(-1)
+ for i in range(1, len(csvData)):
+ if len(csvData[i]):
+ entry = csvData[i].split(",")
+ designName = entry[designNameIdx]
+ for idx in range(len(headerInfo)):
+ if idx != designNameIdx:
+ if designName not in map_out.keys():
+ map_out[designName] = dict()
+ if isBenchmark:
+ map_out[designName]["Status"] = "PASSED"
+ else:
+ map_out[designName]["Status"] = "----"
+ map_out[designName][headerInfo[idx]] = str(entry[idx])
+ return map_out
+
+ def configurationMismatch(benchmark, regression_results):
+ nonlocal configuration_mismatches
+ designList = list()
+ if not_full_benchmark:
+ designList = regression_results.keys()
+ else:
+ designList = benchmark.keys()
+
+ for design in designList:
+ output_report_list.append(
+ "\nComparing Configurations for: " + design + "\n"
+ )
+ configuration_mismatches.append(
+ "\nComparing Configurations for: " + design + "\n"
+ )
+ if design not in regression_results:
+ output_report_list.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided regression sheet\n"
+ )
+ configuration_mismatches.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided regression sheet\n"
+ )
+ continue
+
+ if design not in benchmark:
+ output_report_list.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided benchmark sheet\n"
+ )
+ configuration_mismatches.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided benchmark sheet\n"
+ )
+ continue
+
+ size_before = len(configuration_mismatches)
+ for config in base_configs:
+ if benchmark[design][config] == regression_results[design][config]:
+ output_report_list.append("\tConfiguration " + config + " MATCH\n")
+ output_report_list.append(
+ "\t\tConfiguration "
+ + config
+ + " value: "
+ + benchmark[design][config]
+ + "\n"
+ )
+ else:
+ configuration_mismatches.append(
+ "\tConfiguration " + config + " MISMATCH\n"
+ )
+ output_report_list.append(
+ "\tConfiguration " + config + " MISMATCH\n"
+ )
+ configuration_mismatches.append(
+ "\t\tDesign "
+ + design
+ + " Configuration "
+ + config
+ + " BENCHMARK value: "
+ + benchmark[design][config]
+ + "\n"
+ )
+ output_report_list.append(
+ "\t\tDesign "
+ + design
+ + " Configuration "
+ + config
+ + " BENCHMARK value: "
+ + benchmark[design][config]
+ + "\n"
+ )
+ configuration_mismatches.append(
+ "\t\tDesign "
+ + design
+ + " Configuration "
+ + config
+ + " USER value: "
+ + regression_results[design][config]
+ + "\n"
+ )
+ output_report_list.append(
+ "\t\tDesign "
+ + design
+ + " Configuration "
+ + config
+ + " USER value: "
+ + regression_results[design][config]
+ + "\n"
+ )
+ if size_before == len(configuration_mismatches):
+ configuration_mismatches = configuration_mismatches[:-1]
+
+ def criticalMistmatch(benchmark, regression_results):
+ nonlocal testFail
+ nonlocal critical_mismatches
+ designList = list()
+ if not_full_benchmark:
+ designList = regression_results.keys()
+ else:
+ designList = benchmark.keys()
+
+ for design in designList:
+ output_report_list.append(
+ "\nComparing Critical Statistics for: " + design + "\n"
+ )
+ critical_mismatches.append(
+ "\nComparing Critical Statistics for: " + design + "\n"
+ )
+ if design not in regression_results:
+ testFail = True
+ benchmark[design]["Status"] = "NOT FOUND"
+ output_report_list.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided regression sheet\n"
+ )
+ critical_mismatches.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided regression sheet\n"
+ )
+ continue
+
+ if design not in benchmark:
+ testFail = False
+ output_report_list.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided benchmark sheet\n"
+ )
+ critical_mismatches.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided benchmark sheet\n"
+ )
+ continue
+
+ size_before = len(critical_mismatches)
+ for stat in critical_statistics:
+ if compare_vals(
+ benchmark[design][stat], regression_results[design][stat], stat
+ ):
+ output_report_list.append("\tStatistic " + stat + " MATCH\n")
+ output_report_list.append(
+ "\t\tStatistic "
+ + stat
+ + " value: "
+ + benchmark[design][stat]
+ + "\n"
+ )
+ else:
+ testFail = True
+ benchmark[design]["Status"] = "FAIL"
+ critical_mismatches.append("\tStatistic " + stat + " MISMATCH\n")
+ output_report_list.append("\tStatistic " + stat + " MISMATCH\n")
+ critical_mismatches.append(
+ "\t\tDesign "
+ + design
+ + " Statistic "
+ + stat
+ + " BENCHMARK value: "
+ + benchmark[design][stat]
+ + "\n"
+ )
+ output_report_list.append(
+ "\t\tDesign "
+ + design
+ + " Statistic "
+ + stat
+ + " BENCHMARK value: "
+ + benchmark[design][stat]
+ + "\n"
+ )
+ critical_mismatches.append(
+ "\t\tDesign "
+ + design
+ + " Statistic "
+ + stat
+ + " USER value: "
+ + regression_results[design][stat]
+ + "\n"
+ )
+ output_report_list.append(
+ "\t\tDesign "
+ + design
+ + " Statistic "
+ + stat
+ + " USER value: "
+ + regression_results[design][stat]
+ + "\n"
+ )
+ if len(critical_mismatches) == size_before:
+ critical_mismatches = critical_mismatches[:-1]
+
+ def noteWorthyMismatch(benchmark, regression_results):
+ designList = list()
+ if not_full_benchmark:
+ designList = regression_results.keys()
+ else:
+ designList = benchmark.keys()
+
+ for design in designList:
+ output_report_list.append(
+ "\nComparing Note Worthy Statistics for: " + design + "\n"
+ )
+ if design not in regression_results:
+ output_report_list.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided regression sheet\n"
+ )
+ continue
+
+ if design not in benchmark:
+ output_report_list.append(
+ "\tDesign "
+ + design
+ + " Not Found in the provided benchmark sheet\n"
+ )
+ continue
+
+ for stat in note_worthy_statistics:
+ if (
+ benchmark[design][stat] == regression_results[design][stat]
+ or benchmark[design][stat] == "-1"
+ ):
+ output_report_list.append("\tStatistic " + stat + " MATCH\n")
+ output_report_list.append(
+ "\t\tStatistic "
+ + stat
+ + " value: "
+ + benchmark[design][stat]
+ + "\n"
+ )
+ else:
+ output_report_list.append("\tStatistic " + stat + " MISMATCH\n")
+ output_report_list.append(
+ "\t\tDesign "
+ + design
+ + " Statistic "
+ + stat
+ + " BENCHMARK value: "
+ + benchmark[design][stat]
+ + "\n"
+ )
+ output_report_list.append(
+ "\t\tDesign "
+ + design
+ + " Statistic "
+ + stat
+ + " USER value: "
+ + regression_results[design][stat]
+ + "\n"
+ )
+
+ flow_failures = []
+
+ def flowFailures(regression_results):
+ nonlocal flow_failures
+ for design in regression_results.keys():
+ if "failed" in regression_results[design]["flow_status"]:
+ flow_failures.append(design)
+
+ benchmark = parseCSV(benchmark_file, 1)
+ regression_results = parseCSV(regression_results_file, 0)
+ flowFailures(regression_results)
+ configurationMismatch(benchmark, regression_results)
+ criticalMistmatch(benchmark, regression_results)
+ noteWorthyMismatch(benchmark, regression_results)
+
+ with open(output_report_file, "w") as report_file:
+
+ def write(*args, **kwargs):
+ print(*args, **kwargs, file=report_file)
+
+ if testFail:
+ write("Failed")
+ else:
+ write("Passed")
+ write("---")
+
+ if len(flow_failures):
+ write("[OpenLane Flow Failures] (Designs where OpenLane failed outright)")
+ write("")
+ for failure in flow_failures:
+ write(failure)
+ write("")
+ write("---")
+
+ if len(missing_configs):
+ write("[Missing Configuration Variables] (Do not exist in the sheets.)")
+ write("")
+ for variable in missing_configs:
+ write(variable)
+ write("")
+ write("---")
+
+ if testFail:
+ write("[Critical Mismatches] (Cause Failures)")
+ write("".join(critical_mismatches))
+ write("---")
+
+ if testFail and len(configuration_mismatches):
+ write(
+ "[Configuration Mismatches] (May Contribute To Differences Between Results)"
+ )
+ write("".join(configuration_mismatches))
+ write("---")
+
+ write("[Full Report]")
+ write("".join(output_report_list))
+
+ def formNotFoundStatus(benchmark, regression_results):
+ for design in benchmark.keys():
+ if design not in regression_results:
+ benchmark[design]["Status"] = "NOT FOUND"
+
+ formNotFoundStatus(benchmark, regression_results)
+
+ if output_xlsx_file is None:
+ return
+
+ # Open an Excel workbook
+ workbook = xlsxwriter.Workbook(output_xlsx_file)
+
+ # Set up a format
+ fail_format = workbook.add_format(properties={"bold": True, "font_color": "red"})
+ pass_format = workbook.add_format(properties={"bold": True, "font_color": "green"})
+ diff_format = workbook.add_format(properties={"font_color": "blue"})
+ header_format = workbook.add_format(properties={"font_color": "gray"})
+ benchmark_format = workbook.add_format(
+ properties={"bold": True, "font_color": "navy"}
+ )
+
+ # Create a sheet
+ worksheet = workbook.add_worksheet("diff")
+
+ headerInfo = ["Owner", "design", "Status"]
+ headerInfo.extend(critical_statistics)
+ headerInfo.extend(note_worthy_statistics)
+ headerInfo.extend(base_configs)
+
+ # Write the headers
+ for col_num, header in enumerate(headerInfo):
+ worksheet.write(0, col_num, header, header_format)
+
+ # Save the data from the OrderedDict into the excel sheet
+ idx = 0
+ while idx < len(benchmark):
+ worksheet.write(idx * 2 + 1, 0, "Benchmark", benchmark_format)
+ worksheet.write(idx * 2 + 2, 0, "User")
+
+ design = str(list(benchmark.keys())[idx])
+ if design not in regression_results:
+ for col_num, header in enumerate(headerInfo):
+ if header == "Owner":
+ worksheet.write(idx * 2 + 1, col_num, "Benchmark", benchmark_format)
+ worksheet.write(idx * 2 + 2, col_num, "User")
+ continue
+ if header == "design":
+ worksheet.write(idx * 2 + 1, col_num, design)
+ worksheet.write(idx * 2 + 2, col_num, design)
+ continue
+ worksheet.write(idx * 2 + 1, col_num, benchmark[design][header])
+ else:
+ for col_num, header in enumerate(headerInfo):
+ if header == "Owner":
+ worksheet.write(idx * 2 + 1, col_num, "Benchmark", benchmark_format)
+ worksheet.write(idx * 2 + 2, col_num, "User")
+ continue
+ if header == "design":
+ worksheet.write(idx * 2 + 1, col_num, design)
+ worksheet.write(idx * 2 + 2, col_num, design)
+ continue
+ if header == "Status":
+ if benchmark[design][header] == "PASSED":
+ worksheet.write(
+ idx * 2 + 1, col_num, benchmark[design][header], pass_format
+ )
+ worksheet.write(
+ idx * 2 + 2,
+ col_num,
+ regression_results[design][header],
+ pass_format,
+ )
+ else:
+ worksheet.write(
+ idx * 2 + 1, col_num, benchmark[design][header], fail_format
+ )
+ worksheet.write(
+ idx * 2 + 2,
+ col_num,
+ regression_results[design][header],
+ fail_format,
+ )
+ continue
+ if benchmark[design][header] != regression_results[design][header]:
+ if header in critical_statistics:
+ if not compare_vals(
+ benchmark[design][header],
+ regression_results[design][header],
+ header,
+ ):
+ worksheet.write(
+ idx * 2 + 1,
+ col_num,
+ benchmark[design][header],
+ fail_format,
+ )
+ worksheet.write(
+ idx * 2 + 2,
+ col_num,
+ regression_results[design][header],
+ fail_format,
+ )
+ else:
+ worksheet.write(
+ idx * 2 + 1,
+ col_num,
+ benchmark[design][header],
+ pass_format,
+ )
+ worksheet.write(
+ idx * 2 + 2,
+ col_num,
+ regression_results[design][header],
+ pass_format,
+ )
+ else:
+ worksheet.write(
+ idx * 2 + 1, col_num, benchmark[design][header], diff_format
+ )
+ worksheet.write(
+ idx * 2 + 2,
+ col_num,
+ regression_results[design][header],
+ diff_format,
+ )
+ else:
+ worksheet.write(idx * 2 + 1, col_num, benchmark[design][header])
+ worksheet.write(
+ idx * 2 + 2, col_num, regression_results[design][header]
+ )
+ idx += 1
+
+ # Close the workbook
+ workbook.close()
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/config/config.py b/openlane/scripts/config/config.py
new file mode 100644
index 0000000..6258a4a
--- /dev/null
+++ b/openlane/scripts/config/config.py
@@ -0,0 +1,106 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import subprocess
+import sys
+
+sys.path.append(os.path.dirname(os.path.dirname(__file__)))
+
+from utils.utils import get_run_path, get_design_path # noqa: E402
+from shutil import copyfile # noqa: E402
+from collections import OrderedDict # noqa: E402
+
+
+class ConfigHandler:
+ config_getter_script = os.path.join(os.path.dirname(__file__), "config_get.sh")
+
+ configuration_values = [
+ "CLOCK_PERIOD",
+ "SYNTH_STRATEGY",
+ "SYNTH_MAX_FANOUT",
+ "FP_CORE_UTIL",
+ "FP_ASPECT_RATIO",
+ "FP_PDN_VPITCH",
+ "FP_PDN_HPITCH",
+ "PL_TARGET_DENSITY",
+ "GLB_RT_ADJUSTMENT",
+ "STD_CELL_LIBRARY",
+ "CELL_PAD",
+ "DIODE_INSERTION_STRATEGY",
+ ]
+
+ configuration_files = [
+ "synthesis.tcl",
+ "floorplan.tcl",
+ "placement.tcl",
+ "cts.tcl",
+ "routing.tcl",
+ # "magic.tcl",
+ ]
+
+ @classmethod
+ def update_configuration_values(Self, params, append):
+ if append:
+ Self.configuration_values = Self.configuration_values + params
+ else:
+ Self.configuration_values = params
+ Self.configuration_values = list(
+ OrderedDict.fromkeys(Self.configuration_values)
+ )
+
+ @classmethod
+ def update_configuration_values_to_all(Self, append):
+ config_relative_path = "configuration"
+ config_path = os.path.join(os.getcwd(), config_relative_path)
+ if not append:
+ Self.configuration_values = []
+
+ for file in Self.configuration_files:
+ try:
+ file_string = open(os.path.join(config_path, file), "r").read()
+ file_lines = file_string.split("\n")
+ for line in file_lines:
+ start = line.find("(")
+ end = line.find(")")
+ if (start > -1) & (end > 0) & (line.find("SCRIPT") == -1):
+ Self.configuration_values.append(line[start + 1 : end])
+ except OSError:
+ print("Could not open/read file:", config_path)
+ sys.exit()
+ Self.configuration_values = list(dict.fromkeys(Self.configuration_values))
+
+ @classmethod
+ def get_header(Self):
+ return ",".join(Self.configuration_values)
+
+ @classmethod
+ def get_config(Self, design, tag, run_path=None):
+ if run_path is None:
+ run_path = get_run_path(design=design, tag=tag)
+ config_relative_path = "config.tcl"
+ config_path = os.path.join(os.getcwd(), run_path, config_relative_path)
+ config_coded = subprocess.check_output(
+ [Self.config_getter_script, config_path, *Self.configuration_values]
+ )
+ config = config_coded.decode(sys.getfilesystemencoding()).strip()
+ config = config.split("##")
+ config = list(filter(None, config))
+ config = [element.strip('{}"') for element in config]
+ return config
+
+ @staticmethod
+ def gen_base_config(design, base_config_file):
+ config_file = os.path.join(get_design_path(design=design), "config.tcl")
+ copyfile(config_file, base_config_file)
diff --git a/openlane/scripts/config/config_get.sh b/openlane/scripts/config/config_get.sh
new file mode 100755
index 0000000..d0558dd
--- /dev/null
+++ b/openlane/scripts/config/config_get.sh
@@ -0,0 +1,46 @@
+#!/bin/bash
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+config_file=$1
+args=()
+for arg in "$@"; do
+ args+=("$arg")
+done
+for config_name in "${args[@]:1}"; do
+ val=$(grep "($config_name)" $config_file | tail -1 |sed "s/set *::env(${config_name}) *//")
+ if ! [[ $val ]]; then val=-1; fi
+ printf "##$val"
+done
+printf "##\n"
+
+#get_config_val $config_path $af
+#af_val=$val
+#get_config_val $config_path $util
+#util_val=$val
+#get_config_val $config_path $dens
+#dens_val=$val
+#get_config_val $config_path $strat
+#strat_val=$val
+#get_config_val $config_path $fan
+#fan_val=$val
+#get_config_val $config_path $pdn_v
+#pdn_v_val=$val
+#get_config_val $config_path $pdn_h
+#pdn_h_val=$val
+#get_config_val $config_path $ar
+#ar_val=$val
+
+#echo "$af_val $util_val $dens_val $strat_val $fan_val $pdn_v_val $pdn_h_val $ar_val"
diff --git a/openlane/scripts/config/generate_config.py b/openlane/scripts/config/generate_config.py
new file mode 100644
index 0000000..a9c359a
--- /dev/null
+++ b/openlane/scripts/config/generate_config.py
@@ -0,0 +1,135 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import sys
+
+outputPrefix = sys.argv[1]
+baseConfigFile = sys.argv[2]
+regressionFile = sys.argv[3]
+
+idx = [0]
+
+valuesList = []
+keysList = []
+
+extra = []
+
+std_cell_library = []
+
+
+def readContent(regressionFile):
+ try:
+ tmpFile = open(regressionFile, "r")
+ if tmpFile.mode == "r":
+ regressionFileContent = tmpFile.read().split("\n")
+ i = 0
+ while i < len(regressionFileContent):
+ line = regressionFileContent[i]
+ if line == "":
+ i += 1
+ continue
+ elif line.find("extra") != -1:
+ while regressionFileContent[i][0] != '"':
+ i += 1
+ if (regressionFileContent[i][0] != '"') and (
+ regressionFileContent[i] != ""
+ ):
+ extra.append(regressionFileContent[i])
+ elif line.find("std_cell_library") != -1:
+ while regressionFileContent[i][0] != '"':
+ i += 1
+ if (regressionFileContent[i][0] != '"') and (
+ regressionFileContent[i] != ""
+ ):
+ std_cell_library.append(regressionFileContent[i])
+ else:
+ keysList.append(line.split("=")[0])
+ vals = line.split("=")[1]
+ vals = vals[1:-1]
+ valuesList.append(vals.split(","))
+ i += 1
+ except OSError:
+ print("Could not open/read file:", regressionFile)
+ sys.exit()
+
+
+def resolveExpression(valExpression, expressionKeeper):
+ for i in expressionKeeper.keys():
+ valExpression = valExpression.replace(i, expressionKeeper[i])
+ try:
+ ret = eval(valExpression)
+ return ret
+ except Exception:
+ return valExpression
+
+
+def insertSCL(configs):
+ if len(std_cell_library):
+ lines = configs.split("\n")
+ for idx in range(len(lines)):
+ if lines[idx].find("$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl") != -1:
+ for var in std_cell_library:
+ lines.insert(idx, var)
+ idx += 1
+ configs = "\n".join(lines)
+ return configs
+ for var in std_cell_library:
+ lines.insert(0, var)
+ configs = "\n".join(lines)
+ return configs
+ else:
+ return configs
+
+
+def Generator(i, j, regression_config, expressionKeeper):
+ if i == len(keysList) - 1:
+ outFileName = outputPrefix + str(idx[0]) + ".tcl"
+ outFile = open(outFileName, "w")
+ outFile.write("\n# Design\n")
+ baseConfigFileRead = open(baseConfigFile, "r")
+ outFile.write(insertSCL(baseConfigFileRead.read()))
+ outFile.write("\n# Regression\n")
+ newVal = valuesList[i][j]
+ if newVal.isupper() or newVal.islower():
+ newVal = str(resolveExpression(newVal, expressionKeeper))
+ outFile.write(
+ regression_config + "set ::env(" + keysList[i] + ') "' + newVal + '"\n'
+ )
+ outFile.write("\n# Extra\n")
+ for x in extra:
+ outFile.write(x + "\n")
+ outFile.close()
+ idx[0] += 1
+ else:
+ for k in range(len(valuesList[i + 1])):
+ newVal = valuesList[i][j]
+ if newVal.isupper() or newVal.islower():
+ newVal = str(resolveExpression(newVal, expressionKeeper))
+
+ expressionKeeper[keysList[i]] = newVal
+ Generator(
+ i + 1,
+ k,
+ regression_config + "set ::env(" + keysList[i] + ') "' + newVal + '"\n',
+ expressionKeeper,
+ )
+ expressionKeeper.pop(keysList[i])
+
+
+readContent(regressionFile)
+expressionKeeper = dict()
+for k in range(len(valuesList[0])):
+ Generator(0, k, "", expressionKeeper)
+
+print(idx[0])
diff --git a/openlane/scripts/contextualize.py b/openlane/scripts/contextualize.py
new file mode 100644
index 0000000..0f4986b
--- /dev/null
+++ b/openlane/scripts/contextualize.py
@@ -0,0 +1,167 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import odb
+
+parser = argparse.ArgumentParser(
+ description="Produces a DEF file where a design is shown in the context of its instantiation in a top-level design"
+)
+
+parser.add_argument("--macro-def", "-md", required=True, help="DEF view of the design")
+
+parser.add_argument(
+ "--macro-lef",
+ "-ml",
+ required=True,
+ help="LEF file needed to have a proper view of the macro DEF",
+)
+
+parser.add_argument(
+ "--top-def",
+ "-td",
+ required=True,
+ help="DEF view of the top-level design where the macro is instantiated",
+)
+parser.add_argument(
+ "--top-lef",
+ "-tl",
+ required=True,
+ help="LEF file needed to have a proper view of the top-level DEF",
+)
+
+parser.add_argument(
+ "--output",
+ "-o",
+ required=True,
+ default="output.def",
+ help="Output Contextualized DEF",
+)
+
+parser.add_argument(
+ "--keep-inner-connections",
+ "-keep",
+ action="store_true",
+ default=False,
+ help="If set, the internal cells will remain conneted in the otput DEF",
+)
+
+
+args = parser.parse_args()
+
+macro_def_file_name = args.macro_def
+macro_lef_file_name = args.macro_lef
+top_def_file_name = args.top_def
+top_lef_file_name = args.top_lef
+keep_flag = args.keep_inner_connections
+
+output_def_file_name = args.output
+
+# in the tcl side
+# top_lef_new_file_name = os.path.join(os.path.dirname(macro_lef_file_name), os.path.basename(macro_lef_file_name) + ".top.lef")
+# top_def_new_file_name = os.path.join(os.path.dirname(macro_def_file_name), os.path.basename(macro_def_file_name) + ".top.def")
+
+# copy(os.path.normpath(top_lef_file_name), top_lef_new_file_name)
+# copy(os.path.normpath(top_def_file_name), top_def_new_file_name)
+
+# top_lef_file_name = top_lef_new_file_name
+# top_def_file_name = top_def_new_file_name
+
+db_macro = odb.dbDatabase.create()
+db_top = odb.dbDatabase.create()
+odb.read_lef(
+ db_macro, top_lef_file_name
+) # must read first to have consistent views with the top-level
+odb.read_lef(
+ db_macro, macro_lef_file_name
+) # rest of the macros that don't appear in the top-level are covered here
+odb.read_def(db_macro, macro_def_file_name)
+
+odb.read_lef(db_top, top_lef_file_name)
+odb.read_def(db_top, top_def_file_name)
+
+chip_macro = db_macro.getChip()
+block_macro = chip_macro.getBlock()
+macro_design_name = block_macro.getName()
+
+chip_top = db_top.getChip()
+block_top = chip_top.getBlock()
+top_design_name = block_top.getName()
+
+print("Block design name:", macro_design_name)
+print("Top-level design name:", top_design_name)
+
+nets_top = block_top.getNets()
+to_connect = {}
+MACRO_TOP_PLACEMENT_X = 0
+MACRO_TOP_PLACEMENT_Y = 0
+MACRO_TOP_PLACEMENT_ORIENT = 0
+
+assert macro_design_name in [
+ inst.getMaster().getName() for inst in block_top.getInsts()
+], "%s not found in %s" % (macro_design_name, top_design_name)
+
+for net in nets_top:
+ iterms = net.getITerms() # asssumption: no pins (bterms) on top level
+ block_net_name = None
+ for iterm in iterms:
+ macro_name = iterm.getMTerm().getMaster().getName()
+ if macro_name == macro_design_name:
+ block_net_name = iterm.getMTerm().getName()
+ macro_top_inst = iterm.getInst()
+ MACRO_TOP_PLACEMENT_X, MACRO_TOP_PLACEMENT_Y = macro_top_inst.getLocation()
+ MACRO_TOP_PLACEMENT_ORIENT = macro_top_inst.getOrient()
+ print("Block net name: ", block_net_name)
+ break
+ if block_net_name is not None:
+ to_connect[block_net_name] = []
+ for iterm in iterms:
+ macro_name = iterm.getMTerm().getMaster().getName()
+ if macro_name != macro_design_name:
+ to_connect[block_net_name].append(iterm)
+ block_net_name = None
+
+ # print(macro_name, inst_name, end= ' ')
+ # print(iterm.getMTerm().getName())
+
+# print(to_connect)
+
+nets_macro = block_macro.getNets()
+created_macros = {}
+for net in nets_macro:
+ iterms = net.getITerms() # asssumption: no pins (bterms) on top level
+ if not keep_flag:
+ for iterm in iterms:
+ iterm.disconnect()
+ if net.getName() in to_connect:
+ for node_iterm in to_connect[net.getName()]:
+ node_master = node_iterm.getMTerm().getMaster()
+ node_inst = node_iterm.getInst()
+ node_inst_name = node_iterm.getInst().getName()
+ if node_inst_name not in created_macros:
+ created_macros[node_inst_name] = 1
+ print("Creating: ", node_master.getName(), node_inst_name)
+ new_inst = odb.dbInst_create(block_macro, node_master, node_inst_name)
+ new_inst.setOrient(node_inst.getOrient())
+ new_inst.setLocation(
+ node_inst.getLocation()[0] - MACRO_TOP_PLACEMENT_X,
+ node_inst.getLocation()[1] - MACRO_TOP_PLACEMENT_Y,
+ )
+ new_inst.setPlacementStatus("FIRM")
+ else:
+ new_inst = block_macro.findInst(node_inst_name)
+ new_inst.findITerm(node_iterm.getMTerm().getName()).connect(net)
+
+odb.write_def(block_macro, output_def_file_name)
diff --git a/openlane/scripts/count_lvs.py b/openlane/scripts/count_lvs.py
new file mode 100755
index 0000000..69564b0
--- /dev/null
+++ b/openlane/scripts/count_lvs.py
@@ -0,0 +1,133 @@
+#!/usr/bin/python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+#
+# ---------------------------------------------------------
+# LVS failure check
+#
+# This is a Python script that parses the comp.json
+# output from netgen and reports on the number of
+# errors in the top-level netlist.
+#
+# ---------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Pulled from qflow GUI as standalone script Aug 20, 2018
+# ---------------------------------------------------------
+
+import re
+import json
+import argparse
+
+
+def count_LVS_failures(filename):
+ with open(filename, "r") as cfile:
+ lvsdata = json.load(cfile)
+
+ # Count errors in the JSON file
+ failures = 0
+ devfail = 0
+ netfail = 0
+ pinfail = 0
+ propfail = 0
+ netdiff = 0
+ devdiff = 0
+ ncells = len(lvsdata)
+ for c in range(0, ncells):
+ cellrec = lvsdata[c]
+
+ if c == ncells - 1:
+ topcell = True
+ else:
+ topcell = False
+
+ # Most errors must only be counted for the top cell, because individual
+ # failing cells are flattened and the matching attempted again on the
+ # flattened netlist.
+
+ if topcell:
+ if "devices" in cellrec:
+ devices = cellrec["devices"]
+ devlist = [val for pair in zip(devices[0], devices[1]) for val in pair]
+ devpair = list(devlist[p : p + 2] for p in range(0, len(devlist), 2))
+ for dev in devpair:
+ c1dev = dev[0]
+ c2dev = dev[1]
+ diffdevs = abs(c1dev[1] - c2dev[1])
+ failures += diffdevs
+ devdiff += diffdevs
+
+ if "nets" in cellrec:
+ nets = cellrec["nets"]
+ diffnets = abs(nets[0] - nets[1])
+ failures += diffnets
+ netdiff += diffnets
+
+ if "badnets" in cellrec:
+ badnets = cellrec["badnets"]
+ failures += len(badnets)
+ netfail += len(badnets)
+
+ if "badelements" in cellrec:
+ badelements = cellrec["badelements"]
+ failures += len(badelements)
+ devfail += len(badelements)
+
+ if "pins" in cellrec:
+ pins = cellrec["pins"]
+ pinlist = [val for pair in zip(pins[0], pins[1]) for val in pair]
+ pinpair = list(pinlist[p : p + 2] for p in range(0, len(pinlist), 2))
+ for pin in pinpair:
+ # Avoid flagging global vs. local names, e.g., "gnd" vs. "gnd!,"
+ # and ignore case when comparing pins.
+ pin0 = re.sub("!$", "", pin[0].lower())
+ pin1 = re.sub("!$", "", pin[1].lower())
+ if pin0 != pin1:
+ # The text "(no pin)" indicates a missing pin that can be
+ # ignored because the pin in the other netlist is a no-connect
+ if pin0 != "(no pin)" and pin1 != "(no pin)":
+ failures += 1
+ pinfail += 1
+
+ # Property errors must be counted for every cell
+ if "properties" in cellrec:
+ properties = cellrec["properties"]
+ failures += len(properties)
+ propfail += len(properties)
+
+ return [failures, netfail, devfail, pinfail, propfail, netdiff, devdiff]
+
+
+if __name__ == "__main__":
+
+ parser = argparse.ArgumentParser(description="Parses netgen lvs")
+ parser.add_argument("--file", "-f", required=True)
+ args = parser.parse_args()
+ failures = count_LVS_failures(args.file)
+ total = failures[0]
+ if total > 0:
+ failed = True
+ print("LVS reports:")
+ print(" net count difference = " + str(failures[5]))
+ print(" device count difference = " + str(failures[6]))
+ print(" unmatched nets = " + str(failures[1]))
+ print(" unmatched devices = " + str(failures[2]))
+ print(" unmatched pins = " + str(failures[3]))
+ print(" property failures = " + str(failures[4]))
+ else:
+ print("LVS reports no net, device, pin, or property mismatches.")
+
+ print("")
+ print("Total errors = " + str(total))
diff --git a/openlane/scripts/cvc/sky130A/cdl.awk b/openlane/scripts/cvc/sky130A/cdl.awk
new file mode 100644
index 0000000..96c7c08
--- /dev/null
+++ b/openlane/scripts/cvc/sky130A/cdl.awk
@@ -0,0 +1,16 @@
+/Black-box entry subcircuit/ { # remove black-box defintions
+ while ( $1 != ".ends" ) {
+ getline;
+ }
+ getline;
+}
+/^\*/ { # remove comments
+ next;
+}
+/^.ENDS .*/ { # remove name from ends lines
+ print $1;
+ next;
+}
+ {
+ print $0;
+}
\ No newline at end of file
diff --git a/openlane/scripts/cvc/sky130A/cvc.sky130A.models b/openlane/scripts/cvc/sky130A/cvc.sky130A.models
new file mode 100644
index 0000000..cdbff13
--- /dev/null
+++ b/openlane/scripts/cvc/sky130A/cvc.sky130A.models
@@ -0,0 +1,53 @@
+MN nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8
+MP pfet_01v8_hvt Vth=-0.2 Vgs=1.8 Vds=1.8
+
+R short model=switch_on
+
+D sky130_fd_pr__diode_pw2nd_05v5
+D sky130_fd_pr__diode_pw2nd_11v0
+D sky130_fd_pr__diode_pd2nw_05v5
+D sky130_fd_pr__model__parasitic__diode_ps2dn
+D sky130_fd_pr__model__parasitic__diode_ps2nw
+D sky130_fd_pr__model__parasitic__diode_pw2dn
+D condiode
+
+
+#R sky130_fd_pr__res_generic_m1 R=l/w*0.125
+#R sky130_fd_pr__res_generic_m2 R=l/w*0.125
+#R sky130_fd_pr__res_generic_m3 R=l/w*0.047
+#R sky130_fd_pr__res_generic_m4 R=l/w*0.047
+#R sky130_fd_pr__res_generic_nd R=l/w*0.029
+R sky130_fd_pr__res_generic_m1 R=l/w
+R sky130_fd_pr__res_generic_m2 R=l/w
+R sky130_fd_pr__res_generic_m3 R=l/w
+R sky130_fd_pr__res_generic_m4 R=l/w
+R sky130_fd_pr__res_generic_m5 R=l/w
+R sky130_fd_pr__res_generic_nd R=l/w*120
+R sky130_fd_pr__res_generic_nd__hv R=l/w*114
+R sky130_fd_pr__res_generic_pd__hv R=l/w*191
+R sky130_fd_pr__res_generic_po R=l/w*48
+R sky130_fd_pr__res_xhigh_po R=l/w*2000
+R sky130_fd_pr__res_high_po R=l/w*2000
+
+MN sky130_fd_pr__nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8
+MN sky130_fd_pr__nfet_01v8_lvt Vth=0.1 Vgs=1.8 Vds=1.8
+MN sky130_fd_pr__special_nfet_latch Vth=0.2 Vgs=1.8 Vds=1.8
+MN sky130_fd_pr__nfet_03v3_nvt Vth=0.2 Vgs=3.3 Vds=3.3
+MN sky130_fd_pr__esd_nfet_g5v0d10v5 Vth=0.2
+MN sky130_fd_pr__nfet_05v0_nvt Vth=0.2
+MN sky130_fd_pr__nfet_g5v0d10v5 Vth=0.2
+MN sky130_fd_bs_flash__special_sonosfet_star Vth=0.2
+
+MP sky130_fd_pr__pfet_01v8 Vth=-0.2 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__pfet_01v8_lvt Vth=-0.1 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__special_pfet_pass Vth=-0.2 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__pfet_g5v0d10v5 Vth=-0.2
+
+C sky130_fd_pr__cap_mim_m3_1
+C sky130_fd_pr__cap_mim_m3_2
+C sky130_fd_pr__cap_var
+
+Q sky130_fd_pr__pnp_05v5
+
+
diff --git a/openlane/scripts/cvc/sky130A/cvcrc.sky130A b/openlane/scripts/cvc/sky130A/cvcrc.sky130A
new file mode 100644
index 0000000..420bbd4
--- /dev/null
+++ b/openlane/scripts/cvc/sky130A/cvcrc.sky130A
@@ -0,0 +1,36 @@
+
+CVC_MODEL_FILE = $SCRIPTS_DIR/cvc/$PDK/cvc.$PDK.models
+CVC_TOP = $DESIGN_NAME
+CVC_MODE = $CVC_TOP
+CVC_NETLIST = $signoff_tmpfiles/$DESIGN_NAME.cdl
+CVC_POWER_FILE = $signoff_tmpfiles/$CVC_TOP.power
+CVC_REPORT_FILE = $signoff_reports/$CVC_TOP.rpt
+CVC_FUSE_FILE = ''
+CVC_REPORT_TITLE = 'CVC $CVC_TOP'
+CVC_CIRCUIT_ERROR_LIMIT = '100'
+CVC_SEARCH_LIMIT = '100'
+CVC_LEAK_LIMIT = '0.0002'
+CVC_SOI = 'false'
+CVC_SCRC = 'false'
+CVC_VTH_GATES = 'false'
+CVC_MIN_VTH_GATES = 'false'
+CVC_IGNORE_VTH_FLOATING = 'false'
+CVC_IGNORE_NO_LEAK_FLOATING = 'false'
+CVC_LEAK_OVERVOLTAGE = 'true'
+CVC_LOGIC_DIODES = 'false'
+CVC_ANALOG_GATES = 'true'
+CVC_BACKUP_RESULTS = 'false'
+CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
+CVC_SHORT_ERROR_THRESHOLD = '0'
+CVC_BIAS_ERROR_THRESHOLD = '0'
+CVC_FORWARD_ERROR_THRESHOLD = '0'
+CVC_FLOATING_ERROR_THRESHOLD = '0'
+CVC_GATE_ERROR_THRESHOLD = '0'
+CVC_LEAK?_ERROR_THRESHOLD = '0'
+CVC_EXPECTED_ERROR_THRESHOLD = '0'
+CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
+CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
+CVC_CELL_ERROR_LIMIT_FILE = ''
+CVC_CELL_CHECKSUM_FILE = ''
+CVC_LARGE_CIRCUIT_SIZE = '10000000'
+CVC_NET_CHECK_FILE = ''
diff --git a/openlane/scripts/cvc/sky130A/power.awk b/openlane/scripts/cvc/sky130A/power.awk
new file mode 100644
index 0000000..5b3466e
--- /dev/null
+++ b/openlane/scripts/cvc/sky130A/power.awk
@@ -0,0 +1,15 @@
+BEGIN { # Print power and standard_input definitions
+ printf "%s power 1.8\n", vdd;
+ printf "%s power 0.0\n", gnd;
+ printf "#define std_input min@%s max@%s\n", gnd, vdd;
+}
+$1 == "input" { # Print input nets
+ gsub(/;/, "");
+ if ( $2 == vdd || $2 == gnd ) { # ignore power nets
+ next;
+ }
+ if ( NF == 3 ) { # print buses as net[range]
+ $2 = $3 $2;
+ }
+ print $2, "input std_input";
+}
\ No newline at end of file
diff --git a/openlane/scripts/defutil.py b/openlane/scripts/defutil.py
new file mode 100644
index 0000000..3ff5d68
--- /dev/null
+++ b/openlane/scripts/defutil.py
@@ -0,0 +1,604 @@
+# Copyright 2021 Efabless Corporation
+# Copyright 2022 Arman Avetisyan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import click
+
+import odb
+
+import os # For checks of file existance
+import shutil # For copy
+import sys # For stderr
+
+
+@click.group()
+def cli():
+ pass
+
+
+class OdbReader(object):
+ def __init__(self, lef_in, def_in):
+ self.db = odb.dbDatabase.create()
+
+ self.lef = odb.read_lef(self.db, lef_in)
+ self.sites = self.lef.getSites()
+
+ self.df = odb.read_def(self.db, def_in)
+ self.block = self.db.getChip().getBlock()
+ self.rows = self.block.getRows()
+ self.dbunits = self.block.getDefUnits()
+ self.nets = self.block.getNets()
+
+
+@click.command("extract_core_dims")
+@click.option("-o", "--output-data", required=True, help="Output")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("input_def")
+def extract_core_dims(output_data, input_lef, input_def):
+ reader = OdbReader(input_lef, input_def)
+ core_area = reader.block.getCoreArea()
+
+ with open(output_data, "w") as f:
+ print(
+ f"{core_area.dx() / reader.dbunits} {core_area.dy() / reader.dbunits}",
+ file=f,
+ )
+
+
+cli.add_command(extract_core_dims)
+
+
+@click.command("mark_component_fixed")
+@click.option(
+ "-c", "--cell-name", required=True, help="Cell name of the components to mark fixed"
+)
+@click.option("-o", "--output", default="./out.def")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("input_def")
+def mark_component_fixed(cell_name, output, input_lef, input_def):
+ reader = OdbReader(input_lef, input_def)
+ instances = reader.block.getInsts()
+ for instance in instances:
+ if instance.getMaster().getName() == cell_name:
+ instance.setPlacementStatus("FIRM")
+
+ assert odb.write_def(reader.block, output) == 1
+
+
+cli.add_command(mark_component_fixed)
+
+
+def merge_item_section(
+ item: str, def_one_str: str, def_two_str: str, replace_two: bool = False
+) -> str:
+ import re
+
+ section_start_rx = re.compile(rf"{item}\s+(\d+)\s*;\s*")
+ section_end_rx = re.compile(rf"END\s+{item}")
+
+ def_one_lines = def_one_str.splitlines()
+ def_two_lines = def_two_str.splitlines()
+
+ collecting = False
+ def_two_out_lines = []
+ def_two_count = 0
+ for line in def_two_lines:
+ start_match = section_start_rx.search(line)
+ end_match = section_end_rx.search(line)
+ if end_match is not None:
+ collecting = False
+ break
+ if collecting:
+ def_two_out_lines.append(line)
+ if start_match is not None:
+ def_two_count = int(start_match[1])
+ collecting = True
+
+ # assert(len(def_two_out_lines) == def_two_count) # sanity check
+ final_out_lines = []
+
+ def_one_count = 0
+ for line in def_one_lines:
+ start_match = section_start_rx.search(line)
+ end_match = section_end_rx.search(line)
+ if start_match is not None:
+ def_one_count = int(start_match[1])
+ final_count = def_one_count
+ if not replace_two:
+ final_count += def_two_count
+ final_out_lines.append(f"{item} {final_count} ;")
+ elif end_match is not None:
+ if not replace_two:
+ final_out_lines += def_two_out_lines
+ final_out_lines.append(f"END {item}")
+ else:
+ final_out_lines.append(line)
+
+ return "\n".join(final_out_lines)
+
+
+@click.command("merge_components")
+@click.option("-o", "--output", default="./out.def")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("def_one")
+@click.argument("def_two")
+def merge_components(output, input_lef, def_one, def_two):
+ # TODO: Rewrite in OpenDB if possible
+ def_one_str = open(def_one).read()
+ def_two_str = open(def_two).read()
+
+ with open(output, "w") as f:
+ f.write(merge_item_section("COMPONENTS", def_one_str, def_two_str))
+
+
+cli.add_command(merge_components)
+
+
+@click.command("merge_pins")
+@click.option("-o", "--output", default="./out.def")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("def_one")
+@click.argument("def_two")
+def merge_pins(output, input_lef, def_one, def_two):
+ # TODO: Rewrite in OpenDB if possible
+ def_one_str = open(def_one).read()
+ def_two_str = open(def_two).read()
+
+ with open(output, "w") as f:
+ f.write(merge_item_section("PINS", def_one_str, def_two_str))
+
+
+@click.command("move_diearea")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.option(
+ "-o",
+ "--output-def",
+ required=True,
+ help="Output DEF. File should exist. Die area will be applied to this DEF",
+)
+@click.option("-i", "--template-def", required=True, help="Input DEF")
+def move_diearea_command(input_lef, output_def, template_def):
+ """
+ Move die area from input def to output def
+ """
+ move_diearea(input_lef, output_def, template_def)
+
+
+def move_diearea(input_lef, output_def, template_def):
+ if not os.path.isfile(template_def):
+ print("LEF file ", input_lef, " not found")
+ raise FileNotFoundError
+ if not os.path.isfile(template_def):
+ print("Input DEF file ", template_def, " not found")
+ raise FileNotFoundError
+ if not os.path.isfile(output_def):
+ print("Output DEF file ", output_def, " not found")
+ raise FileNotFoundError
+
+ source_db = odb.dbDatabase.create()
+ destination_db = odb.dbDatabase.create()
+ odb.read_lef(source_db, input_lef)
+ odb.read_lef(destination_db, input_lef)
+
+ odb.read_def(source_db, template_def)
+ odb.read_def(destination_db, output_def)
+
+ assert (
+ source_db.getTech().getManufacturingGrid()
+ == destination_db.getTech().getManufacturingGrid()
+ )
+ assert (
+ source_db.getTech().getDbUnitsPerMicron()
+ == destination_db.getTech().getDbUnitsPerMicron()
+ )
+
+ diearea = source_db.getChip().getBlock().getDieArea()
+ output_block = destination_db.getChip().getBlock()
+ output_block.setDieArea(diearea)
+ # print("Applied die area: ", destination_db.getChip().getBlock().getDieArea().ur(), destination_db.getChip().getBlock().getDieArea().ll(), file=sys.stderr)
+
+ assert odb.write_def(output_block, output_def) == 1
+
+
+def check_pin_grid(
+ manufacturing_grid, dbu_per_microns, pin_name, pin_coordinate, logfile
+):
+ if (pin_coordinate % manufacturing_grid) != 0:
+ print(
+ "[ERROR]: Pin coordinate",
+ pin_coordinate,
+ "for pin",
+ pin_name,
+ "does not match the manufacturing grid",
+ file=sys.stderr,
+ )
+ print(
+ "[ERROR]: Pin coordinate",
+ pin_coordinate,
+ "for pin",
+ pin_name,
+ "does not match the manufacturing grid",
+ file=logfile,
+ ) # IDK how to do this
+ return True
+
+
+# openroad -python scripts/defutil.py replace_pins -o output.def -l designs/def_test/runs/RUN_2022.01.30_12.32.26/tmp/merged.lef designs/def_test/runs/RUN_2022.01.30_12.32.26/tmp/floorplan/4-io.def designs/def_test/def_test.def
+
+
+@click.command("replace_pins")
+@click.option("-o", "--output-def", default="./out.def", help="Destination DEF path")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.option("-lg", "--log", "logpath", help="Log output file")
+@click.argument("source_def")
+@click.argument("template_def")
+def replace_pins_command(output_def, input_lef, logpath, source_def, template_def):
+ """
+ Copies source_def to output, then if same pin exists in template def and first def then, it's written to output def
+
+ Example to run:
+ openroad -python scripts/defutil.py replace_pins -o output.def -l designs/def_test/runs/RUN_2022.01.30_12.32.26/tmp/merged.lef designs/def_test/runs/RUN_2022.01.30_12.32.26/tmp/floorplan/4-io.def designs/def_test/def_test.def --log defutil.log
+ Note: Assumes that all pins are on metal layers and via pins dont exist.
+ Note: It assumes that all pins are rectangles, not polygons.
+ Note: This tool assumes no power pins exist in template def.
+ Note: It should leave pins in source_def as-is if no pin in template def is found.
+ Note: It assumes only one port with the same name exist.
+ Note: It assumes that pin names matches the net names in template DEF.
+ """
+ replace_pins(output_def, input_lef, logpath, source_def, template_def)
+
+
+cli.add_command(replace_pins_command)
+
+# Note: If you decide to change any parameters, also change replace_pins_command's
+def replace_pins(output_def, input_lef, logpath, source_def, template_def):
+ # --------------------------------
+ # 0. Sanity check: Check for all defs and lefs to exist
+ # I removed the output def to NOT exist check, as it was making testing harder
+ # --------------------------------
+
+ if not os.path.isfile(input_lef):
+ print("LEF file ", input_lef, " not found")
+ raise FileNotFoundError
+ if not os.path.isfile(source_def):
+ print("First DEF file ", source_def, " not found")
+ raise FileNotFoundError
+ if not os.path.isfile(template_def):
+ print("Template DEF file ", template_def, " not found")
+ raise FileNotFoundError
+ if logpath is None:
+ logfile = sys.stdout
+ else:
+ logfile = open(logpath, "w+")
+
+ # --------------------------------
+ # 1. Copy the one def to second
+ # --------------------------------
+ print(
+ "[defutil.py:replace_pins] Creating output DEF based on first DEF", file=logfile
+ )
+ shutil.copy(source_def, output_def)
+
+ # --------------------------------
+ # 2. Find list of all bterms in first def
+ # --------------------------------
+ source_db = odb.dbDatabase.create()
+ odb.read_lef(source_db, input_lef)
+ odb.read_def(source_db, source_def)
+ source_bterms = source_db.getChip().getBlock().getBTerms()
+
+ manufacturing_grid = source_db.getTech().getManufacturingGrid()
+ dbu_per_microns = source_db.getTech().getDbUnitsPerMicron()
+
+ print(
+ "Using manufacturing grid:",
+ manufacturing_grid,
+ "Using dbu per mircons: ",
+ dbu_per_microns,
+ file=logfile,
+ )
+
+ all_bterm_names = set()
+
+ for source_bterm in source_bterms:
+ source_name = source_bterm.getName()
+ # TODO: Check for pin name matches net name
+ # print("Bterm", source_name, "is declared as", source_bterm.getSigType())
+
+ # --------------------------------
+ # 3. Check no bterms should be marked as power, because it is assumed that caller already removed them
+ # --------------------------------
+ if (source_bterm.getSigType() == "POWER") or (
+ source_bterm.getSigType() == "GROUND"
+ ):
+ print(
+ "Bterm",
+ source_name,
+ "is declared as",
+ source_bterm.getSigType(),
+ "ignoring it",
+ file=logfile,
+ )
+ continue
+ all_bterm_names.add(source_name)
+
+ print(
+ "[defutil.py:replace_pins] Found",
+ len(all_bterm_names),
+ "block terminals in first def",
+ file=logfile,
+ )
+
+ # --------------------------------
+ # 4. Read the template def
+ # --------------------------------
+ template_db = odb.dbDatabase.create()
+ odb.read_lef(template_db, input_lef)
+ odb.read_def(template_db, template_def)
+ template_bterms = template_db.getChip().getBlock().getBTerms()
+
+ assert (
+ source_db.getTech().getManufacturingGrid()
+ == template_db.getTech().getManufacturingGrid()
+ )
+ assert (
+ source_db.getTech().getDbUnitsPerMicron()
+ == template_db.getTech().getDbUnitsPerMicron()
+ )
+ # --------------------------------
+ # 5. Create a dict with net -> pin location. Check for only one pin location to exist, overwise return an error
+ # --------------------------------
+ template_bterm_locations = dict()
+
+ for template_bterm in template_bterms:
+ template_name = template_bterm.getName()
+ template_pins = template_bterm.getBPins()
+
+ # TODO: Check for pin name matches net name
+ for template_pin in template_pins:
+ boxes = template_pin.getBoxes()
+
+ for box in boxes:
+ layer = box.getTechLayer().getName()
+ if template_name not in template_bterm_locations:
+ template_bterm_locations[template_name] = []
+ template_bterm_locations[template_name].append(
+ (
+ layer,
+ box.xMin(),
+ box.yMin(),
+ box.xMax(),
+ box.yMax(),
+ )
+ )
+
+ print(
+ "[defutil.py:replace_pins] Found template_bterms: ",
+ len(template_bterm_locations),
+ file=logfile,
+ )
+
+ for template_bterm_name in template_bterm_locations:
+ print(
+ template_bterm_name,
+ ": ",
+ template_bterm_locations[template_bterm_name],
+ file=logfile,
+ )
+
+ # --------------------------------
+ # 6. Modify the pins in out def, according to dict
+ # --------------------------------
+ output_db = odb.dbDatabase.create()
+ odb.read_lef(output_db, input_lef)
+ odb.read_def(output_db, output_def)
+ output_tech = output_db.getTech()
+ output_block = output_db.getChip().getBlock()
+ output_bterms = output_block.getBTerms()
+ grid_errors = False
+ for output_bterm in output_bterms:
+ name = output_bterm.getName()
+ output_bpins = output_bterm.getBPins()
+
+ if name in template_bterm_locations and name in all_bterm_names:
+ for output_bpin in output_bpins:
+ odb.dbBPin.destroy(output_bpin)
+
+ for template_bterm_location_tuple in template_bterm_locations[name]:
+ layer = output_tech.findLayer(template_bterm_location_tuple[0])
+
+ # --------------------------------
+ # 6.2 Create new pin
+ # --------------------------------
+
+ output_new_bpin = odb.dbBPin.create(output_bterm)
+
+ print(
+ "For:",
+ name,
+ "Wrote on layer:",
+ layer.getName(),
+ "coordinates: ",
+ template_bterm_location_tuple[1],
+ template_bterm_location_tuple[2],
+ template_bterm_location_tuple[3],
+ template_bterm_location_tuple[4],
+ file=logfile,
+ )
+ grid_errors = (
+ check_pin_grid(
+ manufacturing_grid,
+ dbu_per_microns,
+ name,
+ template_bterm_location_tuple[1],
+ logfile,
+ )
+ or grid_errors
+ )
+ grid_errors = (
+ check_pin_grid(
+ manufacturing_grid,
+ dbu_per_microns,
+ name,
+ template_bterm_location_tuple[2],
+ logfile,
+ )
+ or grid_errors
+ )
+ grid_errors = (
+ check_pin_grid(
+ manufacturing_grid,
+ dbu_per_microns,
+ name,
+ template_bterm_location_tuple[3],
+ logfile,
+ )
+ or grid_errors
+ )
+ grid_errors = (
+ check_pin_grid(
+ manufacturing_grid,
+ dbu_per_microns,
+ name,
+ template_bterm_location_tuple[4],
+ logfile,
+ )
+ or grid_errors
+ )
+ odb.dbBox.create(
+ output_new_bpin,
+ layer,
+ template_bterm_location_tuple[1],
+ template_bterm_location_tuple[2],
+ template_bterm_location_tuple[3],
+ template_bterm_location_tuple[4],
+ )
+ output_new_bpin.setPlacementStatus("PLACED")
+ else:
+ print(
+ "[defutil.py:replace_pins] Not found",
+ name,
+ "in template def, but found in output def. Leaving as-is",
+ file=logfile,
+ )
+
+ if grid_errors:
+ sys.exit("[ERROR]: Grid errors happened. Check log for grid errors.")
+ # --------------------------------
+ # 7. Write back the output def
+ # --------------------------------
+ print("[defutil.py:replace_pins] Writing output def to: ", output_def, file=logfile)
+ assert odb.write_def(output_block, output_def) == 1
+
+
+@click.command("remove_components")
+@click.option(
+ "--rx/--not-rx", default=True, help="Treat instance name as a regular expression"
+)
+@click.option(
+ "-n",
+ "--instance-name",
+ default=".+",
+ help="Instance name to be removed (Default '.+', as a regular expression, removes everything.)",
+)
+@click.option("-o", "--output", default="./out.def")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("input_def")
+def remove_components(rx, instance_name, output, input_lef, input_def):
+ reader = OdbReader(input_lef, input_def)
+ matcher = re.compile(instance_name if rx else f"^{re.escape(instance_name)}$")
+ instances = reader.block.getInsts()
+ for instance in instances:
+ name = instance.getName()
+ name_m = matcher.search(name)
+ if name_m is not None:
+ odb.dbInst.destroy(instance)
+
+ assert odb.write_def(reader.block, output) == 1
+
+
+cli.add_command(remove_components)
+
+
+@click.command("remove_nets")
+@click.option(
+ "--rx/--not-rx", default=True, help="Treat net name as a regular expression"
+)
+@click.option(
+ "-n",
+ "--net-name",
+ default=".+",
+ help="Net name to be removed (Default '.+', as a regular expression, removes everything.)",
+)
+@click.option("-o", "--output", default="./out.def")
+@click.option(
+ "--empty-only", is_flag=True, default=False, help="Only remove empty nets."
+)
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("input_def")
+def remove_nets(rx, net_name, output, empty_only, input_lef, input_def):
+ reader = OdbReader(input_lef, input_def)
+ matcher = re.compile(net_name if rx else f"^{re.escape(net_name)}$")
+ nets = reader.block.getNets()
+ for net in nets:
+ name = net.getName()
+ name_m = matcher.search(name)
+ if name_m is not None:
+ if empty_only and len(net.getITerms()) > 0:
+ continue
+ # BTerms = PINS, if it has a pin we need to keep the net
+ if len(net.getBTerms()) > 0:
+ for port in net.getITerms():
+ odb.dbITerm.disconnect(port)
+ else:
+ odb.dbNet.destroy(net)
+
+ assert odb.write_def(reader.block, output) == 1
+
+
+cli.add_command(remove_nets)
+
+
+@click.command("remove_pins")
+@click.option(
+ "--rx/--not-rx", default=True, help="Treat pin name as a regular expression"
+)
+@click.option(
+ "-n",
+ "--pin-name",
+ default=".+",
+ help="Pin name to be removed (Default '.+', as a regular expression, removes everything.)",
+)
+@click.option("-o", "--output", default="./out.def")
+@click.option("-l", "--input-lef", required=True, help="Merged LEF file")
+@click.argument("input_def")
+def remove_pins(rx, pin_name, output, input_lef, input_def):
+ reader = OdbReader(input_lef, input_def)
+ matcher = re.compile(pin_name if rx else f"^{re.escape(pin_name)}$")
+ pins = reader.block.getBTerms()
+ for pin in pins:
+ name = pin.getName()
+ name_m = matcher.search(name)
+ if name_m is not None:
+ odb.dbBTerm.destroy(pin)
+
+ assert odb.write_def(reader.block, output) == 1
+
+
+cli.add_command(remove_pins)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/dont_buffer.py b/openlane/scripts/dont_buffer.py
new file mode 100644
index 0000000..fc84513
--- /dev/null
+++ b/openlane/scripts/dont_buffer.py
@@ -0,0 +1,137 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+
+import odb
+
+
+def remove_buffers(block_design, dont_buffer):
+ design_nets = block_design.getNets()
+ dont_buffer_nets = [net for net in design_nets if net.getConstName() in dont_buffer]
+
+ for net in dont_buffer_nets:
+ # get the cells driving the dont buffer net
+ master_cells = get_master_cells(net)
+
+ assert (
+ len(master_cells) == 1
+ ), f"Net {net.getConstName()} is driven by multiple cells."
+
+ cell_name = master_cells[0].getMaster().getConstName()
+ assert (
+ "buf" in cell_name
+ ), f"{net.getConstName()} isn't driven by a buffer cell. It is driven by {cell_name}. "
+
+ # get the net connected to the input pin of this buffer
+ input_nets, output_nets = get_nets(master_cells[0])
+
+ assert (
+ len(output_nets) == 1
+ ), f"{cell_name} has more than one output port. Please make sure that {cell_name} is a buffer cell."
+ assert (
+ len(input_nets) == 1
+ ), f"{cell_name} has more than one input port. Please make sure that {cell_name} is a buffer cell."
+ assert (
+ output_nets[0].getConstName() in dont_buffer
+ ), f"{cell_name} isn't driving any of the dont buffer nets."
+
+ # remove the buffer cell instance
+ master_cells[0].destroy(master_cells[0])
+
+ # connect buffer cell input net to the dont buffer port
+ for input_net in input_nets:
+ input_net_master_cell = get_master_cells(input_net)[0]
+ _, output_nets_2 = get_nets(input_net_master_cell)
+ output_net_it = output_nets_2[0].getITerms()[0]
+ output_net_it.connect(net)
+
+
+def get_master_cells(net):
+ master_cells = []
+ for it in net.getITerms():
+ master_instance = it.getInst().getMaster()
+ master_cells.append(it.getInst())
+ cell_type = master_instance.getConstName()
+ cell_pin = it.getMTerm().getConstName()
+ print(f"Net {net.getConstName()} is connected to {cell_type}, pin {cell_pin}")
+
+ return master_cells
+
+
+def get_nets(master_instance):
+ input_nets = []
+ output_nets = []
+ for iterm in master_instance.getITerms():
+ if iterm.isSpecial(): # Skip special nets
+ continue
+
+ if iterm.isInputSignal():
+ input_pin_net = iterm.getNet()
+ input_nets.append(input_pin_net)
+
+ if iterm.isOutputSignal():
+ output_pin_net = iterm.getNet()
+ output_nets.append(output_pin_net)
+
+ return input_nets, output_nets
+
+
+def main():
+ parser = argparse.ArgumentParser(description="DEF to Liberty.")
+
+ parser.add_argument(
+ "--input_lef",
+ "-l",
+ nargs="+",
+ type=str,
+ default=None,
+ required=True,
+ help="Input LEF file(s)",
+ )
+ parser.add_argument(
+ "--input_def", "-i", required=True, help="DEF view of the design."
+ )
+ parser.add_argument("--output_def", "-o", required=True, help="Output DEF file")
+ parser.add_argument(
+ "--dont_buffer", "-d", required=True, help="Dont Buffer list of output ports."
+ )
+
+ args = parser.parse_args()
+ input_lef_files = args.input_lef
+ input_def_file = args.input_def
+ output_def = args.output_def
+ dont_buffer_list = args.dont_buffer
+
+ # parse input def/lef files
+ db_design = odb.dbDatabase.create()
+
+ for lef in input_lef_files:
+ odb.read_lef(db_design, lef)
+
+ odb.read_def(db_design, input_def_file)
+
+ chip_design = db_design.getChip()
+ block_design = chip_design.getBlock()
+
+ # remove buffers connected to the dont buffer nets
+ remove_buffers(block_design, dont_buffer_list)
+
+ # write output def
+ odb.write_def(block_design, output_def)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/openlane/scripts/extract_antenna_count.py b/openlane/scripts/extract_antenna_count.py
new file mode 100644
index 0000000..d7fbe9e
--- /dev/null
+++ b/openlane/scripts/extract_antenna_count.py
@@ -0,0 +1,6 @@
+#!/usr/bin/env python3
+import re
+import sys
+
+in_data = sys.stdin.read()
+print(re.findall(r"[Aa]ntenna violations:\s*(\d+)", in_data)[-1], end="")
diff --git a/openlane/scripts/extract_antenna_violators.py b/openlane/scripts/extract_antenna_violators.py
new file mode 100644
index 0000000..c78670f
--- /dev/null
+++ b/openlane/scripts/extract_antenna_violators.py
@@ -0,0 +1,53 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import re
+
+parser = argparse.ArgumentParser(
+ description="extracts the list of violating nets from an ARC report file"
+)
+
+parser.add_argument("--report", "-i", required=True, help="report file")
+
+parser.add_argument(
+ "--output", "-o", required=True, help="output file to store results"
+)
+
+args = parser.parse_args()
+report_file_name = args.report
+out_file_name = args.output
+
+pattern = re.compile(r"\s*([\S+]+)\s*\([\S+]+\)\s*[\S+]+")
+
+vios_list = []
+current_net = ""
+printed = False
+
+with open(report_file_name, "r") as f:
+ for line in f:
+ m = pattern.match(line)
+ if m:
+ current_net = m.group(1)
+ printed = False
+
+ if "*" in line and not printed:
+ print(current_net)
+ vios_list.append(current_net + " ")
+ printed = True
+
+
+outFileOpener = open(out_file_name, "w")
+outFileOpener.write(" ".join(vios_list))
+outFileOpener.close()
diff --git a/openlane/scripts/extract_metal_layers.py b/openlane/scripts/extract_metal_layers.py
new file mode 100644
index 0000000..0812138
--- /dev/null
+++ b/openlane/scripts/extract_metal_layers.py
@@ -0,0 +1,53 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import click
+from typing import List
+
+
+def extract_metal_layers(techlef_str: str) -> List[str]:
+ printed = False
+ metal_list = []
+ current_layer_name = ""
+
+ pattern = re.compile(r"\s*LAYER\s*([\S+]+)\s*")
+
+ for line in techlef_str.split("\n"):
+ m = pattern.match(line)
+ if m:
+ current_layer_name = m.group(1)
+ printed = False
+
+ if "ROUTING" in line and not printed:
+ metal_list.append(current_layer_name + " ")
+ printed = True
+
+ return metal_list
+
+
+@click.command()
+@click.option("--output", "-o", default="/dev/stdout", help="Output file.")
+@click.argument("techlef")
+def cli(output, techlef):
+ techlef_str = open(techlef).read()
+
+ metal_list = extract_metal_layers(techlef_str)
+
+ with open(output, "w") as f:
+ f.write(" ".join(metal_list).strip())
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/fake_diode_replace.py b/openlane/scripts/fake_diode_replace.py
new file mode 100644
index 0000000..2a81e19
--- /dev/null
+++ b/openlane/scripts/fake_diode_replace.py
@@ -0,0 +1,78 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import argparse
+
+
+# for i in range(len(sys.argv)):
+
+parser = argparse.ArgumentParser(
+ description="Replaces fake diodes with real diodes based on the violating cells/pins"
+)
+
+parser.add_argument("--defFile", "-d", required=True, help="Input DEF")
+
+parser.add_argument(
+ "--viosFile",
+ "-v",
+ required=True,
+ help="vios.txt containing white space separated cells that cause antenna violations",
+)
+
+parser.add_argument(
+ "--fakeDiode", "-f", required=True, help="the name of the fake diode"
+)
+parser.add_argument(
+ "--trueDiode", "-t", required=True, help="the name of the true diode"
+)
+
+args = parser.parse_args()
+
+viosFile = args.viosFile
+defFile = args.defFile
+
+fakeDiode = args.fakeDiode
+trueDiode = args.trueDiode
+
+
+tmpFile = open(viosFile, "r")
+if tmpFile.mode == "r":
+ listOfVios = tmpFile.read().split()
+tmpFile.close()
+
+tmpFile = open(defFile, "r")
+if tmpFile.mode == "r":
+ defContent = tmpFile.read().split("\n")
+tmpFile.close()
+
+exitFlag = False
+for i in range(len(defContent)):
+ if defContent[i].find("COMPONENTS") != -1:
+ if exitFlag:
+ break
+ else:
+ exitFlag = True
+ continue
+
+ antennaPos = defContent[i].find("ANTENNA_")
+ if antennaPos != -1:
+ cell = re.findall(r"- ANTENNA_(\S+)_.* " + fakeDiode + ".*", defContent[i])
+ if len(cell) >= 1:
+ if cell[0] in listOfVios:
+ defContent[i] = defContent[i].replace(fakeDiode, trueDiode)
+
+tmpFile = open(defFile, "w")
+tmpFile.write("\n".join(defContent))
+tmpFile.close()
diff --git a/openlane/scripts/gen_insert_buffer.py b/openlane/scripts/gen_insert_buffer.py
new file mode 100644
index 0000000..046fcae
--- /dev/null
+++ b/openlane/scripts/gen_insert_buffer.py
@@ -0,0 +1,150 @@
+# Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import argparse
+import os
+import odb
+from collections import defaultdict
+import math
+
+parser = argparse.ArgumentParser(
+ description="Converts a 23-spef_extraction_multi_corner_sta.min.rpt file to a eco insert buffer tcl file."
+)
+
+parser.add_argument(
+ "--skip_pin", "-s", type=int, required=True, help="skip input ouput cases"
+)
+parser.add_argument(
+ "--input_file",
+ "-i",
+ required=True,
+ help="input 23-spef_extraction_multi_corner_sta.min.rpt",
+)
+parser.add_argument(
+ "--lef_file", "-l", required=True, help="input lef file to load design"
+)
+parser.add_argument(
+ "--def_file", "-d", required=True, help="input def file for detailed information"
+)
+parser.add_argument("--output_file", "-o", required=True, help="output eco_fix.tcl")
+
+args = parser.parse_args()
+input_file = args.input_file
+output_file = args.output_file
+def_file = args.def_file
+lef_file = args.lef_file
+skip_pin = args.skip_pin
+
+splitLine = "\n\n\n"
+printArr = []
+
+
+db = odb.dbDatabase.create()
+print(def_file)
+odb.read_lef(db, lef_file)
+odb.read_def(db, os.path.join(def_file)) # get db from the file
+chip = db.getChip()
+block = chip.getBlock()
+insts = block.getInsts()
+insts_pin = block.getBTerms() # pins boundary
+
+vio_dict = defaultdict(list)
+
+# iteration to find minus slack
+# create insert_buffer command
+# Converting Magic DRC
+if os.path.exists(input_file):
+ drcFileOpener = open(input_file)
+ if drcFileOpener.mode == "r":
+ drcContent = drcFileOpener.read()
+ drcFileOpener.close()
+
+ # design name
+ # violation message
+ # list of violations
+ # Total Count:
+ vio_count = 0
+ if drcContent is not None:
+ drcSections = drcContent.split(splitLine)
+ # if (len(drcSections) > 2):
+ for i in range(0, len(drcSections)):
+ vio_name = drcSections[i].strip()
+ report_end_str = re.search("min_report_end", vio_name)
+ if report_end_str is not None:
+ print("report is incomplete")
+ break
+ minus_time_str = re.search(
+ r"([0-9]+\.[0-9]+) +slack +\(VIOLATED\)", vio_name
+ )
+ if minus_time_str is not None:
+ # vio_count += 1
+ start_point_str = re.search(r"Startpoint: (.*?)[ \n]", vio_name)
+ if start_point_str is not None:
+ start_point = start_point_str.group(1)
+ # FF
+ pin_name = ""
+ for inst in insts:
+ # find the pin inside inst
+ if inst.getName() == start_point:
+ for iterm in inst.getITerms(): # instance pin
+ mterm = iterm.getMTerm() # mterm get the information
+ if mterm.getIoType() == "OUTPUT":
+ printArr.append(
+ "# Found SP: "
+ + start_point
+ + "mterm: "
+ + mterm.getName()
+ )
+ pin_name = start_point + "/" + mterm.getName()
+ pin_type = "ITerm"
+ # master = inst.getMaster()
+ vio_dict[pin_name + " " + pin_type].append(
+ float(minus_time_str.group(1))
+ )
+ break
+ # pin
+ if pin_name == "" and skip_pin == 0:
+ pin_name = start_point
+ pin_type = "BTerm"
+ # continue
+ vio_dict[pin_name + " " + pin_type].append(
+ float(minus_time_str.group(1))
+ )
+
+ eco_iter = os.environ["ECO_ITER"]
+ for pin_unq in vio_dict.keys():
+ insert_times = math.floor(
+ abs(min(vio_dict[pin_unq])) / 0.5
+ ) # insert buffer conservatively
+ if insert_times < 1:
+ insert_times = 1
+
+ for i in range(0, insert_times):
+ vio_count += 1
+ print("insert multiple buffers: ", insert_times + 1)
+ insert_buffer_line = f"insert_buffer {pin_unq} sky130_fd_sc_hd__dlygate4sd3_1 net_HOLD_NET_{eco_iter}_{vio_count} U_HOLD_FIX_BUF_{eco_iter}_{vio_count}"
+ printArr.append(insert_buffer_line)
+ print(insert_buffer_line)
+
+ if vio_count == 0:
+ insert_buffer_line = "No violations found"
+ printArr.append(insert_buffer_line)
+else:
+ printArr.append("Source not found.")
+
+# write into file
+outputFileOpener = open(output_file, "w")
+outputFileOpener.write("\n".join(printArr))
+outputFileOpener.close()
diff --git a/openlane/scripts/gen_report_routing.py b/openlane/scripts/gen_report_routing.py
new file mode 100644
index 0000000..fb4f80e
--- /dev/null
+++ b/openlane/scripts/gen_report_routing.py
@@ -0,0 +1,38 @@
+# Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+from config.config import ConfigHandler
+from report.report_routing import Report
+
+parser = argparse.ArgumentParser(
+ description="Creates reports after routing phase is concluded"
+)
+
+parser.add_argument("--design", "-d", required=True, help="Design Path")
+
+parser.add_argument("--design_name", "-n", required=True, help="Design Name")
+
+parser.add_argument("--tag", "-t", required=True, help="Run Tag")
+
+parser.add_argument("--run_path", "-r", default=None, help="Run Path")
+
+args = parser.parse_args()
+design = args.design
+design_name = args.design_name
+tag = args.tag
+run_path = args.run_path
+
+params = ConfigHandler.get_config(design, tag, run_path)
+Report(design, tag, design_name, params, run_path).reports_from_logs()
diff --git a/openlane/scripts/generate_reports.py b/openlane/scripts/generate_reports.py
new file mode 100644
index 0000000..32aece9
--- /dev/null
+++ b/openlane/scripts/generate_reports.py
@@ -0,0 +1,173 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# The only purpose of this file is to create a wrapper around report.py and config.py and make them usable by flow.tcl
+
+import os
+import click
+
+import utils.utils as utils
+
+from report.report import Report
+from report.get_file_name import get_name
+
+from config.config import ConfigHandler
+
+
+@click.command()
+@click.option("--design", "-d", required=True, help="Design Path")
+@click.option("--design_name", "-n", required=True, help="Design Name")
+@click.option("--tag", "-t", required=True, help="Run Tag")
+@click.option(
+ "--run_path",
+ "-r",
+ default=None,
+ help="Run Path [Optional, otherwise derived from tag]",
+)
+@click.option("--output_file", "-o", required=True, help="Output Final Summary Report")
+@click.option(
+ "--man_report", "-m", default="/dev/null", help="Output Manufacturability Reports"
+)
+def cli(design, design_name, tag, run_path, output_file, man_report):
+ """
+ Creates manufacturability and metric summary reports for a given design and OpenLane run.
+ """
+ # Extracting Configurations
+ params = ConfigHandler.get_config(design, tag, run_path)
+
+ # Extracting Report
+ report = Report(design, tag, design_name, params, run_path).get_report()
+
+ # Write into file
+ with open(output_file, "w") as f:
+ f.write(Report.get_header() + "," + ConfigHandler.get_header())
+ f.write("\n")
+ f.write(report)
+
+ # Adding Extra Attributes computed from configs and reported statistics
+ utils.add_computed_statistics(output_file)
+
+ # Tracking Magic DRC, LVS, Antenna Logs:
+ run_path = run_path or utils.get_run_path(design, tag)
+
+ _, magic_antenna_report = get_name(
+ os.path.join(run_path, "reports", "routing"), "antenna_violators.rpt"
+ )
+ _, arc_antenna_report = get_name(
+ os.path.join(run_path, "reports", "signoff"), "antenna.rpt"
+ )
+ _, magic_drc_report = get_name(
+ os.path.join(run_path, "reports", "signoff"), "drc.rpt"
+ )
+ _, lvs_report = get_name(
+ os.path.join(run_path, "logs", "signoff"), f"{design_name}.lvs.lef.log"
+ )
+
+ printArr = []
+
+ printArr.append("Design Name: " + design_name)
+ printArr.append("Run Directory: " + str(run_path))
+
+ splitLine = "----------------------------------------"
+
+ # Summarizing Magic DRC
+ drcVioDict = dict()
+ cnt = 0
+ if os.path.exists(magic_drc_report):
+ drcFileOpener = open(magic_drc_report)
+ if drcFileOpener.mode == "r":
+ drcContent = drcFileOpener.read()
+ drcFileOpener.close()
+
+ # design name
+ # violation message
+ # list of violations
+ # Total Count:
+ printArr.append(splitLine)
+ printArr.append("\nMagic DRC Summary:")
+ printArr.append("Source: " + str(magic_drc_report))
+ if drcContent is not None:
+ drcSections = drcContent.split(splitLine)
+ if len(drcSections) > 2:
+ for i in range(1, len(drcSections) - 1, 2):
+ drcVioDict[drcSections[i]] = len(drcSections[i + 1].split("\n")) - 2
+ for key in drcVioDict:
+ val = drcVioDict[key]
+ cnt += val
+ printArr.append(
+ 'Violation Message "'
+ + str(key.strip())
+ + ' "found '
+ + str(val)
+ + " Times."
+ )
+ printArr.append("Total Magic DRC violations is " + str(cnt))
+ else:
+ printArr.append("Source not found.")
+ # Summarizing LVS
+ printArr.append(splitLine)
+ printArr.append("\nLVS Summary:")
+ printArr.append("Source: " + str(lvs_report))
+ if os.path.exists(lvs_report):
+ lvsFileOpener = open(lvs_report)
+ if lvsFileOpener.mode == "r":
+ lvsContent = lvsFileOpener.read()
+ lvsFileOpener.close()
+ flag = False
+ for line in lvsContent.split("\n"):
+ if line.find("Total errors =") != -1:
+ flag = True
+ printArr.append(line)
+ elif line.find("net") != -1:
+ printArr.append(line)
+
+ if not flag:
+ printArr.append("Design is LVS clean.")
+ else:
+ printArr.append("Source not found.")
+
+ # Summarizing Antennas
+ printArr.append(splitLine)
+ printArr.append("\nAntenna Summary:")
+
+ if os.path.exists(arc_antenna_report):
+ printArr.append("Source: " + str(arc_antenna_report))
+ antFileOpener = open(arc_antenna_report)
+ if antFileOpener.mode == "r":
+ antContent = antFileOpener.read().split("\n")[-5:]
+ antFileOpener.close()
+ for line in antContent:
+ if line.find("violated:") != -1:
+ printArr.append(line)
+ elif os.path.exists(magic_antenna_report):
+ printArr.append("Source: " + str(magic_antenna_report))
+ antFileOpener = open(magic_antenna_report)
+ if antFileOpener.mode == "r":
+ antContent = antFileOpener.read().split("\n")
+ antFileOpener.close()
+ tot_cnt = 0
+ for ant in antContent:
+ if len(str(ant).strip()):
+ tot_cnt += 1
+ printArr.append("Number of pins violated: " + str(tot_cnt))
+ else:
+ printArr.append("No antenna report found.")
+
+ # write into file
+ with open(man_report, "w") as f:
+ f.write("\n".join(printArr))
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/io_place.py b/openlane/scripts/io_place.py
new file mode 100644
index 0000000..6dbcf01
--- /dev/null
+++ b/openlane/scripts/io_place.py
@@ -0,0 +1,394 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Places the IOs according to an input file. Supports regexes.
+File format:
+#N|#S|#E|#W
+pin1_regex
+pin2_regex
+...
+
+#S|#N|#E|#W
+...
+...
+"""
+import odb
+
+import os
+import re
+import sys
+import click
+import random
+
+
+@click.command()
+@click.option(
+ "-u",
+ "--unmatched-error",
+ is_flag=True,
+ default=False,
+ help="Treat unmatched pins as error",
+)
+@click.option("-l", "--input-lef", required=True, help="Input merged tlef/lef file.")
+@click.option(
+ "-o",
+ "--output-def",
+ default="./output.def",
+ help="Output DEF file with newly placed pins",
+)
+@click.option("-c", "--config", required=False, help="Optional configuration file.")
+@click.option(
+ "-r",
+ "--reverse",
+ default="",
+ type=str,
+ help="Reverse along comma,delimited,cardinals: e.g. N,E",
+)
+@click.option("-L", "--length", default=2, type=float, help="Pin length in microns.")
+@click.option(
+ "-V",
+ "--ver-layer",
+ required=True,
+ help="Name of metal layer to place vertical pins on.",
+)
+@click.option(
+ "-H",
+ "--hor-layer",
+ required=True,
+ help="Name of metal layer to place horizontal pins on.",
+)
+@click.option(
+ "--hor-extension",
+ default=0,
+ type=float,
+ help="Extension for vertical pins in microns.",
+)
+@click.option(
+ "--ver-extension",
+ default=0,
+ type=float,
+ help="Extension for horizontal pins in microns.",
+)
+@click.option(
+ "--ver-width-mult", default=2, type=float, help="Multiplier for vertical pins."
+)
+@click.option(
+ "--hor-width-mult", default=2, type=float, help="Multiplier for horizontal pins."
+)
+@click.option(
+ "--bus-sort/--no-bus-sort",
+ default=False,
+ help="Misnomer: pins are grouped by index instead of bus, i.e. a[0] goes with b[0] instead of a[1].",
+)
+@click.argument("input_def")
+def cli(
+ input_lef,
+ output_def,
+ config,
+ ver_layer,
+ hor_layer,
+ ver_width_mult,
+ hor_width_mult,
+ length,
+ hor_extension,
+ ver_extension,
+ reverse,
+ bus_sort,
+ input_def,
+ unmatched_error,
+):
+ """
+ Places the IOs in an input def with an optional config file that supports regexes.
+
+ Config format:
+ #N|#S|#E|#W
+ pin1_regex (low co-ordinates to high co-ordinates; e.g., bottom to top and left to right)
+ pin2_regex
+ ...
+
+ #S|#N|#E|#W
+ """
+
+ def_file_name = input_def
+ lef_file_name = input_lef
+ output_def_file_name = output_def
+ config_file_name = config
+ bus_sort_flag = bus_sort
+ unmatched_error_flag = unmatched_error
+
+ h_layer_name = hor_layer
+ v_layer_name = ver_layer
+
+ h_width_mult = float(hor_width_mult)
+ v_width_mult = float(ver_width_mult)
+
+ # Initialize OpenDB
+ db_top = odb.dbDatabase.create()
+ odb.read_lef(db_top, lef_file_name)
+ odb.read_def(db_top, def_file_name)
+ block = db_top.getChip().getBlock()
+
+ micron_in_units = block.getDefUnits()
+
+ LENGTH = int(micron_in_units * length)
+
+ H_EXTENSION = int(micron_in_units * hor_extension)
+ V_EXTENSION = int(micron_in_units * ver_extension)
+
+ if H_EXTENSION < 0:
+ H_EXTENSION = 0
+
+ if V_EXTENSION < 0:
+ V_EXTENSION = 0
+
+ reverse_arr_raw = reverse.split(",")
+ reverse_arr = []
+ for element in reverse_arr_raw:
+ if element.strip() != "":
+ reverse_arr.append(f"#{element}")
+
+ def getGrid(origin, count, step):
+ tracks = []
+ pos = origin
+ for i in range(count):
+ tracks.append(pos)
+ pos += step
+ assert len(tracks) > 0
+ tracks.sort()
+
+ return tracks
+
+ def equallySpacedSeq(m, arr):
+ seq = []
+ n = len(arr)
+ # Bresenham
+ indices = [i * n // m + n // (2 * m) for i in range(m)]
+ for i in indices:
+ seq.append(arr[i])
+ return seq
+
+ # HUMAN SORTING: https://stackoverflow.com/questions/5967500/how-to-correctly-sort-a-string-with-a-number-inside
+ def natural_keys(enum):
+ def atof(text):
+ try:
+ retval = float(text)
+ except ValueError:
+ retval = text
+ return retval
+
+ text = enum[0]
+ text = re.sub(r"(\[|\]|\.|\$)", "", text)
+ """
+ alist.sort(key=natural_keys) sorts in human order
+ http://nedbatchelder.com/blog/200712/human_sorting.html
+ (see toothy's implementation in the comments)
+ float regex comes from https://stackoverflow.com/a/12643073/190597
+ """
+ return [
+ atof(c) for c in re.split(r"[+-]?([0-9]+(?:[.][0-9]*)?|[.][0-9]+)", text)
+ ]
+
+ def bus_keys(enum):
+ text = enum[0]
+ m = re.match(r"^.*\[(\d+)\]$", text)
+ if not m:
+ return -1
+ else:
+ return int(m.group(1))
+
+ # read config
+
+ pin_placement_cfg = {"#N": [], "#E": [], "#S": [], "#W": []}
+ cur_side = None
+ if config_file_name is not None and config_file_name != "":
+ with open(config_file_name, "r") as config_file:
+ for line in config_file:
+ line = line.split()
+ if len(line) == 0:
+ continue
+
+ if len(line) > 1:
+ print("Only one entry allowed per line.")
+ sys.exit(1)
+
+ token = line[0]
+
+ if cur_side is not None and token[0] != "#":
+ pin_placement_cfg[cur_side].append(token)
+ elif token not in [
+ "#N",
+ "#E",
+ "#S",
+ "#W",
+ "#NR",
+ "#ER",
+ "#SR",
+ "#WR",
+ "#BUS_SORT",
+ ]:
+ print(
+ "Valid directives are #N, #E, #S, or #W. Append R for reversing the default order.",
+ "Use #BUS_SORT to group 'bus bits' by index.",
+ "Please make sure you have set a valid side first before listing pins",
+ )
+ sys.exit(1)
+ elif token == "#BUS_SORT":
+ bus_sort_flag = True
+ else:
+ if len(token) == 3:
+ token = token[0:2]
+ reverse_arr.append(token)
+ cur_side = token
+
+ # build a list of pins
+
+ chip_top = db_top.getChip()
+ block_top = chip_top.getBlock()
+ top_design_name = block_top.getName()
+ tech = db_top.getTech()
+
+ H_LAYER = tech.findLayer(h_layer_name)
+ V_LAYER = tech.findLayer(v_layer_name)
+
+ H_WIDTH = int(h_width_mult * H_LAYER.getWidth())
+ V_WIDTH = int(v_width_mult * V_LAYER.getWidth())
+
+ print("Top-level design name:", top_design_name)
+
+ bterms = block_top.getBTerms()
+ bterms_enum = []
+ for bterm in bterms:
+ pin_name = bterm.getName()
+ bterms_enum.append((pin_name, bterm))
+
+ # sort them "humanly"
+ bterms_enum.sort(key=natural_keys)
+ if bus_sort_flag:
+ bterms_enum.sort(key=bus_keys)
+ bterms = [bterm[1] for bterm in bterms_enum]
+
+ pin_placement = {"#N": [], "#E": [], "#S": [], "#W": []}
+ bterm_regex_map = {}
+ for side in pin_placement_cfg:
+ for regex in pin_placement_cfg[side]: # going through them in order
+ regex += "$" # anchor
+ for bterm in bterms:
+ # if a pin name matches multiple regexes, their order will be
+ # arbitrary. More refinement requires more strict regexes (or just
+ # the exact pin name).
+ pin_name = bterm.getName()
+ if re.match(regex, pin_name) is not None:
+ if bterm in bterm_regex_map:
+ print(
+ "Error: Multiple regexes matched",
+ pin_name,
+ ". Those are",
+ bterm_regex_map[bterm],
+ "and",
+ regex,
+ )
+ sys.exit(os.EX_DATAERR)
+ bterm_regex_map[bterm] = regex
+ pin_placement[side].append(bterm) # to maintain the order
+
+ unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map]
+
+ if len(unmatched_bterms) > 0:
+ print("Warning: Some pins weren't matched by the config file")
+ print("Those are:", [bterm.getName() for bterm in unmatched_bterms])
+ if unmatched_error_flag:
+ print("Treating unmatched pins as errors. Exiting..")
+ sys.exit(1)
+ else:
+ print("Assigning random sides to the above pins")
+ for bterm in unmatched_bterms:
+ random_side = random.choice(list(pin_placement.keys()))
+ pin_placement[random_side].append(bterm)
+
+ assert len(block_top.getBTerms()) == len(
+ pin_placement["#N"]
+ + pin_placement["#E"]
+ + pin_placement["#S"]
+ + pin_placement["#W"]
+ )
+
+ # generate slots
+
+ DIE_AREA = block_top.getDieArea()
+ BLOCK_LL_X = DIE_AREA.xMin()
+ BLOCK_LL_Y = DIE_AREA.yMin()
+ BLOCK_UR_X = DIE_AREA.xMax()
+ BLOCK_UR_Y = DIE_AREA.yMax()
+
+ print("Block boundaries:", BLOCK_LL_X, BLOCK_LL_Y, BLOCK_UR_X, BLOCK_UR_Y)
+
+ origin, count, step = block_top.findTrackGrid(H_LAYER).getGridPatternY(0)
+ h_tracks = getGrid(origin, count, step)
+
+ origin, count, step = block_top.findTrackGrid(V_LAYER).getGridPatternX(0)
+ v_tracks = getGrid(origin, count, step)
+
+ for rev in reverse_arr:
+ pin_placement[rev].reverse()
+
+ # create the pins
+ for side in pin_placement:
+ if side in ["#N", "#S"]:
+ slots = equallySpacedSeq(len(pin_placement[side]), v_tracks)
+ else:
+ slots = equallySpacedSeq(len(pin_placement[side]), h_tracks)
+
+ assert len(slots) == len(pin_placement[side])
+
+ for i in range(len(pin_placement[side])):
+ bterm = pin_placement[side][i]
+ slot = slots[i]
+
+ pin_name = bterm.getName()
+ pins = bterm.getBPins()
+ if len(pins) > 0:
+ print("Warning:", pin_name, "already has shapes. Modifying them")
+ assert len(pins) == 1
+ pin_bpin = pins[0]
+ else:
+ pin_bpin = odb.dbBPin_create(bterm)
+
+ pin_bpin.setPlacementStatus("PLACED")
+
+ if side in ["#N", "#S"]:
+ rect = odb.Rect(0, 0, V_WIDTH, LENGTH + V_EXTENSION)
+ if side == "#N":
+ y = BLOCK_UR_Y - LENGTH
+ else:
+ y = BLOCK_LL_Y - V_EXTENSION
+ rect.moveTo(slot - V_WIDTH // 2, y)
+ odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur())
+ else:
+ rect = odb.Rect(0, 0, LENGTH + H_EXTENSION, H_WIDTH)
+ if side == "#E":
+ x = BLOCK_UR_X - LENGTH
+ else:
+ x = BLOCK_LL_X - H_EXTENSION
+ rect.moveTo(x, slot - H_WIDTH // 2)
+ odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur())
+
+ print(
+ f"Writing {output_def_file_name}...",
+ )
+ odb.write_def(block_top, output_def_file_name)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/iterate_timing_closure.py b/openlane/scripts/iterate_timing_closure.py
new file mode 100644
index 0000000..1862b78
--- /dev/null
+++ b/openlane/scripts/iterate_timing_closure.py
@@ -0,0 +1,238 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Adapted from Pathfinder
+# Copyright 2021 The American University in Cairo
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import re
+import os
+import csv
+import sys
+import glob
+import click
+import shutil
+import pathlib
+import datetime
+import subprocess
+from typing import Dict, Tuple
+
+openlane_dir = os.path.dirname(os.path.dirname(__file__))
+
+log_dir = os.path.join(openlane_dir, "_build", "it_tc_logs")
+
+pathlib.Path(log_dir).mkdir(parents=True, exist_ok=True)
+
+
+def rp(path):
+ return os.path.realpath(path)
+
+
+def openlane(*args_tuple, tag="ol_run"):
+ args = list(args_tuple)
+
+ stdout_f = open(os.path.join(log_dir, f"{tag}.stdout"), "w")
+ stderr_f = open(os.path.join(log_dir, f"{tag}.stderr"), "w")
+
+ cmd = [f"{openlane_dir}/flow.tcl"] + args
+ status = subprocess.run(cmd, stdout=stdout_f, stderr=stderr_f)
+
+ stdout_f.close()
+ stderr_f.close()
+
+ if status.returncode != 0:
+ raise Exception(f"{args} failed with exit code {status.returncode}")
+
+
+def read_env(config_path: str) -> dict:
+ rx = r"\s*set\s*::env\((.+?)\)\s*(.+)"
+ env = {}
+ string_data = ""
+ try:
+ string_data = open(config_path).read()
+ except FileNotFoundError:
+ print(f"❌ File {config_path} not found.", file=sys.stderr)
+ exit(os.EX_NOINPUT)
+
+ # Process \ at ends of lines, remove semicolons
+ entries = string_data.split("\n")
+ i = 0
+ while i < len(entries):
+ if not entries[i].endswith("\\"):
+ if entries[i].endswith(";"):
+ entries[i] = entries[i][:-1]
+ i += 1
+ continue
+ entries[i] = entries[i][:-1] + entries[i + 1]
+ del entries[i + 1]
+
+ for entry in entries:
+ match = re.match(rx, entry)
+ if match is None:
+ continue
+ name = match[1]
+ value = match[2]
+ # remove double quotes/{}
+ value = value.strip('"')
+ value = value.strip("{}")
+ env[name] = value
+
+ return env
+
+
+def get_run_dir(design: str, run_tag: str) -> str:
+ return os.path.join(design, "runs", run_tag)
+
+
+def override_env_str(override_env: dict) -> str:
+ return ",".join([f"{k}={v}" for k, v in override_env.items()])
+
+
+def process_report_csv(csv_in: str) -> Dict[str, str]:
+ metric_dict = {}
+ with open(csv_in) as f:
+ csv_data = list(csv.reader(f, delimiter=",", quotechar="'"))
+ column_count = len(csv_data[0])
+ for column in range(0, column_count):
+ key = csv_data[0][column]
+ value = csv_data[1][column]
+ metric_dict[key] = value
+ return metric_dict
+
+
+presynth_end_step = "placement"
+iteration_start_step = "routing"
+
+
+def presynthesize(design: str) -> Tuple[str, Dict[str, float]]:
+ run_tag = f"{datetime.datetime.now().isoformat()}"
+
+ override_env = {"QUIT_ON_TIMING_VIOLATIONS": 0, "SAVE_FINAL_VIEWS": 0}
+
+ design_name = os.path.basename(design)
+
+ openlane(
+ "-tag",
+ run_tag,
+ "-design",
+ design,
+ "-to",
+ presynth_end_step,
+ "-override_env",
+ override_env_str(override_env),
+ tag=f"{design_name}_presynth",
+ )
+
+ return run_tag
+
+
+def run_and_quantify_closure(
+ design: str, run_tag: str, inputs: dict, tag: str = "0"
+) -> float:
+ override_env = {"QUIT_ON_TIMING_VIOLATIONS": 0, **inputs}
+
+ shutil.copytree(get_run_dir(design, run_tag), get_run_dir(design, f"{run_tag}.bk"))
+
+ exception: Exception = None
+
+ try:
+ openlane(
+ "-tag",
+ run_tag,
+ "-design",
+ design,
+ "-from",
+ "routing",
+ "-to",
+ "routing",
+ "-override_env",
+ override_env_str(override_env),
+ tag=tag,
+ )
+
+ metric_glob = glob.glob(
+ f"{get_run_dir(design, run_tag)}/reports/routing/*-parasitics_sta.worst_slack.rpt"
+ )
+ metric_file = list(
+ filter(lambda x: not os.path.basename(x).startswith("-"), metric_glob)
+ )[0]
+ metric_file_str = open(metric_file).read()
+ metric_rx = re.compile(r"worst\s+slack\s+(-?[\d.]+)")
+ metric_match = metric_rx.search(metric_file_str)
+ worst_slack = float(metric_match[1])
+ except Exception as e:
+ exception = e
+ finally:
+ final_dir = get_run_dir(design, f"{run_tag}.exploration_{tag}")
+ shutil.rmtree(final_dir, ignore_errors=True)
+ shutil.move(get_run_dir(design, run_tag), final_dir)
+
+ shutil.move(get_run_dir(design, f"{run_tag}.bk"), get_run_dir(design, run_tag))
+
+ if exception is not None:
+ raise exception
+
+ return worst_slack
+
+
+@click.command()
+@click.option("--inputs", default="", help="Comma,delimited,KEY=VALUE,pairs")
+@click.option(
+ "--iterate-routing/--iterate-pnr",
+ "iterate_routing_only",
+ default=True,
+ help="Pick whether to iterate on only routing or both placement and routing (latter takes a bit longer)",
+)
+@click.option("--run-tag", required=None, help="Run tag from a previous run")
+@click.argument("design")
+def cli(inputs, iterate_routing_only, run_tag, design):
+ global presynth_end_step, iteration_start_step
+
+ if not iterate_routing_only:
+ presynth_end_step = "floorplan"
+ iteration_start_step = "placement"
+
+ if design.endswith("/"):
+ design = design[:-1]
+
+ if run_tag is None:
+ print("Presynthesizing...")
+ run_tag = presynthesize(design)
+ print(f"Done, presynthesized to {run_tag}")
+
+ input_dict = {}
+ for kvp in inputs.split(","):
+ if not kvp:
+ continue
+ key, value = kvp.split("=")
+ input_dict[key] = value
+
+ count = len(glob.glob(get_run_dir(design, run_tag) + "*"))
+
+ print(f"Running exploration {count} with inputs {input_dict}...")
+
+ design_basename = os.path.basename(design)
+
+ worst_slack = run_and_quantify_closure(
+ design, run_tag, input_dict, f"{design_basename}_{count}"
+ )
+ achieved = worst_slack >= 0
+ if achieved:
+ print("Timing closure achieved.")
+ else:
+ print(f"Timing closure failed: worst slack {worst_slack}.")
+ exit(os.EX_DATAERR)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/klayout/def2gds.py b/openlane/scripts/klayout/def2gds.py
new file mode 100644
index 0000000..0f64fcc
--- /dev/null
+++ b/openlane/scripts/klayout/def2gds.py
@@ -0,0 +1,239 @@
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Original Copyright Follows
+#
+# BSD 3-Clause License
+#
+# Copyright (c) 2018, The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import pya
+
+import re
+import copy
+import json
+
+print(
+ """
+Input: {in_def}
+Output: {out_gds}
+Design: {design_name}
+Technology File: {tech_file}
+GDS File List: {in_gds}
+LEF File: {lef_file}
+""".format(
+ in_def=in_def,
+ design_name=design_name,
+ tech_file=tech_file,
+ in_gds=in_gds.split(),
+ lef_file=lef_file,
+ out_gds=out_gds,
+ )
+)
+
+try:
+ # Expand layers in json
+ def expand_cfg_layers(cfg):
+ layers = cfg["layers"]
+ expand = [layer for layer in layers if "layers" in layers[layer]]
+ for layer in expand:
+ for i, (name, num) in enumerate(
+ zip(layers[layer]["names"], layers[layer]["layers"])
+ ):
+ new_layer = copy.deepcopy(layers[layer])
+ del new_layer["names"]
+ new_layer["name"] = name
+ del new_layer["layers"]
+ new_layer["layer"] = num
+ layers[name] = new_layer
+ del layers[layer]
+
+ def read_cfg():
+ print("INFO: Reading config file: " + config_file)
+ with open(config_file, "r") as f:
+ cfg = json.load(f)
+
+ expand_cfg_layers(cfg)
+ cfg = cfg["layers"] # ignore the rest
+
+ # Map gds layers & datatype to KLayout indices
+ # These are arrays for the different mask numbers
+ for layer, vals in cfg.items():
+ layer = vals["layer"]
+ for key in ("opc", "non-opc"):
+ if key not in vals:
+ continue
+ data = vals[key]
+ if isinstance(data["datatype"], int):
+ data["datatype"] = [data["datatype"]] # convert to array
+ data["klayout"] = [
+ main_layout.find_layer(layer, datatype)
+ for datatype in data["datatype"]
+ ]
+
+ return cfg
+
+ # match a line like:
+ # - LAYER M2 + MASK 2 + OPC RECT ( 3000 3000 ) ( 5000 5000 ) ;
+ rect_pat = re.compile(
+ r"""
+ \s*\-\ LAYER\ (?P<layer>\S+) # The layer name
+ (?: # Non-capturing group
+ \s+\+\ MASK\ (?P<mask>\d+) # Mask, None if absent
+ )?
+ (?P<opc> # OPC, None if absent
+ \s+\+\ OPC
+ )?
+ \s+RECT\
+ \(\ (?P<xlo>\d+)\ (?P<ylo>\d+)\ \)\ # rect lower-left pt
+ \(\ (?P<xhi>\d+)\ (?P<yhi>\d+)\ \)\ ; # rect upper-right pt
+ """,
+ re.VERBOSE,
+ )
+
+ def read_fills(top):
+ if config_file == "":
+ print("WARNING: no fill config file specified")
+ return
+ # KLayout doesn't support FILL in DEF so we have to side load them :(
+ cfg = read_cfg()
+ in_fills = False
+ units = None
+ with open(in_def) as fp:
+ for line in fp:
+ if in_fills:
+ if re.match("END FILLS", line):
+ break # done with fills; don't care what follows
+ m = re.match(rect_pat, line)
+ if not m:
+ raise Exception("Unrecognized fill: " + line)
+ opc_type = "opc" if m.group("opc") else "non-opc"
+ mask = m.group("mask")
+ if not mask: # uncolored just uses first entry
+ mask = 0
+ else:
+ mask = int(mask) - 1 # DEF is 1-based indexing
+ layer = cfg[m.group("layer")][opc_type]["klayout"][mask]
+ xlo = int(m.group("xlo")) / units
+ ylo = int(m.group("ylo")) / units
+ xhi = int(m.group("xhi")) / units
+ yhi = int(m.group("yhi")) / units
+ top.shapes(layer).insert(pya.DBox(xlo, ylo, xhi, yhi))
+ elif re.match("FILLS \d+ ;", line):
+ in_fills = True
+ elif not units:
+ m = re.match("UNITS DISTANCE MICRONS (\d+)", line)
+ if m:
+ units = float(m.group(1))
+
+ # Load technology file
+ tech = pya.Technology()
+ tech.load(tech_file)
+ layoutOptions = tech.load_layout_options
+ layoutOptions.lefdef_config.macro_resolution_mode = 1
+ layoutOptions.lefdef_config.lef_files = [lef_file]
+
+ # Load def file
+ main_layout = pya.Layout()
+ main_layout.read(in_def, layoutOptions)
+
+ # Clear cells
+ top_cell_index = main_layout.cell(design_name).cell_index()
+
+ print("[INFO] Clearing cells...")
+ for i in main_layout.each_cell():
+ if i.cell_index() != top_cell_index:
+ if not i.name.startswith("VIA"):
+ # print("\t" + i.name)
+ i.clear()
+
+ # Load in the gds to merge
+ print("[INFO] Merging GDS files...")
+ for gds in in_gds.split():
+ print("\t{0}".format(gds))
+ main_layout.read(gds)
+
+ # Copy the top level only to a new layout
+ print("[INFO] Copying toplevel cell '{0}'".format(design_name))
+ top_only_layout = pya.Layout()
+ top_only_layout.dbu = main_layout.dbu
+ top = top_only_layout.create_cell(design_name)
+ top.copy_tree(main_layout.cell(design_name))
+
+ read_fills(top)
+
+ print("[INFO] Checking for missing GDS...")
+ missing_gds = False
+ for i in top_only_layout.each_cell():
+ if i.is_empty():
+ missing_gds = True
+ print(
+ "[ERROR] LEF Cell '{0}' has no matching GDS cell. Cell will be empty".format(
+ i.name
+ )
+ )
+
+ if not missing_gds:
+ print("[INFO] All LEF cells have matching GDS cells")
+
+ if seal_gds:
+ top_cell = top_only_layout.top_cell()
+
+ print("[INFO] Reading seal GDS file...")
+ print("\t{0}".format(seal_gds))
+ top_only_layout.read(seal_gds)
+
+ for cell in top_only_layout.top_cells():
+ if cell != top_cell:
+ print(
+ "[INFO] Merging '{0}' as child of '{1}'".format(
+ cell.name, top_cell.name
+ )
+ )
+ top.insert(pya.CellInstArray(cell.cell_index(), pya.Trans()))
+
+ # Write out the GDS
+ print("[INFO] Writing out GDS '{0}'".format(out_gds))
+ top_only_layout.write(out_gds)
+ print("[INFO] Done.")
+ pya.Application.instance().exit(0)
+except Exception as e:
+ print(e)
+ pya.Application.instance().exit(1)
diff --git a/openlane/scripts/klayout/mv_shapes.py b/openlane/scripts/klayout/mv_shapes.py
new file mode 100644
index 0000000..15eda01
--- /dev/null
+++ b/openlane/scripts/klayout/mv_shapes.py
@@ -0,0 +1,69 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import pya
+from time import sleep
+import os
+
+try:
+ if output_layout == "":
+ raise NameError
+ _output_layout = output_layout
+except NameError:
+ _output_layout = input_layout
+ print(
+ "Warning: output_layout was not provided; will do the modifications in place!"
+ )
+ print("Hit CTRL-C to cancel...")
+ sleep(3)
+
+print("Starting...")
+app = pya.Application.instance()
+win = app.main_window()
+
+# Load technology file
+tech = pya.Technology()
+tech.load(tech_file)
+layoutOptions = tech.load_layout_options
+
+# Load def/gds file in the main window
+cell_view = win.load_layout(input_layout, layoutOptions, 0)
+layout_view = cell_view.view()
+layout_view.load_layer_props(os.path.splitext(tech_file)[0] + ".lyp")
+layout_view.max_hier()
+
+# gets the corresponding layout object
+layout = cell_view.layout()
+
+# gets the cell to change is "INV2X"
+# cell = layout.cell("Active_area")
+cell = cell_view.cell
+
+# finds source layer
+layer, purpose = source_layer.split("/")
+assert layer and purpose
+_source_layer = layout.layer(int(layer), int(purpose))
+
+# finds (or creates) target layer
+layer, purpose = target_layer.split("/")
+assert layer and purpose
+_target_layer = layout.layer(int(layer), int(purpose))
+
+layout.move_layer(_source_layer, _target_layer)
+
+layout.write(_output_layout)
+
+print("Successfully wrote", _output_layout)
+
+app.exit(0)
diff --git a/openlane/scripts/klayout/mv_shapes.sh b/openlane/scripts/klayout/mv_shapes.sh
new file mode 100644
index 0000000..6e58e44
--- /dev/null
+++ b/openlane/scripts/klayout/mv_shapes.sh
@@ -0,0 +1,28 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+: ${1?"Usage: $0 file.gds src_layer/src_purpose targ_layer/targ_purpose [output.gds]"}
+: ${2?"Usage: $0 file.gds src_layer/src_purpose targ_layer/targ_purpose [output.gds]"}
+: ${3?"Usage: $0 file.gds src_layer/src_purpose targ_layer/targ_purpose [output.gds]"}
+: ${PDK_ROOT?"You need to export PDK_ROOT"}
+TECH=${TECH:-sky130A}
+
+klayout -b\
+ -rm $(dirname $0)/mv_shapes.py\
+ -rd input_layout=$1\
+ -rd tech_file=$PDK_ROOT/$TECH/libs.tech/klayout/$TECH.lyt\
+ -rd source_layer=$2\
+ -rd target_layer=$3\
+ -rd output_layout=$4
diff --git a/openlane/scripts/klayout/open_design.py b/openlane/scripts/klayout/open_design.py
new file mode 100644
index 0000000..8803973
--- /dev/null
+++ b/openlane/scripts/klayout/open_design.py
@@ -0,0 +1,66 @@
+# Copyright 2020-2022 Efabless Corporation
+# Copyright 2021 The American University in Cairo and the Cloud V Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import pya
+
+app = pya.Application.instance()
+
+try:
+ win = app.main_window()
+
+ layout = os.getenv("LAYOUT")
+ if layout is None:
+ raise Exception("LAYOUT environment variable is not set.")
+
+ pdk_root = os.getenv("PDK_ROOT")
+ if pdk_root is None:
+ raise Exception("PDK_ROOT environment variable is not set.")
+
+ pdk_name = os.getenv("PDK")
+ if pdk_name is None:
+ raise Exception("PDK environment variable is not set.")
+
+ # Relative to the layout path, ':' delimited. If not provided, all LEFs
+ # in the same folder as the layout will be loaded.
+ explicitly_listed_lefs_raw = os.getenv("EXPLICITLY_LISTED_LEFS")
+
+ use_explicitly_listed_lefs = explicitly_listed_lefs_raw is not None
+
+ tech_file_path = os.path.join(
+ pdk_root, pdk_name, "libs.tech", "klayout", f"{pdk_name}.lyt"
+ )
+
+ tech = pya.Technology()
+ tech.load(tech_file_path)
+
+ layout_options = tech.load_layout_options
+
+ layout_options.keep_other_cells = True
+
+ layout_options = tech.load_layout_options
+ layout_options.lefdef_config.macro_resolution_mode = 1
+
+ if use_explicitly_listed_lefs:
+ explicitly_listed_lefs = explicitly_listed_lefs_raw.split(":")
+ layout_options.lefdef_config.read_lef_with_def = False
+ layout_options.lefdef_config.lef_files = explicitly_listed_lefs
+
+ cell_view = win.load_layout(layout, layout_options, 0)
+
+except Exception as e:
+ print(e, file=sys.stderr)
+ app.exit(-1)
diff --git a/openlane/scripts/klayout/open_design_cmd.py b/openlane/scripts/klayout/open_design_cmd.py
new file mode 100644
index 0000000..6abebf8
--- /dev/null
+++ b/openlane/scripts/klayout/open_design_cmd.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import click
+import subprocess
+
+
+@click.command("open_design")
+@click.option(
+ "-l",
+ "--input-lef",
+ default=os.getenv("MERGED_LEF"),
+ help="Input merged technology/cells LEF file",
+)
+@click.option(
+ "-P",
+ "--pdk-root",
+ default=os.getenv("PDK_ROOT"),
+ required=not os.getenv("PDK_ROOT"),
+ help="PDK Root",
+)
+@click.option("-p", "--pdk", default="sky130A", help="Name of the PDK")
+@click.argument("input_def")
+def open_design(input_lef, pdk_root, pdk, input_def):
+ """
+ Opens a design in Klayout.
+ """
+ dir = os.path.dirname(__file__)
+ klayout_script_path = os.path.join(dir, "open_design.py")
+ env = os.environ.copy()
+
+ env["EXPLICITLY_LISTED_LEFS"] = input_lef
+ env["PDK_ROOT"] = pdk_root
+ env["PDK"] = pdk
+ env["LAYOUT"] = input_def
+
+ subprocess.check_call(
+ [
+ "klayout",
+ "-rm",
+ klayout_script_path,
+ ],
+ env=env,
+ )
+
+
+if __name__ == "__main__":
+ open_design()
diff --git a/openlane/scripts/klayout/run_drc.sh b/openlane/scripts/klayout/run_drc.sh
new file mode 100644
index 0000000..aba8aaf
--- /dev/null
+++ b/openlane/scripts/klayout/run_drc.sh
@@ -0,0 +1,32 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set -e
+
+: ${1?"Usage: $0 tech_file input.gds output.txt"}
+: ${2?"Usage: $0 tech_file input.gds output.txt"}
+: ${3?"Usage: $0 tech_file input.gds output.txt"}
+
+echo "Using Techfile: $1"
+echo "Using GDS file: $2"
+echo "Output Report File: $3"
+# The -a here is necessary to handle race conditions.
+# This limits the max number of possible jobs to 100.
+klayout -b \
+ -rd input=$2 \
+ -rd report=$3 \
+ -r $1
+
+exit 0
diff --git a/openlane/scripts/klayout/scrotLayout.py b/openlane/scripts/klayout/scrotLayout.py
new file mode 100644
index 0000000..fe5f1dc
--- /dev/null
+++ b/openlane/scripts/klayout/scrotLayout.py
@@ -0,0 +1,58 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import pya
+import re
+import os
+
+WIDTH = 2048
+HEIGHT = 2048
+
+app = pya.Application.instance()
+win = app.main_window()
+
+# Load technology file
+print("[INFO] Reading tech file: " + str(tech_file))
+tech = pya.Technology()
+tech.load(tech_file)
+
+layoutOptions = tech.load_layout_options
+
+# Load def file in the main window
+print("[INFO] Reading Layout file: " + str(input_layout))
+cell_view = win.load_layout(input_layout, layoutOptions, 0)
+layout_view = cell_view.view()
+
+layout_view.load_layer_props(os.path.splitext(tech_file)[0] + ".lyp")
+
+layout_view.max_hier()
+# layout_view.clear_layers()
+
+# Hide layers with these purposes
+hidden_purposes = [0, 4, 5]
+
+li = layout_view.begin_layers()
+while not li.at_end():
+ lp = li.current()
+ if lp.source_datatype in hidden_purposes:
+ new_lp = lp.dup()
+ new_lp.visible = False
+ layout_view.set_layer_properties(li, new_lp)
+
+ li.next()
+
+print("[INFO] Writing out PNG screenshot '{0}'".format(input_layout + ".png"))
+layout_view.save_image(input_layout + ".png", WIDTH, HEIGHT)
+print("Done")
+app.exit(0)
diff --git a/openlane/scripts/klayout/scrotLayout.sh b/openlane/scripts/klayout/scrotLayout.sh
new file mode 100644
index 0000000..d833783
--- /dev/null
+++ b/openlane/scripts/klayout/scrotLayout.sh
@@ -0,0 +1,31 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set -e
+
+: ${1?"Usage: $0 tech_file input"}
+: ${2?"Usage: $0 tech_file input"}
+
+echo "Using Techfile: $1"
+echo "Using layout file: $2"
+
+# The -a here is necessary to handle race conditions.
+# This limits the max number of possible jobs to 100.
+xvfb-run -a klayout -z \
+ -rd input_layout=$2 \
+ -rd tech_file=$1 \
+ -rm $(dirname $0)/scrotLayout.py
+
+exit 0
diff --git a/openlane/scripts/klayout/xor.drc b/openlane/scripts/klayout/xor.drc
new file mode 100644
index 0000000..6caee91
--- /dev/null
+++ b/openlane/scripts/klayout/xor.drc
@@ -0,0 +1,42 @@
+# A general XOR script
+# (https://www.klayout.de/forum/discussion/100/xor-vs-diff-tool)
+# This script uses KLayout's DRC language to implement a generic
+# XOR between two layouts. The name of the layouts is given
+# in $a and $b.
+
+# For layout-to-layout XOR with multiple cores, run this script with
+# ./klayout -r xor.drc -rd thr=NUM_CORES -rd top_cell=TOP_CELL_NAME -rd a=a.gds -rd b=b.gds -rd ol=xor.gds -zz
+# (replace NUM_CORES by the desired number of cores to utilize
+
+# enable timing output
+verbose
+
+# set up input a
+a = source($a, $top_cell)
+
+# set up input b
+b = source($b, $top_cell)
+
+$o && $ext != "gds" && report("XOR #{$a} vs. #{$b}", $o)
+$ol && $ext == "gds" && target($ol, $co || "XOR")
+
+$thr && threads($thr) || threads(2)
+
+# collect all common layers
+layers = {}
+[ a.layout, b.layout ].each do |ly|
+ ly.layer_indices.each do |li|
+ i = ly.get_info(li)
+ layers[i.to_s] = i
+ end
+end
+
+# perform the XOR's
+layers.keys.sort.each do |l|
+ i = layers[l]
+ info("--- Running XOR for #{l} ---")
+ x = a.input(l) ^ b.input(l)
+ info("XOR differences: #{x.data.size}")
+ $o && $ext != "gds" && x.output(l, "XOR results for layer #{l} #{i.name}")
+ $ol && $ext == "gds" && x.output(i.layer, i.datatype, i.name)
+end
diff --git a/openlane/scripts/klayout/xor.sh b/openlane/scripts/klayout/xor.sh
new file mode 100755
index 0000000..b71ef79
--- /dev/null
+++ b/openlane/scripts/klayout/xor.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+: ${1?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${2?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${3?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${4?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+
+
+echo "First Layout: $1"
+echo "Second Layout: $2"
+echo "Design Name: $3"
+echo "Output GDS will be: $4"
+
+klayout -b\
+ -r $(dirname $0)/xor.drc \
+ -rd top_cell=$3 \
+ -rd a=$1 \
+ -rd b=$2 \
+ -rd thr=$(nproc) \
+ -rd ol=$4 \
+ -rd o=$4 \
+ -rd ext=${4##*.}
diff --git a/openlane/scripts/label_macro_pins.py b/openlane/scripts/label_macro_pins.py
new file mode 100644
index 0000000..5f26a7c
--- /dev/null
+++ b/openlane/scripts/label_macro_pins.py
@@ -0,0 +1,353 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Takes a DEF file with no PINS section, a LEF file that has the shapes of all
+i/o ports that need to labeled, and a netlist where i/o ports are connected
+to single macro pin given also as an input -> writes a PINS section with shapes
+generated over those macro pins, "labels".
+"""
+import argparse
+import odb
+
+parser = argparse.ArgumentParser(
+ description="Labels pins of macros according to netlist"
+)
+
+parser.add_argument(
+ "--netlist-def",
+ "-nd",
+ required=True,
+ help="DEF view of the design that has the connectivity information",
+)
+
+
+parser.add_argument(
+ "--lef",
+ "-l",
+ nargs="+",
+ type=str,
+ default=None,
+ required=True,
+ help="LEF file needed to have a proper view of the netlist AND the input DEF",
+)
+
+parser.add_argument(
+ "--input-def",
+ "-id",
+ required=True,
+ help="DEF view of the design that needs to be labeled",
+)
+
+parser.add_argument(
+ "--output",
+ "-o",
+ required=False,
+ help="Output labeled def file. Defaults to the input def",
+)
+
+parser.add_argument("--verbose", "-v", action="store_true", required=False)
+
+parser.add_argument("--all-shapes-flag", "-all", action="store_true", required=False)
+
+parser.add_argument(
+ "--pad-pin-name",
+ "-ppn",
+ required=False,
+ default="PAD",
+ help="Name of the pin of the pad as it appears in the netlist def",
+)
+
+parser.add_argument(
+ "--pin-size",
+ "-ps",
+ required=False,
+ type=int,
+ default=1,
+ help="Size of the block pin created in um",
+)
+
+parser.add_argument(
+ "--db-microns",
+ "-dbum",
+ required=False,
+ type=int,
+ default=1000,
+ help="DEF units per micron",
+)
+
+parser.add_argument(
+ "--map",
+ "-m",
+ action="append",
+ nargs=4,
+ required=False,
+ default=[],
+ help="Extra mappings that are hard to infer from the netlist def. Format: -extra pad_instance_name pad_pin block_pin (INPUT|OUTPUT|INOUT)",
+)
+
+args = parser.parse_args()
+
+VERBOSE = args.verbose
+PAD_PIN_NAME = args.pad_pin_name
+BLOCK_PIN_SIZE = args.pin_size
+DEF_UNITS_PER_MICRON = args.db_microns
+
+all_shapes_flag = args.all_shapes_flag
+netlist_def_file_name = args.netlist_def
+netlist_lef_file_names = args.lef
+input_def_file_name = args.input_def
+input_lef_file_names = args.lef
+
+extra_mappings = args.map
+extra_mappings_pin_names = [tup[2] for tup in extra_mappings]
+
+if args.output is not None:
+ output_def_file_name = args.output
+else:
+ print("Warning: The input DEF file will be overwritten")
+ output_def_file_name = input_def_file_name
+
+
+def getBiggestBox(iterm):
+ inst = iterm.getInst()
+ px, py = inst.getOrigin()
+ orient = inst.getOrient()
+ transform = odb.dbTransform(orient, odb.Point(px, py))
+
+ mterm = iterm.getMTerm()
+ mpins = mterm.getMPins()
+
+ # label biggest mpin
+ biggest_mpin = None
+ biggest_size = -1
+ for i in range(len(mpins)):
+ mpin = mpins[i]
+ box = mpin.getGeometry()[
+ 0
+ ] # assumes there's only one; to extend and get biggest
+
+ llx, lly = box.xMin(), box.yMin()
+ urx, ury = box.xMax(), box.yMax()
+ area = (urx - llx) * (ury - lly)
+ if area > biggest_size:
+ biggest_size = area
+ biggest_mpin = mpin
+
+ main_mpin = biggest_mpin
+ box = main_mpin.getGeometry()[0]
+ ll = odb.Point(box.xMin(), box.yMin())
+ ur = odb.Point(box.xMax(), box.yMax())
+ # x = (ll.getX() + ur.getX())//2
+ # y = (ll.getY() + ur.getY())//2
+ # if VERBOSE: print(x, y)
+ transform.apply(ll)
+ transform.apply(ur)
+
+ layer = box.getTechLayer()
+
+ return [(layer, ll, ur)]
+
+
+def getAllBoxes(iterm):
+ inst = iterm.getInst()
+ px, py = inst.getOrigin()
+ orient = inst.getOrient()
+ transform = odb.dbTransform(orient, odb.Point(px, py))
+
+ mterm = iterm.getMTerm()
+ mpins = mterm.getMPins()
+
+ boxes = []
+
+ for i in range(len(mpins)):
+ mpin = mpins[i]
+ geometries = mpin.getGeometry()
+ for box in geometries:
+ # llx, lly = box.xMin(), box.yMin()
+ # urx, ury = box.xMax(), box.yMax()
+ ll = odb.Point(box.xMin(), box.yMin())
+ ur = odb.Point(box.xMax(), box.yMax())
+ transform.apply(ll)
+ transform.apply(ur)
+ layer = box.getTechLayer()
+ boxes.append((layer, ll, ur))
+
+ return boxes
+
+
+def labelITerm(iterm, pin_name, iotype, all_shapes_flag=False):
+ net_name = pin_name
+ net = chip_block.findNet(net_name)
+ if net is None:
+ net = odb.dbNet_create(chip_block, net_name)
+
+ pin_bterm = chip_block.findBTerm(pin_name)
+ if pin_bterm is None:
+ pin_bterm = odb.dbBTerm_create(net, pin_name)
+
+ assert pin_bterm is not None, "Failed to create or find " + pin_name
+
+ pin_bterm.setIoType(iotype)
+
+ pin_bpin = odb.dbBPin_create(pin_bterm)
+ pin_bpin.setPlacementStatus("PLACED")
+
+ if not all_shapes_flag:
+ boxes = getBiggestBox(pad_iterm)
+ else:
+ boxes = getAllBoxes(pad_iterm)
+
+ for box in boxes:
+ layer, ll, ur = box
+ odb.dbBox_create(pin_bpin, layer, ll.getX(), ll.getY(), ur.getX(), ur.getY())
+
+ pad_iterm.connect(net)
+ pin_bterm.connect(net)
+
+
+mapping_db = odb.dbDatabase.create()
+for lef in netlist_lef_file_names:
+ odb.read_lef(mapping_db, lef)
+odb.read_def(mapping_db, netlist_def_file_name)
+
+# for later
+chip_db = odb.dbDatabase.create()
+for lef in input_lef_file_names:
+ print(lef)
+ odb.read_lef(chip_db, lef)
+odb.read_def(chip_db, input_def_file_name)
+
+mapping_chip = mapping_db.getChip()
+mapping_block = mapping_chip.getBlock()
+mapping_nets = mapping_block.getNets()
+
+pad_pin_map = {}
+for net in mapping_nets:
+ iterms = net.getITerms()
+ bterms = net.getBTerms()
+ if len(iterms) >= 1 and len(bterms) == 1:
+ pin_name = bterms[0].getName()
+ if pin_name in extra_mappings_pin_names:
+ if VERBOSE:
+ print(pin_name, "handled by an external mapping; skipping...")
+ continue
+
+ pad_name = None
+ pad_pin_name = None
+ for iterm in iterms:
+ iterm_pin_name = iterm.getMTerm().getName()
+ if iterm_pin_name == PAD_PIN_NAME:
+ pad_name = iterm.getInst().getName()
+ pad_pin_name = iterm_pin_name
+ break
+
+ # '\[' and '\]' are common DEF names
+
+ if pad_name is None:
+ print(
+ "Warning: net",
+ net.getName(),
+ "has a BTerm but no ITerms that match PAD_PIN_NAME",
+ )
+
+ print("Warning: will label the first ITerm on the net!!!!!!!")
+
+ pad_name = iterms[0].getInst().getName()
+ pad_pin_name = iterms[0].getMTerm().getName()
+
+ if VERBOSE:
+ print(
+ "Labeling ",
+ net.getName(),
+ "(",
+ pin_name,
+ "-",
+ pad_name,
+ "/",
+ pad_pin_name,
+ ")",
+ )
+
+ pad_pin_map.setdefault(pad_name, [])
+ pad_pin_map[pad_name].append((pad_pin_name, pin_name, bterms[0].getIoType()))
+
+for mapping in extra_mappings:
+ pad_pin_map.setdefault(mapping[0], [])
+ pad_pin_map[mapping[0]].append((mapping[1], mapping[2], mapping[3]))
+
+pad_pins_to_label_count = len(
+ [
+ mapping
+ for sublist in [pair[1] for pair in pad_pin_map.items()]
+ for mapping in sublist
+ ]
+)
+bterms = mapping_block.getBTerms()
+print(
+ set([bterm.getName() for bterm in bterms])
+ - set(
+ [
+ mapping[1]
+ for sublist in [pair[1] for pair in pad_pin_map.items()]
+ for mapping in sublist
+ ]
+ )
+)
+assert pad_pins_to_label_count == len(
+ bterms
+), "Some pins were not going to be labeled %d/%d" % (
+ pad_pins_to_label_count,
+ len(bterms),
+)
+print("Labeling", len(pad_pin_map), "pads")
+print("Labeling", pad_pins_to_label_count, "pad pins")
+if VERBOSE:
+ print(pad_pin_map)
+
+##############
+
+chip_chip = chip_db.getChip()
+chip_block = chip_chip.getBlock()
+chip_insts = chip_block.getInsts()
+chip_tech = chip_db.getTech()
+
+labeled_count = 0
+labeled = []
+for inst in chip_insts:
+ inst_name = inst.getName()
+ if inst_name in pad_pin_map:
+ for mapping in pad_pin_map[inst_name]:
+ labeled_count += 1
+ pad_pin_name = mapping[0]
+ pin_name = mapping[1]
+ iotype = mapping[2]
+ if VERBOSE:
+ print("Found: ", inst_name, pad_pin_name, pin_name)
+
+ pad_iterm = inst.findITerm(pad_pin_name)
+
+ labelITerm(pad_iterm, pin_name, iotype, all_shapes_flag=all_shapes_flag)
+
+ labeled.append(inst_name)
+
+assert labeled_count == pad_pins_to_label_count, (
+ "Didn't label what I set out to label %d/%d"
+ % (labeled_count, pad_pins_to_label_count),
+ set(pad_pin_map.keys()) - set(labeled),
+)
+
+print("Writing", output_def_file_name)
+odb.write_def(chip_block, output_def_file_name)
diff --git a/openlane/scripts/libtrim.py b/openlane/scripts/libtrim.py
new file mode 100644
index 0000000..77d5369
--- /dev/null
+++ b/openlane/scripts/libtrim.py
@@ -0,0 +1,72 @@
+#!/usr/bin/python3
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Direct-translated from Perl to Python by Donn.
+
+import re
+import click
+
+
+@click.command()
+@click.option("-c", "--cell-file", required=True, help="Cell file")
+@click.option("-o", "--output", required=True, help="Output liberty file")
+@click.argument("input_lib_files", nargs=-1)
+def cli(cell_file, output, input_lib_files):
+ excluded_cells = list(
+ map(lambda x: x.strip(), open(cell_file).read().strip().split("\n"))
+ )
+
+ output_file_handle = open(output, "w")
+
+ def write(string):
+ print(string, file=output_file_handle)
+
+ cell_start_rx = re.compile(r"(\s*)cell\s*\(\"?(.*?)\"?\)\s*\{")
+
+ state = 0
+ brace_count = 0
+ for file in input_lib_files:
+ input_lib_str = open(file).read()
+ input_lib_lines = input_lib_str.split("\n")
+ for line in input_lib_lines:
+ if state == 0:
+ cell_m = cell_start_rx.search(line)
+ if cell_m is not None:
+ whitespace = cell_m[1]
+ cell_name = cell_m[2]
+ if cell_name in excluded_cells:
+ state = 2
+ write(f"{whitespace}/* removed {cell_name} */")
+ else:
+ state = 1
+ write(line)
+ brace_count = 1
+ else:
+ write(line)
+ elif state in [1, 2]:
+ if "{" in line:
+ brace_count += 1
+ if "}" in line:
+ brace_count -= 1
+ if state == 1:
+ write(line)
+ if brace_count == 0:
+ state = 0
+
+ output_file_handle.close()
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/magic/drc.tcl b/openlane/scripts/magic/drc.tcl
new file mode 100755
index 0000000..8c1892c
--- /dev/null
+++ b/openlane/scripts/magic/drc.tcl
@@ -0,0 +1,78 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { [info exist ::env(MAGIC_DRC_USE_GDS)] && $::env(MAGIC_DRC_USE_GDS) } {
+ gds read $::env(CURRENT_GDS)
+} else {
+ lef read $::env(TECH_LEF)
+ if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+ }
+ def read $::env(CURRENT_DEF)
+}
+
+set drc_rpt_path $::env(drc_prefix).rpt
+set fout [open $drc_rpt_path w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_NAME)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $cell_name\n"
+flush stdout
+load $cell_name
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+
+
+set count 0
+puts $fout "$cell_name"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3fum %.3fum %.3fum %.3fum" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE ($drc_rpt_path)"
+flush stdout
+
+set mag_view $::env(signoff_results)/$::env(DESIGN_NAME).drc.mag
+puts stdout "\[INFO\]: Saving mag view with DRC errors ($mag_view)"
+# WARNING: changes the name of the cell; keep as last step
+save $mag_view
+puts stdout "\[INFO\]: Saved"
+
+exit 0
diff --git a/openlane/scripts/magic/drc_batch.tcl b/openlane/scripts/magic/drc_batch.tcl
new file mode 100755
index 0000000..a34a28c
--- /dev/null
+++ b/openlane/scripts/magic/drc_batch.tcl
@@ -0,0 +1,74 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { [info exists ::env(TECH)] } {
+ tech load $::env(TECH)
+}
+
+gds read $::env(GDS_INPUT)
+proc custom_drc_save_report {{cellname ""} {outfile ""}} {
+
+ if {$outfile == ""} {set outfile "drc.out"}
+
+ set fout [open $outfile w]
+ set oscale [cif scale out]
+
+ # magic::suspendall
+
+ if {$cellname == ""} {
+ select top cell
+ set cellname [cellname list self]
+ set origname ""
+ } else {
+ set origname [cellname list self]
+ puts stdout "\[INFO\]: Loading $cellname\n"
+ flush stdout
+
+ load $cellname
+ select top cell
+ }
+
+ drc check
+ set count [drc list count]
+
+ puts $fout "$cellname count: $count"
+ puts $fout "----------------------------------------"
+ set drcresult [drc listall why]
+ foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3fum %.3fum %.3fum %.3fum" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ }
+ puts $fout "----------------------------------------"
+ }
+ puts $fout ""
+
+ if {$origname != ""} {
+ load $origname
+ }
+
+ # magic::resumeall
+
+ close $fout
+ puts "\[INFO\]: DONE with $outfile\n"
+ #flush stdout
+}
+
+custom_drc_save_report $::env(DESIGN_NAME) $::env(REPORT_OUTPUT)
diff --git a/openlane/scripts/magic/erase_box.sh b/openlane/scripts/magic/erase_box.sh
new file mode 100644
index 0000000..41ceb65
--- /dev/null
+++ b/openlane/scripts/magic/erase_box.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+: ${1?"Usage: $0 file.gds llx lly urx ury"}
+: ${2?"Usage: $0 file.gds llx lly urx ury"}
+: ${3?"Usage: $0 file.gds llx lly urx ury"}
+: ${4?"Usage: $0 file.gds llx lly urx ury"}
+: ${5?"Usage: $0 file.gds llx lly urx ury"}
+: ${PDK_ROOT?"You need to export PDK_ROOT"}
+
+
+export PDK=sky130A
+
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc
+
+MAGTYPE=mag magic -rcfile $MAGIC_MAGICRC -dnull -noconsole <<EOF
+echo $MAGTYPE
+tech unlock *
+gds read $1
+box $2um $3um $4um $5um
+erase
+select area
+delete
+#### REVISE THIS:
+select top cell
+erase labels
+####
+gds write ${1%.*}_erased.gds
+EOF
+ls ${1%.*}_erased.gds
diff --git a/openlane/scripts/magic/gds_pointers.tcl b/openlane/scripts/magic/gds_pointers.tcl
new file mode 100755
index 0000000..0425dcb
--- /dev/null
+++ b/openlane/scripts/magic/gds_pointers.tcl
@@ -0,0 +1,31 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+drc off
+
+gds readonly true
+gds rescale false
+
+# This comes afterwards, so that it would contain GDS pointers
+# And yes, we need to re-read the GDS we just generated...
+gds read $::env(MAGIC_GDS)
+cellname filepath $::env(DESIGN_NAME) $::env(signoff_tmpfiles)
+save
+
+set final_filepath $::env(signoff_tmpfiles)/gds_ptrs.mag
+
+file rename -force $::env(signoff_tmpfiles)/$::env(DESIGN_NAME).mag $final_filepath
+
+puts "\[INFO\]: Wrote $final_filepath including GDS pointers."
+exit 0
diff --git a/openlane/scripts/magic/gdses2mags.tcl b/openlane/scripts/magic/gdses2mags.tcl
new file mode 100755
index 0000000..9f28745
--- /dev/null
+++ b/openlane/scripts/magic/gdses2mags.tcl
@@ -0,0 +1,43 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# convert all external macros to mag views with GDS pointers
+# we will only copy the GDS pointers from these files in the
+# corresponding maglefs
+
+drc off
+
+gds readonly true
+gds rescale false
+
+if { [info exist ::env(EXTRA_GDS_FILES)] } {
+ set gds_files_in $::env(EXTRA_GDS_FILES)
+ foreach gds_file $gds_files_in {
+ gds read $gds_file
+
+ select top cell
+ set design_name [cellname list self]
+
+ cellname filepath $design_name $::env(signoff_results)
+
+ save
+
+ # maglefs reserve the original names
+ file rename $::env(signoff_results)/$design_name.mag $::env(signoff_results)/$design_name.full.mag
+
+ puts "\[INFO]: Saved mag view from $gds_file under $::env(signoff_results)"
+ }
+}
+
+exit 0
diff --git a/openlane/scripts/magic/lef.tcl b/openlane/scripts/magic/lef.tcl
new file mode 100755
index 0000000..3406205
--- /dev/null
+++ b/openlane/scripts/magic/lef.tcl
@@ -0,0 +1,29 @@
+drc off
+
+lef read $::env(TECH_LEF)
+
+if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+}
+
+load $::env(signoff_results)/$::env(DESIGN_NAME).mag -dereference
+
+cellname filepath $::env(DESIGN_NAME) $::env(signoff_results)
+
+# Write LEF
+if { $::env(MAGIC_WRITE_FULL_LEF) } {
+ puts "\[INFO\]: Writing non-abstract (full) LEF"
+ lef write $::env(signoff_results)/$::env(DESIGN_NAME).lef
+} else {
+ puts "\[INFO\]: Writing abstract LEF"
+ if { [info exists ::env(FP_PDN_CORE_RING)] && $::env(FP_PDN_CORE_RING) == 1 } {
+ set tolerance 0.3
+ lef write $::env(signoff_results)/$::env(DESIGN_NAME).lef -hide
+ } else {
+ lef write $::env(signoff_results)/$::env(DESIGN_NAME).lef -hide
+ }
+}
+puts "\[INFO\]: LEF Write Complete"
diff --git a/openlane/scripts/magic/lefs2maglefs.tcl b/openlane/scripts/magic/lefs2maglefs.tcl
new file mode 100755
index 0000000..0de8052
--- /dev/null
+++ b/openlane/scripts/magic/lefs2maglefs.tcl
@@ -0,0 +1,66 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# convert all external macros to maglef views with GDS_* pointers
+
+drc off
+
+# lef read $::env(TECH_LEF)
+
+if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+}
+
+cellname delete \(UNNAMED\)
+
+foreach design_name [cellname list allcells] {
+ load $design_name
+
+ cellname filepath $design_name $::env(signoff_results)
+
+ save
+
+ # Copy GDS pointers from .full.mag files into .mag files
+
+ set gds_properties [list]
+ set fp [open $design_name.full.mag r]
+
+ set mag_lines [split [read $fp] "\n"]
+ foreach line $mag_lines {
+ if { [string first "string GDS_" $line] != -1 } {
+ lappend gds_properties $line
+ }
+ }
+ close $fp
+
+ set fp [open $design_name.mag r]
+ set mag_lines [split [read $fp] "\n"]
+ set new_mag_lines [list]
+ foreach line $mag_lines {
+ if { [string first "<< end >>" $line] != -1 } {
+ lappend new_mag_lines [join $gds_properties "\n"]
+ }
+ lappend new_mag_lines $line
+ }
+ close $fp
+
+ set fp [open $design_name.mag w]
+ puts $fp [join $new_mag_lines "\n"]
+ close $fp
+}
+
+exit 0
diff --git a/openlane/scripts/magic/mag.tcl b/openlane/scripts/magic/mag.tcl
new file mode 100755
index 0000000..043d717
--- /dev/null
+++ b/openlane/scripts/magic/mag.tcl
@@ -0,0 +1,28 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+drc off
+
+gds readonly true
+gds rescale false
+
+puts "\[INFO\]: Saving .mag view With BBox Values: [box values]"
+# This comes afterwards, so that it would contain GDS pointers
+# And yes, we need to re-read the GDS we just generated...
+gds read $::env(MAGIC_GDS)
+cellname filepath $::env(DESIGN_NAME) $::env(signoff_results)
+save
+
+puts "\[INFO\]: MAGIC TAPEOUT STEP DONE"
+exit 0
diff --git a/openlane/scripts/magic/mag_gds.tcl b/openlane/scripts/magic/mag_gds.tcl
new file mode 100755
index 0000000..20cc1f9
--- /dev/null
+++ b/openlane/scripts/magic/mag_gds.tcl
@@ -0,0 +1,101 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+drc off
+
+lef read $::env(TECH_LEF)
+
+if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+}
+
+# Read def and load design
+def read $::env(CURRENT_DEF)
+
+load $::env(DESIGN_NAME)
+select top cell
+
+# padding
+if { $::env(MAGIC_PAD) } {
+ puts "\[INFO\]: Padding LEFs"
+ # assuming scalegrid 1 2
+ # use um
+ select top cell
+ box grow right [expr 100*($::env(PLACE_SITE_WIDTH))]
+ box grow left [expr 100*($::env(PLACE_SITE_WIDTH))]
+ box grow up [expr 100*($::env(PLACE_SITE_HEIGHT))]
+ box grow down [expr 100*($::env(PLACE_SITE_HEIGHT))]
+ property FIXED_BBOX [box values]
+}
+
+if { $::env(MAGIC_ZEROIZE_ORIGIN) } {
+ # assuming scalegrid 1 2
+ # makes origin zero based on the minimum enclosing box
+ # all shapes will be within the block boundary
+ # lower left corner will become (0, 0)
+ puts "\[INFO\]: Zeroizing Origin"
+ set bbox [box values]
+ set offset_x [lindex $bbox 0]
+ set offset_y [lindex $bbox 1]
+ move origin [expr {$offset_x/2}] [expr {$offset_y/2}]
+ puts "\[INFO\]: Current Box Values: [box values]"
+ property FIXED_BBOX [box values]
+} else {
+ # makes origin zero based on the DIEAREA as defined in the DEF
+ # file. Shapes can extend outside the block boundary.
+ # magic "lef write -hide" doesn't produce nice results in this
+ # case for shapes outside the boundary.
+ box [lindex $::env(DIE_AREA) 0]um [lindex $::env(DIE_AREA) 1]um [lindex $::env(DIE_AREA) 2]um [lindex $::env(DIE_AREA) 3]um
+ property FIXED_BBOX [box values]
+}
+
+select top cell
+
+cellname filepath $::env(DESIGN_NAME) $::env(signoff_results)
+
+save
+
+# Write GDS
+if { $::env(MAGIC_GENERATE_GDS) } {
+ # mark the incoming cell defs as readonly so that their
+ # GDS data gets copied verbatim
+ gds readonly true
+ gds rescale false
+ if { [info exist ::env(EXTRA_GDS_FILES)] } {
+ set gds_files_in $::env(EXTRA_GDS_FILES)
+ foreach gds_file $gds_files_in {
+ gds read $gds_file
+ }
+ }
+
+ load $::env(DESIGN_NAME)
+
+ select top cell
+
+ if { [info exist ::env(MAGIC_DISABLE_HIER_GDS)]\
+ && $::env(MAGIC_DISABLE_HIER_GDS) } {
+ cif *hier write disable
+ cif *array write disable
+ }
+
+ gds nodatestamp yes
+
+ gds write $::env(MAGIC_GDS)
+ puts "\[INFO\]: GDS Write Complete"
+}
+
+exit 0
diff --git a/openlane/scripts/magic/maglef.tcl b/openlane/scripts/magic/maglef.tcl
new file mode 100755
index 0000000..ae7f380
--- /dev/null
+++ b/openlane/scripts/magic/maglef.tcl
@@ -0,0 +1,27 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+drc off
+
+lef read $::env(signoff_results)/$::env(DESIGN_NAME).lef
+
+load $::env(DESIGN_NAME)
+
+cellname rename $::env(DESIGN_NAME) $::env(DESIGN_NAME).lef
+
+cellname filepath $::env(DESIGN_NAME).lef $::env(signoff_results)
+save
+
+puts "\[INFO\]: DONE GENERATING MAGLEF VIEW"
+exit 0
diff --git a/openlane/scripts/magic_drc_to_rdb.py b/openlane/scripts/magic_drc_to_rdb.py
new file mode 100644
index 0000000..979a6b1
--- /dev/null
+++ b/openlane/scripts/magic_drc_to_rdb.py
@@ -0,0 +1,73 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Developed by @ganeshgore
+
+import argparse
+
+
+def formatter(prog):
+ return argparse.HelpFormatter(prog, max_help_position=60)
+
+
+parser = argparse.ArgumentParser(formatter_class=formatter)
+
+# Mandatory arguments
+parser.add_argument("--magic_drc_in", type=str, default="./checks/caravel.magic.drc")
+parser.add_argument("--rdb_out", type=str, default="./checks/caravel.magic.rdb")
+args = parser.parse_args()
+
+data, drc = True, False
+
+
+def main():
+ try:
+ fp = open(args.magic_drc_in)
+ lineType = data
+ drcRule = ""
+ with open(args.rdb_out, "w") as fpw:
+ for indx, line in enumerate(fp.readlines()):
+ if ("[INFO]" in line) or (len(line.strip()) == 0):
+ continue
+ elif indx == 0:
+ fpw.write(f"${line} 100\n")
+ elif "------" in line:
+ lineType = not lineType
+ elif lineType == drc:
+ drcRule = line.strip().split("(")
+ drcRule = [drcRule, "UnknownRule"] if len(drcRule) < 2 else drcRule
+ fpw.write(f"r_0_{drcRule[1][:-1]}\n")
+ fpw.write("500 500 2 Nov 29 03:26:39 2020\n")
+ fpw.write(f"Rule File Pathname: {args.magic_drc_in}\n")
+ fpw.write(f"{drcRule[1][:-1]}: {drcRule[0]}\n")
+ drcNumber = 1
+ elif lineType == data:
+ cord = [int(float(i)) * 100 for i in line.strip().split(" ")]
+ fpw.write(f"p {drcNumber} 4\n")
+ fpw.write(f"{cord[0]} {cord[1]}\n")
+ fpw.write(f"{cord[2]} {cord[1]}\n")
+ fpw.write(f"{cord[2]} {cord[3]}\n")
+ fpw.write(f"{cord[0]} {cord[3]}\n")
+ drcNumber += 1
+ print(f"Generated RDB at {args.rdb_out}")
+ except IOError:
+ print("Magic DRC Error file not found {args.magic_drc_in}")
+ except Exception:
+ print("Failed to generate RDB file")
+ finally:
+ fp.close()
+
+
+if __name__ == "__main__":
+ main()
diff --git a/openlane/scripts/magic_drc_to_tcl.py b/openlane/scripts/magic_drc_to_tcl.py
new file mode 100644
index 0000000..497561f
--- /dev/null
+++ b/openlane/scripts/magic_drc_to_tcl.py
@@ -0,0 +1,64 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import os
+
+parser = argparse.ArgumentParser(
+ description="Converts a magic.drc file to a magic readable tcl file."
+)
+
+parser.add_argument("--input_file", "-i", required=True, help="input magic.drc")
+
+parser.add_argument("--output_file", "-o", required=True, help="output magic.drc.tcl")
+
+args = parser.parse_args()
+input_file = args.input_file
+output_file = args.output_file
+
+
+printArr = []
+
+splitLine = "----------------------------------------"
+
+# Converting Magic DRC
+if os.path.exists(input_file):
+ drcFileOpener = open(input_file)
+ if drcFileOpener.mode == "r":
+ drcContent = drcFileOpener.read()
+ drcFileOpener.close()
+
+ # design name
+ # violation message
+ # list of violations
+ # Total Count:
+ if drcContent is not None:
+ drcSections = drcContent.split(splitLine)
+ if len(drcSections) > 2:
+ for i in range(1, len(drcSections) - 1, 2):
+ vio_name = drcSections[i].strip()
+ for vio in drcSections[i + 1].split("\n"):
+ vio = vio.strip()
+ if len(vio):
+ vio_line = (
+ "box " + vio + '; feedback add "' + vio_name + '" medium'
+ )
+ printArr.append(vio_line)
+else:
+ printArr.append("Source not found.")
+
+# write into file
+outputFileOpener = open(output_file, "w")
+outputFileOpener.write("\n".join(printArr))
+outputFileOpener.close()
diff --git a/openlane/scripts/magic_drc_to_tr_drc.py b/openlane/scripts/magic_drc_to_tr_drc.py
new file mode 100644
index 0000000..cbe6f90
--- /dev/null
+++ b/openlane/scripts/magic_drc_to_tr_drc.py
@@ -0,0 +1,99 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import os
+import re
+
+parser = argparse.ArgumentParser(
+ description="Converts a magic.drc file to a TritonRoute DRC format file."
+)
+
+parser.add_argument("--input_file", "-i", required=True, help="input magic.drc")
+
+parser.add_argument("--output_file", "-o", required=True, help="output magic.tr.drc")
+
+args = parser.parse_args()
+input_file = args.input_file
+output_file = args.output_file
+
+
+def cleanup(vio_type):
+ return (
+ str(vio_type)
+ .replace(" ", "_")
+ .replace(">", "gt")
+ .replace("<", "lt")
+ .replace("=", "eq")
+ .replace("!", "not")
+ .replace("^", "pow")
+ .replace(".", "dot")
+ .replace("-", "_")
+ .replace("+", "plus")
+ .replace("(", "")
+ .replace(")", "")
+ )
+
+
+printArr = []
+
+splitLine = "----------------------------------------"
+
+# Converting Magic DRC
+if os.path.exists(input_file):
+ drcFileOpener = open(input_file)
+ if drcFileOpener.mode == "r":
+ drcContent = drcFileOpener.read()
+ drcFileOpener.close()
+
+ # design name
+ # violation message
+ # list of violations
+ # Total Count:
+ pattern = re.compile(r".*\s*\((\S+)\.?\s*[^\(\)]+\)")
+ if drcContent is not None:
+ drcSections = drcContent.split(splitLine)
+ if len(drcSections) > 2:
+ for i in range(1, len(drcSections) - 1, 2):
+ vio_name = drcSections[i].strip()
+ m = pattern.match(vio_name)
+ if m:
+ layer = m.group(1).split(".")[0]
+ message_prefix = (
+ " violation type: " + cleanup(vio_name) + "\n srcs: N/A N/A\n"
+ )
+ for vio in drcSections[i + 1].split("\n"):
+ vio_cor = vio.strip().replace("um", "").split()
+ if len(vio_cor) > 3:
+ vio_line = (
+ message_prefix
+ + " bbox = ( "
+ + vio_cor[0]
+ + ", "
+ + vio_cor[1]
+ + " ) - ( "
+ + vio_cor[2]
+ + ", "
+ + vio_cor[3]
+ + " ) on Layer "
+ + layer
+ )
+ printArr.append(vio_line)
+else:
+ printArr.append("Source not found.")
+
+# write into file
+outputFileOpener = open(output_file, "w")
+outputFileOpener.write("\n".join(printArr))
+outputFileOpener.close()
diff --git a/openlane/scripts/manual_macro_place.py b/openlane/scripts/manual_macro_place.py
new file mode 100644
index 0000000..9efb07f
--- /dev/null
+++ b/openlane/scripts/manual_macro_place.py
@@ -0,0 +1,144 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+
+"""
+
+import argparse
+import os
+import odb
+
+parser = argparse.ArgumentParser(
+ description="Places macros in positions and orientations specified by a config file"
+)
+
+parser.add_argument(
+ "--lef",
+ "-l",
+ nargs="+",
+ type=str,
+ default=None,
+ required=True,
+ help="Input LEF file(s)",
+)
+
+parser.add_argument(
+ "--input-def",
+ "-id",
+ required=True,
+ help="DEF view of the design that needs to have its instances placed",
+)
+
+parser.add_argument("--output-def", "-o", required=True, help="Output placed DEF file")
+
+parser.add_argument("--config", "-c", required=True, help="Configuration file")
+
+parser.add_argument(
+ "--fixed",
+ "-f",
+ action="store_true",
+ default=False,
+ help="a flag to signal whether the placement should be fixed or placed",
+)
+
+args = parser.parse_args()
+input_lef_file_names = args.lef
+input_def_file_name = args.input_def
+output_def_file_name = args.output_def
+config_file_name = args.config
+fixed_flag = args.fixed
+
+LEF2OA_MAP = {
+ "N": "R0",
+ "S": "R180",
+ "W": "R90",
+ "E": "R270",
+ "FN": "MY",
+ "FS": "MX",
+ "FW": "MXR90",
+ "FE": "MYR90",
+}
+
+
+def lef_rot_to_oa_rot(rot):
+ if rot in LEF2OA_MAP:
+ return LEF2OA_MAP[rot]
+ else:
+ assert rot in [item[1] for item in LEF2OA_MAP.items()], rot
+ return rot
+
+
+def gridify(n, f):
+ """
+ e.g., (1.1243, 0.005) -> 1.120
+ """
+ return round(n / f) * f
+
+
+# read config
+macros = {}
+with open(config_file_name, "r") as config_file:
+ for line in config_file:
+ # Discard comments and empty lines
+ line = line.split("#")[0].strip()
+ if not line:
+ continue
+ line = line.split()
+ macros[line[0]] = [
+ str(int(float(line[1]) * 1000)),
+ str(int(float(line[2]) * 1000)),
+ line[3],
+ ]
+
+print("Placing the following macros:")
+print(macros)
+
+db_design = odb.dbDatabase.create()
+
+for lef in input_lef_file_names:
+ odb.read_lef(db_design, lef)
+odb.read_def(db_design, input_def_file_name)
+
+chip_design = db_design.getChip()
+block_design = chip_design.getBlock()
+top_design_name = block_design.getName()
+print("Design name:", top_design_name)
+
+macros_cnt = len(macros)
+for inst in block_design.getInsts():
+ inst_name = inst.getName()
+ if inst.isFixed():
+ assert inst_name not in macros, inst_name
+ continue
+ if inst_name in macros:
+ print("Placing", inst_name)
+ macro_data = macros[inst_name]
+ x = gridify(int(macro_data[0]), 5)
+ y = gridify(int(macro_data[1]), 5)
+ inst.setOrient(lef_rot_to_oa_rot(macro_data[2]))
+ inst.setLocation(x, y)
+ if fixed_flag:
+ inst.setPlacementStatus("FIRM")
+ else:
+ inst.setPlacementStatus("PLACED")
+ del macros[inst_name]
+
+assert not macros, ("Macros not found:", macros)
+
+print("Successfully placed", macros_cnt, "instances")
+
+odb.write_def(block_design, output_def_file_name)
+assert os.path.exists(output_def_file_name), "Output not written successfully"
diff --git a/openlane/scripts/mergeLef.py b/openlane/scripts/mergeLef.py
new file mode 100755
index 0000000..4e619c5
--- /dev/null
+++ b/openlane/scripts/mergeLef.py
@@ -0,0 +1,106 @@
+#!/usr/bin/env python3
+# From: https://github.com/The-OpenROAD-Project/OpenROAD-flow/blob/master/flow/util/mergeLef.py
+# Copyright 2020 The OpenROAD Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import os
+import argparse # argument parsing
+
+# WARNING: this script expects the tech lef first
+
+# Parse and validate arguments
+# ==============================================================================
+parser = argparse.ArgumentParser(description="Merges lefs together")
+parser.add_argument("--inputLef", "-i", required=True, help="Input Lef", nargs="+")
+parser.add_argument("--outputLef", "-o", required=True, help="Output Lef")
+args = parser.parse_args()
+
+
+def get_delimited_blocks(data):
+ # MACRO and SITE blocks
+ # assumes correctly indented LEF; otherwise, assertions should fail
+ blocks = []
+
+ current_block_name = None
+ block_content = []
+ for line in data.splitlines():
+ if line.startswith("MACRO") or line.startswith("SITE"):
+ assert current_block_name is None, (current_block_name, line)
+ assert not block_content, block_content
+ tokens = line.split()
+ assert len(tokens) == 2, line
+ current_block_name = tokens[1]
+ block_content.append(line)
+ elif current_block_name is not None:
+ block_content.append(line)
+ if line.startswith("END"):
+ assert line != "END LIBRARY", current_block_name
+ tokens = line.split()
+ assert len(tokens) == 2, line
+ assert tokens[1] == current_block_name, (line, current_block_name)
+ blocks.append("\n".join(block_content))
+ current_block_name = None
+ block_content = []
+
+ assert not current_block_name, current_block_name
+ assert not block_content, block_content
+ return blocks
+
+
+print(os.path.basename(__file__), ": Merging LEFs")
+
+f = open(args.inputLef[0])
+content = f.read()
+f.close()
+
+# Remove Last line ending the library
+content = re.sub("END LIBRARY", "", content)
+
+content = content.splitlines()
+
+lefs = args.inputLef[1:]
+if len(lefs) == 1:
+ lefs = lefs[0].split()
+
+# Iterate through additional lefs
+for lefFile in lefs:
+ f = open(lefFile)
+ snippet = f.read()
+ f.close()
+
+ snippet = snippet.replace("END LIBRARY", "")
+
+ blocks = get_delimited_blocks(snippet)
+ site_cnt = 0
+ macro_cnt = 0
+ for block in blocks:
+ if block.startswith("MACRO"):
+ macro_cnt += 1
+ else:
+ assert block.startswith("SITE"), block
+ site_cnt += 1
+
+ print(os.path.basename(lefFile) + ": SITEs matched found:", site_cnt)
+ print(os.path.basename(lefFile) + ": MACROs matched found:", macro_cnt)
+
+ content.extend(blocks)
+
+content.append("END LIBRARY")
+
+f = open(args.outputLef, "w")
+f.write("\n".join(content))
+f.close()
+
+print(os.path.basename(__file__), ": Merging LEFs complete")
diff --git a/openlane/scripts/mergeLib.py b/openlane/scripts/mergeLib.py
new file mode 100644
index 0000000..b024498
--- /dev/null
+++ b/openlane/scripts/mergeLib.py
@@ -0,0 +1,88 @@
+#!/usr/bin/env python3
+# Copyright 2022 Efabless Corporation
+# Copyright 2020 The OpenROAD Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Direct-translated (more or less) from Perl to Python by Donn.
+
+import click
+
+import re
+import io
+
+library_start_rx = re.compile(r"library\s*\(")
+cell_start_rx = re.compile(r"^\s*cell\s*\(")
+
+
+def write_header(output_file: io.IOBase, final_library_name: str, input_str: str):
+ f = output_file
+
+ for line in input_str.split("\n"):
+ if library_start_rx.match(line) is not None:
+ print(f"library ({final_library_name}) {{", file=f)
+ elif cell_start_rx.match(line) is not None:
+ break
+ else:
+ print(line, file=f)
+
+
+def write_footer(output_file: io.IOBase):
+ f = output_file
+
+ print("\n}", file=f)
+
+
+@click.command()
+@click.option("-o", "--output", required=True, help="Output file")
+@click.option("-n", "--name", required=True, help="The name of the final library")
+@click.argument("input_libs", nargs=-1)
+def mergeLib(output, name, input_libs):
+ file_strings = [open(input_lib).read() for input_lib in input_libs]
+ out_str = ""
+
+ with io.StringIO() as f:
+ # Write everything up until (and excluding) the first cell to f,
+ # replacing the library() header with a new name
+ write_header(f, name, file_strings[0])
+
+ # Find and write cells (and cells only)
+ for input_str in file_strings:
+ brace_count = 0
+ for line in input_str.split("\n"):
+ if cell_start_rx.match(line) is not None:
+ if brace_count != 0:
+ raise Exception(
+ "Error: New cell before finishing the previous one."
+ )
+ else:
+ print(f"\n{line}", file=f)
+ brace_count += 1
+ elif brace_count > 0:
+ if "{" in line:
+ brace_count += 1
+ if "}" in line:
+ brace_count -= 1
+ print(line, file=f)
+
+ # Write a footer (just a })
+ write_footer(f)
+
+ out_str = f.getvalue()
+
+ with open(output, "w") as f:
+ f.write(out_str)
+
+
+if __name__ == "__main__":
+ mergeLib()
diff --git a/openlane/scripts/most_recent_run.py b/openlane/scripts/most_recent_run.py
new file mode 100644
index 0000000..e784db8
--- /dev/null
+++ b/openlane/scripts/most_recent_run.py
@@ -0,0 +1,45 @@
+#!/usr/bin/env python3
+# Copyright 2022 Efabless Corporation
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import click
+
+
+@click.command("most_recent_run")
+@click.argument("runs_directory")
+def main(runs_directory):
+ max_time = 0
+ latest_run_name = None
+ if not os.path.isdir(runs_directory):
+ print(f"No runs found at '{runs_directory}'.", file=sys.stderr)
+ exit(os.EX_NOINPUT)
+ for run in os.listdir(runs_directory):
+ run_folder_path = os.path.join(runs_directory, run)
+ if not os.path.isdir(run_folder_path):
+ continue
+ time = os.stat(run_folder_path).st_mtime
+ if time > max_time:
+ latest_run_name = run
+
+ if latest_run_name is not None:
+ print(latest_run_name, end="")
+ else:
+ print(f"No runs found at '{runs_directory}'.", file=sys.stderr)
+ exit(os.EX_NOINPUT)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/openlane/scripts/new_tracks.py b/openlane/scripts/new_tracks.py
new file mode 100644
index 0000000..4b5d700
--- /dev/null
+++ b/openlane/scripts/new_tracks.py
@@ -0,0 +1,75 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import argparse
+
+EXAMPLE_INPUT = """
+li1 X 0.23 0.46
+li1 Y 0.17 0.34
+met1 X 0.17 0.34
+met1 Y 0.17 0.34
+met2 X 0.23 0.46
+met2 Y 0.23 0.46
+met3 X 0.34 0.68
+met3 Y 0.34 0.68
+met4 X 0.46 0.92
+met4 Y 0.46 0.92
+met5 X 1.70 3.40
+met5 Y 1.70 3.40
+"""
+
+
+def old_to_new_tracks(old_tracks: str) -> str:
+ """
+ >>> old_to_new_tracks(EXAMPLE_INPUT)
+ 'make_tracks li1 -x_offset 0.23 -x_pitch 0.46 -y_offset 0.17 -y_pitch 0.34\\nmake_tracks met1 -x_offset 0.17 -x_pitch 0.34 -y_offset 0.17 -y_pitch 0.34\\nmake_tracks met2 -x_offset 0.23 -x_pitch 0.46 -y_offset 0.23 -y_pitch 0.46\\nmake_tracks met3 -x_offset 0.34 -x_pitch 0.68 -y_offset 0.34 -y_pitch 0.68\\nmake_tracks met4 -x_offset 0.46 -x_pitch 0.92 -y_offset 0.46 -y_pitch 0.92\\nmake_tracks met5 -x_offset 1.70 -x_pitch 3.40 -y_offset 1.70 -y_pitch 3.40\\n'
+ """
+ old_tracks_lines = old_tracks.split("\n")
+ layers = {}
+
+ for line in old_tracks_lines:
+ if re.match(r"^\s*$", line):
+ continue
+ layer, cardinal, offset, pitch = re.split(r"\s+", line)
+ layers[layer] = layers.get(layer) or {}
+ layers[layer][cardinal] = (offset, pitch)
+
+ final_str = ""
+ for layer, data in layers.items():
+ x_offset, x_pitch = data["X"]
+ y_offset, y_pitch = data["Y"]
+ final_str += f"make_tracks {layer} -x_offset {x_offset} -x_pitch {x_pitch} -y_offset {y_offset} -y_pitch {y_pitch}\n"
+
+ return final_str
+
+
+if __name__ == "__main__":
+ parser = argparse.ArgumentParser(
+ description="Converts an old tracks.info file to a new .tracks file as dictated by OpenROAD."
+ )
+
+ parser.add_argument("--input_file", "-i", required=True, help="input tracks.info")
+
+ parser.add_argument(
+ "--output_file", "-o", required=True, help="output .tracks file"
+ )
+
+ args = parser.parse_args()
+
+ tracks_info_str = open(args.input_file).read()
+
+ with open(args.output_file, "w") as f:
+ f.write(old_to_new_tracks(tracks_info_str))
diff --git a/openlane/scripts/obs.py b/openlane/scripts/obs.py
new file mode 100755
index 0000000..436671f
--- /dev/null
+++ b/openlane/scripts/obs.py
@@ -0,0 +1,67 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# takes a lef file and a y position => obstructs everything above
+import sys
+
+ARGV = sys.argv
+if len(ARGV) < 5:
+ print("Usage " + ARGV[0] + " llx lly urx ury")
+ sys.exit(-1)
+LLX = float(ARGV[1])
+LLY = float(ARGV[2])
+URX = float(ARGV[3])
+URY = float(ARGV[4])
+LAYER_LIST = ["li1", "met1", "met2", "met3", "met4", "met5"]
+
+
+def print_obs_section():
+ for layer in LAYERS:
+ print(" LAYER %s ;" % (layer))
+ print(" RECT %f %f %s %s ;" % (LLX, LLY, URX, URY))
+
+
+obs_section = False
+macro_name = None
+for line in sys.stdin:
+ if line.isspace():
+ continue
+
+ if line.startswith("MACRO"):
+ macro_name = line.split()[1]
+ LAYERS = {layer: False for layer in LAYER_LIST}
+
+ if macro_name and line.startswith("END " + macro_name):
+ macro_name = None
+ if not any(layer[1] for layer in LAYERS.items()):
+ print(" OBS")
+ print_obs_section()
+ print(" END")
+
+ if line.find("OBS") != -1:
+ obs_section = True
+ elif obs_section and line.find("END") != -1:
+ obs_section = False
+ for layer in LAYERS: # draw remaining obs on layers that didn't appear
+ if not LAYERS[layer]:
+ LAYERS[layer] = True
+ print(" LAYER %s ;" % (layer))
+ print(" RECT %.3f %.3f %.3f %.3f ;" % (LLX, LLY, URX, URY))
+
+ print(line, end="")
+ if obs_section and line.find("LAYER") != -1:
+ line = line.split()
+ LAYERS[line[1]] = True
+ print(" RECT %.3f %.3f %.3f %.3f ;" % (LLX, LLY, URX, URY))
diff --git a/openlane/scripts/openroad/antenna_check.tcl b/openlane/scripts/openroad/antenna_check.tcl
new file mode 100755
index 0000000..ca903ac
--- /dev/null
+++ b/openlane/scripts/openroad/antenna_check.tcl
@@ -0,0 +1,29 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+# load layers' antenna rules into ARC
+#load_antenna_rules
+
+# start checking antennas and generate a detail report
+check_antennas -report_file $::env(signoff_reports)/antenna.rpt
diff --git a/openlane/scripts/openroad/basic_mp.tcl b/openlane/scripts/openroad/basic_mp.tcl
new file mode 100755
index 0000000..34c6278
--- /dev/null
+++ b/openlane/scripts/openroad/basic_mp.tcl
@@ -0,0 +1,38 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+foreach lib $::env(LIB_SYNTH) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+macro_placement\
+ -channel $::env(PL_MACRO_CHANNEL)\
+ -halo $::env(PL_MACRO_HALO)
+
+write_def $::env(SAVE_DEF)
diff --git a/openlane/scripts/openroad/cts.tcl b/openlane/scripts/openroad/cts.tcl
new file mode 100755
index 0000000..3333e74
--- /dev/null
+++ b/openlane/scripts/openroad/cts.tcl
@@ -0,0 +1,111 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_CTS) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+
+set max_slew [expr {$::env(SYNTH_MAX_TRAN) * 1e-9}]; # must convert to seconds
+set max_cap [expr {$::env(CTS_MAX_CAP) * 1e-12}]; # must convert to farad
+# set rc values
+source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+estimate_parasitics -placement
+
+# Clone clock tree inverters next to register loads
+# so cts does not try to buffer the inverted clocks.
+repair_clock_inverters
+
+puts "\[INFO\]: Configuring cts characterization..."
+configure_cts_characterization\
+ -max_slew $max_slew\
+ -max_cap $max_cap
+
+puts "\[INFO]: Performing clock tree synthesis..."
+puts "\[INFO]: Looking for the following net(s): $::env(CLOCK_NET)"
+puts "\[INFO]: Running Clock Tree Synthesis..."
+
+set arg_list [list]
+
+lappend arg_list -buf_list $::env(CTS_CLK_BUFFER_LIST)
+lappend arg_list -root_buf $::env(CTS_ROOT_BUFFER)
+lappend arg_list -sink_clustering_size $::env(CTS_SINK_CLUSTERING_SIZE)
+lappend arg_list -sink_clustering_max_diameter $::env(CTS_SINK_CLUSTERING_MAX_DIAMETER)
+lappend arg_list -sink_clustering_enable
+
+if { $::env(CTS_DISTANCE_BETWEEN_BUFFERS) != 0 } {
+ lappend arg_list -distance_between_buffers $::env(CTS_DISTANCE_BETWEEN_BUFFERS)
+}
+
+if { $::env(CTS_DISABLE_POST_PROCESSING) } {
+ lappend arg_list -post_cts_disable
+}
+
+clock_tree_synthesis {*}$arg_list
+
+set_propagated_clock [all_clocks]
+
+estimate_parasitics -placement
+puts "\[INFO]: Repairing long wires on clock nets..."
+# CTS leaves a long wire from the pad to the clock tree root.
+repair_clock_nets -max_wire_length $::env(CTS_CLK_MAX_WIRE_LENGTH)
+
+estimate_parasitics -placement
+write_def $::env(SAVE_DEF)
+
+set buffers "$::env(CTS_ROOT_BUFFER) $::env(CTS_CLK_BUFFER_LIST)"
+set_placement_padding -masters $buffers -left $::env(CELL_PAD)
+puts "\[INFO\]: Legalizing..."
+detailed_placement
+if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
+ optimize_mirroring
+}
+estimate_parasitics -placement
+
+write_def $::env(SAVE_DEF)
+write_sdc $::env(SAVE_SDC)
+if { [catch {check_placement -verbose} errmsg] } {
+ puts stderr $errmsg
+ exit 1
+}
+
+puts "cts_report"
+report_cts
+puts "cts_report_end"
+
+if {[info exists ::env(CLOCK_PORT)]} {
+ if { [info exists ::env(CTS_REPORT_TIMING)] && $::env(CTS_REPORT_TIMING) } {
+ set ::env(RUN_STANDALONE) 0
+ source $::env(SCRIPTS_DIR)/openroad/sta.tcl
+ }
+} else {
+ puts "\[WARN\]: No CLOCK_PORT found. Skipping STA..."
+}
diff --git a/openlane/scripts/openroad/diodes.tcl b/openlane/scripts/openroad/diodes.tcl
new file mode 100755
index 0000000..1b4c1a3
--- /dev/null
+++ b/openlane/scripts/openroad/diodes.tcl
@@ -0,0 +1,100 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# NORMAL MODE: inserts diode cells
+# OPTIMIZED MODE: inserts a fake diode, to be replaced later with a real diode if necessary
+
+set input_def $::env(CURRENT_DEF)
+set input_lef $::env(MERGED_LEF_UNPADDED)
+set output_def $::env(SAVE_DEF)
+
+read_lef $input_lef
+read_def $input_def
+
+set ::PREFIX ANTENNA
+set ::VERBOSE 0
+set ::block [[[::ord::get_db] getChip] getBlock]
+set ::antenna_pin_name $::env(DIODE_CELL_PIN)
+set ::nets [$::block getNets]
+
+if { $::env(DIODE_INSERTION_STRATEGY) == 2 } {
+ if { ! [info exists ::env(FAKEDIODE_CELL)] } {
+ puts "\[ERROR\]: FAKEDIODE_CELL is undefined. Try a different DIODE_INSERTION_STRATEGY."
+ exit 1
+ }
+ set ::antenna_cell_name $::env(FAKEDIODE_CELL)
+} else {
+ set ::antenna_cell_name $::env(DIODE_CELL)
+}
+
+proc add_antenna_cell { iterm } {
+ set antenna_master [[::ord::get_db] findMaster $::antenna_cell_name]
+ set antenna_mterm [$antenna_master getMTerms]
+
+ set iterm_net [$iterm getNet]
+ set iterm_inst [$iterm getInst]
+ set iterm_inst_name [$iterm_inst getName]
+ set iterm_pin_name [[$iterm getMTerm] getConstName]
+ set inst_ori [$iterm_inst getOrient]
+
+ foreach {success avg_iterm_x avg_iterm_y} [$iterm getAvgXY] {}
+ if { ! $success } {
+ foreach {avg_iterm_x avg_iterm_y} [$iterm_inst getLocation] {}
+ }
+
+ set antenna_inst_name ${::PREFIX}_${iterm_inst_name}_${iterm_pin_name}
+ # create a 2-node "subnet" for the antenna (for easy removal) -> doesn't work
+ # set antenna_subnet [odb::dbNet_create $::block NET_${antenna_inst_name}]
+ set antenna_inst [odb::dbInst_create $::block $antenna_master $antenna_inst_name]
+ set antenna_iterm [$antenna_inst findITerm $::antenna_pin_name]
+
+ $antenna_inst setLocation $avg_iterm_x $avg_iterm_y
+ $antenna_inst setOrient $inst_ori
+ $antenna_inst setPlacementStatus PLACED
+ $antenna_iterm connect $iterm_net
+
+ if { $::VERBOSE } {
+ puts "\[INFO\]: Adding $antenna_inst_name on subnet $antenna_subnet for cell $iterm_inst_name pin $iterm_pin_name"
+ }
+}
+
+set count 0
+puts "\[INFO\]: Inserting $::antenna_cell_name..."
+foreach net $::nets {
+ set net_name [$net getName]
+ if { [expr {$net_name eq $::env(VDD_PIN)} || {$net_name eq $::env(GND_PIN)}] } {
+ puts "\[WARN\]: Skipping $net_name"
+ } else {
+ set iterms [$net getITerms]
+ foreach iterm $iterms {
+ if { [$iterm isInputSignal] } {
+ add_antenna_cell $iterm
+ set count [expr $count + 1]
+ }
+ }
+ }
+}
+puts "\n\[INFO\]: $count of $::antenna_cell_name inserted!"
+set_placement_padding -masters $::env(DIODE_CELL) -left $::env(DIODE_PADDING)
+puts "\[INFO\]: Legalizing..."
+detailed_placement
+if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
+ optimize_mirroring
+}
+write_def $::env(SAVE_DEF)
+
+if { [catch {check_placement -verbose} errmsg] } {
+ puts stderr $errmsg
+ exit 1
+}
diff --git a/openlane/scripts/openroad/droute.tcl b/openlane/scripts/openroad/droute.tcl
new file mode 100755
index 0000000..97c44d1
--- /dev/null
+++ b/openlane/scripts/openroad/droute.tcl
@@ -0,0 +1,49 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+set_thread_count $::env(ROUTING_CORES)
+
+set min_layer $::env(RT_MIN_LAYER)
+if { [info exists ::env(DRT_MIN_LAYER)] } {
+ set min_layer $::env(DRT_MIN_LAYER)
+}
+
+set max_layer $::env(RT_MAX_LAYER)
+if { [info exists ::env(DRT_MAX_LAYER)] } {
+ set max_layer $::env(DRT_MAX_LAYER)
+}
+
+detailed_route\
+ -guide $::env(CURRENT_GUIDE)\
+ -bottom_routing_layer $min_layer\
+ -top_routing_layer $max_layer\
+ -output_guide $::env(TRITONROUTE_FILE_PREFIX).guide\
+ -output_maze $::env(TRITONROUTE_FILE_PREFIX)_maze.log\
+ -output_drc $::env(TRITONROUTE_RPT_PREFIX).drc\
+ -droute_end_iter $::env(DRT_OPT_ITERS)\
+ -or_seed 42\
+ -verbose 1
+
+puts stderr "Saving to $::env(SAVE_DEF)"
+write_def $::env(SAVE_DEF)
\ No newline at end of file
diff --git a/openlane/scripts/openroad/eco.tcl b/openlane/scripts/openroad/eco.tcl
new file mode 100644
index 0000000..dd7367b
--- /dev/null
+++ b/openlane/scripts/openroad/eco.tcl
@@ -0,0 +1,101 @@
+# Copyright 2021 The University of Michigan
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+source $::env(SCRIPTS_DIR)/openroad/insert_buffer.tcl
+
+proc move_to_dir {filenames dirname} {
+ foreach filename $filenames {
+ file rename $filename [file join $dirname [file tail $filename]]
+ }
+}
+
+proc pause {{message "Press enter to continue ==> "}} {
+ puts -nonewline $message
+ flush stdout
+ gets stdin
+}
+
+proc size_cell {inst_name new_master_name} {
+ set db [ord::get_db]
+ set new_master [$db findMaster $new_master_name]
+
+ set block [ord::get_db_block]
+ set inst [$block findInst $inst_name]
+ $inst swapMaster $new_master
+}
+
+proc run_eco {args} {
+ set cur_iter [expr $::env(ECO_ITER) == 0 ? 0 : expr {$::env(ECO_ITER) -1}]]
+ # Uncomment to source the generated fix
+ # Currently args in the fix tcl has some bugs:
+ # 1st argument of insert_buffer (pin_name) not found
+ source "$::env(eco_results)/fix/eco_fix_$cur_iter.tcl"
+
+ # Run detailed placement
+ detailed_placement
+
+ # Destroy faulty connections
+ set block [ord::get_db_block]
+ set nets [$block getNets]
+
+ foreach net $nets {
+ set wire [$net getWire]
+ if {$wire != "NULL"} {
+ [odb::dbWire_destroy $wire]
+ }
+ }
+
+}
+
+foreach lib $::env(LIB_CTS) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+set cur_iter [expr $::env(ECO_ITER) == 0 ? \
+ 0 : \
+ [expr {$::env(ECO_ITER) -1}] \
+]
+
+if {[expr {$cur_iter == 0}]} {
+ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+} else {
+ if {[catch {read_def \
+ $::env(eco_results)/def/eco_$cur_iter.def} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+set_propagated_clock [all_clocks]
+
+run_eco
+
+write_verilog $::env(eco_results)/net/eco_$::env(ECO_ITER).v
+write_def $::env(eco_results)/def/eco_$::env(ECO_ITER).def
diff --git a/openlane/scripts/openroad/fill.tcl b/openlane/scripts/openroad/fill.tcl
new file mode 100755
index 0000000..80d424c
--- /dev/null
+++ b/openlane/scripts/openroad/fill.tcl
@@ -0,0 +1,26 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+filler_placement "$::env(DECAP_CELL) $::env(FILL_CELL)"
+
+write_def $::env(SAVE_DEF)
diff --git a/openlane/scripts/openroad/floorplan.tcl b/openlane/scripts/openroad/floorplan.tcl
new file mode 100755
index 0000000..55cb6f8
--- /dev/null
+++ b/openlane/scripts/openroad/floorplan.tcl
@@ -0,0 +1,105 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_verilog $::env(synthesis_results)/$::env(DESIGN_NAME).v
+link_design $::env(DESIGN_NAME)
+read_sdc -echo $::env(CURRENT_SDC)
+unset_propagated_clock [all_clocks]
+
+set bottom_margin [expr $::env(PLACE_SITE_HEIGHT) * $::env(BOTTOM_MARGIN_MULT)]
+set top_margin [expr $::env(PLACE_SITE_HEIGHT) * $::env(TOP_MARGIN_MULT)]
+set left_margin [expr $::env(PLACE_SITE_WIDTH) * $::env(LEFT_MARGIN_MULT)]
+set right_margin [expr $::env(PLACE_SITE_WIDTH) * $::env(RIGHT_MARGIN_MULT)]
+
+if {$::env(FP_SIZING) == "absolute"} {
+ if { ! [info exists ::env(CORE_AREA)] } {
+ set die_ll_x [lindex $::env(DIE_AREA) 0]
+ set die_ll_y [lindex $::env(DIE_AREA) 1]
+ set die_ur_x [lindex $::env(DIE_AREA) 2]
+ set die_ur_y [lindex $::env(DIE_AREA) 3]
+
+ set core_ll_x [expr {$die_ll_x + $left_margin}]
+ set core_ll_y [expr {$die_ll_y + $bottom_margin}]
+ set core_ur_x [expr {$die_ur_x - $right_margin}]
+ set core_ur_y [expr {$die_ur_y - $top_margin}]
+
+ set ::env(CORE_AREA) [list $core_ll_x $core_ll_y $core_ur_x $core_ur_y]
+ } else {
+ puts "\[INFO] Using the set CORE_AREA; ignoring core margin parameters"
+ }
+
+ initialize_floorplan \
+ -die_area $::env(DIE_AREA) \
+ -core_area $::env(CORE_AREA) \
+ -site $::env(PLACE_SITE)
+
+} else {
+
+ initialize_floorplan \
+ -utilization $::env(FP_CORE_UTIL) \
+ -aspect_ratio $::env(FP_ASPECT_RATIO) \
+ -core_space "$bottom_margin $top_margin $left_margin $right_margin" \
+ -site $::env(PLACE_SITE)
+
+ set ::chip [[::ord::get_db] getChip]
+ set ::tech [[::ord::get_db] getTech]
+ set ::block [$::chip getBlock]
+ puts "\[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan"
+ set ::env(DIE_AREA) [list]
+ set ::env(CORE_AREA) [list]
+
+ set die_area [$::block getDieArea]
+ set core_area [$::block getCoreArea]
+
+ set die_area [list [$die_area xMin] [$die_area yMin] [$die_area xMax] [$die_area yMax]]
+ set core_area [list [$core_area xMin] [$core_area yMin] [$core_area xMax] [$core_area yMax]]
+
+ set dbu [$tech getDbUnitsPerMicron]
+
+ foreach coord $die_area {
+ lappend ::env(DIE_AREA) [expr {1.0 * $coord / $dbu}]
+ }
+ foreach coord $core_area {
+ lappend ::env(CORE_AREA) [expr {1.0 * $coord / $dbu}]
+ }
+
+ puts "\[INFO] Floorplanned on a die area of $::env(DIE_AREA) (microns). Saving to $::env(fp_report_prefix)_die_area.rpt."
+ puts "\[INFO] Floorplanned on a core area of $::env(CORE_AREA) (microns). Saving to $::env(fp_report_prefix)_core_area.rpt."
+}
+source $::env(TRACKS_INFO_FILE_PROCESSED)
+
+set die_area_file [open $::env(fp_report_prefix)_die_area.rpt w]
+set core_area_file [open $::env(fp_report_prefix)_core_area.rpt w]
+ puts -nonewline $die_area_file $::env(DIE_AREA)
+ puts -nonewline $core_area_file $::env(CORE_AREA)
+close $core_area_file
+close $die_area_file
+
+write_def $::env(SAVE_DEF)
+write_sdc $::env(SAVE_SDC)
diff --git a/openlane/scripts/openroad/groute.tcl b/openlane/scripts/openroad/groute.tcl
new file mode 100644
index 0000000..d0ad8a0
--- /dev/null
+++ b/openlane/scripts/openroad/groute.tcl
@@ -0,0 +1,78 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+set_propagated_clock [all_clocks]
+
+if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
+ set_placement_padding -masters $::env(DIODE_CELL) -left $::env(DIODE_PADDING)
+}
+
+source $::env(SCRIPTS_DIR)/openroad/set_routing_layers.tcl
+
+set_macro_extension $::env(GLB_RT_MACRO_EXTENSION)
+
+source $::env(SCRIPTS_DIR)/openroad/layer_adjustments.tcl
+
+set arg_list [list]
+lappend arg_list -congestion_iterations $::env(GLB_RT_OVERFLOW_ITERS)
+lappend arg_list -verbose
+if { $::env(GLB_RT_ALLOW_CONGESTION) == 1 } {
+ lappend arg_list -allow_congestion
+}
+puts $arg_list
+global_route {*}$arg_list
+
+if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
+ repair_antennas "$::env(DIODE_CELL)/$::env(DIODE_CELL_PIN)" -iterations $::env(GLB_RT_ANT_ITERS)
+ check_placement
+}
+
+
+write_guides $::env(SAVE_GUIDE)
+write_def $::env(SAVE_DEF)
+
+if {[info exists ::env(CLOCK_PORT)]} {
+ if { $::env(GLB_RT_ESTIMATE_PARASITICS) == 1 } {
+ # set rc values
+ source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+ # estimate wire rc parasitics
+ estimate_parasitics -global_routing
+
+ set ::env(RUN_STANDALONE) 0
+ source $::env(SCRIPTS_DIR)/openroad/sta.tcl
+ }
+} else {
+ puts "\[WARN\]: No CLOCK_PORT found. Skipping STA..."
+}
diff --git a/openlane/scripts/openroad/gui.tcl b/openlane/scripts/openroad/gui.tcl
new file mode 100644
index 0000000..922f4f1
--- /dev/null
+++ b/openlane/scripts/openroad/gui.tcl
@@ -0,0 +1,23 @@
+# Copyright 2022 The Regents of the University of California
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
diff --git a/openlane/scripts/openroad/insert_buffer.tcl b/openlane/scripts/openroad/insert_buffer.tcl
new file mode 100644
index 0000000..65c1207
--- /dev/null
+++ b/openlane/scripts/openroad/insert_buffer.tcl
@@ -0,0 +1,134 @@
+# Copyright 2021 The University of Michigan
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc insert_buffer {pin_name pin_type master_name net_name inst_name} {
+ set db [ord::get_db]
+ set block [ord::get_db_block]
+
+ # Create buffer instance
+ set master [$db findMaster $master_name]
+ if { $master == "NULL" } {
+ puts "Buffer cell '$master' not found."
+ exit -1
+ }
+
+ set inst [odb::dbInst_create $block $master $inst_name]
+
+ # Figure out the inputs & outputs of the master
+ foreach mterm [$master getMTerms] {
+ if {[$mterm getSigType] == "POWER"} {
+ continue
+ }
+ if {[$mterm getSigType] == "GROUND"} {
+ continue
+ }
+ if {[$mterm getIoType] == "INPUT"} {
+ set input $mterm
+ }
+ if {[$mterm getIoType] == "OUTPUT"} {
+ set output $mterm
+ }
+ }
+
+ # New net to connect to
+ set new_net [odb::dbNet_create $block $net_name]
+
+ if {$pin_type=="ITerm"} {
+ # Finding the block with pin name
+ set iterm [$block findITerm $pin_name]
+ if { $iterm == "NULL" } {
+ puts "Instance terminal '$pin_name' not found."
+ exit -1
+ }
+ set old_net [$iterm getNet]
+
+ # Original disconnect command
+ odb::dbITerm_disconnect $iterm
+
+ # Original connect command
+ odb::dbITerm_connect $iterm $new_net
+
+ # Set I/O of iterm (Buffer)
+ set in_iterm [$inst getITerm $input]
+ set out_iterm [$inst getITerm $output]
+
+ if { ![info exists ::env(INSERT_BUFFER_NO_PLACE)] } {
+ # define the instance to which the buffer inserted will connected to
+ set master_inst [$iterm getInst]
+ # get the geometry of the instance, geometry means its shape, the coordinate of its vertex...
+ set box [$master_inst getBBox]
+
+ # get the position of the lower left point of this instance
+ set x_min [$box xMin]
+ set y_min [$box yMin]
+
+ # $inst is the buffer we want to insert, now insert it in the position of the instance it is connected to,
+ # using setLocation, and detail_place will help us separate them
+ [$inst setLocation $x_min $y_min]
+ [$inst setPlacementStatus PLACED]
+ }
+
+ odb::dbITerm_connect $in_iterm $new_net
+ odb::dbITerm_connect $out_iterm $old_net
+
+ } else {
+ # Finding the block with pin name
+ set bterm [$block findBTerm $pin_name]
+ set old_net [$bterm getNet]
+ set net_out_iterm [odb::dbNet_get1stITerm $old_net]
+ set old_net_inst [$net_out_iterm getInst]
+ set net_mterm [$net_out_iterm getMTerm]
+ set old_net_input $net_mterm
+ odb::dbITerm_disconnect $net_out_iterm
+
+ if { ![info exists ::env(INSERT_BUFFER_NO_PLACE)] } {
+ set box [$bterm getBBox]
+
+ # get the position of the lower left point of this instance
+ set x_min [$box xMin]
+ set y_min [$box yMin]
+
+ # $inst is the buffer we want to insert, now insert it in the position of the instance it is connected to,
+ # using setLocation, and detail_place will help us separate them
+ [$inst setLocation $x_min $y_min]
+ [$inst setPlacementStatus PLACED]
+ }
+
+ # Find output/input of buffer iterm
+ set in_iterm [$inst getITerm $input]
+ set out_iterm [$inst getITerm $output]
+
+ odb::dbITerm_connect $out_iterm $new_net
+ odb::dbITerm_connect $net_out_iterm $new_net
+ odb::dbITerm_connect $in_iterm $old_net
+ }
+}
+
+if { [info exists ::env(INSERT_BUFFER_COMMAND) ]} {
+ if {[catch {read_lef $::env(MERGED_LEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+
+ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+
+ set arg_list [split $::env(INSERT_BUFFER_COMMAND) " "]
+ insert_buffer {*}$arg_list
+
+ write_def $::env(SAVE_DEF)
+}
\ No newline at end of file
diff --git a/openlane/scripts/openroad/ioplacer.tcl b/openlane/scripts/openroad/ioplacer.tcl
new file mode 100755
index 0000000..baf15b6
--- /dev/null
+++ b/openlane/scripts/openroad/ioplacer.tcl
@@ -0,0 +1,62 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { [info exists ::env(CONTEXTUAL_IO_FLAG)] } {
+ read_lef $::env(placement_tmpfiles)/top_level.lef
+ #ppl::set_num_slots 2
+}
+
+if {[catch {read_lef $::env(MERGED_LEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {$::env(FP_IO_HLENGTH) != "" && $::env(FP_IO_HLENGTH) != ""} {
+ set_pin_length -hor_length $::env(FP_IO_HLENGTH) \
+ -ver_length $::env(FP_IO_VLENGTH)
+}
+
+if {$::env(FP_IO_HLENGTH) != "" && $::env(FP_IO_HLENGTH) != ""} {
+ set_pin_length_extension -hor_extension $::env(FP_IO_HEXTEND) \
+ -ver_extension $::env(FP_IO_VEXTEND)
+}
+
+if {$::env(FP_IO_HLENGTH) != "" && $::env(FP_IO_HLENGTH) != ""} {
+ set_pin_thick_multiplier -hor_multiplier $::env(FP_IO_HTHICKNESS_MULT) \
+ -ver_multiplier $::env(FP_IO_VTHICKNESS_MULT)
+}
+
+set arg_list [list]
+if { $::env(FP_IO_MODE) == 1 } {
+ lappend arg_list -random
+}
+
+if { $::env(FP_IO_MIN_DISTANCE) != "" } {
+ lappend arg_list -min_distance $::env(FP_IO_MIN_DISTANCE)
+}
+
+set HMETAL $::env(FP_IO_HLAYER)
+set VMETAL $::env(FP_IO_VLAYER)
+
+place_pins {*}$arg_list \
+ -random_seed 42 \
+ -hor_layers $HMETAL \
+ -ver_layers $VMETAL
+
+write_def $::env(SAVE_DEF)
diff --git a/openlane/scripts/openroad/layer_adjustments.tcl b/openlane/scripts/openroad/layer_adjustments.tcl
new file mode 100644
index 0000000..c357842
--- /dev/null
+++ b/openlane/scripts/openroad/layer_adjustments.tcl
@@ -0,0 +1,66 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set_global_routing_layer_adjustment * $::env(GLB_RT_ADJUSTMENT)
+
+# Legacy format for layer adjustments: Convert to new format
+set array [split $::env(GLB_RT_LAYER_ADJUSTMENTS) ","]
+
+set conversion_flag 0
+
+set l1_adj [lindex $array 0]
+if { [info exists ::env(GLB_RT_L1_ADJUSTMENT)] } {
+ set conversion_flag 1
+ set l1_adj $::env(GLB_RT_L1_ADJUSTMENT)
+}
+set l2_adj [lindex $array 1]
+if { [info exists ::env(GLB_RT_L2_ADJUSTMENT)] } {
+ set conversion_flag 1
+ set l2_adj $::env(GLB_RT_L2_ADJUSTMENT)
+}
+set l3_adj [lindex $array 2]
+if { [info exists ::env(GLB_RT_L3_ADJUSTMENT)] } {
+ set conversion_flag 1
+ set l3_adj $::env(GLB_RT_L3_ADJUSTMENT)
+}
+set l4_adj [lindex $array 3]
+if { [info exists ::env(GLB_RT_L4_ADJUSTMENT)] } {
+ set conversion_flag 1
+ set l4_adj $::env(GLB_RT_L4_ADJUSTMENT)
+}
+set l5_adj [lindex $array 4]
+if { [info exists ::env(GLB_RT_L5_ADJUSTMENT)] } {
+ set conversion_flag 1
+ set l5_adj $::env(GLB_RT_L5_ADJUSTMENT)
+}
+set l6_adj [lindex $array 5]
+if { [info exists ::env(GLB_RT_L6_ADJUSTMENT)] } {
+ set conversion_flag 1
+ set l6_adj $::env(GLB_RT_L6_ADJUSTMENT)
+}
+
+if { $conversion_flag } {
+ set ::env(GLB_RT_LAYER_ADJUSTMENTS) "$l1_adj,$l2_adj,$l3_adj,$l4_adj,$l5_adj,$l6_adj"
+
+ puts stderr "You're using a GLB_RT_LX_ADJUSTMENT variable in your configuration, which is a deprecated variable that will be removed in the future."
+ puts stderr "We recommend you update your configuration as follows:"
+ puts stderr "\tset ::env(GLB_RT_LAYER_ADJUSTMENTS) $::env(GLB_RT_LAYER_ADJUSTMENTS)"
+}
+
+set i 0
+foreach adjustment $array {
+ set layer_name [lindex $::env(TECH_METAL_LAYERS) $i]
+ set_global_routing_layer_adjustment $layer_name $adjustment
+ incr i
+}
\ No newline at end of file
diff --git a/openlane/scripts/openroad/opendp.tcl b/openlane/scripts/openroad/opendp.tcl
new file mode 100755
index 0000000..0d940fc
--- /dev/null
+++ b/openlane/scripts/openroad/opendp.tcl
@@ -0,0 +1,43 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+set_placement_padding -global -right $::env(CELL_PAD)
+
+if { $::env(CELL_PAD_EXCLUDE) != "" } {
+ set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
+}
+
+detailed_placement\
+ -max_displacement [subst { $::env(PL_MAX_DISPLACEMENT_X) $::env(PL_MAX_DISPLACEMENT_Y) }]
+
+if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
+ optimize_mirroring
+}
+
+if { [catch {check_placement -verbose} errmsg] } {
+ puts stderr $errmsg
+ exit 1
+}
+
+write_def $::env(SAVE_DEF)
diff --git a/openlane/scripts/openroad/pdn.tcl b/openlane/scripts/openroad/pdn.tcl
new file mode 100644
index 0000000..2c5b4ba
--- /dev/null
+++ b/openlane/scripts/openroad/pdn.tcl
@@ -0,0 +1,59 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+# load the grid definitions
+if {[catch {source $::env(PDN_CFG)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+# run PDNGEN
+if {[catch {pdngen} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+# checks for unconnected nodes (e.g., isolated rails or stripes)
+if { $::env(FP_PDN_CHECK_NODES) } {
+ check_power_grid -net $::env(VDD_NET)
+ check_power_grid -net $::env(GND_NET)
+}
+
+if { $::env(FP_PDN_IRDROP) } {
+ # set rc values
+ source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+ analyze_power_grid -net $::env(VDD_NET) -outfile $::env(PGA_RPT_FILE)
+}
+
+write_def $::env(SAVE_DEF)
diff --git a/openlane/scripts/openroad/pdn_cfg.tcl b/openlane/scripts/openroad/pdn_cfg.tcl
new file mode 100644
index 0000000..1a65b40
--- /dev/null
+++ b/openlane/scripts/openroad/pdn_cfg.tcl
@@ -0,0 +1,165 @@
+# Power nets
+
+if { ! [info exists ::env(VDD_NET)] } {
+ set ::env(VDD_NET) $::env(VDD_PIN)
+}
+
+if { ! [info exists ::env(GND_NET)] } {
+ set ::env(GND_NET) $::env(GND_PIN)
+}
+
+if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
+ if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
+ foreach power_pin $::env(STD_CELL_POWER_PINS) {
+ add_global_connection \
+ -net $::env(VDD_NET) \
+ -inst_pattern .* \
+ -pin_pattern $power_pin \
+ -power
+ }
+ foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
+ add_global_connection \
+ -net $::env(GND_NET) \
+ -inst_pattern .* \
+ -pin_pattern $ground_pin \
+ -ground
+ }
+ }
+}
+
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
+ [info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+ set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+ foreach pdn_hook $pdn_hooks {
+ set instance_name [lindex $pdn_hook 0]
+ set power_net [lindex $pdn_hook 1]
+ set ground_net [lindex $pdn_hook 2]
+ # This assumes the power pin and the power net have the same name.
+ # The macro hooks only give an instance name and not power pin names.
+
+ add_global_connection \
+ -net $power_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $power_net \
+ -power
+
+ add_global_connection \
+ -net $ground_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $ground_net \
+ -ground
+ }
+}
+
+set secondary []
+
+foreach net $::env(VDD_NETS) {
+ if { $net != $::env(VDD_NET)} {
+ lappend secondary $net
+
+ set db_net [[ord::get_db_block] findNet $net]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $net]
+ $net setSpecial
+ $net setSigType "POWER"
+ }
+ }
+}
+
+foreach net $::env(GND_NETS) {
+ if { $net != $::env(GND_NET)} {
+ lappend secondary $net
+
+ set db_net [[ord::get_db_block] findNet $net]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $net]
+ $net setSpecial
+ $net setSigType "GROUND"
+ }
+ }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+ -secondary_power $secondary
+
+# Assesses whether the design is the core of the chip or not based on the
+# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
+if { $::env(DESIGN_IS_CORE) == 1 } {
+ # Used if the design is the core of the chip
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_UPPER_LAYER) \
+ -width $::env(FP_PDN_HWIDTH) \
+ -pitch $::env(FP_PDN_HPITCH) \
+ -offset $::env(FP_PDN_HOFFSET) \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+} else {
+ # Used if the design is a macro in the core
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins $::env(FP_PDN_LOWER_LAYER)
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -starts_with POWER
+}
+
+# Adds the standard cell rails if enabled.
+if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_RAILS_LAYER) \
+ -width $::env(FP_PDN_RAIL_WIDTH) \
+ -followpins \
+ -starts_with POWER
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
+}
+
+
+# Adds the core ring if enabled.
+if { $::env(FP_PDN_CORE_RING) == 1 } {
+ add_pdn_ring \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
+ -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+ -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+ -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
+}
+
+define_pdn_grid \
+ -macro \
+ -default \
+ -name macro \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect \
+ -grid macro \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
diff --git a/openlane/scripts/openroad/rcx.tcl b/openlane/scripts/openroad/rcx.tcl
new file mode 100644
index 0000000..9472c27
--- /dev/null
+++ b/openlane/scripts/openroad/rcx.tcl
@@ -0,0 +1,51 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(RCX_LIB) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(RCX_LEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_sdc $::env(CURRENT_SDC)
+set_propagated_clock [all_clocks]
+
+set rcx_flags ""
+if { !$::env(RCX_MERGE_VIA_WIRE_RES) } {
+ set rcx_flags "-no_merge_via_res"
+}
+
+# RCX
+puts "Using RCX ruleset '$::env(RCX_RULESET)'..."
+define_process_corner -ext_model_index 0 X
+extract_parasitics $rcx_flags\
+ -ext_model_file $::env(RCX_RULESET)\
+ -lef_res
+
+puts "Writing result to $::env(SAVE_SPEF)..."
+write_spef $::env(SAVE_SPEF)
diff --git a/openlane/scripts/openroad/replace.tcl b/openlane/scripts/openroad/replace.tcl
new file mode 100755
index 0000000..d1aafb5
--- /dev/null
+++ b/openlane/scripts/openroad/replace.tcl
@@ -0,0 +1,108 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+set ::block [[[::ord::get_db] getChip] getBlock]
+set ::insts [$::block getInsts]
+
+set free_insts_flag 0
+
+foreach inst $::insts {
+ set placement_status [$inst getPlacementStatus]
+ if { $placement_status != "FIRM" } {
+ set free_insts_flag 1
+ break
+ }
+}
+
+if { ! $free_insts_flag } {
+ puts "\[WARN] All instances are FIXED"
+ puts "\[WARN] No need to use replace"
+ puts "\[WARN] Skipping..."
+ file copy -force $::env(CURRENT_DEF) $::env(SAVE_DEF)
+ exit 0
+}
+
+set arg_list [list]
+
+lappend arg_list -verbose_level 1
+lappend arg_list -density $::env(PL_TARGET_DENSITY)
+
+if { $::env(PL_BASIC_PLACEMENT) } {
+ lappend arg_list -overflow 0.9
+ lappend arg_list -init_density_penalty 0.0001
+ lappend arg_list -initial_place_max_iter 20
+ lappend arg_list -bin_grid_count 64
+}
+
+if { $::env(PL_TIME_DRIVEN) } {
+ source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+ read_sdc $::env(CURRENT_SDC)
+ lappend arg_list -timing_driven
+}
+
+if { $::env(PL_ROUTABILITY_DRIVEN) } {
+ source $::env(SCRIPTS_DIR)/openroad/set_routing_layers.tcl
+ set_macro_extension $::env(GLB_RT_MACRO_EXTENSION)
+ source $::env(SCRIPTS_DIR)/openroad/layer_adjustments.tcl
+ lappend arg_list -routability_driven
+}
+
+if { $::env(PL_SKIP_INITIAL_PLACEMENT) && !$::env(PL_BASIC_PLACEMENT) } {
+ lappend arg_list -skip_initial_place
+}
+
+set_placement_padding -global -right $::env(CELL_PAD)
+
+if { $::env(CELL_PAD_EXCLUDE) != "" } {
+ set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
+}
+
+global_placement {*}$arg_list
+
+write_def $::env(SAVE_DEF)
+
+if {[info exists ::env(CLOCK_PORT)]} {
+ if { $::env(PL_ESTIMATE_PARASITICS) == 1 } {
+ read_sdc -echo $::env(CURRENT_SDC)
+ unset_propagated_clock [all_clocks]
+ # set rc values
+ source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+ estimate_parasitics -placement
+
+ set ::env(RUN_STANDALONE) 0
+ source $::env(SCRIPTS_DIR)/openroad/sta.tcl
+ }
+} else {
+ puts "\[WARN\]: No CLOCK_PORT found. Skipping STA..."
+}
diff --git a/openlane/scripts/openroad/resizer.tcl b/openlane/scripts/openroad/resizer.tcl
new file mode 100644
index 0000000..b2cdc12
--- /dev/null
+++ b/openlane/scripts/openroad/resizer.tcl
@@ -0,0 +1,95 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_RESIZER_OPT) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+unset_propagated_clock [all_clocks]
+
+# set rc values
+source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+
+# estimate wire rc parasitics
+estimate_parasitics -placement
+
+if { [info exists ::env(DONT_USE_CELLS)] } {
+ set_dont_use $::env(DONT_USE_CELLS)
+}
+
+if { [info exists ::env(PL_RESIZER_BUFFER_INPUT_PORTS)] && $::env(PL_RESIZER_BUFFER_INPUT_PORTS) } {
+ buffer_ports -inputs
+}
+
+if { [info exists ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS)] && $::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) } {
+ buffer_ports -outputs
+}
+# Resize
+if { [info exists ::env(PL_RESIZER_MAX_WIRE_LENGTH)] && $::env(PL_RESIZER_MAX_WIRE_LENGTH) } {
+ repair_design -max_wire_length $::env(PL_RESIZER_MAX_WIRE_LENGTH) \
+ -slew_margin $::env(PL_RESIZER_MAX_SLEW_MARGIN) \
+ -cap_margin $::env(PL_RESIZER_MAX_CAP_MARGIN)
+} else {
+ repair_design -slew_margin $::env(PL_RESIZER_MAX_SLEW_MARGIN) \
+ -cap_margin $::env(PL_RESIZER_MAX_CAP_MARGIN)
+}
+
+if { $::env(PL_RESIZER_REPAIR_TIE_FANOUT) == 1} {
+ # repair tie lo fanout
+ repair_tie_fanout -separation $::env(PL_RESIZER_TIE_SEPERATION) [lindex $::env(SYNTH_TIELO_PORT) 0]/[lindex $::env(SYNTH_TIELO_PORT) 1]
+ # repair tie hi fanout
+ repair_tie_fanout -separation $::env(PL_RESIZER_TIE_SEPERATION) [lindex $::env(SYNTH_TIEHI_PORT) 0]/[lindex $::env(SYNTH_TIEHI_PORT) 1]
+}
+
+report_floating_nets -verbose
+
+set_placement_padding -global -right $::env(CELL_PAD)
+
+if { $::env(CELL_PAD_EXCLUDE) != "" } {
+ set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
+}
+detailed_placement
+if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
+ optimize_mirroring
+}
+
+if { [catch {check_placement -verbose} errmsg] } {
+ puts stderr $errmsg
+ exit 1
+}
+
+write_def $::env(SAVE_DEF)
+write_sdc $::env(SAVE_SDC)
+
+# Run post design optimizations STA
+estimate_parasitics -placement
+set ::env(RUN_STANDALONE) 0
+source $::env(SCRIPTS_DIR)/openroad/sta.tcl
diff --git a/openlane/scripts/openroad/resizer_routing_timing.tcl b/openlane/scripts/openroad/resizer_routing_timing.tcl
new file mode 100644
index 0000000..1fdd527
--- /dev/null
+++ b/openlane/scripts/openroad/resizer_routing_timing.tcl
@@ -0,0 +1,105 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_RESIZER_OPT) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+set_propagated_clock [all_clocks]
+
+if { [info exists ::env(DONT_USE_CELLS)] } {
+ set_dont_use $::env(DONT_USE_CELLS)
+}
+
+source $::env(SCRIPTS_DIR)/openroad/set_routing_layers.tcl
+
+source $::env(SCRIPTS_DIR)/openroad/layer_adjustments.tcl
+
+set arg_list [list]
+lappend arg_list -congestion_iterations $::env(GLB_RT_OVERFLOW_ITERS)
+lappend arg_list -verbose
+if { $::env(GLB_RT_ALLOW_CONGESTION) == 1 } {
+ lappend arg_list -allow_congestion
+}
+puts $arg_list
+global_route {*}$arg_list
+
+# set rc values
+source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+
+# estimate wire rc parasitics
+estimate_parasitics -global_routing
+
+# Resize
+if { [catch {repair_timing -setup \
+ -slack_margin $::env(GLB_RESIZER_SETUP_SLACK_MARGIN) \
+ -max_buffer_percent $::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT)}
+]} {
+ puts "Setup utilization limit is reached. Continuing the flow... "
+}
+
+if { $::env(GLB_RESIZER_ALLOW_SETUP_VIOS) == 1} {
+ if { [catch {repair_timing -hold -allow_setup_violations \
+ -slack_margin $::env(GLB_RESIZER_HOLD_SLACK_MARGIN) \
+ -max_buffer_percent $::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT)}
+ ]} {
+ puts "Hold utilization limit is reached. Continuing the flow... "
+ }
+} else {
+ if { [catch {repair_timing -hold \
+ -slack_margin $::env(GLB_RESIZER_HOLD_SLACK_MARGIN) \
+ -max_buffer_percent $::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT)}
+ ]} {
+ puts "Hold utilization limit is reached. Continuing the flow... "
+ }
+}
+
+# set_placement_padding -global -right $::env(CELL_PAD)
+# set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
+
+detailed_placement
+
+if { $::env(GLB_OPTIMIZE_MIRRORING) } {
+ optimize_mirroring
+}
+
+if { [catch {check_placement -verbose} errmsg] } {
+ puts stderr $errmsg
+ exit 1
+}
+
+write_def $::env(SAVE_DEF)
+write_sdc $::env(SAVE_SDC)
+
+# Run post timing optimizations STA
+estimate_parasitics -global_routing
+set ::env(RUN_STANDALONE) 0
+source $::env(SCRIPTS_DIR)/openroad/sta.tcl
diff --git a/openlane/scripts/openroad/resizer_timing.tcl b/openlane/scripts/openroad/resizer_timing.tcl
new file mode 100644
index 0000000..93ab316
--- /dev/null
+++ b/openlane/scripts/openroad/resizer_timing.tcl
@@ -0,0 +1,94 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+foreach lib $::env(LIB_RESIZER_OPT) {
+ read_liberty $lib
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+}
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+set_propagated_clock [all_clocks]
+
+if { [info exists ::env(DONT_USE_CELLS)] } {
+ set_dont_use $::env(DONT_USE_CELLS)
+}
+
+# set rc values
+source $::env(SCRIPTS_DIR)/openroad/set_rc.tcl
+
+# CTS and detailed placement move instances, so update parastic estimates.
+# estimate wire rc parasitics
+estimate_parasitics -placement
+
+# Resize
+if { [catch {repair_timing -setup \
+ -slack_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN) \
+ -max_buffer_percent $::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT)}
+]} {
+ puts "Setup utilization limit is reached. Continuing the flow... "
+}
+
+if { $::env(PL_RESIZER_ALLOW_SETUP_VIOS) == 1} {
+ if { [catch {repair_timing -hold -allow_setup_violations \
+ -slack_margin $::env(PL_RESIZER_HOLD_SLACK_MARGIN) \
+ -max_buffer_percent $::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT)}
+ ]} {
+ puts "Hold utilization limit is reached. Continuing the flow... "
+ }
+} else {
+ if { [catch {repair_timing -hold \
+ -slack_margin $::env(PL_RESIZER_HOLD_SLACK_MARGIN) \
+ -max_buffer_percent $::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT)}
+ ]} {
+ puts "Hold utilization limit is reached. Continuing the flow... "
+ }
+}
+
+set_placement_padding -global -right $::env(CELL_PAD)
+if { $::env(CELL_PAD_EXCLUDE) != "" } {
+ set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
+}
+
+detailed_placement
+if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
+ optimize_mirroring
+}
+
+if { [catch {check_placement -verbose} errmsg] } {
+ puts stderr $errmsg
+ exit 1
+}
+
+write_def $::env(SAVE_DEF)
+write_sdc $::env(SAVE_SDC)
+
+# Run post timing optimizations STA
+estimate_parasitics -placement
+set ::env(RUN_STANDALONE) 0
+source $::env(SCRIPTS_DIR)/openroad/sta.tcl
diff --git a/openlane/scripts/openroad/set_rc.tcl b/openlane/scripts/openroad/set_rc.tcl
new file mode 100644
index 0000000..4673672
--- /dev/null
+++ b/openlane/scripts/openroad/set_rc.tcl
@@ -0,0 +1,25 @@
+# set resistance and capacitence
+# Via resistance
+puts "\[INFO\]: Setting RC values..."
+if { [info exist ::env(VIAS_RC)] } {
+ set vias_rc [split $::env(VIAS_RC) ","]
+ foreach via_rc $vias_rc {
+ set layer_name [lindex $via_rc 0]
+ set resistance [lindex $via_rc 1]
+ set_layer_rc -via $layer_name -resistance $resistance
+ }
+}
+
+# Metal resistance and capacitence
+if { [info exist ::env(LAYERS_RC)] } {
+ set layers_rc [split $::env(LAYERS_RC) ","]
+ foreach layer_rc $layers_rc {
+ set layer_name [lindex $layer_rc 0]
+ set capacitance [lindex $layer_rc 1]
+ set resistance [lindex $layer_rc 2]
+ set_layer_rc -layer $layer_name -capacitance $capacitance -resistance $resistance
+ }
+}
+
+set_wire_rc -signal -layer $::env(WIRE_RC_LAYER)
+set_wire_rc -clock -layer $::env(WIRE_RC_LAYER)
\ No newline at end of file
diff --git a/openlane/scripts/openroad/set_routing_layers.tcl b/openlane/scripts/openroad/set_routing_layers.tcl
new file mode 100644
index 0000000..7d100b1
--- /dev/null
+++ b/openlane/scripts/openroad/set_routing_layers.tcl
@@ -0,0 +1,30 @@
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set signal_min_layer $::env(RT_MIN_LAYER)
+set signal_max_layer $::env(RT_MAX_LAYER)
+set clock_min_layer $::env(RT_MIN_LAYER)
+set clock_max_layer $::env(RT_MAX_LAYER)
+
+if { [info exists ::env(RT_CLOCK_MIN_LAYER)]} {
+ set clock_min_layer $::env(RT_CLOCK_MIN_LAYER)
+}
+if { [info exists ::env(RT_CLOCK_MAX_LAYER)]} {
+ set clock_max_layer $::env(RT_CLOCK_MAX_LAYER)
+}
+
+puts "\[INFO]: Setting signal min routing layer to: $signal_min_layer and clock min routing layer to $clock_min_layer. "
+puts "\[INFO]: Setting signal max routing layer to: $signal_max_layer and clock max routing layer to $clock_max_layer. "
+
+set_routing_layers -signal [subst $signal_min_layer]-[subst $signal_max_layer] -clock [subst $clock_min_layer]-[subst $clock_max_layer]
diff --git a/openlane/scripts/openroad/sta.tcl b/openlane/scripts/openroad/sta.tcl
new file mode 100644
index 0000000..673719a
--- /dev/null
+++ b/openlane/scripts/openroad/sta.tcl
@@ -0,0 +1,152 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if { $::env(RUN_STANDALONE) == 1 } {
+ foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ read_liberty $lib
+ }
+
+ if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty $lib
+ }
+ }
+
+ if {[catch {read_lef $::env(STA_LEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+
+ if { $::env(CURRENT_DEF) != 0 } {
+ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+ } else {
+ if {[catch {read_verilog $::env(CURRENT_NETLIST)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+ link_design $::env(DESIGN_NAME)
+ }
+
+ read_sdc -echo $::env(CURRENT_SDC)
+ if { $::env(STA_PRE_CTS) == 1 } {
+ unset_propagated_clock [all_clocks]
+ } else {
+ set_propagated_clock [all_clocks]
+ }
+}
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+
+if { [info exists ::env(CURRENT_SPEF)] } {
+ read_spef $::env(CURRENT_SPEF)
+}
+
+puts "min_report"
+puts "\n==========================================================================="
+puts "report_checks -path_delay min (Hold)"
+puts "============================================================================"
+report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 5
+puts "min_report_end"
+
+puts "max_report"
+puts "\n==========================================================================="
+puts "report_checks -path_delay max (Setup)"
+puts "============================================================================"
+report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 5
+puts "max_report_end"
+
+
+puts "check_report"
+puts "\n==========================================================================="
+puts "report_checks -unconstrained"
+puts "============================================================================"
+report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded
+
+puts "\n==========================================================================="
+puts "report_checks --slack_max -0.01"
+puts "============================================================================"
+report_checks -slack_max -0.01 -fields {slew cap input nets fanout} -format full_clock_expanded
+puts "check_report_end"
+
+puts "check_slew"
+puts "\n==========================================================================="
+puts " report_check_types -max_slew -max_cap -max_fanout -violators"
+puts "============================================================================"
+report_check_types -max_slew -max_capacitance -max_fanout -violators
+
+
+puts "\n==========================================================================="
+puts "max slew violation count [sta::max_slew_violation_count]"
+puts "max fanout violation count [sta::max_fanout_violation_count]"
+puts "max cap violation count [sta::max_capacitance_violation_count]"
+puts "============================================================================"
+puts "check_slew_end"
+
+puts "tns_report"
+puts "\n==========================================================================="
+puts " report_tns"
+puts "============================================================================"
+report_tns
+puts "tns_report_end"
+
+puts "wns_report"
+puts "\n==========================================================================="
+puts " report_wns"
+puts "============================================================================"
+report_wns
+puts "wns_report_end"
+
+puts "worst_slack"
+puts "\n==========================================================================="
+puts " report_worst_slack -max (Setup)"
+puts "============================================================================"
+report_worst_slack -max
+
+puts "\n==========================================================================="
+puts " report_worst_slack -min (Hold)"
+puts "============================================================================"
+report_worst_slack -min
+puts "worst_slack_end"
+
+# report clock skew if the clock port is defined
+# OR hangs if this command is run on clockless designs
+if { $::env(CLOCK_PORT) != "__VIRTUAL_CLK__" && $::env(CLOCK_PORT) != "" } {
+ puts "clock_skew"
+ puts "\n==========================================================================="
+ puts " report_clock_skew"
+ puts "============================================================================"
+ report_clock_skew
+ puts "clock_skew_end"
+}
+
+puts "power_report"
+puts "\n==========================================================================="
+puts " report_power"
+puts "============================================================================"
+report_power
+puts "power_report_end"
+
+puts "area_report"
+puts "\n==========================================================================="
+puts " report_design_area"
+puts "============================================================================"
+report_design_area
+puts "area_report_end"
+
+if { [info exists ::env(SAVE_SDF)] } {
+ write_sdf $::env(SAVE_SDF) -divider . -include_typ
+}
diff --git a/openlane/scripts/openroad/sta_multi_corner.tcl b/openlane/scripts/openroad/sta_multi_corner.tcl
new file mode 100755
index 0000000..6bece93
--- /dev/null
+++ b/openlane/scripts/openroad/sta_multi_corner.tcl
@@ -0,0 +1,203 @@
+# Copyright 2020-2021 Efabless Corporation
+# ECO Flow Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+define_corners ss tt ff
+
+foreach lib $::env(LIB_SLOWEST) {
+ read_liberty -corner ss $lib
+}
+foreach lib $::env(LIB_TYPICAL) {
+ read_liberty -corner tt $lib
+}
+foreach lib $::env(LIB_FASTEST) {
+ read_liberty -corner ff $lib
+}
+
+foreach corner {ss tt ff} {
+ if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty -corner $corner $lib
+ }
+ }
+}
+
+if {[catch {read_lef $::env(STA_LEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if { $::env(CURRENT_DEF) != 0 } {
+ if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+} else {
+ if {[catch {read_verilog $::env(CURRENT_NETLIST)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+ link_design $::env(DESIGN_NAME)
+}
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+
+# read spef files if they are generated prior to this point
+if { [info exists ::env(CURRENT_SPEF)] } {
+ read_spef -corner ss $::env(CURRENT_SPEF)
+ read_spef -corner tt $::env(CURRENT_SPEF)
+ read_spef -corner ff $::env(CURRENT_SPEF)
+}
+
+read_sdc -echo $::env(CURRENT_SDC)
+if { $::env(STA_PRE_CTS) == 1 } {
+ unset_propagated_clock [all_clocks]
+} else {
+ set_propagated_clock [all_clocks]
+}
+
+puts "min_report"
+puts "\n==========================================================================="
+puts "report_checks -path_delay min (Hold)"
+puts "============================================================================"
+puts "\n======================= Slowest Corner ===================================\n"
+report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner ss
+puts "\n======================= Typical Corner ===================================\n"
+report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner tt
+puts "\n======================= Fastest Corner ===================================\n"
+report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner ff
+puts "min_report_end"
+
+
+puts "max_report"
+puts "\n==========================================================================="
+puts "report_checks -path_delay max (Setup)"
+puts "============================================================================"
+puts "\n======================= Slowest Corner ===================================\n"
+report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner ss
+puts "\n======================= Typical Corner ===================================\n"
+report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner tt
+puts "\n======================= Fastest Corner ===================================\n"
+report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner ff
+puts "max_report_end"
+
+
+puts "check_report"
+puts "\n==========================================================================="
+puts "report_checks -unconstrained"
+puts "============================================================================"
+puts "\n======================= Slowest Corner ===================================\n"
+report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded -corner ss
+puts "\n======================= Typical Corner ===================================\n"
+report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded -corner tt
+puts "\n======================= Fastest Corner ===================================\n"
+report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded -corner ff
+
+
+puts "\n==========================================================================="
+puts "report_checks --slack_max -0.01"
+puts "============================================================================"
+puts "\n======================= Slowest Corner ===================================\n"
+report_checks -slack_max -0.01 -fields {slew cap input nets fanout} -format full_clock_expanded -corner ss
+puts "\n======================= Typical Corner ===================================\n"
+report_checks -slack_max -0.01 -fields {slew cap input nets fanout} -format full_clock_expanded -corner tt
+puts "\n======================= Fastest Corner ===================================\n"
+report_checks -slack_max -0.01 -fields {slew cap input nets fanout} -format full_clock_expanded -corner ff
+puts "check_report_end"
+
+
+puts "check_slew"
+puts "\n==========================================================================="
+puts " report_check_types -max_slew -max_cap -max_fanout -violators"
+puts "============================================================================"
+puts "\n======================= Slowest Corner ===================================\n"
+report_check_types -max_slew -max_capacitance -max_fanout -violators -corner ss
+puts "\n======================= Typical Corner ===================================\n"
+report_check_types -max_slew -max_capacitance -max_fanout -violators -corner tt
+puts "\n======================= Fastest Corner ===================================\n"
+report_check_types -max_slew -max_capacitance -max_fanout -violators -corner ff
+
+puts "\n==========================================================================="
+puts "max slew violation count [sta::max_slew_violation_count]"
+puts "max fanout violation count [sta::max_fanout_violation_count]"
+puts "max cap violation count [sta::max_capacitance_violation_count]"
+puts "============================================================================"
+puts "check_slew_end"
+
+puts "tns_report"
+puts "\n==========================================================================="
+puts " report_tns"
+puts "============================================================================"
+report_tns
+puts "tns_report_end"
+
+puts "wns_report"
+puts "\n==========================================================================="
+puts " report_wns"
+puts "============================================================================"
+report_wns
+puts "wns_report_end"
+
+
+puts "worst_slack"
+puts "\n==========================================================================="
+puts " report_worst_slack -max (Setup)"
+puts "============================================================================"
+report_worst_slack -max
+
+puts "\n==========================================================================="
+puts " report_worst_slack -min (Hold)"
+puts "============================================================================"
+report_worst_slack -min
+puts "worst_slack_end"
+
+
+# report clock skew if the clock port is defined
+# OR hangs if this command is run on clockless designs
+if { $::env(CLOCK_PORT) != "__VIRTUAL_CLK__" && $::env(CLOCK_PORT) != "" } {
+ puts "clock_skew"
+ puts "\n==========================================================================="
+ puts " report_clock_skew"
+ puts "============================================================================"
+ puts "\n======================== Slowest Corner ==================================\n"
+ report_clock_skew -corner ss
+ puts "\n======================= Typical Corner ===================================\n"
+ report_clock_skew -corner tt
+ puts "\n======================= Fastest Corner ===================================\n"
+ report_clock_skew -corner ff
+ puts "clock_skew_end"
+}
+
+# this sometimes segfaults on corner cases
+if { $::env(STA_REPORT_POWER) == 1 } {
+ puts "power_report"
+ puts "\n==========================================================================="
+ puts " report_power"
+ puts "============================================================================"
+ puts "\n\n======================= Slowest Corner =================================\n"
+ report_power -corner ss
+ puts "\n======================= Typical Corner ===================================\n"
+ report_power -corner tt
+ puts "\n\n======================= Fastest Corner =================================\n"
+ report_power -corner ff
+ puts "power_report_end"
+}
+
+
+puts "area_report"
+puts "\n==========================================================================="
+puts " report_design_area"
+puts "============================================================================"
+report_design_area
+puts "area_report_end"
diff --git a/openlane/scripts/openroad/tapcell.tcl b/openlane/scripts/openroad/tapcell.tcl
new file mode 100755
index 0000000..616124e
--- /dev/null
+++ b/openlane/scripts/openroad/tapcell.tcl
@@ -0,0 +1,33 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+tapcell\
+ -endcap_cpp "1"\
+ -distance $::env(FP_TAPCELL_DIST)\
+ -tapcell_master "$::env(FP_WELLTAP_CELL)"\
+ -endcap_master "$::env(FP_ENDCAP_CELL)"\
+ -halo_width_x $::env(FP_TAP_HORIZONTAL_HALO)\
+ -halo_width_y $::env(FP_TAP_VERTICAL_HALO)
+
+write_def $::env(SAVE_DEF)
diff --git a/openlane/scripts/openroad/write_verilog.tcl b/openlane/scripts/openroad/write_verilog.tcl
new file mode 100755
index 0000000..748f043
--- /dev/null
+++ b/openlane/scripts/openroad/write_verilog.tcl
@@ -0,0 +1,27 @@
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(INPUT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if { [info exists ::env(LEC_ENABLE)] && $::env(LEC_ENABLE) } {
+ write_verilog $::env(SAVE_NETLIST).without_power_pins.v
+}
+
+write_verilog -include_pwr_gnd $::env(SAVE_NETLIST)
diff --git a/openlane/scripts/or_issue.py b/openlane/scripts/or_issue.py
new file mode 100755
index 0000000..1b30693
--- /dev/null
+++ b/openlane/scripts/or_issue.py
@@ -0,0 +1,421 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+See <openlane_root>/docs/source/using_or_issue.md.
+
+This script is intended for use by bug reporters and maintainers and is not part of the flow.
+"""
+
+import os
+import re
+import sys
+import glob
+import shutil
+import pathlib
+import argparse
+from typing import List
+from collections import deque
+from os.path import join, abspath, dirname, basename, isdir, relpath
+
+openlane_path = abspath(dirname(dirname(__file__)))
+
+parser = argparse.ArgumentParser(description="OpenROAD Issue Packager")
+parser.add_argument(
+ "--or-script",
+ "-s",
+ required=True,
+ help="Path to the OpenROAD script causing the failure: i.e. ./scripts/openroad/antenna_check.tcl, ./scripts/openroad/pdn.tcl, etc. [required]",
+)
+parser.add_argument(
+ "--pdk-root",
+ required=(os.getenv("PDK_ROOT") is None),
+ default=os.getenv("PDK_ROOT"),
+ help="Path to the PDK root [required if environment variable PDK_ROOT is not set]",
+)
+parser.add_argument(
+ "--run-path",
+ "-r",
+ default=None,
+ help="The run path. If not specified, the script will attempt to discern it from the input_def path.",
+)
+parser.add_argument(
+ "--output",
+ "-o",
+ default="./out.def",
+ help="Name of def file to be generated [default: ./out.def]",
+)
+parser.add_argument(
+ "--verbose",
+ action="store_true",
+ default=False,
+ help="Verbose output of all found environment variables.",
+)
+parser.add_argument(
+ "--netlist",
+ "-n",
+ action="store_true",
+ default=False,
+ help="Use the netlist as an input instead of a def file. Useful for evaluating some scripts such as floorplan.tcl.",
+)
+parser.add_argument("--output-dir", default=None, help="Output to this directory.")
+parser.add_argument(
+ "input",
+ help="Name of input into the OR script (usually denoted by environment variable CURRENT_NETLIST or CURRENT_DEF: get it from the logs) [required]",
+)
+args = parser.parse_args()
+
+OPEN_SOURCE_PDKS = ["sky130A"]
+print(
+ """
+or_issue.py OpenROAD Issue Packager
+
+EFABLESS CORPORATION AND ALL AUTHORS OF THE OPENLANE PROJECT SHALL NOT BE HELD
+LIABLE FOR ANY LEAKS THAT MAY OCCUR TO ANY PROPRIETARY DATA AS A RESULT OF USING
+THIS SCRIPT. THIS SCRIPT IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
+CONDITIONS OF ANY KIND.
+
+BY USING THIS SCRIPT, YOU ACKNOWLEDGE THAT YOU FULLY UNDERSTAND THIS DISCLAIMER
+AND ALL IT ENTAILS.
+""",
+ file=sys.stderr,
+)
+
+script_path = abspath(args.or_script)
+pdk_root = abspath(args.pdk_root)
+or_scripts_path = join(openlane_path, "scripts", "openroad")
+use_netlist = args.netlist
+input_file = abspath(args.input)
+run_path = None
+if args.run_path is not None:
+ run_path = abspath(args.run_path)
+else:
+ current_dir = dirname(input_file)
+ while current_dir != "/":
+ if "config.tcl" in os.listdir(current_dir):
+ run_path = current_dir
+ break
+ current_dir = dirname(current_dir)
+
+ if run_path is None:
+ print(
+ f"[ERR] No run path provided and {input_file} is not in the run path.",
+ file=sys.stderr,
+ )
+ exit(os.EX_USAGE)
+ else:
+ print(f"[INF] Resolved run path to {run_path}.")
+
+save_def = args.output
+verbose = args.verbose
+
+if not os.path.exists(input_file):
+ print(f"[ERR] {input_file} not found.", file=sys.stderr)
+ exit(os.EX_NOINPUT)
+
+if not script_path.startswith(or_scripts_path):
+ print(
+ f"[ERR] The OpenROAD script {script_path} does not appear to be in {or_scripts_path}.",
+ file=sys.stderr,
+ )
+ exit(os.EX_CONFIG)
+
+if not os.path.exists(run_path) and os.path.isdir(run_path):
+ print(f"[ERR] The run path {run_path} is not a valid folder.", file=sys.stderr)
+ exit(os.EX_CONFIG)
+
+run_name = basename(run_path)
+
+# Phase 1: Read All Environment Variables
+# pdk_config = join(args.pdk_root, "sky130A", "libs.tech", "openlane", "config.tcl")
+print("Parsing config file(s)…", file=sys.stderr)
+run_config = join(run_path, "config.tcl")
+
+env = {}
+
+
+def read_env(config_path: str, from_path: str, input_env={}) -> dict:
+ rx = r"\s*set\s*::env\((.+?)\)\s*(.+)"
+ env = input_env.copy()
+ string_data = ""
+ try:
+ string_data = open(config_path).read()
+ except FileNotFoundError:
+ print(
+ f"❌ File {config_path} not found. The path {from_path} may have been specified incorrectly.",
+ file=sys.stderr,
+ )
+ exit(os.EX_NOINPUT)
+
+ # Process \ at ends of lines, remove semicolons
+ entries = string_data.split("\n")
+ i = 0
+ while i < len(entries):
+ if not entries[i].endswith("\\"):
+ if entries[i].endswith(";"):
+ entries[i] = entries[i][:-1]
+ i += 1
+ continue
+ entries[i] = entries[i][:-1] + entries[i + 1]
+ del entries[i + 1]
+
+ for entry in entries:
+ match = re.match(rx, entry)
+ if match is None:
+ continue
+ name = match[1]
+ value = match[2]
+ # remove double quotes/{}
+ value = value.strip('"')
+ value = value.strip("{}")
+ env[name] = value
+
+ return env
+
+
+env = read_env(run_config, "Run Path") # , read_env(pdk_config, "PDK Root"))
+
+# Cannot be reliably read from config.tcl
+input_key = "CURRENT_DEF"
+if use_netlist:
+ input_key = "CURRENT_NETLIST"
+env[input_key] = input_file
+env["SAVE_DEF"] = save_def
+
+
+# Phase 2: Set up destination folder
+script_basename = basename(args.or_script)[:-4]
+destination_folder = args.output_dir or abspath(
+ join(".", "_build", f"{run_name}_{script_basename}_packaged")
+)
+print(f"Setting up {destination_folder}…", file=sys.stderr)
+
+
+def mkdirp(path):
+ return pathlib.Path(path).mkdir(parents=True, exist_ok=True)
+
+
+try:
+ shutil.rmtree(destination_folder)
+except FileNotFoundError:
+ pass
+
+mkdirp(destination_folder)
+
+# Phase 3: Process TCL Scripts To Find Full List Of Files
+tcls_to_process = deque([script_path])
+
+
+def shift(deque):
+ try:
+ return deque.popleft()
+ except Exception:
+ return None
+
+
+or_script_counter = 0
+
+
+def get_or_script():
+ global or_script_counter
+ value = f"OR_SCRIPT_{or_script_counter}"
+ or_script_counter += 1
+ return value
+
+
+env_keys_used = set()
+tcls = set()
+current = shift(tcls_to_process)
+while current is not None:
+ env_key = get_or_script()
+ env_keys_used.add(env_key)
+ env[env_key] = current
+
+ try:
+ script = open(current).read()
+
+ for key, value in env.items():
+ key_accessor = re.compile(rf"((\$::env\({re.escape(key)}\))([/\-\w\.]*))")
+ for use in key_accessor.findall(script):
+ use: List[str]
+ full, accessor, extra = use
+ env_keys_used.add(key)
+
+ value_substituted = full.replace(accessor, value)
+
+ if value_substituted.endswith(".tcl") or value_substituted.endswith(
+ ".sdc"
+ ):
+ if value_substituted not in tcls:
+ tcls.add(value_substituted)
+ tcls_to_process.append(value_substituted)
+ except Exception:
+ print(
+ f"[WRN] {current} was not found, might be a product. Skipping",
+ file=sys.stderr,
+ )
+
+ current = shift(tcls_to_process)
+
+# Phase 4: Copy The Files
+final_env = {}
+
+pdk_path = join(destination_folder, "pdk")
+openlane_misc_path = join(destination_folder, "openlane")
+
+warnings = []
+
+
+def copy(frm, to):
+ parents = dirname(to)
+ mkdirp(parents)
+
+ def do_copy():
+ if isdir(frm):
+ shutil.copytree(frm, to)
+ else:
+ shutil.copyfile(frm, to)
+
+ try:
+ incomplete_matches = glob.glob(frm + "*")
+
+ if len(incomplete_matches) == 0:
+ raise Exception()
+ elif len(incomplete_matches) != 1 or incomplete_matches[0] != frm:
+ # Prefix For Other Files
+ for match in incomplete_matches:
+ if match == frm:
+ # If it's both a file AND a prefix for other files
+ do_copy()
+ else:
+ new_frm = match
+ new_to = to + new_frm[len(frm) :]
+ copy(new_frm, new_to)
+ else:
+ do_copy()
+ except Exception as e:
+ warnings.append(f"[WRN] Couldn't copy {frm}: {e}. Skipped.")
+
+
+if verbose:
+ print("\nProcessing environment variables…\n---", file=sys.stderr)
+for key in env_keys_used:
+ value = env[key]
+ if verbose:
+ print(f"{key}: {value}")
+ if value == input_file:
+ final_path = join(destination_folder, "in.def")
+ from_path = value
+ copy(from_path, final_path)
+
+ final_env[input_key] = "./in.def"
+ elif value.startswith(run_path):
+ relative = relpath(value, run_path)
+ final_value = join(".", relative)
+ final_path = join(destination_folder, final_value)
+ from_path = value
+ copy(from_path, final_path)
+
+ final_env[key] = final_value
+ elif value.startswith(pdk_root):
+ nonfree_warning = True
+ value_components = value.split(os.path.sep)
+ for pdk in OPEN_SOURCE_PDKS:
+ if pdk in value_components:
+ nonfree_warning = False
+ if nonfree_warning:
+ warnings.append(
+ f"[WRN] {value} appears to be a confidential PDK file. ENSURE THAT YOU INSPECT THE RESULTS."
+ )
+ relative = relpath(value, pdk_root)
+ final_value = join("pdk", relative)
+ final_path = join(destination_folder, final_value)
+ copy(value, final_path)
+ final_env[key] = final_value
+ elif value.startswith("/openlane"):
+ relative = relpath(value, "/openlane")
+ final_value = join("openlane", relative)
+ final_path = join(destination_folder, final_value)
+ from_path = value.replace("/openlane", openlane_path)
+ if value != "/openlane/scripts": # Too many files to copy otherwise
+ copy(from_path, final_path)
+ final_env[key] = final_value
+ elif value.startswith("/"):
+ final_value = value[1:]
+ final_path = join(destination_folder, final_value)
+ copy(value, final_path)
+ final_env[key] = final_value
+ else:
+ final_env[key] = value
+if verbose:
+ print("---\n", file=sys.stderr)
+
+for warning in warnings:
+ print(warning)
+print("\n")
+
+# Phase 5: Create Environment Set/Run Files
+run_shell = join(destination_folder, "run.sh")
+with open(run_shell, "w") as f:
+ env_list = "\n".join(
+ [f"export {key}='{value}';" for key, value in final_env.items()]
+ )
+ f.write(
+ f"""\
+#!/bin/sh
+dir=$(cd -P -- "$(dirname -- "$0")" && pwd -P)
+cd $dir;
+{env_list}
+OPENROAD_BIN=${{OPENROAD_BIN:-openroad}}
+$OPENROAD_BIN -exit $OR_SCRIPT_0
+ """
+ )
+os.chmod(run_shell, 0o755)
+
+run_tcl = join(destination_folder, "run.tcl")
+with open(run_tcl, "w") as f:
+ env_list = "\n".join(
+ [f"set ::env({key}) {{{value}}};" for key, value in final_env.items()]
+ )
+ f.write(
+ f"""\
+#!/usr/bin/env openroad
+{env_list}
+source $::env(OR_SCRIPT_0)
+ """
+ )
+os.chmod(run_tcl, 0o755)
+
+gdb_env = join(destination_folder, "env.gdb")
+with open(gdb_env, "w") as f:
+ env_list = "\n".join([f"set env {key} {value}" for key, value in final_env.items()])
+ f.write(
+ f"""\
+{env_list}
+ """
+ )
+
+lldb_env = join(destination_folder, "env.lldb")
+with open(lldb_env, "w") as f:
+ env_list = "\n".join([f"env {key}={value}" for key, value in final_env.items()])
+ f.write(
+ f"""\
+{env_list}
+ """
+ )
+
+print("[FIN] Done.", file=sys.stderr)
+print(destination_folder)
diff --git a/openlane/scripts/padframe_extract_area.sh b/openlane/scripts/padframe_extract_area.sh
new file mode 100755
index 0000000..7a709c7
--- /dev/null
+++ b/openlane/scripts/padframe_extract_area.sh
@@ -0,0 +1,23 @@
+#!/bin/sh
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# grep -P "/^AREA\s(\d+)\s(\d+)\s;$/" $1
+padarea=$(perl -ne 'print "$1 $2" if /^AREA\s(\d+)\s(\d+)\s;$/' $1)
+diearea="0 0"
+for dim in $padarea
+do
+ diearea="$diearea $(( $dim ))"
+done
+echo $diearea
diff --git a/openlane/scripts/padframe_generator.py b/openlane/scripts/padframe_generator.py
new file mode 100755
index 0000000..6020bae
--- /dev/null
+++ b/openlane/scripts/padframe_generator.py
@@ -0,0 +1,2976 @@
+#!/usr/bin/env python3
+# flake8: noqa
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+#
+# --------------------------------------------------------
+# Padframe Editor and Core Floorplanner
+#
+# --------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# April 24, 2019
+# Version 0.5
+# Based on https://github.com/YosysHQ/padring (requirement)
+# Update: May 9, 2019 to add console message window
+# Update: May 10, 2019 to incorporate core floorplanning
+# Update: Jan 31, 2020 to allow batch operation
+# --------------------------------------------------------
+
+import os
+import re
+import sys
+import glob
+import json
+import math
+import shutil
+import signal
+import select
+import subprocess
+import faulthandler
+
+import tkinter
+from tkinter import ttk
+
+# User preferences file (if it exists)
+prefsfile = "~/design/.profile/prefs.json"
+
+# ------------------------------------------------------
+# Dialog for entering a pad
+# ------------------------------------------------------
+
+
+class ConsoleText(tkinter.Text):
+ linelimit = 500
+
+ class IORedirector(object):
+ """A general class for redirecting I/O to this Text widget."""
+
+ def __init__(self, text_area):
+ self.text_area = text_area
+
+ class StdoutRedirector(IORedirector):
+ """A class for redirecting stdout to this Text widget."""
+
+ def write(self, str):
+ self.text_area.write(str, False)
+
+ class StderrRedirector(IORedirector):
+ """A class for redirecting stderr to this Text widget."""
+
+ def write(self, str):
+ self.text_area.write(str, True)
+
+ def __init__(self, master=None, cnf={}, **kw):
+ """See the __init__ for Tkinter.Text."""
+
+ tkinter.Text.__init__(self, master, cnf, **kw)
+
+ self.tag_configure("stdout", background="white", foreground="black")
+ self.tag_configure("stderr", background="white", foreground="red")
+ # None of these works! Cannot change selected text background!
+ self.config(selectbackground="blue", selectforeground="white")
+ self.tag_configure("sel", background="blue", foreground="white")
+
+ def write(self, val, is_stderr=False):
+ lines = int(self.index("end-1c").split(".")[0])
+ if lines > self.linelimit:
+ self.delete("1.0", str(lines - self.linelimit) + ".0")
+ self.insert("end", val, "stderr" if is_stderr else "stdout")
+ self.see("end")
+
+ def limit(self, val):
+ self.linelimit = val
+
+
+class Dialog(tkinter.Toplevel):
+ def __init__(
+ self, parent, message=None, title=None, seed=None, border="blue", **kwargs
+ ):
+
+ tkinter.Toplevel.__init__(self, parent)
+ self.transient(parent)
+
+ if title:
+ self.title(title)
+
+ self.configure(background=border, padx=2, pady=2)
+ self.obox = ttk.Frame(self)
+ self.obox.pack(side="left", fill="both", expand="true")
+
+ self.parent = parent
+ self.result = None
+ body = ttk.Frame(self.obox)
+ self.initial_focus = self.body(body, message, seed, **kwargs)
+ body.pack(padx=5, pady=5)
+ self.buttonbox()
+ self.grab_set()
+
+ if not self.initial_focus:
+ self.initial_focus = self
+
+ self.protocol("WM_DELETE_WINDOW", self.cancel)
+ self.geometry("+%d+%d" % (parent.winfo_rootx() + 50, parent.winfo_rooty() + 50))
+
+ self.initial_focus.focus_set()
+ self.wait_window(self)
+
+ # Construction hooks
+
+ def body(self, master, **kwargs):
+ # Create dialog body. Return widget that should have
+ # initial focus. This method should be overridden
+ pass
+
+ def buttonbox(self):
+ # Add standard button box. Override if you don't want the
+ # standard buttons
+
+ box = ttk.Frame(self.obox)
+
+ self.okb = ttk.Button(
+ box, text="OK", width=10, command=self.ok, default="active"
+ )
+ self.okb.pack(side="left", padx=5, pady=5)
+ w = ttk.Button(box, text="Cancel", width=10, command=self.cancel)
+ w.pack(side="left", padx=5, pady=5)
+
+ self.bind("<Return>", self.ok)
+ self.bind("<Escape>", self.cancel)
+ box.pack(fill="x", expand="true")
+
+ # Standard button semantics
+
+ def ok(self, event=None):
+
+ if not self.validate():
+ self.initial_focus.focus_set() # put focus back
+ return
+
+ self.withdraw()
+ self.update_idletasks()
+ self.result = self.apply()
+ self.cancel()
+
+ def cancel(self, event=None):
+
+ # Put focus back to the parent window
+ self.parent.focus_set()
+ self.destroy()
+
+ def validate(self):
+ return 1 # Override this
+
+ def apply(self):
+ return None # Override this
+
+
+class PadNameDialog(Dialog):
+ def body(self, master, warning=None, seed=None):
+ if warning:
+ ttk.Label(master, text=warning).grid(row=0, columnspan=2, sticky="wns")
+ ttk.Label(master, text="Enter new group name:").grid(
+ row=1, column=0, sticky="wns"
+ )
+ self.nentry = ttk.Entry(master)
+ self.nentry.grid(row=1, column=1, sticky="ewns")
+ if seed:
+ self.nentry.insert(0, seed)
+ return self.nentry # initial focus
+
+ def apply(self):
+ return self.nentry.get()
+
+
+# ------------------------------------------------------
+# Dialog for entering core dimensions
+# ------------------------------------------------------
+
+
+class CoreSizeDialog(Dialog):
+ def body(self, master, warning="Chip core dimensions", seed=None):
+ if warning:
+ ttk.Label(master, text=warning).grid(row=0, columnspan=2, sticky="wns")
+ ttk.Label(master, text="Enter core width x height (microns):").grid(
+ row=1, column=0, sticky="wns"
+ )
+ self.nentry = ttk.Entry(master)
+ self.nentry.grid(row=1, column=1, sticky="ewns")
+
+ if seed:
+ self.nentry.insert(0, seed)
+ return self.nentry # initial focus
+
+ def apply(self):
+ return self.nentry.get()
+
+
+# ------------------------------------------------
+# SoC Floorplanner and Padframe Generator GUI
+# ------------------------------------------------
+
+
+class SoCFloorplanner(ttk.Frame):
+ """Open Galaxy Pad Frame Generator."""
+
+ def __init__(self, parent=None, *args, **kwargs):
+ """See the __init__ for Tkinter.Toplevel."""
+ ttk.Frame.__init__(self, parent, *args[1:], **kwargs)
+ self.root = parent
+ self.init_data()
+ if args[0] == True:
+ self.do_gui = True
+ self.init_gui()
+ else:
+ self.do_gui = False
+ self.use_console = False
+
+ def on_quit(self):
+ """Exits program."""
+ quit()
+
+ def init_gui(self):
+ """Builds GUI."""
+ global prefsfile
+
+ message = []
+ fontsize = 11
+
+ # Read user preferences file, get default font size from it.
+ prefspath = os.path.expanduser(prefsfile)
+ if os.path.exists(prefspath):
+ with open(prefspath, "r") as f:
+ self.prefs = json.load(f)
+ if "fontsize" in self.prefs:
+ fontsize = self.prefs["fontsize"]
+ else:
+ self.prefs = {}
+
+ s = ttk.Style()
+
+ available_themes = s.theme_names()
+ s.theme_use(available_themes[0])
+
+ s.configure(
+ "normal.TButton", font=("Helvetica", fontsize), border=3, relief="raised"
+ )
+ s.configure(
+ "title.TLabel",
+ font=("Helvetica", fontsize, "bold italic"),
+ foreground="brown",
+ anchor="center",
+ )
+ s.configure("blue.TLabel", font=("Helvetica", fontsize), foreground="blue")
+ s.configure("normal.TLabel", font=("Helvetica", fontsize))
+ s.configure("normal.TCheckbutton", font=("Helvetica", fontsize))
+ s.configure("normal.TMenubutton", font=("Helvetica", fontsize))
+ s.configure("normal.TEntry", font=("Helvetica", fontsize), background="white")
+ s.configure(
+ "pad.TLabel", font=("Helvetica", fontsize), foreground="blue", relief="flat"
+ )
+ s.configure(
+ "select.TLabel",
+ font=("Helvetica", fontsize, "bold"),
+ foreground="white",
+ background="blue",
+ relief="flat",
+ )
+
+ # parent.withdraw()
+ self.root.title("Padframe Generator and Core Floorplanner")
+ self.root.option_add("*tearOff", "FALSE")
+ self.pack(side="top", fill="both", expand="true")
+ self.root.protocol("WM_DELETE_WINDOW", self.on_quit)
+
+ pane = tkinter.PanedWindow(
+ self, orient="vertical", sashrelief="groove", sashwidth=6
+ )
+ pane.pack(side="top", fill="both", expand="true")
+
+ self.toppane = ttk.Frame(pane)
+ self.botpane = ttk.Frame(pane)
+
+ self.toppane.columnconfigure(0, weight=1)
+ self.toppane.rowconfigure(0, weight=1)
+ self.botpane.columnconfigure(0, weight=1)
+ self.botpane.rowconfigure(0, weight=1)
+
+ # Scrolled frame using canvas widget
+ self.pframe = tkinter.Frame(self.toppane)
+ self.pframe.grid(row=0, column=0, sticky="news")
+ self.pframe.rowconfigure(0, weight=1)
+ self.pframe.columnconfigure(0, weight=1)
+
+ # Add column on the left, listing all groups and the pads they belong to.
+ # This starts as just a frame to be filled. Use a canvas to create a
+ # scrolled frame.
+
+ # The primary frame holds the canvas
+ self.canvas = tkinter.Canvas(self.pframe, background="white")
+ self.canvas.grid(row=0, column=0, sticky="news")
+
+ # Add Y scrollbar to pad list window
+ xscrollbar = ttk.Scrollbar(self.pframe, orient="horizontal")
+ xscrollbar.grid(row=1, column=0, sticky="news")
+ yscrollbar = ttk.Scrollbar(self.pframe, orient="vertical")
+ yscrollbar.grid(row=0, column=1, sticky="news")
+
+ self.canvas.config(xscrollcommand=xscrollbar.set)
+ xscrollbar.config(command=self.canvas.xview)
+ self.canvas.config(yscrollcommand=yscrollbar.set)
+ yscrollbar.config(command=self.canvas.yview)
+
+ self.canvas.bind("<Button-4>", self.on_scrollwheel)
+ self.canvas.bind("<Button-5>", self.on_scrollwheel)
+
+ # Configure callback
+ self.canvas.bind("<Configure>", self.frame_configure)
+
+ # Add a text window to capture output. Redirect print statements to it.
+ self.console = ttk.Frame(self.botpane)
+ self.console.grid(column=0, row=0, sticky="news")
+ self.text_box = ConsoleText(self.console, wrap="word", height=4)
+ self.text_box.pack(side="left", fill="both", expand="true")
+ console_scrollbar = ttk.Scrollbar(self.console)
+ console_scrollbar.pack(side="right", fill="y")
+ # Attach console to scrollbar
+ self.text_box.config(yscrollcommand=console_scrollbar.set)
+ console_scrollbar.config(command=self.text_box.yview)
+
+ # Add the bottom bar with buttons
+ self.bbar = ttk.Frame(self.botpane)
+ self.bbar.grid(column=0, row=1, sticky="news")
+
+ self.bbar.import_button = ttk.Button(
+ self.bbar, text="Import", command=self.vlogimport, style="normal.TButton"
+ )
+ self.bbar.import_button.grid(column=0, row=0, padx=5)
+
+ self.bbar.generate_button = ttk.Button(
+ self.bbar, text="Generate", command=self.generate, style="normal.TButton"
+ )
+ self.bbar.generate_button.grid(column=1, row=0, padx=5)
+
+ self.bbar.save_button = ttk.Button(
+ self.bbar, text="Save", command=self.save, style="normal.TButton"
+ )
+ self.bbar.save_button.grid(column=2, row=0, padx=5)
+
+ self.bbar.cancel_button = ttk.Button(
+ self.bbar, text="Quit", command=self.on_quit, style="normal.TButton"
+ )
+ self.bbar.cancel_button.grid(column=3, row=0, padx=5)
+
+ pane.add(self.toppane)
+ pane.add(self.botpane)
+ pane.paneconfig(self.toppane, stretch="first")
+
+ def init_data(self):
+
+ self.vlogpads = []
+ self.corecells = []
+ self.Npads = []
+ self.Spads = []
+ self.Epads = []
+ self.Wpads = []
+ self.NEpad = []
+ self.NWpad = []
+ self.SEpad = []
+ self.SWpad = []
+ self.coregroup = []
+
+ self.celldefs = []
+ self.coredefs = []
+ self.selected = []
+ self.ioleflibs = []
+ self.llx = 0
+ self.lly = 0
+ self.urx = 0
+ self.ury = 0
+
+ self.event_data = {}
+ self.event_data["x0"] = 0
+ self.event_data["y0"] = 0
+ self.event_data["x"] = 0
+ self.event_data["y"] = 0
+ self.event_data["tag"] = None
+ self.scale = 1.0
+ self.margin = 100
+ self.pad_rotation = 0
+
+ self.init_messages = []
+ self.stdout = None
+ self.stderr = None
+
+ self.keep_cfg = False
+ self.ef_format = False
+ self.use_console = False
+
+ def init_padframe(self):
+ self.set_project()
+ self.vlogimport()
+ self.readplacement(precheck=True)
+ self.resolve()
+ self.generate(0)
+
+ # Local routines for handling printing to the text console
+
+ def print(self, message, file=None, end="\n", flush=True):
+ if not file:
+ if not self.use_console:
+ file = sys.stdout
+ else:
+ file = ConsoleText.StdoutRedirector(self.text_box)
+ if self.stdout:
+ print(message, file=file, end=end)
+ if flush:
+ self.stdout.flush()
+ self.update_idletasks()
+ else:
+ self.init_messages.append(message)
+
+ def text_to_console(self):
+ # Redirect stdout and stderr to the console as the last thing to do. . .
+ # Otherwise errors in the GUI get sucked into the void.
+
+ self.stdout = sys.stdout
+ self.stderr = sys.stderr
+ if self.use_console:
+ sys.stdout = ConsoleText.StdoutRedirector(self.text_box)
+ sys.stderr = ConsoleText.StderrRedirector(self.text_box)
+
+ if len(self.init_messages) > 0:
+ for message in self.init_messages:
+ self.print(message)
+ self.init_messages = []
+
+ # Set the project name(s). This is the name of the top-level verilog.
+ # The standard protocol is that the project directory contains a file
+ # project.json that defines a name 'ip-name' that is the same as the
+ # layout name, the verilog module name, etc.
+
+ def set_project(self):
+ # Check pwd
+ pwdname = self.projectpath if self.projectpath else os.getcwd()
+
+ subdir = os.path.split(pwdname)[1]
+ if subdir == "mag" or subdir == "verilog":
+ projectpath = os.path.split(pwdname)[0]
+ else:
+ projectpath = pwdname
+
+ projectroot = os.path.split(projectpath)[0]
+ projectdirname = os.path.split(projectpath)[1]
+
+ # Check for project.json
+
+ jsonname = None
+ if os.path.isfile(projectpath + "/project.json"):
+ jsonname = projectpath + "/project.json"
+ elif os.path.isfile(projectroot + "/" + projectdirname + ".json"):
+ jsonname = projectroot + "/" + projectdirname + ".json"
+ if os.path.isfile(projectroot + "/project.json"):
+ # Just in case this was started from some other subdirectory
+ projectpath = projectroot
+ jsonname = projectroot + "/project.json"
+
+ if jsonname:
+ self.print("Reading project JSON file " + jsonname)
+ with open(jsonname, "r") as ifile:
+ topdata = json.load(ifile)
+ if "data-sheet" in topdata:
+ dsheet = topdata["data-sheet"]
+ if "ip-name" in dsheet:
+ self.project = dsheet["ip-name"]
+ self.projectpath = projectpath
+ else:
+ self.print(
+ "No project JSON file; using directory name as the project name."
+ )
+ self.project = os.path.split(projectpath)[1]
+ self.projectpath = projectpath
+
+ self.print("Project name is " + self.project + " (" + self.projectpath + ")")
+
+ # Functions for drag-and-drop capability
+ def add_draggable(self, tag):
+ self.canvas.tag_bind(tag, "<ButtonPress-1>", self.on_button_press)
+ self.canvas.tag_bind(tag, "<ButtonRelease-1>", self.on_button_release)
+ self.canvas.tag_bind(tag, "<B1-Motion>", self.on_button_motion)
+ self.canvas.tag_bind(tag, "<ButtonPress-2>", self.on_button2_press)
+ self.canvas.tag_bind(tag, "<ButtonPress-3>", self.on_button3_press)
+
+ def on_button_press(self, event):
+ """Begining drag of an object"""
+ # Find the closest item, then record its tag.
+ locx = event.x + self.canvas.canvasx(0)
+ locy = event.y + self.canvas.canvasy(0)
+ item = self.canvas.find_closest(locx, locy)[0]
+ self.event_data["tag"] = self.canvas.gettags(item)[0]
+ self.event_data["x0"] = event.x
+ self.event_data["y0"] = event.y
+ self.event_data["x"] = event.x
+ self.event_data["y"] = event.y
+
+ def on_button2_press(self, event):
+ """Flip an object (excluding corners)"""
+ locx = event.x + self.canvas.canvasx(0)
+ locy = event.y + self.canvas.canvasy(0)
+ item = self.canvas.find_closest(locx, locy)[0]
+ tag = self.canvas.gettags(item)[0]
+
+ try:
+ corecell = next(item for item in self.coregroup if item["name"] == tag)
+ except Exception:
+ try:
+ pad = next(item for item in self.Npads if item["name"] == tag)
+ except Exception:
+ pad = None
+ if not pad:
+ try:
+ pad = next(item for item in self.Epads if item["name"] == tag)
+ except Exception:
+ pad = None
+ if not pad:
+ try:
+ pad = next(item for item in self.Spads if item["name"] == tag)
+ except Exception:
+ pad = None
+ if not pad:
+ try:
+ pad = next(item for item in self.Wpads if item["name"] == tag)
+ except Exception:
+ pad = None
+ if not pad:
+ self.print("Error: Object cannot be flipped.")
+ else:
+ # Flip the pad (in the only way meaningful for the pad).
+ orient = pad["o"]
+ if orient == "N":
+ pad["o"] = "FN"
+ elif orient == "E":
+ pad["o"] = "FW"
+ elif orient == "S":
+ pad["o"] = "FS"
+ elif orient == "W":
+ pad["o"] = "FE"
+ elif orient == "FN":
+ pad["o"] = "N"
+ elif orient == "FE":
+ pad["o"] = "W"
+ elif orient == "FS":
+ pad["o"] = "S"
+ elif orient == "FW":
+ pad["o"] = "E"
+ else:
+ # Flip the cell. Use the DEF meaning of flip, which is to
+ # add or subtract 'F' from the orientation.
+ orient = corecell["o"]
+ if not "F" in orient:
+ corecell["o"] = "F" + orient
+ else:
+ corecell["o"] = orient[1:]
+
+ # Redraw
+ self.populate(0)
+
+ def on_button3_press(self, event):
+ """Rotate a core object (no pads)"""
+ locx = event.x + self.canvas.canvasx(0)
+ locy = event.y + self.canvas.canvasy(0)
+ item = self.canvas.find_closest(locx, locy)[0]
+ tag = self.canvas.gettags(item)[0]
+
+ try:
+ corecell = next(item for item in self.coregroup if item["name"] == tag)
+ except Exception:
+ self.print("Error: Object cannot be rotated.")
+ else:
+ # Modify its orientation
+ orient = corecell["o"]
+ if orient == "N":
+ corecell["o"] = "E"
+ elif orient == "E":
+ corecell["o"] = "S"
+ elif orient == "S":
+ corecell["o"] = "W"
+ elif orient == "W":
+ corecell["o"] = "N"
+ elif orient == "FN":
+ corecell["o"] = "FW"
+ elif orient == "FW":
+ corecell["o"] = "FS"
+ elif orient == "FS":
+ corecell["o"] = "FE"
+ elif orient == "FE":
+ corecell["o"] = "FN"
+
+ # rewrite the core DEF file
+ self.write_core_def()
+
+ # Redraw
+ self.populate(0)
+
+ def on_button_motion(self, event):
+ """Handle dragging of an object"""
+ # compute how much the mouse has moved
+ delta_x = event.x - self.event_data["x"]
+ delta_y = event.y - self.event_data["y"]
+ # move the object the appropriate amount
+ self.canvas.move(self.event_data["tag"], delta_x, delta_y)
+ # record the new position
+ self.event_data["x"] = event.x
+ self.event_data["y"] = event.y
+
+ def on_button_release(self, event):
+ """End drag of an object"""
+
+ # Find the pad associated with the tag and update its position information
+ tag = self.event_data["tag"]
+
+ # Collect pads in clockwise order. Note that E and S rows are not clockwise
+ allpads = []
+ allpads.extend(self.Npads)
+ allpads.extend(self.NEpad)
+ allpads.extend(reversed(self.Epads))
+ allpads.extend(self.SEpad)
+ allpads.extend(reversed(self.Spads))
+ allpads.extend(self.SWpad)
+ allpads.extend(self.Wpads)
+ allpads.extend(self.NWpad)
+
+ # Create a list of row references (also in clockwise order, but no reversing)
+ padrows = [
+ self.Npads,
+ self.NEpad,
+ self.Epads,
+ self.SEpad,
+ self.Spads,
+ self.SWpad,
+ self.Wpads,
+ self.NWpad,
+ ]
+
+ # Record the row or corner where this pad was located before the move
+ for row in padrows:
+ try:
+ pad = next(item for item in row if item["name"] == tag)
+ except Exception:
+ pass
+ else:
+ padrow = row
+ break
+
+ # Currently there is no procedure to move a pad out of the corner
+ # position; corners are fixed by definition.
+ if (
+ padrow == self.NEpad
+ or padrow == self.SEpad
+ or padrow == self.SWpad
+ or padrow == self.NWpad
+ ):
+ # Easier to run generate() than to put the pad back. . .
+ self.generate(0)
+ return
+
+ # Find the original center point of the pad being moved
+
+ padllx = pad["x"]
+ padlly = pad["y"]
+ if pad["o"] == "N" or pad["o"] == "S":
+ padurx = padllx + pad["width"]
+ padury = padlly + pad["height"]
+ else:
+ padurx = padllx + pad["height"]
+ padury = padlly + pad["width"]
+ padcx = (padllx + padurx) / 2
+ padcy = (padlly + padury) / 2
+
+ # Add distance from drag information (note that drag position in y
+ # is negative relative to the chip dimensions)
+ padcx += (self.event_data["x"] - self.event_data["x0"]) / self.scale
+ padcy -= (self.event_data["y"] - self.event_data["y0"]) / self.scale
+
+ # reset the drag information
+ self.event_data["tag"] = None
+ self.event_data["x"] = 0
+ self.event_data["y"] = 0
+ self.event_data["x0"] = 0
+ self.event_data["y0"] = 0
+
+ # Find the distance from the pad to all other pads, and get the two
+ # closest entries.
+
+ wwidth = self.urx - self.llx
+ dist0 = wwidth
+ dist1 = wwidth
+ pad0 = None
+ pad1 = None
+
+ for npad in allpads:
+ if npad == pad:
+ continue
+
+ npadllx = npad["x"]
+ npadlly = npad["y"]
+ if npad["o"] == "N" or npad["o"] == "S":
+ npadurx = npadllx + npad["width"]
+ npadury = npadlly + npad["height"]
+ else:
+ npadurx = npadllx + npad["height"]
+ npadury = npadlly + npad["width"]
+ npadcx = (npadllx + npadurx) / 2
+ npadcy = (npadlly + npadury) / 2
+
+ deltx = npadcx - padcx
+ delty = npadcy - padcy
+ pdist = math.sqrt(deltx * deltx + delty * delty)
+ if pdist < dist0:
+ dist1 = dist0
+ pad1 = pad0
+ dist0 = pdist
+ pad0 = npad
+
+ elif pdist < dist1:
+ dist1 = pdist
+ pad1 = npad
+
+ # Diagnostic
+ # self.print('Two closest pads to pad ' + pad['name'] + ' (' + pad['cell'] + '): ')
+ # self.print(pad0['name'] + ' (' + pad0['cell'] + ') dist = ' + str(dist0))
+ # self.print(pad1['name'] + ' (' + pad1['cell'] + ') dist = ' + str(dist1))
+
+ # Record the row or corner where these pads are
+ for row in padrows:
+ try:
+ testpad = next(item for item in row if item["name"] == pad0["name"])
+ except Exception:
+ pass
+ else:
+ padrow0 = row
+ break
+
+ for row in padrows:
+ try:
+ testpad = next(item for item in row if item["name"] == pad1["name"])
+ except Exception:
+ pass
+ else:
+ padrow1 = row
+ break
+
+ # Remove pad from its own row
+ padrow.remove(pad)
+
+ # Insert pad into new row. Watch for wraparound from the last entry to the first
+ padidx0 = allpads.index(pad0)
+ padidx1 = allpads.index(pad1)
+ if padidx0 == 0 and padidx1 > 2:
+ padidx1 = -1
+
+ if padidx1 > padidx0:
+ padafter = pad1
+ rowafter = padrow1
+ padbefore = pad0
+ rowbefore = padrow0
+ else:
+ padafter = pad0
+ rowafter = padrow0
+ padbefore = pad1
+ rowbefore = padrow1
+
+ # Do not replace corner positions (? may be necessary ?)
+ if rowafter == self.NWpad:
+ self.Wpads.append(pad)
+ elif rowafter == self.NWpad:
+ self.Npads.append(pad)
+ elif rowafter == self.SEpad:
+ self.Epads.insert(0, pad)
+ elif rowafter == self.SWpad:
+ self.Spads.insert(0, pad)
+ elif rowafter == self.Wpads or rowafter == self.Npads:
+ idx = rowafter.index(padafter)
+ rowafter.insert(idx, pad)
+ elif rowbefore == self.NEpad:
+ self.Epads.append(pad)
+ elif rowbefore == self.SEpad:
+ self.Spads.append(pad)
+ else:
+ # rows E and S are ordered counterclockwise
+ idx = rowbefore.index(padbefore)
+ rowbefore.insert(idx, pad)
+
+ # Re-run padring
+ self.generate(0)
+
+ def on_scrollwheel(self, event):
+ if event.num == 4:
+ zoomval = 1.1
+ elif event.num == 5:
+ zoomval = 0.9
+ else:
+ zoomval = 1.0
+
+ self.scale *= zoomval
+ self.canvas.scale("all", -15 * zoomval, -15 * zoomval, zoomval, zoomval)
+ self.event_data["x"] *= zoomval
+ self.event_data["y"] *= zoomval
+ self.event_data["x0"] *= zoomval
+ self.event_data["y0"] *= zoomval
+ self.frame_configure(event)
+
+ # Callback functions similar to the pad event callbacks above, but for
+ # core cells. Unlike pad cells, core cells can be rotated and flipped
+ # arbitrarily, and they do not force a recomputation of the padframe
+ # unless their position forces the padframe to expand
+
+ def add_core_draggable(self, tag):
+ self.canvas.tag_bind(tag, "<ButtonPress-1>", self.on_button_press)
+ self.canvas.tag_bind(tag, "<ButtonRelease-1>", self.core_on_button_release)
+ self.canvas.tag_bind(tag, "<B1-Motion>", self.on_button_motion)
+ self.canvas.tag_bind(tag, "<ButtonPress-2>", self.on_button2_press)
+ self.canvas.tag_bind(tag, "<ButtonPress-3>", self.on_button3_press)
+
+ def core_on_button_release(self, event):
+ """End drag of a core cell"""
+
+ # Find the pad associated with the tag and update its position information
+ tag = self.event_data["tag"]
+
+ try:
+ corecell = next(item for item in self.coregroup if item["name"] == tag)
+ except Exception:
+ self.print("Error: cell " + item["name"] + " is not in coregroup!")
+ else:
+ # Modify its position values
+ corex = corecell["x"]
+ corey = corecell["y"]
+
+ # Add distance from drag information (note that drag position in y
+ # is negative relative to the chip dimensions)
+ deltax = (self.event_data["x"] - self.event_data["x0"]) / self.scale
+ deltay = (self.event_data["y"] - self.event_data["y0"]) / self.scale
+
+ corecell["x"] = corex + deltax
+ corecell["y"] = corey - deltay
+
+ # rewrite the core DEF file
+ self.write_core_def()
+
+ # reset the drag information
+ self.event_data["tag"] = None
+ self.event_data["x"] = 0
+ self.event_data["y"] = 0
+ self.event_data["x0"] = 0
+ self.event_data["y0"] = 0
+
+ # Critically needed or else frame does not resize to scrollbars!
+ def grid_configure(self, padx, pady):
+ pass
+
+ # Redraw the chip frame view in response to changes in the pad list
+ def redraw_frame(self):
+ self.canvas.coords("boundary", self.llx, self.urx, self.lly, self.ury)
+
+ # Update the canvas scrollregion to incorporate all the interior windows
+ def frame_configure(self, event):
+ if self.do_gui == False:
+ return
+ self.update_idletasks()
+ bbox = self.canvas.bbox("all")
+ try:
+ newbbox = (-15, -15, bbox[2] + 15, bbox[3] + 15)
+ except Exception:
+ pass
+ else:
+ self.canvas.configure(scrollregion=newbbox)
+
+ # Fill the GUI entries with resident data
+ def populate(self, level):
+ if self.do_gui == False:
+ return
+
+ if level > 1:
+ self.print("Recursion error: Returning now.")
+ return
+
+ self.print("Populating floorplan view.")
+
+ # Remove all entries from the canvas
+ self.canvas.delete("all")
+
+ allpads = (
+ self.Npads
+ + self.NEpad
+ + self.Epads
+ + self.SEpad
+ + self.Spads
+ + self.SWpad
+ + self.Wpads
+ + self.NWpad
+ )
+
+ notfoundlist = []
+
+ for pad in allpads:
+ if "x" not in pad:
+ self.print(
+ "Error: Pad " + pad["name"] + " has no placement information."
+ )
+ continue
+ llx = int(pad["x"])
+ lly = int(pad["y"])
+ pado = pad["o"]
+ try:
+ padcell = next(
+ item for item in self.celldefs if item["name"] == pad["cell"]
+ )
+ except Exception:
+ # This should not happen (failsafe)
+ if pad["cell"] not in notfoundlist:
+ self.print(
+ "Warning: there is no cell named "
+ + pad["cell"]
+ + " in the libraries."
+ )
+ notfoundlist.append(pad["cell"])
+ continue
+ padw = padcell["width"]
+ padh = padcell["height"]
+ if "N" in pado or "S" in pado:
+ urx = int(llx + padw)
+ ury = int(lly + padh)
+ else:
+ urx = int(llx + padh)
+ ury = int(lly + padw)
+
+ pad["llx"] = llx
+ pad["lly"] = lly
+ pad["urx"] = urx
+ pad["ury"] = ury
+
+ # Note that the DEF coordinate system is reversed in Y from the canvas. . .
+
+ height = self.ury - self.lly
+ for pad in allpads:
+
+ llx = pad["llx"]
+ lly = height - pad["lly"]
+ urx = pad["urx"]
+ ury = height - pad["ury"]
+
+ tag_id = pad["name"]
+ if "subclass" in pad:
+ if pad["subclass"] == "POWER":
+ pad_color = "orange2"
+ elif pad["subclass"] == "INOUT":
+ pad_color = "yellow"
+ elif pad["subclass"] == "OUTPUT":
+ pad_color = "powder blue"
+ elif pad["subclass"] == "INPUT":
+ pad_color = "goldenrod1"
+ elif pad["subclass"] == "SPACER":
+ pad_color = "green yellow"
+ elif pad["class"] == "ENDCAP":
+ pad_color = "green yellow"
+ elif pad["subclass"] == "" or pad["class"] == ";":
+ pad_color = "khaki1"
+ else:
+ self.print("Unhandled pad class " + pad["class"])
+ pad_color = "gray"
+ else:
+ pad_color = "gray"
+
+ sllx = self.scale * llx
+ slly = self.scale * lly
+ surx = self.scale * urx
+ sury = self.scale * ury
+
+ self.canvas.create_rectangle(
+ (sllx, slly), (surx, sury), fill=pad_color, tags=[tag_id]
+ )
+ cx = (sllx + surx) / 2
+ cy = (slly + sury) / 2
+
+ s = 10 if pad["width"] >= 10 else pad["width"]
+ if pad["height"] < s:
+ s = pad["height"]
+
+ # Create an indicator line at the bottom left corner of the cell
+ if pad["o"] == "N":
+ allx = sllx
+ ally = slly - s
+ aurx = sllx + s
+ aury = slly
+ elif pad["o"] == "E":
+ allx = sllx
+ ally = sury + s
+ aurx = sllx + s
+ aury = sury
+ elif pad["o"] == "S":
+ allx = surx
+ ally = sury + s
+ aurx = surx - s
+ aury = sury
+ elif pad["o"] == "W":
+ allx = surx
+ ally = slly - s
+ aurx = surx - s
+ aury = slly
+ elif pad["o"] == "FN":
+ allx = surx
+ ally = slly - s
+ aurx = surx - s
+ aury = slly
+ elif pad["o"] == "FE":
+ allx = surx
+ ally = sury + s
+ aurx = surx - s
+ aury = sury
+ elif pad["o"] == "FS":
+ allx = sllx
+ ally = sury + s
+ aurx = sllx + s
+ aury = sury
+ elif pad["o"] == "FW":
+ allx = sllx
+ ally = slly - s
+ aurx = sllx + s
+ aury = slly
+ self.canvas.create_line((allx, ally), (aurx, aury), tags=[tag_id])
+
+ # Rotate text on top and bottom rows if the tkinter version allows it.
+ if tkinter.TclVersion >= 8.6:
+ if pad["o"] == "N" or pad["o"] == "S":
+ angle = 90
+ else:
+ angle = 0
+ self.canvas.create_text(
+ (cx, cy), text=pad["name"], angle=angle, tags=[tag_id]
+ )
+ else:
+ self.canvas.create_text((cx, cy), text=pad["name"], tags=[tag_id])
+
+ # Make the pad draggable
+ self.add_draggable(tag_id)
+
+ # Now add the core cells
+ for cell in self.coregroup:
+ if "x" not in cell:
+ self.print(
+ "Error: Core cell "
+ + cell["name"]
+ + " has no placement information."
+ )
+ continue
+ # else:
+ # self.print('Diagnostic: Creating object for core cell ' + cell['name'])
+ llx = int(cell["x"])
+ lly = int(cell["y"])
+ cello = cell["o"]
+ try:
+ corecell = next(
+ item for item in self.coredefs if item["name"] == cell["cell"]
+ )
+ except Exception:
+ # This should not happen (failsafe)
+ if cell["cell"] not in notfoundlist:
+ self.print(
+ "Warning: there is no cell named "
+ + cell["cell"]
+ + " in the libraries."
+ )
+ notfoundlist.append(cell["cell"])
+ continue
+ cellw = corecell["width"]
+ cellh = corecell["height"]
+ if "N" in cello or "S" in cello:
+ urx = int(llx + cellw)
+ ury = int(lly + cellh)
+ else:
+ urx = int(llx + cellh)
+ ury = int(lly + cellw)
+ print(
+ "NOTE: cell "
+ + corecell["name"]
+ + " is rotated, w = "
+ + str(urx - llx)
+ + "; h = "
+ + str(ury - lly)
+ )
+
+ cell["llx"] = llx
+ cell["lly"] = lly
+ cell["urx"] = urx
+ cell["ury"] = ury
+
+ # Watch for out-of-window position in core cells.
+ corellx = self.llx
+ corelly = self.lly
+ coreurx = self.urx
+ coreury = self.ury
+
+ for cell in self.coregroup:
+
+ if "llx" not in cell:
+ # Error message for this was handled above
+ continue
+
+ llx = cell["llx"]
+ lly = height - cell["lly"]
+ urx = cell["urx"]
+ ury = height - cell["ury"]
+
+ # Check for out-of-window cell
+ if llx < corellx:
+ corellx = llx
+ if lly < corelly:
+ corelly = lly
+ if urx > coreurx:
+ coreurx = urx
+ if ury > coreury:
+ coreury = ury
+
+ tag_id = cell["name"]
+ cell_color = "gray40"
+
+ sllx = self.scale * llx
+ slly = self.scale * lly
+ surx = self.scale * urx
+ sury = self.scale * ury
+
+ self.canvas.create_rectangle(
+ (sllx, slly), (surx, sury), fill=cell_color, tags=[tag_id]
+ )
+ cx = (sllx + surx) / 2
+ cy = (slly + sury) / 2
+
+ s = 10 if cell["width"] >= 10 else cell["width"]
+ if cell["height"] < s:
+ s = cell["height"]
+
+ # Create an indicator line at the bottom left corner of the cell
+ if cell["o"] == "N":
+ allx = sllx
+ ally = slly - s
+ aurx = sllx + s
+ aury = slly
+ elif cell["o"] == "E":
+ allx = sllx
+ ally = sury + s
+ aurx = sllx + s
+ aury = sury
+ elif cell["o"] == "S":
+ allx = surx
+ ally = sury + s
+ aurx = surx - s
+ aury = sury
+ elif cell["o"] == "W":
+ allx = surx
+ ally = slly - s
+ aurx = surx - s
+ aury = slly
+ elif cell["o"] == "FN":
+ allx = surx
+ ally = slly - s
+ aurx = surx - s
+ aury = slly
+ elif cell["o"] == "FE":
+ allx = surx
+ ally = sury + s
+ aurx = surx - s
+ aury = sury
+ elif cell["o"] == "FS":
+ allx = sllx
+ ally = sury + s
+ aurx = sllx + s
+ aury = sury
+ elif cell["o"] == "FW":
+ allx = sllx
+ ally = slly - s
+ aurx = sllx + s
+ aury = slly
+ self.canvas.create_line((allx, ally), (aurx, aury), tags=[tag_id])
+
+ # self.print('Created entry for cell ' + cell['name'] + ' at {0:g}, {1:g}'.format(cx, cy))
+
+ # Rotate text on top and bottom rows if the tkinter version allows it.
+ if tkinter.TclVersion >= 8.6:
+ if "N" in cell["o"] or "S" in cell["o"]:
+ angle = 90
+ else:
+ angle = 0
+ self.canvas.create_text(
+ (cx, cy), text=cell["name"], angle=angle, tags=[tag_id]
+ )
+ else:
+ self.canvas.create_text((cx, cy), text=cell["name"], tags=[tag_id])
+
+ # Make the core cell draggable
+ self.add_core_draggable(tag_id)
+
+ # Is there a boundary size defined?
+ if self.urx > self.llx and self.ury > self.lly:
+ self.create_boundary()
+
+ # Did the core extend into negative X or Y? If so, adjust all canvas
+ # coordinates to fit in the window, or else objects cannot be reached
+ # even by zooming out (since zooming is pinned on the top corner).
+
+ offsetx = 0
+ offsety = 0
+
+ # NOTE: Probably want to check if the core exceeds the inner
+ # dimension of the pad ring, not the outer (to check and to do).
+
+ if corellx < self.llx:
+ offsetx = self.llx - corellx
+ if corelly < self.lly:
+ offsety = self.lly - corelly
+ if offsetx > 0 or offsety > 0:
+ self.canvas.move("all", offsetx, offsety)
+ # An offset implies that the chip is core limited, and the
+ # padframe requires additional space. This can be accomplished
+ # simply by running "Generate". NOTE: Since generate() calls
+ # populate(), be VERY SURE that this does not infinitely recurse!
+ self.generate(level)
+
+ # Generate a DEF file of the core area
+
+ def write_core_def(self):
+ self.print('Writing core placementment information in DEF file "core.def".')
+
+ mag_path = self.projectpath + "/mag"
+
+ # The core cells must always clear the I/O pads on the left and
+ # bottom (with the ad-hoc margin of self.margin). If core cells have
+ # been moved to the left or down past the padframe edge, then the
+ # entire core needs to be repositioned.
+
+ # To be done: draw a boundary around the core, let the edges of that
+ # boundary be draggable, and let the difference between the boundary
+ # and the core area define the margin.
+
+ if self.SWpad != []:
+ corellx = self.SWpad[0]["x"] + self.SWpad[0]["width"] + self.margin
+ corelly = self.SWpad[0]["y"] + self.SWpad[0]["height"] + self.margin
+ else:
+ corellx = self.Wpads[0]["x"] + self.Wpads[0]["height"] + self.margin
+ corelly = self.Spads[0]["x"] + self.Spads[0]["height"] + self.margin
+
+ offsetx = 0
+ offsety = 0
+ for corecell in self.coregroup:
+ if corecell["x"] < corellx:
+ if corellx - corecell["x"] > offsetx:
+ offsetx = corellx - corecell["x"]
+ if corecell["y"] < corelly:
+ if corelly - corecell["y"] > offsety:
+ offsety = corelly - corecell["y"]
+ if offsetx > 0 or offsety > 0:
+ for corecell in self.coregroup:
+ corecell["x"] += offsetx
+ corecell["y"] += offsety
+
+ # Now write the core DEF file
+
+ with open(mag_path + "/core.def", "w") as ofile:
+ print("DESIGN CORE ;", file=ofile)
+ print("UNITS DISTANCE MICRONS 1000 ;", file=ofile)
+ print("COMPONENTS {0:d} ;".format(len(self.coregroup)), file=ofile)
+ for corecell in self.coregroup:
+ print(
+ " - " + corecell["name"] + " " + corecell["cell"],
+ file=ofile,
+ end="",
+ )
+ print(
+ " + PLACED ( {0:d} {1:d} ) {2:s} ;".format(
+ int(corecell["x"] * 1000),
+ int(corecell["y"] * 1000),
+ corecell["o"],
+ ),
+ file=ofile,
+ )
+ print("END COMPONENTS", file=ofile)
+ print("END DESIGN", file=ofile)
+
+ # Create the chip boundary area
+
+ def create_boundary(self):
+ scale = self.scale
+ llx = (self.llx - 10) * scale
+ lly = (self.lly - 10) * scale
+ urx = (self.urx + 10) * scale
+ ury = (self.ury + 10) * scale
+
+ pad_color = "plum1"
+ tag_id = "boundary"
+ self.canvas.create_rectangle(
+ (llx, lly), (urx, ury), outline=pad_color, width=2, tags=[tag_id]
+ )
+ # Add text to the middle representing the chip and core areas
+ cx = ((self.llx + self.urx) / 2) * scale
+ cy = ((self.lly + self.ury) / 2) * scale
+ width = self.urx - self.llx
+ height = self.ury - self.lly
+ areatext = "Chip dimensions (um): {0:g} x {1:g}".format(width, height)
+ tag_id = "chiparea"
+ self.canvas.create_text((cx, cy), text=areatext, tags=[tag_id])
+
+ # Rotate orientation according to self.pad_rotation.
+
+ def rotate_orientation(self, orient_in):
+ orient_v = ["N", "E", "S", "W", "N", "E", "S", "W"]
+ idxadd = int(self.pad_rotation / 90)
+ idx = orient_v.index(orient_in)
+ return orient_v[idx + idxadd]
+
+ # Read a list of cell macros (name, size, class) from a LEF library
+
+ def read_lef_macros(self, libpath, libname=None, libtype="iolib"):
+ if libtype == "iolib":
+ libtext = "I/O "
+ elif libtype == "celllib":
+ libtext = "core "
+ else:
+ libtext = ""
+
+ macros = []
+
+ if libname:
+ if os.path.splitext(libname)[1] == "":
+ libname += ".lef"
+ leffiles = glob.glob(libpath + "/" + libname)
+ else:
+ leffiles = glob.glob(libpath + "/*.lef")
+ if leffiles == []:
+ if libname:
+ self.print("WARNING: No file " + libpath + "/" + libname + ".lef")
+ else:
+ self.print("WARNING: No files " + libpath + "/*.lef")
+ for leffile in leffiles:
+ libpath = os.path.split(leffile)[0]
+ libname = os.path.split(libpath)[1]
+ self.print("Reading LEF " + libtext + "library " + leffile)
+ with open(leffile, "r") as ifile:
+ ilines = ifile.read().splitlines()
+ in_macro = False
+ for iline in ilines:
+ iparse = iline.split()
+ if iparse == []:
+ continue
+ elif iparse[0] == "MACRO":
+ in_macro = True
+ newmacro = {}
+ newmacro["name"] = iparse[1]
+ newmacro[libtype] = leffile
+ macros.append(newmacro)
+ elif in_macro:
+ if iparse[0] == "END":
+ if len(iparse) > 1 and iparse[1] == newmacro["name"]:
+ in_macro = False
+ elif iparse[0] == "CLASS":
+ newmacro["class"] = iparse[1]
+ if len(iparse) > 2:
+ newmacro["subclass"] = iparse[2]
+
+ # Use the 'ENDCAP' class to identify pad rotations
+ # other than BOTTOMLEFT. This is somewhat ad-hoc
+ # depending on the foundry; may not be generally
+ # applicable.
+
+ if newmacro["class"] == "ENDCAP":
+ if newmacro["subclass"] == "TOPLEFT":
+ self.pad_rotation = 90
+ elif newmacro["subclass"] == "TOPRIGHT":
+ self.pad_rotation = 180
+ elif newmacro["subclass"] == "BOTTOMRIGHT":
+ self.pad_rotation = 270
+ else:
+ newmacro["subclass"] = None
+ elif iparse[0] == "SIZE":
+ newmacro["width"] = float(iparse[1])
+ newmacro["height"] = float(iparse[3])
+ elif iparse[0] == "ORIGIN":
+ newmacro["x"] = float(iparse[1])
+ newmacro["y"] = float(iparse[2])
+ return macros
+
+ # Read a list of cell names from a verilog file
+ # If filename is relative, then check in the same directory as the verilog
+ # top-level netlist (vlogpath) and in the subdirectory 'source/' of the top-
+ # level directory. Also check in the ~/design/ip/ directory. These are
+ # common include paths for the simulation.
+
+ def read_verilog_lib(self, incpath, vlogpath):
+ iocells = []
+ if not os.path.isfile(incpath) and incpath[0] != "/":
+ locincpath = vlogpath + "/" + incpath
+ if not os.path.isfile(locincpath):
+ locincpath = vlogpath + "/source/" + incpath
+ if not os.path.isfile(locincpath):
+ projectpath = os.path.split(vlogpath)[0]
+ designpath = os.path.split(projectpath)[0]
+ locincpath = designpath + "/ip/" + incpath
+ else:
+ locincpath = incpath
+
+ if not os.path.isfile(locincpath):
+ self.print("File " + incpath + " not found (at " + locincpath + ")!")
+ else:
+ self.print("Reading verilog library " + locincpath)
+ with open(locincpath, "r") as ifile:
+ ilines = ifile.read().splitlines()
+ for iline in ilines:
+ iparse = re.split("[\t ()]", iline)
+ while "" in iparse:
+ iparse.remove("")
+ if iparse == []:
+ continue
+ elif iparse[0] == "module":
+ iocells.append(iparse[1])
+ return iocells
+
+ # Generate a LEF abstract view from a magic layout. If "outpath" is not
+ # "None", then write output to outputpath (this is required if the input
+ # file is in a read-only directory).
+
+ def write_lef_file(self, magfile, outpath=None):
+ mag_path = os.path.split(magfile)[0]
+ magfullname = os.path.split(magfile)[1]
+ module = os.path.splitext(magfullname)[0]
+
+ if outpath:
+ write_path = outpath
+ else:
+ write_path = mag_path
+
+ self.print("Generating LEF view from layout for module " + module)
+
+ with open(write_path + "/pfg_write_lef.tcl", "w") as ofile:
+ print("drc off", file=ofile)
+ print("box 0 0 0 0", file=ofile)
+ # NOTE: Using "-force" option in case an IP with a different but
+ # compatible tech is used (e.g., EFHX035A IP inside EFXH035C). This
+ # is not checked for legality!
+ if outpath:
+ print("load " + magfile + " -force", file=ofile)
+ else:
+ print("load " + module + " -force", file=ofile)
+ print("lef write", file=ofile)
+ print("quit", file=ofile)
+
+ magicexec = self.magic_path if self.magic_path else "magic"
+ mproc = subprocess.Popen(
+ [magicexec, "-dnull", "-noconsole", "pfg_write_lef.tcl"],
+ stdin=subprocess.PIPE,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE,
+ cwd=write_path,
+ universal_newlines=True,
+ )
+
+ self.watch(mproc)
+ os.remove(write_path + "/pfg_write_lef.tcl")
+
+ # Watch a running process, polling for output and updating the GUI message
+ # window as output arrives. Return only when the process has exited.
+ # Note that this process cannot handle stdin(), so any input to the process
+ # must be passed from a file.
+
+ def watch(self, process):
+ if process == None:
+ return
+
+ while True:
+ status = process.poll()
+ if status != None:
+ try:
+ outputpair = process.communicate(timeout=1)
+ except ValueError:
+ self.print("Process forced stop, status " + str(status))
+ else:
+ for line in outputpair[0].splitlines():
+ self.print(line)
+ for line in outputpair[1].splitlines():
+ self.print(line, file=sys.stderr)
+ break
+ else:
+ sresult = select.select([process.stdout, process.stderr], [], [], 0)[0]
+ if process.stdout in sresult:
+ outputline = process.stdout.readline().strip()
+ self.print(outputline)
+ elif process.stderr in sresult:
+ outputline = process.stderr.readline().strip()
+ self.print(outputline, file=sys.stderr)
+ else:
+ self.update_idletasks()
+
+ # Reimport the pad list by reading the top-level verilog netlist. Determine
+ # what pads are listed in the file, and check against the existing pad list.
+
+ # The verilog/ directory should have a .v file containing a module of the
+ # same name as self.project (ip-name). The .v filename should have the
+ # same name as well (but not necessarily). To do: Handle import of
+ # projects having a top-level schematic instead of a verilog netlist.
+
+ def vlogimport(self):
+ self.print("Importing verilog sources.")
+
+ # First find the process PDK name for this project. Read the nodeinfo.json
+ # file and find the list of I/O cell libraries.
+
+ techpath = self.techpath if self.techpath else self.projectpath
+ if os.path.exists(techpath + "/.config"):
+ config_dir = "/.config"
+ else:
+ config_dir = "/.ef-config"
+ if os.path.exists(techpath + config_dir):
+ self.ef_format = True
+
+ pdkpath = (
+ self.techpath
+ if self.techpath
+ else os.path.realpath(self.projectpath + config_dir + "/techdir")
+ )
+ nodeinfopath = pdkpath + config_dir + "/nodeinfo.json"
+ ioleflist = []
+ if os.path.exists(nodeinfopath):
+ self.print("Reading known I/O cell libraries from " + nodeinfopath)
+ with open(nodeinfopath, "r") as ifile:
+ itop = json.load(ifile)
+ if "iocells" in itop:
+ ioleflist = []
+ for iolib in itop["iocells"]:
+ if "/" in iolib:
+ # Entries <lib>/<cell> refer to specific files
+ libcell = iolib.split("/")
+ if self.ef_format:
+ iolibpath = pdkpath + "/libs.ref/lef/" + libcell[0]
+ else:
+ iolibpath = (
+ pdkpath + "/libs.ref/" + libcell[0] + "/lef/"
+ )
+ ioleflist.extend(
+ glob.glob(iolibpath + "/" + libcell[1] + ".lef")
+ )
+ else:
+ # All other entries refer to everything in the directory.
+ if self.ef_format:
+ iolibpath = pdkpath + "/libs.ref/lef/" + iolib
+ else:
+ iolibpath = pdkpath + "/libs.ref/" + iolib + "/lef/"
+ print(iolibpath)
+ ioleflist.extend(glob.glob(iolibpath + "/*.lef"))
+ else:
+ # Diagnostic
+ print("Cannot read PDK information file " + nodeinfopath)
+
+ # Fallback behavior: List everything in libs.ref/lef/ beginning with "IO"
+ if len(ioleflist) == 0:
+ if self.ef_format:
+ ioleflist = glob.glob(pdkpath + "/libs.ref/lef/IO*/*.lef")
+ else:
+ ioleflist = glob.glob(pdkpath + "/libs.ref/IO*/lef/*.lef")
+
+ if len(ioleflist) == 0:
+ self.print("Cannot find any I/O cell libraries for this technology")
+ return
+
+ # Read the LEF libraries to get a list of all available cells. Keep
+ # this list of cells in "celldefs".
+
+ celldefs = []
+ ioliblist = []
+ ioleflibs = []
+ for iolib in ioleflist:
+ iolibpath = os.path.split(iolib)[0]
+ iolibfile = os.path.split(iolib)[1]
+ ioliblist.append(os.path.split(iolibpath)[1])
+ celldefs.extend(self.read_lef_macros(iolibpath, iolibfile, "iolib"))
+
+ verilogcells = []
+ newpadlist = []
+ coredefs = []
+ corecells = []
+ corecelllist = []
+ lefprocessed = []
+
+ busrex = re.compile(".*\[[ \t]*([0-9]+)[ \t]*:[ \t]*([0-9]+)[ \t]*\]")
+
+ vlogpath = self.projectpath + "/verilog"
+ vlogfile = vlogpath + "/" + self.project + ".v"
+ if os.path.isfile(vlogfile):
+ with open(vlogfile, "r") as ifile:
+ vloglines = ifile.read().splitlines()
+ for vlogline in vloglines:
+ vlogparse = re.split("[\t ()]", vlogline)
+ while "" in vlogparse:
+ vlogparse.remove("")
+ if vlogparse == []:
+ continue
+ elif vlogparse[0] == "//":
+ continue
+ elif vlogparse[0] == "`include":
+ incpath = vlogparse[1].strip('"')
+ libpath = os.path.split(incpath)[0]
+ libname = os.path.split(libpath)[1]
+ libfile = os.path.split(incpath)[1]
+
+ # Read the verilog library for module names to match
+ # against macro names in celldefs.
+ modulelist = self.read_verilog_lib(incpath, vlogpath)
+ matching = list(
+ item for item in celldefs if item["name"] in modulelist
+ )
+ for imatch in matching:
+ verilogcells.append(imatch["name"])
+ leffile = imatch["iolib"]
+ if leffile not in ioleflibs:
+ ioleflibs.append(leffile)
+
+ # Read a corresponding LEF file entry for non-I/O macros, if one
+ # can be found (this handles files in the PDK).
+ if len(matching) == 0:
+ if libname != "":
+ # (NOTE: Assumes full path starting with '/')
+ lefpath = libpath.replace("verilog", "lef")
+ lefname = libfile.replace(".v", ".lef")
+ if not os.path.exists(lefpath + "/" + lefname):
+ leffiles = glob.glob(lefpath + "/*.lef")
+ else:
+ leffiles = [lefpath + "/" + lefname]
+
+ for leffile in leffiles:
+ if leffile in ioleflibs:
+ continue
+ elif leffile in lefprocessed:
+ continue
+ else:
+ lefprocessed.append(leffile)
+
+ lefname = os.path.split(leffile)[1]
+
+ newcoredefs = self.read_lef_macros(
+ lefpath, lefname, "celllib"
+ )
+ coredefs.extend(newcoredefs)
+ corecells.extend(
+ list(item["name"] for item in newcoredefs)
+ )
+
+ if leffiles == []:
+ maglefname = libfile.replace(".v", ".mag")
+
+ # Handle PDK files with a maglef/ view but no LEF file.
+ maglefpath = libpath.replace("verilog", "maglef")
+ if not os.path.exists(
+ maglefpath + "/" + maglefname
+ ):
+ magleffiles = glob.glob(maglefpath + "/*.mag")
+ else:
+ magleffiles = [maglefpath + "/" + maglefname]
+
+ if magleffiles == []:
+ # Handle user ip/ files with a maglef/ view but
+ # no LEF file.
+ maglefpath = libpath.replace(
+ "verilog", "maglef"
+ )
+ designpath = os.path.split(self.projectpath)[0]
+ maglefpath = designpath + "/ip/" + maglefpath
+
+ if not os.path.exists(
+ maglefpath + "/" + maglefname
+ ):
+ magleffiles = glob.glob(
+ maglefpath + "/*.mag"
+ )
+ else:
+ magleffiles = [
+ maglefpath + "/" + maglefname
+ ]
+
+ for magleffile in magleffiles:
+ # Generate LEF file. Since PDK and ip/ entries
+ # are not writeable, write into the project mag/
+ # directory.
+ magpath = self.projectpath + "/mag"
+ magname = os.path.split(magleffile)[1]
+ magroot = os.path.splitext(magname)[0]
+ leffile = magpath + "/" + magroot + ".lef"
+ if not os.path.isfile(leffile):
+ self.write_lef_file(magleffile, magpath)
+
+ if leffile in ioleflibs:
+ continue
+ elif leffile in lefprocessed:
+ continue
+ else:
+ lefprocessed.append(leffile)
+
+ lefname = os.path.split(leffile)[1]
+
+ newcoredefs = self.read_lef_macros(
+ magpath, lefname, "celllib"
+ )
+ coredefs.extend(newcoredefs)
+ corecells.extend(
+ list(item["name"] for item in newcoredefs)
+ )
+ # LEF files generated on-the-fly are not needed
+ # after they have been parsed.
+ # os.remove(leffile)
+
+ # Check if all modules in modulelist are represented by
+ # corresponding LEF macros. If not, then go looking for a LEF
+ # file in the mag/ or maglef/ directory. Then, go looking for
+ # a .mag file in the mag/ or maglef/ directory, and build a
+ # LEF macro from it.
+
+ matching = list(
+ item["name"]
+ for item in coredefs
+ if item["name"] in modulelist
+ )
+ for module in modulelist:
+ if module not in matching:
+ lefpath = self.projectpath + "/lef"
+ magpath = self.projectpath + "/mag"
+ maglefpath = self.projectpath + "/mag"
+ lefname = libfile.replace(".v", ".lef")
+
+ # If the verilog file root name is not the same as
+ # the module name, then make a quick check for a
+ # LEF file with the same root name as the verilog.
+ # That indicates that the module does not exist in
+ # the LEF file, probably because it is a primary
+ # module that does not correspond to any layout.
+
+ leffile = lefpath + "/" + lefname
+ if os.path.exists(leffile):
+ self.print(
+ "Diagnostic: module "
+ + module
+ + " is not in "
+ + leffile
+ + " (probably a primary module)"
+ )
+ continue
+
+ leffile = magpath + "/" + lefname
+ istemp = False
+ if not os.path.exists(leffile):
+ magname = libfile.replace(".v", ".mag")
+ magfile = magpath + "/" + magname
+ if os.path.exists(magfile):
+ self.print(
+ "Diagnostic: Found a .mag file for "
+ + module
+ + " in "
+ + magfile
+ )
+ self.write_lef_file(magfile)
+ istemp = True
+ else:
+ magleffile = maglefpath + "/" + lefname
+ if not os.path.exists(magleffile):
+ self.print(
+ "Diagnostic: (module "
+ + module
+ + ") has no LEF file "
+ + leffile
+ + " or "
+ + magleffile
+ )
+ magleffile = maglefpath + "/" + magname
+ if os.path.exists(magleffile):
+ self.print(
+ "Diagnostic: Found a .mag file for "
+ + module
+ + " in "
+ + magleffile
+ )
+ if os.access(maglefpath, os.W_OK):
+ self.write_lef_file(magleffile)
+ leffile = magleffile
+ istemp = True
+ else:
+ self.write_lef_file(
+ magleffile, magpath
+ )
+ else:
+ self.print(
+ "Did not find a file " + magfile
+ )
+ # self.print('Warning: module ' + module + ' has no LEF or .mag views')
+ pass
+ else:
+ self.print(
+ "Diagnostic: Found a LEF file for "
+ + module
+ + " in "
+ + magleffile
+ )
+ leffile = magleffile
+ else:
+ self.print(
+ "Diagnostic: Found a LEF file for "
+ + module
+ + " in "
+ + leffile
+ )
+
+ if os.path.exists(leffile):
+ if leffile in lefprocessed:
+ continue
+ else:
+ lefprocessed.append(leffile)
+
+ newcoredefs = self.read_lef_macros(
+ magpath, lefname, "celllib"
+ )
+ # The LEF file generated on-the-fly is not needed
+ # any more after parsing the macro(s).
+ # if istemp:
+ # os.remove(leffile)
+ coredefs.extend(newcoredefs)
+ corecells.extend(
+ list(item["name"] for item in newcoredefs)
+ )
+ else:
+ # self.print('Failed to find a LEF view for module ' + module)
+ pass
+
+ elif vlogparse[0] in verilogcells:
+ # Check for array of pads
+ bushigh = buslow = -1
+ if len(vlogparse) >= 3:
+ bmatch = busrex.match(vlogline)
+ if bmatch:
+ bushigh = int(bmatch.group(1))
+ buslow = int(bmatch.group(2))
+
+ for i in range(buslow, bushigh + 1):
+ newpad = {}
+ if i >= 0:
+ newpad["name"] = vlogparse[1] + "[" + str(i) + "]"
+ else:
+ newpad["name"] = vlogparse[1]
+ # hack
+ newpad["name"] = newpad["name"].replace("\\", "")
+ newpad["cell"] = vlogparse[0]
+ padcell = next(
+ item
+ for item in celldefs
+ if item["name"] == vlogparse[0]
+ )
+ newpad["iolib"] = padcell["iolib"]
+ newpad["class"] = padcell["class"]
+ newpad["subclass"] = padcell["subclass"]
+ newpad["width"] = padcell["width"]
+ newpad["height"] = padcell["height"]
+ newpadlist.append(newpad)
+
+ elif vlogparse[0] in corecells:
+ # Check for array of cells
+ bushigh = buslow = -1
+ if len(vlogparse) >= 3:
+ bmatch = busrex.match(vlogline)
+ if bmatch:
+ bushigh = int(bmatch.group(1))
+ buslow = int(bmatch.group(2))
+
+ for i in range(buslow, bushigh + 1):
+ newcorecell = {}
+ if i >= 0:
+ newcorecell["name"] = vlogparse[1] + "[" + str(i) + "]"
+ else:
+ newcorecell["name"] = vlogparse[1]
+ newcorecell["cell"] = vlogparse[0]
+ corecell = next(
+ item
+ for item in coredefs
+ if item["name"] == vlogparse[0]
+ )
+ newcorecell["celllib"] = corecell["celllib"]
+ newcorecell["class"] = corecell["class"]
+ newcorecell["subclass"] = corecell["subclass"]
+ newcorecell["width"] = corecell["width"]
+ newcorecell["height"] = corecell["height"]
+ corecelllist.append(newcorecell)
+
+ self.print("")
+ self.print("Source file information:")
+ self.print("Source filename: " + vlogfile)
+ self.print("Number of I/O libraries is " + str(len(ioleflibs)))
+ self.print(
+ "Number of library cells in I/O libraries used: " + str(len(verilogcells))
+ )
+ self.print("Number of core celldefs is " + str(len(coredefs)))
+ self.print("")
+ self.print("Number of I/O cells in design: " + str(len(newpadlist)))
+ self.print("Number of core cells in design: " + str(len(corecelllist)))
+ self.print("")
+
+ # Save the results
+ self.celldefs = celldefs
+ self.coredefs = coredefs
+ self.vlogpads = newpadlist
+ self.corecells = corecelllist
+ self.ioleflibs = ioleflibs
+
+ # Check self.vlogpads, which was created during import (above) against
+ # self.(N,S,W,E)pads, which was read from the DEF file (if there was one)
+ # Also check self.corecells, which was created during import against
+ # self.coregroup, which was read from the DEF file.
+
+ def resolve(self):
+ self.print("Resolve differences in verilog and LEF views.")
+
+ samepads = []
+ addedpads = []
+ removedpads = []
+
+ # (1) Create list of entries that are in both self.vlogpads and self.()pads
+ # (2) Create list of entries that are in self.vlogpads but not in self.()pads
+
+ allpads = (
+ self.Npads
+ + self.NEpad
+ + self.Epads
+ + self.SEpad
+ + self.Spads
+ + self.SWpad
+ + self.Wpads
+ + self.NWpad
+ )
+
+ for pad in self.vlogpads:
+ newpadname = pad["name"]
+ try:
+ lpad = next(item for item in allpads if item["name"] == newpadname)
+ except Exception:
+ addedpads.append(pad)
+ else:
+ samepads.append(lpad)
+
+ # (3) Create list of entries that are in allpads but not in self.vlogpads
+ for pad in allpads:
+ newpadname = pad["name"]
+ try:
+ lpad = next(
+ item for item in self.vlogpads if item["name"] == newpadname
+ )
+ except Exception:
+ removedpads.append(pad)
+
+ # Print results
+ if len(addedpads) > 0:
+ self.print("Added pads:")
+ for pad in addedpads:
+ self.print(pad["name"] + " (" + pad["cell"] + ")")
+
+ if len(removedpads) > 0:
+ plist = []
+ nspacers = 0
+ for pad in removedpads:
+ if "subclass" in pad:
+ if pad["subclass"] != "SPACER":
+ plist.append(pad)
+ else:
+ nspacers += 1
+
+ if nspacers > 0:
+ self.print(str(nspacers) + " spacer cells ignored.")
+ if len(plist) > 0:
+ self.print("Removed pads:")
+ for pad in removedpads:
+ self.print(pad["name"] + " (" + pad["cell"] + ")")
+
+ if len(addedpads) + len(removedpads) == 0:
+ self.print("Pad list has not changed.")
+
+ # Remove all cells from the "removed" list, with comment
+
+ allpads = [
+ self.Npads,
+ self.NEpad,
+ self.Epads,
+ self.SEpad,
+ self.Spads,
+ self.SWpad,
+ self.Wpads,
+ self.NWpad,
+ ]
+
+ for pad in removedpads:
+ rname = pad["name"]
+ for row in allpads:
+ try:
+ rpad = next(item for item in row if item["name"] == rname)
+ except Exception:
+ rpad = None
+ else:
+ row.remove(rpad)
+
+ # Now the verilog file has no placement information, so the old padlist
+ # entries (if they exist) are preferred. Add to these the new padlist
+ # entries
+
+ # First pass for unassigned pads: Use of "CLASS ENDCAP" is preferred
+ # for identifying corner pads. Otherwise, if 'CORNER' or 'corner' is
+ # in the pad name, then make sure there is one per row in the first
+ # position. This is not foolproof and depends on the cell library
+ # using the text 'corner' in the name of the corner cell. However,
+ # if the ad hoc methods fail, the user can still manually move the
+ # corner cells to the right place (to be done: Identify if library
+ # uses ENDCAP designation for corner cells up front; don't go
+ # looking for 'corner' text if the cells are easily identifiable by
+ # LEF class).
+
+ for pad in addedpads[:]:
+ iscorner = False
+ if "class" in pad and pad["class"] == "ENDCAP":
+ iscorner = True
+ elif "CORNER" in pad["cell"].upper():
+ iscorner = True
+
+ if iscorner:
+ if self.NWpad == []:
+ self.NWpad.append(pad)
+ pad["o"] = "E"
+ addedpads.remove(pad)
+ elif self.NEpad == []:
+ self.NEpad.append(pad)
+ pad["o"] = "S"
+ addedpads.remove(pad)
+ elif self.SEpad == []:
+ self.SEpad.append(pad)
+ pad["o"] = "W"
+ addedpads.remove(pad)
+ elif self.SWpad == []:
+ self.SWpad.append(pad)
+ pad["o"] = "N"
+ addedpads.remove(pad)
+
+ numN = len(self.Npads)
+ numS = len(self.Spads)
+ numE = len(self.Epads)
+ numW = len(self.Wpads)
+
+ minnum = min(numN, numS, numE, numW)
+ minnum = max(minnum, int(len(addedpads) / 4))
+
+ # Add pads in clockwise order. Note that S and E pads are defined counterclockwise
+ for pad in addedpads:
+ if numN < minnum:
+ self.Npads.append(pad)
+ numN += 1
+ pad["o"] = "S"
+ self.print("Adding pad " + pad["name"] + " to Npads")
+ elif numE < minnum:
+ self.Epads.insert(0, pad)
+ numE += 1
+ pad["o"] = "W"
+ self.print("Adding pad " + pad["name"] + " to Epads")
+ elif numS < minnum:
+ self.Spads.insert(0, pad)
+ numS += 1
+ pad["o"] = "N"
+ self.print("Adding pad " + pad["name"] + " to Spads")
+ # elif numW < minnum:
+ else:
+ self.Wpads.append(pad)
+ numW += 1
+ pad["o"] = "E"
+ self.print("Adding pad " + pad["name"] + " to Wpads")
+
+ minnum = min(numN, numS, numE, numW)
+ minnum = max(minnum, int(len(addedpads) / 4))
+
+ # Make sure all pads have included information from the cell definition
+
+ allpads = (
+ self.Npads
+ + self.NEpad
+ + self.Epads
+ + self.SEpad
+ + self.Spads
+ + self.SWpad
+ + self.Wpads
+ + self.NWpad
+ )
+
+ for pad in allpads:
+ if "width" not in pad:
+ try:
+ celldef = next(
+ item for item in celldefs if item["name"] == pad["cell"]
+ )
+ except Exception:
+ self.print("Cell " + pad["cell"] + " not found!")
+ else:
+ pad["width"] = celldef["width"]
+ pad["height"] = celldef["height"]
+ pad["class"] = celldef["class"]
+ pad["subclass"] = celldef["subclass"]
+
+ # Now treat the core cells in the same way (resolve list parsed from verilog
+ # against the list parsed from DEF)
+
+ # self.print('Diagnostic: ')
+ # self.print('self.corecells = ' + str(self.corecells))
+ # self.print('self.coregroup = ' + str(self.coregroup))
+
+ samecore = []
+ addedcore = []
+ removedcore = []
+
+ # (1) Create list of entries that are in both self.corecells and self.coregroup
+ # (2) Create list of entries that are in self.corecells but not in self.coregroup
+
+ for cell in self.corecells:
+ newcellname = cell["name"]
+ try:
+ lcore = next(
+ item for item in self.coregroup if item["name"] == newcellname
+ )
+ except Exception:
+ addedcore.append(cell)
+ else:
+ samecore.append(lcore)
+
+ # (3) Create list of entries that are in self.coregroup but not in self.corecells
+ for cell in self.coregroup:
+ newcellname = cell["name"]
+ try:
+ lcore = next(
+ item for item in self.corecells if item["name"] == newcellname
+ )
+ except Exception:
+ removedcore.append(cell)
+
+ # Print results
+ if len(addedcore) > 0:
+ self.print("Added core cells:")
+ for cell in addedcore:
+ self.print(cell["name"] + " (" + cell["cell"] + ")")
+
+ if len(removedcore) > 0:
+ clist = []
+ for cell in removedcore:
+ clist.append(cell)
+
+ if len(clist) > 0:
+ self.print("Removed core cells:")
+ for cell in removedcore:
+ self.print(cell["name"] + " (" + cell["cell"] + ")")
+
+ if len(addedcore) + len(removedcore) == 0:
+ self.print("Core cell list has not changed.")
+
+ # Remove all cells from the "removed" list
+
+ coregroup = self.coregroup
+ for cell in removedcore:
+ rname = cell["name"]
+ try:
+ rcell = next(item for item in coregroup if item["name"] == rname)
+ except Exception:
+ rcell = None
+ else:
+ coregroup.remove(rcell)
+
+ # Add all cells from the "added" list to coregroup
+
+ for cell in addedcore:
+ rname = cell["name"]
+ try:
+ rcell = next(item for item in coregroup if item["name"] == rname)
+ except Exception:
+ coregroup.append(cell)
+ if not "o" in cell:
+ cell["o"] = "N"
+ if not "x" in cell:
+ if len(self.Wpads) > 0:
+ pad = self.Wpads[0]
+ padx = pad["x"] if "x" in pad else 0
+ cell["x"] = padx + pad["height"] + self.margin
+ else:
+ cell["x"] = self.margin
+ if not "y" in cell:
+ if len(self.Spads) > 0:
+ pad = self.Spads[0]
+ pady = pad["y"] if "y" in pad else 0
+ cell["y"] = pady + pad["height"] + self.margin
+ else:
+ cell["y"] = self.margin
+ else:
+ rcell = None
+
+ # Make sure all core cells have included information from the cell definition
+
+ for cell in coregroup:
+ if "width" not in cell:
+ try:
+ coredef = next(
+ item for item in coredefs if item["name"] == cell["cell"]
+ )
+ except Exception:
+ self.print("Cell " + cell["cell"] + " not found!")
+ else:
+ cell["width"] = coredef["width"]
+ cell["height"] = coredef["height"]
+ cell["class"] = coredef["class"]
+ cell["subclass"] = coredef["subclass"]
+
+ # Generate a new padframe by writing the configuration file, running
+ # padring, reading back the DEF file, and (re)poplulating the workspace
+
+ def generate(self, level):
+ self.print("Generate legal padframe using padring")
+
+ # Write out the configuration file
+ self.writeconfig()
+ # Run the padring app
+ self.runpadring()
+ # Rotate pads in the output if pad orientations are different from
+ # padring's expectations
+ self.rotate_pads_in_def()
+ # Read the placement information back from the generated DEF file
+ self.readplacement()
+ # Resolve differences (e.g., remove spacers)
+ self.resolve()
+ # Recreate and draw the padframe view on the canvas
+ self.populate(level + 1)
+ self.frame_configure(None)
+
+ # Write a new configuration file
+
+ def writeconfig(self):
+ mag_path = self.projectpath + "/mag"
+
+ self.print("Writing padring configuration file.")
+
+ # Determine cell width and height from pad sizes.
+ # NOTE: This compresses the chip to the minimum dimensions
+ # allowed by the arrangement of pads. Use a "core" block to
+ # force the area larger than minimum (not yet implemented)
+
+ topwidth = 0
+ for pad in self.Npads:
+ if "width" not in pad:
+ self.print("No width: pad = " + str(pad))
+ topwidth += pad["width"]
+
+ # Add in the corner cells
+ if self.NWpad != []:
+ topwidth += self.NWpad[0]["height"]
+ if self.NEpad != []:
+ topwidth += self.NEpad[0]["width"]
+
+ botwidth = 0
+ for pad in self.Spads:
+ botwidth += pad["width"]
+
+ # Add in the corner cells
+ if self.SWpad != []:
+ botwidth += self.SWpad[0]["width"]
+ if self.SEpad != []:
+ botwidth += self.SEpad[0]["height"]
+
+ width = max(botwidth, topwidth)
+
+ # if width < self.urx - self.llx:
+ # width = self.urx - self.llx
+
+ leftheight = 0
+ for pad in self.Wpads:
+ leftheight += pad["width"]
+
+ # Add in the corner cells
+ if self.NWpad != []:
+ leftheight += self.NWpad[0]["height"]
+ if self.SWpad != []:
+ leftheight += self.SWpad[0]["width"]
+
+ rightheight = 0
+ for pad in self.Epads:
+ rightheight += pad["width"]
+
+ # Add in the corner cells
+ if self.NEpad != []:
+ rightheight += self.NEpad[0]["width"]
+ if self.SEpad != []:
+ rightheight += self.SEpad[0]["height"]
+
+ height = max(leftheight, rightheight)
+
+ # Check the dimensions of the core cells. If they exceed the available
+ # padframe area, then expand the padframe to accomodate the core.
+
+ corellx = coreurx = (self.llx + self.urx) / 2
+ corelly = coreury = (self.lly + self.ury) / 2
+
+ for corecell in self.coregroup:
+ corient = corecell["o"]
+ if "S" in corient or "N" in corient:
+ cwidth = corecell["width"]
+ cheight = corecell["height"]
+ else:
+ cwidth = corecell["height"]
+ cheight = corecell["width"]
+
+ if corecell["x"] < corellx:
+ corellx = corecell["x"]
+ if corecell["x"] + cwidth > coreurx:
+ coreurx = corecell["x"] + cwidth
+ if corecell["y"] < corelly:
+ corelly = corecell["y"]
+ if corecell["y"] + cheight > coreury:
+ coreury = corecell["y"] + cheight
+
+ coreheight = coreury - corelly
+ corewidth = coreurx - corellx
+
+ # Ignoring the possibility of overlaps with nonstandard-sized pads,
+ # assuming that the user has visually separated them. Only check
+ # the core bounds against the standard padframe inside edge.
+
+ if self.SWpad != [] and self.SEpad != []:
+ if corewidth > width - self.SWpad[0]["width"] - self.SEpad[0]["width"]:
+ width = corewidth + self.SWpad[0]["width"] + self.SEpad[0]["width"]
+ if self.NWpad != [] and self.SWpad != []:
+ if coreheight > height - self.NWpad[0]["height"] - self.SWpad[0]["height"]:
+ height = coreheight + self.NWpad[0]["height"] + self.SWpad[0]["height"]
+
+ # Core cells are given a margin of self.margin from the pad inside edge, so the
+ # core area passed to the padring app is 2 * self.margin larger than the
+ # measured size of the core area.
+ width += 2 * self.margin
+ height += 2 * self.margin
+
+ # SCALE UP
+ # width *= 1.4
+ # height *= 1.4
+
+ if self.keep_cfg == False or not os.path.exists(mag_path + "/padframe.cfg"):
+
+ if os.path.exists(mag_path + "/padframe.cfg"):
+ # Copy the previous padframe.cfg file to a backup. In case something
+ # goes badly wrong, this should be the only file overwritten, and can
+ # be recovered from the backup.
+ shutil.copy(mag_path + "/padframe.cfg", mag_path + "/padframe.cfg.bak")
+
+ with open(mag_path + "/padframe.cfg", "w") as ofile:
+ print(
+ "AREA " + str(int(width)) + " " + str(int(height)) + " ;",
+ file=ofile,
+ )
+ print("", file=ofile)
+ for pad in self.NEpad:
+ print(
+ "CORNER " + pad["name"] + " SW " + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.SEpad:
+ print(
+ "CORNER " + pad["name"] + " NW " + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.SWpad:
+ print(
+ "CORNER " + pad["name"] + " NE " + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.NWpad:
+ print(
+ "CORNER " + pad["name"] + " SE " + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.Npads:
+ flip = "F " if "F" in pad["o"] else ""
+ print(
+ "PAD " + pad["name"] + " N " + flip + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.Epads:
+ flip = "F " if "F" in pad["o"] else ""
+ print(
+ "PAD " + pad["name"] + " E " + flip + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.Spads:
+ flip = "F " if "F" in pad["o"] else ""
+ print(
+ "PAD " + pad["name"] + " S " + flip + pad["cell"] + " ;",
+ file=ofile,
+ )
+ for pad in self.Wpads:
+ flip = "F " if "F" in pad["o"] else ""
+ print(
+ "PAD " + pad["name"] + " W " + flip + pad["cell"] + " ;",
+ file=ofile,
+ )
+
+ # Run the padring app.
+
+ def runpadring(self):
+ self.print("Running padring")
+
+ mag_path = self.projectpath + "/mag"
+ if self.padring_path:
+ padringopts = [self.padring_path]
+ else:
+ padringopts = ["padring"]
+
+ # Diagnostic
+ # self.print('Used libraries (self.ioleflibs) = ' + str(self.ioleflibs))
+
+ for iolib in self.ioleflibs:
+ padringopts.append("-L")
+ padringopts.append(iolib)
+ padringopts.append("--def")
+ padringopts.append("padframe.def")
+ padringopts.append("padframe.cfg")
+
+ self.print("Running " + str(padringopts))
+
+ p = subprocess.Popen(
+ padringopts, stdout=subprocess.PIPE, stderr=subprocess.PIPE, cwd=mag_path
+ )
+ self.watch(p)
+
+ # Read placement information from the DEF file generated by padring.
+
+ def readplacement(self, precheck=False):
+ self.print("Reading placement information from DEF file")
+
+ mag_path = self.projectpath + "/mag"
+ if not os.path.isfile(mag_path + "/padframe.def"):
+ if not precheck:
+ self.print("No file padframe.def: pad frame was not generated.")
+ return False
+
+ # Very simple DEF file parsing. The placement DEF only contains a
+ # COMPONENTS section. Certain assumptions are made about the syntax
+ # that depends on the way 'padring' writes its output. This is not
+ # a rigorous DEF parser!
+
+ units = 1000
+ in_components = False
+ Npadlist = []
+ Spadlist = []
+ Epadlist = []
+ Wpadlist = []
+ NEpad = []
+ NWpad = []
+ SEpad = []
+ SWpad = []
+ coregroup = []
+
+ # Reset bounds
+ self.llx = self.lly = self.urx = self.ury = 0
+ corners = 0
+
+ with open(mag_path + "/padframe.def", "r") as ifile:
+ deflines = ifile.read().splitlines()
+ for line in deflines:
+ if "UNITS DISTANCE MICRONS" in line:
+ units = line.split()[3]
+ elif in_components:
+ lparse = line.split()
+ if lparse[0] == "-":
+ instname = lparse[1]
+ cellname = lparse[2]
+
+ elif lparse[0] == "+":
+ if lparse[1] == "FIXED":
+ placex = lparse[3]
+ placey = lparse[4]
+ placeo = lparse[6]
+
+ newpad = {}
+ newpad["name"] = instname
+ newpad["cell"] = cellname
+
+ try:
+ celldef = next(
+ item
+ for item in self.celldefs
+ if item["name"] == cellname
+ )
+ except Exception:
+ celldef = None
+ else:
+ newpad["iolib"] = celldef["iolib"]
+ newpad["width"] = celldef["width"]
+ newpad["height"] = celldef["height"]
+ newpad["class"] = celldef["class"]
+ newpad["subclass"] = celldef["subclass"]
+
+ newpad["x"] = float(placex) / float(units)
+ newpad["y"] = float(placey) / float(units)
+ newpad["o"] = placeo
+
+ # Adjust bounds
+ if celldef:
+ if newpad["x"] < self.llx:
+ self.llx = newpad["x"]
+ if newpad["y"] < self.lly:
+ self.lly = newpad["y"]
+
+ if newpad["o"] == "N" or newpad["o"] == "S":
+ padurx = newpad["x"] + celldef["width"]
+ padury = newpad["y"] + celldef["height"]
+ else:
+ padurx = newpad["x"] + celldef["height"]
+ padury = newpad["y"] + celldef["width"]
+
+ if padurx > self.urx:
+ self.urx = padurx
+ if padury > self.ury:
+ self.ury = padury
+
+ # First four entries in the DEF file are corners
+ # padring puts the lower left corner at zero, so
+ # use the zero coordinates to determine which pads
+ # are which. Note that padring assumes the corner
+ # pad is drawn in the SW corner position!
+
+ if corners < 4:
+ if newpad["x"] == 0 and newpad["y"] == 0:
+ SWpad.append(newpad)
+ elif newpad["x"] == 0:
+ NWpad.append(newpad)
+ elif newpad["y"] == 0:
+ SEpad.append(newpad)
+ else:
+ NEpad.append(newpad)
+ corners += 1
+ else:
+ # Place according to orientation. If orientation
+ # is not standard, be sure to make it standard!
+ placeo = self.rotate_orientation(placeo)
+ if placeo == "N":
+ Spadlist.append(newpad)
+ elif placeo == "E":
+ Wpadlist.append(newpad)
+ elif placeo == "S":
+ Npadlist.append(newpad)
+ else:
+ Epadlist.append(newpad)
+
+ elif "END COMPONENTS" in line:
+ in_components = False
+ elif "COMPONENTS" in line:
+ in_components = True
+
+ self.Npads = Npadlist
+ self.Wpads = Wpadlist
+ self.Spads = Spadlist
+ self.Epads = Epadlist
+
+ self.NWpad = NWpad
+ self.NEpad = NEpad
+ self.SWpad = SWpad
+ self.SEpad = SEpad
+
+ # The padframe has its own DEF file from the padring app, but the core
+ # does not. The core needs to be floorplanned in a very similar manner.
+ # This will be done by searching for a DEF file of the project top-level
+ # layout. If none exists, it is created by generating it from the layout.
+ # If the top-level layout does not exist, then all core cells are placed
+ # at the origin, and the origin placed at the padframe inside corner.
+
+ mag_path = self.projectpath + "/mag"
+ if not os.path.isfile(mag_path + "/" + self.project + ".def"):
+ if os.path.isfile(mag_path + "/" + self.project + ".mag"):
+
+ # Create a DEF file from the layout
+ with open(mag_path + "/pfg_write_def.tcl", "w") as ofile:
+ print("drc off", file=ofile)
+ print("box 0 0 0 0", file=ofile)
+ print("load " + self.project, file=ofile)
+ print("def write", file=ofile)
+ print("quit", file=ofile)
+
+ magicexec = self.magic_path if self.magic_path else "magic"
+ mproc = subprocess.Popen(
+ [magicexec, "-dnull", "-noconsole", "pfg_write_def.tcl"],
+ stdin=subprocess.PIPE,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE,
+ cwd=mag_path,
+ universal_newlines=True,
+ )
+
+ self.watch(mproc)
+ os.remove(mag_path + "/pfg_write_def.tcl")
+
+ elif not os.path.isfile(mag_path + "/core.def"):
+
+ # With no other information available, copy the corecells
+ # (from the verilog file) into the coregroup list.
+ # Position all core cells starting at the padframe top left
+ # inside corner, and arranging in rows without overlapping.
+ # Note that no attempt is made to organize the cells or
+ # otherwise produce an efficient layout. Any dimension larger
+ # than the current padframe overruns to the right or bottom.
+
+ if self.SWpad != []:
+ corellx = SWpad[0]["x"] + SWpad[0]["width"] + self.margin
+ corelly = SWpad[0]["y"] + SWpad[0]["height"] + self.margin
+ else:
+ corellx = Wpadlist[0]["x"] + Wpadlist[0]["height"] + self.margin
+ corelly = Spadlist[0]["x"] + Spadlist[0]["height"] + self.margin
+ if self.NEpad != []:
+ coreurx = NEpad[0]["x"] - self.margin
+ coreury = NEpad[0]["y"] - self.margin
+ else:
+ coreurx = Epadlist[0]["x"] - self.margin
+ coreury = Npadlist[0]["x"] - self.margin
+ locllx = corellx
+ testllx = corellx
+ loclly = corelly
+ testlly = corelly
+ nextlly = corelly
+
+ for cell in self.corecells:
+
+ testllx = locllx + cell["width"]
+ if testllx > coreurx:
+ locllx = corellx
+ corelly = nextlly
+ loclly = nextlly
+
+ newcore = cell
+ newcore["x"] = locllx
+ newcore["y"] = loclly
+ newcore["o"] = "N"
+
+ locllx += cell["width"] + self.margin
+
+ testlly = corelly + cell["height"] + self.margin
+ if testlly > nextlly:
+ nextlly = testlly
+
+ coregroup.append(newcore)
+
+ self.coregroup = coregroup
+
+ if os.path.isfile(mag_path + "/" + self.project + ".def"):
+ # Read the top-level DEF, and use it to position the core cells.
+ self.print("Reading the top-level cell DEF for core cell placement.")
+
+ units = 1000
+ in_components = False
+ with open(mag_path + "/" + self.project + ".def", "r") as ifile:
+ deflines = ifile.read().splitlines()
+ for line in deflines:
+ if "UNITS DISTANCE MICRONS" in line:
+ units = line.split()[3]
+ elif in_components:
+ lparse = line.split()
+ if lparse[0] == "-":
+ instname = lparse[1]
+ # NOTE: Magic should not drop the entire path to the
+ # cell for the cellname; this needs to be fixed! To
+ # work around it, remove any path components.
+ cellpath = lparse[2]
+ cellname = os.path.split(cellpath)[1]
+
+ elif lparse[0] == "+":
+ if lparse[1] == "PLACED":
+ placex = lparse[3]
+ placey = lparse[4]
+ placeo = lparse[6]
+
+ newcore = {}
+ newcore["name"] = instname
+ newcore["cell"] = cellname
+
+ try:
+ celldef = next(
+ item
+ for item in self.coredefs
+ if item["name"] == cellname
+ )
+ except Exception:
+ celldef = None
+ else:
+ newcore["celllib"] = celldef["celllib"]
+ newcore["width"] = celldef["width"]
+ newcore["height"] = celldef["height"]
+ newcore["class"] = celldef["class"]
+ newcore["subclass"] = celldef["subclass"]
+
+ newcore["x"] = float(placex) / float(units)
+ newcore["y"] = float(placey) / float(units)
+ newcore["o"] = placeo
+ coregroup.append(newcore)
+
+ elif "END COMPONENTS" in line:
+ in_components = False
+ elif "COMPONENTS" in line:
+ in_components = True
+
+ self.coregroup = coregroup
+
+ elif os.path.isfile(mag_path + "/core.def"):
+ # No DEF or .mag file, so fallback position is the last core.def
+ # file generated by this script.
+ self.read_core_def(precheck=precheck)
+
+ return True
+
+ # Read placement information from the "padframe.def" file and rotate
+ # all cells according to self.pad_rotation. This accounts for the
+ # problem that the default orientation of pads is arbitrarily defined
+ # by the foundry, while padring assumes that the corner pad is drawn
+ # in the lower-left position and other pads are drawn with the pad at
+ # the bottom and the buses at the top.
+
+ def rotate_pads_in_def(self):
+ if self.pad_rotation == 0:
+ return
+
+ self.print("Rotating pads in padframe DEF file.")
+ mag_path = self.projectpath + "/mag"
+
+ if not os.path.isfile(mag_path + "/padframe.def"):
+ self.print("No file padframe.def: Cannot modify pad rotations.")
+ return
+
+ deflines = []
+ with open(mag_path + "/padframe.def", "r") as ifile:
+ deflines = ifile.read().splitlines()
+
+ outlines = []
+ in_components = False
+ for line in deflines:
+ if in_components:
+ lparse = line.split()
+ if lparse[0] == "+":
+ if lparse[1] == "PLACED":
+ lparse[1] = "FIXED"
+ neworient = lparse[6]
+ lparse[6] = neworient
+ line = " ".join(lparse)
+
+ elif "END COMPONENTS" in line:
+ in_components = False
+ elif "COMPONENTS" in line:
+ in_components = True
+ outlines.append(line)
+
+ with open(mag_path + "/padframe.def", "w") as ofile:
+ for line in outlines:
+ print(line, file=ofile)
+
+ # Read placement information from the DEF file for the core (created by
+ # a previous run of this script)
+
+ def read_core_def(self, precheck=False):
+ self.print("Reading placement information from core DEF file.")
+
+ mag_path = self.projectpath + "/mag"
+
+ if not os.path.isfile(mag_path + "/core.def"):
+ if not precheck:
+ self.print("No file core.def: core placement was not generated.")
+ return False
+
+ # Very simple DEF file parsing, similar to the padframe.def reading
+ # routine above.
+
+ units = 1000
+ in_components = False
+
+ coregroup = []
+
+ with open(mag_path + "/core.def", "r") as ifile:
+ deflines = ifile.read().splitlines()
+ for line in deflines:
+ if "UNITS DISTANCE MICRONS" in line:
+ units = line.split()[3]
+ elif in_components:
+ lparse = line.split()
+ if lparse[0] == "-":
+ instname = lparse[1]
+ cellname = lparse[2]
+
+ elif lparse[0] == "+":
+ if lparse[1] == "PLACED":
+ placex = lparse[3]
+ placey = lparse[4]
+ placeo = lparse[6]
+
+ newcore = {}
+ newcore["name"] = instname
+ newcore["cell"] = cellname
+
+ try:
+ celldef = next(
+ item
+ for item in self.coredefs
+ if item["name"] == cellname
+ )
+ except Exception:
+ celldef = None
+ else:
+ newcore["celllib"] = celldef["celllib"]
+ newcore["width"] = celldef["width"]
+ newcore["height"] = celldef["height"]
+ newcore["class"] = celldef["class"]
+ newcore["subclass"] = celldef["subclass"]
+
+ newcore["x"] = float(placex) / float(units)
+ newcore["y"] = float(placey) / float(units)
+ newcore["o"] = placeo
+ coregroup.append(newcore)
+
+ elif "END COMPONENTS" in line:
+ in_components = False
+ elif "COMPONENTS" in line:
+ in_components = True
+
+ self.coregroup = coregroup
+
+ return True
+
+ # Save the layout to a Magic database file (to be completed)
+
+ def save(self):
+ self.print("Saving results in a magic layout database.")
+
+ # Generate a list of (unique) LEF libraries for all padframe and core cells
+ leflist = []
+ for pad in self.celldefs:
+ if pad["iolib"] not in leflist:
+ leflist.append(pad["iolib"])
+
+ for core in self.coredefs:
+ if core["celllib"] not in leflist:
+ leflist.append(core["celllib"])
+
+ # Run magic, and generate the padframe with a series of commands
+ mag_path = self.projectpath + "/mag"
+
+ with open(mag_path + "/pfg_write_mag.tcl", "w") as ofile:
+ print("drc off", file=ofile)
+ print("box 0 0 0 0", file=ofile)
+ for leffile in leflist:
+ print("lef read " + leffile, file=ofile)
+ print("def read padframe", file=ofile)
+ print("select top cell", file=ofile)
+ print("select area", file=ofile)
+ print("select save padframe", file=ofile)
+ print("delete", file=ofile)
+ print("def read core", file=ofile)
+ print("getcell padframe", file=ofile)
+ print("save " + self.project, file=ofile)
+ print("writeall force " + self.project, file=ofile)
+ print("quit", file=ofile)
+
+ magicexec = self.magic_path if self.magic_path else "magic"
+ mproc = subprocess.Popen(
+ [magicexec, "-dnull", "-noconsole", "pfg_write_mag.tcl"],
+ stdin=subprocess.PIPE,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.PIPE,
+ cwd=mag_path,
+ universal_newlines=True,
+ )
+ self.watch(mproc)
+ os.remove(mag_path + "/pfg_write_mag.tcl")
+ self.print("Done writing layout " + self.project + ".mag")
+
+ # Write the core DEF file if it does not exist yet.
+ if not os.path.isfile(mag_path + "/core.def"):
+ self.write_core_def()
+
+
+if __name__ == "__main__":
+ faulthandler.register(signal.SIGUSR2)
+ options = []
+ arguments = []
+ for item in sys.argv[1:]:
+ if item.find("-", 0) == 0:
+ options.append(item)
+ else:
+ arguments.append(item)
+
+ if "-help" in options:
+ print(sys.argv[0] + " [options]")
+ print("")
+ print("options:")
+ print(" -noc Print output to terminal, not the gui window")
+ print(" -nog No graphics, run in batch mode")
+ print(" -cfg Use existing padframe.cfg, do not regenerate")
+ print(" -padring-path=<path> path to padring executable")
+ print(" -magic-path=<path> path to magic executable")
+ print(" -tech-path=<path> path to tech root folder")
+ print(" -project-path=<path> path to project root folder")
+ print(" -help Print this usage information")
+ print("")
+ sys.exit(0)
+
+ root = tkinter.Tk()
+ do_gui = False if ("-nog" in options or "-nogui" in options) else True
+ app = SoCFloorplanner(root, do_gui)
+
+ # Allow option -noc to bypass the text-to-console redirection, so crash
+ # information doesn't disappear with the app.
+
+ app.use_console = False if ("-noc" in options or "-noconsole" in options) else True
+ if do_gui == False:
+ app.use_console = False
+
+ # efabless format can be specified on the command line, but note that it
+ # is otherwise auto-detected by checking for .config vs. .ef-config in
+ # the project space.
+
+ app.ef_format = True if "-ef_format" in options else False
+ app.keep_cfg = True if "-cfg" in options else False
+
+ app.padring_path = None
+ app.magic_path = None
+ app.techpath = None
+ app.projectpath = None
+
+ for option in options:
+ if option.split("=")[0] == "-padring-path":
+ app.padring_path = option.split("=")[1]
+ elif option.split("=")[0] == "-magic-path":
+ app.magic_path = option.split("=")[1]
+ elif option.split("=")[0] == "-tech-path":
+ app.techpath = option.split("=")[1]
+ elif option.split("=")[0] == "-project-path":
+ app.projectpath = option.split("=")[1]
+ app.projectpath = (
+ app.projectpath[:-1] if app.projectpath[-1] == "/" else app.projectpath
+ )
+
+ app.text_to_console()
+ app.init_padframe()
+ if app.do_gui:
+ root.mainloop()
+ else:
+ # Run 'save' in non-GUI mode
+ app.save()
+ sys.exit(0)
diff --git a/openlane/scripts/padringer.py b/openlane/scripts/padringer.py
new file mode 100644
index 0000000..7e46e13
--- /dev/null
+++ b/openlane/scripts/padringer.py
@@ -0,0 +1,446 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Reads in a structural verilog containing pads and a LEF file that
+contains at least those pads and produces a DEF file with the padframe.
+TODO:
+core placement
+config init,
+external config
+"""
+import os
+import sys
+import argparse
+from subprocess import Popen, PIPE
+
+import odb
+
+# TECH = ""
+# PDK_ROOT = os.environ["PDK_ROOT"]
+# os.environ["MAGTYPE"] = "maglef"
+
+parser = argparse.ArgumentParser(description="Generates a padframe DEF")
+
+# required if -cfg is not specified
+parser.add_argument(
+ "--verilog-netlist",
+ "-verilog",
+ help="A structural verilog containing the pads (and other user macros)",
+)
+
+parser.add_argument(
+ "--def-netlist",
+ "-def",
+ help="A DEF file containing the unplaced pads (and other user macros)",
+)
+
+parser.add_argument("--design", "-d", help="Name of the top-level module")
+
+parser.add_argument("--width", help="Width of the die area")
+
+parser.add_argument("--height", help="Height of the die area")
+
+
+parser.add_argument(
+ "--output-def", "-o", required=True, help="Name of the output file name"
+)
+
+parser.add_argument("--padframe-config", "-cfg", help="CFG file -- input to padring")
+
+parser.add_argument(
+ "--pad-name-prefixes",
+ "-prefixes",
+ default=["sky130_fd_io", "sky130_ef_io"],
+ help="e.g., sky130_fd_io",
+)
+
+parser.add_argument(
+ "--init-padframe-config",
+ "-init",
+ action="store_true",
+ default=False,
+ help="Only generate a CFG file to be user edited",
+)
+
+parser.add_argument(
+ "--working-dir",
+ "-dir",
+ default=".",
+ help="Working directory to create temporary files needed",
+)
+
+parser.add_argument(
+ "--special-nets",
+ "-special",
+ nargs="+",
+ type=str,
+ default=None,
+ help="Net names to mark as special",
+)
+
+parser.add_argument(
+ "--lefs", "-l", nargs="+", type=str, default=None, required=True, help="LEF input"
+)
+
+args = parser.parse_args()
+
+verilog_netlist = args.verilog_netlist
+def_netlist = args.def_netlist
+design = args.design
+width = args.width
+height = args.height
+config_file_name = args.padframe_config
+output_file_name = args.output_def
+init_padframe_config_flag = args.init_padframe_config
+working_dir = args.working_dir
+lefs = args.lefs
+special_nets = args.special_nets
+pad_name_prefixes = args.pad_name_prefixes
+
+working_def = f"{working_dir}/{design}.pf.def"
+working_cfg = f"{working_dir}/{design}.pf.cfg"
+
+for lef in lefs:
+ assert os.path.exists(lef), lef + " doesn't exist"
+
+
+def invoke_padring(config_file_name, output_file_name):
+ print("Invoking padring to generate a padframe")
+ padring_command = []
+ padring_command.append("padring")
+ for lef in lefs:
+ padring_command.extend(["-L", lef])
+ padring_command.extend(["--def", output_file_name])
+ padring_command.append(config_file_name)
+
+ p = Popen(padring_command, stdout=PIPE, stdin=PIPE, stderr=PIPE, encoding="utf8")
+
+ output = p.communicate()
+ print("STDERR:")
+ print("\n".join(output[1].splitlines()[-10:]))
+ print("STDOUT:")
+ print(output[0].strip())
+
+ print("Padring exit code:", p.returncode)
+ assert p.returncode == 0, p.returncode
+ assert os.path.exists(output_file_name)
+
+
+# hard requirement of a user netlist either as a DEF or verilog
+# this is to ensure that the padframe will contain all pads in the design
+# whether the config is autogenerated or user-provided
+assert (
+ verilog_netlist is not None or def_netlist is not None
+), "One of --verilog_netlist or --def-netlist is required"
+
+# Step 1: create an openDB database from the verilog/def using OpenSTA's read_verilog
+if verilog_netlist is not None:
+ assert (
+ def_netlist is None
+ ), "Only one of --verilog_netlist or --def-netlist is required"
+ assert design is not None, "--design is required"
+
+ openroad_script = []
+ for lef in lefs:
+ openroad_script.append(f"read_lef {lef}")
+ openroad_script.append(f"read_verilog {verilog_netlist}")
+ openroad_script.append(f"link_design {design}")
+ openroad_script.append(f"write_def {working_def}")
+ # openroad_script.append(f"write_db {design}.pf.db")
+ openroad_script.append("exit")
+
+ p = Popen(["openroad"], stdout=PIPE, stdin=PIPE, stderr=PIPE, encoding="utf8")
+
+ openroad_script = "\n".join(openroad_script)
+ # print(openroad_script)
+
+ output = p.communicate(openroad_script)
+ print("STDOUT:")
+ print(output[0].strip())
+ print("STDERR:")
+ print(output[1].strip())
+ print("openroad exit code:", p.returncode)
+ assert p.returncode == 0, p.returncode
+ # TODO: check for errors
+else:
+ assert def_netlist is not None
+ working_def = def_netlist
+
+assert os.path.exists(working_def), "DEF file doesn't exist"
+
+db_top = odb.dbDatabase.create()
+# odb.read_db(db_top, f"{design}.pf.db")
+for lef in lefs:
+ odb.read_lef(db_top, lef)
+odb.read_def(db_top, working_def)
+
+chip_top = db_top.getChip()
+block_top = chip_top.getBlock()
+top_design_name = block_top.getName()
+
+print("Top-level design name:", top_design_name)
+
+
+## Step 2: create a simple data structure with pads from the library
+# types: corner, power, other
+pads = {}
+libs = db_top.getLibs()
+for lib in libs:
+ masters = lib.getMasters()
+ for m in masters:
+ name = m.getName()
+ if m.isPad():
+ assert any(name.startswith(p) for p in pad_name_prefixes), name
+ print("Found pad:", name)
+ pad_type = m.getType()
+ pads[name] = pad_type
+ if pad_type == "PAD_SPACER":
+ print("Found PAD_SPACER:", name)
+ elif pad_type == "PAD_AREAIO":
+ # using this for special bus fillers...
+ print("Found PAD_AREAIO", name)
+ if m.isEndCap():
+ # FIXME: regular endcaps
+ assert any(name.startswith(p) for p in pad_name_prefixes), name
+ assert not m.isPad(), name + " is both pad and endcap?"
+ print("Found corner pad:", name)
+ pads[name] = "corner"
+
+print()
+print("The I/O library contains", len(pads), "cells")
+print()
+
+assert len(pads) != 0, "^"
+
+## Step 3: Go over instances in the design and extract the used pads
+def clean_name(name):
+ return name.replace("\\", "")
+
+
+used_pads = []
+used_corner_pads = []
+other_instances = []
+for inst in block_top.getInsts():
+ inst_name = inst.getName()
+ master_name = inst.getMaster().getName()
+ if inst.isPad():
+ assert any(master_name.startswith(p) for p in pad_name_prefixes), master_name
+ print("Found pad instance", inst_name, "of type", master_name)
+ used_pads.append((inst_name, master_name))
+ elif inst.isEndCap():
+ # FIXME: regular endcaps
+ assert any(master_name.startswith(p) for p in pad_name_prefixes), master_name
+ print("Found pad instance", inst_name, "of type", master_name)
+ print("Found corner pad instance", inst_name, "of type", master_name)
+ used_corner_pads.append((inst_name, master_name))
+ else:
+ assert not any(
+ master_name.startswith(p) for p in pad_name_prefixes
+ ), master_name
+ other_instances.append(inst_name)
+
+# FIXME: if used_corner_pads aren't supposed to be instantiated
+assert len(used_corner_pads) == 4, used_corner_pads
+
+print()
+print(
+ "The user design contains",
+ len(used_pads),
+ "pads, 4 corner pads, and",
+ len(other_instances),
+ "other instances",
+)
+print()
+assert len(used_pads) != 0, "^"
+
+## Step 4: Generate a CFG or verify a user-provided config
+
+
+def chunker(seq, size):
+ chunks = [seq[i::size] for i in range(size)]
+ # sort by type
+ chunks.sort(key=lambda pad_pair: pad_pair[1])
+ return chunks
+
+
+def diff_lists(l1, l2):
+ return list(list(set(l1) - set(l2)) + list(set(l2) - set(l1)))
+
+
+def generate_cfg(north, east, south, west, corner_pads, width, height):
+ cfg = []
+ cfg.append(f"AREA {width} {height} ;")
+ cfg.append("")
+
+ assert len(corner_pads) == 4, corner_pads
+ cfg.append(f"CORNER {corner_pads[0][0]} SW {corner_pads[0][1]} ;")
+ cfg.append(f"CORNER {corner_pads[1][0]} NW {corner_pads[1][1]} ;")
+ cfg.append(f"CORNER {corner_pads[2][0]} NE {corner_pads[2][1]} ;")
+ cfg.append(f"CORNER {corner_pads[3][0]} SE {corner_pads[3][1]} ;")
+
+ cfg.append("")
+
+ for pad in north:
+ cfg.append(f"PAD {pad[0]} N {pad[1]} ;")
+
+ cfg.append("")
+
+ for pad in east:
+ cfg.append(f"PAD {pad[0]} E {pad[1]} ;")
+
+ cfg.append("")
+
+ for pad in south:
+ cfg.append(f"PAD {pad[0]} S {pad[1]} ;")
+
+ cfg.append("")
+
+ for pad in west:
+ cfg.append(f"PAD {pad[0]} W {pad[1]} ;")
+
+ return "\n".join(cfg)
+
+
+if config_file_name is not None:
+ assert os.path.exists(config_file_name), config_file_name + " doesn't exist"
+ with open(config_file_name, "r") as f:
+ lines = f.readlines()
+ user_config_pads = []
+ for line in lines:
+ if line.startswith("CORNER") or line.startswith("PAD"):
+ tokens = line.split()
+ assert len(tokens) == 5, tokens
+ inst_name, master_name = tokens[1], tokens[3]
+ if (
+ not pads[master_name] == "PAD_SPACER"
+ and not pads[master_name] == "PAD_AREAIO"
+ ):
+ user_config_pads.append((inst_name, master_name))
+ elif line.startswith("AREA"):
+ tokens = line.split()
+ assert len(tokens) == 4, tokens
+ width = int(tokens[1])
+ height = int(tokens[2])
+
+ assert sorted(user_config_pads) == sorted(used_pads + used_corner_pads), (
+ "Mismatch between the provided config and the provided netlist. Diff:",
+ diff_lists(user_config_pads, used_pads + used_corner_pads),
+ )
+
+ print("User config verified")
+ working_cfg = config_file_name
+else:
+ # TODO: get minimum width/height so that --width and --height aren't required
+ assert width is not None, "--width is required"
+ assert height is not None, "--height is required"
+
+ # auto generate a configuration
+
+ # TODO: after calssification, center power pads on each side
+ north, east, south, west = chunker(used_pads, 4)
+
+ with open(working_cfg, "w") as f:
+ f.write(generate_cfg(north, east, south, west, used_corner_pads, width, height))
+
+if not init_padframe_config_flag:
+ invoke_padring(working_cfg, working_def)
+else:
+ print(
+ "Padframe config generated at",
+ working_cfg,
+ f"Modify it and re-run this program with the '-cfg {working_cfg}' option",
+ )
+ sys.exit()
+
+print("Applying pad placements to the design DEF")
+
+db_padframe = odb.dbDatabase.create()
+for lef in lefs:
+ odb.read_lef(db_padframe, lef)
+odb.read_def(db_padframe, working_def)
+
+chip_padframe = db_padframe.getChip()
+block_padframe = chip_padframe.getBlock()
+padframe_design_name = block_padframe.getName()
+
+assert padframe_design_name == "PADRING", padframe_design_name
+
+print("Padframe design name:", padframe_design_name)
+
+# Mark special nets
+if special_nets is not None:
+ for net in block_top.getNets():
+ net_name = net.getName()
+ if net_name in special_nets:
+ print("Marking", net_name, "as a special net")
+ net.setSpecial()
+ for iterm in net.getITerms():
+ iterm.setSpecial()
+
+# get minimum width/height (core-bounded)
+
+placed_cells_count = 0
+created_cells_count = 0
+for inst in block_padframe.getInsts():
+ assert inst.isPad() or inst.isEndCap(), (
+ inst.getName() + " is neither a pad nor corner pad"
+ )
+
+ inst_name = inst.getName()
+ master = inst.getMaster()
+ master_name = master.getName()
+ x, y = inst.getLocation()
+ orient = inst.getOrient()
+
+ if (inst_name, master_name) in used_pads + used_corner_pads:
+ original_inst = block_top.findInst(inst_name)
+ assert original_inst is not None, "Failed to find " + inst_name
+ assert original_inst.getPlacementStatus() == "NONE", (
+ inst_name + " is already placed"
+ )
+ original_inst.setOrient(orient)
+ original_inst.setLocation(x, y)
+ original_inst.setPlacementStatus("FIRM")
+ placed_cells_count += 1
+ else:
+ # must be a filler cell
+ new_inst = odb.dbInst_create(
+ block_top, db_top.findMaster(master_name), inst_name
+ )
+ assert new_inst is not None, "Failed to create " + inst_name
+ new_inst.setOrient(orient)
+ new_inst.setLocation(x, y)
+ new_inst.setPlacementStatus("FIRM")
+ created_cells_count += 1
+
+# TODO: place the core macros within the padframe (chip floorplan)
+for inst in block_top.getInsts():
+ if inst.isPlaced() or inst.isFixed():
+ continue
+ print("Placing", inst.getName())
+ master = inst.getMaster()
+ master_width = master.getWidth()
+ master_height = master.getHeight()
+ print(master_width, master_height)
+ print(width, height)
+
+ inst.setLocation(
+ width * 1000 // 2 - master_width // 2, height * 1000 // 2 - master_height // 2
+ )
+ inst.setPlacementStatus("PLACED")
+
+odb.write_def(block_top, output_file_name)
+print("Done")
diff --git a/openlane/scripts/parse_klayout_xor_log.py b/openlane/scripts/parse_klayout_xor_log.py
new file mode 100644
index 0000000..db3fcb0
--- /dev/null
+++ b/openlane/scripts/parse_klayout_xor_log.py
@@ -0,0 +1,43 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import re
+
+parser = argparse.ArgumentParser(
+ description="extracts the total xor differnces from an xor log"
+)
+
+parser.add_argument("--log_file", "-l", required=True, help="log file")
+
+parser.add_argument(
+ "--output", "-o", required=True, help="output file to store results"
+)
+
+args = parser.parse_args()
+log_file_name = args.log_file
+out_file_name = args.output
+
+string = "XOR differences:"
+pattern = re.compile(r"\s*%s\s*([\d+]+)" % string)
+tot_cnt = 0
+with open(log_file_name, "r") as f:
+ for line in f:
+ m = pattern.match(line)
+ if m:
+ tot_cnt += int(m.group(1))
+
+outFileOpener = open(out_file_name, "w")
+outFileOpener.write("Total XOR differences = " + str(tot_cnt))
+outFileOpener.close()
diff --git a/openlane/scripts/pdk-linker.py b/openlane/scripts/pdk-linker.py
new file mode 100755
index 0000000..d9a0782
--- /dev/null
+++ b/openlane/scripts/pdk-linker.py
@@ -0,0 +1,105 @@
+#!/usr/bin/env python3
+
+###############################################################################
+## BSD 3-Clause License
+##
+## Copyright (c) 2022, The Regents of the University of California
+## All rights reserved.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions are met:
+##
+## * Redistributions of source code must retain the above copyright notice, this
+## list of conditions and the following disclaimer.
+##
+## * Redistributions in binary form must reproduce the above copyright notice,
+## this list of conditions and the following disclaimer in the documentation
+## and/or other materials provided with the distribution.
+##
+## * Neither the name of the copyright holder nor the names of its
+## contributors may be used to endorse or promote products derived from
+## this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+## POSSIBILITY OF SUCH DAMAGE.
+
+# The purpose of this script is to build a symbolic link farm from a
+# source PDK according to a JSON mapping file. This is to adapt a PDK
+# from a vendor into the form expected by OpenLane without actually
+# modifying the source PDK. This is in opposition to the open_pdks
+# approach which modifies the vendor PDK to fit.
+
+# This is a transitional tool. Eventually OpenLane scripts will use
+# the mapping file to directly access the files without needing the
+# link farm. This will free OL from any dependency on PDK organization.
+
+import argparse
+import glob
+import json
+import os
+
+parser = argparse.ArgumentParser(
+ description="""Builds a link farm from <source> in <dest> according to <mappings>"""
+)
+parser.add_argument("-s", "--source", required=True)
+parser.add_argument("-d", "--destination", required=True)
+parser.add_argument("-m", "--mappings", required=True)
+parser.add_argument("-v", "--verbose", action="store_true")
+
+args = parser.parse_args()
+
+
+def link_files(source_path, destination_path):
+ """Create a link from source_path to destination path unless
+ one already exists. If it exists but is different then the
+ arguments imply an exception is raised."""
+
+ destination_dir = os.path.dirname(destination_path)
+ if not os.path.isdir(destination_dir):
+ os.makedirs(destination_dir)
+ if os.path.exists(destination_path):
+ if (
+ os.path.islink(destination_path)
+ and os.path.realpath(destination_path) == source_path
+ ):
+ if args.verbose:
+ print(f" Skip {source_path} -> {destination_path}")
+ return
+ else:
+ raise Exception(f"File {destination_path} already exists")
+ os.symlink(source_path, destination_path)
+ if args.verbose:
+ print(f" Link {source_path} -> {destination_path}")
+
+
+with open(args.mappings) as f:
+ mappings = json.load(f)
+
+if not os.path.isdir(args.source):
+ raise Exception(f"{args.source} is not a directory")
+
+source = os.path.abspath(f"{args.source}")
+destination = os.path.abspath(f"{args.destination}")
+
+for category, mapping in mappings.items():
+ print(f"Linking {category}")
+ pdk = mapping["pdk"]
+ openlane = mapping["openlane"]
+ for pattern in mapping["files"]:
+ pattern = f"{source}/{pdk}/{pattern}"
+ paths = glob.glob(pattern)
+ if len(paths) == 0:
+ raise Exception(f"No matches for {pattern}")
+ for source_path in paths:
+ file_name = os.path.basename(source_path)
+ destination_path = f"{destination}/{openlane}/{file_name}"
+ link_files(source_path, destination_path)
diff --git a/openlane/scripts/place_diodes.py b/openlane/scripts/place_diodes.py
new file mode 100644
index 0000000..0178329
--- /dev/null
+++ b/openlane/scripts/place_diodes.py
@@ -0,0 +1,393 @@
+#!/usr/bin/env python3
+#
+# Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
+# SPDX-License-Identifier: Apache-2.0
+#
+
+import argparse
+import random
+import sys
+
+import odb
+
+
+class DiodeInserter:
+ def __init__(
+ self,
+ block,
+ diode_cell,
+ diode_pin,
+ fake_diode_cell=None,
+ side_strategy="source",
+ short_span=0,
+ port_protect=[],
+ verbose=False,
+ ):
+ self.block = block
+ self.verbose = verbose
+
+ self.diode_cell = diode_cell
+ self.diode_pin = diode_pin
+ self.fake_diode_cell = fake_diode_cell
+ self.side_strategy = side_strategy
+ self.short_span = short_span
+ self.port_protect = port_protect
+
+ self.true_diode_master = block.getDataBase().findMaster(diode_cell)
+ self.fake_diode_master = (
+ block.getDataBase().findMaster(fake_diode_cell)
+ if (fake_diode_cell is not None)
+ else None
+ )
+ if not self.check():
+ raise RuntimeError("True and Fake diodes are inconsistent")
+
+ self.diode_master = self.fake_diode_master or self.true_diode_master
+ self.diode_site = self.true_diode_master.getSite().getConstName()
+
+ self.inserted = {}
+
+ def check(self):
+ if self.fake_diode_master is None:
+ return True
+
+ tm = self.true_diode_master
+ fm = self.fake_diode_master
+
+ if fm.getSite() is None:
+ self.error("[!] Fake diode cell missing SITE attribute")
+ else:
+ if fm.getSite().getConstName() != tm.getSite().getConstName():
+ return False
+
+ if fm.getWidth() != tm.getWidth():
+ return False
+ if fm.getHeight() != tm.getHeight():
+ return False
+
+ return True
+
+ def debug(self, msg):
+ if self.verbose:
+ print(msg, file=sys.stderr)
+
+ def error(self, msg):
+ print(msg, file=sys.stderr)
+
+ def net_source(self, net):
+ # See if it's an input pad
+ for bt in net.getBTerms():
+ if bt.getIoType() != "INPUT":
+ continue
+ good, x, y = bt.getFirstPinLocation()
+ if good:
+ return (x, y)
+
+ # Or maybe output of a cell
+ # x = odb.new_int(0)
+ # y = odb.new_int(0)
+
+ for it in net.getITerms():
+ if not it.isOutputSignal():
+ continue
+ found, x, y = it.getAvgXY()
+ if found:
+ return x, y
+
+ # Nothing found
+ return None
+
+ def net_from_pin(self, net, io_types=None):
+ for bt in net.getBTerms():
+ if (io_types is None) or (bt.getIoType() in io_types):
+ return True
+ return False
+
+ def net_has_diode(self, net):
+ for it in net.getITerms():
+ cell_type = it.getInst().getMaster().getConstName()
+ cell_pin = it.getMTerm().getConstName()
+ if (cell_type == self.diode_cell) and (cell_pin == self.diode_pin):
+ return True
+ else:
+ return False
+
+ def net_span(self, net):
+ xs = []
+ ys = []
+
+ for bt in net.getBTerms():
+ good, x, y = bt.getFirstPinLocation()
+ if good:
+ xs.append(x)
+ ys.append(y)
+
+ for it in net.getITerms():
+ x, y = self.pin_position(it)
+ xs.append(x)
+ ys.append(y)
+
+ if len(xs) == 0:
+ return 0
+
+ return (max(ys) - min(ys)) + (max(xs) - min(xs))
+
+ def pin_position(self, it):
+ # px = odb.new_int(0)
+ # py = odb.new_int(0)
+
+ found, px, py = it.getAvgXY()
+ if found:
+ # Got it
+ return px, py
+ else:
+ # Failed, use the center coordinate of the instance as fall back
+ return it.getInst().getLocation()
+
+ def place_diode_stdcell(self, it, px, py, src_pos=None):
+ # Get information about the instance
+ inst_name = it.getInst().getConstName()
+ inst_width = it.getInst().getMaster().getWidth()
+ inst_pos = it.getInst().getLocation()
+ inst_ori = it.getInst().getOrient()
+
+ # Is the pin left-ish, center-ish or right-ish ?
+ pos = None
+
+ if self.side_strategy == "source":
+ # Always be on the side of the source
+ if src_pos is not None:
+ pos = "l" if (src_pos[0] < inst_pos[0]) else "r"
+
+ elif self.side_strategy == "pin":
+ # Always be on the side of the pin
+ pos = "l" if (px < (inst_pos[0] + inst_width // 2)) else "r"
+
+ elif self.side_strategy == "balanced":
+ # If pin is really on the side, use that, else use source side
+ th_left = int(inst_pos[0] + inst_width * 0.25)
+ th_right = int(inst_pos[0] + inst_width * 0.75)
+
+ if px < th_left:
+ pos = "l"
+ elif px > th_right:
+ pos = "r"
+ elif src_pos is not None:
+ # Sort of middle, so put it on the side where signal is coming from
+ pos = "l" if (src_pos[0] < inst_pos[0]) else "r"
+
+ if pos is None:
+ # Coin toss ...
+ pos = "l" if (random.random() > 0.5) else "r"
+
+ # X position
+ dw = self.diode_master.getWidth()
+
+ if pos == "l":
+ dx = inst_pos[0] - dw * (1 + self.inserted.get((inst_name, "l"), 0))
+ else:
+ dx = inst_pos[0] + inst_width + dw * self.inserted.get((inst_name, "r"), 0)
+
+ # Record insertion
+ self.inserted[(inst_name, pos)] = self.inserted.get((inst_name, pos), 0) + 1
+
+ # Done
+ return dx, inst_pos[1], inst_ori
+
+ def place_diode_macro(self, it, px, py, src_pos=None):
+ # Scan all rows to see how close we can get to the point
+ best = None
+
+ for row in self.block.getRows():
+ rbb = row.getBBox()
+
+ dx = max(min(rbb.xMax(), px), rbb.xMin())
+ dy = rbb.yMin()
+ do = row.getOrient()
+
+ d = abs(px - dx) + abs(py - dy)
+
+ if (best is None) or (best[0] > d):
+ best = (d, dx, dy, do)
+
+ return best[1:]
+
+ def insert_diode(self, it, src_pos, force_true=False):
+ # Get information about the instance
+ inst = it.getInst()
+ inst_name = inst.getConstName()
+ inst_site = (
+ inst.getMaster().getSite().getConstName()
+ if (inst.getMaster().getSite() is not None)
+ else None
+ )
+
+ # Find where the pin is
+ px, py = self.pin_position(it)
+
+ # Apply standard cell or macro placement ?
+ if inst_site == self.diode_site:
+ dx, dy, do = self.place_diode_stdcell(it, px, py, src_pos)
+ else:
+ dx, dy, do = self.place_diode_macro(it, px, py, src_pos)
+
+ # Insert instance and wire it up
+ diode_inst_name = "ANTENNA_" + inst_name + "_" + it.getMTerm().getConstName()
+ diode_master = self.true_diode_master if force_true else self.diode_master
+
+ diode_inst = odb.dbInst_create(self.block, diode_master, diode_inst_name)
+
+ diode_inst.setOrient(do)
+ diode_inst.setLocation(dx, dy)
+ diode_inst.setPlacementStatus("PLACED")
+
+ ait = diode_inst.findITerm(self.diode_pin)
+ ait.connect(it.getNet())
+
+ def execute(self):
+ # Scan all nets
+ for net in self.block.getNets():
+ # Skip special nets
+ if net.isSpecial():
+ self.debug(f"[d] Skipping special net {net.getConstName():s}")
+ continue
+
+ # Check if we already have diode on the net
+ # if yes, then we assume that the user took care of that net manually
+ if self.net_has_diode(net):
+ self.debug(
+ f"[d] Skipping manually protected net {net.getConstName():s}"
+ )
+ continue
+
+ # Find signal source (first one found ...)
+ src_pos = self.net_source(net)
+
+ # Is this an IO we need to protect
+ io_protect = self.net_from_pin(net, io_types=self.port_protect)
+ if io_protect:
+ self.debug(
+ f"[d] Forcing protection diode on net {net.getConstName():s}"
+ )
+
+ # Determine the span of the signal and skip small internal nets
+ span = self.net_span(net)
+ if (span < self.short_span) and not io_protect:
+ self.debug(f"[d] Skipping small net {net.getConstName():s} ({span:d})")
+ continue
+
+ # Scan all internal terminals
+ for it in net.getITerms():
+ if it.isInputSignal():
+ self.insert_diode(it, src_pos, force_true=io_protect)
+
+
+# Arguments
+parser = argparse.ArgumentParser(description="Diode Insertion script")
+
+parser.add_argument(
+ "--lef",
+ "-l",
+ nargs="+",
+ type=str,
+ default=None,
+ required=True,
+ help="Input LEF file(s)",
+)
+
+parser.add_argument(
+ "--input-def",
+ "-id",
+ required=True,
+ help="DEF view of the design that needs to have diodes inserted",
+)
+
+parser.add_argument("--output-def", "-o", required=True, help="Output DEF file")
+
+parser.add_argument(
+ "--verbose",
+ "-v",
+ action="store_true",
+ default=False,
+ help="Enable verbose debug output",
+)
+
+parser.add_argument(
+ "--diode-cell",
+ "-c",
+ default="sky130_fd_sc_hd__diode_2",
+ help="Name of the cell to use as diode",
+)
+
+parser.add_argument(
+ "--fake-diode-cell", "-f", help="Name of the cell to use as fake diode"
+)
+
+parser.add_argument(
+ "--diode-pin", "-p", default="DIODE", help="Name of the pin to use on diode cells"
+)
+
+parser.add_argument(
+ "--side-strategy",
+ choices=["source", "pin", "balanced", "random"],
+ default="source",
+ help="Strategy to select if placing diode left/right of the cell",
+)
+
+parser.add_argument(
+ "--short-span",
+ "-s",
+ default=90000,
+ type=int,
+ help='Maximum span of a net to be considered "short" and not needing a diode',
+)
+
+parser.add_argument(
+ "--port-protect",
+ choices=["none", "in", "out", "both"],
+ default="in",
+ help="Always place a true diode on nets connected to selected ports",
+)
+
+
+args = parser.parse_args()
+input_lef_file_names = args.lef
+input_def_file_name = args.input_def
+output_def_file_name = args.output_def
+
+# Load
+db_design = odb.dbDatabase.create()
+
+for lef in input_lef_file_names:
+ odb.read_lef(db_design, lef)
+odb.read_def(db_design, input_def_file_name)
+
+chip_design = db_design.getChip()
+block_design = chip_design.getBlock()
+top_design_name = block_design.getConstName()
+print("Design name:", top_design_name)
+
+
+pp_val = {
+ "none": [],
+ "in": ["INPUT"],
+ "out": ["OUTPUT"],
+ "both": ["INPUT", "OUTPUT"],
+}
+
+di = DiodeInserter(
+ block_design,
+ diode_cell=args.diode_cell,
+ diode_pin=args.diode_pin,
+ fake_diode_cell=args.fake_diode_cell,
+ side_strategy=args.side_strategy,
+ short_span=args.short_span,
+ port_protect=pp_val[args.port_protect],
+ verbose=args.verbose,
+)
+di.execute()
+
+print("Inserted", len(di.inserted), "diodes.")
+
+# Write result
+odb.write_def(block_design, output_def_file_name)
diff --git a/openlane/scripts/power_route.py b/openlane/scripts/power_route.py
new file mode 100644
index 0000000..7d1be99
--- /dev/null
+++ b/openlane/scripts/power_route.py
@@ -0,0 +1,927 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+"""
+Takes a pre-routed top-level layout and creates the pg connections
+from the power/ground pads to the *core ring*
+"""
+
+import sys
+import argparse
+import odb
+
+parser = argparse.ArgumentParser(
+ description="Produces a DEF file with VDD and GND special nets\
+ where the power pads are connected to the core ring"
+)
+
+parser.add_argument(
+ "--input-def", "-d", required=True, help="DEF view of the design pre-routing"
+)
+
+parser.add_argument(
+ "--input-lef",
+ "-l",
+ required=True,
+ help="LEF file needed to have a proper view of the DEF",
+)
+
+parser.add_argument(
+ "--core-vdd-pin",
+ "-cvdd",
+ required=True,
+ help="Name of the power pin of core macro (exposed as its core ring)",
+)
+
+parser.add_argument(
+ "--core-gnd-pin",
+ "-cgnd",
+ required=True,
+ help="Name of the ground pin of core macro (exposed as its core ring)",
+)
+
+
+parser.add_argument(
+ "--output-def",
+ "-o",
+ required=True,
+ default="output.def",
+ help="Output power-routed DEF",
+)
+
+parser.add_argument(
+ "--vdd-pad-pin-map",
+ "-vmap",
+ action="append",
+ nargs=2,
+ required=False,
+ default=None,
+ help="Mappings to mark PAD-pin pairs as part of the VDD net. Defaults to sky130 settings.",
+)
+
+parser.add_argument(
+ "--gnd-pad-pin-map",
+ "-gmap",
+ action="append",
+ nargs=2,
+ required=False,
+ default=None,
+ help="Mappings to mark PAD-pin pairs as part of the GND net. Defaults to sky130 settings.",
+)
+
+
+args = parser.parse_args()
+
+def_file_name = args.input_def
+lef_file_name = args.input_lef
+output_def_file_name = args.output_def
+core_vdd_pin = args.core_vdd_pin
+core_gnd_pin = args.core_gnd_pin
+vdd_pad_pin_map = args.vdd_pad_pin_map
+gnd_pad_pin_map = args.gnd_pad_pin_map
+
+
+# TODO: expose through arguments
+ORIENT_LOC_MAP = {"R0": "N", "R90": "W", "R180": "S", "R270": "E"}
+
+# TODO: allow control
+VDD_NET_NAME = "VDD"
+GND_NET_NAME = "GND"
+
+# SKY130 DEFAULT
+SPECIAL_NETS = {
+ VDD_NET_NAME: {"core_pin": core_vdd_pin, "covered": False, "map": []},
+ GND_NET_NAME: {"core_pin": core_gnd_pin, "covered": False, "map": []},
+}
+
+if vdd_pad_pin_map is None:
+ vdd_pad_pin_map = [{"pad_pin": "vccd", "pad_name_substr": "vccd"}]
+else:
+ vdd_pad_pin_map = [
+ {"pad_pin": mapping[0], "pad_name_substr": mapping[1]}
+ for mapping in vdd_pad_pin_map
+ ]
+
+if gnd_pad_pin_map is None:
+ gnd_pad_pin_map = [
+ {"pad_pin": "vssd", "pad_name_substr": "vssd"},
+ {"pad_pin": "vssa", "pad_name_substr": "vssa"},
+ {"pad_pin": "vssio", "pad_name_substr": "vssio"},
+ ]
+else:
+ gnd_pad_pin_map = [
+ {"pad_pin": mapping[0], "pad_name_substr": mapping[1]}
+ for mapping in gnd_pad_pin_map
+ ]
+
+SPECIAL_NETS[VDD_NET_NAME]["map"] = vdd_pad_pin_map
+SPECIAL_NETS[GND_NET_NAME]["map"] = gnd_pad_pin_map
+
+
+##################
+
+db_top = odb.dbDatabase.create()
+odb.read_lef(db_top, lef_file_name)
+odb.read_def(db_top, def_file_name)
+
+chip_top = db_top.getChip()
+block_top = chip_top.getBlock()
+top_design_name = block_top.getName()
+tech = db_top.getTech()
+
+via_rules = tech.getViaGenerateRules()
+print("Found", len(via_rules), "VIA GENERATE rules")
+
+# build dictionary of basic custom vias (ROW = COL = 1)
+custom_vias = {}
+for rule in via_rules:
+ lower_rules = rule.getViaLayerRule(0)
+ upper_rules = rule.getViaLayerRule(1)
+ cut_rules = rule.getViaLayerRule(2)
+
+ lower_layer = lower_rules.getLayer()
+ upper_layer = upper_rules.getLayer()
+ cut_layer = cut_rules.getLayer()
+
+ if lower_layer.getName() in custom_vias:
+ print("Skipping", rule.getName())
+ continue
+
+ via_params = odb.dbViaParams()
+
+ via_params.setBottomLayer(lower_layer)
+ via_params.setTopLayer(upper_layer)
+ via_params.setCutLayer(cut_layer)
+
+ cut_rect = cut_rules.getRect()
+ via_params.setXCutSize(cut_rect.dx())
+ via_params.setYCutSize(cut_rect.dy())
+
+ cut_spacing = cut_rules.getSpacing()
+ via_params.setXCutSpacing(cut_spacing[0] - cut_rect.dx())
+ via_params.setYCutSpacing(cut_spacing[1] - cut_rect.dy())
+
+ lower_enclosure = lower_rules.getEnclosure()
+ upper_enclosure = upper_rules.getEnclosure()
+ if "M1M2" in rule.getName():
+ print(lower_enclosure)
+ via_params.setXBottomEnclosure(lower_enclosure[0])
+ via_params.setYBottomEnclosure(lower_enclosure[1])
+ via_params.setXTopEnclosure(upper_enclosure[0])
+ via_params.setYTopEnclosure(upper_enclosure[1])
+
+ custom_vias[lower_layer.getName()] = {}
+ custom_vias[lower_layer.getName()][upper_layer.getName()] = {
+ "rule": rule,
+ "params": via_params,
+ }
+ print("Added", rule.getName())
+
+
+def create_custom_via(layer1, layer2, width, height, reorient="R0"):
+ assert width > 0 and height > 0
+
+ if layer1.getRoutingLevel() < layer2.getRoutingLevel():
+ lower_layer_name = layer1.getName()
+ upper_layer_name = layer2.getName()
+ elif layer1.getRoutingLevel() > layer2.getRoutingLevel():
+ lower_layer_name = layer2.getName()
+ upper_layer_name = layer1.getName()
+ else:
+ raise Exception("Cannot create a custom via between two identical layers")
+
+ if reorient in ["R90", "R270"]:
+ width, height = height, width
+
+ via_name = "via_%s_%s_%dx%d" % (lower_layer_name, upper_layer_name, width, height)
+
+ custom_via = block_top.findVia(via_name)
+ if not custom_via:
+ print("Creating", via_name)
+
+ via_params = custom_vias[lower_layer_name][upper_layer_name]["params"]
+ via_rule = custom_vias[lower_layer_name][upper_layer_name]["rule"]
+
+ cut_width = via_params.getXCutSize()
+ cut_height = via_params.getYCutSize()
+ cut_spacing_x = via_params.getXCutSpacing()
+ cut_spacing_y = via_params.getXCutSpacing()
+ lower_enclosure_x = via_params.getXBottomEnclosure()
+ lower_enclosure_y = via_params.getYBottomEnclosure()
+ upper_enclosure_x = via_params.getXTopEnclosure()
+ upper_enclosure_y = via_params.getYTopEnclosure()
+
+ custom_via = odb.dbVia_create(block_top, via_name)
+ custom_via.setViaGenerateRule(via_rule)
+
+ array_width = width - 2 * max(lower_enclosure_x, upper_enclosure_x)
+ array_height = height - 2 * max(lower_enclosure_y, upper_enclosure_y)
+
+ # set ROWCOL
+ rows = 1 + (array_height - cut_height) // (cut_spacing_y + cut_height)
+ cols = 1 + (array_width - cut_width) // (cut_spacing_x + cut_width)
+ via_params.setNumCutRows(rows)
+ via_params.setNumCutCols(cols)
+
+ custom_via.setViaParams(via_params)
+
+ return custom_via
+
+
+def boxes2Rects(boxes, transform):
+ rects = []
+ for box in boxes:
+ ur = odb.Point(box.xMin(), box.yMin())
+ ll = odb.Point(box.xMax(), box.yMax())
+ transform.apply(ll)
+ transform.apply(ur)
+ pin_layer = box.getTechLayer()
+
+ rects.append({"layer": pin_layer, "rect": odb.Rect(ll, ur)})
+ return rects
+
+
+def getInstObs(inst):
+ master = inst.getMaster()
+ master_ox, master_oy = master.getOrigin()
+ inst_ox, inst_oy = inst.getOrigin()
+ px, py = master_ox + inst_ox, master_oy + inst_oy
+ orient = inst.getOrient()
+ transform = odb.dbTransform(orient, odb.Point(px, py))
+
+ obstructions = master.getObstructions()
+ rects = boxes2Rects(obstructions, transform)
+ for rect in rects:
+ rect["type"] = "obstruction"
+ return rects
+
+
+def getITermBoxes(iterm):
+ iterm_boxes = []
+ inst = iterm.getInst()
+ mterm = iterm.getMTerm()
+ master_ox, master_oy = inst.getMaster().getOrigin()
+ inst_ox, inst_oy = inst.getOrigin()
+ px, py = master_ox + inst_ox, master_oy + inst_oy
+ orient = inst.getOrient()
+ transform = odb.dbTransform(orient, odb.Point(px, py))
+ mpins = mterm.getMPins()
+ if len(mpins) > 1:
+ print(
+ "Warning:", len(mpins), "mpins for iterm", inst.getName(), mterm.getName()
+ )
+ for i in range(len(mpins)):
+ mpin = mpins[i]
+ boxes = mpin.getGeometry()
+ iterm_boxes += boxes2Rects(boxes, transform)
+
+ # filter duplications
+ # TODO: OpenDB bug? duplicate mpins for some reason
+ iterm_boxes_set = set()
+ iterm_boxes_uniq = []
+ for box in iterm_boxes:
+ rect = box["rect"]
+ llx, lly = rect.ll()
+ urx, ury = rect.ur()
+ set_item = (box["layer"].getName(), llx, lly, urx, ury)
+ if set_item not in iterm_boxes_set:
+ iterm_boxes_set.add(set_item)
+ iterm_boxes_uniq.append(box)
+
+ return iterm_boxes_uniq
+
+
+def getBiggestBoxAndIndex(boxes):
+ biggest_area = -1
+ biggest_box = None
+ biggest_i = -1
+ for i in range(len(boxes)):
+ box = boxes[i]
+ rect = box["rect"]
+ area = rect.area()
+ if area > biggest_area:
+ biggest_area = area
+ biggest_box = box
+ biggest_i = i
+
+ return biggest_box, biggest_i
+
+
+def rectOverlaps(rect1, rect2):
+ return not (
+ rect1.xMax() <= rect2.xMin()
+ or rect1.xMin() >= rect2.xMax()
+ or rect1.yMax() <= rect2.yMin()
+ or rect1.yMin() >= rect2.yMax()
+ )
+
+
+def rectMerge(rect1, rect2):
+ rect = odb.Rect(
+ min(rect1.xMin(), rect2.xMin()),
+ min(rect1.yMin(), rect2.yMin()),
+ max(rect1.xMax(), rect2.xMax()),
+ max(rect1.yMax(), rect2.yMax()),
+ )
+
+ return rect
+
+
+def getShapesOverlappingBBox(llx, lly, urx, ury, layers=[], ext_orient="R0"):
+ shapes_overlapping = []
+ rect_bbox = odb.Rect(llx, lly, urx, ury)
+
+ for box in ALL_BOXES:
+ box_layer = box["layer"]
+ ignore_box = len(layers) != 0
+ for layer in layers:
+ if equalLayers(layer, box_layer):
+ ignore_box = False
+ break
+ if not ignore_box:
+ rect_box = transformRect(box["rect"], ext_orient)
+ if rectOverlaps(rect_box, rect_bbox):
+ shapes_overlapping.append(box)
+
+ return shapes_overlapping
+
+
+def rectIntersection(rect1, rect2):
+ rect = odb.Rect()
+ if rectOverlaps(rect1, rect2):
+ rect.set_xlo(max(rect1.xMin(), rect2.xMin()))
+ rect.set_ylo(max(rect1.yMin(), rect2.yMin()))
+ rect.set_xhi(min(rect1.xMax(), rect2.xMax()))
+ rect.set_yhi(min(rect1.yMax(), rect2.yMax()))
+
+ return rect
+
+
+def manhattanDistance(x1, y1, x2, y2):
+ return odb.Point.manhattanDistance(odb.Point(x1, y1), odb.Point(x2, y2))
+
+
+def center(x1, y1, x2, y2):
+ return (x1 + x2) // 2, (y1 + y2) // 2
+
+
+def gridify(rect):
+ x1, y1 = rect.ll()
+ x2, y2 = rect.ur()
+ if (x2 - x1) % 2 != 0:
+ x1 += 5 # 0.005 microns !
+ return odb.Rect(x1, y1, x2, y2)
+
+
+def forward(point, orient, distance):
+ x, y = point.x(), point.y()
+ if orient == "R0":
+ point_forward = odb.Point(x, y - distance)
+ elif orient == "R90":
+ point_forward = odb.Point(x + distance, y)
+ elif orient == "R180":
+ point_forward = odb.Point(x, y + distance)
+ elif orient == "R270":
+ point_forward = odb.Point(x - distance, y)
+ else:
+ print("Unknown orientation")
+ sys.exit(1)
+ return point_forward
+
+
+def transformRect(rect, orient):
+ transform = odb.dbTransform(orient)
+ rect_ll = odb.Point(*rect.ll())
+ rect_ur = odb.Point(*rect.ur())
+ transform.apply(rect_ll)
+ transform.apply(rect_ur)
+ rect = odb.Rect(rect_ll, rect_ur)
+ return rect
+
+
+def isObstruction(box):
+ return box["type"] == "obstruction"
+
+
+def isCorePin(box):
+ return box["type"] == "core_pin"
+
+
+def isStripe(box):
+ return isCorePin(box) and box["stripe_flag"]
+
+
+def isPadPin(box):
+ return box["type"] == "pad_pin"
+
+
+def isHighestRoutingLayer(layer):
+ return layer.getRoutingLevel() == tech.getRoutingLayerCount()
+
+
+def isLowestRoutingLayer(layer):
+ return layer.getRoutingLevel() == 1
+
+
+def isRoutingLayer(layer):
+ return isinstance(layer, odb.dbTechLayer) and layer.getRoutingLevel() != 0
+
+
+def getUpperRoutingLayer(layer):
+ if not isRoutingLayer(layer):
+ raise Exception("Attempting to get upper routing layer of a non-routing layer")
+
+ if isHighestRoutingLayer(layer):
+ raise Exception(
+ "Attempting to get upper routing layer of the highest routing layer"
+ )
+
+ return layer.getUpperLayer().getUpperLayer()
+
+
+def getLowerRoutingLayer(layer):
+ if not isRoutingLayer(layer):
+ raise Exception("Attempting to get lower routing layer of a non-routing layer")
+
+ if isLowestRoutingLayer(layer):
+ raise Exception(
+ "Attempting to get lower routing layer of the lowest routing layer"
+ )
+
+ return layer.getLowerLayer().getLowerLayer()
+
+
+def equalLayers(layer1, layer2):
+ return layer1.getName() == layer2.getName()
+
+
+def layersBetween(layer1, layer2):
+ # Inclusive
+ layers_between = [layer1]
+
+ if not equalLayers(layer1, layer2):
+ if layer1.getRoutingLevel() < layer2.getRoutingLevel():
+ layer1 = getUpperRoutingLayer(layer1)
+ while not equalLayers(layer1, layer2):
+ layers_between.append(layer1)
+ layer1 = getUpperRoutingLayer(layer1)
+ else:
+ layer1 = getLowerRoutingLayer(layer1)
+ while not equalLayers(layer1, layer2):
+ layers_between.append(layer1)
+ layer1 = getLowerRoutingLayer(layer1)
+ layers_between.append(layer2)
+
+ return layers_between
+
+
+def createWireBox(rect_width, rect_height, rect_x, rect_y, layer, net, reorient="R0"):
+ rect = odb.Rect(0, 0, rect_width, rect_height)
+ rect.moveTo(rect_x, rect_y)
+ rect = transformRect(rect, reorient)
+
+ box = {"rect": rect, "layer": layer, "net": net}
+
+ return box
+
+
+def getTechMaxSpacing(layers=tech.getLayers()):
+ max_spacing = -1
+ for layer in layers:
+ max_spacing = max(max_spacing, layer.getSpacing())
+ # print("Max spacing for", layers, "is", max_spacing)
+ return max_spacing
+
+
+print("Top-level design name:", top_design_name)
+
+# create special nets
+for special_net_name in SPECIAL_NETS:
+ net = odb.dbNet_create(block_top, special_net_name)
+ net.setSpecial()
+ net.setWildConnected()
+
+ wire = odb.dbSWire_create(net, "ROUTED")
+
+ SPECIAL_NETS[special_net_name]["net"] = net
+ SPECIAL_NETS[special_net_name]["wire"] = wire
+
+ALL_BOXES = []
+
+# disconnect all iterms from anywhere else !!! (is this even needed?)
+for inst in block_top.getInsts():
+ iterms = inst.getITerms()
+ ALL_BOXES += getInstObs(inst)
+ for iterm in iterms:
+ master_name = inst.getMaster().getName()
+ pin_name = iterm.getMTerm().getName()
+ matched_special_net_name = None
+ for special_net_name in SPECIAL_NETS:
+ net = SPECIAL_NETS[special_net_name]["net"]
+
+ for mapping in SPECIAL_NETS[special_net_name]["map"]:
+ core_pin = SPECIAL_NETS[special_net_name]["core_pin"]
+ pad_pin = mapping["pad_pin"]
+ pad_name_substr = mapping["pad_name_substr"]
+
+ if pin_name == pad_pin and pad_name_substr in master_name: # pad pin
+ matched_special_net_name = special_net_name
+ print(inst.getName(), "connected to", net.getName())
+ # iterm.connect(net)
+ # iterm.setSpecial()
+
+ # get the pin shapes
+ iterm_boxes = getITermBoxes(iterm)
+ pad_orient = iterm.getInst().getOrient()
+ for box in iterm_boxes:
+ box["net"] = special_net_name
+ box["type"] = "pad_pin"
+ box["orient"] = pad_orient
+ ALL_BOXES += iterm_boxes
+ elif pin_name == core_pin: # macro ring
+ matched_special_net_name = special_net_name
+ print(
+ inst.getName(),
+ "will be connected to",
+ master_name,
+ "/",
+ pin_name,
+ )
+ # iterm.connect(net)
+ # iterm.setSpecial()
+
+ iterm_boxes = getITermBoxes(iterm)
+ for box in iterm_boxes:
+ box["net"] = special_net_name
+ box["type"] = "core_pin"
+ box["stripe_flag"] = False
+
+ h_stripes = []
+ v_stripes = []
+ for i in range(4): # ASSUMPTION: 4 CORE RING-STRIPES
+ biggest_pin_box, biggest_pin_box_i = getBiggestBoxAndIndex(
+ iterm_boxes
+ )
+ if biggest_pin_box is None:
+ continue
+
+ del iterm_boxes[biggest_pin_box_i]
+
+ biggest_pin_box["stripe_flag"] = True
+
+ rect = biggest_pin_box["rect"]
+ if rect.dx() > rect.dy(): # horizontal stripe
+ biggest_pin_box["orient"] = "R90"
+ h_stripes.append(biggest_pin_box)
+ else:
+ biggest_pin_box["orient"] = "R0"
+ v_stripes.append(biggest_pin_box)
+
+ if len(h_stripes) >= 2:
+ if h_stripes[0]["rect"].yMin() < h_stripes[1]["rect"].yMin():
+ h_stripes[0]["side"] = "S"
+ h_stripes[1]["side"] = "N"
+ else:
+ h_stripes[0]["side"] = "N"
+ h_stripes[1]["side"] = "S"
+ elif len(h_stripes) == 1:
+ print("Warning: only one horizontal stripe found for", core_pin)
+ if (
+ block_top.getBBox().yMax() - h_stripes[0]["rect"].yMin()
+ > block_top.getBBox().yMin() - h_stripes[0]["rect"].yMin()
+ ):
+ h_stripes[0]["side"] = "S"
+ else:
+ h_stripes[0]["side"] = "N"
+ else:
+ print("Warning: No horizontal stripes in the design!")
+
+ if len(v_stripes) >= 2:
+ if v_stripes[0]["rect"].xMin() < v_stripes[1]["rect"].xMin():
+ v_stripes[0]["side"] = "W"
+ v_stripes[1]["side"] = "E"
+ else:
+ v_stripes[0]["side"] = "E"
+ v_stripes[1]["side"] = "W"
+ elif len(v_stripes) == 1:
+ print("Warning: only one vertical stripe found for", core_pin)
+ if (
+ block_top.getBBox().xMax() - v_stripes[0]["rect"].xMin()
+ > block_top.getBBox().xMin() - v_stripes[0]["rect"].xMin()
+ ):
+ v_stripes[0]["side"] = "W"
+ else:
+ v_stripes[0]["side"] = "E"
+ else:
+ print("Warning: No vertical stripes in the design!")
+
+ ALL_BOXES += iterm_boxes + v_stripes + h_stripes
+ if (
+ matched_special_net_name is None
+ ): # other pins are obstructions for our purposes
+ new_obstructions = getITermBoxes(iterm)
+ for obs in new_obstructions:
+ obs["type"] = "obstruction"
+ ALL_BOXES += new_obstructions
+
+# only types are: obstruction, core_pin, pad_pin
+assert len({box["type"]: None for box in ALL_BOXES}) == 3
+
+wire_boxes = []
+
+PAD_PINS = [box for box in ALL_BOXES if isPadPin(box)]
+CORE_STRIPES = [box for box in ALL_BOXES if isStripe(box)]
+
+# Go over power pad pins, find the nearest ring-stripe,
+# check how to connect to it
+connections_count = 0
+for box in PAD_PINS:
+ pad_pin_orient = box["orient"]
+ pad_pin_layer = box["layer"]
+ pad_pin_rect = box["rect"]
+
+ ##
+ # if connections_count > 29:
+ # pprint(wire_boxes)
+ # break
+ ##
+
+ nearest_stripe_box = None
+ for stripe in CORE_STRIPES:
+ if (
+ box["net"] == stripe["net"]
+ and stripe["side"] == ORIENT_LOC_MAP[pad_pin_orient]
+ ):
+ nearest_stripe_box = stripe
+
+ if nearest_stripe_box is None:
+ print(
+ "Pad pin at",
+ box["rect"].ll(),
+ box["rect"].ur(),
+ "doesn't have a facing stripe. Skipping.",
+ )
+ continue
+
+ stripe_rect = nearest_stripe_box["rect"]
+
+ # TRANSFORM TO R0 ORIENTATION
+ pad_pin_orient_inv = "R" + str((360 - int(pad_pin_orient[1:])) % 360)
+ assert pad_pin_orient_inv in ORIENT_LOC_MAP
+
+ pad_pin_rect = transformRect(pad_pin_rect, pad_pin_orient_inv)
+ stripe_rect = transformRect(stripe_rect, pad_pin_orient_inv)
+
+ pad_pin_width = pad_pin_rect.dx()
+
+ projection_x_min, projection_x_max = max(
+ pad_pin_rect.xMin(), stripe_rect.xMin()
+ ), min(stripe_rect.xMax(), pad_pin_rect.xMax())
+
+ MIN_WIDTH = 5000
+ if projection_x_max - projection_x_min < MIN_WIDTH:
+ continue
+
+ # account for obstructions
+
+ from_layer = box["layer"]
+ to_layer = nearest_stripe_box["layer"]
+
+ # prefer the highest possible connecting layer (antenna reasons)
+ connecting_layer = from_layer
+ if not isHighestRoutingLayer(to_layer):
+ connecting_layer = getUpperRoutingLayer(to_layer)
+ elif not isLowestRoutingLayer(to_layer):
+ connecting_layer = getLowerRoutingLayer(to_layer)
+
+ print("Connecting with", connecting_layer.getName(), "to", to_layer.getName())
+
+ wire_rect = odb.Rect(
+ projection_x_min, pad_pin_rect.yMin(), projection_x_max, stripe_rect.yMin()
+ )
+
+ # adjust width
+ MAX_SPACING = getTechMaxSpacing(
+ (
+ set(layersBetween(from_layer, connecting_layer)).union(
+ layersBetween(connecting_layer, to_layer)
+ )
+ )
+ )
+ # note that the box is move away from the pad to evade interactions with
+ # nearby pads
+ overlapping_boxes = getShapesOverlappingBBox(
+ wire_rect.xMin() - MAX_SPACING,
+ wire_rect.yMin(),
+ wire_rect.xMax() + MAX_SPACING,
+ wire_rect.yMax() - MAX_SPACING,
+ ext_orient=pad_pin_orient_inv,
+ layers=list(set(layersBetween(connecting_layer, to_layer)) - set([to_layer])),
+ )
+
+ # find the new possible wire_rect width after subtracting the obstructions
+ skip = False
+ obs_boundaries = []
+ for ov_box in overlapping_boxes:
+ obs_rect = transformRect(ov_box["rect"], pad_pin_orient_inv)
+ # if it is completely contained in an obstruction
+
+ if obs_rect.xMin() <= wire_rect.xMin() < wire_rect.xMax() <= obs_rect.xMax():
+ skip = True
+ break
+
+ if (
+ wire_rect.xMin() - MAX_SPACING
+ <= obs_rect.xMin()
+ <= wire_rect.xMax() + MAX_SPACING
+ ):
+ obs_boundaries.append(obs_rect.xMin())
+
+ if (
+ wire_rect.xMin() - MAX_SPACING
+ <= obs_rect.xMax()
+ <= wire_rect.xMax() + MAX_SPACING
+ ):
+ obs_boundaries.append(obs_rect.xMax())
+
+ obs_boundaries.sort()
+
+ if len(obs_boundaries) > 0:
+ obs_min_x = obs_boundaries[0]
+ obs_max_x = obs_boundaries[-1]
+
+ print("Adjusting", wire_rect.ll(), wire_rect.ur())
+ print(obs_max_x - obs_min_x)
+ print(obs_min_x, obs_max_x)
+ if (
+ obs_min_x - (wire_rect.xMin() - MAX_SPACING)
+ > (wire_rect.xMax() + MAX_SPACING) - obs_max_x
+ ):
+ wire_rect.set_xhi(obs_min_x - MAX_SPACING)
+ else:
+ wire_rect.set_xlo(obs_max_x + MAX_SPACING)
+ print("To", wire_rect.ll(), wire_rect.ur())
+
+ # leave some space for routing
+ from_layer_space = 2 * from_layer.getSpacing() + from_layer.getWidth()
+ wire_width = wire_rect.dx() - from_layer_space
+ wire_x = wire_rect.xMin() + from_layer_space
+ wire_y = wire_rect.yMax()
+
+ if wire_width < MIN_WIDTH:
+ skip = True
+
+ if skip:
+ continue
+
+ basic_rect = rectIntersection(wire_rect, stripe_rect)
+
+ # 1. extend outside by half of the size of the "basic rectangle"
+ wire_y -= basic_rect.dy() // 2
+ wire_boxes.append(
+ createWireBox(
+ wire_width,
+ basic_rect.dy() // 2,
+ wire_x,
+ wire_y,
+ from_layer,
+ box["net"],
+ reorient=pad_pin_orient,
+ )
+ )
+
+ # 2. vias up till the connecting_layer on the next basic rect
+ wire_y -= basic_rect.dy()
+ prev_layer = None
+ for layer in layersBetween(from_layer, connecting_layer):
+ if prev_layer is not None:
+ via = create_custom_via(
+ prev_layer, layer, wire_width, basic_rect.dy(), reorient=pad_pin_orient
+ )
+
+ wire_boxes.append(
+ createWireBox(
+ wire_width,
+ basic_rect.dy(),
+ wire_x,
+ wire_y,
+ via,
+ box["net"],
+ reorient=pad_pin_orient,
+ )
+ )
+
+ wire_boxes.append(
+ createWireBox(
+ wire_width,
+ basic_rect.dy(),
+ wire_x,
+ wire_y,
+ layer,
+ box["net"],
+ reorient=pad_pin_orient,
+ )
+ )
+ prev_layer = layer
+
+ # 3. use the connecting layer to connect to the stripe
+ wire_height = wire_y - wire_rect.yMin()
+ wire_y = wire_rect.yMin()
+ wire_boxes.append(
+ createWireBox(
+ wire_width,
+ wire_height,
+ wire_x,
+ wire_y,
+ connecting_layer,
+ box["net"],
+ reorient=pad_pin_orient,
+ )
+ )
+
+ # 4. vias down from the connecting_layer to the to_layer (stripe layer)
+ prev_layer = None
+ for layer in layersBetween(connecting_layer, to_layer):
+ if prev_layer is not None:
+ via = create_custom_via(
+ prev_layer, layer, wire_width, basic_rect.dy(), reorient=pad_pin_orient
+ )
+
+ wire_boxes.append(
+ createWireBox(
+ wire_width,
+ basic_rect.dy(),
+ wire_x,
+ wire_y,
+ via,
+ box["net"],
+ reorient=pad_pin_orient,
+ )
+ )
+ wire_boxes.append(
+ createWireBox(
+ wire_width,
+ basic_rect.dy(),
+ wire_x,
+ wire_y,
+ layer,
+ box["net"],
+ reorient=pad_pin_orient,
+ )
+ )
+ prev_layer = layer
+ connections_count += 1
+
+# ROUTING
+print("creating", len(wire_boxes), "wires")
+for box in wire_boxes:
+ net_name = box["net"]
+ print(net_name, ": drawing a special wire on layer", box["layer"].getName())
+ rect = gridify(box["rect"])
+ if isRoutingLayer(box["layer"]):
+ odb.dbSBox_create(
+ SPECIAL_NETS[net_name]["wire"],
+ box["layer"],
+ *rect.ll(),
+ *rect.ur(),
+ "COREWIRE",
+ odb.dbSBox.UNDEFINED
+ )
+ else:
+ odb.dbSBox_create(
+ SPECIAL_NETS[net_name]["wire"],
+ box["layer"],
+ (rect.xMin() + rect.xMax()) // 2,
+ (rect.yMin() + rect.yMax()) // 2,
+ "COREWIRE",
+ )
+
+ SPECIAL_NETS[net_name]["covered"] = True
+
+uncovered_nets = [
+ net_name for net_name in SPECIAL_NETS if not SPECIAL_NETS[net_name]["covered"]
+]
+if len(uncovered_nets) > 0:
+ print("No routes created on the following nets:")
+ print(uncovered_nets)
+ print("Make sure the pads to be connected are facing the core rings")
+ sys.exit(1)
+
+
+# OUTPUT
+odb.write_def(block_top, output_def_file_name)
+
+odb.write_lef(odb.dbLib_getLib(db_top, 1), output_def_file_name + ".lef")
+
+print("Done")
diff --git a/openlane/scripts/random_place.py b/openlane/scripts/random_place.py
new file mode 100644
index 0000000..3b0103a
--- /dev/null
+++ b/openlane/scripts/random_place.py
@@ -0,0 +1,91 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import random
+import odb
+
+parser = argparse.ArgumentParser(
+ description="Places instances in random locations in layout. Intended for cases, where using a placer would be an overkill (very small number of instances < ~40)"
+)
+
+parser.add_argument(
+ "--lef",
+ "-l",
+ nargs="+",
+ type=str,
+ default=None,
+ required=True,
+ help="Input LEF file(s)",
+)
+
+parser.add_argument(
+ "--input-def",
+ "-id",
+ required=True,
+ help="DEF view of the design that needs to have its instances placed",
+)
+
+parser.add_argument("--output-def", "-o", required=True, help="Output placed DEF file")
+
+args = parser.parse_args()
+
+input_lef_file_names = args.lef
+input_def_file_name = args.input_def
+output_def_file_name = args.output_def
+
+
+def gridify(n, f):
+ """
+ e.g., (1.1243, 0.005) -> 1.120
+ """
+ return round(n / f) * f
+
+
+db_design = odb.dbDatabase.create()
+
+for lef in input_lef_file_names:
+ odb.read_lef(db_design, lef)
+odb.read_def(db_design, input_def_file_name)
+
+chip_design = db_design.getChip()
+block_design = chip_design.getBlock()
+top_design_name = block_design.getName()
+core_area = block_design.getCoreArea()
+LLX, LLY = core_area.ll()
+URX, URY = core_area.ur()
+insts = block_design.getInsts()
+
+print("Design name:", top_design_name)
+print("Core Area Boundaries:", LLX, LLY, URX, URY)
+print("Number of instances", len(insts))
+
+placed_cnt = 0
+for inst in insts:
+ if inst.isFixed():
+ continue
+ master = inst.getMaster()
+ master_width = master.getWidth()
+ master_height = master.getHeight()
+ x = gridify(random.randint(LLX, max(LLX, URX - master_width)), 5)
+ y = gridify(random.randint(LLY, max(LLY, URY - master_height)), 5)
+ inst.setLocation(x, y)
+ inst.setPlacementStatus("PLACED")
+
+ placed_cnt += 1
+
+print("Placed", placed_cnt, "instances")
+
+odb.write_def(block_design, output_def_file_name)
diff --git a/openlane/scripts/rectify.py b/openlane/scripts/rectify.py
new file mode 100755
index 0000000..bad7ce5
--- /dev/null
+++ b/openlane/scripts/rectify.py
@@ -0,0 +1,148 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+takes a lef file and a rectangle => trims all RECT statements within the area
+"""
+import re
+import sys
+
+ARGV = sys.argv
+if len(ARGV) < 5:
+ print("Usage " + ARGV[0] + " llx lly urx ury")
+ sys.exit(-1)
+LLX = float(ARGV[1])
+LLY = float(ARGV[2])
+URX = float(ARGV[3])
+URY = float(ARGV[4])
+LAYERS = ["li1", "met1", "met2", "met3", "met4", "met5"]
+RECT_REGEX = (
+ r"^\s*RECT\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+;$"
+)
+# SIZE_REGEX = r"^\s*SIZE\s+(-?\d+\.?\d*)\s+BY\s+\s+(-?\d+\.?\d*);$"
+
+
+def get_cut_rect_x(rect, axis):
+ """
+ cuts one rect about an x axis
+ """
+ rects = [rect]
+ llx, lly, urx, ury = rect
+ if llx < axis and urx > axis:
+ rects = [(llx, lly, axis, ury), (axis, lly, urx, ury)]
+ return rects
+
+
+def get_cut_rect_y(rect, axis):
+ """
+ cuts one rect about an y axis
+ """
+ rects = [rect]
+ llx, lly, urx, ury = rect
+ if lly < axis and ury > axis:
+ rects = [(llx, lly, urx, axis), (llx, axis, urx, ury)]
+ return rects
+
+
+def rects2cutrects(rects, axis, direction):
+ """
+ cut a list of rects (4-tuple) and returns another list of of rects (4-tuple)
+ cut by an x or y axis
+
+ axix is a position
+
+ direction is either 'x' or 'y'
+ """
+ rects_cut = []
+ if direction == "x":
+ for rect in rects:
+ rects_cut += get_cut_rect_x(rect, axis)
+ else:
+ for rect in rects:
+ rects_cut += get_cut_rect_y(rect, axis)
+ return rects_cut
+
+
+def get_all_cut_rects(rect):
+ """
+ cut a rect about the 4 axis LLX, LLY, URX, URY
+ """
+ rects = [rect]
+ rects = rects2cutrects(rects, LLX, "x")
+ rects = rects2cutrects(rects, URX, "x")
+ rects = rects2cutrects(rects, LLY, "y")
+ rects = rects2cutrects(rects, URY, "y")
+ return rects
+
+
+def rectify(rects):
+ """
+ gets a list of already cut rects (4-tuple) and returns another list of of
+ rects (4-tuple) that are not within LLX, LLY, URX, URY
+ """
+ rect_outside = []
+ for rect in rects:
+ llx, lly, urx, ury = rect
+ if (
+ llx < LLX
+ or llx > URX
+ or urx > URX
+ or urx < LLX
+ or lly < LLY
+ or lly > URY
+ or ury > URY
+ or ury < LLY
+ ):
+ rect_outside += [rect]
+ return rect_outside
+
+
+def print_rects(prefix, rects):
+ for rect in rects:
+ llx, lly, urx, ury = rect
+ print(prefix + "RECT %f %f %f %f ;" % (llx, lly, urx, ury))
+
+
+layer = ""
+for line in sys.stdin:
+ if line.isspace():
+ continue
+ rect_match = re.search(RECT_REGEX, line)
+ if rect_match:
+ llx, lly, urx, ury = (
+ float(rect_match.group(1)),
+ float(rect_match.group(2)),
+ float(rect_match.group(3)),
+ float(rect_match.group(4)),
+ )
+ if (
+ (lly < LLY and ury < LLY)
+ or (lly > URY and ury > URY)
+ or (llx < LLX and urx < LLX)
+ or (llx > URX and urx > URX)
+ ): # outside the whole thing
+ rects = [(llx, lly, urx, ury)]
+ else:
+ rects = rectify(get_all_cut_rects((llx, lly, urx, ury)))
+ if len(rects) > 0:
+ print(layer)
+ if layer != "": # LAYER printed, clear it
+ layer = ""
+ print_rects(line[: line.find("R")], rects)
+ else:
+ if line.find("LAYER") != -1: # print it only if there're RECTs
+ layer = line
+ else:
+ print(line, end="")
diff --git a/openlane/scripts/reorg_reports.sh b/openlane/scripts/reorg_reports.sh
new file mode 100644
index 0000000..2a84ad8
--- /dev/null
+++ b/openlane/scripts/reorg_reports.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+# Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+# Handle generated timing reports
+mkdir -p $RUN_DIR/reports/routing/eco_$ECO_ITER
+rsync -vt $RUN_DIR/reports/routing/* \
+ $RUN_DIR/reports/routing/eco_$ECO_ITER
+find $RUN_DIR/reports/routing -maxdepth 1 -type f -delete
+
+# if [ $ECO_ITER -ne 0 ]; then
+# mv $RUN_DIR/results/routing/*.def
+# fi
diff --git a/openlane/scripts/reorg_results.sh b/openlane/scripts/reorg_results.sh
new file mode 100644
index 0000000..9d752bc
--- /dev/null
+++ b/openlane/scripts/reorg_results.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+# Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Handle generated spefs/defs
+mkdir -p $RUN_DIR/results/eco/def
+mkdir -p $RUN_DIR/results/eco/spef
+mkdir -p $RUN_DIR/results/eco/sdf
+
+# Breakpoint to see if dirs are generated
+# exit 111
+# rsync -av $RUN_DIR/results/routing/*.def \
+# $RUN_DIR/results/routing/eco_$ECO_ITER/def
+# rsync -av $RUN_DIR/results/routing/*.spef \
+# $RUN_DIR/results/routing/eco_$ECO_ITER/spef
+# rsync -av $RUN_DIR/results/routing/*.sdf \
+# $RUN_DIR/results/routing/eco_$ECO_ITER/sdf
+
diff --git a/openlane/scripts/replace_prefix_from_def_instances.py b/openlane/scripts/replace_prefix_from_def_instances.py
new file mode 100644
index 0000000..a22a6c3
--- /dev/null
+++ b/openlane/scripts/replace_prefix_from_def_instances.py
@@ -0,0 +1,62 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import re
+import argparse
+
+
+parser = argparse.ArgumentParser(
+ description="Replaces a given prefix from instances in DEF COMPONENTS with another."
+)
+
+parser.add_argument("--def_file", "-d", required=True, help="Input DEF")
+
+parser.add_argument(
+ "--original_prefix", "-op", required=True, help="The original prefix"
+)
+parser.add_argument("--new_prefix", "-np", required=True, help="The new prefix")
+
+
+args = parser.parse_args()
+
+def_file = args.def_file
+
+original_prefix = args.original_prefix
+new_prefix = args.new_prefix
+
+
+tmpFile = open(def_file, "r")
+if tmpFile.mode == "r":
+ defContent = tmpFile.read()
+tmpFile.close()
+
+exitFlag = False
+for line in defContent.split("\n"):
+ if line.find("COMPONENTS") != -1:
+ if exitFlag:
+ break
+ else:
+ exitFlag = True
+ continue
+
+ if exitFlag:
+ cell = re.findall(r"- " + original_prefix + r"_(\d+) ", line)
+ if len(cell) == 1:
+ old = " " + original_prefix + "_" + cell[0] + " "
+ new = " " + new_prefix + "_" + cell[0] + " "
+ defContent = defContent.replace(old, new)
+
+tmpFile = open(def_file, "w")
+tmpFile.write(defContent)
+tmpFile.close()
diff --git a/openlane/scripts/replicate_design_configs.py b/openlane/scripts/replicate_design_configs.py
new file mode 100644
index 0000000..b4f46b6
--- /dev/null
+++ b/openlane/scripts/replicate_design_configs.py
@@ -0,0 +1,113 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+import argparse
+import os
+from os import path
+import utils.utils as utils
+
+parser = argparse.ArgumentParser(
+ description="replicate configurations of design(s) from a given (PDK, STD_CELL_LIB) to another, or generates an empty config file for a given (PDK, STD_CELL_LIB)"
+)
+
+
+parser.add_argument(
+ "--from-pdk", "-fp", action="store", help="The name of the PDK to copy from"
+)
+
+parser.add_argument(
+ "--from-std-cell-library",
+ "-fscl",
+ action="store",
+ help="The name of the STD_CELL_LIBRARY to copy from",
+)
+
+parser.add_argument(
+ "--to-pdk",
+ "-tp",
+ action="store",
+ required=True,
+ help="The name of the PDK to copy to",
+)
+
+parser.add_argument(
+ "--to-std-cell-library",
+ "-tscl",
+ action="store",
+ required=True,
+ help="The name of the STD_CELL_LIBRARY to copy to",
+)
+
+parser.add_argument(
+ "--designs",
+ "-d",
+ nargs="+",
+ default=[],
+ help="designs to update. Same as -d in run desings. If none provided, then all designs under ./designs will be replicated",
+)
+
+
+args = parser.parse_args()
+pdkFrom = args.from_pdk
+from_std_cell_library = args.from_std_cell_library
+pdkTo = args.to_pdk
+to_std_cell_library = args.to_std_cell_library
+
+designs = list(dict.fromkeys(args.designs))
+
+if pdkFrom is None:
+ pdkFrom = "ThisFileDoesntExist"
+
+if from_std_cell_library is None:
+ from_std_cell_library = "ThisFileDoesntExist"
+
+
+if len(designs) == 0:
+ designs = [x for x in os.listdir("./designs/")]
+ for i in designs:
+ if not os.path.isdir("./designs/" + i):
+ designs.remove(i)
+
+for design in designs:
+ print("Replicating " + design + " config...")
+ base_path = utils.get_design_path(design=design)
+ configFileTo = (
+ str(base_path)
+ + "/"
+ + str(pdkTo)
+ + "_"
+ + str(to_std_cell_library)
+ + "_config.tcl"
+ )
+ configFileFrom = (
+ str(base_path)
+ + "/"
+ + str(pdkFrom)
+ + "_"
+ + str(from_std_cell_library)
+ + "_config.tcl"
+ )
+ if path.exists(configFileFrom):
+ configFileFromOpener = open(configFileFrom, "r")
+ configFileFromData = configFileFromOpener.read()
+ configFileFromOpener.close()
+
+ configFileToOpener = open(configFileTo, "w+")
+ configFileToOpener.write(configFileFromData)
+ configFileToOpener.close()
+ else:
+ configFileToOpener = open(configFileTo, "w+")
+ configFileToOpener.write("#init Configs")
+ configFileToOpener.close()
diff --git a/openlane/scripts/report/get_best.py b/openlane/scripts/report/get_best.py
new file mode 100755
index 0000000..6063bb0
--- /dev/null
+++ b/openlane/scripts/report/get_best.py
@@ -0,0 +1,244 @@
+#!/usr/bin/python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+from operator import itemgetter
+
+
+parser = argparse.ArgumentParser(
+ description="Selects top configuration from a report file and produces a new report file containing the top configurations only for each design"
+)
+
+parser.add_argument("--input", "-i", required=True, help="input report file")
+parser.add_argument(
+ "--output", "-o", required=True, help="output report file with top configuration"
+)
+
+args = parser.parse_args()
+report_file = args.input
+output_file = args.output
+
+tr_violations_idx = 0
+lvs_errors_idx = 0
+magic_violations_idx = 0
+antenna_violations_idx = 0
+wire_length_idx = 0
+via_idx = 0
+flow_status_idx = 0
+design_idx = 0
+
+
+def get_header(report_file):
+ f = open(report_file, "r")
+ header = f.readline()
+ return header
+
+
+def build_dictionary(report_file):
+ with open(report_file, "r") as f:
+ lines = list(filter(None, (line.rstrip() for line in f)))
+ header = lines[0]
+ lines = lines[1:]
+ lines = [line.split(",") for line in lines]
+
+ dictionary = {}
+ for config in lines:
+ if len(config) < len(header.split(",")):
+ continue
+
+ key = config[design_idx]
+ if key in dictionary:
+ dictionary[key].append(config[design_idx + 1 :])
+ else:
+ dictionary[key] = [config[design_idx + 1 :]]
+
+ return dictionary
+
+
+def convert_vio_to_int(val):
+ val = int(val)
+ if val < 0:
+ val = 2**31 # Explode
+ return val
+
+
+def convert_vio_to_string(val):
+ if val == 2**31:
+ val = -1
+ return str(val)
+
+
+def convert_vios_to_int(results_vector):
+ # change violations to int
+ for i in range(len(results_vector)):
+ row = results_vector[i]
+ row[tr_violations_idx] = convert_vio_to_int(row[tr_violations_idx])
+ row[lvs_errors_idx] = convert_vio_to_int(row[lvs_errors_idx])
+ row[magic_violations_idx] = convert_vio_to_int(row[magic_violations_idx])
+ row[antenna_violations_idx] = convert_vio_to_int(row[antenna_violations_idx])
+ results_vector[i] = row
+ return results_vector
+
+
+def filter_by_tr_vios(results_vector):
+ # Get a close subset by TR vios
+ sorted_violations = sorted(results_vector, key=itemgetter(tr_violations_idx))
+ best_violation = int(sorted_violations[0][tr_violations_idx])
+
+ close_subset = [sorted_violations[0]]
+ for result in sorted_violations[1:]:
+ violation = int(result[tr_violations_idx])
+ if (abs(violation - best_violation) < 5) and best_violation != 0:
+ close_subset.append(result)
+ elif violation == 0:
+ close_subset.append(result)
+ return close_subset
+
+
+def filter_by_lvs_errors(results_vector):
+ # Get a close subset by LVS errors
+ # The philosiphy here is if one run is LVS clean, then don't accept anything that
+ # is not LVS clean. Otherwise, don't trust the reported result by netgen and pass
+ # everything as is to the next filter.
+ sorted_violations = sorted(results_vector, key=itemgetter(lvs_errors_idx))
+ best_violation = int(sorted_violations[0][lvs_errors_idx])
+
+ if best_violation == 0:
+ close_subset = [sorted_violations[0]]
+ for result in sorted_violations[1:]:
+ violation = int(result[lvs_errors_idx])
+ if violation == 0:
+ close_subset.append(result)
+ return close_subset
+ else:
+ return results_vector
+
+
+def filter_by_magic_vios(results_vector):
+ # Get a close subset by magic drc vios
+ sorted_violations = sorted(results_vector, key=itemgetter(magic_violations_idx))
+ best_violation = int(sorted_violations[0][magic_violations_idx])
+
+ close_subset = [sorted_violations[0]]
+ for result in sorted_violations[1:]:
+ violation = int(result[magic_violations_idx])
+ # Allow for 100 vios tolerance (given the history of magic drc(full))
+ if (abs(violation - best_violation) < 100) and best_violation != 0:
+ close_subset.append(result)
+ elif violation == 0:
+ close_subset.append(result)
+ return close_subset
+
+
+def filter_by_antenna_vios(results_vector):
+ # Get a close subset by antenna vios
+ sorted_violations = sorted(results_vector, key=itemgetter(antenna_violations_idx))
+ best_violation = int(sorted_violations[0][antenna_violations_idx])
+
+ close_subset = [sorted_violations[0]]
+ for result in sorted_violations[1:]:
+ violation = int(result[antenna_violations_idx])
+ # Allow for 10 vios tolerance
+ if (abs(violation - best_violation) < 10) and best_violation != 0:
+ close_subset.append(result)
+ elif violation == 0:
+ close_subset.append(result)
+ return close_subset
+
+
+def get_best_violation(results_vector):
+ # Remove all failing designs (unless they are all failing then only keep one of them)
+ remover = 0
+ n = len(results_vector)
+ while remover != n and n != 1:
+ if "fail" in str(results_vector[remover][flow_status_idx]):
+ results_vector.pop(remover)
+ remover -= 1
+ n = len(results_vector)
+ remover += 1
+ # Convert violations to integers
+ results_vector = convert_vios_to_int(results_vector)
+
+ # Filter the results vector by TR violations
+ close_subset = filter_by_tr_vios(results_vector)
+ # Filter the close subset by LVS errors
+ close_subset = filter_by_lvs_errors(close_subset)
+ # Filter the close subset by magic DRC violations
+ close_subset = filter_by_magic_vios(close_subset)
+ # Filter the close subset by antenna violations
+ close_subset = filter_by_antenna_vios(close_subset)
+ # Finalize selection based on wire length and via count
+ for i in range(len(close_subset)):
+ row = close_subset[i]
+ wirelength = row[wire_length_idx]
+ via = row[via_idx]
+ row.append((int(wirelength) + int(via)))
+ row[tr_violations_idx] = convert_vio_to_string(row[tr_violations_idx])
+ row[lvs_errors_idx] = convert_vio_to_string(row[lvs_errors_idx])
+ row[magic_violations_idx] = convert_vio_to_string(row[magic_violations_idx])
+ row[antenna_violations_idx] = convert_vio_to_string(row[antenna_violations_idx])
+ close_subset[i] = row
+
+ sorted_wire_length_via = sorted(close_subset, key=itemgetter(-1))
+ best_result = sorted_wire_length_via[0][:-1]
+ return best_result
+
+
+def get_best_results(results_dictionary):
+ best = {}
+ for key in results_dictionary:
+ results = results_dictionary[key]
+ best_result = get_best_violation(results)
+ best[key] = best_result
+
+ return best
+
+
+def save_top_results(results_dictionary, output_file, header):
+ out = open(output_file, "w")
+ out.write(header)
+
+ for key in results_dictionary:
+ out.writelines("%s,%s" % (key, ",".join(results_dictionary[key])))
+ out.write("\n")
+
+ out.close()
+
+
+def findIdx(header, column):
+
+ for idx in range(len(header)):
+ if header[idx] == column:
+ return int(idx)
+ return -1
+
+
+header = get_header(report_file)
+
+headerSplit = header.split(",")
+design_idx = findIdx(headerSplit, "design")
+
+results_dictionary = build_dictionary(report_file)
+
+tr_violations_idx = findIdx(headerSplit, "tritonRoute_violations") - (design_idx + 1)
+lvs_errors_idx = findIdx(headerSplit, "lvs_total_errors") - (design_idx + 1)
+magic_violations_idx = findIdx(headerSplit, "Magic_violations") - (design_idx + 1)
+antenna_violations_idx = findIdx(headerSplit, "antenna_violations") - (design_idx + 1)
+wire_length_idx = findIdx(headerSplit, "wire_length") - (design_idx + 1)
+via_idx = findIdx(headerSplit, "vias") - (design_idx + 1)
+flow_status_idx = findIdx(headerSplit, "flow_status") - (design_idx + 1)
+best_results = get_best_results(results_dictionary)
+
+save_top_results(best_results, output_file, ",".join(headerSplit[design_idx:]))
diff --git a/openlane/scripts/report/get_file_name.py b/openlane/scripts/report/get_file_name.py
new file mode 100755
index 0000000..31572ed
--- /dev/null
+++ b/openlane/scripts/report/get_file_name.py
@@ -0,0 +1,82 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import argparse
+
+
+def get_name(pathname, output_file, partial_match=False):
+ pathname = str(pathname)
+ output_file = str(output_file)
+
+ try:
+ candidates = []
+ for file in os.listdir(pathname):
+ if not os.path.isfile(os.path.join(pathname, file)):
+ continue # Directory
+
+ file_components = file.split("-", 1)
+
+ if len(file_components) <= 1:
+ continue
+
+ step_index, name = file_components
+ step_index = int(step_index)
+
+ if partial_match:
+ if output_file not in name:
+ continue
+ else:
+ if output_file != name:
+ continue
+
+ candidates.append((step_index, name))
+
+ candidates.sort(key=lambda x: x[0], reverse=True)
+
+ file = f"{candidates[0][0]}-{candidates[0][1]}"
+
+ return candidates[0][0], os.path.join(pathname, file)
+ except Exception:
+ return "", os.path.join(pathname, output_file)
+
+
+if __name__ == "__main__":
+ parser = argparse.ArgumentParser(
+ description="Returns the output_file name with the highest index."
+ )
+
+ parser.add_argument("--path", "-p", required=True, help="Path")
+
+ parser.add_argument(
+ "--output_file",
+ "-o",
+ required=True,
+ help="File name to search for, i.e. 1.X 2.X 3.X, then the script will return <path>/3.X",
+ )
+
+ # This whole thing is a contrived way to say "partial match"
+ parser.add_argument(
+ "--include_only",
+ "-I",
+ action="store_true",
+ default=False,
+ help="If enabled the matching is done for inclusion, i.e. the passed output_file is a string that is included in the file name to be matched. -o exam will return matches like: exam.txt and example.txl.",
+ )
+
+ args = parser.parse_args()
+ path = args.path
+ output_file = args.output_file
+ include_only = args.include_only
+ print(get_name(path, output_file, include_only))
diff --git a/openlane/scripts/report/report.py b/openlane/scripts/report/report.py
new file mode 100755
index 0000000..e4c30a2
--- /dev/null
+++ b/openlane/scripts/report/report.py
@@ -0,0 +1,666 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import re
+import sys
+import yaml
+from typing import Iterable, Optional
+
+sys.path.append(os.path.dirname(os.path.dirname(__file__)))
+
+from .get_file_name import get_name # noqa E402
+from utils.utils import get_run_path # noqa E402
+
+
+def debug(*args, **kwargs):
+ if os.getenv("REPORT_INFRASTRUCTURE_VERBOSE") == "1":
+ print(*args, **kwargs, file=sys.stderr)
+
+
+def parse_to_report(
+ input_log: str, output_report: str, start: str, end: Optional[str] = None
+):
+ """
+ Parses a log in the format
+ START_MARKER
+ data
+ END_MARKER
+ to a report file.
+ """
+ if end is None:
+ end = f"{start}_end"
+
+ log_lines = open(input_log).read().split("\n")
+ with open(output_report, "w") as f:
+ started = False
+
+ for line in log_lines:
+ if line.strip() == end:
+ break
+ if started:
+ f.write(line + "\n")
+ if line.strip() == start:
+ started = True
+
+ if not started:
+ f.write("SKIPPED!")
+
+
+class Artifact(object):
+ def __init__(
+ self,
+ run_path: str,
+ kind: str,
+ step: str,
+ filename: str,
+ find_by_partial_match: bool = False,
+ ):
+ self.run_path = run_path
+ self.kind = kind
+ self.step = step
+
+ self.pathname = os.path.join(self.run_path, self.kind, self.step)
+ self.filename = filename
+
+ self.index, self.path = get_name(
+ self.pathname, self.filename, find_by_partial_match
+ )
+
+ if self.is_valid():
+ debug(f"Resolved {kind}, {step}, {filename} to {self.path}")
+ else:
+ debug(f"Failed to resolve {kind}, {step}, {filename}")
+
+ def is_valid(self) -> bool:
+ valid = os.path.exists(self.path) and os.path.isfile(self.path)
+ return valid
+
+ def get_content(self) -> Optional[str]:
+ if not self.is_valid():
+ return None
+ return open(self.path).read()
+
+ def is_logtoreport_valid(self) -> bool:
+ # >10 bytes is a magic number, yes. It was this way in the script I rewrote and I'm not a fan of shaking beehives.
+ return self.is_valid() and os.path.getsize(self.path) > 10
+
+ def log_to_report(self, report_name: str, start: str, end: Optional[str] = None):
+ report_path = os.path.join(self.run_path, "reports", self.step, report_name)
+ if not self.is_logtoreport_valid():
+ debug(f"{self.step}:{self.filename} not found or empty.")
+ return
+ parse_to_report(self.path, report_path, start, end)
+
+ def generate_reports(self, *args: Iterable[Iterable[str]]):
+ if (self.index or "") == "":
+ self.index = "X"
+ for report in args:
+ filename = f"{self.index}-{report[0]}"
+ start = report[1]
+ end = None
+ try:
+ end = report[2]
+ except Exception:
+ pass
+ self.log_to_report(filename, start, end)
+
+
+class Report(object):
+ def __init__(self, design_path, tag, design_name, params, run_path=None):
+ self.design_path = design_path
+ self.design_name = design_name
+ self.tag = tag
+ self.current_directory = os.path.dirname(__file__)
+ if run_path is None:
+ run_path = get_run_path(design=design_path, tag=tag)
+ self.run_path = run_path
+ self.configuration = params
+ self.raw_report = None
+ self.formatted_report = None
+
+ values = (
+ [
+ "design",
+ "design_name",
+ "config",
+ "flow_status",
+ "total_runtime",
+ "routed_runtime",
+ "DIEAREA_mm^2",
+ "CellPer_mm^2",
+ "OpenDP_Util",
+ "Peak_Memory_Usage_MB",
+ "cell_count",
+ "tritonRoute_violations",
+ "Short_violations",
+ "MetSpc_violations",
+ "OffGrid_violations",
+ "MinHole_violations",
+ "Other_violations",
+ "Magic_violations",
+ "antenna_violations",
+ "lvs_total_errors",
+ "cvc_total_errors",
+ "klayout_violations",
+ "wire_length",
+ "vias",
+ "wns",
+ "pl_wns",
+ "optimized_wns",
+ "fastroute_wns",
+ "spef_wns",
+ "tns",
+ "pl_tns",
+ "optimized_tns",
+ "fastroute_tns",
+ "spef_tns",
+ "HPWL",
+ "routing_layer1_pct",
+ "routing_layer2_pct",
+ "routing_layer3_pct",
+ "routing_layer4_pct",
+ "routing_layer5_pct",
+ "routing_layer6_pct",
+ "wires_count",
+ "wire_bits",
+ "public_wires_count",
+ "public_wire_bits",
+ "memories_count",
+ "memory_bits",
+ "processes_count",
+ "cells_pre_abc",
+ "AND",
+ "DFF",
+ "NAND",
+ "NOR",
+ "OR",
+ "XOR",
+ "XNOR",
+ "MUX",
+ ]
+ + (["NOT"] if os.getenv("MORE_METRICS") else [])
+ + [
+ "inputs",
+ "outputs",
+ "level",
+ "EndCaps",
+ "TapCells",
+ "Diodes",
+ "Total_Physical_Cells",
+ ]
+ )
+
+ @classmethod
+ def get_header(Self):
+ header = ",".join(Self.values)
+ return header
+
+ def reports_from_logs(self):
+ rp = self.run_path
+
+ basic_set = [
+ ("_sta.rpt", "check_report"),
+ ("_sta.min.rpt", "min_report"),
+ ("_sta.max.rpt", "max_report"),
+ ("_sta.wns.rpt", "wns_report"),
+ ("_sta.tns.rpt", "tns_report"),
+ ("_sta.clock_skew.rpt", "clock_skew"),
+ ]
+
+ additional_set = [
+ ("_sta.slew.rpt", "check_slew"),
+ ("_sta.worst_slack.rpt", "worst_slack"),
+ ("_sta.clock_skew.rpt", "clock_skew"),
+ ("_sta.power.rpt", "power_report"),
+ ("_sta.area.rpt", "area_report"),
+ ]
+
+ for name, log in [
+ ("cts", Artifact(rp, "logs", "cts", "cts.log")),
+ ("gpl", Artifact(rp, "logs", "placement", "global.log")),
+ ("grt", Artifact(rp, "logs", "routing", "global.log")),
+ ]:
+ generate_report_args = [
+ (name + report_postfix, report_locus)
+ for report_postfix, report_locus in basic_set
+ ]
+ log.generate_reports(*generate_report_args)
+
+ for name, log in [
+ ("syn", Artifact(rp, "logs", "synthesis", "sta.log")),
+ ("cts_rsz", Artifact(rp, "logs", "cts", "resizer.log")),
+ ("pl_rsz", Artifact(rp, "logs", "placement", "resizer.log")),
+ ("rt_rsz", Artifact(rp, "logs", "routing", "resizer.log")),
+ ("rcx", Artifact(rp, "logs", "signoff", "parasitics_sta.log")),
+ (
+ "rcx_mca",
+ Artifact(rp, "logs", "signoff", "parasitics_multi_corner_sta.log"),
+ ),
+ ]:
+ generate_report_args = [
+ (name + report_postfix, report_locus)
+ for report_postfix, report_locus in (basic_set + additional_set)
+ ]
+ log.generate_reports(*generate_report_args)
+
+ def extract_all_values(self):
+ rp = self.run_path
+ self.reports_from_logs()
+
+ def re_get_last_capture(rx, string):
+ matches = re.findall(rx, string)
+ if len(matches) == 0:
+ return None
+ return matches[-1]
+
+ # Runtime
+
+ flow_status = "flow_exceptional_failure"
+ total_runtime = -1
+ routed_runtime = -1
+ try:
+ runtime_yaml_str = open(os.path.join(rp, "runtime.yaml")).read()
+ yaml_docs = list(yaml.safe_load_all(runtime_yaml_str))
+ if len(yaml_docs) != 2:
+ raise Exception("Attempted to generate report on a non-finalized run.")
+
+ routed_info, total_info = yaml_docs[1]
+
+ flow_status = total_info["status"]
+ total_runtime = total_info["runtime_ts"]
+ routed_runtime = routed_info["runtime_ts"]
+ except Exception as e:
+ print(
+ f"Failed to extract runtime info for {self.design_name}/{self.tag}: {e}",
+ file=sys.stderr,
+ )
+
+ # Cell Count
+ cell_count = -1
+ yosys_report = Artifact(rp, "reports", "synthesis", "synthesis.stat.rpt", True)
+ yosys_report_content = yosys_report.get_content()
+ if yosys_report_content is not None:
+ match = re.search(r"Number of cells:\s*(\d+)", yosys_report_content)
+ if match is not None:
+ cell_count = int(match[1])
+
+ # Die Area
+ die_area = -1
+ placed_def = Artifact(rp, "results", "floorplan", f"{self.design_name}.def")
+ def_content = placed_def.get_content()
+ if def_content is not None:
+ match = re.search(
+ r"DIEAREA\s*\(\s*(\d+)\s+(\d+)\s*\)\s*\(\s*(\d+)\s+(\d+)\s*\)",
+ def_content,
+ )
+ if match is not None:
+ lx, ly, ux, uy = (
+ float(match[1]),
+ float(match[2]),
+ float(match[3]),
+ float(match[4]),
+ )
+
+ die_area = ((ux - lx) / 1000) * ((uy - ly) / 1000)
+
+ die_area /= 1000000 # To mm^2
+
+ # Cells per micrometer
+ cells_per_mm = -1
+ if cell_count != -1 and die_area != -1:
+ cells_per_mm = cell_count / die_area
+
+ # OpenDP Utilization and HPWL
+ utilization = -1
+ hpwl = -1 # Half Perimeter Wire Length?
+ global_placement_log = Artifact(rp, "logs", "placement", "global.log")
+ global_log_content = global_placement_log.get_content()
+ if global_log_content is not None:
+ match = re.search(r"Util\(%\):\s*([\d\.]+)", global_log_content)
+
+ if match is not None:
+ utilization = float(match[1])
+
+ match = re_get_last_capture(r"HPWL:\s*([\d\.]+)", global_log_content)
+ if match is not None:
+ hpwl = float(match)
+
+ # TritonRoute Logged Info Extraction
+ tr_log = Artifact(rp, "logs", "routing", "detailed.log")
+ tr_log_content = tr_log.get_content()
+
+ tr_memory_peak = -1
+ tr_violations = -1
+ wire_length = -1
+ vias = -1
+ if tr_log_content is not None:
+ match = re_get_last_capture(r"peak\s*=\s*([\d\.]+)", tr_log_content)
+ if match is not None:
+ tr_memory_peak = float(match)
+
+ match = re_get_last_capture(
+ r"Number of violations\s*=\s*(\d+)", tr_log_content
+ )
+ if match is not None:
+ tr_violations = int(match)
+
+ match = re_get_last_capture(
+ r"Total wire length = ([\d\.]+)\s*\wm", tr_log_content
+ )
+ if match is not None:
+ wire_length = int(match)
+
+ match = re_get_last_capture(r"Total number of vias = (\d+)", tr_log_content)
+ if match is not None:
+ vias = int(match)
+
+ # TritonRoute DRC Extraction
+ tr_drc = Artifact(rp, "reports", "routing", "detailed.drc")
+ tr_drc_content = tr_drc.get_content()
+
+ other_violations = tr_violations
+ short_violations = -1
+ metspc_violations = -1
+ offgrid_violations = -1
+ minhole_violations = -1
+ if tr_drc_content is not None:
+ short_violations = 0
+ metspc_violations = 0
+ offgrid_violations = 0
+ minhole_violations = 0
+ for line in tr_drc_content.split("\n"):
+ if "Short" in line:
+ short_violations += 1
+ other_violations -= 1
+ if "MetSpc" in line:
+ metspc_violations += 1
+ other_violations -= 1
+ if "OffGrid" in line:
+ offgrid_violations += 1
+ other_violations -= 1
+ if "MinHole" in line:
+ minhole_violations += 1
+ other_violations -= 1
+
+ # Magic Violations
+ magic_drc = Artifact(rp, "reports", "signoff", "drc.rpt")
+ magic_drc_content = magic_drc.get_content()
+
+ magic_violations = -1
+ if magic_drc_content is not None:
+ # Magic DRC Content
+ match = re.search(r"COUNT:\s*(\d+)", magic_drc_content)
+ if match is not None:
+ magic_violations_raw = int(match[1])
+
+ # Not really sure why we do this
+ magic_violations = (magic_violations_raw + 3) // 4
+
+ # Klayout DRC Violations
+ klayout_drc = Artifact(rp, "reports", "signoff", "magic.lydrc", True)
+ klayout_drc_content = klayout_drc.get_content()
+
+ klayout_violations = -1
+ if klayout_drc_content is not None:
+ klayout_violations = 0
+ for line in klayout_violations.split("\n"):
+ if "<item>" in line:
+ klayout_violations += 1
+
+ # Antenna Violations
+ arc_antenna_report = Artifact(rp, "reports", "signoff", "antenna.rpt")
+ aar_content = arc_antenna_report.get_content()
+
+ antenna_violations = -1
+ if aar_content is not None:
+ match = re.search(r"Number of pins violated:\s*(\d+)", aar_content)
+
+ if match is not None:
+ antenna_violations = int(match[1])
+ else:
+ # Old Magic-Based Check: Just Count The Lines
+ magic_antenna_report = Artifact(
+ rp, "reports", "routing", "antenna_violators.rpt"
+ )
+ mar_content = magic_antenna_report.get_content()
+
+ if mar_content is not None:
+ antenna_violations = len(mar_content.split("\n"))
+
+ # STA Report Extractions
+ def sta_report_extraction(
+ sta_report_filename: str, filter: str, kind="reports", step="synthesis"
+ ):
+ value = -1
+ report = Artifact(rp, kind, step, sta_report_filename)
+ report_content = report.get_content()
+ if report_content is not None:
+ match = re.search(rf"{filter}\s+(-?[\d\.]+)", report_content)
+ if match is not None:
+ value = float(match[1])
+ else:
+ debug(
+ f"Didn't find {filter} in {kind}/{step}/{sta_report_filename}"
+ )
+ else:
+ debug(f"Can't find {sta_report_filename}")
+ return value
+
+ wns = sta_report_extraction("syn_sta.wns.rpt", "wns", step="synthesis")
+ spef_wns = sta_report_extraction("rcx_sta.wns.rpt", "wns", step="routing")
+ opt_wns = sta_report_extraction("rt_rsz_sta.wns.rpt", "wns", step="routing")
+ pl_wns = sta_report_extraction(
+ "global.log", "wns", kind="logs", step="placement"
+ )
+ fr_wns = sta_report_extraction("global.log", "wns", kind="logs", step="routing")
+
+ tns = sta_report_extraction("syn_sta.tns.rpt", "tns", step="synthesis")
+ spef_tns = sta_report_extraction("rcx_sta.tns.rpt", "tns", step="routing")
+ opt_tns = sta_report_extraction("rt_rsz_sta.tns.rpt", "tns", step="routing")
+ pl_tns = sta_report_extraction(
+ "global.log", "tns", kind="logs", step="placement"
+ )
+ fr_tns = sta_report_extraction("global.log", "tns", kind="logs", step="routing")
+
+ # Yosys Metrics
+ yosys_metrics = [
+ "Number of wires:",
+ "Number of wire bits:",
+ "Number of public wires:",
+ "Number of public wire bits:",
+ "Number of memories:",
+ "Number of memory bits:",
+ "Number of processes:",
+ "Number of cells:",
+ "$_AND_",
+ "$_DFF_",
+ "$_NAND_",
+ "$_NOR_",
+ "$_OR_",
+ "$_XOR_",
+ "$_XNOR_",
+ "$_MUX_",
+ ]
+
+ if os.getenv("MORE_METRICS"):
+ yosys_metrics.append("$_NOT_")
+
+ yosys_log = Artifact(rp, "logs", "synthesis", "synthesis.log")
+ yosys_log_content = yosys_log.get_content()
+
+ yosys_metrics_values = []
+ for metric in yosys_metrics:
+ metric_value = -1
+ if yosys_log_content is not None:
+ metric_value = 0
+ metric_name_escaped = re.escape(metric)
+
+ if metric == "$_DFF_":
+ metric_name_escaped = r"\$_DFF_(?:\w+)?"
+
+ match = re.search(rf"{metric_name_escaped}\s+(\d+)", yosys_log_content)
+
+ if match is not None:
+ metric_value = int(match[1])
+ yosys_metrics_values.append(metric_value)
+
+ # ABC Info
+ abc_i = -1
+ abc_o = -1
+ abc_level = -1
+
+ if yosys_log_content is not None:
+ match = re.search(
+ r"ABC:\s*netlist\s*:\s*i\/o\s*=\s*(\d+)\/\s*(\d+)\s+lat\s*=\s*(\d+)\s+nd\s*=\s*(\d+)\s*edge\s*=\s*(\d+)\s*area\s*=\s*([\d\.]+)\s+delay\s*=\s*([\d\.]+)\s*lev\s*=\s*(\d+)",
+ yosys_log_content,
+ )
+
+ if match is not None:
+ abc_i = match[1]
+ abc_o = match[2]
+ # We don't use most of the ones in the middle.
+ abc_level = match[8]
+
+ # Fastroute Layer Usage Percentages
+ routing_log = Artifact(rp, "logs", "routing", "global.log")
+ routing_log_content = routing_log.get_content()
+
+ # MAGIC NUMBER ALERT
+ layer_usage = [-1] * 6
+ if routing_log_content is not None:
+ routing_log_lines = routing_log_content.split("\n")
+
+ final_congestion_report_start_line = None
+ for i, line in enumerate(routing_log_lines):
+ if "Final congestion report" in line:
+ final_congestion_report_start_line = i
+ break
+
+ if final_congestion_report_start_line is not None:
+ start = final_congestion_report_start_line
+ header = start + 1
+ separator = header + 1
+ layer_start = separator + 1
+ for i in range(6):
+ line = routing_log_lines[layer_start + i]
+ match = re.search(r"([\d\.]+)%", line)
+ if match is not None:
+ layer_usage[i] = float(match[1])
+
+ # Process Filler Cells
+ # Also includes endcap info
+ tapcell_log = Artifact(rp, "logs", "floorplan", "tap.log")
+ tapcell_log_content = tapcell_log.get_content()
+
+ diode_log = Artifact(rp, "logs", "routing", "diodes.log")
+ diode_log_content = diode_log.get_content()
+
+ tapcells, endcaps, diodes = 0, 0, 0
+ if tapcell_log_content is not None:
+ match = re.search(r"Inserted (\d+) end\s*caps\.", tapcell_log_content)
+
+ if match is not None:
+ endcaps = int(match[1])
+
+ match = re.search(r"Inserted (\d+) tap\s*cells\.", tapcell_log_content)
+
+ if match is not None:
+ tapcells = int(match[1])
+
+ if diode_log_content is not None:
+ match = None
+ if "inserted!" in diode_log_content:
+ match = re.search(r"(\d+)\s+of\s+.+?\s+inserted!", diode_log_content)
+ else:
+ match = re.search(r"(\d+)\s+diodes\s+inserted\.", diode_log_content)
+ if match is not None:
+ diodes = int(match[1])
+
+ filler_cells = tapcells + endcaps + diodes
+
+ # LVS Total Errors
+ lvs_report = Artifact(rp, "logs", "signoff", f"{self.design_name}.lvs.lef.log")
+ lvs_report_content = lvs_report.get_content()
+
+ lvs_total_errors = -1
+ if lvs_report_content is not None:
+ lvs_total_errors = 0
+ match = re.search(r"Total errors\s*=\s*(\d+)", lvs_report_content)
+ if match is not None:
+ lvs_total_errors = int(match[1])
+
+ # CVC Total Errors
+ cvc_log = Artifact(rp, "logs", "signoff", "erc_screen.log")
+ cvc_log_content = cvc_log.get_content()
+
+ cvc_total_errors = -1
+ if cvc_log_content is not None:
+ match = re.search(r"CVC:\s*Total:\s*(\d+)", cvc_log_content)
+ if match is not None:
+ cvc_total_errors = int(match[1])
+
+ return [
+ flow_status,
+ total_runtime,
+ routed_runtime,
+ die_area,
+ cells_per_mm,
+ utilization,
+ tr_memory_peak,
+ cell_count,
+ tr_violations,
+ short_violations,
+ metspc_violations,
+ offgrid_violations,
+ minhole_violations,
+ other_violations,
+ magic_violations,
+ antenna_violations,
+ lvs_total_errors,
+ cvc_total_errors,
+ klayout_violations,
+ wire_length,
+ vias,
+ wns,
+ pl_wns,
+ opt_wns,
+ fr_wns,
+ spef_wns,
+ tns,
+ pl_tns,
+ opt_tns,
+ fr_tns,
+ spef_tns,
+ hpwl,
+ *layer_usage,
+ *yosys_metrics_values,
+ abc_i,
+ abc_o,
+ abc_level,
+ endcaps,
+ tapcells,
+ diodes,
+ filler_cells,
+ ]
+
+ def get_report(self):
+ row = [
+ self.design_path,
+ self.design_name,
+ self.tag,
+ *self.extract_all_values(),
+ *self.configuration,
+ ]
+ return ",".join([f"{cell}" for cell in row])
diff --git a/openlane/scripts/report/report_routing.py b/openlane/scripts/report/report_routing.py
new file mode 100644
index 0000000..20b562e
--- /dev/null
+++ b/openlane/scripts/report/report_routing.py
@@ -0,0 +1,242 @@
+# Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+from typing import Iterable, Optional
+
+sys.path.append(os.path.dirname(os.path.dirname(__file__)))
+
+from utils.utils import get_run_path # noqa E402
+from .get_file_name import get_name # noqa E402
+
+
+def debug(*args, **kwargs):
+ if os.getenv("REPORT_INFRASTRUCTURE_VERBOSE") == "1":
+ print(*args, **kwargs)
+
+
+def parse_to_report(
+ input_log: str, output_report: str, start: str, end: Optional[str] = None
+):
+ """
+ Parses a log in the format
+ START_MARKER
+ data
+ END_MARKER
+ to a report file.
+ """
+ if end is None:
+ end = f"{start}_end"
+
+ log_lines = open(input_log).read().split("\n")
+ with open(output_report, "w") as f:
+ started = False
+
+ for line in log_lines:
+ if line.strip() == end:
+ break
+ if started:
+ f.write(line + "\n")
+ if line.strip() == start:
+ started = True
+
+ if not started:
+ f.write("SKIPPED!")
+
+
+class Artifact(object):
+ def __init__(
+ self,
+ run_path: str,
+ kind: str,
+ step: str,
+ filename: str,
+ find_by_partial_match: bool = False,
+ ):
+ self.run_path = run_path
+ self.kind = kind
+ self.step = step
+
+ self.pathname = os.path.join(self.run_path, self.kind, self.step)
+ self.filename = filename
+
+ self.index, self.path = get_name(
+ self.pathname, self.filename, find_by_partial_match
+ )
+
+ if self.is_valid():
+ debug(f"Resolved {kind}, {step}, {filename} to {self.path}")
+ else:
+ debug(f"Failed to resolve {kind}, {step}, {filename}")
+
+ def is_valid(self) -> bool:
+ valid = os.path.exists(self.path) and os.path.isfile(self.path)
+ return valid
+
+ def get_content(self) -> Optional[str]:
+ if not self.is_valid():
+ return None
+ return open(self.path).read()
+
+ def is_logtoreport_valid(self) -> bool:
+ return self.is_valid() and os.path.getsize(self.path) > 10
+
+ def log_to_report(self, report_name: str, start: str, end: Optional[str] = None):
+ report_path = os.path.join(self.run_path, "reports", self.step, report_name)
+ if not self.is_logtoreport_valid():
+ with open(report_path, "w") as f:
+ f.write(f"{self.step}:{self.filename} not found or empty.")
+ return
+ parse_to_report(self.path, report_path, start, end)
+
+ def generate_reports(self, *args: Iterable[Iterable[str]]):
+ for report in args:
+ filename = f"{self.index}-{report[0]}"
+ start = report[1]
+ end = None
+ try:
+ end = report[2]
+ except Exception:
+ pass
+ self.log_to_report(filename, start, end)
+
+
+class Report(object):
+ def __init__(self, design_path, tag, design_name, params, run_path=None):
+ self.design_path = design_path
+ self.design_name = design_name
+ self.tag = tag
+ self.current_directory = os.path.dirname(__file__)
+ if run_path is None:
+ run_path = get_run_path(design=design_path, tag=tag)
+ self.run_path = run_path
+ self.configuration = params
+ self.raw_report = None
+ self.formatted_report = None
+
+ values = [
+ "design",
+ "design_name",
+ "config",
+ "flow_status",
+ "total_runtime",
+ "routed_runtime",
+ "DIEAREA_mm^2",
+ "CellPer_mm^2",
+ "OpenDP_Util",
+ "Peak_Memory_Usage_MB",
+ "cell_count",
+ "tritonRoute_violations",
+ "Short_violations",
+ "MetSpc_violations",
+ "OffGrid_violations",
+ "MinHole_violations",
+ "Other_violations",
+ "Magic_violations",
+ "antenna_violations",
+ "lvs_total_errors",
+ "cvc_total_errors",
+ "klayout_violations",
+ "wire_length",
+ "vias",
+ "wns",
+ "pl_wns",
+ "optimized_wns",
+ "fastroute_wns",
+ "spef_wns",
+ "tns",
+ "pl_tns",
+ "optimized_tns",
+ "fastroute_tns",
+ "spef_tns",
+ "HPWL",
+ "routing_layer1_pct",
+ "routing_layer2_pct",
+ "routing_layer3_pct",
+ "routing_layer4_pct",
+ "routing_layer5_pct",
+ "routing_layer6_pct",
+ "wires_count",
+ "wire_bits",
+ "public_wires_count",
+ "public_wire_bits",
+ "memories_count",
+ "memory_bits",
+ "processes_count",
+ "cells_pre_abc",
+ "AND",
+ "DFF",
+ "NAND",
+ "NOR",
+ "OR",
+ "XOR",
+ "XNOR",
+ "MUX",
+ "inputs",
+ "outputs",
+ "level",
+ "EndCaps",
+ "TapCells",
+ "Diodes",
+ "Total_Physical_Cells",
+ ]
+
+ @classmethod
+ def get_header(Self):
+ header = ",".join(Self.values)
+ return header
+
+ def reports_from_logs(self):
+ rp = self.run_path
+
+ routing_log = Artifact(rp, "logs", "routing", "fastroute.log")
+ routing_log.generate_reports(
+ ("fastroute_sta.rpt", "check_report"),
+ ("fastroute_sta.clock_skew.rpt", "clock_skew"),
+ ("fastroute_sta.min.rpt", "min_report"),
+ ("fastroute_sta.max.rpt", "max_report"),
+ ("fastroute_sta.wns.rpt", "wns_report"),
+ ("fastroute_sta.tns.rpt", "tns_report"),
+ )
+
+ sta_spef_log = Artifact(rp, "logs", "routing", "spef_extraction_sta")
+ sta_spef_log.generate_reports(
+ ("spef_extraction_sta.rpt", "check_report"),
+ ("spef_extraction_sta.min.rpt", "min_report"),
+ ("spef_extraction_sta.max.rpt", "max_report"),
+ ("spef_extraction_sta.wns.rpt", "wns_report"),
+ ("spef_extraction_sta.tns.rpt", "tns_report"),
+ ("spef_extraction_sta.slew.rpt", "check_slew"),
+ ("spef_extraction_sta.worst_slack.rpt", "worst_slack"),
+ ("spef_extraction_sta.clock_skew.rpt", "clock_skew"),
+ ("spef_extraction_sta.power.rpt", "power_report"),
+ ("spef_extraction_sta.area.rpt", "area_report"),
+ )
+
+ sta_spef_multi_corner_log = Artifact(
+ rp, "logs", "routing", "spef_extraction_multi_corner_sta"
+ )
+ sta_spef_multi_corner_log.generate_reports(
+ ("spef_extraction_multi_corner_sta.rpt", "check_report"),
+ ("spef_extraction_multi_corner_sta.min.rpt", "min_report"),
+ ("spef_extraction_multi_corner_sta.max.rpt", "max_report"),
+ ("spef_extraction_multi_corner_sta.wns.rpt", "wns_report"),
+ ("spef_extraction_multi_corner_sta.tns.rpt", "tns_report"),
+ ("spef_extraction_multi_corner_sta.slew.rpt", "check_slew"),
+ ("spef_extraction_multi_corner_sta.worst_slack.rpt", "worst_slack"),
+ ("spef_extraction_multi_corner_sta.clock_skew.rpt", "clock_skew"),
+ ("spef_extraction_multi_corner_sta.power.rpt", "power_report"),
+ ("spef_extraction_multi_corner_sta.area.rpt", "area_report"),
+ )
diff --git a/openlane/scripts/set_layer_tracks.py b/openlane/scripts/set_layer_tracks.py
new file mode 100644
index 0000000..2492d6a
--- /dev/null
+++ b/openlane/scripts/set_layer_tracks.py
@@ -0,0 +1,78 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+
+parser = argparse.ArgumentParser(
+ description="sets the tracks on a layer to specific value"
+)
+
+parser.add_argument("--defFile", "-d", required=True, help="Input DEF")
+
+parser.add_argument("--layer", "-l", required=True, help="layer to change")
+
+parser.add_argument(
+ "--valuesFile", "-v", required=True, help="tmp file to read the new value from"
+)
+
+parser.add_argument(
+ "--originalFile", "-o", required=True, help="tmp file to store the original value"
+)
+
+
+args = parser.parse_args()
+def_file_name = args.defFile
+layer = args.layer
+input_file_name = args.valuesFile
+output_file_name = args.originalFile
+
+defFileOpener = open(def_file_name, "r")
+if defFileOpener.mode == "r":
+ defContent = defFileOpener.read().split("\n")
+defFileOpener.close()
+
+
+inputFileOpener = open(input_file_name, "r")
+if inputFileOpener.mode == "r":
+ inputXY = inputFileOpener.read().split()
+inputFileOpener.close()
+
+printedXY = ["0", "0"]
+
+outOrder = 0
+for i in range(len(defContent)):
+ if outOrder == 2:
+ break
+ if defContent[i].find(layer) != -1:
+ tmpLine = defContent[i].split(" ")
+ if tmpLine[0] != "TRACKS":
+ continue
+ if tmpLine[1] == "X":
+ printedXY[0] = tmpLine[4]
+ tmpLine[4] = inputXY[0]
+ else:
+ printedXY[1] = tmpLine[4]
+ tmpLine[4] = inputXY[1]
+ defContent[i] = " ".join(tmpLine)
+ outOrder += 1
+ continue
+
+
+defFileOpener = open(def_file_name, "w")
+defFileOpener.write("\n".join(defContent))
+defFileOpener.close()
+
+outputFileOpener = open(output_file_name, "w")
+outputFileOpener.write("\n".join(printedXY))
+outputFileOpener.close()
diff --git a/openlane/scripts/simple_cts.py b/openlane/scripts/simple_cts.py
new file mode 100644
index 0000000..70f6fdc
--- /dev/null
+++ b/openlane/scripts/simple_cts.py
@@ -0,0 +1,140 @@
+#!/usr/bin/env python3
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Original code by M. Shalan, Translated to Python by Donn
+
+import io
+import re
+import math
+import click
+import textwrap
+
+
+@click.command()
+@click.option("--fanout", required=True)
+@click.option("--clk-net", required=True)
+@click.option("--root-clkbuf", required=True, help="Clock tree root buffer type")
+@click.option("--clkbuf", required=True, help="Clock tree branching buffer type")
+@click.option(
+ "--clkbuf-input-pin", required=True, help="Name of input pin in clock buffers"
+)
+@click.option(
+ "--clkbuf-output-pin", required=True, help="Name of output pin in clock buffers"
+)
+@click.option("--clk-port", required=True, help="Name of clock pin in storage elements")
+@click.option("-o", "--output", required=True, help="Name of output netlist")
+@click.argument("input_netlist")
+def cli(
+ fanout,
+ clk_net,
+ clkbuf,
+ root_clkbuf,
+ clkbuf_input_pin,
+ clkbuf_output_pin,
+ clk_port,
+ output,
+ input_netlist,
+):
+ """
+ Shalan's Simple Clock Tree Synthesizer
+
+ Made to work on Yosys netlists.
+ """
+ fanout = int(fanout)
+
+ netlist_str = open(input_netlist).read()
+ clock_port_rx = re.compile(rf"{re.escape(clk_port)}\(\s*{re.escape(clk_net)}\s*\)")
+ leaves = len(clock_port_rx.findall(netlist_str))
+ levels = math.ceil(math.log(leaves, fanout))
+
+ buffers = [0] * (levels + 1)
+ buffers[0] = leaves
+
+ verilog_wires = []
+ verilog_cells = []
+
+ cell_count = 0
+ for level in range(1, levels):
+ level_before = level - 1
+ instance = f"_CTS_buf_{level}_"
+ input_wire = f"clk_{level}_"
+ output_wire = f"clk_{level_before}_"
+
+ # obviously translated c-style for loop
+ i = 0
+ while i < leaves:
+ next_level_fanout = fanout ** (level + 1)
+ ii = i // next_level_fanout * next_level_fanout
+ cell_name = f"{instance}{i}"
+ verilog_cells.append(
+ textwrap.dedent(
+ f"""
+ {clkbuf} {cell_name} (
+ \t.{clkbuf_input_pin}({input_wire}{ii}),
+ \t.{clkbuf_output_pin}({output_wire}{i})
+ );"""
+ )
+ )
+ verilog_wires.append(f"wire {output_wire}{i};")
+ buffers[level] += 1
+ cell_count += 1
+
+ i += fanout**level
+
+ root_net = f"clk_{levels - 1}_0"
+ verilog_cells.append(
+ textwrap.dedent(
+ f"""
+ {root_clkbuf} _CTS_root(
+ \t.{clkbuf_input_pin}({clk_net}),
+ \t.{clkbuf_output_pin}({root_net})
+ );"""
+ )
+ )
+ verilog_wires.append(f"wire clk_{levels - 1}_0;\n")
+
+ with io.StringIO() as sio:
+ state = 0
+ ff_count = 0
+ for line in netlist_str.split("\n"):
+ if state == 0:
+ if "wire" in line:
+ state = 1
+ print(line, file=sio)
+ elif state == 1:
+ if "wire" not in line and "input" not in line and "output" not in line:
+ state = 2
+ print("\n// CTS added wires:", file=sio)
+ print("\n".join(verilog_wires), file=sio)
+ print("\n// CTS added buffers:", file=sio)
+ print("\n".join(verilog_cells), file=sio)
+ print(line, file=sio)
+ else:
+ print(line, file=sio)
+ elif state == 2:
+ clk_port = clock_port_rx.search(line)
+ if clk_port is not None:
+ clk_wire_name = f"clk_0_{ff_count // fanout * fanout}"
+ line_replaced = re.sub(re.escape(clk_net), clk_wire_name, line)
+ ff_count += 1
+ print(line_replaced, file=sio)
+ else:
+ print(line, file=sio)
+ with open(output, "w") as f:
+ f.write(sio.getvalue())
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/synth_exp/analyze.py b/openlane/scripts/synth_exp/analyze.py
new file mode 100644
index 0000000..e2cf840
--- /dev/null
+++ b/openlane/scripts/synth_exp/analyze.py
@@ -0,0 +1,292 @@
+#!/usr/bin/python3
+# Copyright 2021 Efabless Corporation
+# Original File Copyright 2020 Mohamed Shalan
+#
+# Licensed under the Apache License, Version 2.0 (the "License")
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Direct-translated from Perl to Python by Donn.
+
+from math import inf
+import re
+import click
+
+
+@click.command()
+@click.option("-o", "--output", required=True, help="Output HTML file")
+@click.argument("input_file")
+def cli(output, input_file):
+ """
+ This script parses a yosys synthesis exploration log and generates a
+ rudimentary HTML report.
+ """
+ output_file_handle = open(output, "w")
+
+ def write(string):
+ print(string, file=output_file_handle)
+
+ file_str = open(input_file).read()
+ file_lines = file_str.split("\n")
+
+ # aw = 0.5
+ # dw = 0.5
+ # ascale = 100
+ minimum_area = inf
+ minimum_gates = inf
+ minimum_delay = inf
+
+ best_area = ""
+ best_delay = ""
+
+ strat_rx = re.compile(r"USING STRATEGY ([A-Z]+\d+)")
+ delay_rx = re.compile(r"Delay\s+\=\s+(\S+)")
+ area_rx = re.compile(r"Area\s+\=\s+(\S+)")
+ gates_rx = re.compile(r"Gates\s+\=\s+(\S+)")
+
+ data = []
+
+ strategy_name = "UNKNOWN"
+ for line in file_lines:
+ if "USING STRATEGY " in line:
+ strat_m = strat_rx.search(line)
+ strat = strat_m[1]
+
+ strategy_name = strat
+
+ if "none" in line:
+ delay_m = delay_rx.search(line)
+ delay = float(delay_m[1])
+ area_m = area_rx.search(line)
+ area = float(area_m[1])
+ gates_m = gates_rx.search(line)
+ gates = float(gates_m[1])
+ # factor = aw * area / ascale + dw * delay
+ if area < minimum_area:
+ minimum_area = area
+ best_area = strategy_name
+
+ if delay < minimum_delay:
+ minimum_delay = delay
+ best_delay = strategy_name
+
+ if gates < minimum_gates:
+ minimum_gates = gates
+ bestGates = strategy_name
+
+ data.append((strategy_name, delay, area, gates))
+
+ write(
+ f"""
+ <html>
+
+ <head>
+ <title>Scatter Chart</title>
+ <link href='table.css' rel='stylesheet' type='text/css' media='screen' />
+ <script src='https://cdnjs.cloudflare.com/ajax/libs/Chart.js/2.7.2/Chart.min.js'></script>
+ <script src='utils.js'></script>
+ <style>
+ canvas {{
+ -moz-user-select: none;
+ -webkit-user-select: none;
+ -ms-user-select: none;
+ }}
+ </style>
+ </head>
+
+ <body>
+ <div style='width:50%''>
+
+ <table cellspacing='0' cellpadding='0' class='demo-table' >
+ <tr>
+ <th bgcolor='b0c4de'>Best Area</th>
+ <th bgcolor='b0c4de'>Best Gate Count</th>
+ <th bgcolor='b0c4de'>Best Delay</th>
+ </tr>
+ <tr>
+ <td>{minimum_area}</td>
+ <td>{minimum_gates}</td>
+ <td>{minimum_delay}</td>
+ </tr>
+ <tr>
+ <td>{best_area}</td>
+ <td>{bestGates}</td>
+ <td>{best_delay}</td>
+ </tr>
+ </table><br>
+
+ <table cellspacing='0' cellpadding='0' class='demo-table' >
+ <tr>
+ <th bgcolor='b0c4de'>Strategy</th>
+ <th bgcolor='b0c4de'>Gate Count</th>
+ <th bgcolor='b0c4de'>Area (um^2)</th>
+ <th bgcolor='b0c4de'>Delay (ps)</th>
+
+ <th bgcolor='b0c4de'>Gates Ratio</th>
+ <th bgcolor='b0c4de'>Area Ratio</th>
+ <th bgcolor='b0c4de'>Delay Ratio</th>
+
+ </tr>
+ """
+ )
+
+ for index, datapoint in enumerate(data):
+ label, delay, area, gates = datapoint
+ write("<tr>")
+
+ # dfactor = 0.25 * area / minArea + 0.75 * delay / minDelay
+ # afactor = 0.75 * area / minArea + 0.25 * delay / minDelay
+
+ dratio = int(delay / minimum_delay * 1000) / 1000
+ aratio = int(area / minimum_area * 1000) / 1000
+ gratio = int(gates / minimum_gates * 1000) / 1000
+
+ write(f"<td>{label}</td>")
+
+ if gratio < 1.0001:
+ write(f"<td bgcolor='#ccff99'>{gates}</td>")
+ else:
+ write(f"<td>{gates}</td>")
+
+ if aratio < 1.0001:
+ write(f"<td bgcolor='#ccff99'>{area}</td>")
+ else:
+ write(f"<td>{area}</td>")
+
+ if dratio < 1.0001:
+ write(f"<td bgcolor='#ccff99'>{delay}</td>")
+ else:
+ write(f"<td>{delay}</td>\n")
+
+ if gratio <= 1.1:
+ write(f"<td bgcolor='#fffacd'>{gratio}</td>")
+ else:
+ write(f"<td>{gratio}</td>")
+
+ if aratio <= 1.1:
+ write(f"<td bgcolor='#fffacd'>{aratio}</td>")
+ else:
+ write(f"<td>{aratio}</td>")
+
+ if dratio <= 1.1:
+ write(f"<td bgcolor='#fffacd'>{dratio}</td>")
+ else:
+ write(f"<td>{dratio}</td>")
+ # print " + Best Area" if(aratio < 1.0001)
+ # print " + Best Delay" if(dratio < 1.0001)
+
+ write("</tr>")
+
+ # if((dratio < 1.15) && (aratio < 1.15)){
+ # printf (" <== Best Ratio: %.3f - %.3f\n", aratio, dratio)
+ # } else {
+ # print "\n"
+ # }
+ write("</table>")
+
+ colors = [
+ "red",
+ "olive",
+ "yellow",
+ "green",
+ "blue",
+ "purple",
+ "grey",
+ "black",
+ "aqua",
+ "fuchsia",
+ "orange",
+ "tan",
+ ]
+
+ write(
+ """
+ </div>
+ <div style='width:65%''>
+ <canvas id='myChart'></canvas>
+ </div>
+
+
+
+ <script>
+ var ctx = document.getElementById('myChart');
+ var color = Chart.helpers.color;
+ var scatterChart = new Chart(ctx, {
+ type: 'scatter',
+
+ data: {
+ datasets: [
+ """
+ )
+
+ for index, datapoint in enumerate(data):
+ label, delay, area, gates = datapoint
+ # dfactor = 0.25 * area / minArea + 0.75 * delay / minDelay
+ # afactor = 0.75 * area / minArea + 0.25 * delay / minDelay
+
+ color = colors[index % len(colors)]
+
+ write(
+ f"""
+ {{
+ label: '{label}',
+ borderColor: window.chartColors.{color},
+ backgroundColor: color(window.chartColors.{color}).alpha(0.2).rgbString(),
+ pointRadius: 7,
+ data: [{{
+ x: {area},
+ y: {delay}
+ }}]
+ }},
+ """
+ )
+
+ write(
+ """
+ ]
+ },
+ options: {
+ title: {
+ display: true,
+ text: 'Synthesis Strategies Comparison'
+ },
+ scales: {
+ xAxes: [{
+ type: 'linear',
+ position: 'bottom',
+ scaleLabel: {
+ display: true,
+ labelString: 'Area'
+ }
+ }],
+ yAxes: [{
+ type: 'linear',
+ position: 'left',
+ scaleLabel: {
+ display: true,
+ labelString: 'Delay'
+ }
+ }]
+ }
+ }
+ });
+ </script>
+
+ </body>
+
+ </html>
+ """
+ )
+ output_file_handle.close()
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/synth_exp/table.css b/openlane/scripts/synth_exp/table.css
new file mode 100644
index 0000000..6a61fcf
--- /dev/null
+++ b/openlane/scripts/synth_exp/table.css
@@ -0,0 +1,53 @@
+.demo-table {
+ border-collapse: collapse;
+ font-size: 11px;
+ font-family: verdana;
+ }
+ .demo-table th,
+ .demo-table td {
+ border: 2px solid #e1edff;
+ padding: 3px 10px;
+ }
+ .demo-table .title {
+ caption-side: bottom;
+ margin-top: 12px;
+ }
+
+ /* Table Header */
+ .demo-table thead th {
+ background-color: #707070;
+ color: #0000ff;
+ border-color: #6ea1cc !important;
+ text-transform: uppercase;
+ }
+
+ /* Table Body */
+ .demo-table tbody td {
+ color: #353535;
+ }
+ .demo-table tbody td:first-child,
+ .demo-table tbody td:last-child,
+ .demo-table tbody td:nth-child(4) {
+ text-align: left;
+ }
+/*
+ .demo-table tbody tr:nth-child(odd) td {
+ background-color: #f4fbff;
+ }*/
+ .demo-table tbody tr:hover td {
+ background-color: #ffffa2;
+ border-color: #ffff0f;
+ transition: all .2s;
+ }
+
+ /* Table Footer */
+ .demo-table tfoot th {
+ background-color: #e5f5ff;
+ }
+ .demo-table tfoot th:first-child {
+ text-align: left;
+ }
+ .demo-table tbody td:empty
+ {
+ background-color: #ffcccc;
+ }
diff --git a/openlane/scripts/synth_exp/utils.js b/openlane/scripts/synth_exp/utils.js
new file mode 100644
index 0000000..178635a
--- /dev/null
+++ b/openlane/scripts/synth_exp/utils.js
@@ -0,0 +1,167 @@
+// Copyright 2020 Mohamed Shalan
+
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+'use strict';
+
+window.chartColors = {
+ red: 'rgb(255, 99, 132)',
+ orange: 'rgb(255, 159, 64)',
+ yellow: 'rgb(230, 230, 6)',
+ green: 'rgb(10, 250, 10)',
+ blue: 'rgb(54, 162, 235)',
+ purple: 'rgb(153, 102, 255)',
+ grey: 'rgb(201, 203, 207)',
+ black: 'rgb(10, 10, 10)',
+ aqua: 'rgb(10, 250, 250)',
+ fuchsia: 'rgb(250, 5, 250)',
+ olive: 'rgb(128, 128, 0)',
+ tan: 'rgb(210, 180, 140)'
+
+
+};
+
+(function(global) {
+ var Months = [
+ 'January',
+ 'February',
+ 'March',
+ 'April',
+ 'May',
+ 'June',
+ 'July',
+ 'August',
+ 'September',
+ 'October',
+ 'November',
+ 'December'
+ ];
+
+ var COLORS = [
+ '#4dc9f6',
+ '#f67019',
+ '#f53794',
+ '#537bc4',
+ '#acc236',
+ '#166a8f',
+ '#00a950',
+ '#58595b',
+ '#8549ba'
+ ];
+
+ var Samples = global.Samples || (global.Samples = {});
+ var Color = global.Color;
+
+ Samples.utils = {
+ // Adapted from http://indiegamr.com/generate-repeatable-random-numbers-in-js/
+ srand: function(seed) {
+ this._seed = seed;
+ },
+
+ rand: function(min, max) {
+ var seed = this._seed;
+ min = min === undefined ? 0 : min;
+ max = max === undefined ? 1 : max;
+ this._seed = (seed * 9301 + 49297) % 233280;
+ return min + (this._seed / 233280) * (max - min);
+ },
+
+ numbers: function(config) {
+ var cfg = config || {};
+ var min = cfg.min || 0;
+ var max = cfg.max || 1;
+ var from = cfg.from || [];
+ var count = cfg.count || 8;
+ var decimals = cfg.decimals || 8;
+ var continuity = cfg.continuity || 1;
+ var dfactor = Math.pow(10, decimals) || 0;
+ var data = [];
+ var i, value;
+
+ for (i = 0; i < count; ++i) {
+ value = (from[i] || 0) + this.rand(min, max);
+ if (this.rand() <= continuity) {
+ data.push(Math.round(dfactor * value) / dfactor);
+ } else {
+ data.push(null);
+ }
+ }
+
+ return data;
+ },
+
+ labels: function(config) {
+ var cfg = config || {};
+ var min = cfg.min || 0;
+ var max = cfg.max || 100;
+ var count = cfg.count || 8;
+ var step = (max - min) / count;
+ var decimals = cfg.decimals || 8;
+ var dfactor = Math.pow(10, decimals) || 0;
+ var prefix = cfg.prefix || '';
+ var values = [];
+ var i;
+
+ for (i = min; i < max; i += step) {
+ values.push(prefix + Math.round(dfactor * i) / dfactor);
+ }
+
+ return values;
+ },
+
+ months: function(config) {
+ var cfg = config || {};
+ var count = cfg.count || 12;
+ var section = cfg.section;
+ var values = [];
+ var i, value;
+
+ for (i = 0; i < count; ++i) {
+ value = Months[Math.ceil(i) % 12];
+ values.push(value.substring(0, section));
+ }
+
+ return values;
+ },
+
+ color: function(index) {
+ return COLORS[index % COLORS.length];
+ },
+
+ transparentize: function(color, opacity) {
+ var alpha = opacity === undefined ? 0.5 : 1 - opacity;
+ return Color(color).alpha(alpha).rgbString();
+ }
+ };
+
+ // DEPRECATED
+ window.randomScalingFactor = function() {
+ return Math.round(Samples.utils.rand(-100, 100));
+ };
+
+ // INITIALIZATION
+
+ Samples.utils.srand(Date.now());
+
+ // Google Analytics
+ /* eslint-disable */
+ if (document.location.hostname.match(/^(www\.)?chartjs\.org$/)) {
+ (function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){
+ (i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),
+ m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)
+ })(window,document,'script','//www.google-analytics.com/analytics.js','ga');
+ ga('create', 'UA-28909194-3', 'auto');
+ ga('send', 'pageview');
+ }
+ /* eslint-enable */
+
+}(this));
diff --git a/openlane/scripts/tcl_commands/README.md b/openlane/scripts/tcl_commands/README.md
new file mode 100644
index 0000000..8d56a95
--- /dev/null
+++ b/openlane/scripts/tcl_commands/README.md
@@ -0,0 +1,9 @@
+# OpenLane Package
+-------------------
+
+## Commands:
+
+Refer to this [README](../../docs/source/openlane_commands.md)
+
+** All .tcl files placed here should `provide openlane`; otherwise, they won't
+be available in the flow.
diff --git a/openlane/scripts/tcl_commands/all.tcl b/openlane/scripts/tcl_commands/all.tcl
new file mode 100755
index 0000000..3ceca08
--- /dev/null
+++ b/openlane/scripts/tcl_commands/all.tcl
@@ -0,0 +1,1010 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+package require json
+package require openlane_utils
+
+
+proc save_state {args} {
+ set ::env(INIT_ENV_VAR_ARRAY) [split [array names ::env] " "]
+ puts_info "Saving runtime environment..."
+ set_log ::env(PDK_ROOT) $::env(PDK_ROOT) $::env(GLB_CFG_FILE) 1
+ foreach index [lsort [array names ::env]] {
+ if { $index != "INIT_ENV_VAR_ARRAY" && $index != "PS1" } {
+ set escaped_env_var [string map {\" \\\"} $::env($index)]
+ set escaped_env_var [string map {\$ \\\$} $escaped_env_var]
+ set_log ::env($index) $escaped_env_var $::env(GLB_CFG_FILE) 1
+ }
+ }
+}
+
+proc set_netlist {netlist args} {
+ set options {}
+
+ set flags {
+ -lec
+ }
+ set args_copy $args
+
+ parse_key_args "set_netlist" args arg_values $options flags_map $flags
+
+ set netlist_relative [relpath . $netlist]
+
+ puts_verbose "Changing netlist to '$netlist_relative'..."
+
+ set ::env(PREV_NETLIST) $::env(CURRENT_NETLIST)
+ set ::env(CURRENT_NETLIST) $netlist
+
+ set replace [string map {/ \\/} $::env(CURRENT_NETLIST)]
+ try_catch sed -i -e "s/\\(set ::env(CURRENT_NETLIST)\\).*/\\1 $replace/" "$::env(GLB_CFG_FILE)"
+
+ set replace [string map {/ \\/} $::env(PREV_NETLIST)]
+ try_catch sed -i -e "s/\\(set ::env(PREV_NETLIST)\\).*/\\1 $replace/" "$::env(GLB_CFG_FILE)"
+
+ if { [info exists flags_map(-lec)] && [file exists $::env(PREV_NETLIST)] } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+}
+
+proc set_def {def} {
+ set def_relative [relpath . $def]
+ puts_verbose "Changing layout to '$def_relative'..."
+ set ::env(CURRENT_DEF) $def
+ set replace [string map {/ \\/} $def]
+ exec sed -i -e "s/\\(set ::env(CURRENT_DEF)\\).*/\\1 $replace/" "$::env(GLB_CFG_FILE)"
+}
+
+proc set_guide {guide} {
+ set guide_relative [relpath . $guide]
+ puts_verbose "Changing guide to '$guide_relative'..."
+ set ::env(CURRENT_GUIDE) $guide
+ set replace [string map {/ \\/} $guide]
+ exec sed -i -e "s/\\(set ::env(CURRENT_GUIDE)\\).*/\\1 $replace/" "$::env(GLB_CFG_FILE)"
+}
+
+proc prep_lefs {args} {
+ set options {
+ {-tech_lef optional}
+ {-cell_lef optional}
+ {-corner optional}
+ {-env_var optional}
+ }
+
+ set flags {-no_widen}
+
+ parse_key_args "prep_lefs" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-tech_lef) $::env(TECH_LEF)
+ set_if_unset arg_values(-cell_lef) $::env(CELLS_LEF)
+ set_if_unset arg_values(-env_var) MERGED_LEF
+ set_if_unset arg_values(-corner) nom
+
+ if { ![file exists $arg_values(-tech_lef)] } {
+ if { $arg_values(-env_var) == "MERGED_LEF" } {
+ puts_err "Nominal process corner '$arg_values(-tech_lef)' not found."
+ return -code error
+ }
+ puts_info "'$arg_values(-tech_lef)' not found, skipping..."
+ return
+ }
+ puts_info "Preparing LEF files for the $arg_values(-corner) corner..."
+
+ if { $arg_values(-corner) == "nom" } {
+ puts_verbose "Extracting the number of available metal layers from $arg_values(-tech_lef)"
+
+ set ::env(TECH_METAL_LAYERS) [exec python3 $::env(SCRIPTS_DIR)/extract_metal_layers.py $arg_values(-tech_lef)]
+ set ::env(MAX_METAL_LAYER) [llength $::env(TECH_METAL_LAYERS)]
+
+ puts_verbose "The available metal layers ($::env(MAX_METAL_LAYER)) are $::env(TECH_METAL_LAYERS)"
+ puts_verbose "Merging LEF Files..."
+ }
+
+ set mlu $::env(TMP_DIR)/merged.unpadded.$arg_values(-corner).lef
+
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py\
+ -o $mlu\
+ -i $arg_values(-tech_lef) $arg_values(-cell_lef)\
+ |& tee $::env(TERMINAL_OUTPUT)
+
+ set mlu_relative [relpath . $mlu]
+ puts_verbose "Created merged LEF without pads at '$mlu_relative'..."
+
+ # Merged Extra Lefs (if they exist)
+ if { [info exist ::env(EXTRA_LEFS)] } {
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py\
+ -o $mlu\
+ -i $mlu {*}$::env(EXTRA_LEFS)\
+ |& tee $::env(TERMINAL_OUTPUT)
+ puts_verbose "Added extra lefs to '$mlu_relative'..."
+ }
+
+ # Merge optimization TLEF/CLEF (if exists)
+ if { [info exist ::env(STD_CELL_LIBRARY_OPT)] && $::env(STD_CELL_LIBRARY_OPT) != $::env(STD_CELL_LIBRARY) } {
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py\
+ -o $mlu\
+ -i $mlu $::env(TECH_LEF_OPT) {*}$::env(CELLS_LEF_OPT) |& tee $::env(TERMINAL_OUTPUT)
+ puts_verbose "Added optimization library tech lef and cell lefs to '$mlu_relative'..."
+ }
+
+ # Merge pads (if GPIO_PADS_LEF exists)
+ set ml $::env(TMP_DIR)/merged.$arg_values(-corner).lef
+ set ml_relative [relpath . $ml]
+ if { $::env(USE_GPIO_PADS) } {
+ if { [info exists ::env(USE_GPIO_ROUTING_LEF)] && $::env(USE_GPIO_ROUTING_LEF)} {
+ set ::env(GPIO_PADS_LEF) $::env(GPIO_PADS_LEF_CORE_SIDE)
+ }
+
+ puts_verbose "Merging the following GPIO LEF views: $::env(GPIO_PADS_LEF)..."
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py\
+ -o $ml\
+ -i $mlu {*}$::env(GPIO_PADS_LEF)
+ puts_verbose "Created '$ml_relative' with gpio pads."
+ } else {
+ file copy -force $mlu $ml
+ puts_verbose "Created '$ml_relative' unaltered."
+ }
+
+ set ::env($arg_values(-env_var)_UNPADDED) $mlu
+ set ::env($arg_values(-env_var)) $ml
+
+ if { ![info exists flags_map(-no_widen)] } {
+ widen_site_width
+ use_widened_lefs
+ }
+}
+
+proc gen_exclude_list {args} {
+ puts_verbose "Generating cell exclude list..."
+ set options {
+ {-lib required}
+ {-drc_exclude_list optional}
+ {-synth_exclude_list optional}
+ {-output optional}
+ }
+ set flags {
+ -drc_exclude_only
+ -create_dont_use_list
+ }
+ parse_key_args "gen_exclude_list" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-drc_exclude_list) $::env(DRC_EXCLUDE_CELL_LIST)
+ set_if_unset arg_values(-synth_exclude_list) $::env(NO_SYNTH_CELL_LIST)
+ set_if_unset arg_values(-output) $arg_values(-lib).exclude.list
+
+ # Copy the drc exclude list into the run directory, if it exists.
+ foreach list_file $arg_values(-drc_exclude_list) {
+ set out [open $arg_values(-output) a]
+ if { [file exists $list_file] } {
+ set in [open $list_file]
+ fcopy $in $out
+ close $in
+ }
+ close $out
+ }
+
+ # If you're not told to only use the drc exclude list, and if the no_synth.cells exists, merge the two lists
+ if { (![info exists flags_map(-drc_exclude_only)]) && [file exists $arg_values(-synth_exclude_list)] } {
+ set out [open $arg_values(-output) a]
+ set in [open $arg_values(-synth_exclude_list)]
+ fcopy $in $out
+ close $in
+ close $out
+ }
+
+ if { [file exists $arg_values(-output)] && [info exists flags_map(-create_dont_use_list)] } {
+ puts_verbose "Creating ::env(DONT_USE_CELLS)..."
+ set x [cat "$arg_values(-output)"]
+ set y [split $x]
+ set ::env(DONT_USE_CELLS) [join $y " "]
+ }
+
+
+}
+
+proc trim_lib {args} {
+ puts_verbose "Trimming Liberty..."
+ set options {
+ {-input optional}
+ {-output optional}
+ }
+ set flags {
+ -drc_exclude_only
+ }
+ parse_key_args "trim_lib" args arg_values $options flags_map $flags
+ set_if_unset arg_values(-input) $::env(LIB_SYNTH_COMPLETE)
+ set_if_unset arg_values(-output) $::env(LIB_SYNTH)
+
+ if { [info exists flags_map(-drc_exclude_only)] } {
+ gen_exclude_list -lib $arg_values(-output) -drc_exclude_only
+ } else {
+ gen_exclude_list -lib $arg_values(-output)
+ }
+
+ # Trim the liberty with the generated list, if it exists.
+ if { ! [file exists $arg_values(-output).exclude.list] } {
+ set fid [open $arg_values(-output).exclude.list w]
+ close $fid
+ }
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/libtrim.py\
+ --cell-file $arg_values(-output).exclude.list\
+ --output $arg_values(-output)\
+ $arg_values(-input)
+}
+
+proc source_config {config_file} {
+ puts_info "Sourcing Configurations from $config_file"
+ if { ![file exists $config_file] } {
+ puts_err "Configuration file $config_file not found"
+ return -code error
+ }
+ if { [file extension $config_file] == ".tcl" } {
+ # for trusted end-users only
+ source $config_file
+ } elseif { [file extension $config_file] == ".json" } {
+ set config_content [cat $config_file]
+
+ if { [catch {json::json2dict "$config_content"} config_dict] } {
+ puts_err "Failed to parse JSON file $config_file"
+ return -code error
+ }
+ dict for {config_key config_value} $config_dict {
+ # TODO after refactor: check if config_key is a valid configuration
+ set ::env($config_key) $config_value
+ }
+ } else {
+ puts_err "Configuration file $config_file with invalid extension"
+ return -code error
+ }
+
+ return -code ok
+}
+
+proc prep {args} {
+
+ set ::env(timer_start) [clock seconds]
+ TIMER::timer_start
+ set options {
+ {-design required}
+ {-tag optional}
+ {-config_tag optional}
+ {-config_file optional}
+ {-run_path optional}
+ {-src optional}
+ {-override_env optional}
+ {-verbose optional}
+ }
+
+ set flags {
+ -init_design_config
+ -overwrite
+ -last_run
+ }
+
+ set args_copy $args
+ parse_key_args "prep" args arg_values $options flags_map $flags
+
+ # Storing the current state of environment variables
+ set ::env(INIT_ENV_VAR_ARRAY) [split [array names ::env] " "]
+
+ if { [info exists arg_values(-config_tag)] } {
+ if { [info exists arg_values(-config_file)] } {
+ puts_err "Cannot specify both -config_tag and -config_file"
+ return -code error
+ }
+ set config_tag $arg_values(-config_tag)
+ } else {
+ set config_tag "config"
+ }
+ set src_files ""
+
+ set ::env(DESIGN_DIR) [file normalize $arg_values(-design)]
+ if { ![file exists $::env(DESIGN_DIR)] } {
+ set ::env(DESIGN_DIR) [file normalize $::env(OPENLANE_ROOT)/designs/$arg_values(-design)]
+ }
+
+ if { [info exists flags_map(-init_design_config)] } {
+ set config_tag "config"
+ if { [info exists arg_values(-tag) ] } {
+ set config_tag $arg_values(-tag)
+ }
+
+ if { [info exists arg_values(-src) ] } {
+ set src_files $arg_values(-src)
+ }
+
+ init_design $arg_values(-design) $config_tag $src_files
+ puts_success "Done..."
+ exit 0
+ }
+
+ set_if_unset arg_values(-verbose) "0"
+ set ::env(OPENLANE_VERBOSE) $arg_values(-verbose)
+
+
+ set ::env(TERMINAL_OUTPUT) "/dev/null"
+ if { $::env(OPENLANE_VERBOSE) >= 2 } {
+ set ::env(TERMINAL_OUTPUT) ">&@stdout"
+ }
+
+ set ::env(START_TIME) [clock format [clock seconds] -format %Y.%m.%d_%H.%M.%S ]
+
+ if { [info exists flags_map(-last_run)] } {
+ if { [info exists arg_values(-tag)] } {
+ puts_err "Cannot specify a tag with -last_run set."
+ return -code error
+ }
+
+ set arg_values(-tag) [exec python3 ./scripts/most_recent_run.py $::env(DESIGN_DIR)/runs]
+ }
+
+ set_if_unset arg_values(-tag) "RUN_$::env(START_TIME)"
+ set tag $arg_values(-tag)
+
+
+ set ::env(CONFIGS) [glob $::env(OPENLANE_ROOT)/configuration/*.tcl]
+
+ if { [info exists arg_values(-config_file)] } {
+ set ::env(DESIGN_CONFIG) $arg_values(-config_file)
+ } else {
+ if { [file exists $::env(DESIGN_DIR)/$config_tag.tcl] } {
+ set ::env(DESIGN_CONFIG) $::env(DESIGN_DIR)/$config_tag.tcl
+ } else {
+ set ::env(DESIGN_CONFIG) $::env(DESIGN_DIR)/$config_tag.json
+ }
+ }
+
+ if { ! [file exists $::env(DESIGN_CONFIG)] } {
+ puts_err "No design configuration found at $::env(DESIGN_CONFIG)"
+ return -code error
+ }
+
+ puts_info "Using design configuration at $::env(DESIGN_CONFIG)"
+
+ foreach config $::env(CONFIGS) {
+ source $config
+ }
+
+ # needs to be sourced first since it can choose to determine the PDK and SCL
+ source_config $::env(DESIGN_CONFIG)
+
+ if { [info exists arg_values(-override_env)] } {
+ set env_overrides [split $arg_values(-override_env) ',']
+ foreach override $env_overrides {
+ set kva [split $override '=']
+ set key [lindex $kva 0]
+ set value [lindex $kva 1]
+ set ::env(${key}) $value
+ }
+ }
+
+
+ # DEPRECATED PDK_VARIANT
+ handle_deprecated_config PDK_VARIANT STD_CELL_LIBRARY
+
+ # Diagnostics
+ if { ! [info exists ::env(PDK_ROOT)] || $::env(PDK_ROOT) == "" } {
+ puts_err "PDK_ROOT is not specified. Please make sure you have it set."
+ return -code error
+ } else {
+ puts_info "PDKs root directory: $::env(PDK_ROOT)"
+ }
+
+ if { ! [info exists ::env(PDK)] } {
+ puts_err "PDK is not specified."
+ return -code error
+ } else {
+ puts_info "PDK: $::env(PDK)"
+ puts_info "Setting PDKPATH to $::env(PDK_ROOT)/$::env(PDK)"
+ set ::env(PDKPATH) $::env(PDK_ROOT)/$::env(PDK)
+ }
+
+ if { ! [info exists ::env(STD_CELL_LIBRARY)] } {
+ puts_err "STD_CELL_LIBRARY is not specified."
+ return -code error
+ } else {
+ puts_info "Standard Cell Library: $::env(STD_CELL_LIBRARY)"
+ }
+
+ if { ! [info exists ::env(STD_CELL_LIBRARY_OPT)] } {
+ set ::env(STD_CELL_LIBRARY_OPT) $::env(STD_CELL_LIBRARY)
+ puts_info "Optimization Standard Cell Library is set to: $::env(STD_CELL_LIBRARY_OPT)"
+ } else {
+ puts_info "Optimization Standard Cell Library: $::env(STD_CELL_LIBRARY_OPT)"
+ }
+
+ if {![info exists ::env(PDN_CFG)]} {
+ set ::env(PDN_CFG) $::env(SCRIPTS_DIR)/openroad/pdn_cfg.tcl
+ }
+
+ # source PDK and SCL specific configurations
+ set pdk_config $::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/config.tcl
+ set scl_config $::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/config.tcl
+ source $pdk_config
+
+ # Value set by PDK for some reason
+ if { [info exists ::env(GLB_RT_L1_ADJUSTMENT) ] } {
+ unset ::env(GLB_RT_L1_ADJUSTMENT)
+ }
+
+ source $scl_config
+
+ # needs to be resourced to make sure it overrides the above
+ source_config $::env(DESIGN_CONFIG)
+
+ # DEPRECATED CONFIGS
+ handle_deprecated_config LIB_MIN LIB_FASTEST;
+ handle_deprecated_config LIB_MAX LIB_SLOWEST;
+ handle_deprecated_config CELL_PAD_EXECLUDE CELL_PAD_EXCLUDE;
+ handle_deprecated_config ROUTING_OPT_ITERS DRT_OPT_ITERS;
+ handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO;
+ handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO;
+
+ if { [info exists arg_values(-run_path)] } {
+ set run_path "[file normalize $arg_values(-run_path)]/$tag"
+ } else {
+ set run_path $::env(DESIGN_DIR)/runs/$tag
+ }
+
+
+ #
+ ############################
+ # Prep directories and files
+ ############################
+ #
+ set ::env(RUN_TAG) "$tag"
+ set ::env(RUN_DIR) "$run_path"
+ set ::env(RESULTS_DIR) "$::env(RUN_DIR)/results"
+ set ::env(TMP_DIR) "$::env(RUN_DIR)/tmp"
+ set ::env(LOGS_DIR) "$::env(RUN_DIR)/logs"
+ set ::env(REPORTS_DIR) "$::env(RUN_DIR)/reports"
+ set ::env(GLB_CFG_FILE) "$::env(RUN_DIR)/config.tcl"
+
+ set skip_basic_prep 0
+
+ if { [file exists $::env(RUN_DIR)] } {
+ if { [info exists flags_map(-overwrite)] } {
+ puts_warn "Removing existing run at $::env(RUN_DIR)..."
+ after 1000
+ file delete -force $::env(RUN_DIR)
+ } elseif { ![info exists flags_map(-last_run)] } {
+ puts_warn "A run for $::env(DESIGN_NAME) with tag '$tag' already exists. Pass the -overwrite option to overwrite it."
+ after 1000
+ set skip_basic_prep 1
+ }
+ }
+
+
+ # file mkdir *ensures* they exists (no problem if they already do)
+ file mkdir $::env(RESULTS_DIR) $::env(TMP_DIR) $::env(LOGS_DIR) $::env(REPORTS_DIR)
+
+ puts_info "Current run directory is $::env(RUN_DIR)"
+
+ if { [file exists $::env(GLB_CFG_FILE)] } {
+ if { [info exists flags_map(-overwrite)] } {
+ puts_info "Removing $::env(GLB_CFG_FILE)"
+ file delete $::env(GLB_CFG_FILE)
+ } else {
+ puts_info "Sourcing $::env(GLB_CFG_FILE)\nAny changes to the DESIGN config file will NOT be applied"
+ source $::env(GLB_CFG_FILE)
+ if { [info exists ::env(CURRENT_DEF)] && $::env(CURRENT_DEF) != 0 } {
+ puts_info "Current DEF: $::env(CURRENT_DEF)."
+ puts_info "Use 'set_def file_name.def' if you'd like to change it."
+ }
+ after 1000
+ }
+ }
+
+
+ set run_subfolder_structure [list \
+ synthesis\
+ floorplan\
+ placement\
+ cts\
+ routing\
+ eco\
+ signoff
+ ]
+
+ foreach subfolder $run_subfolder_structure {
+
+ set ::env(${subfolder}_reports) $::env(REPORTS_DIR)/$subfolder
+ file mkdir $::env(${subfolder}_reports)
+
+ set ::env(${subfolder}_logs) $::env(LOGS_DIR)/$subfolder
+ file mkdir $::env(${subfolder}_logs)
+
+ set ::env(${subfolder}_tmpfiles) $::env(TMP_DIR)/$subfolder
+ file mkdir $::env(${subfolder}_tmpfiles)
+
+ set ::env(${subfolder}_results) $::env(RESULTS_DIR)/$subfolder
+ file mkdir $::env(${subfolder}_results)
+ }
+
+ set util $::env(FP_CORE_UTIL)
+ set density $::env(PL_TARGET_DENSITY)
+
+ # Fill config file
+ puts_verbose "Storing configs into config.tcl ..."
+ exec echo "# Run configs" > $::env(GLB_CFG_FILE)
+ set_log ::env(PDK_ROOT) $::env(PDK_ROOT) $::env(GLB_CFG_FILE) 1
+ foreach index [lsort [array names ::env]] {
+ if { $index != "INIT_ENV_VAR_ARRAY" } {
+ if { $index ni $::env(INIT_ENV_VAR_ARRAY) } {
+ set_log ::env($index) $::env($index) $::env(GLB_CFG_FILE) 1
+ }
+ }
+ }
+
+ # Process LEFs and LIB files
+ if { ! $skip_basic_prep } {
+ prep_lefs -tech_lef $::env(TECH_LEF) -corner nom -env_var MERGED_LEF
+
+ if { [info exists ::env(TECH_LEF_MIN)] } {
+ prep_lefs -tech_lef $::env(TECH_LEF_MIN) -corner min -env_var MERGED_LEF_MIN -no_widen
+ }
+ if { [info exists ::env(TECH_LEF_MAX)] } {
+ prep_lefs -tech_lef $::env(TECH_LEF_MAX) -corner max -env_var MERGED_LEF_MAX -no_widen
+ }
+
+ set ::env(LIB_SYNTH_COMPLETE) $::env(LIB_SYNTH)
+ # merge synthesis libraries
+ set ::env(LIB_SYNTH_MERGED) $::env(synthesis_tmpfiles)/merged.lib
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/mergeLib.py\
+ --output $::env(LIB_SYNTH_MERGED)\
+ --name $::env(PDK)_merged\
+ {*}$::env(LIB_SYNTH_COMPLETE)
+
+ # trim synthesis library
+ set ::env(LIB_SYNTH) $::env(synthesis_tmpfiles)/trimmed.lib
+ trim_lib -input $::env(LIB_SYNTH_MERGED)
+
+ # trim resizer library
+ if { ! [info exists ::env(LIB_RESIZER_OPT) ] } {
+ set ::env(LIB_RESIZER_OPT) [list]
+ foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ set fbasename [file rootname [file tail $lib]]
+ set lib_resizer $::env(synthesis_tmpfiles)/resizer_$fbasename.lib
+ file copy -force $lib $lib_resizer
+ lappend ::env(LIB_RESIZER_OPT) $lib_resizer
+ }
+
+ if { $::env(STD_CELL_LIBRARY_OPT) != $::env(STD_CELL_LIBRARY) } {
+ foreach lib $::env(LIB_SYNTH_OPT) {
+ set fbasename [file rootname [file tail $lib]]
+ set lib_resizer $::env(synthesis_tmpfiles)/resizer_opt_$fbasename.lib
+ file copy -force $lib $lib_resizer
+ lappend ::env(LIB_RESIZER_OPT) $lib_resizer
+ }
+ }
+ }
+
+ if { ! [info exists ::env(DONT_USE_CELLS)] } {
+ if { $::env(STD_CELL_LIBRARY_OPT) != $::env(STD_CELL_LIBRARY) } {
+ set drc_exclude_list "$::env(DRC_EXCLUDE_CELL_LIST) $::env(DRC_EXCLUDE_CELL_LIST_OPT)"
+ } else {
+ set drc_exclude_list "$::env(DRC_EXCLUDE_CELL_LIST)"
+ }
+ gen_exclude_list -lib resizer_opt -drc_exclude_list $drc_exclude_list -output $::env(synthesis_tmpfiles)/resizer_opt.exclude.list -drc_exclude_only -create_dont_use_list
+ }
+
+ if { $::env(USE_GPIO_PADS) } {
+ if { ! [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ set ::env(VERILOG_FILES_BLACKBOX) ""
+ }
+ if { [info exists ::env(GPIO_PADS_VERILOG)] } {
+ lappend ::env(VERILOG_FILES_BLACKBOX) {*}$::env(GPIO_PADS_VERILOG)
+ } else {
+ puts_warn "GPIO_PADS_VERILOG is not set; cannot read as a blackbox"
+ }
+ }
+ }
+
+ # Fill config file with special cases
+ if { ! [info exists ::env(SYNTH_MAX_TRAN)] } {
+ if { [info exists ::env(CLOCK_PERIOD)] } {
+ if { [info exists ::env(DEFAULT_MAX_TRAN)] } {
+ set ::env(SYNTH_MAX_TRAN) [expr min([expr {0.1*$::env(CLOCK_PERIOD)}], $::env(DEFAULT_MAX_TRAN))]
+ } else {
+ set ::env(SYNTH_MAX_TRAN) [expr {0.1*$::env(CLOCK_PERIOD)}]
+ }
+ } else {
+ set ::env(SYNTH_MAX_TRAN) 0
+ }
+ set_log ::env(SYNTH_MAX_TRAN) $::env(SYNTH_MAX_TRAN) $::env(GLB_CFG_FILE) 1
+ }
+ if { $::env(SYNTH_TOP_LEVEL) } {
+ set_log ::env(SYNTH_SCRIPT) "$::env(SCRIPTS_DIR)/yosys/synth_top.tcl" $::env(GLB_CFG_FILE) 0
+ }
+ set_log ::env(SYNTH_OPT) 0 $::env(GLB_CFG_FILE) 0
+ set_log ::env(PL_INIT_COEFF) 0.00002 $::env(GLB_CFG_FILE) 0
+ set_log ::env(PL_IO_ITER) 5 $::env(GLB_CFG_FILE) 0
+
+ if { ! [info exists ::env(CURRENT_DEF)] } {
+ set ::env(CURRENT_DEF) 0
+ set_log ::env(CURRENT_DEF) $::env(CURRENT_DEF) $::env(GLB_CFG_FILE) 1
+ }
+
+ if { ! [info exists ::env(CURRENT_GUIDE)] } {
+ set ::env(CURRENT_GUIDE) 0
+ set_log ::env(CURRENT_GUIDE) $::env(CURRENT_GUIDE) $::env(GLB_CFG_FILE) 1
+ }
+
+ if { ! [info exists ::env(CURRENT_INDEX)] } {
+ set ::env(CURRENT_INDEX) 0
+ set_log ::env(CURRENT_INDEX) $::env(CURRENT_INDEX) $::env(GLB_CFG_FILE) 1
+ }
+
+ if { ! [info exists ::env(CURRENT_NETLIST)] } {
+ set ::env(CURRENT_NETLIST) 0
+ set_log ::env(CURRENT_NETLIST) $::env(CURRENT_NETLIST) $::env(GLB_CFG_FILE) 1
+ }
+
+ if { ! [info exists ::env(PREV_NETLIST)] } {
+ set ::env(PREV_NETLIST) 0
+ set_log ::env(PREV_NETLIST) $::env(PREV_NETLIST) $::env(GLB_CFG_FILE) 1
+ }
+
+ if { [file exists $::env(PDK_ROOT)/$::env(PDK)/SOURCES] } {
+ file copy -force $::env(PDK_ROOT)/$::env(PDK)/SOURCES $::env(RUN_DIR)/PDK_SOURCES
+ }
+ if { [info exists ::env(OPENLANE_VERSION) ] } {
+ try_catch echo "openlane $::env(OPENLANE_VERSION)" > $::env(RUN_DIR)/OPENLANE_VERSION
+ }
+
+ # Convert Tracks
+ if { $::env(TRACKS_INFO_FILE) != "" } {
+ set tracks_processed $::env(routing_tmpfiles)/config.tracks
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/new_tracks.py -i $::env(TRACKS_INFO_FILE) -o $tracks_processed
+ set ::env(TRACKS_INFO_FILE_PROCESSED) $tracks_processed
+ }
+
+ if { [info exists ::env(EXTRA_GDS_FILES)] } {
+ puts_info "Looking for files defined in ::env(EXTRA_GDS_FILES) $::env(EXTRA_GDS_FILES) ..."
+ assert_files_exist $::env(EXTRA_GDS_FILES)
+ }
+
+
+ if [catch {exec python3 $::env(OPENLANE_ROOT)/dependencies/verify_versions.py} ::env(VCHECK_OUTPUT)] {
+ if { $::env(QUIT_ON_MISMATCHES) == "1" } {
+ puts_err $::env(VCHECK_OUTPUT)
+ puts_err "Please update your environment. OpenLane will now quit."
+ flow_fail
+ return -code error
+ }
+
+ puts_warn "OpenLane may not function properly: $::env(VCHECK_OUTPUT)"
+ }
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "openlane design prep"
+ return -code ok
+}
+
+proc padframe_gen {args} {
+ puts_info "Generating Padframe..."
+ set options {{-folder required}}
+ set flags {}
+ parse_key_args "padframe_gen" args arg_values $options flags_map $flags
+ set pf_src_tmp [file normalize $arg_values(-folder)]
+ #
+ set pfg_exec $::env(SCRIPTS_DIR)/padframe_generator.py
+ # set pf_src $::env(DESIGN_DIR)/src
+ # set pf_src_tmp $::env(TMP_DIR)/src
+ # file copy $pf_src $pf_src_tmp
+
+ fake_display_buffer
+
+ exec $pfg_exec -nogui -tech-path=$::env(PDK_ROOT)/$::env(PDK) \
+ -project-path=$pf_src_tmp -cfg \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $pf_src_tmp/pfg.log]
+ kill_display_buffer
+}
+
+proc padframe_gen_legacy {args} {
+ set pfg_exec $::env(SCRIPTS_DIR)/padframe_generator.py
+ set pf_src $::env(DESIGN_DIR)/src
+ set pf_src_tmp $::env(TMP_DIR)/src
+ file copy $pf_src $pf_src_tmp
+
+ fake_display_buffer
+
+ exec $pfg_exec -nogui -tech-path=$::env(PDK_ROOT)/$::env(PDK) \
+ -project-path=$pf_src_tmp -cfg \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $pf_src_tmp/pfg.log]
+ kill_display_buffer
+}
+
+
+proc save_views {args} {
+ set options {
+ {-lef_path optional}
+ {-mag_path optional}
+ {-maglef_path optional}
+ {-def_path optional}
+ {-gds_path optional}
+ {-verilog_path optional}
+ {-spice_path optional}
+ {-sdf_path optional}
+ {-spef_path optional}
+ {-sdc_path optional}
+ {-save_path optional}
+ }
+
+ set flags {}
+ parse_key_args "save_views" args arg_values $options flags_map $flags
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set path "[file normalize $arg_values(-save_path)]"
+ } else {
+ set path $::env(RESULTS_DIR)/final
+ }
+ puts_info "Saving final set of views in '$path'..."
+
+ if { [info exists arg_values(-lef_path)] } {
+ set destination $path/lef
+ file mkdir $destination
+ if { [file exists $arg_values(-lef_path)] } {
+ file copy -force $arg_values(-lef_path) $destination/$::env(DESIGN_NAME).lef
+ }
+ }
+
+ if { [info exists arg_values(-mag_path)] } {
+ set destination $path/mag
+ file mkdir $destination
+ if { [file exists $arg_values(-mag_path)] } {
+ file copy -force $arg_values(-mag_path) $destination/$::env(DESIGN_NAME).mag
+ }
+ }
+
+ if { [info exists arg_values(-maglef_path)] } {
+ set destination $path/maglef
+ file mkdir $destination
+ if { [file exists $arg_values(-maglef_path)] } {
+ file copy -force $arg_values(-maglef_path) $destination/$::env(DESIGN_NAME).mag
+ }
+ }
+
+ if { [info exists arg_values(-def_path)] } {
+ set destination $path/def
+ file mkdir $destination
+ if { [file exists $arg_values(-def_path)] } {
+ file copy -force $arg_values(-def_path) $destination/$::env(DESIGN_NAME).def
+ }
+ }
+
+ if { [info exists arg_values(-gds_path)] } {
+ set destination $path/gds
+ file mkdir $destination
+ if { [file exists $arg_values(-gds_path)] } {
+ file copy -force $arg_values(-gds_path) $destination/$::env(DESIGN_NAME).gds
+ }
+ }
+ if { [info exists arg_values(-verilog_path)] } {
+ set destination $path/verilog/gl
+ file mkdir $destination
+ if { [file exists $arg_values(-verilog_path)] } {
+ file copy -force $arg_values(-verilog_path) $destination/$::env(DESIGN_NAME).v
+ }
+ }
+
+ if { [info exists arg_values(-spice_path)] } {
+ set destination $path/spi/lvs
+ file mkdir $destination
+ if { [file exists $arg_values(-spice_path)] } {
+ file copy -force $arg_values(-spice_path) $destination/$::env(DESIGN_NAME).spice
+ }
+ }
+
+ if { [info exists arg_values(-spef_path)] } {
+ set destination $path/spef
+ file mkdir $destination
+ if { [file exists $arg_values(-spef_path)] } {
+ file copy -force $arg_values(-spef_path) $destination/$::env(DESIGN_NAME).spef
+ }
+ }
+
+ if { [info exists arg_values(-sdf_path)] } {
+ set destination $path/sdf
+ file mkdir $destination
+ if { [file exists $arg_values(-sdf_path)] } {
+ file copy -force $arg_values(-sdf_path) $destination/$::env(DESIGN_NAME).sdf
+ }
+ }
+
+ if { [info exists arg_values(-sdc_path)] } {
+ set destination $path/sdc
+ file mkdir $destination
+ if { [file exists $arg_values(-sdc_path)] } {
+ file copy -force $arg_values(-sdc_path) $destination/$::env(DESIGN_NAME).sdc
+ }
+ }
+}
+
+
+# to be done after detailed routing and run_magic_antenna_check
+proc heal_antenna_violators {args} {
+ # requires a pre-existing report containing a list of cells (-pins?)
+ # that need the real diode in place of the fake diode:
+ # => fixes the routed def
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ increment_index
+ TIMER::timer_start
+ puts_info "Healing Antenna Violators..."
+ if { $::env(USE_ARC_ANTENNA_CHECK) == 1 } {
+ #ARC specific
+ if { [info exists ::env(ANTENNA_CHECKER_LOG)] } {
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/extract_antenna_violators.py -i $::env(ANTENNA_CHECKER_LOG) -o [index_file $::env(routing_reports)/violators.txt]
+ } else {
+ puts_err "Ran heal_antenna_violators without running the antenna check first."
+ flow_fail
+ }
+ } else {
+ #Magic Specific
+ set report_file [open [index_file $::env(routing_reports)/antenna_violators.rpt] r]
+ set violators [split [string trim [read $report_file]]]
+ close $report_file
+ # may need to speed this up for extremely huge files using hash tables
+ exec echo $violators >> [index_file $::env(routing_reports)/violators.txt]
+ }
+ #replace violating cells with real diodes
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/fake_diode_replace.py -v [index_file $::env(routing_reports)/violators.txt] -d $::env(routing_results)/$::env(DESIGN_NAME).def -f $::env(FAKEDIODE_CELL) -t $::env(DIODE_CELL)
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "heal antenna violators - custom"
+ }
+}
+
+proc widen_site_width {args} {
+ set ::env(MERGED_LEF_UNPADDED_ORIGINAL) $::env(MERGED_LEF_UNPADDED)
+ set ::env(MERGED_LEF_ORIGINAL) $::env(MERGED_LEF)
+
+ if { $::env(WIDEN_SITE) == 1 && $::env(WIDEN_SITE_IS_FACTOR) == 1 } {
+ set ::env(MERGED_LEF_UNPADDED_WIDENED) $::env(MERGED_LEF_UNPADDED)
+ set ::env(MERGED_LEF_WIDENED) $::env(MERGED_LEF)
+ } else {
+ puts_info "Widenning Site Width..."
+ set ::env(MERGED_LEF_UNPADDED_WIDENED) $::env(TMP_DIR)/merged_unpadded_wider.lef
+ set ::env(MERGED_LEF_WIDENED) $::env(TMP_DIR)/merged_wider.lef
+ if { $::env(WIDEN_SITE_IS_FACTOR) == 1 } {
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/widen_site_lef.py -l $::env(MERGED_LEF_UNPADDED) -w $::env(WIDEN_SITE) -f -o $::env(MERGED_LEF_UNPADDED_WIDENED)
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/widen_site_lef.py -l $::env(MERGED_LEF) -w $::env(WIDEN_SITE) -f -o $::env(MERGED_LEF_WIDENED)
+
+ } else {
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/widen_site_lef.py -l $::env(MERGED_LEF_UNPADDED) -w $::env(WIDEN_SITE) -o $::env(MERGED_LEF_UNPADDED_WIDENED)
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/widen_site_lef.py -l $::env(MERGED_LEF) -w $::env(WIDEN_SITE) -o $::env(MERGED_LEF_WIDENED)
+ }
+ }
+}
+
+proc use_widened_lefs {args} {
+ if { $::env(WIDEN_SITE) != 1 || $::env(WIDEN_SITE_IS_FACTOR) != 1 } {
+ set ::env(MERGED_LEF_UNPADDED) $::env(MERGED_LEF_UNPADDED_WIDENED)
+ set ::env(MERGED_LEF) $::env(MERGED_LEF_WIDENED)
+ }
+}
+
+proc use_original_lefs {args} {
+ if { $::env(WIDEN_SITE) != 1 || $::env(WIDEN_SITE_IS_FACTOR) != 1 } {
+ set ::env(MERGED_LEF_UNPADDED) $::env(MERGED_LEF_UNPADDED_ORIGINAL)
+ set ::env(MERGED_LEF) $::env(MERGED_LEF_ORIGINAL)
+ }
+}
+
+
+proc label_macro_pins {args} {
+ TIMER::timer_start
+ puts_info "Labeling macro pins..."
+ set options {
+ {-lef required}
+ {-netlist_def required}
+ {-pad_pin_name optional}
+ {-output optional}
+ {-extra_args optional}
+ }
+ set flags {}
+ parse_key_args "label_macro_pins" args arg_values $options flags_map $flags
+
+ set output_def $::env(CURRENT_DEF)
+ set extra_args ""
+
+ if {[info exists arg_values(-output)]} {
+ set output_def $arg_values(-output)
+ }
+
+ if {[info exists arg_values(-extra_args)]} {
+ set extra_args $arg_values(-extra_args)
+ }
+
+ set_if_unset arg_values(-pad_pin_name) ""
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/label_macro_pins.py\
+ --lef $arg_values(-lef)\
+ --input-def $::env(CURRENT_DEF)\
+ --netlist-def $arg_values(-netlist_def)\
+ --pad-pin-name $arg_values(-pad_pin_name)\
+ -o $output_def\
+ {*}$extra_args |& tee [index_file $::env(signoff_logs)/label_macro_pins.log] $::env(TERMINAL_OUTPUT)
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "label macro pins - label_macro_pins.py"
+}
+
+
+proc write_verilog {filename args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Writing Verilog..."
+ set ::env(SAVE_NETLIST) $filename
+
+ set options {
+ {-def optional}
+ {-log optional}
+ }
+ set flags {
+ -canonical
+ }
+ parse_key_args "write_verilog" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-def) $::env(CURRENT_DEF)
+ set_if_unset arg_values(-log) /dev/null
+
+ set ::env(INPUT_DEF) $arg_values(-def)
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/write_verilog.tcl -indexed_log [index_file $arg_values(-log)]
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "write verilog - openroad"
+ if { [info exists flags_map(-canonical)] } {
+ yosys_rewrite_verilog $filename
+ }
+}
+
+proc set_layer_tracks {args} {
+ puts_info "Setting Layer Tracks..."
+ set options {
+ {-defFile required}
+ {-layer required}
+ {-valuesFile required}
+ {-originalFile required}
+ }
+ set flags {}
+ parse_key_args "set_layer_tracks" args arg_values $options flags_map $flags
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/set_layer_tracks.py -d $arg_values(-defFile) -l $arg_values(-layer) -v $arg_values(-valuesFile) -o $arg_values(-originalFile)
+
+}
+
+proc run_or_antenna_check {args} {
+ TIMER::timer_start
+ increment_index
+ puts_info "Running OpenROAD Antenna Rule Checker..."
+ set antenna_log [index_file $::env(signoff_logs)/antenna.log]
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/antenna_check.tcl -indexed_log $antenna_log
+ set ::env(ANTENNA_CHECKER_LOG) $antenna_log
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "antenna check - openroad"
+}
+
+proc run_antenna_check {args} {
+ puts_info "Running Antenna Checks..."
+ if { $::env(USE_ARC_ANTENNA_CHECK) == 1 } {
+ run_or_antenna_check
+ } else {
+ run_magic_antenna_check
+ }
+}
+
+proc or_gui {args} {
+ run_openroad_script -gui $::env(SCRIPTS_DIR)/openroad/gui.tcl
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/checkers.tcl b/openlane/scripts/tcl_commands/checkers.tcl
new file mode 100755
index 0000000..cb4e6ee
--- /dev/null
+++ b/openlane/scripts/tcl_commands/checkers.tcl
@@ -0,0 +1,270 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+
+proc check_assign_statements {args} {
+ set checker [count_matches assign $::env(synthesis_results).v]
+
+ if { $checker != 0 } {
+ puts_err "There are assign statements in the netlist"
+ flow_fail
+ } else {
+ puts_info "No assign statement in netlist"
+ }
+}
+
+proc check_synthesis_failure {args} {
+ set checker [catch {exec grep "\\\$" [index_file $::env(synthesis_reports)/2.stat.rpt]}]
+
+ if { ! $checker } {
+ puts_err "Synthesis failed"
+ flow_fail
+ }
+}
+
+proc check_timing_violations {args} {
+ if { [info exists ::env(LAST_TIMING_REPORT_TAG)] } {
+ set hold_report $::env(LAST_TIMING_REPORT_TAG).min.rpt
+ set setup_report $::env(LAST_TIMING_REPORT_TAG).max.rpt
+ set slew_report $::env(LAST_TIMING_REPORT_TAG).slew.rpt
+
+ foreach file [ list $hold_report $setup_report $slew_report] {
+ if {![file exist $file]} {
+ puts_err "File $file doesn't exist."
+ flow_fail
+ }
+ }
+
+ check_slew_violations -report_file $slew_report -corner "typical"
+ check_hold_violations -report_file $hold_report -corner "typical" -quit_on_vios [expr $::env(QUIT_ON_TIMING_VIOLATIONS) && $::env(QUIT_ON_HOLD_VIOLATIONS)]
+ check_setup_violations -report_file $setup_report -corner "typical" -quit_on_vios [expr $::env(QUIT_ON_TIMING_VIOLATIONS) && $::env(QUIT_ON_HOLD_VIOLATIONS)]
+ }
+}
+
+proc check_hold_violations {args} {
+ set options {
+ {-report_file required}
+ {-corner required}
+ {-quit_on_vios optional}
+ }
+ parse_key_args "check_hold_violations" args arg_values $options
+ set_if_unset arg_values(-quit_on_vios) 0
+ set report_file $arg_values(-report_file)
+ set quit_on_vios $arg_values(-quit_on_vios)
+ set corner $arg_values(-corner)
+
+ set checker [catch {exec grep "VIOLATED" $report_file }]
+ if { ! $checker } {
+ set report_file_relative [relpath . $report_file]
+ if { $quit_on_vios } {
+ puts_err "There are hold violations in the design at the $corner corner. Please refer to '$report_file_relative'."
+ flow_fail
+ } else {
+ puts_warn "There are hold violations in the design at the $corner corner. Please refer to '$report_file_relative'."
+ }
+ } else {
+ puts_info "There are no hold violations in the design at the $corner corner."
+ }
+}
+
+proc check_setup_violations {args} {
+ set options {
+ {-report_file required}
+ {-corner required}
+ {-quit_on_vios optional}
+ }
+ parse_key_args "check_setup_violations" args arg_values $options
+ set_if_unset arg_values(-quit_on_vios) 0
+ set report_file $arg_values(-report_file)
+ set quit_on_vios $arg_values(-quit_on_vios)
+ set corner $arg_values(-corner)
+
+ set checker [catch {exec grep "VIOLATED" $report_file }]
+ if { ! $checker } {
+ set report_file_relative [relpath . $report_file]
+ if { $quit_on_vios } {
+ puts_err "There are setup violations in the design at the $corner corner. Please refer to '$report_file_relative'."
+ flow_fail
+ } else {
+ puts_warn "There are setup violations in the design at the $corner corner. Please refer to '$report_file_relative'."
+ }
+ } else {
+ puts_info "There are no setup violations in the design at the $corner corner."
+ }
+}
+
+proc check_slew_violations {args} {
+ set options {
+ {-report_file required}
+ {-corner required}
+ {-quit_on_vios optional}
+ }
+ parse_key_args "check_slew_violations" args arg_values $options
+ set_if_unset arg_values(-quit_on_vios) 0
+ set report_file $arg_values(-report_file)
+ set quit_on_vios $arg_values(-quit_on_vios)
+ set corner $arg_values(-corner)
+
+ set checker [catch {exec grep "VIOLATED" $report_file }]
+ if { ! $checker } {
+ set report_file_relative [relpath . $report_file]
+ if { $quit_on_vios } {
+ puts_err "There are max slew violations in the design at the $corner corner. Please refer to '$report_file_relative'."
+ flow_fail
+ } else {
+ puts_warn "There are max slew violations in the design at the $corner corner. Please refer to '$report_file_relative'."
+ }
+ } else {
+ puts_info "There are no max slew violations in the design at the $corner corner."
+ }
+}
+
+proc check_floorplan_missing_lef {args} {
+ set checker [catch {exec grep -E -o "module \[^\[:space:]]+ not found" [index_file $::env(floorplan_logs)/initial_fp.log]} missing_lefs]
+
+ if { ! $checker } {
+ puts_err "Floorplanning failed"
+ set lines [split $missing_lefs "\n"]
+ foreach line $lines {
+ puts_err "$line in $::env(MERGED_LEF)"
+ }
+ puts_err "Check whether EXTRA_LEFS is set appropriately"
+ flow_fail
+ }
+}
+
+proc check_floorplan_missing_pins {args} {
+ set checker [catch {exec grep -E -o "instance \[^\[:space:]]+ port \[^\[:space:]]+ not found" [index_file $::env(floorplan_logs)/openroad.log]} mismatches]
+
+ if { ! $checker } {
+ set lines [split $mismatches "\n"]
+ foreach line $lines {
+ puts_err "$line in $::env(MERGED_LEF)"
+ }
+ puts_err "Check whether EXTRA_LEFS is set appropriately and if they have the referenced pins."
+ flow_fail
+ }
+}
+
+proc check_cts_clock_nets {args} {
+ set checker [catch {exec grep -E -o "Error: No clock nets have been found." [index_file $::env(cts_logs)/cts.log]} error]
+
+ if { ! $checker } {
+ puts_err "Clock Tree Synthesis failed"
+ puts_err $error
+ puts_err "TritonCTS failed to find clock nets and/or sinks in the design; check whether the synthesized netlist contains flip-flops."
+ flow_fail
+ }
+}
+
+proc check_replace_divergence {args} {
+ set checker [catch {exec grep -E -o "RePlAce diverged. Please tune the parameters again" [index_file $::env(placement_logs)/global.log]} error]
+
+ if { ! $checker } {
+ puts_err "Global placement failed"
+ puts_err $error
+ flow_fail
+ }
+}
+
+proc check_macro_placer_num_solns {args} {
+ set checker [catch {exec grep -E -o "NumFinalSols = 0" [index_file $::env(placement_logs)/basic_mp.log]} error]
+
+ if { ! $checker } {
+ puts_err "Macro placement failed"
+ puts_err "$error; you may need to adjust the HALO"
+ flow_fail
+ }
+}
+
+proc quit_on_tr_drc {args} {
+ if { [info exists ::env(QUIT_ON_TR_DRC)] && $::env(QUIT_ON_TR_DRC) } {
+ set checker [count_matches violation $::env(routing_reports)/detailed.drc]
+
+ if { $checker != 0 } {
+ puts_err "There are violations in the design after detailed routing."
+ puts_err "Total Number of violations is $checker"
+ flow_fail
+ } else {
+ puts_info "No DRC violations after detailed routing."
+ }
+ }
+}
+
+proc quit_on_magic_drc {args} {
+ if { [info exists ::env(QUIT_ON_MAGIC_DRC)] && $::env(QUIT_ON_MAGIC_DRC) } {
+ set options {
+ {-log required}
+ }
+ parse_key_args "quit_on_magic_drc" args arg_values $options
+
+ set checker [count_matches violation $arg_values(-log)]
+
+ if { $checker != 0 } {
+ puts_err "There are violations in the design after Magic DRC."
+ puts_err "Total Number of violations is $checker"
+ flow_fail
+ } else {
+ puts_info "No DRC violations after GDS streaming out."
+ }
+ }
+}
+
+proc quit_on_lvs_error {args} {
+ if { [info exists ::env(QUIT_ON_LVS_ERROR)] && $::env(QUIT_ON_LVS_ERROR) } {
+ set options {
+ {-log required}
+ }
+ parse_key_args "quit_on_lvs_error" args arg_values $options
+ set checker [catch {exec grep -E -o "Total errors = 0" $arg_values(-log)} error]
+
+ if { $checker != 0 } {
+ set log_relative [relpath . $arg_values(-log)]
+ puts_err "There are LVS errors in the design: See '$log_relative' for details."
+ flow_fail
+ }
+ }
+}
+
+proc quit_on_illegal_overlaps {args} {
+ if { [info exists ::env(QUIT_ON_ILLEGAL_OVERLAPS)] && $::env(QUIT_ON_ILLEGAL_OVERLAPS) } {
+ set options {
+ {-log required}
+ }
+ parse_key_args "quit_on_illegal_overlaps" args arg_values $options
+
+ set checker [catch {exec grep -E -o "Illegal overlap" $arg_values(-log)} error]
+ if { ! $checker } {
+ puts_err "There are illegal overlaps (e.g., routes over obstructions) in your design."
+ puts_err "See $arg_values(-log) for more."
+ flow_fail
+ }
+ }
+}
+
+proc quit_on_unconnected_pdn_nodes {args} {
+ set log_file [index_file $::env(floorplan_logs)/pdn.log]
+ set checker [catch {exec grep -E "Unconnected PDN node" $log_file} error]
+
+ if { ! $checker } {
+ puts_err "PDN generation failed."
+ puts_err "You may need to adjust your macro placements or PDN \
+ offsets/pitches to power all standard cell rails (or other PDN stripes) \
+ in your design."
+ flow_fail
+ }
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/cts.tcl b/openlane/scripts/tcl_commands/cts.tcl
new file mode 100755
index 0000000..14ef44a
--- /dev/null
+++ b/openlane/scripts/tcl_commands/cts.tcl
@@ -0,0 +1,125 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+global script_path
+set script_path [ file dirname [ file normalize [ info script ] ] ]
+
+proc simple_cts {args} {
+ puts_info "Running Simple CTS..."
+ set options {
+ {-verilog required}
+ {-fanout required}
+ {-clk_net required}
+ {-root_clk_buf required}
+ {-clk_buf required}
+ {-clk_buf_input required}
+ {-clk_buf_output required}
+ {-cell_clk_port required}
+ {-output required}
+ }
+ parse_key_args "simple_cts" args values $options
+ global script_path
+ set tmp $::env(synthesis_tmpfiles)/$::env(DESIGN_NAME).v
+ file copy -force $values(-verilog) $tmp
+ set script $script_path/../simple_cts.py
+ #set values(-clk_net) [string map {\\ \\\\} $values(-clk_net)]
+ try_catch $::env(OPENROAD_BIN) -python $script \
+ --fanout $values(-fanout) \
+ --clk-net $values(-clk_net) \
+ --root-clkbuf $values(-root_clk_buf) \
+ --clkbuf $values(-clk_buf) \
+ --clkbuf-input-pin $values(-clk_buf_input) \
+ --clkbuf-output-pin $values(-clk_buf_output) \
+ --clk-port $values(-cell_clk_port) \
+ --output $values(-output) \
+ $tmp
+}
+
+
+proc run_cts {args} {
+ if { ! [info exists ::env(CLOCK_PORT)] && ! [info exists ::env(CLOCK_NET)] } {
+ puts_info "::env(CLOCK_PORT) is not set"
+ puts_warn "Skipping CTS..."
+ set ::env(CLOCK_TREE_SYNTH) 0
+ }
+
+ if {$::env(CLOCK_TREE_SYNTH) && !$::env(RUN_SIMPLE_CTS)} {
+ increment_index
+ puts_info "Running Clock Tree Synthesis..."
+ set ::env(CURRENT_STAGE) cts
+ TIMER::timer_start
+
+ if { ! [info exists ::env(CLOCK_NET)] } {
+ set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+ }
+
+ set ::env(SAVE_DEF) $::env(cts_results)/$::env(DESIGN_NAME).def
+ set ::env(SAVE_SDC) $::env(cts_results)/$::env(DESIGN_NAME).sdc
+ set report_tag_holder $::env(cts_reports)
+ set ::env(cts_reports) [ index_file $::env(cts_reports)/cts.rpt ]
+ # trim the lib to exclude cells with drc errors
+ if { ! [info exists ::env(LIB_CTS) ] } {
+ set ::env(LIB_CTS) $::env(cts_tmpfiles)/cts.lib
+ trim_lib -input $::env(LIB_SYNTH_COMPLETE) -output $::env(LIB_CTS) -drc_exclude_only
+ }
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/cts.tcl -indexed_log [index_file $::env(cts_logs)/cts.log]
+ check_cts_clock_nets
+ set ::env(cts_reports) $report_tag_holder
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "cts"
+
+ set_def $::env(SAVE_DEF)
+ set ::env(CURRENT_SDC) $::env(SAVE_SDC)
+ write_verilog $::env(cts_results)/$::env(DESIGN_NAME).v -log $::env(cts_logs)/write_verilog.log
+ set_netlist $::env(cts_results)/$::env(DESIGN_NAME).v
+ if { $::env(LEC_ENABLE) } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(cts_logs)/screenshot.log
+ } elseif { $::env(RUN_SIMPLE_CTS) } {
+ exec echo "Simple CTS was run earlier." >> [index_file $::env(cts_logs)/cts.log]
+ } else {
+ exec echo "SKIPPED!" >> [index_file $::env(cts_logs)/cts.log]
+ }
+
+}
+
+proc run_resizer_timing {args} {
+ if { $::env(PL_RESIZER_TIMING_OPTIMIZATIONS) == 1} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Placement Resizer Timing Optimizations..."
+ set ::env(SAVE_DEF) [index_file $::env(cts_tmpfiles)/resizer_timing.def]
+ set ::env(SAVE_SDC) [index_file $::env(cts_tmpfiles)/resizer_timing.sdc]
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer_timing.tcl -indexed_log [index_file $::env(cts_logs)/resizer.log]
+ set_def $::env(SAVE_DEF)
+ set ::env(CURRENT_SDC) $::env(SAVE_SDC)
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "resizer timing optimizations - openroad"
+
+ write_verilog $::env(cts_results)/$::env(DESIGN_NAME).resized.v -log $::env(cts_logs)/write_verilog.log
+ set_netlist $::env(cts_results)/$::env(DESIGN_NAME).resized.v
+
+ if { $::env(LEC_ENABLE) && [file exists $::env(PREV_NETLIST)] } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+
+ } else {
+ puts_info "Skipping Placement Resizer Timing Optimizations."
+ }
+}
+
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/cvc.tcl b/openlane/scripts/tcl_commands/cvc.tcl
new file mode 100755
index 0000000..8dddf35
--- /dev/null
+++ b/openlane/scripts/tcl_commands/cvc.tcl
@@ -0,0 +1,80 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+proc run_lef_cvc {args} {
+ if { $::env(RUN_CVC) != 1} {
+ puts_info "Skipping CVC..."
+ return
+ }
+
+ if { [info exists ::env(EXTRA_LEFS)] } {
+ puts_info "Your design contains macros, which is not supported by the current integration of CVC. So CVC won't run, however CVC is just a check so it's not critical to your design."
+ return
+ }
+
+ if { $::env(VDD_PIN) != $::env(VDD_NETS) || $::env(GND_PIN) != $::env(GND_NETS)} {
+ puts_info "Your design uses the advanced power settings, which is not supported by the current integration of CVC. So CVC won't run, however CVC is just a check so it's not critical to your design."
+ return
+ }
+
+ set ::env(CVC_SCRIPTS_DIR) $::env(SCRIPTS_DIR)/cvc/$::env(PDK)
+
+ if { ![file exist $::env(CVC_SCRIPTS_DIR)/cvcrc.$::env(PDK)] } {
+ puts_warn "This PDK does not support cvc, skipping..."
+ return
+ }
+
+ set lef_spice $::env(signoff_results)/$::env(DESIGN_NAME).lef.spice
+ if { ![file exist $lef_spice] } {
+ puts_warn "No lefspice found, skipping CVC..."
+ return
+ }
+
+ increment_index
+ TIMER::timer_start
+ puts_info "Running CVC..."
+
+ # merge cdl views of the optimization library and the base library if they are different
+ if { $::env(STD_CELL_LIBRARY_OPT) != $::env(STD_CELL_LIBRARY) } {
+ set lib_cdl $::env(qor_tempfiles)/merged.cdl
+ file copy -force $::env(STD_CELL_LIBRARY_CDL) $lib_cdl
+ set out [open $lib_cdl a]
+ set in [open $::env(STD_CELL_LIBRARY_OPT_CDL)]
+ fcopy $in $out
+ close $in
+ close $out
+ } else {
+ set lib_cdl $::env(STD_CELL_LIBRARY_CDL)
+ }
+
+ # Create power file
+ try_catch awk -v vdd=$::env(VDD_PIN) -v gnd=$::env(GND_PIN) \
+ -f $::env(CVC_SCRIPTS_DIR)/power.awk $::env(CURRENT_NETLIST) \
+ > $::env(signoff_tmpfiles)/$::env(DESIGN_NAME).power
+
+ # Create cdl file by combining cdl library with lef spice
+ try_catch awk -f $::env(CVC_SCRIPTS_DIR)/cdl.awk $lib_cdl $lef_spice \
+ > $::env(signoff_tmpfiles)/$::env(DESIGN_NAME).cdl
+
+ # The main event
+ try_catch cvc $::env(CVC_SCRIPTS_DIR)/cvcrc.$::env(PDK) \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/erc_screen.log]
+
+ TIMER::timer_stop
+
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "erc - cvc"
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/eco.tcl b/openlane/scripts/tcl_commands/eco.tcl
new file mode 100755
index 0000000..4f5b232
--- /dev/null
+++ b/openlane/scripts/tcl_commands/eco.tcl
@@ -0,0 +1,171 @@
+# Copyright 2021 The University of Michigan
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc insert_buffer {args} {
+ set options {
+ {-at_pin required}
+ {-buffer_cell required}
+ {-net_name optional}
+ {-inst_name optional}
+ }
+ set flags {-block -place}
+
+ parse_key_args "insert_buffer" args arg_values $options flags_map $flags
+
+ if { ![info exists ::env(INSERT_BUFFER_COUNTER)]} {
+ set ::env(INSERT_BUFFER_COUNTER) 0
+ }
+
+ set_if_unset arg_values(-net_name) "inserted_buffer_$::env(INSERT_BUFFER_COUNTER)_net"
+ set_if_unset arg_values(-inst_name) "inserted_buffer_$::env(INSERT_BUFFER_COUNTER)"
+
+ set pin_type "ITerm"
+ if { [info exists flags_map(-block)] } {
+ set pin_type "BTerm"
+ }
+
+ if { ![info exists flags_map(-place)] } {
+ set ::env(INSERT_BUFFER_NO_PLACE) "1"
+ }
+
+ set ::env(SAVE_DEF) [index_file $::env(eco_tmpfiles)/$::env(DESIGN_NAME).def]
+
+ set ::env(INSERT_BUFFER_COMMAND) "$arg_values(-at_pin) $pin_type $arg_values(-buffer_cell) $arg_values(-net_name) $arg_values(-inst_name)"
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/insert_buffer.tcl -indexed_log [index_file $::env(eco_logs)/insert_buffer.log]
+
+ unset ::env(INSERT_BUFFER_COMMAND)
+
+ if { ![info exists flags_map(-place)] } {
+ unset ::env(INSERT_BUFFER_NO_PLACE)
+ }
+
+
+ incr ::env(INSERT_BUFFER_COUNTER)
+
+ set_def $::env(SAVE_DEF)
+
+
+}
+
+proc eco_gen_buffer {args} {
+ # Generate fixes via the gen_insert_buffer Python script
+ # It reads in the LATEST multi-corner sta min report
+
+ set lef_file [lindex [glob -directory $::env(RUN_DIR)/tmp \
+ *_unpadded.lef] end]
+ set sta_file [lindex [glob -directory $::env(routing_logs) \
+ *multi_corner_sta*] end]
+
+ set files [glob -directory $::env(routing_logs) *multi_corner_sta*]
+ set newest 0
+ foreach f $files {
+ set mtime [file mtime $f]
+ if { $newest == 0 || $mtime > $newest } {
+ set newest $mtime
+ set sta_file $f
+ }
+ }
+
+ if { $::env(ECO_ITER) == 0 } {
+ set def_file [lindex [glob -directory $::env(eco_results)/arcdef \
+ $::env(ECO_ITER)_post-route.def] end]
+ } else {
+ set def_file [lindex [glob -directory $::env(eco_results)/def \
+ *.def] end]
+ }
+
+ puts_info "\[ECO: $::env(ECO_ITER)\] Generating buffer insertion script..."
+ puts_verbose "Using report $sta_file..."
+
+ try_catch $::env(OPENROAD_BIN) \
+ -python $::env(SCRIPTS_DIR)/gen_insert_buffer.py \
+ -s $::env(ECO_SKIP_PIN) \
+ -i $sta_file \
+ -l $lef_file \
+ -d $def_file \
+ -o $::env(eco_results)/fix/eco_fix_$::env(ECO_ITER).tcl
+}
+
+proc eco_output_check {args} {
+ puts_info "\[ECO: $::env(ECO_ITER)\] Checking output..."
+
+ eco_gen_buffer
+
+ set lines [split [cat "$::env(eco_results)/fix/eco_fix_$::env(ECO_ITER).tcl"] "\n"]
+ foreach line $lines {
+ # Use regex to determine if finished here
+ if {[regexp {No violations} $line]} {
+ puts_info "ECO done after [expr $::env(ECO_ITER) + 1] iterations."
+ set ::env(ECO_FINISH) 1;
+ } else {
+ puts_info "\[ECO: $::env(ECO_ITER)\] Timing violations found, performing another ECO iteration..."
+ incr ::env(ECO_ITER) 1;
+ }
+ break
+ }
+}
+
+proc run_apply_step {args} {
+ puts_info "\[ECO: $::env(ECO_ITER)\] Applying fixes..."
+ try_catch $::env(OPENROAD_BIN) \
+ -exit $::env(SCRIPTS_DIR)/openroad/eco.tcl \
+ |& tee $::env(TERMINAL_OUTPUT) $::env(eco_logs)/$::env(ECO_ITER)_eco.log
+
+ if { $::env(ECO_ITER) > 10 } {
+ pause;
+ }
+
+ set_netlist $::env(eco_results)/net/eco_$::env(ECO_ITER).v
+ set_def $::env(eco_results)/def/eco_$::env(ECO_ITER).def
+}
+
+proc run_eco_flow {args} {
+ # Assume script generate fix commands
+ puts_info "Starting ECO flow..."
+
+ # Re-organize report/result files here
+ exec sh $::env(SCRIPTS_DIR)/reorg_reports.sh
+ eco_output_check
+
+ while {$::env(ECO_FINISH) != 1} {
+
+ puts_info "\[ECO: $::env(ECO_ITER)\] Starting iteration..."
+ # Then run detailed placement again
+ # Get the connections then destroy them
+
+ # Pause to see puts output
+ if {$::env(ECO_ITER) > 10} {
+ puts_info "Ran for 10 itertations; Check files"
+ pause;
+ }
+
+ run_apply_step
+ run_routing
+ run_parasitics_sta\
+ -spef_out_prefix $::env(eco_results)/spef/$::env(ECO_ITER)_$::env(DESIGN_NAME)\
+ -sdf_out $::env(eco_results)/sdf/$::env(ECO_ITER)_$::env(DESIGN_NAME).sdf
+
+ ins_fill_cells
+
+ if { $::env(ECO_ITER) != 0 } {
+ set post_eco_net [lindex [glob -directory $::env(eco_results)/net *.v] end]
+ set post_eco_def [lindex [glob -directory $::env(eco_results)/def *.def] end]
+ file copy -force $post_eco_net $::env(synthesis_results)/$::env(DESIGN_NAME).synthesis_preroute.v
+ file copy -force $post_eco_def $::env(routing_results)/post_eco-$::env(DESIGN_NAME).def
+ }
+ }
+}
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/floorplan.tcl b/openlane/scripts/tcl_commands/floorplan.tcl
new file mode 100755
index 0000000..b9a8407
--- /dev/null
+++ b/openlane/scripts/tcl_commands/floorplan.tcl
@@ -0,0 +1,400 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+proc set_core_dims {args} {
+ puts_info "Setting Core Dimensions..."
+ set options {}
+ parse_key_args "set_core_dims" args values $options
+ set def_units $::env(DEF_UNITS_PER_MICRON)
+
+ set out_tmp $::env(TMP_DIR)/dimensions.txt
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py\
+ extract_core_dims\
+ --output-data $out_tmp\
+ --input-lef $::env(MERGED_LEF)\
+ $::env(CURRENT_DEF)
+
+ set dims [join [cat $out_tmp] " "]
+
+ set ::env(CORE_WIDTH) [lindex $dims 0]
+ set ::env(CORE_HEIGHT) [lindex $dims 1]
+}
+
+proc init_floorplan_or {args} {
+ handle_deprecated_command init_floorplan
+}
+
+proc init_floorplan {args} {
+ increment_index
+ puts_info "Running Initial Floorplanning..."
+ TIMER::timer_start
+ set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/initial_fp.def]
+ set ::env(SAVE_SDC) [index_file $::env(floorplan_tmpfiles)/initial_fp.sdc]
+
+ set ::env(fp_report_prefix) [index_file $::env(floorplan_reports)/initial_fp]
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/floorplan.tcl -indexed_log [index_file $::env(floorplan_logs)/initial_fp.log] -netlist_in
+
+ check_floorplan_missing_lef
+ check_floorplan_missing_pins
+
+ set die_area_file [open $::env(fp_report_prefix)_die_area.rpt]
+ set core_area_file [open $::env(fp_report_prefix)_core_area.rpt]
+
+ set ::env(DIE_AREA) [read $die_area_file]
+ set ::env(CORE_AREA) [read $core_area_file]
+
+ close $die_area_file
+ close $core_area_file
+
+ set core_width [expr {[lindex $::env(CORE_AREA) 2] - [lindex $::env(CORE_AREA) 0]}]
+ set core_height [expr {[lindex $::env(CORE_AREA) 3] - [lindex $::env(CORE_AREA) 1]}]
+
+ puts_verbose "Core area width: $core_width"
+ puts_verbose "Core area height: $core_height"
+
+ if { $::env(FP_PDN_AUTO_ADJUST) } {
+ if { $core_width <= [expr {$::env(FP_PDN_VOFFSET) + $::env(FP_PDN_VPITCH)}] ||\
+ $core_height <= [expr {$::env(FP_PDN_HOFFSET) + $::env(FP_PDN_HPITCH)}]} {
+ puts_warn "Current core area is too small for a power grid. The power grid will be minimized."
+
+ set ::env(FP_PDN_VOFFSET) [expr {$core_width/8.0}]
+ set ::env(FP_PDN_HOFFSET) [expr {$core_height/8.0}]
+
+ set ::env(FP_PDN_VPITCH) [expr {$core_width/4.0}]
+ set ::env(FP_PDN_HPITCH) [expr {$core_height/4.0}]
+ }
+
+ }
+
+ puts_verbose "Final Vertical PDN Offset: $::env(FP_PDN_VOFFSET)"
+ puts_verbose "Final Horizontal PDN Offset: $::env(FP_PDN_HOFFSET)"
+
+ puts_verbose "Final Vertical PDN Pitch: $::env(FP_PDN_VPITCH)"
+ puts_verbose "Final Horizontal PDN Pitch: $::env(FP_PDN_HPITCH)"
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "floorplan initialization - openroad"
+ set_def $::env(SAVE_DEF)
+ set ::env(CURRENT_SDC) $::env(SAVE_SDC)
+
+ set_core_dims
+}
+
+
+proc place_io_ol {args} {
+ increment_index
+ puts_info "Running IO Placement..."
+ TIMER::timer_start
+ set options {
+ {-lef optional}
+ {-def optional}
+ {-cfg optional}
+ {-horizontal_layer optional}
+ {-vertical_layer optional}
+ {-horizontal_mult optional}
+ {-horizontal_ext optional}
+ {-vertical_layer optional}
+ {-vertical_mult optional}
+ {-vertical_ext optional}
+ {-length optional}
+ {-output_def optional}
+ {-extra_args optional}
+ }
+ set flags {-unmatched_error optional}
+
+ parse_key_args "place_io_ol" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-lef) $::env(MERGED_LEF)
+ set_if_unset arg_values(-def) $::env(CURRENT_DEF)
+
+ set_if_unset arg_values(-cfg) $::env(FP_PIN_ORDER_CFG)
+
+ set_if_unset arg_values(-horizontal_layer) $::env(FP_IO_HLAYER)
+ set_if_unset arg_values(-vertical_layer) $::env(FP_IO_VLAYER)
+
+ set_if_unset arg_values(-vertical_mult) $::env(FP_IO_VTHICKNESS_MULT)
+ set_if_unset arg_values(-horizontal_mult) $::env(FP_IO_HTHICKNESS_MULT)
+
+ set_if_unset arg_values(-vertical_ext) $::env(FP_IO_VEXTEND)
+ set_if_unset arg_values(-horizontal_ext) $::env(FP_IO_HEXTEND)
+
+ set_if_unset arg_values(-length) [expr max($::env(FP_IO_VLENGTH), $::env(FP_IO_HLENGTH))]
+ set_if_unset arg_values(-output_def) [index_file $::env(floorplan_tmpfiles)/io.def]
+
+ if { $::env(FP_IO_UNMATCHED_ERROR) } {
+ set_if_unset flags_map(-unmatched_error) "--unmatched-error"
+ } else {
+ set_if_unset flags_map(-unmatched_error) ""
+ }
+ set_if_unset arg_values(-extra_args) ""
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/io_place.py\
+ --input-lef $arg_values(-lef)\
+ --config $arg_values(-cfg)\
+ --hor-layer $arg_values(-horizontal_layer)\
+ --ver-layer $arg_values(-vertical_layer)\
+ --ver-width-mult $arg_values(-vertical_mult)\
+ --hor-width-mult $arg_values(-horizontal_mult)\
+ --hor-extension $arg_values(-horizontal_ext)\
+ --ver-extension $arg_values(-vertical_ext)\
+ --length $arg_values(-length)\
+ {*}$flags_map(-unmatched_error)\
+ -o $arg_values(-output_def)\
+ {*}$arg_values(-extra_args)\
+ $arg_values(-def) |& tee [index_file $::env(floorplan_logs)/place_io_ol.log] $::env(TERMINAL_OUTPUT)
+
+ set_def $arg_values(-output_def)
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "ioplace - io_place.py"
+}
+
+proc place_io {args} {
+ increment_index
+ puts_info "Running IO Placement..."
+ TIMER::timer_start
+ set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/io.def]
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/ioplacer.tcl -indexed_log [index_file $::env(floorplan_logs)/io.log]
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "ioplace - openroad"
+ set_def $::env(SAVE_DEF)
+}
+
+proc place_contextualized_io {args} {
+ increment_index
+ puts_info "Running Contextualized IO Placement..."
+ set options {{-lef required} {-def required}}
+ set flags {}
+ parse_key_args "place_contextualized_io" args arg_values $options flags_map $flags
+
+ if {[file exists $arg_values(-def)] && [file exists $arg_values(-lef)]} {
+ TIMER::timer_start
+
+ file copy -force $arg_values(-def) $::env(placement_tmpfiles)/top_level.def
+ file copy -force $arg_values(-lef) $::env(placement_tmpfiles)/top_level.lef
+
+
+ set prev_def $::env(CURRENT_DEF)
+ set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/io.context.def]
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/contextualize.py \
+ -md $prev_def -ml $::env(MERGED_LEF_UNPADDED) \
+ -td $::env(placement_tmpfiles)/top_level.def -tl $::env(placement_tmpfiles)/top_level.lef \
+ -o $::env(SAVE_DEF) |& \
+ tee [index_file $::env(floorplan_logs)/io.contextualize.log]
+ puts_info "Custom floorplan created"
+
+ set_def $::env(SAVE_DEF)
+
+ set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/io.def]
+
+ set old_mode $::env(FP_IO_MODE)
+ set ::env(FP_IO_MODE) 0; # set matching mode
+ set ::env(CONTEXTUAL_IO_FLAG) 1
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/ioplacer.tcl -indexed_log [index_file $::env(floorplan_logs)/io.log]
+ set ::env(FP_IO_MODE) $old_mode
+
+ move_pins -from $::env(SAVE_DEF) -to $prev_def
+ set_def $prev_def
+
+ TIMER::timer_stop
+
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "ioplace - openroad (contextual)"
+
+ } else {
+ puts_err "Contextual IO placement: def/lef files don't exist, exiting"
+ return -code error
+ }
+}
+
+proc tap_decap_or {args} {
+ if { $::env(TAP_DECAP_INSERTION) } {
+ if {[info exists ::env(FP_WELLTAP_CELL)] && $::env(FP_WELLTAP_CELL) ne ""} {
+ increment_index
+ puts_info "Running Tap/Decap Insertion..."
+ TIMER::timer_start
+ set ::env(SAVE_DEF) $::env(floorplan_results)/$::env(DESIGN_NAME).def
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/tapcell.tcl -indexed_log [index_file $::env(floorplan_logs)/tap.log]
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "tap/decap insertion - openroad"
+ set_def $::env(SAVE_DEF)
+ } else {
+ puts_info "No tap cells found in this library. Skipping Tap/Decap Insertion."
+ }
+ } else {
+ puts_warn "Skipping Tap/Decap Insertion."
+ }
+}
+
+
+proc padframe_extract_area {args} {
+ puts_info "Extracting Padframe area..."
+ set options {{-cfg required}}
+ set flags {}
+ parse_key_args "padframe_extract_area" args arg_values $options flags_map $flags
+ set area [exec $::env(SCRIPTS_DIR)/padframe_extract_area.sh $arg_values(-cfg)]
+ return $area
+}
+
+proc chip_floorplan {args} {
+ puts_info "Running Chip Floorplanning..."
+ # intial fp
+ init_floorplan
+ # remove pins section and others
+ remove_pins -input $::env(CURRENT_DEF)
+ remove_empty_nets -input $::env(CURRENT_DEF)
+}
+
+proc apply_def_template {args} {
+ if { [info exists ::env(FP_DEF_TEMPLATE)] } {
+ set log [index_file $::env(floorplan_logs)/apply_def_template.log]
+ set def [index_file $::env(floorplan_tmpfiles)/apply_def_template.def]
+ puts_info "Applying DEF template. See log: $log"
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/apply_def_template.py\
+ --lef $::env(MERGED_LEF) \
+ --def-template $::env(FP_DEF_TEMPLATE)\
+ --log $log \
+ $::env(CURRENT_DEF)
+ }
+
+}
+
+proc run_power_grid_generation {args} {
+ if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
+ # they both must exist and be equal in length
+ # current assumption: they cannot have a common ground
+ if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
+ puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
+ return -code error
+ }
+ # standard cell power and ground nets are assumed to be the first net
+ set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
+ set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
+ } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+ set ::env(VDD_NETS) [list]
+ set ::env(GND_NETS) [list]
+ # get the pins that are in $synthesis_tmpfiles.pg_define.v
+ # that are not in $synthesis_results.v
+ #
+ set full_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_tmpfiles)/pg_define.v]
+ puts_info $full_pins
+
+ set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_results)/$::env(DESIGN_NAME).v]
+ puts_info $non_pg_pins
+
+ # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
+ foreach {vdd gnd} $full_pins {
+ if { $vdd ne "" && $vdd ni $non_pg_pins } {
+ lappend ::env(VDD_NETS) $vdd
+ }
+ if { $gnd ne "" && $gnd ni $non_pg_pins } {
+ lappend ::env(GND_NETS) $gnd
+ }
+ }
+ } else {
+ set ::env(VDD_NETS) $::env(VDD_PIN)
+ set ::env(GND_NETS) $::env(GND_PIN)
+ }
+
+ puts_info "Power planning with power {$::env(VDD_NETS)} and ground {$::env(GND_NETS)}..."
+
+ if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
+ puts_err "VDD_NETS and GND_NETS must be of equal lengths"
+ return -code error
+ }
+
+ # check internal macros' power connection definitions
+ if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+ set macro_hooks [dict create]
+ set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+ foreach pdn_hook $pdn_hooks {
+ set instance_name [lindex $pdn_hook 0]
+ set power_net [lindex $pdn_hook 1]
+ set ground_net [lindex $pdn_hook 2]
+ dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
+ }
+
+ set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
+ set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
+
+ # make sure that the specified power domains exist.
+ if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
+ puts_err "Can't find $power_net and $ground_net domain. \
+ Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
+ }
+ }
+
+ gen_pdn
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement f
+ } else {
+ global_placement_or
+ basic_macro_placement
+ }
+ }
+
+ tap_decap_or
+
+ scrot_klayout -layout $::env(CURRENT_DEF) $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/init_design.tcl b/openlane/scripts/tcl_commands/init_design.tcl
new file mode 100755
index 0000000..4cb7a52
--- /dev/null
+++ b/openlane/scripts/tcl_commands/init_design.tcl
@@ -0,0 +1,55 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+proc init_design {design_name config_tag src_files} {
+ set src "\$::env(DESIGN_DIR)/src"
+ set src_dir "$::env(DESIGN_DIR)/src"
+ set config_path "$::env(DESIGN_DIR)/$config_tag.tcl"
+ set base_config_path "$::env(DESIGN_DIR)/base_config.tcl"
+ puts_info "Creating design src directory $src_dir"
+ exec mkdir -p $src_dir
+ exec touch $config_path
+
+ puts_info "Populating $config_path.."
+
+ set config_user \
+"# User config
+set ::env(DESIGN_NAME) ${design_name}
+
+# Change if needed
+set ::env(VERILOG_FILES) \[glob $src/*.v\]
+
+# Fill this
+set ::env(CLOCK_PERIOD) \"10.0\"
+set ::env(CLOCK_PORT) \"clk\"
+
+set filename \$::env(DESIGN_DIR)/\$::env(PDK)_\$::env(STD_CELL_LIBRARY)_config.tcl
+if { \[file exists \$filename\] == 1} {
+ source \$filename
+}
+"
+ set config_file [open $config_path w]
+ puts $config_file $config_user
+ close $config_file
+
+ foreach src_file $src_files {
+ puts_info "Copying $src_file to $src_file"
+ file copy $src_file $src_dir
+ }
+
+ puts_info "Finished populating:\n$config_path \nPlease modify CLOCK_PORT, CLOCK_PERIOD and add your advanced settings to $config_path"
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/klayout.tcl b/openlane/scripts/tcl_commands/klayout.tcl
new file mode 100755
index 0000000..8fe17ce
--- /dev/null
+++ b/openlane/scripts/tcl_commands/klayout.tcl
@@ -0,0 +1,187 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc run_klayout {args} {
+ TIMER::timer_start
+ set ::env(CURRENT_STAGE) signoff
+ if {[ info exists ::env(KLAYOUT_TECH)] } {
+ increment_index
+ puts_info "Streaming out GDS-II with Klayout..."
+ set gds_files_in ""
+ if { [info exist ::env(EXTRA_GDS_FILES)] } {
+ set gds_files_in $::env(EXTRA_GDS_FILES)
+ }
+ if { $::env(STD_CELL_LIBRARY_OPT) != $::env(STD_CELL_LIBRARY) } {
+ set cells_gds "$::env(GDS_FILES) $::env(GDS_FILES_OPT)"
+ } else {
+ set cells_gds $::env(GDS_FILES)
+ }
+
+ set klayout_out $::env(signoff_results)/$::env(DESIGN_NAME).klayout.gds
+ try_catch klayout -b\
+ -rm $::env(SCRIPTS_DIR)/klayout/def2gds.py\
+ -rd out_gds=$klayout_out\
+ -rd tech_file=$::env(KLAYOUT_TECH)\
+ -rd design_name=$::env(DESIGN_NAME)\
+ -rd in_def=$::env(CURRENT_DEF)\
+ -rd "in_gds=$cells_gds $gds_files_in"\
+ -rd "config_file="\
+ -rd "seal_gds="\
+ -rd lef_file=$::env(MERGED_LEF)\
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/gdsii-klayout.log]
+
+
+ if {[info exists ::env(KLAYOUT_PROPERTIES)]} {
+ file copy -force $::env(KLAYOUT_PROPERTIES) $::env(signoff_results)/$::env(DESIGN_NAME).lyp
+ } else {
+ puts_warn "::env(KLAYOUT_PROPERTIES) is not defined. So, it won't be copied to the run directory."
+ }
+
+
+ if { $::env(PRIMARY_SIGNOFF_TOOL) == "klayout" } {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ file copy -force $klayout_out $::env(CURRENT_GDS)
+ }
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "gdsii - klayout"
+ scrot_klayout -layout $::env(signoff_results)/$::env(DESIGN_NAME).gds -log $::env(signoff_logs)/screenshot.klayout.log
+ } elseif { $::env(PRIMARY_SIGNOFF_TOOL) != "klayout" } {
+ puts_warn "::env(KLAYOUT_TECH) is not defined for the current PDK. So, GDS-II streaming out using Klayout will be skipped."
+ puts_warn "This warning can be turned off by setting ::env(RUN_KLAYOUT) to 0, or defining a tech file."
+ } else {
+ puts_err "::env(KLAYOUT_TECH) is not defined for the current PDK, however Klayout is set as the primary signoff tool. This is a critical error."
+ flow_fail
+ }
+
+}
+
+proc scrot_klayout {args} {
+ if {$::env(TAKE_LAYOUT_SCROT)} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Taking a Screenshot of the Layout Using Klayout..."
+ if {[ info exists ::env(KLAYOUT_TECH)] } {
+ set options {
+ {-log required}
+ {-layout optional}
+ }
+ parse_key_args "scrot_klayout" args arg_values $options
+ if {[info exists ::env(CURRENT_GDS)]} {
+ set_if_unset arg_values(-layout) $::env(CURRENT_GDS)
+ }
+ set log [index_file $arg_values(-log)]
+ try_catch bash $::env(SCRIPTS_DIR)/klayout/scrotLayout.sh $::env(KLAYOUT_TECH) $arg_values(-layout) |& tee $::env(TERMINAL_OUTPUT) $log
+ puts_info "Screenshot taken."
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "screenshot - klayout"
+ } elseif { $::env(PRIMARY_SIGNOFF_TOOL) != "klayout" } {
+ puts_warn "::env(KLAYOUT_DRC_TECH_SCRIPT) is not defined for the current PDK. So, GDS-II streaming out using Klayout will be skipped."
+ puts_warn "This warning can be turned off by setting ::env(RUN_KLAYOUT_DRC) to 0, or designating a tech file."
+ } else {
+ puts_err "::env(KLAYOUT_DRC_TECH_SCRIPT) is not defined for the current PDK, however Klayout is set as the primary signoff tool. This is a critical error."
+ flow_fail
+ }
+ }
+}
+
+proc run_klayout_drc {args} {
+ TIMER::timer_start
+ if {[ info exists ::env(KLAYOUT_DRC_TECH_SCRIPT)] && [file exists $::env(KLAYOUT_DRC_TECH_SCRIPT)]} {
+ increment_index
+ puts_info "Running DRC on the layout using Klayout..."
+ set options {
+ {-gds optional}
+ {-stage optional}
+ }
+ parse_key_args "run_klayout_drc" args arg_values $options
+ if {[info exists ::env(CURRENT_GDS)]} {
+ set_if_unset arg_values(-gds) $::env(CURRENT_GDS)
+ }
+ set_if_unset arg_values(-stage) magic
+ try_catch bash $::env(SCRIPTS_DIR)/klayout/run_drc.sh $::env(KLAYOUT_DRC_TECH_SCRIPT) $arg_values(-gds) $arg_values(-gds).lydrc |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/$arg_values(-stage).drc.log]
+ file copy -force $arg_values(-gds).lydrc [index_file $::env(signoff_reports)/$arg_values(-stage).lydrc]
+ puts_info "Klayout DRC Complete"
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "drc - klayout"
+ } elseif { $::env(PRIMARY_SIGNOFF_TOOL) != "klayout" } {
+ puts_warn "::env(KLAYOUT_DRC_TECH_SCRIPT) is not defined or doesn't exist for the current PDK. So, GDS-II streaming out using Klayout will be skipped."
+ puts_warn "This warning can be turned off by setting ::env(RUN_KLAYOUT_DRC) to 0, or designating a tech file."
+ } else {
+ puts_err "::env(KLAYOUT_DRC_TECH_SCRIPT) is not defined or doesn't exist for the current PDK, however Klayout is set as the primary signoff tool. This is a critical error."
+ flow_fail
+ }
+}
+
+proc run_klayout_gds_xor {args} {
+ increment_index
+ index_file $::env(signoff_logs)/xor.log
+ TIMER::timer_start
+ puts_info "Running XOR on the layouts using Klayout..."
+ set options {
+ {-layout1 optional}
+ {-layout2 optional}
+ {-output_xml optional}
+ {-output_gds optional}
+ }
+ parse_key_args "run_klayout_gds_xor" args arg_values $options
+ set_if_unset arg_values(-layout1) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ set_if_unset arg_values(-layout2) $::env(signoff_results)/$::env(DESIGN_NAME).klayout.gds
+ set_if_unset arg_values(-output_xml) $::env(signoff_reports)/$::env(DESIGN_NAME).xor.xml
+ set_if_unset arg_values(-output_gds) $::env(signoff_reports)/$::env(DESIGN_NAME).xor.gds
+ if { [file exists $arg_values(-layout1)]} {
+ if { [file exists $arg_values(-layout2)] } {
+ if { $::env(KLAYOUT_XOR_GDS) } {
+ try_catch bash $::env(SCRIPTS_DIR)/klayout/xor.sh \
+ $arg_values(-layout1) $arg_values(-layout2) $::env(DESIGN_NAME) \
+ $arg_values(-output_gds) \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/xor.log]
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/parse_klayout_xor_log.py \
+ -l [index_file $::env(signoff_logs)/xor.log] \
+ -o [index_file $::env(signoff_reports)/xor.rpt]
+ scrot_klayout -layout $arg_values(-output_gds) -log $::env(signoff_logs)/screenshot.klayout.xor.log
+ }
+
+ if { $::env(KLAYOUT_XOR_XML) } {
+ try_catch bash $::env(SCRIPTS_DIR)/klayout/xor.sh \
+ $arg_values(-layout1) $arg_values(-layout2) $::env(DESIGN_NAME) \
+ $arg_values(-output_xml) \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/xor.log]
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/parse_klayout_xor_log.py \
+ -l [index_file $::env(signoff_logs)/xor.log] \
+ -o [index_file $::env(signoff_reports)/xor.rpt]
+ }
+ } else {
+ puts_warn "$arg_values(-layout2) wasn't found. Skipping GDS XOR."
+ }
+ } else {
+ puts_warn "$arg_values(-layout1) wasn't found. Skipping GDS XOR."
+ }
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "xor - klayout"
+}
+
+proc open_in_klayout {args} {
+ set options {
+ {-layout optional}
+ }
+ parse_key_args "open_in_klayout" args arg_values $options
+
+ set_if_unset arg_values(-layout) $::env(CURRENT_DEF)
+
+ try_catch python3 $::env(SCRIPTS_DIR)/klayout/open_design_cmd.py\
+ $arg_values(-layout)
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/lvs.tcl b/openlane/scripts/tcl_commands/lvs.tcl
new file mode 100755
index 0000000..de57c9c
--- /dev/null
+++ b/openlane/scripts/tcl_commands/lvs.tcl
@@ -0,0 +1,182 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# WORKS ON VERILOG FILES
+proc verilog_to_verilogPower {args} {
+ puts_info "Adding Power Nets to Verilog..."
+ set options {
+ {-input required}
+ {-output required}
+ {-lef required}
+ {-power required}
+ {-ground required}
+ }
+ set flags {}
+ parse_key_args "verilog_to_verilogPower" args arg_values $options flags_map $flags
+ set bin vlog2Verilog
+ set in $arg_values(-input)
+ set out $arg_values(-output)
+ set power $arg_values(-power)
+ set gnd $arg_values(-ground)
+ set lef $arg_values(-lef)
+
+ try_catch $bin \
+ -v $power \
+ -g $gnd \
+ -l $lef \
+ $in |& tee $out
+}
+
+# WORKS ON DEF FILES
+proc write_powered_verilog {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Writing Powered Verilog..."
+ set options {
+ {-def optional}
+ {-lef optional}
+ {-power optional}
+ {-ground optional}
+ {-powered_netlist optional}
+ {-def_log optional}
+ {-output_def required}
+ {-output_verilog required}
+ }
+ set flags {}
+
+ parse_key_args "write_powered_verilog" args arg_values $options flags_map $flags
+ set_if_unset arg_values(-def) $::env(CURRENT_DEF)
+ set_if_unset arg_values(-power) $::env(VDD_PIN)
+ set_if_unset arg_values(-ground) $::env(GND_PIN)
+ set_if_unset arg_values(-lef) $::env(MERGED_LEF)
+ set_if_unset arg_values(-def_log) /dev/null
+ set_if_unset arg_values(-log) /dev/null
+
+
+ if { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+ set_if_unset arg_values(-powered_netlist) $::env(synthesis_tmpfiles)/pg_define.v
+ } else {
+ set_if_unset arg_values(-powered_netlist) ""
+ }
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/write_powered_def.py \
+ -d $arg_values(-def) \
+ -l $arg_values(-lef) \
+ --power-port $arg_values(-power) \
+ --ground-port $arg_values(-ground) \
+ --powered-netlist $arg_values(-powered_netlist) \
+ -o $arg_values(-output_def) \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $arg_values(-def_log)]
+
+ write_verilog $arg_values(-output_verilog) -def $arg_values(-output_def) -log [index_file $arg_values(-log)] -canonical
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "write powered verilog - openlane"
+}
+
+# "layout": a spice netlist
+# "schematic": a verilog netlist
+proc run_lvs {{layout "$::env(EXT_NETLIST)"}} {
+ # LEF LVS output to lvs.lef.log, design.lvs.lef.log, design.lvs.lef.json, design.lvs.lef.log
+ # GDS LVS output to lvs.gds.log, design.lvs.gds.log, design.lvs.gds.json, design.lvs.gds.log
+ # GDS LVS uses STD_CELL_LIBRARY spice and
+ # if defined, additional LVS_EXTRA_STD_CELL_LIBRARY spice and LVS_EXTRA_GATE_LEVEL_VERILOG files
+ # Write Netlist
+ if { $::env(LVS_INSERT_POWER_PINS) } {
+ set powered_netlist_name [index_file $::env(signoff_tmpfiles)/powered_netlist.v]
+ set powered_def_name [index_file $::env(signoff_tmpfiles)/powered_def.def]
+ write_powered_verilog\
+ -output_verilog $powered_netlist_name\
+ -output_def $powered_def_name\
+ -log $::env(signoff_logs)/write_verilog.log\
+ -def_log $::env(signoff_logs)/write_powered_def.log
+
+ set_netlist $powered_netlist_name
+
+ if { $::env(LEC_ENABLE) } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+ }
+
+ increment_index
+ TIMER::timer_start
+ if { [info exist ::env(MAGIC_EXT_USE_GDS)] && $::env(MAGIC_EXT_USE_GDS) } {
+ set extract_type gds
+ puts_info "Running GDS LVS..."
+ } else {
+ set extract_type lef
+ puts_info "Running LEF LVS..."
+ }
+
+
+ set schematic $::env(CURRENT_NETLIST)
+
+ set layout [subst $layout]
+
+ set setup_file $::env(NETGEN_SETUP_FILE)
+ set module_name $::env(DESIGN_NAME)
+ #writes setup_file_*_lvs to tmp directory.
+ set lvs_file_path [index_file $::env(signoff_tmpfiles)/setup_file.$extract_type.lvs]
+ set lvs_file [open $lvs_file_path w]
+ if { "$extract_type" == "gds" } {
+ if { [info exist ::env(LVS_EXTRA_STD_CELL_LIBRARY)] } {
+ set libs_in $::env(LVS_EXTRA_STD_CELL_LIBRARY)
+ foreach lib_file $libs_in {
+ puts $lvs_file "puts \"Reading spice netlist file $lib_file\""
+ puts $lvs_file "readnet spice $lib_file 1"
+ }
+ } else {
+ if { [info exist ::env(STD_CELL_LIBRARY)] } {
+ set std_cell_source $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/spice/$::env(STD_CELL_LIBRARY).spice
+ } else {
+ set std_cell_source $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+ }
+ puts $lvs_file "puts \"Reading spice netlist file $std_cell_source\""
+ puts $lvs_file "readnet spice $std_cell_source 1"
+ }
+ if { [info exist ::env(LVS_EXTRA_GATE_LEVEL_VERILOG)] } {
+ set libs_in $::env(LVS_EXTRA_GATE_LEVEL_VERILOG)
+ foreach lib_file $libs_in {
+ puts $lvs_file "puts \"Reading verilog netlist file $lib_file\""
+ puts $lvs_file "readnet verilog $lib_file 1"
+ }
+ }
+ }
+
+ set extraction_prefix [index_file $::env(signoff_logs)/$::env(DESIGN_NAME).$extract_type]
+
+ puts $lvs_file "lvs {$layout $module_name} {$schematic $module_name} $setup_file $extraction_prefix.log -json"
+ close $lvs_file
+
+ puts_verbose "$layout against $schematic"
+
+ try_catch netgen -batch source $lvs_file_path \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/$extract_type.log]
+
+ set count_lvs_log [index_file $::env(signoff_logs)/$::env(DESIGN_NAME).lvs.$extract_type.log]
+
+ exec python3 $::env(SCRIPTS_DIR)/count_lvs.py \
+ -f $extraction_prefix.json \
+ |& tee $::env(TERMINAL_OUTPUT) $count_lvs_log
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "lvs - netgen"
+ quit_on_lvs_error -log $count_lvs_log
+}
+
+proc run_netgen {args} {
+ handle_deprecated_command run_lvs
+}
+
+package provide openlane 0.9
+
diff --git a/openlane/scripts/tcl_commands/magic.tcl b/openlane/scripts/tcl_commands/magic.tcl
new file mode 100755
index 0000000..3969984
--- /dev/null
+++ b/openlane/scripts/tcl_commands/magic.tcl
@@ -0,0 +1,351 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc run_magic {args} {
+ TIMER::timer_start
+ increment_index
+ puts_info "Running Magic to generate various views..."
+ # |----------------------------------------------------|
+ # |---------------- 6. TAPE-OUT ---------------------|
+ # |----------------------------------------------------|
+ puts_info "Streaming out GDS-II with Magic..."
+ set ::env(CURRENT_STAGE) signoff
+ set ::env(PDKPATH) "$::env(PDK_ROOT)/$::env(PDK)"
+ # the following MAGTYPE better be mag for clean GDS generation
+ # use load -dereference to ignore it later if needed
+
+ set ::env(MAGTYPE) mag
+ # Generate GDS and MAG views
+ set ::env(MAGIC_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).magic.gds
+
+ try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $::env(SCRIPTS_DIR)/magic/mag_gds.tcl \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/gdsii.log]
+
+ if { $::env(PRIMARY_SIGNOFF_TOOL) == "magic" } {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ file copy -force $::env(MAGIC_GDS) $::env(CURRENT_GDS)
+ }
+
+ file copy -force $::env(MAGIC_MAGICRC) $::env(signoff_results)/.magicrc
+ # Take a PNG screenshot
+ scrot_klayout -log $::env(cts_logs)/screenshot.log
+
+ if { ($::env(MAGIC_GENERATE_LEF) && $::env(MAGIC_GENERATE_MAGLEF)) || $::env(MAGIC_INCLUDE_GDS_POINTERS) } {
+ puts_info "Generating MAGLEF views..."
+
+ # Generate mag file that includes GDS pointers
+ set ::env(MAGTYPE) mag
+ try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $::env(SCRIPTS_DIR)/magic/gds_pointers.tcl \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/gds_ptrs.log]
+ # Only keep the properties section in the file
+ try_catch sed -i -n "/^<< properties >>/,/^<< end >>/p" $::env(signoff_tmpfiles)/gds_ptrs.mag
+ }
+
+ # If desired, copy GDS_* properties into the mag/ view
+ if { $::env(MAGIC_INCLUDE_GDS_POINTERS) } {
+ copy_gds_properties $::env(signoff_tmpfiles)/gds_ptrs.mag $::env(signoff_results)/$::env(DESIGN_NAME).mag
+ }
+
+ if { $::env(MAGIC_GENERATE_LEF) } {
+ # Generate LEF view
+ set ::env(MAGTYPE) maglef
+ try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $::env(SCRIPTS_DIR)/magic/lef.tcl \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/lef.log]
+ if { $::env(MAGIC_GENERATE_MAGLEF) } {
+ # Generate MAGLEF view
+ set ::env(MAGTYPE) maglef
+ try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $::env(SCRIPTS_DIR)/magic/maglef.tcl \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/maglef.log]
+ # By default, copy the GDS properties into the maglef/ view
+ copy_gds_properties $::env(signoff_tmpfiles)/gds_ptrs.mag $::env(signoff_results)/$::env(DESIGN_NAME).lef.mag
+ }
+ }
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "gdsii - magic"
+}
+
+
+proc run_magic_drc {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Magic DRC..."
+
+ set ::env(PDKPATH) "$::env(PDK_ROOT)/$::env(PDK)"
+ set ::env(drc_prefix) $::env(signoff_reports)/drc
+ # Has to be maglef for DRC Checking
+ set ::env(MAGTYPE) maglef
+
+ try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $::env(SCRIPTS_DIR)/magic/drc.tcl \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/drc.log]
+
+ puts_info "Converting Magic DRC Violations to Magic Readable Format..."
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/magic_drc_to_tcl.py \
+ -i $::env(drc_prefix).rpt \
+ -o $::env(drc_prefix).tcl
+
+ puts_info "Converting Magic DRC Violations to Klayout XML Database..."
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/magic_drc_to_tr_drc.py \
+ -i $::env(drc_prefix).rpt \
+ -o $::env(drc_prefix).tr
+
+ puts_info "Converting TritonRoute DRC Violations to Klayout XML Database..."
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/tr_drc_to_klayout_drc.py \
+ -i $::env(drc_prefix).tr \
+ -o $::env(drc_prefix).klayout.xml \
+ --design-name $::env(DESIGN_NAME)
+
+ if { $::env(MAGIC_CONVERT_DRC_TO_RDB) == 1 } {
+ puts_info "Converting DRC Violations to RDB Format..."
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/magic_drc_to_rdb.py \
+ --magic_drc_in $::env(drc_prefix).rpt \
+ --rdb_out $::env(drc_prefix).rdb
+ }
+
+ file copy -force $::env(MAGIC_MAGICRC) $::env(signoff_results)/.magicrc
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "drc - magic"
+
+ quit_on_magic_drc -log $::env(drc_prefix).tr
+}
+
+proc run_magic_spice_export {args} {
+ TIMER::timer_start
+ increment_index
+ if { [info exist ::env(MAGIC_EXT_USE_GDS)] && $::env(MAGIC_EXT_USE_GDS) } {
+ set extract_type "gds.spice"
+ puts_info "Running Magic Spice Export from GDS..."
+ # GDS extracted file design.gds.spice, log file magic_gds.spice.log
+ } else {
+ set extract_type "spice"
+ puts_info "Running Magic Spice Export from LEF..."
+ # LEF extracted file design.spice (copied to design.lef.spice), log file magic_spice.log
+ }
+
+ set ::env(magic_extract_prefix) [index_file $::env(signoff_logs)/ext2]
+
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).$extract_type
+ set magic_export $::env(signoff_tmpfiles)/$extract_type.tcl
+ set commands \
+ "
+if { \[info exist ::env(MAGIC_EXT_USE_GDS)\] && \$::env(MAGIC_EXT_USE_GDS) } {
+ gds read \$::env(CURRENT_GDS)
+} else {
+ lef read $::env(TECH_LEF)
+ if { \[info exist ::env(EXTRA_LEFS)\] } {
+ set lefs_in \$::env(EXTRA_LEFS)
+ foreach lef_file \$lefs_in {
+ lef read \$lef_file
+ }
+ }
+ def read $::env(CURRENT_DEF)
+}
+load $::env(DESIGN_NAME) -dereference
+cd $::env(signoff_results)/
+extract do local
+extract no capacitance
+extract no coupling
+extract no resistance
+extract no adjust
+if { ! $::env(LVS_CONNECT_BY_LABEL) } {
+ extract unique
+}
+# extract warn all
+extract
+
+ext2spice lvs
+ext2spice -o $::env(EXT_NETLIST) $::env(DESIGN_NAME).ext
+feedback save $::env(magic_extract_prefix)$extract_type.feedback.txt
+# exec cp $::env(DESIGN_NAME).spice $::env(signoff_results)/$::env(DESIGN_NAME).spice
+"
+set magic_export_file [open $magic_export w]
+puts $magic_export_file $commands
+close $magic_export_file
+set ::env(PDKPATH) "$::env(PDK_ROOT)/$::env(PDK)/"
+# the following MAGTYPE has to be maglef for the purpose of LVS
+# otherwise underlying device circuits would be considered
+set ::env(MAGTYPE) maglef
+try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $magic_export \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/$extract_type.log]
+
+if { $extract_type == "spice" } {
+ file copy -force $::env(signoff_results)/$::env(DESIGN_NAME).spice $::env(signoff_results)/$::env(DESIGN_NAME).lef.spice
+}
+file rename -force {*}[glob $::env(signoff_results)/*.ext] $::env(signoff_tmpfiles)
+TIMER::timer_stop
+exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "$extract_type extraction - magic"
+
+quit_on_illegal_overlaps -log [index_file $::env(signoff_logs)/ext2$extract_type.feedback.txt]
+}
+
+proc export_magic_view {args} {
+ TIMER::timer_start
+ set options {
+ {-def required}
+ {-output required}
+ }
+ set flags {}
+ parse_key_args "export_magic_views" args arg_values $options flags_map $flags
+ set script_dir $::env(signoff_tmpfiles)/magic_mag_save.tcl
+ set commands \
+ "
+lef read $::env(TECH_LEF)
+if { \[info exist ::env(EXTRA_LEFS)\] } {
+ set lefs_in \$::env(EXTRA_LEFS)
+ foreach lef_file \$lefs_in {
+ lef read \$lef_file
+ }
+}
+def read $arg_values(-def)
+save $arg_values(-output)
+puts \"\[INFO\]: Done exporting $arg_values(-output)\"
+"
+set stream [open $script_dir w]
+puts $stream $commands
+close $stream
+set ::env(PDKPATH) "$::env(PDK_ROOT)/$::env(PDK)/"
+try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $script_dir \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(signoff_logs)/save_mag.log]
+TIMER::timer_stop
+exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "mag export - magic"
+}
+
+proc run_magic_antenna_check {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Magic Antenna Checks..."
+ set feedback_file [index_file $::env(signoff_logs)/ext2spice.antenna.feedback.txt]
+ set magic_export $::env(signoff_tmpfiles)/magic_antenna.tcl
+ set commands \
+ "
+lef read \$::env(TECH_LEF)
+if { \[info exist ::env(EXTRA_LEFS)\] } {
+ set lefs_in \$::env(EXTRA_LEFS)
+ foreach lef_file \$lefs_in {
+ lef read \$lef_file
+ }
+}
+def read \$::env(CURRENT_DEF)
+load \$::env(DESIGN_NAME) -dereference
+cd \$::env(signoff_tmpfiles)
+select top cell
+
+# for now, do extraction anyway; can be optimized by reading the maglef ext
+# but getting many warnings
+if { ! \[file exists \$::env(DESIGN_NAME).ext\] } {
+ extract do local
+ extract no capacitance
+ extract no coupling
+ extract no resistance
+ extract no adjust
+ if { ! $::env(LVS_CONNECT_BY_LABEL) } {
+ extract unique
+ }
+ # extract warn all
+ extract
+ feedback save $feedback_file
+}
+antennacheck debug
+antennacheck
+"
+set magic_export_file [open $magic_export w]
+puts $magic_export_file $commands
+close $magic_export_file
+set ::env(PDKPATH) "$::env(PDK_ROOT)/$::env(PDK)/"
+# the following MAGTYPE has to be mag; antennacheck needs to know
+# about the underlying devices, layers, etc.
+set ::env(MAGTYPE) mag
+
+set antenna_log [index_file $::env(signoff_logs)/antenna.log]
+try_catch magic \
+ -noconsole \
+ -dnull \
+ -rcfile $::env(MAGIC_MAGICRC) \
+ $magic_export \
+ </dev/null \
+ |& tee $::env(TERMINAL_OUTPUT) $antenna_log
+
+# process the log
+try_catch awk "/Cell:/ {print \$2}" $antenna_log > $antenna_log
+
+set ::env(ANTENNA_CHECKER_LOG) $antenna_log
+
+TIMER::timer_stop
+exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "antenna check - magic"
+
+}
+
+proc copy_gds_properties {from to} {
+ # copy GDS properties from $from to $to
+ set gds_properties [list]
+ set fp [open $from r]
+ set mag_lines [split [read $fp] "\n"]
+ foreach line $mag_lines {
+ if { [string first "string GDS_" $line] != -1 } {
+ lappend gds_properties $line
+ }
+ }
+ close $fp
+
+ set fp [open $to r]
+ set mag_lines [split [read $fp] "\n"]
+ set new_mag_lines [list]
+ foreach line $mag_lines {
+ if { [string first "<< end >>" $line] != -1 } {
+ lappend new_mag_lines [join $gds_properties "\n"]
+ }
+ lappend new_mag_lines $line
+ }
+ close $fp
+
+ set fp [open $to w]
+ puts $fp [join $new_mag_lines "\n"]
+ close $fp
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/pkgIndex.tcl b/openlane/scripts/tcl_commands/pkgIndex.tcl
new file mode 100755
index 0000000..7159528
--- /dev/null
+++ b/openlane/scripts/tcl_commands/pkgIndex.tcl
@@ -0,0 +1,25 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Tcl package index file, version 1.1
+# This file is generated by the "pkg_mkIndex" command
+# and sourced either when an application starts up or
+# by a "package unknown" script. It invokes the
+# "package ifneeded" command to set up package-related
+# information so that packages will be loaded automatically
+# in response to "package require" commands. When this
+# script is sourced, the variable $dir must contain the
+# full path name of this file's directory.
+
+package ifneeded openlane 0.9 [list source [file join $dir all.tcl]]\n[list source [file join $dir checkers.tcl]]\n[list source [file join $dir cts.tcl]]\n[list source [file join $dir floorplan.tcl]]\n[list source [file join $dir init_design.tcl]]\n[list source [file join $dir lvs.tcl]]\n[list source [file join $dir magic.tcl]]\n[list source [file join $dir placement.tcl]]\n[list source [file join $dir routing.tcl]]\n[list source [file join $dir synthesis.tcl]]\n[list source [file join $dir klayout.tcl]]\n[list source [file join $dir cvc.tcl]]\n[list source [file join $dir eco.tcl]]\n[list source [file join $dir sta.tcl]]
diff --git a/openlane/scripts/tcl_commands/placement.tcl b/openlane/scripts/tcl_commands/placement.tcl
new file mode 100755
index 0000000..79a2230
--- /dev/null
+++ b/openlane/scripts/tcl_commands/placement.tcl
@@ -0,0 +1,206 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc global_placement_or {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Global Placement..."
+ set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/global.def]
+
+ # random initial placement
+ if { $::env(PL_RANDOM_INITIAL_PLACEMENT) } {
+ random_global_placement
+ set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
+ }
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/replace.tcl -indexed_log [index_file $::env(placement_logs)/global.log]
+ # sometimes replace fails with a ZERO exit code; the following is a workaround
+ # until the cause is found and fixed
+ if { ! [file exists $::env(SAVE_DEF)] } {
+ puts_err "Failure in global placement"
+ return -code error
+ }
+
+ check_replace_divergence
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "global placement - openroad"
+ set_def $::env(SAVE_DEF)
+}
+
+proc global_placement {args} {
+ global_placement_or args
+}
+
+
+proc random_global_placement {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Performing Random Global Placement..."
+ set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/global.def]
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/random_place.py --lef $::env(MERGED_LEF_UNPADDED) \
+ --input-def $::env(CURRENT_DEF) --output-def $::env(SAVE_DEF) \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(placement_logs)/global.log]
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "global placement - random_place.py"
+ set_def $::env(SAVE_DEF)
+}
+
+proc detailed_placement_or {args} {
+ set options {
+ {-log required}
+ {-def required}
+ }
+ set flags {}
+ parse_key_args "detailed_placement_or" args arg_values $options flags_map $flags
+
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Detailed Placement..."
+ set ::env(SAVE_DEF) $arg_values(-def)
+ set log [index_file $arg_values(-log)]
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/opendp.tcl -indexed_log $log
+ set_def $::env(SAVE_DEF)
+
+ if {[catch {exec grep -q -i "fail" $log}] == 0} {
+ puts "Error: Check $log"
+ puts stderr "\[ERROR\]: Check $log"
+ exit 1
+ }
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "detailed placement - openroad"
+ set_def $::env(SAVE_DEF)
+}
+
+proc detailed_placement {args} {
+ detailed_placement_or args
+}
+
+proc add_macro_placement {args} {
+ puts_info "Adding Macro Placement..."
+ set ori "NONE"
+ if { [llength $args] == 4 } {
+ set ori [lindex $args 3]
+ }
+ try_catch echo [lindex $args 0] [lindex $args 1] [lindex $args 2] $ori >> $::env(placement_tmpfiles)/macro_placement.cfg
+}
+
+proc manual_macro_placement {args} {
+ increment_index
+ puts_info "Performing Manual Macro Placement..."
+ set var "f"
+ set fbasename [file rootname $::env(CURRENT_DEF)]
+ if { [string compare [lindex $args 0] $var] == 0 } {
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/manual_macro_place.py -l $::env(MERGED_LEF) -id $::env(CURRENT_DEF) -o ${fbasename}.macro_placement.def -c $::env(placement_tmpfiles)/macro_placement.cfg -f |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(placement_logs)/macro_placement.log]
+ } else {
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/manual_macro_place.py -l $::env(MERGED_LEF) -id $::env(CURRENT_DEF) -o ${fbasename}.macro_placement.def -c $::env(placement_tmpfiles)/macro_placement.cfg |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(placement_logs)/macro_placement.log]
+ }
+ set_def ${fbasename}.macro_placement.def
+}
+
+proc basic_macro_placement {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running basic macro placement..."
+
+ set fbasename [file rootname $::env(CURRENT_DEF)]
+ set ::env(SAVE_DEF) ${fbasename}.macro_placement.def
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/basic_mp.tcl -indexed_log [index_file $::env(placement_logs)/basic_mp.log]
+
+ check_macro_placer_num_solns
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "macro placement - basic_mp.tcl"
+ set_def $::env(SAVE_DEF)
+}
+
+proc run_placement {args} {
+ # |----------------------------------------------------|
+ # |---------------- 3. PLACEMENT ------------------|
+ # |----------------------------------------------------|
+ set ::env(CURRENT_STAGE) placement
+
+ if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
+ set old_pl_target_density $::env(PL_TARGET_DENSITY)
+ set ::env(PL_TARGET_DENSITY) $::env(PL_TARGET_DENSITY_CELLS)
+ }
+
+ if { $::env(PL_RANDOM_GLB_PLACEMENT) } {
+ # useful for very tiny designs
+ random_global_placement
+ } else {
+ global_placement_or
+ }
+
+ if { [info exists ::env(PL_TARGET_DENSITY_CELLS)] } {
+ set ::env(PL_TARGET_DENSITY) $old_pl_target_density
+ }
+
+ run_resizer_design
+
+ if { [info exists ::env(DONT_BUFFER_PORTS) ]} {
+ remove_buffers
+ }
+
+ detailed_placement_or -def $::env(placement_results)/$::env(DESIGN_NAME).def -log $::env(placement_logs)/detailed.log
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(placement_logs)/screenshot.log
+}
+
+proc run_resizer_design {args} {
+ if { $::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) == 1} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Placement Resizer Design Optimizations..."
+ set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/resizer.def]
+ set ::env(SAVE_SDC) [index_file $::env(placement_tmpfiles)/resizer.sdc]
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer.tcl -indexed_log [index_file $::env(placement_logs)/resizer.log]
+ set_def $::env(SAVE_DEF)
+ set ::env(CURRENT_SDC) $::env(SAVE_SDC)
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "resizer design optimizations - openroad"
+
+ write_verilog $::env(placement_results)/$::env(DESIGN_NAME).resized.v -log $::env(placement_logs)/write_verilog.log
+ set_netlist $::env(placement_results)/$::env(DESIGN_NAME).resized.v
+
+ if { $::env(LEC_ENABLE) && [file exists $::env(PREV_NETLIST)] } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+ } else {
+ puts_info "Skipping Placement Resizer Design Optimizations."
+ }
+}
+
+proc remove_buffers {args} {
+ increment_index
+ puts_info "Removing buffers..."
+ set fbasename [file rootname $::env(CURRENT_DEF)]
+ set ::env(SAVE_DEF) ${fbasename}.remove_buffers.def
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/dont_buffer.py\
+ --input_lef $::env(MERGED_LEF)\
+ --input_def $::env(CURRENT_DEF)\
+ --dont_buffer $::env(DONT_BUFFER_PORTS)\
+ --output_def $::env(SAVE_DEF)\
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(LOG_DIR)/placement/remove_buffers.log]
+
+ set_def $::env(SAVE_DEF)
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/refresh.tcl b/openlane/scripts/tcl_commands/refresh.tcl
new file mode 100755
index 0000000..20b7957
--- /dev/null
+++ b/openlane/scripts/tcl_commands/refresh.tcl
@@ -0,0 +1,15 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+pkg_mkIndex .
diff --git a/openlane/scripts/tcl_commands/routing.tcl b/openlane/scripts/tcl_commands/routing.tcl
new file mode 100755
index 0000000..59aa271
--- /dev/null
+++ b/openlane/scripts/tcl_commands/routing.tcl
@@ -0,0 +1,539 @@
+# Copyright 2020-2021 Efabless Corporation
+# ECO Flow Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc global_routing_or {args} {
+ handle_deprecated_command global_routing
+}
+
+proc translate_min_max_layer_variables {args} {
+ if { [info exists ::env(GLB_RT_MINLAYER) ] } {
+ set ::env(RT_MIN_LAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MINLAYER) - 1}]]
+ puts_warn "You're using GLB_RT_MINLAYER in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(RT_MIN_LAYER) {$::env(RT_MIN_LAYER)}"
+ }
+
+ if { [info exists ::env(GLB_RT_MAXLAYER) ] } {
+ set ::env(RT_MAX_LAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MAXLAYER) - 1}]]
+ puts_warn "You're using GLB_RT_MAXLAYER in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(RT_MAX_LAYER) {$::env(RT_MAX_LAYER)}"
+ }
+
+ if { [info exists ::env(GLB_RT_CLOCK_MINLAYER) ] } {
+ set ::env(RT_CLOCK_MIN_LAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MINLAYER) - 1}]]
+ puts_warn "You're using GLB_RT_CLOCK_MINLAYER in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(RT_CLOCK_MIN_LAYER) {$::env(RT_CLOCK_MIN_LAYER)}"
+ }
+
+ if { [info exists ::env(GLB_RT_CLOCK_MAXLAYER) ] } {
+ set ::env(RT_CLOCK_MAX_LAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MAXLAYER) - 1}]]
+ puts_warn "You're using GLB_RT_CLOCK_MAXLAYER in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(RT_CLOCK_MAX_LAYER) {$::env(RT_CLOCK_MAX_LAYER)}"
+ }
+}
+
+proc global_routing_cugr {args} {
+ if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
+ puts_err "DIODE_INSERTION_STRATEGY 3 is only valid when OpenROAD is used for global routing."
+ puts_err "Please try a different strategy."
+ return -code error
+ }
+ try_catch cugr \
+ -lef $::env(MERGED_LEF_UNPADDED) \
+ -def $::env(CURRENT_DEF) \
+ -output $::env(SAVE_GUIDE) \
+ -threads $::env(ROUTING_CORES) \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(routing_logs)/global.log]
+ file copy -force $::env(CURRENT_DEF) $::env(SAVE_DEF)
+}
+
+proc groute_antenna_extract {args} {
+ set options {
+ {-from_log required}
+ }
+ set flags {}
+ parse_key_args "groute_antenna_extract" args arg_values $options flags_map $flags
+
+ set value [exec python3 $::env(SCRIPTS_DIR)/extract_antenna_count.py < $arg_values(-from_log)]
+
+ return value
+}
+
+proc global_routing_fastroute {args} {
+ set saveLOG [index_file $::env(routing_logs)/global.log]
+
+ translate_min_max_layer_variables
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/groute.tcl -indexed_log $saveLOG
+ if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
+ puts_info "Starting FastRoute Antenna Repair Iterations..."
+ set_def $::env(SAVE_DEF)
+ set_guide $::env(SAVE_GUIDE)
+ set iter 2
+
+ set prevDEF1 $::env(SAVE_DEF)
+ set prevDEF2 $::env(SAVE_DEF)
+ set prevGUIDE1 $::env(SAVE_GUIDE)
+ set prevGUIDE2 $::env(SAVE_GUIDE)
+ set prevLOG1 $saveLOG
+ set prevLOG2 $saveLOG
+
+ set prevAntennaVal [groute_antenna_extract -from_log [index_file $::env(routing_logs)/global.log]]
+
+ while {$iter <= $::env(GLB_RT_MAX_DIODE_INS_ITERS) && $prevAntennaVal > 0} {
+ set ::env(SAVE_DEF) [index_file $::env(routing_tmpfiles)/global_$iter.def]
+ set ::env(SAVE_GUIDE) [index_file $::env(routing_tmpfiles)/global_$iter.guide]
+ set saveLOG [index_file $::env(routing_logs)/global_$iter.log]
+ set replaceWith "INSDIODE$iter"
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/replace_prefix_from_def_instances.py -op "ANTENNA" -np $replaceWith -d $::env(CURRENT_DEF)
+ puts_info "FastRoute Iteration $iter"
+ puts_info "Antenna Violations Previous: $prevAntennaVal"
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/groute.tcl -indexed_log $saveLOG
+ set currAntennaVal [groute_antenna_extract -from_log $saveLOG]
+ puts_info "Antenna Violations Current: $currAntennaVal"
+ if { $currAntennaVal >= $prevAntennaVal } {
+ set iter [expr $iter - 1]
+ set ::env(SAVE_DEF) $prevDEF1
+ set ::env(SAVE_GUIDE) $prevGUIDE1
+ set saveLOG $prevLOG1
+ break
+ } else {
+ set prevAntennaVal $currAntennaVal
+ set iter [expr $iter + 1]
+ set prevDEF1 $prevDEF2
+ set prevGUIDE1 $prevGUIDE2
+ set prevLOG1 $prevLOG2
+ set prevDEF2 $::env(SAVE_DEF)
+ set prevGUIDE2 $::env(SAVE_GUIDE)
+ set prevLOG2 $saveLOG
+ }
+ set_def $::env(SAVE_DEF)
+ set_guide $::env(SAVE_GUIDE)
+ }
+ }
+}
+
+proc global_routing {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Global Routing..."
+ set ::env(SAVE_GUIDE) [index_file $::env(routing_tmpfiles)/global.guide]
+ set ::env(SAVE_DEF) [index_file $::env(routing_tmpfiles)/global.def]
+
+ set tool "openroad"
+ if { $::env(GLOBAL_ROUTER) == "cugr" } {
+ set tool "cugr"
+ global_routing_cugr
+ } else {
+ global_routing_fastroute
+ }
+
+ set_def $::env(SAVE_DEF)
+ set_guide $::env(SAVE_GUIDE)
+
+ TIMER::timer_stop
+
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "global routing - $tool"
+}
+
+proc detailed_routing_tritonroute {args} {
+ set ::env(TRITONROUTE_FILE_PREFIX) $::env(routing_tmpfiles)/detailed
+ set ::env(TRITONROUTE_RPT_PREFIX) $::env(routing_reports)/detailed
+
+ translate_min_max_layer_variables
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/droute.tcl -indexed_log [index_file $::env(routing_logs)/detailed.log]
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/tr_drc_to_klayout_drc.py \
+ -i $::env(routing_reports)/detailed.drc \
+ -o $::env(routing_reports)/detailed.klayout.xml \
+ --design-name $::env(DESIGN_NAME)
+
+ quit_on_tr_drc
+}
+
+proc detailed_routing_drcu {args} {
+ try_catch drcu \
+ -lef $::env(MERGED_LEF_UNPADDED) \
+ -def $::env(CURRENT_DEF) \
+ -guide $::env(CURRENT_GUIDE) \
+ -threads $::env(ROUTING_CORES) \
+ -tat 99999999 \
+ -output $::env(routing_results)/$::env(DESIGN_NAME).def \
+ |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(routing_logs)/detailed.log]
+}
+
+proc detailed_routing {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Detailed Routing..."
+
+ set ::env(SAVE_DEF) $::env(routing_results)/$::env(DESIGN_NAME).def
+ if { $::env(ECO_ENABLE) == 1 && $::env(ECO_ITER) == 0 } {
+ set ::env(SAVE_DEF) $::env(eco_results)/arcdef/$::env(ECO_ITER)_post-route.def
+ }
+
+ set tool "openroad"
+ if {$::env(RUN_ROUTING_DETAILED)} {
+ if { $::env(DETAILED_ROUTER) == "drcu" } {
+ set tool "drcu"
+ detailed_routing_drcu
+ } else {
+ detailed_routing_tritonroute
+ }
+ } else {
+ exec echo "SKIPPED!" >> [index_file $::env(routing_logs)/detailed.log]
+ }
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "detailed_routing - $tool"
+ set_def $::env(SAVE_DEF)
+}
+
+proc ins_fill_cells_or {args} {
+ handle_deprecated_command ins_fill_cells
+}
+
+proc ins_fill_cells {args} {
+ increment_index
+
+ if {$::env(FILL_INSERTION)} {
+ TIMER::timer_start
+ puts_info "Running Fill Insertion..."
+ set ::env(SAVE_DEF) [index_file $::env(routing_tmpfiles)/fill.def]
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/fill.tcl -indexed_log [index_file $::env(routing_logs)/fill.log]
+ set_def $::env(SAVE_DEF)
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "fill insertion - openroad"
+ } else {
+ exec echo "SKIPPED!" >> [index_file $::env(routing_logs)/fill.log]
+ }
+
+}
+
+proc power_routing {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Routing top-level power nets..."
+
+ set options {
+ {-lef optional}
+ {-def optional}
+ {-power optional}
+ {-ground optional}
+ {-output_def optional}
+ {-extra_args optional}
+ }
+ set flags {}
+ parse_key_args "power_routing" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-lef) $::env(MERGED_LEF)
+ set_if_unset arg_values(-def) $::env(CURRENT_DEF)
+ set_if_unset arg_values(-power) $::env(VDD_PIN)
+ set_if_unset arg_values(-ground) $::env(GND_PIN)
+ set_if_unset arg_values(-output_def) [index_file $::env(routing_tmpfiles)/$::env(DESIGN_NAME).power_routed.def]
+ set_if_unset arg_values(-extra_args) ""
+
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/power_route.py\
+ --input-lef $arg_values(-lef)\
+ --input-def $arg_values(-def)\
+ --core-vdd-pin $arg_values(-power)\
+ --core-gnd-pin $arg_values(-ground)\
+ -o $arg_values(-output_def)\
+ {*}$arg_values(-extra_args) |& tee [index_file $::env(routing_logs)/power_routing.log] $::env(TERMINAL_OUTPUT)
+
+ set_def $arg_values(-output_def)
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "top level power routing - power_route.py"
+}
+
+proc gen_pdn {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Generating PDN..."
+
+ set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/pdn.def]
+ set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles)/pdn.pga.rpt]
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
+ |& -indexed_log [index_file $::env(floorplan_logs)/pdn.log]
+
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "pdn generation - openroad"
+
+ quit_on_unconnected_pdn_nodes
+
+ set_def $::env(SAVE_DEF)
+}
+
+
+proc ins_diode_cells_1 {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Diode Insertion..."
+ set ::env(SAVE_DEF) [index_file $::env(routing_tmpfiles)/diodes.def]
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/diodes.tcl -indexed_log [index_file $::env(routing_logs)/diodes.log]
+
+ set_def $::env(SAVE_DEF)
+
+ write_verilog $::env(synthesis_results)/$::env(DESIGN_NAME)_diodes.v -log $::env(routing_logs)/write_verilog.with_diodes.log
+ set_netlist $::env(synthesis_results)/$::env(DESIGN_NAME)_diodes.v
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "diode insertion - openroad"
+ if { $::env(LEC_ENABLE) } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+}
+
+proc ins_diode_cells_4 {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Diode Insertion..."
+ set ::env(SAVE_DEF) [index_file $::env(routing_tmpfiles)/diodes.def]
+
+ # Select diode cell
+ if { $::env(DIODE_INSERTION_STRATEGY) == 5 } {
+ if { ! [info exists ::env(FAKEDIODE_CELL)] } {
+ puts_err "DIODE_INSERTION_STRATEGY $::env(DIODE_INSERTION_STRATEGY) is only valid when FAKEDIODE_CELL is defined."
+ puts_err "Please try a different strategy."
+ return -code error
+ }
+ set ::antenna_cell_name $::env(FAKEDIODE_CELL)
+ } else {
+ set ::antenna_cell_name $::env(DIODE_CELL)
+ }
+
+ # Custom script
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/place_diodes.py -l $::env(MERGED_LEF) -id $::env(CURRENT_DEF) -o $::env(SAVE_DEF) --diode-cell $::env(DIODE_CELL) --diode-pin $::env(DIODE_CELL_PIN) --fake-diode-cell $::antenna_cell_name |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(routing_logs)/diodes.log]
+
+ set_def $::env(SAVE_DEF)
+
+ # Legalize
+ detailed_placement_or -def $::env(CURRENT_DEF) -log $::env(routing_logs)/diode_legalization.log
+
+ # Update netlist
+ write_verilog $::env(synthesis_results)/$::env(DESIGN_NAME)_diodes.v -log $::env(routing_logs)/write_verilog.with_diodes.log
+ set_netlist $::env(synthesis_results)/$::env(DESIGN_NAME)_diodes.v
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "diode insertion - place_diodes.py"
+ if { $::env(LEC_ENABLE) } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+}
+
+proc apply_route_obs {args} {
+ puts_info "Adding routing obstructions..."
+ # keep a warning for a while
+ puts_warn "Specifying a routing obstruction is now done using the coordinates"
+ puts_warn "of its bounding box instead of the now deprecated (x, y, size_x, size_y)."
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/add_def_obstructions.py \
+ --input-def $::env(CURRENT_DEF) \
+ --lef $::env(MERGED_LEF) \
+ --obstructions $::env(GLB_RT_OBS) \
+ --output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(routing_logs)/obs.log
+ puts_info "Obstructions added over $::env(GLB_RT_OBS)"
+ set_def [file rootname $::env(CURRENT_DEF)].obs.def
+}
+
+proc add_route_obs {args} {
+ if {[info exists ::env(GLB_RT_OBS)]} {
+ apply_route_obs
+ }
+}
+
+proc run_spef_extraction {args} {
+ set options {
+ {-log required}
+ {-rcx_lib optional}
+ {-rcx_lef optional}
+ {-rcx_rules optional}
+ {-process_corner optional}
+ }
+ parse_key_args "run_spef_extraction" args arg_values $options
+
+ set_if_unset arg_values(-rcx_lib) $::env(LIB_SYNTH_COMPLETE)
+ set_if_unset arg_values(-rcx_lef) $::env(MERGED_LEF_UNPADDED)
+ set_if_unset arg_values(-rcx_rules) $::env(RCX_RULES)
+
+ set ::env(RCX_LIB) $arg_values(-rcx_lib)
+ set ::env(RCX_LEF) $arg_values(-rcx_lef)
+ set ::env(RCX_RULESET) $arg_values(-rcx_rules)
+
+ if { ![file exists $::env(RCX_RULESET)]} {
+ puts_err "RCX ruleset '$::env(RCX_RULESET)' does not exist."
+ return -code error
+ }
+ if { ![file exists $::env(RCX_LEF)]} {
+ puts_err "Technology LEF file '$::env(RCX_LEF)' does not exist."
+ return -code error
+ }
+
+ increment_index
+ TIMER::timer_start
+ set log [index_file $arg_values(-log)]
+
+ set ec_postfix ""
+ if { [info exists arg_values(-process_corner)]} {
+ set ec_postfix " at the $arg_values(-process_corner) process corner"
+ }
+
+ puts_info "Running SPEF Extraction$ec_postfix..."
+
+ if { $::env(SPEF_EXTRACTOR) == "def2spef" } {
+ puts_warn "def2spef/spef_extractor has been removed. OpenROAD OpenRCX will be used instead."
+ set ::env(SPEF_EXTRACTOR) "openrcx"
+ }
+
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/rcx.tcl -indexed_log $log
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "parasitics extraction - openroad"
+}
+
+proc run_routing {args} {
+ puts_info "Routing..."
+
+ if { $::env(ECO_ENABLE) == 1 && $::env(ECO_ITER) == 0 } {
+ set log "$::env(eco_logs)"
+ set path "$::env(eco_results)"
+ set fix_path "$::env(eco_results)/fix"
+ set def_path "$::env(eco_results)/def"
+ set net_path "$::env(eco_results)/net"
+ set spef_path "$::env(eco_results)/spef"
+ set sdf_path "$::env(eco_results)/sdf"
+ set arc_def_path "$::env(eco_results)/arcdef"
+ file mkdir $log
+ file mkdir $path
+ file mkdir $fix_path
+ file mkdir $def_path
+ file mkdir $net_path
+ file mkdir $spef_path
+ file mkdir $sdf_path
+ file mkdir $arc_def_path
+ }
+ if { $::env(ECO_ENABLE) == 1 && $::env(ECO_ITER) != 0 } {
+ set ::env(CURRENT_DEF) $::env(eco_results)/def/eco_$::env(ECO_ITER).def
+ set ::env(CURRENT_NETLIST) $::env(eco_results)/net/eco_$::env(ECO_ITER).v
+ }
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+
+ # |----------------------------------------------------|
+ # |---------------- 5. ROUTING ----------------------|
+ # |----------------------------------------------------|
+ set ::env(CURRENT_STAGE) routing
+ run_resizer_timing_routing
+
+ if { [info exists ::env(DIODE_CELL)] && ($::env(DIODE_CELL) ne "") } {
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 1) || ($::env(DIODE_INSERTION_STRATEGY) == 2) } {
+ ins_diode_cells_1
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 4) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ ins_diode_cells_4
+ }
+ }
+
+ use_original_lefs
+
+ add_route_obs
+
+ #legalize if not yet legalized
+ if { ($::env(DIODE_INSERTION_STRATEGY) != 4) && ($::env(DIODE_INSERTION_STRATEGY) != 5) } {
+ detailed_placement_or -def $::env(CURRENT_DEF) -log $::env(routing_logs)/diode_legalization.log
+ }
+
+ # if diode insertion does *not* happen as part of global routing, then
+ # we can insert fill cells early on
+ if { ($::env(DIODE_INSERTION_STRATEGY) != 3) && ($::env(ECO_ENABLE) ==0 || $::env(ECO_FINISH) ==1) } {
+ ins_fill_cells
+ }
+
+ global_routing
+
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 3) && ($::env(ECO_ENABLE) ==0 || $::env(ECO_FINISH) ==1) } {
+ # Doing this here can be problematic and is something that needs to be
+ # addressed in FastRoute since fill cells *might* occupy some of the
+ # resources that were already used during global routing causing the
+ # detailed router to suffer later.
+ ins_fill_cells
+ }
+
+ set global_routed_netlist [index_file $::env(routing_tmpfiles)/global.v]
+ write_verilog $global_routed_netlist -log $::env(routing_logs)/write_verilog_global.log
+ set_netlist $global_routed_netlist
+ if { $::env(LEC_ENABLE) } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+
+ # detailed routing
+ detailed_routing
+
+ set detailed_routed_netlist [index_file $::env(routing_tmpfiles)/detailed.v]
+
+ write_verilog $detailed_routed_netlist -log $::env(routing_logs)/write_verilog_detailed.log
+
+ # for lvs
+ set_netlist $detailed_routed_netlist
+
+ if { $::env(ECO_ENABLE) == 1 && $::env(ECO_ITER) != 0 } {
+ set_netlist $::env(eco_results)/net/eco_$::env(ECO_ITER).v
+ }
+
+ if { $::env(LEC_ENABLE) } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(routing_logs)/screenshot.log
+
+ # spef extraction at the three corners
+
+ ## Calculate Runtime To Routing
+ set ::env(timer_routed) [clock seconds]
+}
+
+proc run_resizer_timing_routing {args} {
+ if { $::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) == 1} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Global Routing Resizer Timing Optimizations..."
+ set ::env(SAVE_DEF) [index_file $::env(routing_tmpfiles)/resizer_timing.def]
+ set ::env(SAVE_SDC) [index_file $::env(routing_tmpfiles)/resizer_timing.sdc]
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer_routing_timing.tcl -indexed_log [index_file $::env(routing_logs)/resizer.log]
+ set_def $::env(SAVE_DEF)
+ set ::env(CURRENT_SDC) $::env(SAVE_SDC)
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "resizer timing optimizations - openroad"
+
+ write_verilog $::env(routing_results)/$::env(DESIGN_NAME).resized.v -log $::env(routing_logs)/write_verilog.log
+ set_netlist $::env(routing_results)/$::env(DESIGN_NAME).resized.v
+
+ if { $::env(LEC_ENABLE) && [file exists $::env(PREV_NETLIST)] } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+
+ } else {
+ puts_info "Skipping Global Routing Resizer Timing Optimizations."
+ }
+}
+
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/sta.tcl b/openlane/scripts/tcl_commands/sta.tcl
new file mode 100644
index 0000000..8c988db
--- /dev/null
+++ b/openlane/scripts/tcl_commands/sta.tcl
@@ -0,0 +1,124 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc run_sta {args} {
+ set options {
+ {-log required}
+ {-lef optional}
+ {-process_corner optional}
+ }
+ set flags {
+ -multi_corner
+ -pre_cts
+ }
+ parse_key_args "run_sta" args arg_values $options flags_map $flags
+ set multi_corner [info exists flags_map(-multi_corner)]
+ set pre_cts [info exists flags_map(-pre_cts)]
+
+ set_if_unset arg_values(-lef) $::env(MERGED_LEF)
+ set ::env(STA_LEF) $arg_values(-lef)
+ set ::env(RUN_STANDALONE) 1
+
+ increment_index
+ TIMER::timer_start
+
+ set corner_prefix "Single-Corner"
+ if { $multi_corner } {
+ set corner_prefix "Multi-Corner"
+ }
+ set process_corner_postfix ""
+ if { [info exists arg_values(-process_corner)]} {
+ set process_corner_postfix " at the $arg_values(-process_corner) process corner"
+ }
+ puts_info "Running $corner_prefix Static Timing Analysis$process_corner_postfix..."
+
+ set ::env(STA_PRE_CTS) $pre_cts
+
+ set log [index_file $arg_values(-log)]
+
+ if {[info exists ::env(CLOCK_PORT)]} {
+ if { $multi_corner == 1 } {
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/sta_multi_corner.tcl \
+ -indexed_log $log
+ } else {
+ run_openroad_script $::env(SCRIPTS_DIR)/openroad/sta.tcl \
+ -indexed_log $log
+ }
+ } else {
+ puts_warn "CLOCK_PORT is not set. STA will be skipped..."
+ }
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "sta - openroad"
+}
+
+proc run_parasitics_sta {args} {
+ set options {
+ {-sdf_out optional}
+ {-spef_out_prefix optional}
+ }
+ set flags {}
+ parse_key_args "parasitics_sta" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-sdf_out) [file rootname $::env(CURRENT_DEF)].sdf
+ set_if_unset arg_values(-spef_out_prefix) [file rootname $::env(CURRENT_DEF)]
+
+ set ::env(SPEF_PREFIX) $arg_values(-spef_out_prefix)
+ set ::env(SAVE_SDF) $arg_values(-sdf_out)
+
+ puts_info "Running parasitics-based static timing analysis..."
+
+ # Nom last so CURRENT_SPEF is the nom current SPEF after the loop is done
+ foreach {process_corner lef ruleset} {
+ min MERGED_LEF_MIN RCX_RULES_MIN
+ max MERGED_LEF_MAX RCX_RULES_MAX
+ nom MERGED_LEF RCX_RULES
+ } {
+ if { [info exists ::env($lef)] } {
+ set ::env(SAVE_SPEF) "$::env(SPEF_PREFIX).$process_corner.spef"
+
+ run_spef_extraction\
+ -log $::env(signoff_logs)/parasitics_extraction.$process_corner.log\
+ -rcx_lib $::env(LIB_SYNTH_COMPLETE)\
+ -rcx_rules $::env($ruleset)\
+ -rcx_lef $::env($lef)\
+ -process_corner $process_corner
+
+ set ::env(CURRENT_SPEF) $::env(SAVE_SPEF)
+
+ set log_name $::env(signoff_logs)/parasitics_multi_corner_sta.$process_corner.log
+
+ if { $process_corner == "nom" } {
+ # First, we need this for the reports:
+ set log_name $::env(signoff_logs)/parasitics_multi_corner_sta.log
+
+ # We also need to run a single-corner STA at the tt timing corner
+ run_sta\
+ -log $::env(signoff_logs)/parasitics_sta.log\
+ -process_corner $process_corner
+
+ set ::env(LAST_TIMING_REPORT_TAG) [index_file $::env(signoff_reports)/rcx_sta]
+
+ set ::env(CURRENT_SDF) $::env(SAVE_SDF)
+ }
+
+ run_sta\
+ -lef $::env($lef)\
+ -log $log_name\
+ -process_corner $process_corner\
+ -multi_corner
+ }
+ }
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/tcl_commands/synthesis.tcl b/openlane/scripts/tcl_commands/synthesis.tcl
new file mode 100755
index 0000000..311f81d
--- /dev/null
+++ b/openlane/scripts/tcl_commands/synthesis.tcl
@@ -0,0 +1,236 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc get_yosys_bin {} {
+ return $::env(SYNTH_BIN)
+}
+
+proc convert_pg_pins {lib_in lib_out} {
+ try_catch sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} $lib_in > $lib_out
+}
+
+proc run_yosys {args} {
+ set ::env(CURRENT_STAGE) synthesis
+
+ set options {
+ {-output optional}
+ }
+ set flags {
+ -no_set_netlist
+ }
+
+ parse_key_args "run_yosys" args arg_values $options flags_map $flags
+
+ if { [info exists arg_values(-output)] } {
+ set ::env(SAVE_NETLIST) $arg_values(-output)
+ } else {
+ set ::env(SAVE_NETLIST) $::env(synthesis_results)/$::env(DESIGN_NAME).v
+ }
+ if { [ info exists ::env(SYNTH_ADDER_TYPE)] && ($::env(SYNTH_ADDER_TYPE) in [list "RCA" "CSA"]) } {
+ set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+ }
+
+ set ::env(synth_report_prefix) [index_file $::env(synthesis_reports)/synthesis]
+
+ set ::env(LIB_SYNTH_COMPLETE_NO_PG) [list]
+ foreach lib $::env(LIB_SYNTH_COMPLETE) {
+ set fbasename [file rootname [file tail $lib]]
+ set lib_path [index_file $::env(synthesis_tmpfiles)/$fbasename.no_pg.lib]
+ convert_pg_pins $lib $lib_path
+ lappend ::env(LIB_SYNTH_COMPLETE_NO_PG) $lib_path
+ }
+
+ try_catch $::env(SYNTH_BIN) \
+ -c $::env(SYNTH_SCRIPT) \
+ -l [index_file $::env(synthesis_logs)/synthesis.log] \
+ |& tee $::env(TERMINAL_OUTPUT)
+
+ if { ! [info exists flags_map(-no_set_netlist)] } {
+ set_netlist $::env(SAVE_NETLIST)
+ }
+
+ if { $::env(LEC_ENABLE) && [file exists $::env(PREV_NETLIST)] } {
+ logic_equiv_check -rhs $::env(PREV_NETLIST) -lhs $::env(CURRENT_NETLIST)
+ }
+
+ # The following is a naive workaround to the defparam issue.. it should be handled with
+ # an issue to the OpenROAD verilog parser.
+ if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
+ puts_info "This is a Synthesis Exploration and so no need to remove the defparam lines."
+ } else {
+ try_catch sed -i {/defparam/d} $::env(SAVE_NETLIST)
+ }
+}
+
+proc run_synth_exploration {args} {
+ if { $::env(SYNTH_NO_FLAT) } {
+ puts_err "Cannot run synthesis exploration with SYNTH_NO_FLAT."
+ return -code error
+ }
+
+ puts_info "Running Synthesis Exploration..."
+
+ set ::env(SYNTH_EXPLORE) 1
+
+ run_yosys
+
+ set exploration_report [index_file $::env(synthesis_reports)/exploration_analysis.html]
+
+ puts_info "Generating exploration report..."
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/synth_exp/analyze.py\
+ --output $exploration_report\
+ [index_file $::env(synthesis_logs)/synthesis.log]
+
+ set exploration_report_relative [relpath . $exploration_report]
+
+ puts_success "Done with synthesis exploration: See report at '$exploration_report_relative'."
+
+ # Following two cannot be indexed- referenced by path in the HTML file.
+ file copy $::env(SCRIPTS_DIR)/synth_exp/table.css $::env(synthesis_reports)
+ file copy $::env(SCRIPTS_DIR)/synth_exp/utils.js $::env(synthesis_reports)
+}
+
+proc run_synthesis {args} {
+ increment_index
+ TIMER::timer_start
+ puts_info "Running Synthesis..."
+ set ::env(CURRENT_SDC) $::env(BASE_SDC_FILE)
+ # in-place insertion
+ if { [file exists $::env(synthesis_results)/$::env(DESIGN_NAME).v] } {
+ puts_warn "A netlist at $::env(synthesis_results)/$::env(DESIGN_NAME).v already exists. Synthesis will be skipped."
+ set_netlist $::env(synthesis_results)/$::env(DESIGN_NAME).v
+ } else {
+ run_yosys
+ }
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "synthesis - yosys"
+
+ run_sta -pre_cts -log $::env(synthesis_logs)/sta.log
+ set ::env(LAST_TIMING_REPORT_TAG) [index_file $::env(synthesis_reports)/syn_sta]
+
+ if { $::env(RUN_SIMPLE_CTS) && $::env(CLOCK_TREE_SYNTH) } {
+ if { ! [info exists ::env(CLOCK_NET)] } {
+ set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+ }
+
+ simple_cts \
+ -verilog $::env(synthesis_results)/$::env(DESIGN_NAME).v \
+ -fanout $::env(CLOCK_BUFFER_FANOUT) \
+ -clk_net $::env(CLOCK_NET) \
+ -root_clk_buf $::env(ROOT_CLK_BUFFER) \
+ -clk_buf $::env(CLK_BUFFER) \
+ -clk_buf_input $::env(CLK_BUFFER_INPUT) \
+ -clk_buf_output $::env(CLK_BUFFER_OUTPUT) \
+ -cell_clk_port $::env(CELL_CLK_PORT) \
+ -output $::env(synthesis_results)/$::env(DESIGN_NAME).v
+ }
+
+ if { $::env(CHECK_ASSIGN_STATEMENTS) == 1 } {
+ check_assign_statements
+ }
+
+ if { $::env(CHECK_UNMAPPED_CELLS) == 1 } {
+ check_synthesis_failure
+ }
+
+ if { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+ puts_info "Creating a netlist with power/ground pins."
+ if { ! [info exists ::env(SYNTH_DEFINES)] } {
+ set ::env(SYNTH_DEFINES) [list]
+ }
+ lappend ::env(SYNTH_DEFINES) {*}$::env(SYNTH_USE_PG_PINS_DEFINES)
+ run_yosys -output $::env(synthesis_tmpfiles)/pg_define.v -no_set_netlist
+ }
+
+}
+
+proc verilog_elaborate {args} {
+ # usually run on structural verilog (top-level netlists)
+ set synth_script_old $::env(SYNTH_SCRIPT)
+ set ::env(SYNTH_SCRIPT) $::env(SCRIPTS_DIR)/yosys/synth_top.tcl
+ run_yosys {*}$args
+ set ::env(SYNTH_SCRIPT) $synth_script_old
+}
+
+proc yosys_rewrite_verilog {filename} {
+ if { !$::env(LEC_ENABLE) } {
+ puts_verbose "Skipping Verilog rewrite (logic equivalency checks are disabled)..."
+ return
+ }
+ if { !$::env(YOSYS_REWRITE_VERILOG) } {
+ puts_verbose "Skipping Verilog rewrite."
+ return
+ }
+
+ if { ! [file exists $filename] } {
+ puts_err "Failed to rewrite Verilog file $filename: File does not exist."
+ return -code error
+ }
+
+ set ::env(SAVE_NETLIST) $filename
+
+ increment_index
+ TIMER::timer_start
+ puts_info "Rewriting $filename to $::env(SAVE_NETLIST) using Yosys..."
+
+ try_catch $::env(SYNTH_BIN) \
+ -c $::env(SCRIPTS_DIR)/yosys/rewrite_verilog.tcl \
+ -l [index_file $::env(synthesis_logs)/rewrite_verilog.log]
+
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "verilog rewrite - yosys"
+}
+
+
+proc logic_equiv_check {args} {
+ set options {
+ {-lhs required}
+ {-rhs required}
+ }
+
+ set flags {}
+
+ set args_copy $args
+ parse_key_args "logic_equiv_check" args arg_values $options flags_map $flags
+
+
+ if { [file exists $arg_values(-lhs).without_power_pins.v] } {
+ set ::env(LEC_LHS_NETLIST) $arg_values(-lhs).without_power_pins.v
+ } else {
+ set ::env(LEC_LHS_NETLIST) $arg_values(-lhs)
+ }
+
+ if { [file exists $arg_values(-rhs).without_power_pins.v] } {
+ set ::env(LEC_RHS_NETLIST) $arg_values(-rhs).without_power_pins.v
+ } else {
+ set ::env(LEC_RHS_NETLIST) $arg_values(-rhs)
+ }
+ increment_index
+ TIMER::timer_start
+ puts_info "Running LEC: $::env(LEC_LHS_NETLIST) Vs. $::env(LEC_RHS_NETLIST)"
+
+
+ if { [catch {exec $::env(SYNTH_BIN) -c $::env(SCRIPTS_DIR)/yosys/logic_equiv_check.tcl -l [index_file $::env(synthesis_logs).equiv.log] |& tee $::env(TERMINAL_OUTPUT)} ]} {
+ puts_err "$::env(LEC_LHS_NETLIST) is not logically equivalent to $::env(LEC_RHS_NETLIST)."
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "logic equivalence check - yosys"
+ return -code error
+ }
+
+ puts_info "$::env(LEC_LHS_NETLIST) and $::env(LEC_RHS_NETLIST) are proven equivalent"
+ TIMER::timer_stop
+ exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "logic equivalence check - yosys"
+}
+
+package provide openlane 0.9
diff --git a/openlane/scripts/topModuleGen/README.md b/openlane/scripts/topModuleGen/README.md
new file mode 100644
index 0000000..b4c2b0d
--- /dev/null
+++ b/openlane/scripts/topModuleGen/README.md
@@ -0,0 +1,192 @@
+# Top Module Generator
+
+This program takes a chip core verilog file as well as a json description for the full chip with the desired IO pads connections, and auto generates the top level module of the chip including all the io pads and their connections, as well as automatically adding the power/corner pads.
+
+An example input should be available [here][1]
+
+## Command Line Arguments
+
+The following are arguments that can be passed to `src/TopModuleGen.py`
+
+<table>
+ <tr>
+ <th width="196">
+ Argument
+ </th>
+ <th >
+ Description
+ </th>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--design | -d <JSON file> </code> <br> (Required)
+ </td>
+ <td align="justify">
+ Specifies The JSON description of the design.
+ </td>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--padsLibs | -p <JSON file></code> <br> (Required)
+ </td>
+ <td align="justify">
+ Specifies the pad libraries JSON description.
+ </td>
+ </tr>
+ <tr>
+ <td align="center">
+ <code>--verilog | -v <verilog file></code> <br> (Required)
+ </td>
+ <td align="justify">
+ The input verilog file containing the core module header definition.
+ </td>
+ </tr>
+ <tr>
+ </tr>
+ <td align="center">
+ <code>--output | -o <file></code> <br> (Required)
+ </td>
+ <td align="justify">
+ Specifies The verilog output file.
+ </td>
+ </tr>
+</table>
+
+## The Design JSON description
+
+### The Full Description
+
+The json description of the design goes as follows:
+```json
+ {
+ "design_name": <name of the top module>,
+ "pads_library": <name of the io library to use>,
+ "defines": <Any defines/macros to add>,
+ "includes": <Any includes to add>,
+ "module":{
+ "name": <name of the chip core>,
+ "pads": <list of the IO pads and their sources>
+ },
+ "extra_verilog: <any extra verilog lines that the user would like to be put as is in the top module>
+ }
+```
+
+Use this [file][0] as a reference
+
+### Using Guards:
+You can use guards in the defines or includes sections by following this format for the object. For example, below we provide a description for a guard block inside the includes section:
+```json
+{
+ "inlcudes": [{...},
+ {
+ "condition":{
+ "name": <The name of the guard>,
+ "def": [{ //This will be translated to the `ifdef
+ "name": <name of the first include>
+ },
+ {
+ "name": <name of the second include>
+ }
+ ],
+ "ndef":[ //This will be translated to the `ifndef
+ {
+ "name": <name of the first include>
+ },
+ {
+ "name":<name of the second include>
+ }
+ ]
+
+ }
+ },
+ {...},
+ ....
+ ]
+}
+```
+The `def` and `ndef` sections are optional. But, at least on of them should exist inside a condition block.
+
+Nested guards are supported. by starting an object in the list of objects under either `def` or `ndef` and starting it with `condition`, and following the same format.
+
+### defines Block
+It expects a list of objects that could either contain a `name: <name of the define>` or a [guard block](#using-guards)
+
+```json
+ {
+ "defines":[
+ {
+ "name": <name of the define>
+ },
+ {<guard block>}
+ ]
+
+ }
+```
+
+
+
+### includes Block
+
+It expects a list of objects that could either contain a `name: <name of the include>` or a [guard block](#using-guards)
+
+```json
+ {
+ "includes":[
+ {
+ "name": <name of the include>
+ },
+ {<guard block>}
+
+ ]
+ }
+```
+
+### pads Block
+
+The pads description is simply listing objects, each of them describes one pad as follows:
+
+```json
+ {
+ "pads":[
+ {...},
+ {
+ "name":<name of the interface/pad>,
+ "size":<number>,
+ "type":"DIGITAL_OUTPUT",//The type
+ "output":< the connections from the core module to the pad>
+ },
+ {...},
+ ...
+ ]
+ }
+```
+
+**Note:** The pad name and its connection must have different names in order to produce valid verilog code.
+
+**Note:** If the `"type"` is `DIGITAL_OUTPUT` or `ANALOG_OUTPUT` then `"output":` should be used to describe the source connection from the core module. If it's a `DIGITAL_INPUT` or `ANALOG_OUTPUT`, then `"input":` should be used instead, and so on.
+
+There are optional fields that you can specify for each pad. To know those fields and their mapping, run the `padHelper.py` script under [src](./src). Run it first with `-h` flag to know the options.
+
+
+### size Block:
+
+The size block used in the pad section or the macros section could be represented in one of the following forms:
+
+1. Doesn't exist: The size is considered implicit in case of connection and `1` in case of declaration.
+2. `"size": <number>` The number is used as the size.
+3. `"size": {"start": <the start bit>, "offset": the offset}` The object description is to create a bus `[start+offset-1:start]`.
+
+### Source Block:
+
+The source (input/output) block could be described in any of the following ways:
+
+1. `"input":["","",""]` list of string(s)
+2. `"input":[{"name":<name of the connection>,"size": <size of the connection>},...]` list of objects that describe the name and size of the connections. Please check this [section](#size-block) to know the different size representations.
+
+### Supported Pad Types
+
+To show a list of supported pad types in a given PADs libraries json use the script `padHelper` under [./src](./src). Use the `-h` flag for the possible options.
+
+
+[0]: ./Examples/openram_tc/openram_tc_1kb.json
+[1]: ./Examples/openram_tc/
\ No newline at end of file
diff --git a/openlane/scripts/topModuleGen/src/TopModuleGen.py b/openlane/scripts/topModuleGen/src/TopModuleGen.py
new file mode 100644
index 0000000..2dba557
--- /dev/null
+++ b/openlane/scripts/topModuleGen/src/TopModuleGen.py
@@ -0,0 +1,913 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import json
+import argparse
+import copy
+import re
+import os
+from pyverilog.vparser.parser import parse
+
+# import StringIO
+try:
+ from StringIO import StringIO
+except ImportError:
+ from io import StringIO
+parser = argparse.ArgumentParser(
+ description="top module generation for a given (core design, pads library) pair"
+)
+
+
+parser.add_argument(
+ "--design",
+ "-d",
+ action="store",
+ required=True,
+ help="The json description of the design",
+)
+
+parser.add_argument(
+ "--padsLibs",
+ "-p",
+ action="store",
+ required=True,
+ help="The pad libraries json description",
+)
+
+parser.add_argument(
+ "--verilog",
+ "-v",
+ action="store",
+ required=True,
+ help="The input verilog file containing the core module header definition",
+)
+
+parser.add_argument(
+ "--output",
+ "-o",
+ action="store",
+ required=True,
+ help="The verilog file to output to",
+)
+
+
+args = parser.parse_args()
+design = args.design
+padsLibs = args.padsLibs
+output = args.output
+verilog_file = args.verilog
+
+# description of the design parsed into a dict
+if not os.path.exists(design):
+ raise IOError("file not found: " + design)
+designJSONOpener = open(design, "r")
+design_json_complete = json.load(designJSONOpener)
+designJSONOpener.close()
+
+
+# description of the libraries parsed into a dict
+if not os.path.exists(padsLibs):
+ raise IOError("file not found: " + padsLibs)
+padsLibsJSONOpener = open(padsLibs, "r")
+padsLibs_json = json.load(padsLibsJSONOpener)
+padsLibsJSONOpener.close()
+
+# Finding the used pads library
+padsLib_json = dict()
+for padsLib in padsLibs_json:
+ if padsLib["library_name"] == design_json_complete["pads_library"]:
+ padsLib_json = padsLib
+ break
+
+if len(padsLib_json) == 0:
+ raise Exception("Used Pad Lib is not found in the given Pad Libraries JSON")
+
+# extracting the core module needed pads
+design_json = design_json_complete["module"]
+
+# Necessary intermediate containers
+written_macros = list()
+wiresToDeclare = dict()
+headerSignalsToDeclare = dict()
+
+# Segments of the final written verilog code
+topModuleHeader = "module " + design_json_complete["design_name"] + "(\n"
+topModuleDeclarations = ""
+topModuleDefines = (
+ "`timescale 1 ns / 1 ps\n\n`define USE_PG_PIN\n`define functional\n\n"
+)
+topModuleIncludes = ""
+topModuleBody = ""
+topModuleMacros = ""
+designDeclaration = ""
+topModuleExtra = ""
+padFrameModule = ""
+padFrameHeader = "chip_io padframe(\n"
+padFrameHeaderDefinition = "module chip_io(\n"
+padFrameWires = ""
+# parsePads is responsible for parsing the pads except for power/corner pads
+def parsePads():
+ global topModuleHeader
+ for user_pad in design_json["pads"]:
+ # find pad direction
+ padType = user_pad["type"]
+
+ padUsed = dict()
+
+ # extract pad
+ for library_pad in padsLib["pads"]:
+ if library_pad["type"] == padType:
+ padUsed = library_pad
+ break
+ if len(padUsed) == 0:
+ raise Exception("Used Pad is not of a defined type")
+ writePad(padUsed, user_pad)
+ topModuleHeader = topModuleHeader[:-2] + ");\n"
+
+
+# writePad is responsible for adding a non-power/non-corner pad to the output verilog
+def writePad(padUsed, user_info):
+ global topModuleHeader
+ global padFrameModule
+ global padFrameHeaderDefinition
+ global padFrameHeader
+
+ v = user_info["size"] > 1
+ macro_name = ""
+ if v:
+ macro_name += padUsed["type"] + "_V"
+ else:
+ macro_name += padUsed["type"]
+ writePadMacro(padUsed, v, macro_name)
+ instType = resolveInterfaceType(user_info["type"])
+ instSize = resolveSize(user_info["size"])
+ topModuleHeader += instType + " "
+ topModuleHeader += instSize + " "
+ topModuleHeader += user_info["name"] + ",\n"
+
+ if instType == "input":
+ instType = "inout"
+ padFrameHeaderDefinition += instType + " "
+ padFrameHeaderDefinition += instSize + " "
+ padFrameHeaderDefinition += user_info["name"] + ",\n"
+
+ padFrameHeader += "." + user_info["name"] + "(" + user_info["name"] + "),\n"
+
+ inst_body = "`" + macro_name + " ("
+ if v:
+ inst_body += str(user_info["size"]) + ","
+
+ for key in padUsed["mapping"].keys():
+ res = None
+
+ if key == "name":
+ res = [user_info]
+ elif key in user_info.keys():
+ res = user_info[key]
+ else:
+ for port in padUsed["ports"]:
+ if "condition" in port.keys():
+ continue
+ if port["name"] == padUsed["mapping"][key]:
+ res = port["connection"]
+ break
+ if res is not None:
+ if isinstance(res, dict) and "name" not in res.keys():
+ wire_name = padUsed["type"] + "_" + user_info["name"] + "_" + key
+ createDictWireForPads(wire_name, res, user_info["size"])
+ inst_body += wire_name + ","
+ elif len(res) > 1 and key != "name":
+ wire_name = padUsed["type"] + "_" + user_info["name"] + "_" + key
+ createWireForPads(wire_name, res)
+ inst_body += wire_name + ","
+ else:
+ if isinstance(res[0], dict):
+ inst_body += res[0]["name"] + " "
+ if "size" in res[0].keys() and key != "name":
+ inst_body += resolveSize(res[0]["size"])
+ else:
+ inst_body += res[0] + " "
+ inst_body += ","
+ else:
+ inst_body += " , "
+ inst_body = inst_body[:-1] + ");\n"
+
+ padFrameModule += inst_body
+
+
+# createDictWireForPads creates the wire for a pad macro parameter if it has a complex object description. The description is parsed into an assign to that wire. i.e. "mode":{"bit_0":{}, "bit_1":{}, "bit_2":{}}
+def createDictWireForPads(wire_name, wire_info, size):
+ global padFrameWires
+ wire_body = (
+ "wire ["
+ + str(size * len(wire_info.keys()) - 1)
+ + ":0] "
+ + wire_name
+ + " = {\n\t\t"
+ )
+ for i in reversed(range(size)):
+ for key in wire_info.keys():
+ wire_body += wire_info[key] + "[" + str(i) + "],"
+ wire_body += "\n\t\t"
+ wire_body = wire_body[:-4] + "};\n"
+ padFrameWires += wire_body
+
+
+# createWireForPads creates the wire for a pad macro parameter if it has a list description.
+def createWireForPads(wire_name, wire_info):
+ global padFrameWires
+ wire_body = (
+ "wire [" + str(getConcatSize(wire_info) - 1) + ":0] " + wire_name + " = {"
+ )
+ for con in wire_info:
+ if isinstance(con, dict):
+ wire_body += con["name"] + " "
+ if "size" in con.keys():
+ wire_body += resolveSize(con["size"])
+ else:
+ wire_body += con + " "
+ wire_body += ", "
+ wire_body = wire_body[:-2] + "};\n"
+ padFrameWires += wire_body
+
+
+# getConcatSize gets the total size of a concatenation
+def getConcatSize(concatentation):
+ tot_size = 0
+
+ for signal in concatentation:
+ if isinstance(signal, dict):
+ if "size" in signal.keys():
+ if isinstance(signal["size"], int):
+ tot_size += signal["size"]
+ else:
+ tot_size += signal["size"]["offset"]
+ else:
+ tot_size += 1
+ else:
+ tot_size += 1
+ return tot_size
+
+
+# writePadMacro is responsible for writing the macro definition of the pads except for power/corner pads
+def writePadMacro(pad_macro, v, macro_name):
+ if macro_name in written_macros:
+ return
+ pad_macro_copy = copy.deepcopy(pad_macro)
+ written_macros.append(macro_name)
+ global topModuleMacros
+ macro_body = ""
+ if v:
+ macro_body += "`define " + macro_name + "(V,"
+ else:
+ macro_body += "`define " + macro_name + "("
+
+ for key in pad_macro_copy["mapping"].keys():
+ macro_body += key.upper() + ","
+
+ pad_macro_copy["ports"] = resolvePortMapping(
+ pad_macro_copy["mapping"], pad_macro_copy["ports"]
+ )
+ macro_body = macro_body[:-1] + ") \\\n"
+
+ for wire in pad_macro_copy["wire_declaration_info"]:
+ macro_body += "wire "
+ if v:
+ macro_body += "[V-1:0] "
+ macro_body += resolveConnectionName(wire["name"]) + "; \\\n"
+
+ macro_body += pad_macro_copy["pad_name"] + " NAME``_pad "
+ if v:
+ macro_body += "[V-1:0] ( \\\n"
+ else:
+ macro_body += "( \\\n"
+
+ if "defines" in pad_macro_copy.keys():
+ macro_body += addPadDefines(pad_macro_copy["defines"], True)
+
+ for port in pad_macro_copy["ports"]:
+ if "condition" in port.keys():
+ hasElse = False
+ if "def" in port["condition"].keys():
+ portd = port["condition"]["def"]
+ macro_body += "`ifdef " + port["condition"]["name"] + " \\\n"
+ macro_body += "\t." + portd["name"] + "( "
+ if portd["connection"] is not None:
+ if len(portd["connection"]) > 1:
+ macro_body += "{"
+ for connection in portd["connection"]:
+ macro_body += resolveConnectionName(connection) + ","
+ macro_body = macro_body[:-1] + "},"
+ else:
+ macro_body += (
+ resolveConnectionName(portd["connection"][0]) + ","
+ )
+ macro_body = macro_body[:-1] + "), \\\n"
+ hasElse = True
+ if "ndef" in port["condition"].keys():
+ portd = port["condition"]["ndef"]
+ if hasElse:
+ macro_body += "`else \\\n"
+ else:
+ macro_body += "`ifndef " + port["condition"]["name"] + " \\\n"
+ macro_body += "\t." + portd["name"] + "( "
+ if portd["connection"] is not None:
+ if len(portd["connection"]) > 1:
+ macro_body += "{"
+ for connection in portd["connection"]:
+ macro_body += resolveConnectionName(connection) + ","
+ macro_body = macro_body[:-1] + "},"
+ else:
+ macro_body += (
+ resolveConnectionName(portd["connection"][0]) + ","
+ )
+ macro_body = macro_body[:-1] + "), \\\n"
+ macro_body += "`endif \\\n"
+
+ else:
+ macro_body += "." + port["name"] + "( "
+ if port["connection"] is not None:
+ if len(port["connection"]) > 1:
+ macro_body += "{"
+ for connection in port["connection"]:
+ macro_body += resolveConnectionName(connection) + ","
+ macro_body = macro_body[:-1] + "},"
+ else:
+ macro_body += resolveConnectionName(port["connection"][0]) + ","
+ macro_body = macro_body[:-1] + "), \\\n"
+
+ macro_body = macro_body[:-4] + ")\n\n"
+
+ topModuleMacros += macro_body
+
+
+# resolveConnectionName to replace any references to $name with the proper ``NAME or NAME``
+def resolveConnectionName(connection):
+ if connection.find("$name") == 0:
+ return connection.replace("$name", "NAME``")
+ else:
+ return connection.replace("$name", "``NAME")
+
+
+# resolvePortMapping to resolve the value of defined port with the user defined value or retrieve it from the the default values defined in the PADs library
+def resolvePortMapping(mapping, ports):
+ for key in mapping.keys():
+ for portIdx in range(len(ports)):
+ port = ports[portIdx]
+ if "condition" in port.keys():
+ if "def" in port["condition"].keys():
+ if port["condition"]["def"]["name"] == mapping[key]:
+ port["condition"]["def"]["connection"] = [key.upper()]
+
+ if "ndef" in port["condition"].keys():
+ if port["condition"]["ndef"]["name"] == mapping[key]:
+ port["condition"]["ndef"]["connection"] = [key.upper()]
+ elif port["name"] == mapping[key]:
+ port["connection"] = [key.upper()]
+ ports[portIdx] = port
+ return ports
+
+
+# resolveSize to resolve the size whether its defined as 1, [size-1:0], or [offset-start+1:start]
+def resolveSize(size):
+ if isinstance(size, int):
+ if int(size) > 1:
+ return "[" + str(size - 1) + ":0] "
+ else:
+ return ""
+ else:
+ return (
+ "["
+ + str(size["offset"] + size["start"] - 1)
+ + ":"
+ + str(size["start"])
+ + "] "
+ )
+
+
+# resolveInterfaceType to resolve type of interface to input, output, or inout
+def resolveInterfaceType(padType):
+ if padType in ["DIGITAL_INPUT", "ANALOG_INPUT", "DIGITAL_INPUT_TV2", "XRES"]:
+ return "input"
+ if padType in ["DIGITAL_OUTPUT", "ANALOG_OUTPUT", "DIGITAL_OUTPUT_TV2"]:
+ return "output"
+ if padType in ["DIGITAL_INOUT", "ANALOG_INOUT"]:
+ return "inout"
+
+ raise Exception("Used Pad is not of a defined type")
+
+
+# parsePowerCornerPads is responsible for parsing the power/corner pads
+def parsePowerCornerPads():
+ # Handle Case of user give power/corner pads
+ for pad in padsLib["pads"]:
+ if "count" in pad.keys():
+ global padFrameModule
+ if "powerCornerPads" in design_json_complete.keys():
+ for new_pad in design_json_complete["powerCornerPads"]:
+ if pad["type"] == new_pad["type"]:
+ if "count" in new_pad.keys():
+ pad["count"] = new_pad["count"]
+
+ if "ports" in new_pad.keys():
+ for p_new in new_pad["ports"]:
+ for p_default_idx in range(len(pad["ports"])):
+ if (
+ p_new["name"]
+ == pad["ports"][p_default_idx]["name"]
+ ):
+ pad["ports"][p_default_idx] = p_new
+ break
+ break
+ if "condition" in pad.keys():
+ if pad["condition"]["def"]:
+ padFrameModule += "`ifdef " + pad["condition"]["name"] + "\n"
+ else:
+ padFrameModule += "`ifndef " + pad["condition"]["name"] + "\n"
+ padFrameModule += writePowerCornerPad(pad)
+ padFrameModule += "`endif\n"
+ else:
+ padFrameModule += writePowerCornerPad(pad) + "\n"
+
+
+# writePowerCornerPad is responsible for adding a power/corner pad to the output verilog
+def writePowerCornerPad(padUsed):
+ padBody = str(padUsed["pad_name"]) + " " + str(padUsed["type"])
+ if int(padUsed["count"]) > 1:
+ padBody += " [" + str(int(padUsed["count"]) - 1) + ":0] (\n"
+ else:
+ padBody += " (\n"
+
+ if "defines" in padUsed.keys():
+ padBody += addPadDefines(padUsed["defines"], False)
+
+ ports = padUsed["ports"]
+
+ # add wires to the declaration plan
+ if "wire_declaration_info" in padUsed.keys():
+ if padUsed["wire_declaration_info"] is not None:
+ for wire in padUsed["wire_declaration_info"]:
+ wiresToDeclare[wire["name"]] = wire
+
+ # add header signals to the declaration plan
+ if "interface_declaration_info" in padUsed.keys():
+ if padUsed["interface_declaration_info"] is not None:
+ for signal in padUsed["interface_declaration_info"]:
+ headerSignalsToDeclare[signal["name"]] = signal
+
+ for port in ports:
+ if "condition" in port.keys():
+ hasElse = False
+ if "def" in port["condition"].keys():
+ portd = port["condition"]["def"]
+ padBody += "`ifdef " + port["condition"]["name"] + " \n"
+ padBody += "\t." + portd["name"] + "( "
+ if portd["connection"] is not None:
+ if len(portd["connection"]) > 1:
+ padBody += "{"
+ for con in portd["connection"]:
+ padBody += con + ", "
+ padBody = padBody[:-2] + "},"
+ else:
+ padBody += portd["connection"][0] + ","
+
+ padBody = padBody[:-1] + "),\n"
+ hasElse = True
+ if "ndef" in port["condition"].keys():
+ portd = port["condition"]["ndef"]
+ if hasElse:
+ padBody += "`else \n"
+ else:
+ padBody += "`ifndef " + port["condition"]["name"] + " \n"
+ padBody += "\t." + portd["name"] + "( "
+ if portd["connection"] is not None:
+ padBody += "{"
+ if len(portd["connection"]) > 1:
+ for con in portd["connection"]:
+ padBody += con + ", "
+ padBody = padBody[:-2] + "},"
+ else:
+ padBody += portd["connection"][0] + ","
+ padBody = padBody[:-1] + "),\n"
+ padBody += "`endif \n"
+ else:
+ padBody += "." + port["name"] + "( "
+ if port["connection"] is not None:
+ if len(port["connection"]) > 1:
+ padBody += "{"
+ for con in port["connection"]:
+ padBody += con + ", "
+ padBody = padBody[:-2] + "},"
+ else:
+ padBody += port["connection"][0] + ","
+ padBody = padBody[:-1] + "),\n"
+
+ padBody = padBody[:-2] + ");\n"
+ return padBody
+
+
+# addPadDefines adds the defines inside the pads i.e. `ABUTMENT_PINS
+def addPadDefines(defines, isMacro):
+ ret = ""
+ for define in defines:
+ if "condition" in define.keys():
+ hasElse = False
+ if "def" in define["condition"]:
+ hasElse = True
+ ret += "`ifdef " + define["condition"]["name"]
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+ for single_define in define["condition"]["def"]:
+ ret += "`" + single_define["name"]
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+
+ if "ndef" in define["condition"]:
+ if hasElse:
+ ret += "`else"
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+ else:
+ ret += "`ifndef " + define["condition"]["name"]
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+ for single_define in define["condition"]["ndef"]:
+ ret += "`" + single_define["name"]
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+ ret += "`endif"
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+ else:
+ ret += "`" + define["name"]
+ if isMacro:
+ ret += " \\\n"
+ else:
+ ret += " \n"
+ return ret
+
+
+# parseMacros parses user defines or pad library defines
+def parseMacros(defines):
+ global topModuleDefines
+ for define in defines:
+ # add wires to the declaration plan
+ if "wire_declaration_info" in define.keys():
+ if define["wire_declaration_info"] is not None:
+ for wire in define["wire_declaration_info"]:
+ wiresToDeclare[wire["name"]] = wire
+
+ # add header signals to the declaration plan
+ if "interface_declaration_info" in define.keys():
+ if define["interface_declaration_info"] is not None:
+ for signal in define["interface_declaration_info"]:
+ headerSignalsToDeclare[signal["name"]] = signal
+
+ topModuleDefines += writeMacro(define)[:-2] + "\n\n"
+
+
+# writeMacro writes the macro to the final verilog output
+def writeMacro(define):
+ macro_body = ""
+ if "condition" in define.keys():
+ hasElse = False
+ if "def" in define["condition"]:
+ hasElse = True
+ macro_body += "`ifdef " + define["condition"]["name"] + " \n"
+ macro_body += writeMacro(define["condition"]["def"])
+
+ if "ndef" in define["condition"]:
+ if hasElse:
+ macro_body = macro_body[:-2] + "\n`else \n"
+ else:
+ macro_body += "`ifndef " + define["condition"]["name"] + " \n"
+ macro_body += writeMacro(define["condition"]["ndef"])
+ macro_body = macro_body[:-2] + "\n`endif \n"
+ else:
+ macro_body += "`define " + define["name"] + " \\\n"
+ if "ports" in define.keys():
+ for port in define["ports"]:
+ if "condition" in port.keys():
+ hasElse = False
+ if "def" in port["condition"]:
+ hasElse = True
+ portd = port["condition"]["def"]
+ macro_body += "`ifdef " + port["condition"]["name"] + " \\\n"
+ macro_body += "\t." + portd["name"] + "( "
+ if portd["connection"] is not None:
+ if len(portd["connection"]) > 1:
+ macro_body += "{"
+ for con in portd["connection"]:
+ macro_body += con + ", "
+ macro_body = macro_body[:-2] + "},"
+ else:
+ macro_body += portd["connection"][0] + ","
+ macro_body = macro_body[:-1] + "), \\\n"
+ if "ndef" in define["condition"]:
+ portd = port["condition"]["ndef"]
+ if hasElse:
+ macro_body += "`else \\\n"
+ else:
+ macro_body += (
+ "`ifndef " + define["condition"]["name"] + " \\\n"
+ )
+ macro_body += "\t." + portd["name"] + "( "
+ if portd["connection"] is not None:
+ if len(portd["connection"]) > 1:
+ macro_body += "{"
+ for con in portd["connection"]:
+ macro_body += con + ", "
+ macro_body = macro_body[:-2] + "},"
+ else:
+ macro_body += portd["connection"][0] + ","
+ macro_body = macro_body[:-1] + "), \\\n"
+ macro_body += "`endif \\\n"
+ else:
+ macro_body += "\t." + port["name"] + "( "
+ if port["connection"] is not None:
+ if len(port["connection"]) > 1:
+ macro_body += "{"
+ for con in port["connection"]:
+ macro_body += con + ", "
+ macro_body = macro_body[:-2] + "},"
+ else:
+ macro_body += port["connection"][0] + ","
+ macro_body = macro_body[:-1] + "), \\\n"
+ return macro_body
+
+
+# addTopModuleWires writes the wires required by the pads/user in the top module
+def addPadFrameWires():
+ global padFrameWires
+ for wire in wiresToDeclare:
+ if wire in headerSignalsToDeclare:
+ continue
+ else:
+ decl = "\nwire "
+ if "size" in wiresToDeclare[wire]:
+ decl += resolveSize(wiresToDeclare[wire]["size"])
+ decl += wire + ";"
+ padFrameWires += decl
+
+
+# Add the module interface required by the pads: i.e. vss, vdd1v8, vdd
+def addTopModulePadsInterface():
+ global topModuleHeader
+ global padFrameHeaderDefinition
+ global padFrameHeader
+
+ if len(headerSignalsToDeclare):
+ topModuleHeader = topModuleHeader[:-3] + ",\n"
+ for signal in headerSignalsToDeclare:
+ decl = resolveInterfaceType(headerSignalsToDeclare[signal]["type"]) + " "
+ if "size" in headerSignalsToDeclare[signal]:
+ decl += resolveSize(headerSignalsToDeclare[signal]["size"]) + " "
+ decl += signal + ",\n"
+ topModuleHeader += decl
+ padFrameHeaderDefinition += decl
+ padFrameHeader += "." + signal + "(" + signal + "),\n"
+ topModuleHeader = topModuleHeader[:-2] + ");\n"
+ padFrameHeaderDefinition = padFrameHeaderDefinition[:-2] + ");\n"
+ padFrameHeader = padFrameHeader[:-2] + ");\n"
+
+
+# parseDesignHeader parses the verilog module header of the core module and creates its wires and connections
+def parseDesignHeader(verilog_file):
+ global padFrameHeaderDefinition
+ global padFrameHeader
+ global topModuleDeclarations
+ global topModuleBody
+ module_header = design_json["name"] + " core_inst(\n"
+ wiresDeclarations = ""
+ ast, x = parse([verilog_file])
+ # output = StringIO()
+ out = StringIO()
+ ast.show(buf=out)
+ rlst = out.getvalue()
+ # print(rlst)
+ startString = "ModuleDef: " + design_json["name"]
+ startPoint = rlst.find(startString)
+ startPoint = rlst.find("Portlist:", startPoint)
+ declIdx = rlst.find("Decl:", startPoint)
+ instanceListIdx = rlst.find("InstanceList:", startPoint)
+ moduleDefIdx = rlst.find("ModuleDef:", startPoint)
+ if declIdx == -1:
+ declIdx = 0x0FFFFFFF
+ if instanceListIdx == -1:
+ instanceListIdx = 0x0FFFFFFF
+ if moduleDefIdx == -1:
+ moduleDefIdx = 0x0FFFFFFF
+ endIdx = min(declIdx, instanceListIdx, moduleDefIdx)
+ if endIdx != 0x0FFFFFFF:
+ rlst = rlst[:endIdx]
+ portList = rlst[startPoint:].split("Ioport:")
+ # print(portList)
+ # print(portList)
+ for port in portList[1:]:
+ port_split = port.split("\n")
+ for idx in range(len(port_split)):
+ line = port_split[idx]
+ if line.find("Input") != -1:
+ signalName = getSignalName(line)
+ signalSize = extractSizeFromVerilog(port_split, idx)
+ module_header += "." + signalName + "(" + signalName + "),\n"
+ wiresDeclarations += "wire " + signalSize + " " + signalName + ";\n"
+ padFrameHeader += "." + signalName + "(" + signalName + "),\n"
+ padFrameHeaderDefinition += (
+ "output " + signalSize + " " + signalName + ",\n"
+ )
+ break
+ elif line.find("Output") != -1:
+ signalName = getSignalName(line)
+ signalSize = extractSizeFromVerilog(port_split, idx)
+ module_header += "." + signalName + "(" + signalName + "),\n"
+ wiresDeclarations += "wire " + signalSize + " " + signalName + ";\n"
+ padFrameHeader += "." + signalName + "(" + signalName + "),\n"
+ padFrameHeaderDefinition += (
+ "input " + signalSize + " " + signalName + ",\n"
+ )
+ break
+ elif line.find("Inout") != -1:
+ signalName = getSignalName(line).strip()
+ signalSize = extractSizeFromVerilog(port_split, idx)
+ module_header += "." + signalName + "(" + signalName + "),\n"
+ wiresDeclarations += "wire " + signalSize + " " + signalName + ";\n"
+ padFrameHeader += "." + signalName + "(" + signalName + "),\n"
+ padFrameHeaderDefinition += (
+ "inout " + signalSize + " " + signalName + ",\n"
+ )
+ break
+ module_header = module_header[:-2] + ");\n"
+ topModuleDeclarations += wiresDeclarations
+ topModuleBody += module_header
+
+
+def getSignalName(line):
+ pattern = re.compile(r"\s*?[\S+]+\,")
+ for signal in re.findall(pattern, line):
+ return signal[1:-1]
+
+
+def extractSizeFromVerilog(port_split, start_idx):
+ size = ""
+ end_idx = min(start_idx + 3, len(port_split))
+ for idx in range(start_idx, end_idx):
+ line = port_split[idx]
+ if line.find("Width") != -1:
+ pattern = re.compile(r"\s*?\d+\s")
+ size += "["
+ for s in re.findall(pattern, port_split[idx + 1]):
+ size += s + ":"
+ break
+ for s in re.findall(pattern, port_split[idx + 2]):
+ size += s + "]"
+ break
+ return size
+
+
+# parseIncludes parses the includes of a given json
+def parseIncludes(includes):
+ global topModuleIncludes
+ for include in includes:
+ topModuleIncludes += writeInclude(include) + "\n\n"
+
+
+# writeInclude writes the includes into the final verilog output
+def writeInclude(include):
+ include_body = ""
+ if isinstance(include, dict) and "condition" in include.keys():
+ hasElse = False
+ if "def" in include["condition"]:
+ hasElse = True
+ include_body += "`ifdef " + include["condition"]["name"] + " \n"
+ if isinstance(include["condition"]["def"], list):
+ for i in include["condition"]["def"]:
+ include_body += writeInclude(i)
+ else:
+ include_body += writeInclude(include["condition"]["def"])
+
+ if "ndef" in include["condition"]:
+ if hasElse:
+ include_body = include_body + "`else \n"
+ else:
+ include_body += "`ifndef " + include["condition"]["name"] + " \n"
+ include_body += writeInclude(include["condition"]["ndef"])
+ if isinstance(include["condition"]["ndef"], list):
+ for i in include["condition"]["ndef"]:
+ include_body += writeInclude(i)
+ else:
+ include_body += writeInclude(include["condition"]["ndef"])
+ include_body = include_body + "`endif \n"
+ else:
+ include_body += '\t`include "' + include["name"] + '"\n'
+ return include_body
+
+
+# If defines/macros section exists in the descriptions, write those defines
+if "defines" in padsLib.keys() and len(padsLib["defines"]):
+ topModuleDefines += "\n//PADs Library defines/macros\n"
+ parseMacros(padsLib["defines"])
+if "defines" in design_json_complete.keys() and len(design_json_complete["defines"]):
+ topModuleDefines += "\n//User defines/macros\n"
+ parseMacros(design_json_complete["defines"])
+
+# If the includes section exists in the description, write those includes
+if "includes" in padsLib_json.keys() and len(padsLib_json["includes"]):
+ topModuleIncludes += "\n//PADs Library includes\n"
+ parseIncludes(padsLib_json["includes"])
+if "includes" in design_json_complete.keys() and len(design_json_complete["includes"]):
+ topModuleIncludes += "\n//User includes\n"
+ parseIncludes(design_json_complete["includes"])
+
+# Parse the pads
+padFrameModule += "\n//Input/Output PADs\n"
+parsePads()
+padFrameModule += "\n//Power/Corner PADs\n"
+parsePowerCornerPads()
+
+
+# if section extra_verilog exists, write append the extra_verilog to the module
+if "extra_verilog" in design_json_complete.keys():
+ if isinstance(design_json_complete["extra_verilog"], list):
+ for ex in design_json_complete["extra_verilog"]:
+ topModuleExtra += ex + "\n"
+ else:
+ topModuleExtra = design_json_complete["extra_verilog"]
+
+# Read the user verilog file and parse the top module header
+if not os.path.exists(verilog_file):
+ raise IOError("file not found: " + verilog_file)
+"""verilogFileOpener = open(verilog_file, 'r')
+verilogFileData = verilogFileOpener.read()
+verilogFileOpener.close()"""
+topModuleBody += "\n\n//Core Module Instantiation\n"
+parseDesignHeader(verilog_file)
+
+
+# add the module interface
+addTopModulePadsInterface()
+
+# add the used wires
+addPadFrameWires()
+
+
+# write endmodule
+topModuleBody += "\n\n//PadFrame Instantiation\n" + padFrameHeader
+topModuleBody += "\n\nendmodule"
+
+# join padframe module sections
+padFrameModule = (
+ padFrameHeaderDefinition
+ + "\n\n"
+ + padFrameWires
+ + "\n\n"
+ + padFrameModule
+ + "\n\nendmodule"
+)
+
+# join the code segments
+topModule = (
+ topModuleDefines
+ + "\n\n\n"
+ + topModuleIncludes
+ + "\n\n\n"
+ + topModuleMacros
+ + "\n\n\n"
+ + topModuleHeader
+ + "\n\n\n"
+ + topModuleDeclarations
+ + "\n\n\n"
+ + topModuleExtra
+ + topModuleBody
+ + "\n\n"
+ + padFrameModule
+ + "\n\n"
+)
+
+# write the code
+outputFileOpener = open(output, "w+")
+outputFileOpener.write(topModule)
+outputFileOpener.close()
diff --git a/openlane/scripts/topModuleGen/src/padHelper.py b/openlane/scripts/topModuleGen/src/padHelper.py
new file mode 100644
index 0000000..573b7ff
--- /dev/null
+++ b/openlane/scripts/topModuleGen/src/padHelper.py
@@ -0,0 +1,96 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import json
+import argparse
+import os
+
+parser = argparse.ArgumentParser(
+ description="top module generation helper to show the optional fields of a given pad"
+)
+
+parser.add_argument(
+ "--padType",
+ "-t",
+ action="store",
+ required=False,
+ help="The pad type to show the mapping for",
+)
+
+parser.add_argument(
+ "--showPadTypes",
+ "-s",
+ action="store_true",
+ default=False,
+ help="A flag to list all the available pad types in a given library.",
+)
+
+parser.add_argument(
+ "--padsLibs",
+ "-p",
+ action="store",
+ required=True,
+ help="The pad libraries json description",
+)
+
+parser.add_argument(
+ "--padsLibName",
+ "-n",
+ action="store",
+ required=True,
+ help="The name of the pad library to use from the given padsLibs",
+)
+
+
+args = parser.parse_args()
+padType = args.padType
+padsLibs = args.padsLibs
+showPadTypes = args.showPadTypes
+padsLibName = args.padsLibName
+
+
+if padType is None and not showPadTypes:
+ print(
+ "Please either specify a pad type to show the mapping for, or use the showPadTypes flag to list all possible types in the library"
+ )
+else:
+ # description of the libraries parsed into a dict
+ if not os.path.exists(padsLibs):
+ raise IOError("file not found: " + padsLibs)
+ padsLibsJSONOpener = open(padsLibs, "r")
+ padsLibs_json = json.load(padsLibsJSONOpener)
+ padsLibsJSONOpener.close()
+
+ # Finding the used pads library
+ padsLib_json = dict()
+ for padsLib in padsLibs_json:
+ if padsLib["library_name"] == padsLibName:
+ padsLib_json = padsLib
+ break
+
+ if len(padsLib_json) == 0:
+ raise Exception("Used Pad Lib is not found in the given Pad Libraries JSON")
+
+ if showPadTypes:
+ for pad in padsLib_json["pads"]:
+ if "mapping" in pad:
+ print(pad["type"])
+ if padType is not None:
+ for pad in padsLib_json["pads"]:
+ if padType == pad["type"]:
+ print("print mapping for pad", padType)
+ print("key : mapped_to")
+ for mapping in pad["mapping"].keys():
+ print(mapping, " : ", pad["mapping"][mapping])
+ break
diff --git a/openlane/scripts/tr_drc_to_klayout_drc.py b/openlane/scripts/tr_drc_to_klayout_drc.py
new file mode 100644
index 0000000..cfca7f3
--- /dev/null
+++ b/openlane/scripts/tr_drc_to_klayout_drc.py
@@ -0,0 +1,118 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import re
+import xml.etree.ElementTree as ET
+import xml.dom.minidom as minidom
+
+parser = argparse.ArgumentParser(
+ description="Converts a TritonRoute DRC Report to a KLayout database"
+)
+
+parser.add_argument("--input", "-i", required=True, help="")
+
+parser.add_argument("--design-name", "-name", required=True, help="")
+
+parser.add_argument("--output", "-o", required=True, help="")
+
+args = parser.parse_args()
+
+input_file_name = args.input
+design_name = args.design_name
+output_file_name = args.output
+
+RE_VIOLATION = re.compile(
+ r"violation type: (?P<type>\S+)\s+"
+ + r"srcs: (?P<src1>\S+)( (?P<src2>\S+))?\s+"
+ + r"bbox = \( (?P<llx>\S+), (?P<lly>\S+) \)"
+ + r" - "
+ + r"\( (?P<urx>\S+), (?P<ury>\S+) \) "
+ + r"on Layer (?P<layer>\S+)",
+ re.M,
+)
+
+
+def prettify(elem):
+ """
+ Return a pretty-printed XML string for the Element.
+ """
+ rough_string = ET.tostring(elem, "utf-8")
+ reparsed = minidom.parseString(rough_string)
+ return reparsed.toprettyxml(indent=" ", newl="\n")
+ # encoding='utf-8')
+
+
+with open(input_file_name, "r") as f:
+ content = f.read()
+
+cnt = 0
+vio_dict = {}
+for match in RE_VIOLATION.finditer(content):
+ cnt += 1
+ type_ = match.group("type")
+ src1 = match.group("src1")
+ src2 = match.group("src2")
+ llx = match.group("llx")
+ lly = match.group("lly")
+ urx = match.group("urx")
+ ury = match.group("ury")
+ layer = match.group("layer")
+
+ item = ET.Element("item")
+ ET.SubElement(item, "category").text = type_
+ ET.SubElement(item, "cell").text = design_name
+ ET.SubElement(item, "visited").text = "false"
+ ET.SubElement(item, "multiplicity").text = "1"
+ values = ET.SubElement(item, "values")
+ box = ET.SubElement(values, "value")
+ box.text = f"box: ({llx},{lly};{urx},{ury})"
+ layer_msg = ET.SubElement(values, "value")
+ layer_msg.text = f"text: 'On layer {layer}'"
+ srcs = ET.SubElement(values, "value")
+ if src2:
+ srcs.text = f"text: 'Between {src1} {src2}'"
+ else:
+ srcs.text = f"text: 'Between {src1}'"
+
+ # create XML object
+ if type_ not in vio_dict:
+ vio_dict[type_] = []
+
+ vio_dict[type_].append(item)
+
+print("Found", cnt, "violations")
+
+report_database = ET.Element("report-database")
+categories = ET.SubElement(report_database, "categories")
+for type_ in vio_dict.keys():
+ category = ET.SubElement(categories, "category")
+ ET.SubElement(category, "name").text = type_
+
+cells = ET.SubElement(report_database, "cells")
+cell = ET.SubElement(cells, "cell")
+ET.SubElement(cell, "name").text = design_name
+
+items = ET.Element("items")
+for _, vios in vio_dict.items():
+ for item in vios:
+ items.append(item)
+
+report_database.append(items)
+
+report_database_str = prettify(report_database)
+
+with open(output_file_name, "w") as f:
+ f.write(report_database_str)
diff --git a/openlane/scripts/update_design_configs.py b/openlane/scripts/update_design_configs.py
new file mode 100644
index 0000000..2542366
--- /dev/null
+++ b/openlane/scripts/update_design_configs.py
@@ -0,0 +1,164 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+import subprocess
+import utils.utils as utils
+
+parser = argparse.ArgumentParser(
+ description="update configuration of design(s) per given PDK"
+)
+
+parser.add_argument(
+ "--root",
+ "-r",
+ action="store",
+ default="./",
+ help="The root directory. assuming root/designs, root/scripts root/logs",
+)
+
+parser.add_argument(
+ "--pdk", "-p", action="store", required=True, help="The name of the PDK"
+)
+
+parser.add_argument(
+ "--std-cell-library",
+ "-scl",
+ action="store",
+ required=True,
+ help="The name of the standard cell library",
+)
+
+
+parser.add_argument("--designs", "-d", nargs="+", default=[], help="designs to update ")
+
+parser.add_argument(
+ "--best_results",
+ "-b",
+ action="store",
+ required=True,
+ help="name of the log file from which to extract the name of the best configs",
+)
+
+parser.add_argument(
+ "--clean",
+ "-cl",
+ action="store_true",
+ default=False,
+ help="deletes the config file that the data was extracted from",
+)
+
+parser.add_argument(
+ "--update_clock_period",
+ "-ucp",
+ action="store_true",
+ default=False,
+ help="Updates the CLOCK_PERIOD of the design based on the suggested_clock_period parameter",
+)
+
+args = parser.parse_args()
+root = args.root
+pdk = args.pdk
+std_cell_library = args.std_cell_library
+designs = list(dict.fromkeys(args.designs))
+best_results = args.best_results
+clean = args.clean
+update_clock_period = args.update_clock_period
+
+logFileOpener = open(root + "/regression_results/" + best_results, "r")
+logFileData = logFileOpener.read().split("\n")
+logFileOpener.close()
+
+
+headerInfo = logFileData[0].split(",")
+configIdx = 0
+designIdx = 0
+flow_statusIdx = 0
+clkPeriodIdx = -1
+for i in range(len(headerInfo)):
+ if headerInfo[i] == "config":
+ configIdx = i
+ continue
+ if headerInfo[i] == "design":
+ designIdx = i
+ continue
+ if headerInfo[i] == "flow_status":
+ flow_statusIdx = i
+ continue
+ if headerInfo[i] == "suggested_clock_period":
+ clkPeriodIdx = i
+
+designConfigDict = dict()
+designFailDict = dict()
+designClockDict = dict()
+
+logFileData = logFileData[1:]
+
+for line in logFileData:
+ if line != "":
+ splitLine = line.split(",")
+ designConfigDict[str(splitLine[designIdx])] = str(splitLine[configIdx])
+ designFailDict[str(splitLine[designIdx])] = (
+ str(splitLine[flow_statusIdx]) == "flow_completed"
+ )
+ if clkPeriodIdx != -1:
+ designClockDict[str(splitLine[designIdx])] = str(splitLine[clkPeriodIdx])
+
+if len(designs) == 0:
+ designs = [key for key in designConfigDict]
+
+for design in designs:
+ if design not in designConfigDict.keys():
+ print(f"{design} not found in sheet. Skipping...")
+
+ if not designFailDict[design]:
+ print(f"Skipping {design} ...")
+ continue
+
+ print(f"Updating {design} config...")
+ base_path = utils.get_design_path(design=design)
+ configFileToUpdate = (
+ str(base_path) + "/" + str(pdk) + "_" + str(std_cell_library) + "_config.tcl"
+ )
+ configFileBest = str(base_path) + "/" + str(designConfigDict[design]) + ".tcl"
+
+ configFileBestOpener = open(configFileBest, "r")
+ configFileBestData = configFileBestOpener.read().split("\n")
+ configFileBestOpener.close()
+
+ newData = ""
+ copyFrom = False
+ for line in configFileBestData:
+ if line == "# Regression":
+ copyFrom = True
+
+ if copyFrom:
+ newData += line + "\n"
+
+ configFileToUpdateOpener = open(configFileToUpdate, "a+")
+ configFileToUpdateOpener.write(newData)
+ if update_clock_period:
+ if design in designClockDict and float(designClockDict[design]) > 0:
+ clockLine = (
+ '\n# Suggested Clock Period:\nset ::env(CLOCK_PERIOD) "'
+ + str(round(float(designClockDict[design]), 2))
+ + '"\n'
+ )
+ configFileToUpdateOpener.write(clockLine)
+ configFileToUpdateOpener.close()
+
+ if clean:
+ clean_cmd = f"rm -f {configFileBest}"
+ subprocess.check_output(clean_cmd.split())
+ # clean config file
diff --git a/openlane/scripts/utils/__init__.py b/openlane/scripts/utils/__init__.py
new file mode 100644
index 0000000..44c42c0
--- /dev/null
+++ b/openlane/scripts/utils/__init__.py
@@ -0,0 +1,13 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
diff --git a/openlane/scripts/utils/deflef_utils.tcl b/openlane/scripts/utils/deflef_utils.tcl
new file mode 100755
index 0000000..c7520e0
--- /dev/null
+++ b/openlane/scripts/utils/deflef_utils.tcl
@@ -0,0 +1,186 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc remove_empty_nets {args} {
+ set options {{-input required}}
+ set flags {}
+ parse_key_args "remove_empty_nets" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py remove_nets\
+ --empty-only\
+ --input-lef $::env(MERGED_LEF)\
+ --output $arg_values(-input)\
+ $arg_values(-input)
+}
+
+proc resize_die {args} {
+ set options {\
+ {-def required} \
+ {-area required}
+ }
+ set flags {}
+ parse_key_args "resize_die" args arg_values $options flags_map $flags
+
+ set llx [expr {[lindex $arg_values(-area) 0] * $::env(DEF_UNITS_PER_MICRON)}]
+ set lly [expr {[lindex $arg_values(-area) 1] * $::env(DEF_UNITS_PER_MICRON)}]
+ set urx [expr {[lindex $arg_values(-area) 2] * $::env(DEF_UNITS_PER_MICRON)}]
+ set ury [expr {[lindex $arg_values(-area) 3] * $::env(DEF_UNITS_PER_MICRON)}]
+ puts_info "Resizing Die to $arg_values(-area)"
+ try_catch sed -i -E "0,/^DIEAREA.*$/{s/^DIEAREA.*$/DIEAREA ( $llx $lly ) ( $urx $ury ) ;/}" $arg_values(-def)
+}
+
+proc get_instance_position {args} {
+ set options {\
+ {-instance required}\
+ {-def optional}
+ }
+ set flags {}
+ parse_key_args "get_instance_position" args arg_values $options flags_map $flags
+
+ set instance $arg_values(-instance)
+ if { [info exists arg_values(-def)] } {
+ set def $arg_values(-def)
+ } elseif { [info exists ::env(CURRENT_DEF)] } {
+ set def $::env(CURRENT_DEF)
+ } else {
+ puts_err "No DEF specified"
+ return -code error
+ }
+
+ puts $instance
+ set pos [exec sed -E -n "s/^\s*-\s+$instance.*\( (\[\[:digit:\]\]+) (\[\[:digit:\]\]+) \).*;$/\1 \2/p" $arg_values(-def)]
+
+ return $pos
+}
+
+
+
+proc add_lefs {args} {
+ set options {{-src required} \
+ \
+ }
+ set flags {}
+ parse_key_args "add_lefs" args arg_values $options flags_map $flags
+ puts_info "Merging $arg_values(-src)"
+
+
+ if { $::env(WIDEN_SITE) == 1 && $::env(WIDEN_SITE_IS_FACTOR) == 1 } {
+
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py -i $::env(MERGED_LEF) {*}$arg_values(-src) -o $::env(MERGED_LEF).new
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py -i $::env(MERGED_LEF_UNPADDED) {*}$arg_values(-src) -o $::env(MERGED_LEF_UNPADDED).new
+
+ try_catch mv $::env(MERGED_LEF).new $::env(MERGED_LEF)
+ try_catch mv $::env(MERGED_LEF_UNPADDED).new $::env(MERGED_LEF_UNPADDED)
+
+ } else {
+ # The original lef
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py -i $::env(MERGED_LEF_ORIGINAL) {*}$arg_values(-src) -o $::env(MERGED_LEF_ORIGINAL).new
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py -i $::env(MERGED_LEF_UNPADDED_ORIGINAL) {*}$arg_values(-src) -o $::env(MERGED_LEF_UNPADDED_ORIGINAL).new
+
+ try_catch mv $::env(MERGED_LEF_ORIGINAL).new $::env(MERGED_LEF_ORIGINAL)
+ try_catch mv $::env(MERGED_LEF_UNPADDED_ORIGINAL).new $::env(MERGED_LEF_UNPADDED_ORIGINAL)
+
+ # The modified lef
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py -i $::env(MERGED_LEF_WIDENED) {*}$arg_values(-src) -o $::env(MERGED_LEF_WIDENED).new
+ try_catch $::env(SCRIPTS_DIR)/mergeLef.py -i $::env(MERGED_LEF_UNPADDED_WIDENED) {*}$arg_values(-src) -o $::env(MERGED_LEF_UNPADDED_WIDENED).new
+
+ try_catch mv $::env(MERGED_LEF_WIDENED).new $::env(MERGED_LEF_WIDENED)
+ try_catch mv $::env(MERGED_LEF_UNPADDED_WIDENED).new $::env(MERGED_LEF_UNPADDED_WIDENED)
+ }
+}
+
+proc merge_components {args} {
+ set options {{-input1 required} \
+ {-input2 required} \
+ {-output required} \
+ }
+ set flags {}
+ parse_key_args "merge_components" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutils.py\
+ merge_components\
+ --input-lef $::env(MERGED_LEF)\
+ --output $arg_values(-output)\
+ $arg_values(-input1) $arg_values(-input2)
+}
+
+
+proc move_pins {args} {
+ # To be precise, this REPLACES pins in to with the ones in from.
+ set options {{-from required} \
+ {-to required} \
+ }
+ set flags {}
+ parse_key_args "move_pins" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py replace_pins\
+ --output $arg_values(-to)\
+ --input-lef $::env(MERGED_LEF)\
+ $arg_values(-from) $arg_values(-to)
+}
+
+proc zeroize_origin_lef {args} {
+ set options {{-file required} \
+ }
+ set flags {}
+ parse_key_args "zeroize_origin_lef" args arg_values $options flags_map $flags
+ exec cp $arg_values(-file) $arg_values(-file).original
+ try_catch python3 $::env(SCRIPTS_DIR)/zeroize_origin_lef.py < $arg_values(-file) > $arg_values(-file).zeroized
+ exec mv $arg_values(-file).zeroized $arg_values(-file)
+}
+
+
+proc remove_pins {args} {
+ set options {{-input required}}
+ set flags {}
+ parse_key_args "remove_pins" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py remove_pins\
+ --input-lef $::env(MERGED_LEF)\
+ --output $arg_values(-input)\
+ $arg_values(-input)
+}
+
+
+proc remove_nets {args} {
+ set options {{-input required}}
+ set flags {}
+ parse_key_args "remove_nets" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py remove_nets\
+ --input-lef $::env(MERGED_LEF)\
+ --output $arg_values(-input)\
+ $arg_values(-input)
+}
+
+proc remove_components {args} {
+ set options {{-input required}}
+ set flags {}
+ parse_key_args "remove_components" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py remove_components\
+ --input-lef $::env(MERGED_LEF)\
+ --output $arg_values(-input)\
+ $arg_values(-input)
+}
+
+proc remove_component {args} {
+ set options {
+ {-input required}
+ {-instance_name required}
+ }
+ set flags {}
+ parse_key_args "remove_component" args arg_values $options flags_map $flags
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/defutil.py remove_components\
+ --input-lef $::env(MERGED_LEF)\
+ --instance-name $arg_values(-instance_name) --not-rx\
+ --output $arg_values(-input)\
+ $arg_values(-input)
+}
+
+package provide openlane_utils 0.9
diff --git a/openlane/scripts/utils/fake_display_buffer.tcl b/openlane/scripts/utils/fake_display_buffer.tcl
new file mode 100755
index 0000000..343c477
--- /dev/null
+++ b/openlane/scripts/utils/fake_display_buffer.tcl
@@ -0,0 +1,26 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+proc fake_display_buffer {args} {
+ set screen :9
+ exec Xvfb $screen -screen 0 640x480x24 &
+ set ::env(DISPLAY) $screen
+}
+
+proc kill_display_buffer {args} {
+ exec killall Xvfb
+}
+
+
+package provide openlane_utils 0.9
diff --git a/openlane/scripts/utils/pkgIndex.tcl b/openlane/scripts/utils/pkgIndex.tcl
new file mode 100755
index 0000000..f642ddd
--- /dev/null
+++ b/openlane/scripts/utils/pkgIndex.tcl
@@ -0,0 +1,25 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Tcl package index file, version 1.1
+# This file is generated by the "pkg_mkIndex" command
+# and sourced either when an application starts up or
+# by a "package unknown" script. It invokes the
+# "package ifneeded" command to set up package-related
+# information so that packages will be loaded automatically
+# in response to "package require" commands. When this
+# script is sourced, the variable $dir must contain the
+# full path name of this file's directory.
+
+package ifneeded openlane_utils 0.9 [list source [file join $dir deflef_utils.tcl]]\n[list source [file join $dir utils.tcl]]\n[list source [file join $dir fake_display_buffer.tcl]]
diff --git a/openlane/scripts/utils/utils.py b/openlane/scripts/utils/utils.py
new file mode 100644
index 0000000..9af85ac
--- /dev/null
+++ b/openlane/scripts/utils/utils.py
@@ -0,0 +1,89 @@
+#!/usr/bin/python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import re
+import csv
+
+
+def get_design_path(design):
+ path = os.path.abspath(design) + "/"
+ if not os.path.exists(path):
+ path = os.path.join(os.getcwd(), f"./designs/{design}/")
+ if os.path.exists(path):
+ return path
+ else:
+ return None
+
+
+def get_run_path(design, tag):
+ return os.path.join(get_design_path(design), "runs", tag)
+
+
+def get_design_name(design, config):
+ design_path = get_design_path(design=design)
+ if design_path is None:
+ return ("Design path not found", None)
+ config_file = f"{design_path}/{config}.tcl"
+ try:
+ config_file_opener = open(config_file, "r")
+ configs = config_file_opener.read()
+ config_file_opener.close()
+ pattern = re.compile(r"\s*?set ::env\(DESIGN_NAME\)\s*?(\S+)\s*")
+ for name in re.findall(pattern, configs):
+ return (None, name.strip('"{}'))
+ return ("Invalid configuration file", None)
+ except OSError:
+ return ("Configuration file not found", None)
+
+
+def add_computed_statistics(filename):
+ """
+ Adds some calculated values to a report CSV file, namely:
+
+ * Cells per mm sq over core utilization
+ * Suggested clock period
+ * Suggested clock frequency
+ """
+ rows = []
+
+ csv_headers = open(filename).read().split("\n")[0].split(",")
+
+ def add(name: str, before: str):
+ nonlocal csv_headers
+ idx = csv_headers.index(before)
+ csv_headers.insert(idx, name)
+
+ add("(Cell/mm^2)/Core_Util", "DIEAREA_mm^2")
+ add("suggested_clock_period", "CLOCK_PERIOD")
+ add("suggested_clock_frequency", "CLOCK_PERIOD")
+
+ csv_file_in = open(filename)
+ reader = csv.DictReader(csv_file_in)
+ for row in reader:
+ row["(Cell/mm^2)/Core_Util"] = float(row["CellPer_mm^2"]) / (
+ float(row["FP_CORE_UTIL"]) / 100
+ )
+
+ suggest_clock_period = float(row["CLOCK_PERIOD"]) - float(row["spef_wns"])
+ row["suggested_clock_period"] = suggest_clock_period
+ row["suggested_clock_frequency"] = 1000 / suggest_clock_period
+ rows.append(row)
+ csv_file_in.close()
+
+ with open(filename, "w") as f:
+ writer = csv.DictWriter(f, csv_headers)
+ writer.writeheader()
+ for row in rows:
+ writer.writerow(row)
diff --git a/openlane/scripts/utils/utils.tcl b/openlane/scripts/utils/utils.tcl
new file mode 100755
index 0000000..dec8591
--- /dev/null
+++ b/openlane/scripts/utils/utils.tcl
@@ -0,0 +1,464 @@
+# Copyright 2020-2022 Efabless Corporation
+# ECO Flow Copyright 2021 The University of Michigan
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# warn about deprecated configs and preserve backwards compatibility
+proc handle_deprecated_config {old new} {
+ if { [info exists ::env($old)] } {
+ puts_warn "$old is now deprecated; use $new instead."
+
+ if { ! [info exists ::env($new)] } {
+ set ::env($new) $::env($old)
+ }
+ if { $::env($new) != $::env($old) } {
+ puts_err "Conflicting values of $new and $old; please remove $old from your design configurations"
+ return -code error
+ }
+ }
+}
+
+proc find_all {ext} {
+ if { ! [info exists ::env(RUN_DIR)] } {
+ puts_err "You are not currently running a design. Perhaps you forgot to run 'prep'?"
+ return -code error
+ }
+ return [exec find $::env(RUN_DIR) -name "*.$ext" | sort | xargs realpath --relative-to=$::env(PWD)]
+}
+
+proc handle_deprecated_command {new} {
+ set invocation [info level -1]
+ set caller [lindex $invocation 0]
+ set args [lrange $invocation 1 end]
+
+ puts_warn "$caller is now deprecated; use $new instead."
+ eval {$new {*}$args}
+}
+
+proc set_if_unset {var default_value} {
+ upvar $var x
+ if {! [info exists x] } {
+ set x $default_value
+ }
+}
+
+# create an array out of a list
+
+proc add_to_env {my_array} {
+ foreach {key value} [array get my_array] {
+ set $::env($key) $value
+ }
+}
+
+# helper function for argument parsing
+proc is_keyword_arg { arg } {
+ if { [string length $arg] >= 2 \
+ && [string index $arg 0] == "-" \
+ && [string is alpha [string index $arg 1]] } {
+ return 1
+ } else {
+ return 0
+ }
+}
+
+proc extract_pins_from_yosys_netlist {netlist_file} {
+ # This sed command works because the module herader in a
+ # yosys-generated netlist is on one line.
+ return [list [exec sed -E -n {/^module/ s/module[[:space:]]+[^[:space:]]+[[:space:]]*\((.*)\);/\1/pg}\
+ $netlist_file \
+ | tr -d ',']]
+
+}
+
+# parse arguments
+# adopted from https://github.com/The-OpenROAD-Project/OpenSTA/blob/77f22e482e8d48d29f2810d871a22847f1bdd74a/tcl/Util.tcl#L31
+
+proc parse_key_args {cmd arg_var key_var options {flag_var ""} {flags {}} {consume_args_flag "-consume"}} {
+ upvar 1 $arg_var args
+ upvar 1 $key_var key_value
+ upvar 1 $flag_var flag_present
+ set args_copy $args
+ set keys {}
+ foreach option $options {
+ set option_name [lindex $option 0]
+ if { [lsearch -exact $option required ] >= 0} {
+ set key_index [lsearch -exact $args [lindex $option 0]]
+ if {$key_index < 0} {
+ puts_err "$cmd missing required $option_name"
+ return -code error
+ }
+ }
+ lappend keys $option_name
+ }
+
+ set args_rtn {}
+ while { $args != "" } {
+ set arg [lindex $args 0]
+ if { [is_keyword_arg $arg] } {
+ set key_index [lsearch -exact $keys $arg]
+ if { $key_index >= 0 } {
+ set key $arg
+ if { [llength $args] == 1 } {
+ puts_err "$cmd $key missing value."
+ return -code error
+ }
+ set key_value($key) [lindex $args 1]
+ set args [lrange $args 1 end]
+ } else {
+ set flag_index [lsearch -exact $flags $arg]
+ if { $flag_index >= 0 } {
+ set flag_present($arg) 1
+ }
+ }
+ } else {
+ lappend args_rtn $arg
+ }
+ set args [lrange $args 1 end]
+ }
+
+ if { $consume_args_flag == "-no_consume" } {
+ set args $args_copy
+ } else {
+ set args $args_rtn
+ }
+ return -code ok
+}
+
+# puts a variable in a log file
+proc set_log {var val filepath log_flag} {
+ set cmd "set ${var} \{${val}\}"
+ uplevel #0 ${cmd}
+ set global_cfg_file [open $filepath a+]
+ if { $log_flag } {
+ puts $global_cfg_file $cmd
+ }
+ close $global_cfg_file
+}
+
+# a minimal try catch block
+proc try_catch {args} {
+ # puts_info "Executing \"$args\"\n"
+ if { ! [catch { set cmd_log_file [open $::env(RUN_DIR)/cmds.log a+] } ]} {
+ set timestamp [clock format [clock seconds]]
+ puts $cmd_log_file "$timestamp - Executing \"$args\"\n"
+ close $cmd_log_file
+ }
+ set exit_code [catch {eval exec $args} error_msg]
+ if { $exit_code } {
+ set tool [string range $args 0 [string first " " $args]]
+ set print_error_msg "during executing: \"$args\""
+
+ puts_err "$print_error_msg"
+ puts_err "Exit code: $exit_code"
+ puts_err "Last 10 lines:\n[exec tail -10 << $error_msg]\n"
+
+ flow_fail
+ }
+}
+
+proc relpath {args} {
+ set from [lindex $args 0]
+ set to [lindex $args 1]
+ return [exec python3 -c "import os; print(os.path.relpath('$to', '$from'), end='')"]
+}
+
+proc run_openroad_script {args} {
+ # Note that this proc is not responsible for indexing its own logs.
+ set options {
+ {-indexed_log optional}
+ }
+
+ set flags {-netlist_in -gui}
+
+ parse_key_args "run_openroad_script" args arg_values $options flag_map $flags
+
+ set_if_unset arg_values(-indexed_log) /dev/null
+
+ set script [lindex $args 0]
+
+ if { [info exists flag_map(-gui)] } {
+ set args "$::env(OPENROAD_BIN) -gui $script |& tee $::env(TERMINAL_OUTPUT) $arg_values(-indexed_log)"
+ } else {
+ set args "$::env(OPENROAD_BIN) -exit $script |& tee $::env(TERMINAL_OUTPUT) $arg_values(-indexed_log)"
+ }
+
+ if { ! [catch { set cmd_log_file [open $::env(RUN_DIR)/cmds.log a+] } ]} {
+ set timestamp [clock format [clock seconds]]
+ puts $cmd_log_file "$timestamp - Executing \"$args\"\n"
+ close $cmd_log_file
+ }
+
+ set script_relative [relpath . $script]
+
+ puts_verbose "Executing OpenROAD with script '$script_relative'..."
+
+ set exit_code [catch {exec {*}$args } error_msg]
+
+ if { $exit_code } {
+ set tool [string range $args 0 [string first " " $args]]
+ set print_error_msg "during executing openroad script $script"
+
+ puts_err "$print_error_msg"
+ puts_err "Exit code: $exit_code"
+ puts_err "full log: [relpath $::env(PWD) $arg_values(-indexed_log)]"
+ puts_err "Last 10 lines:\n[exec tail -10 << $error_msg]\n"
+
+ save_state
+ puts_info "Creating reproducible..."
+
+ set reproducible_dir $::env(RUN_DIR)/openroad_issue_reproducible
+ set reproducible_dir_relative [relpath $::env(PWD) $reproducible_dir]
+
+ set or_issue_arg_list [list]
+
+ lappend or_issue_arg_list --output-dir $reproducible_dir
+ lappend or_issue_arg_list --or-script $script
+ lappend or_issue_arg_list --run-path $::env(RUN_DIR)
+
+ if { [info exists flag_map(-netlist_in)] } {
+ lappend or_issue_arg_list --netlist $::env(CURRENT_NETLIST)
+ } else {
+ lappend or_issue_arg_list $::env(CURRENT_DEF)
+ }
+
+ if {[catch {exec -ignorestderr python3 $::env(SCRIPTS_DIR)/or_issue.py {*}$or_issue_arg_list} result] == 0} {
+ puts_info "Reproducible packaged: Please tarball and upload $reproducible_dir_relative if you're going to submit an issue."
+ } else {
+ puts_err "Failed to package reproducible."
+ }
+
+ flow_fail
+ }
+}
+
+proc increment_index {args} {
+ set ::env(CURRENT_INDEX) [expr 1 + $::env(CURRENT_INDEX)]
+ puts "\[STEP $::env(CURRENT_INDEX)\]"
+}
+
+proc index_file {args} {
+ set file_full_name [lindex $args 0]
+
+ if { $file_full_name == "/dev/null" } {
+ # Can't index that :)
+ return $file_full_name
+ }
+
+ set file_path [file dirname $file_full_name]
+ set fbasename [file tail $file_full_name]
+ set fbasename "$::env(CURRENT_INDEX)-$fbasename"
+
+ set new_file_full_name "$file_path/$fbasename"
+ set replace [string map {/ \\/} $::env(CURRENT_INDEX)]
+ if { [info exists ::env(GLB_CFG_FILE)]} {
+ exec sed -i -e "s/\\(set ::env(CURRENT_INDEX)\\).*/\\1 $replace/" "$::env(GLB_CFG_FILE)"
+ }
+ return $new_file_full_name
+}
+
+proc flow_fail {args} {
+ if { ! [info exists ::env(FLOW_FAILED)] || ! $::env(FLOW_FAILED) } {
+ set ::env(FLOW_FAILED) 1
+ calc_total_runtime -status "flow failed"
+ generate_final_summary_report
+ save_state
+ puts_err "Flow failed."
+ show_warnings "The failure may have been because of the following warnings:"
+ return -code error
+ }
+}
+
+proc calc_total_runtime {args} {
+ ## Calculate Total Runtime
+ if {[info exists ::env(timer_start)] && [info exists ::env(START_TIME)]} {
+ puts_verbose "Calculating runtime..."
+ set ::env(timer_end) [clock seconds]
+ set options {
+ {-report optional}
+ {-status optional}
+ }
+ parse_key_args "calc_total_runtime" args arg_values $options
+ set_if_unset arg_values(-report) $::env(REPORTS_DIR)/total_runtime.txt
+ set_if_unset arg_values(-status) "flow completed"
+
+ exec python3 $::env(SCRIPTS_DIR)/write_runtime.py --conclude --seconds --time-in $::env(timer_end) $arg_values(-status)
+ }
+}
+
+# Value Color
+# 0 Black
+# 1 Red *******
+# 2 Green *******
+# 3 Yellow *******
+# 4 Blue
+# 5 Magenta
+# 6 Cyan *******
+# 7 White
+# 8 Not used
+# 9 Reset to default color
+proc color_text {color txt} {
+ if {[info exists ::env(TERM)] && $::env(TERM) != ""} {
+ return [exec tput setaf $color]$txt[exec tput setaf 9]
+ } else {
+ return $txt
+ }
+}
+
+proc puts_err {txt} {
+ set message "\[ERROR\]: $txt"
+ puts "[color_text 1 "$message"]"
+ if { [info exists ::env(RUN_DIR)] } {
+ exec echo $message >> $::env(RUN_DIR)/openlane.log
+ exec echo $message >> $::env(RUN_DIR)/errors.log
+ }
+}
+
+proc puts_success {txt} {
+ set message "\[SUCCESS\]: $txt"
+ puts "[color_text 2 "$message"]"
+ if { [info exists ::env(RUN_DIR)] } {
+ exec echo $message >> $::env(RUN_DIR)/openlane.log
+ }
+}
+
+proc puts_warn {txt} {
+ set message "\[WARNING\]: $txt"
+ puts "[color_text 3 "$message"]"
+ if { [info exists ::env(RUN_DIR)] } {
+ exec echo $message >> $::env(RUN_DIR)/openlane.log
+ exec echo $message >> $::env(RUN_DIR)/warnings.log
+ }
+}
+
+proc puts_info {txt} {
+ set message "\[INFO\]: $txt"
+ puts "[color_text 6 "$message"]"
+ if { [info exists ::env(RUN_DIR)] } {
+ exec echo $message >> $::env(RUN_DIR)/openlane.log
+ }
+}
+
+proc puts_verbose {txt} {
+ if { $::env(OPENLANE_VERBOSE) } {
+ set message "\[INFO\]: $txt"
+ puts "[color_text 6 "$message"]"
+ if { [info exists ::env(RUN_DIR)] } {
+ exec echo $message >> $::env(RUN_DIR)/openlane.log
+ }
+ }
+}
+
+proc show_warnings {msg} {
+ if { [info exists ::env(RUN_DIR)] && [file exists $::env(RUN_DIR)/warnings.log] } {
+ puts_info $msg
+ set warnings_file [open $::env(RUN_DIR)/warnings.log "r"]
+ set warnings [read $warnings_file]
+ close $warnings_file
+ puts $warnings
+ }
+}
+
+proc generate_routing_report {args} {
+ puts_info "Generating a partial report for routing..."
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(SCRIPTS_DIR)/gen_report_routing.py -d $::env(DESIGN_DIR) \
+ --design_name $::env(DESIGN_NAME) \
+ --tag $::env(RUN_TAG) \
+ --run_path $::env(RUN_DIR)
+}
+
+
+proc generate_final_summary_report {args} {
+ if { $::env(GENERATE_FINAL_SUMMARY_REPORT) == 0 } {
+ return
+ }
+ puts_info "Generating final set of reports..."
+ set options {
+ {-output optional}
+ {-man_report optional}
+ }
+ set flags {}
+ parse_key_args "generate_final_summary_report" args arg_values $options flags_map $flags
+
+ set_if_unset arg_values(-output) $::env(REPORTS_DIR)/metrics.csv
+ set_if_unset arg_values(-man_report) $::env(REPORTS_DIR)/manufacturability.rpt
+
+ try_catch $::env(OPENROAD_BIN) -python $::env(OPENLANE_ROOT)/scripts/generate_reports.py -d $::env(DESIGN_DIR) \
+ --design_name $::env(DESIGN_NAME) \
+ --tag $::env(RUN_TAG) \
+ --output_file $arg_values(-output) \
+ --man_report $arg_values(-man_report) \
+ --run_path $::env(RUN_DIR)
+
+ set man_report_rel [relpath . $arg_values(-man_report)]
+ set metrics_report_rel [relpath . $arg_values(-output)]
+
+ puts_info "Created manufacturability report at '$man_report_rel'."
+ puts_info "Created metrics report at '$metrics_report_rel'."
+}
+
+namespace eval TIMER {
+ variable timer_start
+ variable timer_end
+
+ proc timer_start {} {
+ variable timer_start
+ set timer_start [clock milliseconds]
+ }
+ proc timer_stop {} {
+ variable timer_end
+ set timer_end [clock milliseconds]
+ }
+
+ proc get_runtime {} {
+ variable timer_start
+ variable timer_end
+ set total_ms [expr {$timer_end - $timer_start }]
+ set runtime_ms [expr { int($total_ms) % 1000 }]
+ set runtime_s [expr { int(floor($total_ms) / 1000) % 60 }]
+ set runtime_m [expr { int(floor($total_ms / (1000*60))) % 60 }]
+ set runtime_h [expr { int(floor($total_ms / (1000*3600))) % 24 }]
+ set runtime "${runtime_h}h${runtime_m}m${runtime_s}s${runtime_ms}ms"
+ return $runtime
+ }
+}
+
+proc assert_files_exist {files} {
+ foreach f $files {
+ if { ! [file exists $f] } {
+ puts_err "$f doesn't exist."
+ flow_fail
+ } else {
+ puts_info "$f exists."
+ }
+ }
+}
+
+proc count_matches {pattern search_file} {
+ set count [exec bash -c "grep $pattern $search_file | wc -l"]
+ return $count
+}
+
+proc cat {args} {
+ set res {}
+ foreach file $args {
+ set f [open $file r]
+ set tmp [read $f]
+ close $f
+ append res $tmp
+ }
+ return $res
+}
+
+
+package provide openlane_utils 0.9
diff --git a/openlane/scripts/widen_site_lef.py b/openlane/scripts/widen_site_lef.py
new file mode 100644
index 0000000..1b7f174
--- /dev/null
+++ b/openlane/scripts/widen_site_lef.py
@@ -0,0 +1,85 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import argparse
+
+parser = argparse.ArgumentParser(description="produces a widened site lef")
+
+parser.add_argument("--lefFile", "-l", required=True, help="Input LEF")
+
+parser.add_argument(
+ "--widenValue",
+ "-w",
+ help="widen value to be used as a factor or an absolute value based on the factor flage",
+)
+
+parser.add_argument(
+ "--factor",
+ "-f",
+ action="store_true",
+ default=False,
+ help="use the widen value as a factor or an absolute value",
+)
+
+
+parser.add_argument(
+ "--output", "-o", required=True, help="output file to store results"
+)
+
+args = parser.parse_args()
+lef_file_name = args.lefFile
+widenValue = args.widenValue
+isFactor = args.factor
+out_file_name = args.output
+
+# reading lef
+lefFileOpener = open(lef_file_name, "r")
+if lefFileOpener.mode == "r":
+ lefContent = lefFileOpener.read().split("\n")
+lefFileOpener.close()
+
+
+startFlag = False
+doneFlag = False
+for i in range(len(lefContent)):
+ # looking for SITE
+ if lefContent[i].find("SITE") != -1:
+ startFlag = True
+
+ if startFlag:
+ # looking for SIZE
+ if lefContent[i].find("SIZE") != -1:
+ line = lefContent[i].split(" ")
+ for j in range(len(line)):
+ if line[j] == "SIZE":
+ # if a factor modify the value by the factor
+ for x in range(j + 1, len(line)):
+ if line[x] != "":
+ if isFactor:
+ orgVal = float(line[x])
+ widenValue = float(widenValue) * orgVal
+ # change the value
+ line[x] = str(widenValue)
+ doneFlag = True
+ break
+ break
+ lefContent[i] = " ".join(line)
+
+ if doneFlag:
+ break
+
+# writing to output file
+outFileOpener = open(out_file_name, "w")
+outFileOpener.write("\n".join(lefContent))
+outFileOpener.close()
diff --git a/openlane/scripts/write_powered_def.py b/openlane/scripts/write_powered_def.py
new file mode 100644
index 0000000..9688b1a
--- /dev/null
+++ b/openlane/scripts/write_powered_def.py
@@ -0,0 +1,300 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import sys
+import argparse
+from subprocess import Popen, PIPE
+import odb
+
+parser = argparse.ArgumentParser(
+ description="Add cell power connections in the netlist. Useful for LVS purposes."
+)
+
+parser.add_argument("--input-def", "-d", required=True, help="DEF view of the design")
+
+parser.add_argument(
+ "--input-lef",
+ "-l",
+ required=True,
+ help="LEF file needed to have a proper view of the design. Every cell having a pin labeled as a power pin (e.g., USE POWER) will be connected to the power/ground port of the design.",
+)
+
+parser.add_argument(
+ "--power-port",
+ "-v",
+ help="Name of the power port of the design. The power pin of the subcells will be connected to it by default",
+)
+
+parser.add_argument(
+ "--ground-port",
+ "-g",
+ help="Name of the ground port of the design. The ground pin of the subcells will be connected to it by default",
+)
+
+parser.add_argument(
+ "--powered-netlist",
+ "-pv",
+ help="A structural verilog netlist, readable by openroad, that includes extra power connections that are to be applied after connecting to the default power-port and ground-port specified.",
+)
+
+parser.add_argument("--ignore-missing-pins", "-q", action="store_true", required=False)
+
+parser.add_argument(
+ "--output", "-o", default="output.def", help="Output modified netlist"
+)
+
+# parser.add_argument('--create-pg-ports',
+# help='Create power and ground ports if not found')
+
+args = parser.parse_args()
+
+def_file_name = args.input_def
+lef_file_name = args.input_lef
+power_port_name = args.power_port
+ground_port_name = args.ground_port
+
+powered_netlist_file_name = args.powered_netlist
+
+ignore_missing_pins = args.ignore_missing_pins
+
+output_file_name = args.output
+
+
+def get_power_ground_ports(ports):
+ vdd_ports = []
+ gnd_ports = []
+ for port in ports:
+ if port.getSigType() == "POWER" or port.getName() == power_port_name:
+ vdd_ports.append(port)
+ elif port.getSigType() == "GROUND" or port.getName() == ground_port_name:
+ gnd_ports.append(port)
+ return (vdd_ports, gnd_ports)
+
+
+def find_power_ground_port(port_name, ports):
+ for port in ports:
+ if port.getName() == port_name:
+ return port
+ return None
+
+
+db = odb.dbDatabase.create()
+
+odb.read_lef(db, lef_file_name)
+odb.read_def(db, def_file_name)
+
+chip = db.getChip()
+block = chip.getBlock()
+design_name = block.getName()
+
+print("Top-level design name:", design_name)
+
+VDD_PORTS, GND_PORTS = get_power_ground_ports(block.getBTerms())
+assert (
+ VDD_PORTS and GND_PORTS
+), "No power ports found at the top-level. Make sure that they exist and have the USE POWER|GROUND property or they match the arguments specified with --power-port and --ground-port."
+
+vdd_net_idx = None
+for index, port in enumerate(VDD_PORTS):
+ if port.getNet().getName() == power_port_name:
+ vdd_net_idx = index
+
+gnd_net_idx = None
+for index, port in enumerate(GND_PORTS):
+ if port.getNet().getName() == ground_port_name:
+ gnd_net_idx = index
+
+assert (
+ vdd_net_idx is not None
+), "Can't find power net at the top-level. Make sure that argument specified with --power-port."
+
+assert (
+ gnd_net_idx is not None
+), "Can't find ground net at the top-level. Make sure that argument specified with --ground-port."
+
+DEFAULT_VDD = VDD_PORTS[vdd_net_idx].getNet()
+DEFAULT_GND = GND_PORTS[gnd_net_idx].getNet()
+
+print("Default power net: ", DEFAULT_VDD.getName())
+print("Default ground net:", DEFAULT_GND.getName())
+
+print("Found a total of", len(VDD_PORTS), "power ports.")
+print("Found a total of", len(GND_PORTS), "ground ports.")
+
+modified_cells = 0
+cells = block.getInsts()
+for cell in cells:
+ iterms = cell.getITerms()
+ cell_name = cell.getName()
+ if len(iterms) == 0:
+ continue
+
+ VDD_ITERMS = []
+ GND_ITERMS = []
+ VDD_ITERM_BY_NAME = None
+ GND_ITERM_BY_NAME = None
+ for iterm in iterms:
+ if iterm.getSigType() == "POWER":
+ VDD_ITERMS.append(iterm)
+ elif iterm.getSigType() == "GROUND":
+ GND_ITERMS.append(iterm)
+ elif iterm.getMTerm().getName() == power_port_name:
+ VDD_ITERM_BY_NAME = iterm
+ elif iterm.getMTerm().getName() == ground_port_name: # note **PORT**
+ GND_ITERM_BY_NAME = iterm
+
+ if len(VDD_ITERMS) == 0:
+ print(
+ "Warning: No pins in the LEF view of", cell_name, " marked for use as power"
+ )
+ print(
+ "Warning: Attempting to match power pin by name (using top-level port name) for cell:",
+ cell_name,
+ )
+ if VDD_ITERM_BY_NAME is not None: # note **PORT**
+ print("Found", power_port_name, "using that as a power pin")
+ VDD_ITERMS.append(VDD_ITERM_BY_NAME)
+
+ if len(GND_ITERMS) == 0:
+ print(
+ "Warning: No pins in the LEF view of",
+ cell_name,
+ " marked for use as ground",
+ )
+ print(
+ "Warning: Attempting to match ground pin by name (using top-level port name) for cell:",
+ cell_name,
+ )
+ if GND_ITERM_BY_NAME is not None: # note **PORT**
+ print("Found", ground_port_name, "using that as a ground pin")
+ GND_ITERMS.append(GND_ITERM_BY_NAME)
+
+ if len(VDD_ITERMS) == 0 or len(GND_ITERMS) == 0:
+ print("Warning: not all power pins found for cell:", cell_name)
+ if ignore_missing_pins:
+ print("Warning: ignoring", cell_name, "!!!!!!!")
+ continue
+ else:
+ print("Exiting... Use --ignore-missing-pins to ignore such errors")
+ sys.exit(1)
+
+ if len(VDD_ITERMS) > 2:
+ print("Warning: cell", cell_name, "has", len(VDD_ITERMS), "power pins.")
+
+ if len(GND_ITERMS) > 2:
+ print("Warning: cell", cell_name, "has", len(GND_ITERMS), "ground pins.")
+
+ for VDD_ITERM in VDD_ITERMS:
+ if VDD_ITERM.isConnected():
+ pin_name = VDD_ITERM.getMTerm().getName()
+ cell_name = cell_name
+ print(
+ "Warning: power pin", pin_name, "of", cell_name, "is already connected"
+ )
+ print("Warning: ignoring", cell_name + "/" + pin_name, "!!!!!!!")
+ else:
+ VDD_ITERM.connect(DEFAULT_VDD)
+
+ for GND_ITERM in GND_ITERMS:
+ if GND_ITERM.isConnected():
+ pin_name = GND_ITERM.getMTerm().getName()
+ cell_name = cell_name
+ print(
+ "Warning: ground pin", pin_name, "of", cell_name, "is already connected"
+ )
+ print("Warning: ignoring", cell_name + "/" + pin_name, "!!!!!!!")
+ else:
+ GND_ITERM.connect(DEFAULT_GND)
+
+ modified_cells += 1
+
+print(
+ "Modified power connections of",
+ modified_cells,
+ "cells (Remaining:",
+ len(cells) - modified_cells,
+ ").",
+)
+
+# apply extra special connections taken from another netlist:
+if powered_netlist_file_name is not None and os.path.exists(powered_netlist_file_name):
+ tmp_def_file = f"{os.path.splitext(powered_netlist_file_name)[0]}.def"
+ openroad_script = []
+ openroad_script.append(f"read_lef {lef_file_name}")
+ openroad_script.append(f"read_verilog {powered_netlist_file_name}")
+ openroad_script.append(f"link_design {design_name}")
+ openroad_script.append(f"write_def {tmp_def_file}")
+ openroad_script.append("exit")
+
+ p = Popen(["openroad"], stdout=PIPE, stdin=PIPE, stderr=PIPE, encoding="utf8")
+
+ openroad_script = "\n".join(openroad_script)
+
+ output = p.communicate(openroad_script)
+ print("STDOUT:")
+ print(output[0].strip())
+ print("STDERR:")
+ print(output[1].strip())
+ print("openroad exit code:", p.returncode)
+ assert p.returncode == 0, p.returncode
+ assert os.path.exists(tmp_def_file), "DEF file doesn't exist"
+
+ db_power = odb.dbDatabase.create()
+ odb.read_lef(db_power, lef_file_name)
+ odb.read_def(db_power, tmp_def_file)
+ chip_power = db_power.getChip()
+ block_power = chip_power.getBlock()
+ assert block_power.getName() == design_name
+ print("Successfully created a new database")
+ POWER_GROUND_PORT_NAMES = [port.getName() for port in VDD_PORTS + GND_PORTS]
+
+ # using get_power_ground_ports doesn't work since the pins weren't
+ # created using pdngen
+ power_ground_ports = [
+ port
+ for port in block_power.getBTerms()
+ if port.getName() in POWER_GROUND_PORT_NAMES
+ ]
+
+ for port in power_ground_ports:
+ iterms = port.getNet().getITerms()
+ for iterm in iterms:
+ inst_name = iterm.getInst().getName()
+ pin_name = iterm.getMTerm().getName()
+
+ original_inst = block.findInst(inst_name)
+ assert original_inst is not None, (
+ "Instance "
+ + inst_name
+ + " not found in the original netlist. Perhaps it was optimized out during synthesis?"
+ )
+
+ original_iterm = original_inst.findITerm(pin_name)
+ assert original_iterm is not None, (
+ inst_name + " doesn't have a pin named " + pin_name
+ )
+
+ original_port = find_power_ground_port(
+ port.getName(), VDD_PORTS + GND_PORTS
+ )
+ assert original_port is not None, (
+ port.getName() + " not found in the original netlist."
+ )
+
+ original_iterm.connect(original_port.getNet())
+ print("Modified connections between", port.getName(), "and", inst_name)
+
+odb.write_def(block, output_file_name)
diff --git a/openlane/scripts/write_runtime.py b/openlane/scripts/write_runtime.py
new file mode 100644
index 0000000..cc71c7f
--- /dev/null
+++ b/openlane/scripts/write_runtime.py
@@ -0,0 +1,147 @@
+# Copyright 2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import re
+import sys
+import yaml
+import click
+from typing import List, Optional
+
+
+def timestamp_to_seconds(runtime: str) -> Optional[float]:
+ pattern = re.compile(r"\s*([\d+]+)h([\d+]+)m([\d+]+)s(?:([\d+]+)+ms)?")
+ m = pattern.match(runtime)
+ if m is None:
+ return None
+ time = (
+ int(m.group(1)) * 60 * 60
+ + int(m.group(2)) * 60
+ + int(m.group(3))
+ + int(m.group(4) or 0) / 1000.0
+ )
+ return time
+
+
+def seconds_to_timestamp(runtime: float) -> str:
+ hours = int(runtime // 3600)
+ minutes_and_seconds_and_milliseconds = runtime % 3600
+ minutes = int(minutes_and_seconds_and_milliseconds // 60)
+ seconds_and_milliseconds = minutes_and_seconds_and_milliseconds % 60
+ seconds = int(seconds_and_milliseconds // 1)
+ milliseconds = int((seconds_and_milliseconds % 1) * 1000)
+ return f"{hours}h{minutes}m{seconds}s{milliseconds}ms"
+
+
+runtime_file_path: str = os.path.join(os.environ["RUN_DIR"], "runtime.yaml")
+
+
+def read_runtime_yaml():
+ runtime_data_str: str = "[]"
+ try:
+ runtime_data_str = open(runtime_file_path).read()
+ except FileNotFoundError:
+ pass
+
+ yaml_docs: List[List] = list(yaml.safe_load_all(runtime_data_str))
+
+ return yaml_docs[0]
+
+
+def write_runtime(status: str, time_in: float):
+ runtime_data = read_runtime_yaml()
+
+ obj = {}
+ obj["status"] = f"{os.environ['CURRENT_INDEX']} - {status}"
+ obj["runtime_s"] = round(time_in, 2)
+ obj["runtime_ts"] = seconds_to_timestamp(time_in)
+
+ runtime_data.append(obj)
+
+ with open(runtime_file_path, "w") as f:
+ f.write(yaml.safe_dump(runtime_data, sort_keys=False))
+
+
+def conclude_run(status: str, time_in: float):
+ runtime_data = read_runtime_yaml()
+
+ final_runtime_data = []
+
+ timer_start = os.getenv("timer_start")
+ if timer_start is None:
+ raise Exception(
+ "Attempted to conclude a run without timer_start environment variable set"
+ )
+ timer_start = float(timer_start)
+
+ timer_routed = os.getenv("timer_routed")
+ routed_s = -1
+ routed_ts = "-1"
+ if timer_routed is not None:
+ timer_routed = float(timer_routed)
+ routed_s = timer_routed - timer_start
+ routed_ts = seconds_to_timestamp(routed_s)
+
+ obj = {}
+ obj["status"] = "routed"
+ obj["runtime_s"] = routed_s
+ obj["runtime_ts"] = routed_ts
+ final_runtime_data.append(obj)
+
+ done_s = time_in - timer_start
+ done_ts = seconds_to_timestamp(done_s)
+
+ obj = {}
+ obj["status"] = status
+ obj["runtime_s"] = done_s
+ obj["runtime_ts"] = done_ts
+ final_runtime_data.append(obj)
+
+ with open(runtime_file_path, "w") as f:
+ f.write(yaml.safe_dump_all([runtime_data, final_runtime_data], sort_keys=False))
+
+
+@click.command("write_runtime")
+@click.option("--conclude/--no-conclude", default=False)
+@click.option(
+ "--seconds/--timestamp",
+ "seconds",
+ default=False,
+ help="Process the input string either as a timestamp or a floating point second value",
+)
+@click.option(
+ "--time-in",
+ default=None,
+ help="If this argument is not specified, time is read from stdin.",
+)
+@click.argument("status")
+def cli(seconds, conclude, time_in, status):
+ if time_in is None:
+ time_in = sys.stdin.read().rstrip()
+
+ if seconds:
+ time_in = float(time_in)
+ else:
+ temp = timestamp_to_seconds(time_in)
+ if temp is None:
+ raise Exception(f"Invalid timestamp {time_in}")
+ time_in = temp
+
+ if conclude:
+ conclude_run(status, time_in)
+ else:
+ write_runtime(status, time_in)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/scripts/yosys/logic_equiv_check.tcl b/openlane/scripts/yosys/logic_equiv_check.tcl
new file mode 100755
index 0000000..13e3e51
--- /dev/null
+++ b/openlane/scripts/yosys/logic_equiv_check.tcl
@@ -0,0 +1,122 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+yosys -import
+
+if { [info exists ::env(FP_WELLTAP_CELL)] && $::env(FP_WELLTAP_CELL) ne ""} {
+ set well_tap_cell "$::env(FP_WELLTAP_CELL)"
+}
+set decap_cell_wildcard "$::env(DECAP_CELL)*"
+set fill_cell_wildcard "$::env(FILL_CELL)*"
+
+set vtop $::env(DESIGN_NAME)
+#set sdc_file $::env(SDC_FILE)
+
+# LHS
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ puts "Defining $define"
+ verilog_defines -D$define
+ }
+}
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -lib $verilog_file
+ }
+}
+foreach lib $::env(LIB_SYNTH_COMPLETE_NO_PG) {
+ read_liberty -nooverwrite -lib -ignore_miss_dir -setattr blackbox $lib
+}
+
+read_verilog $::env(LEC_LHS_NETLIST)
+rmports
+if { [info exists well_tap_cell] } {
+ hierarchy -generate $well_tap_cell
+}
+hierarchy -generate $decap_cell_wildcard
+hierarchy -generate $fill_cell_wildcard
+splitnets -ports;;
+hierarchy -auto-top
+if { $::env(SYNTH_FLAT_TOP) } {
+ flatten
+}
+setattr -set keep 1
+stat
+renames -top gold
+design -stash gold
+
+
+# RHS
+# Rebuild the database due to -stash
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ puts "Defining $define"
+ verilog_defines -D$define
+ }
+}
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -lib $verilog_file
+ }
+}
+foreach lib $::env(LIB_SYNTH_COMPLETE_NO_PG) {
+ read_liberty -nooverwrite -lib -ignore_miss_dir -setattr blackbox $lib
+}
+
+read_verilog $::env(LEC_RHS_NETLIST)
+rmports
+if { [info exists well_tap_cell] } {
+ hierarchy -generate $well_tap_cell
+}
+hierarchy -generate $decap_cell_wildcard
+hierarchy -generate $fill_cell_wildcard
+splitnets -ports;;
+hierarchy -auto-top
+if { $::env(SYNTH_FLAT_TOP) } {
+ flatten
+}
+setattr -set keep 1
+stat
+renames -top gate
+design -stash gate
+
+
+design -copy-from gold -as gold gold
+design -copy-from gate -as gate gate
+
+# Rebuild the database due to -stash
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ puts "Defining $define"
+ verilog_defines -D$define
+ }
+}
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -lib $verilog_file
+ }
+}
+foreach lib $::env(LIB_SYNTH_COMPLETE_NO_PG) {
+ read_liberty -nooverwrite -lib -ignore_miss_dir -setattr blackbox $lib
+}
+
+equiv_make gold gate equiv
+if { [info exists well_tap_cell] } {
+ hierarchy -generate $well_tap_cell
+}
+hierarchy -generate $decap_cell_wildcard
+hierarchy -generate $fill_cell_wildcard
+setattr -set keep 1
+prep -flatten -top equiv
+equiv_simple -seq 10 -v
+equiv_status -assert
diff --git a/openlane/scripts/yosys/rewrite_verilog.tcl b/openlane/scripts/yosys/rewrite_verilog.tcl
new file mode 100755
index 0000000..42cc14d
--- /dev/null
+++ b/openlane/scripts/yosys/rewrite_verilog.tcl
@@ -0,0 +1,18 @@
+# Copyright 2020-2021 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+yosys -import
+
+read_verilog "$::env(SAVE_NETLIST)"; # usually from openroad
+
+write_verilog -noattr -noexpr -nohex -nodec "$::env(SAVE_NETLIST)"; # mainly to get explicit wire declarations
diff --git a/openlane/scripts/yosys/synth.tcl b/openlane/scripts/yosys/synth.tcl
new file mode 100755
index 0000000..3ff9653
--- /dev/null
+++ b/openlane/scripts/yosys/synth.tcl
@@ -0,0 +1,395 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+yosys -import
+
+# inputs expected as env vars
+set buffering $::env(SYNTH_BUFFERING)
+set sizing $::env(SYNTH_SIZING)
+set vtop $::env(DESIGN_NAME)
+set sclib $::env(LIB_SYNTH)
+if {[info exists ::env(DFF_LIB_SYNTH)]} {
+ set dfflib $::env(DFF_LIB_SYNTH)
+} else {
+ set dfflib $sclib
+}
+#set opt $::env(SYNTH_OPT)
+#set sdc_file $::env(SDC_FILE)
+
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ log "Defining $define"
+ verilog_defines -D$define
+ }
+}
+
+set vIdirsArgs ""
+if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
+ foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+ lappend vIdirsArgs "-I$dir"
+ }
+ set vIdirsArgs [join $vIdirsArgs]
+}
+
+if { $::env(SYNTH_READ_BLACKBOX_LIB) } {
+ log "Reading $::env(LIB_SYNTH_COMPLETE_NO_PG) as a blackbox"
+ foreach lib $::env(LIB_SYNTH_COMPLETE_NO_PG) {
+ read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+}
+
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -sv -lib {*}$vIdirsArgs $verilog_file
+ }
+}
+
+
+# ns expected (in sdc as well)
+set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
+
+set driver $::env(SYNTH_DRIVING_CELL)
+set cload $::env(SYNTH_CAP_LOAD)
+# input pin cap of IN_3VX8
+set max_FO $::env(SYNTH_MAX_FANOUT)
+if {![info exist ::env(SYNTH_MAX_TRAN)]} {
+ set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
+} else {
+ set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
+}
+set max_Tran $::env(SYNTH_MAX_TRAN)
+
+
+# Mapping parameters
+set A_factor 0.00
+set B_factor 0.88
+set F_factor 0.00
+
+# Don't change these unless you know what you are doing
+set stat_ext ".stat.rpt"
+set chk_ext ".chk.rpt"
+set gl_ext ".gl.v"
+set constr_ext ".$clock_period.constr"
+set timing_ext ".timing.txt"
+set abc_ext ".abc"
+
+
+# get old sdc, add library specific stuff for abc scripts
+set sdc_file $::env(synthesis_tmpfiles)/synthesis.sdc
+set outfile [open ${sdc_file} w]
+#puts $outfile $sdc_data
+puts $outfile "set_driving_cell ${driver}"
+puts $outfile "set_load ${cload}"
+close $outfile
+
+
+# Assemble Scripts (By Strategy)
+set abc_rs_K "resub,-K,"
+set abc_rs "resub"
+set abc_rsz "resub,-z"
+set abc_rw_K "rewrite,-K,"
+set abc_rw "rewrite"
+set abc_rwz "rewrite,-z"
+set abc_rf "refactor"
+set abc_rfz "refactor,-z"
+set abc_b "balance"
+
+set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
+set abc_share "strash; multi,-m; ${abc_resyn2}"
+set abc_resyn2a "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
+set abc_resyn3 "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
+set abc_resyn2rs "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
+
+set abc_choice "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+set abc_choice2 "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+
+set abc_map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set abc_map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area "retime,-D,{D},-M,5"
+set abc_retime_dly "retime,-D,{D},-M,6"
+set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+set abc_area_recovery_1 "${abc_choice}; map;"
+set abc_area_recovery_2 "${abc_choice2}; map;"
+
+set map_old_cnt "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set map_old_dly "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area "retime,-D,{D},-M,5"
+set abc_retime_dly "retime,-D,{D},-M,6"
+set abc_map_new_area "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+if {$buffering==1} {
+ set abc_fine_tune "buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
+} elseif {$sizing} {
+ set abc_fine_tune "upsize,{D};dnsize,{D}"
+} else {
+ set abc_fine_tune ""
+}
+
+
+set delay_scripts [list \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ "+read_constr,${sdc_file};&get -n;&st;&dch;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;buffer -c -N ${max_FO};topo;stime -c;upsize -c;dnsize -c;;stime,-p;print_stats -m" \
+]
+
+set area_scripts [list \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ \
+ "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \
+ "+read_constr,${sdc_file};strash;dch;map -B 0.9;topo;stime -c;buffer -c -N ${max_FO};upsize -c;dnsize -c;stime,-p;print_stats -m" \
+]
+
+set all_scripts [list {*}$delay_scripts {*}$area_scripts]
+
+set strategy_parts [split $::env(SYNTH_STRATEGY)]
+
+proc synth_strategy_format_err { } {
+ upvar area_scripts area_scripts
+ upvar delay_scripts delay_scripts
+ log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
+ log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
+ exit 1
+}
+
+if { [llength $strategy_parts] != 2 } {
+ synth_strategy_format_err
+}
+
+set strategy_type [lindex $strategy_parts 0]
+set strategy_type_idx [lindex $strategy_parts 1]
+
+if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
+ log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
+ synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
+ log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+ synth_strategy_format_err
+}
+
+if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
+ log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+ synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" } {
+ set strategy_script [lindex $delay_scripts $strategy_type_idx]
+ set strategy_name "DELAY $strategy_type_idx"
+} else {
+ set strategy_script [lindex $area_scripts $strategy_type_idx]
+ set strategy_name "AREA $strategy_type_idx"
+}
+
+# Get Adder Type
+set adder_type $::env(SYNTH_ADDER_TYPE)
+if { !($adder_type in [list "YOSYS" "FA" "RCA" "CSA"]) } {
+ log -stderr "\[ERROR] Misformatted SYNTH_ADDER_TYPE (\"$::env(SYNTH_ADDER_TYPE)\")."
+ log -stderr "\[ERROR] Correct format is \"YOSYS|FA|RCA|CSA\"."
+ exit 1
+}
+
+# Start Synthesis
+for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
+ read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
+}
+
+select -module $vtop
+show -format dot -prefix $::env(synthesis_tmpfiles)/hierarchy
+select -clear
+
+hierarchy -check -top $vtop
+
+# Infer tri-state buffers.
+set tbuf_map false
+if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
+ if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
+ set tbuf_map true
+ tribuf
+ } else {
+ log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
+ }
+}
+
+# Handle technology mapping of RCS/CSA adders
+if { $adder_type == "RCA"} {
+ if { [info exists ::env(RIPPLE_CARRY_ADDER_MAP)] && [file exists $::env(RIPPLE_CARRY_ADDER_MAP)] } {
+ techmap -map $::env(RIPPLE_CARRY_ADDER_MAP)
+ }
+} elseif { $adder_type == "CSA"} {
+ if { [info exists ::env(CARRY_SELECT_ADDER_MAP)] && [file exists $::env(CARRY_SELECT_ADDER_MAP)] } {
+ techmap -map $::env(CARRY_SELECT_ADDER_MAP)
+ }
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+ synth -top $vtop
+} else {
+ synth -top $vtop -flatten
+}
+
+if { $::env(SYNTH_EXTRA_MAPPING_FILE) ne "" } {
+ if { [file exists $::env(SYNTH_EXTRA_MAPPING_FILE)] } {
+ log "\[INFO\] applying mappings in $::env(SYNTH_EXTRA_MAPPING_FILE)"
+ techmap -map $::env(SYNTH_EXTRA_MAPPING_FILE)
+ } else {
+ log -stderr "\[ERROR] file not found $::env(SYNTH_EXTRA_MAPPING_FILE)."
+ }
+}
+
+show -format dot -prefix $::env(synthesis_tmpfiles)/post_techmap
+
+if { $::env(SYNTH_SHARE_RESOURCES) } {
+ share -aggressive
+}
+
+set fa_map false
+if { $adder_type == "FA" } {
+ if { [info exists ::env(FULL_ADDER_MAP)] && [file exists $::env(FULL_ADDER_MAP)] } {
+ extract_fa -fa -v
+ extract_fa -ha -v
+ set fa_map true
+ }
+}
+
+opt
+opt_clean -purge
+
+tee -o "$::env(synth_report_prefix)_pre.stat" stat
+
+# Map tri-state buffers
+if { $tbuf_map } {
+ log {mapping tbuf}
+ techmap -map $::env(TRISTATE_BUFFER_MAP)
+ simplemap
+}
+
+# Map full adders
+if { $fa_map } {
+ techmap -map $::env(FULL_ADDER_MAP)
+}
+
+# Handle technology mapping of latches
+if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
+ techmap -map $::env(SYNTH_LATCH_MAP)
+ simplemap
+}
+
+dfflibmap -liberty $dfflib
+tee -o "$::env(synth_report_prefix)_dff.stat" stat
+
+proc run_strategy {output script ext} {
+ upvar clock_period clock_period
+ upvar sdc_file sdc
+ upvar sclib lib
+
+ log "\[INFO\]: USING STRATEGY $ext"
+
+ design -load checkpoint
+
+ abc -D "$clock_period" \
+ -constr "$sdc" \
+ -liberty "$lib" \
+ -script "$script" \
+ -showtmp
+
+ setundef -zero
+
+ hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+ splitnets
+ opt_clean -purge
+ insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+ tee -o "$::env(synth_report_prefix).$ext.chk.rpt" check
+ tee -o "$::env(synth_report_prefix).$ext.stat.rpt" stat -top $::env(DESIGN_NAME) -liberty [lindex $::env(LIB_SYNTH_COMPLETE_NO_PG) 0]
+ write_verilog -noattr -noexpr -nohex -nodec -defparam $output
+ design -reset
+}
+design -save checkpoint
+
+# Explore/Finalize
+if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
+ for { set index 0 } { $index < [llength $delay_scripts] } { incr index } {
+ set name "DELAY$index"
+ run_strategy\
+ "$::env(synthesis_results)/$::env(DESIGN_NAME).$name.v"\
+ [lindex $delay_scripts $index]\
+ "$name"
+ }
+
+ for { set index 0 } { $index < [llength $area_scripts] } { incr index } {
+ set name "AREA$index"
+ run_strategy\
+ "$::env(synthesis_results)/$::env(DESIGN_NAME).$name.v"\
+ [lindex $area_scripts $index]\
+ "$name"
+ }
+} else {
+ run_strategy\
+ "$::env(SAVE_NETLIST)"\
+ "$strategy_script"\
+ "$strategy_name"
+
+ if { $::env(SYNTH_NO_FLAT) } {
+ design -reset
+
+ if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ log "Defining $define"
+ verilog_defines -D$define
+ }
+ }
+
+ foreach lib $::env(LIB_SYNTH_COMPLETE_NO_PG) {
+ read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+
+ if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+ }
+
+ if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -sv -lib {*}$vIdirsArgs $verilog_file
+ }
+ }
+
+ file copy -force $::env(SAVE_NETLIST) $::env(synthesis_results)/$::env(DESIGN_NAME).hierarchy.v
+ read_verilog -sv $::env(SAVE_NETLIST)
+ synth -top $vtop -flatten
+
+ design -save checkpoint
+ run_strategy\
+ "$::env(SAVE_NETLIST)"\
+ "$strategy_script"\
+ "$strategy_name"
+ }
+
+}
diff --git a/openlane/scripts/yosys/synth_top.tcl b/openlane/scripts/yosys/synth_top.tcl
new file mode 100755
index 0000000..8ed7ebd
--- /dev/null
+++ b/openlane/scripts/yosys/synth_top.tcl
@@ -0,0 +1,84 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+yosys -import
+
+set vtop $::env(DESIGN_NAME)
+set sclib $::env(LIB_SYNTH)
+#set sdc_file $::env(SDC_FILE)
+
+set stat_ext ".stat.rpt"
+set chk_ext ".chk.rpt"
+set gl_ext ".gl.v"
+set timing_ext ".timing.txt"
+set abc_ext ".abc"
+
+if { $::env(SYNTH_READ_BLACKBOX_LIB) } {
+ foreach lib $::env(LIB_SYNTH_COMPLETE_NO_PG) {
+ read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+}
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+ foreach lib $::env(EXTRA_LIBS) {
+ read_liberty -lib -ignore_miss_dir -setattr blackbox $lib
+ }
+}
+
+
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+ foreach define $::env(SYNTH_DEFINES) {
+ verilog_defines -D$define
+ }
+}
+
+set vIdirsArgs ""
+if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
+ foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+ lappend vIdirsArgs "-I$dir"
+ }
+ set vIdirsArgs [join $vIdirsArgs]
+}
+
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+ foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+ read_verilog -lib {*}$vIdirsArgs $verilog_file
+ }
+}
+
+
+for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
+ read_verilog {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
+}
+
+select -module $vtop
+show -format dot -prefix $::env(synthesis_tmpfiles)/hierarchy
+select -clear
+
+hierarchy -check -top $vtop
+if { $::env(SYNTH_FLAT_TOP) } {
+ flatten
+}
+
+setattr -set keep 1
+#synth -top $vtop
+tee -o "$::env(synth_report_prefix).stat" stat
+
+
+#debug opt_clean -purge
+#setundef -zero
+splitnets
+opt_clean -purge
+tee -o "$::env(synth_report_prefix)$chk_ext" check
+tee -o "$::env(synth_report_prefix)$stat_ext" stat -top $vtop -liberty $sclib
+write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
diff --git a/openlane/scripts/zeroize_origin_lef.py b/openlane/scripts/zeroize_origin_lef.py
new file mode 100755
index 0000000..2f05789
--- /dev/null
+++ b/openlane/scripts/zeroize_origin_lef.py
@@ -0,0 +1,50 @@
+#!/usr/bin/env python3
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+takes a lef file and a rectangle => trims all RECT statements within the area
+"""
+import re
+import sys
+
+RECT_REGEX = (
+ r"^\s*RECT\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+;$"
+)
+ORIGIN_REGEX = r"^\s*ORIGIN\s+(-?\d+\.?\d*)\s+(-?\d+\.?\d*)\s+;$"
+
+OFFSET_X = OFFSET_Y = 0
+for line in sys.stdin:
+ if line.isspace():
+ continue
+ origin_match = re.search(ORIGIN_REGEX, line)
+ if origin_match:
+ OFFSET_X, OFFSET_Y = float(origin_match.group(1)), float(origin_match.group(2))
+ print(line[: line.find("O")] + "ORIGIN %.3f %.3f ;" % (0, 0))
+ else:
+ rect_match = re.search(RECT_REGEX, line)
+ if rect_match:
+ llx, lly, urx, ury = (
+ float(rect_match.group(1)),
+ float(rect_match.group(2)),
+ float(rect_match.group(3)),
+ float(rect_match.group(4)),
+ )
+ print(
+ line[: line.find("R")]
+ + "RECT %.3f %.3f %.3f %.3f ;"
+ % (llx + OFFSET_X, lly + OFFSET_Y, urx + OFFSET_X, ury + OFFSET_Y)
+ )
+ else:
+ print(line, end="")
diff --git a/openlane/tests/.gitignore b/openlane/tests/.gitignore
new file mode 100644
index 0000000..bc0a362
--- /dev/null
+++ b/openlane/tests/.gitignore
@@ -0,0 +1,8 @@
+*/runs/
+*/lef/
+*/gds/
+*/mag/
+*/config*.tcl
+*/base_config.tcl
+!*/config.tcl
+!*/script.tcl
diff --git a/openlane/tests/1007/.gitignore b/openlane/tests/1007/.gitignore
new file mode 100644
index 0000000..30a3007
--- /dev/null
+++ b/openlane/tests/1007/.gitignore
@@ -0,0 +1 @@
+out.def
\ No newline at end of file
diff --git a/openlane/tests/1007/config.tcl b/openlane/tests/1007/config.tcl
new file mode 100644
index 0000000..967e0ed
--- /dev/null
+++ b/openlane/tests/1007/config.tcl
@@ -0,0 +1 @@
+set ::env(DESIGN_NAME) inverter
\ No newline at end of file
diff --git a/openlane/tests/1007/hooks/post_run.py b/openlane/tests/1007/hooks/post_run.py
new file mode 100644
index 0000000..f873d37
--- /dev/null
+++ b/openlane/tests/1007/hooks/post_run.py
@@ -0,0 +1,42 @@
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+import odb
+
+
+class OdbReader(object):
+ def __init__(self, lef_in, def_in):
+ self.db = odb.dbDatabase.create()
+ self.lef = odb.read_lef(self.db, lef_in)
+ self.df = odb.read_def(self.db, def_in)
+ self.block = self.db.getChip().getBlock()
+ self.insts = self.block.getInsts()
+
+
+reader = OdbReader(os.getenv("MERGED_LEF"), os.getenv("CURRENT_DEF"))
+buffers = [
+ instance for instance in reader.insts if instance.getName() == "inserted_buffer"
+]
+assert len(buffers) == 1
+buffer = buffers[0]
+
+connected_terminals = [
+ iterm for iterm in buffer.getITerms() if iterm.getNet() is not None
+]
+
+names = [iterm.getNet().getName() for iterm in connected_terminals]
+
+assert "inserted_net" in names
+assert "in" in names
diff --git a/openlane/tests/1007/in.def b/openlane/tests/1007/in.def
new file mode 100644
index 0000000..92ba82c
--- /dev/null
+++ b/openlane/tests/1007/in.def
@@ -0,0 +1,79 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN inverter ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 34165 54885 ) ;
+ROW ROW_0 unithd 5520 10880 N DO 50 BY 1 STEP 460 0 ;
+ROW ROW_1 unithd 5520 13600 FS DO 50 BY 1 STEP 460 0 ;
+ROW ROW_2 unithd 5520 16320 N DO 50 BY 1 STEP 460 0 ;
+ROW ROW_3 unithd 5520 19040 FS DO 50 BY 1 STEP 460 0 ;
+ROW ROW_4 unithd 5520 21760 N DO 50 BY 1 STEP 460 0 ;
+ROW ROW_5 unithd 5520 24480 FS DO 50 BY 1 STEP 460 0 ;
+ROW ROW_6 unithd 5520 27200 N DO 50 BY 1 STEP 460 0 ;
+ROW ROW_7 unithd 5520 29920 FS DO 50 BY 1 STEP 460 0 ;
+ROW ROW_8 unithd 5520 32640 N DO 50 BY 1 STEP 460 0 ;
+ROW ROW_9 unithd 5520 35360 FS DO 50 BY 1 STEP 460 0 ;
+ROW ROW_10 unithd 5520 38080 N DO 50 BY 1 STEP 460 0 ;
+ROW ROW_11 unithd 5520 40800 FS DO 50 BY 1 STEP 460 0 ;
+TRACKS X 230 DO 74 STEP 460 LAYER li1 ;
+TRACKS Y 170 DO 161 STEP 340 LAYER li1 ;
+TRACKS X 170 DO 100 STEP 340 LAYER met1 ;
+TRACKS Y 170 DO 161 STEP 340 LAYER met1 ;
+TRACKS X 230 DO 74 STEP 460 LAYER met2 ;
+TRACKS Y 230 DO 119 STEP 460 LAYER met2 ;
+TRACKS X 340 DO 50 STEP 680 LAYER met3 ;
+TRACKS Y 340 DO 81 STEP 680 LAYER met3 ;
+TRACKS X 460 DO 37 STEP 920 LAYER met4 ;
+TRACKS Y 460 DO 60 STEP 920 LAYER met4 ;
+TRACKS X 1700 DO 10 STEP 3400 LAYER met5 ;
+TRACKS Y 1700 DO 16 STEP 3400 LAYER met5 ;
+COMPONENTS 32 ;
+ - PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 10880 ) N ;
+ - PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 10880 ) FN ;
+ - PHY_10 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 24480 ) FS ;
+ - PHY_11 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 24480 ) S ;
+ - PHY_12 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 27200 ) N ;
+ - PHY_13 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 27200 ) FN ;
+ - PHY_14 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 29920 ) FS ;
+ - PHY_15 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 29920 ) S ;
+ - PHY_16 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 32640 ) N ;
+ - PHY_17 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 32640 ) FN ;
+ - PHY_18 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 35360 ) FS ;
+ - PHY_19 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 35360 ) S ;
+ - PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 13600 ) FS ;
+ - PHY_20 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 38080 ) N ;
+ - PHY_21 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 38080 ) FN ;
+ - PHY_22 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 40800 ) FS ;
+ - PHY_23 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 40800 ) S ;
+ - PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 13600 ) S ;
+ - PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 16320 ) N ;
+ - PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 16320 ) FN ;
+ - PHY_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 19040 ) FS ;
+ - PHY_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 19040 ) S ;
+ - PHY_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 21760 ) N ;
+ - PHY_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 27140 21760 ) FN ;
+ - TAP_24 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 10880 ) N ;
+ - TAP_25 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 16320 ) N ;
+ - TAP_26 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 21760 ) N ;
+ - TAP_27 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 27200 ) N ;
+ - TAP_28 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 32640 ) N ;
+ - TAP_29 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 38080 ) N ;
+ - TAP_30 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18400 40800 ) FS ;
+ - _0_ sky130_fd_sc_hd__inv_2 ;
+END COMPONENTS
+PINS 2 ;
+ - in + NET in + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 32430 52885 ) N ;
+ - out + NET out + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 230 2000 ) N ;
+END PINS
+NETS 2 ;
+ - in ( PIN in ) ( _0_ A ) + USE SIGNAL ;
+ - out ( PIN out ) ( _0_ Y ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/tests/1007/interactive.tcl b/openlane/tests/1007/interactive.tcl
new file mode 100644
index 0000000..83a443c
--- /dev/null
+++ b/openlane/tests/1007/interactive.tcl
@@ -0,0 +1,17 @@
+package require openlane;
+
+prep -design tests/1007
+
+set ::env(CURRENT_DEF) $::env(DESIGN_DIR)/in.def
+
+insert_buffer\
+ -at_pin _0_/A\
+ -buffer_cell sky130_fd_sc_hd__dlygate4sd3_1\
+ -net_name inserted_net\
+ -inst_name inserted_buffer
+
+exec cp $::env(CURRENT_DEF) $::env(DESIGN_DIR)/out.def
+
+exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py
+
+puts_info "Done."
\ No newline at end of file
diff --git a/openlane/tests/892/Readme.txt b/openlane/tests/892/Readme.txt
new file mode 100644
index 0000000..3f4e12c
--- /dev/null
+++ b/openlane/tests/892/Readme.txt
@@ -0,0 +1 @@
+Also tests apply_def_template
\ No newline at end of file
diff --git a/openlane/tests/892/config.tcl b/openlane/tests/892/config.tcl
new file mode 100755
index 0000000..97da782
--- /dev/null
+++ b/openlane/tests/892/config.tcl
@@ -0,0 +1,22 @@
+# User config
+set ::env(DESIGN_NAME) def_test
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+# turn off clock
+set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(CLOCK_PORT) ""
+
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/def_test.def
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 300 300"
+set ::env(PL_TARGET_DENSITY) 0.75
+
+set ::env(FP_PDN_HORIZONTAL_HALO) 6
+set ::env(FP_PDN_VERTICAL_HALO) $::env(FP_PDN_HORIZONTAL_HALO)
+
+set ::env(DIODE_INSERTION_STRATEGY) 3
\ No newline at end of file
diff --git a/openlane/tests/892/def_test.def b/openlane/tests/892/def_test.def
new file mode 100644
index 0000000..36445ec
--- /dev/null
+++ b/openlane/tests/892/def_test.def
@@ -0,0 +1,33 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN def_test ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 400000 400000 ) ;
+PINS 4 ;
+ - in + NET in + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 1000 350000 ) N ;
+ - out + NET out + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 400 2000 ) N ;
+ - tied_to_zero + NET zero_ + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 4000 2000 ) N ;
+ - manufacturing_grid_missaligned_pin + NET manufacturing_grid_missaligned_pin + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 10000 2000 ) N ;
+ - VPWR + NET VPWR + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 20000 2000 ) N ;
+ - VGND + NET VGND + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 25000 2000 ) N ;
+END PINS
+END DESIGN
diff --git a/openlane/tests/892/hooks/post_run.py b/openlane/tests/892/hooks/post_run.py
new file mode 100644
index 0000000..9486dad
--- /dev/null
+++ b/openlane/tests/892/hooks/post_run.py
@@ -0,0 +1,92 @@
+# export TECH_LEF=/home/armleo/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef
+# export MERGED_LEF=/openlane/designs/def_test/runs/RUN_2022.01.23_17.23.46/tmp/merged.lef
+# export HOOK_OUTPUT_PATH=/openlane/designs/def_test/runs/RUN_2022.01.23_17.23.46/results/final
+# export DESIGN_DIR=/openlane/designs/def_test
+# openroad -python designs/def_test/hooks/post_run.py
+
+import odb
+
+import os
+import sys
+
+
+def extract_pins(db, def_file):
+ odb.read_lef(db, os.environ["TECH_LEF"])
+ odb.read_lef(db, os.environ["MERGED_LEF"])
+ odb.read_def(db, def_file)
+ chip = db.getChip()
+ block = chip.getBlock()
+ nets = block.getNets()
+ # tech = db.getTech() # Not needed
+
+ result_data = {}
+ for net in nets:
+ net_name = net.getName()
+ # BTerms = PINS, if it has a pin we need to keep the net
+ bterms = net.getBTerms()
+ if len(bterms) > 0:
+ for port in bterms:
+ if (port.getSigType() == "POWER") or (port.getSigType() == "GROUND"):
+ # Ignore power pins
+ continue
+ name = port.getName()
+
+ bbox = port.getBBox()
+ result_data[name] = bbox
+ print(
+ "Net:",
+ net_name,
+ "Port:",
+ name,
+ "ll: ",
+ " ".join(str(e) for e in bbox.ll()),
+ "ur: ",
+ " ".join(str(e) for e in bbox.ur()),
+ )
+ return result_data
+
+
+result_db = odb.dbDatabase.create()
+ref_db = odb.dbDatabase.create()
+
+print("TECH_LEF ", os.environ["TECH_LEF"])
+print("MERGED_LEF ", os.environ["MERGED_LEF"])
+print("HOOK_OUTPUT_PATH ", os.environ["HOOK_OUTPUT_PATH"])
+print("DESIGN_DIR ", os.environ["DESIGN_DIR"])
+
+
+result_data = extract_pins(
+ result_db, os.environ["HOOK_OUTPUT_PATH"] + "/def/def_test.def"
+)
+
+# result_data = extract_pins(result_db, os.environ["DESIGN_DIR"] + "/def_test.def")
+ref_data = extract_pins(ref_db, os.environ["DESIGN_DIR"] + "/def_test.def")
+
+# print(result_data)
+# print(ref_data)
+
+for k, v in ref_data.items():
+ assert (
+ v.ll() == result_data[k].ll()
+ ), f"For pin {k} lower left rectangle point {result_data[k].ll()} does not match {v.ll()}"
+ assert (
+ v.ur() == result_data[k].ur()
+ ), f"For pin {k} upper right rectangle point {result_data[k].ur()} does not match {v.ur()}"
+
+assert (
+ result_db.getTech().getManufacturingGrid()
+ == ref_db.getTech().getManufacturingGrid()
+)
+assert (
+ result_db.getTech().getDbUnitsPerMicron() == ref_db.getTech().getDbUnitsPerMicron()
+)
+assert (
+ result_db.getChip().getBlock().getDieArea().ur()
+ == ref_db.getChip().getBlock().getDieArea().ur()
+)
+assert (
+ result_db.getChip().getBlock().getDieArea().ll()
+ == ref_db.getChip().getBlock().getDieArea().ll()
+)
+
+sys.exit(0)
diff --git a/openlane/tests/892/src/def_test.v b/openlane/tests/892/src/def_test.v
new file mode 100644
index 0000000..723b707
--- /dev/null
+++ b/openlane/tests/892/src/def_test.v
@@ -0,0 +1,27 @@
+// Copyright 2022 Arman Avetisyan
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`default_nettype none
+module def_test (
+ input wire in,
+ output out,
+ output tied_to_zero,
+ output manufacturing_grid_missaligned_pin
+ );
+ // We tie this to one, so if def's pin is tied to zero, it will LVS error
+assign tied_to_zero = 1;
+
+ assign out = !in;
+
+endmodule
diff --git a/openlane/tests/912/config.tcl b/openlane/tests/912/config.tcl
new file mode 120000
index 0000000..bdeb9e0
--- /dev/null
+++ b/openlane/tests/912/config.tcl
@@ -0,0 +1 @@
+../892/config.tcl
\ No newline at end of file
diff --git a/openlane/tests/912/def_test.def b/openlane/tests/912/def_test.def
new file mode 100644
index 0000000..10cdf07
--- /dev/null
+++ b/openlane/tests/912/def_test.def
@@ -0,0 +1,33 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN def_test ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 400000 400000 ) ;
+PINS 4 ;
+ - in + NET in + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 1000 350000 ) N ;
+ - out + NET out + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 400 2000 ) N ;
+ - tied_to_zero + NET zero_ + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 4000 2000 ) N ;
+ - manufacturing_grid_missaligned_pin + NET manufacturing_grid_missaligned_pin + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 10001 2000 ) N ;
+ - VPWR + NET VPWR + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 20000 2000 ) N ;
+ - VGND + NET VGND + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 25000 2000 ) N ;
+END PINS
+END DESIGN
diff --git a/openlane/tests/912/issue_regression.py b/openlane/tests/912/issue_regression.py
new file mode 100644
index 0000000..0d21ac7
--- /dev/null
+++ b/openlane/tests/912/issue_regression.py
@@ -0,0 +1,32 @@
+# Copyright 2022 Arman Avetisyan
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import sys
+
+
+with open(sys.argv[1] + "/openlane.log") as f:
+ content = f.read()
+ if (
+ content.find(
+ "Pin coordinate 9861 for pin manufacturing_grid_missaligned_pin does not match the manufacturing grid"
+ )
+ is not -1
+ ) and (
+ content.find(
+ "Pin coordinate 10141 for pin manufacturing_grid_missaligned_pin does not match the manufacturing grid"
+ )
+ is not -1
+ ):
+ sys.exit(0)
+ else:
+ sys.exit("Didn't match the log")
diff --git a/openlane/tests/912/src b/openlane/tests/912/src
new file mode 120000
index 0000000..5bb0825
--- /dev/null
+++ b/openlane/tests/912/src
@@ -0,0 +1 @@
+../892/src
\ No newline at end of file
diff --git a/openlane/tests/Readme.md b/openlane/tests/Readme.md
new file mode 100644
index 0000000..ee317d4
--- /dev/null
+++ b/openlane/tests/Readme.md
@@ -0,0 +1,5 @@
+# Regression Tests
+These are test suites for very specific issues, named by issue.
+
+# Acknowledgement
+The issue regression test suite was created by [@armleo](https://github.com/armleo).
\ No newline at end of file
diff --git a/verilog/rtl/my_design/count_monitor.v b/verilog/rtl/my_design/count_monitor.v
new file mode 100644
index 0000000..c7edee9
--- /dev/null
+++ b/verilog/rtl/my_design/count_monitor.v
@@ -0,0 +1,99 @@
+
+module count_monitor ( input wire clk,
+ output reg comp_en,
+ output reg sample,
+ output reg d1,
+ output wire d1b,
+ output reg d2,
+ output wire d2b,
+ output reg d3,
+ output wire d3b,
+ output reg d4,
+ output wire d4b,
+ output reg d5,
+ output wire d5b,
+ output reg d6,
+ output wire d6b,
+ output reg rs);
+
+ reg [4:0] sar_counter;
+
+ // 初期値代入
+ initial begin
+ sar_counter = 8;
+ comp_en <= 1;
+ sample <= 0;
+ d1 <= 0;
+ d2 <= 0;
+ d3 <= 0;
+ d4 <= 0;
+ d5 <= 0;
+ d6 <= 0;
+ rs <= 0;
+ end
+
+ // 比較回数モニタ，制御
+ always @ (posedge clk)
+ if (sar_counter == 8) begin
+ sample <= 0;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 7) begin
+ comp_en <= 0;
+ d6 <= 1;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 6) begin
+ d5 <= 1;
+ d6 <= 0;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 5) begin
+ d4 <= 1;
+ d5 <= 0;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 4) begin
+ d3 <= 1;
+ d4 <= 0;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 3) begin
+ d2 <= 1;
+ d3 <= 0;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 2) begin
+ d1 <= 1;
+ d2 <= 0;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 1) begin
+ d1 <= 0;
+ comp_en <= 1;
+ sar_counter = sar_counter - 1;
+ end
+ else if (sar_counter == 0) begin
+ sample <= 1;
+ sar_counter = 8;
+ end
+
+ always @ (negedge clk)
+ if (sar_counter == 0) begin
+ rs <= 1;
+ sample <= 1;
+ end
+ else if (sar_counter == 8) begin
+ rs <= 0;
+ end
+
+ assign d1b = ~d1;
+ assign d2b = ~d2;
+ assign d3b = ~d3;
+ assign d4b = ~d4;
+ assign d5b = ~d5;
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/my_design/dff.v b/verilog/rtl/my_design/dff.v
new file mode 100644
index 0000000..159f16e
--- /dev/null
+++ b/verilog/rtl/my_design/dff.v
@@ -0,0 +1,21 @@
+// dff
+
+module dff ( input wire d,
+ input wire rst,
+ input wire clk,
+ output reg q,
+ output wire qn);
+
+ initial begin
+ q <= 0;
+ end
+
+ always @ (posedge clk or posedge rst)
+ if (rst)
+ q <= 0;
+ else
+ q <= d;
+
+ assign qn = ~q;
+
+endmodule
diff --git a/verilog/rtl/my_design/hold.v b/verilog/rtl/my_design/hold.v
new file mode 100644
index 0000000..f9d7683
--- /dev/null
+++ b/verilog/rtl/my_design/hold.v
@@ -0,0 +1,50 @@
+
+module hold ( input wire comp_in,
+ input wire sample,
+ input wire d1b,
+ input wire d2b,
+ input wire d3b,
+ input wire d4b,
+ input wire d5b,
+ input wire d6b,
+ output wire r5,
+ output wire r4,
+ output wire r3,
+ output wire r2,
+ output wire r1,
+ output wire r0);
+
+ dff dff5 ( .d(comp_in),
+ .rst (sample),
+ .clk (d6b),
+ .q (r5),
+ .qn ()),
+ dff4 ( .d(comp_in),
+ .rst (sample),
+ .clk (d5b),
+ .q (r4),
+ .qn ()),
+ dff3 ( .d(comp_in),
+ .rst (sample),
+ .clk (d4b),
+ .q (r3),
+ .qn ()),
+ dff2 ( .d(comp_in),
+ .rst (sample),
+ .clk (d3b),
+ .q (r2),
+ .qn ()),
+ dff1 ( .d(comp_in),
+ .rst (sample),
+ .clk (d2b),
+ .q (r1),
+ .qn ()),
+ dff0 ( .d(comp_in),
+ .rst (sample),
+ .clk (d1b),
+ .q (r0),
+ .qn ());
+
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/my_design/main.v b/verilog/rtl/my_design/main.v
new file mode 100644
index 0000000..d2047ed
--- /dev/null
+++ b/verilog/rtl/my_design/main.v
@@ -0,0 +1,104 @@
+module sar_logic (input clk,
+ input comp_in,
+ output comp_en,
+ output sample,
+ output q5,
+ output q4,
+ output q3,
+ output q2,
+ output q1,
+ output q0,
+ output sw5,
+ output sw5b,
+ output sw4,
+ output sw4b,
+ output sw3,
+ output sw3b,
+ output sw2,
+ output sw2b,
+ output sw1,
+ output sw1b,
+ output sw0,
+ output sw0b,
+ output rs,
+ output r5,
+ output r4,
+ output r3,
+ output r2,
+ output r1,
+ output r0,
+ output d1,
+ output d1b,
+ output d2,
+ output d2b,
+ output d3,
+ output d3b,
+ output d4,
+ output d4b,
+ output d5,
+ output d5b,
+ output d6);
+
+
+ count_monitor ccc ( .clk(clk),
+ .comp_en (comp_en),
+ .sample (sample),
+ .d1 (d1),
+ .d1b (d1b),
+ .d2 (d2),
+ .d2b (d2b),
+ .d3 (d3),
+ .d3b (d3b),
+ .d4 (d4),
+ .d4b (d4b),
+ .d5 (d5),
+ .d5b (d5b),
+ .d6 (d6),
+ .d6b (d6b),
+ .rs (rs));
+
+ hold hhh ( .comp_in(comp_in),
+ .sample(sample),
+ .d1b(d1b),
+ .d2b(d2b),
+ .d3b(d3b),
+ .d4b(d4b),
+ .d5b(d5b),
+ .d6b(d6b),
+ .r5(r5),
+ .r4(r4),
+ .r3(r3),
+ .r2(r2),
+ .r1(r1),
+ .r0(r0));
+
+ qout qqq ( .sample(sample),
+ .rs(rs),
+ .r5(r5),
+ .r4(r4),
+ .r3(r3),
+ .r2(r2),
+ .r1(r1),
+ .r0(r0),
+ .q5(q5),
+ .q4(q4),
+ .q3(q3),
+ .q2(q2),
+ .q1(q1),
+ .q0(q0));
+
+
+ assign sw5 = sample | r5 | d6;
+ assign sw5b = ~sw5;
+ assign sw4 = sample | r4 | d5;
+ assign sw4b = ~sw4;
+ assign sw3 = sample | r3 | d4;
+ assign sw3b = ~sw3;
+ assign sw2 = sample | r2 | d3;
+ assign sw2b = ~sw2;
+ assign sw1 = sample | r1 | d2;
+ assign sw1b = ~sw1;
+ assign sw0 = sample | r0 | d1;
+ assign sw0b = ~sw0;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/my_design/qout.v b/verilog/rtl/my_design/qout.v
new file mode 100644
index 0000000..0a78084
--- /dev/null
+++ b/verilog/rtl/my_design/qout.v
@@ -0,0 +1,50 @@
+
+module qout ( input wire sample,
+ input wire rs,
+ input wire r5,
+ input wire r4,
+ input wire r3,
+ input wire r2,
+ input wire r1,
+ input wire r0,
+ output wire q5,
+ output wire q4,
+ output wire q3,
+ output wire q2,
+ output wire q1,
+ output wire q0);
+
+ dff dff6 ( .d(r5),
+ .rst (sample),
+ .clk (rs),
+ .q (q5),
+ .qn ()),
+ dff5 ( .d(r4),
+ .rst (sample),
+ .clk (rs),
+ .q (q4),
+ .qn ()),
+ dff4 ( .d(r3),
+ .rst (sample),
+ .clk (rs),
+ .q (q3),
+ .qn ()),
+ dff3 ( .d(r2),
+ .rst (sample),
+ .clk (rs),
+ .q (q2),
+ .qn ()),
+ dff2 ( .d(r1),
+ .rst (sample),
+ .clk (rs),
+ .q (q1),
+ .qn ()),
+ dff1 ( .d(r0n),
+ .rst (sample),
+ .clk (rs),
+ .q (q0),
+ .qn ());
+
+
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/my_design/sample/sample.o b/verilog/rtl/my_design/sample/sample.o
new file mode 100755
index 0000000..03df3fb
--- /dev/null
+++ b/verilog/rtl/my_design/sample/sample.o
@@ -0,0 +1,130 @@
+#! /usr/bin/vvp
+:ivl_version "10.3 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x557b47f79c10 .scope module, "tb_Prpg10" "tb_Prpg10" 2 3;
+ .timescale -9 -12;
+P_0x557b47f79d90 .param/l "CYC" 0 2 8, +C4<00000000000000000000000001100100>;
+v0x557b47f91fb0_0 .var "Clk", 0 0;
+v0x557b47f92070_0 .net "PrpgOut", 9 0, L_0x557b47f41550; 1 drivers
+v0x557b47f92140_0 .var "PrpgSeed", 9 0;
+v0x557b47f92240_0 .var "PrpgStart", 0 0;
+v0x557b47f92310_0 .var "PrpgUpld", 0 0;
+v0x557b47f923b0_0 .var "ResetB", 0 0;
+S_0x557b47f41050 .scope module, "dut" "Prpg10" 2 11, 3 3 0, S_0x557b47f79c10;
+ .timescale -9 -12;
+ .port_info 0 /INPUT 1 "Clk"
+ .port_info 1 /INPUT 1 "ResetB"
+ .port_info 2 /INPUT 1 "PrpgUpld"
+ .port_info 3 /INPUT 1 "PrpgStart"
+ .port_info 4 /INPUT 10 "PrpgSeed"
+ .port_info 5 /OUTPUT 10 "PrpgOut"
+P_0x557b47f41220 .param/l "Prpg10_UD" 0 3 5, +C4<00000000000000000000000000000001>;
+L_0x557b47f7aa40 .functor XOR 1, L_0x557b47f92580, L_0x557b47f926a0, C4<0>, C4<0>;
+L_0x557b47f41550 .functor AND 10, v0x557b47f912d0_0, L_0x557b47f92bf0, C4<1111111111>, C4<1111111111>;
+v0x557b47f41390_0 .net "Clk", 0 0, v0x557b47f91fb0_0; 1 drivers
+v0x557b47f911f0_0 .net "PrpgOut", 9 0, L_0x557b47f41550; alias, 1 drivers
+v0x557b47f912d0_0 .var "PrpgReg", 9 0;
+v0x557b47f913c0_0 .net "PrpgRegIn", 9 0, L_0x557b47f92a70; 1 drivers
+v0x557b47f914a0_0 .net "PrpgSeed", 9 0, v0x557b47f92140_0; 1 drivers
+v0x557b47f915d0_0 .net "PrpgStart", 0 0, v0x557b47f92240_0; 1 drivers
+v0x557b47f91690_0 .var "PrpgStartReg", 0 0;
+v0x557b47f91750_0 .net "PrpgUpld", 0 0, v0x557b47f92310_0; 1 drivers
+v0x557b47f91810_0 .net "ResetB", 0 0, v0x557b47f923b0_0; 1 drivers
+v0x557b47f918d0_0 .net *"_s1", 8 0, L_0x557b47f92480; 1 drivers
+v0x557b47f919b0_0 .net *"_s10", 9 0, L_0x557b47f92980; 1 drivers
+v0x557b47f91a90_0 .net *"_s14", 9 0, L_0x557b47f92bf0; 1 drivers
+v0x557b47f91b70_0 .net *"_s3", 0 0, L_0x557b47f92580; 1 drivers
+v0x557b47f91c50_0 .net *"_s5", 0 0, L_0x557b47f926a0; 1 drivers
+v0x557b47f91d30_0 .net *"_s6", 0 0, L_0x557b47f7aa40; 1 drivers
+v0x557b47f91e10_0 .net *"_s8", 9 0, L_0x557b47f92810; 1 drivers
+E_0x557b47f419c0/0 .event negedge, v0x557b47f91810_0;
+E_0x557b47f419c0/1 .event posedge, v0x557b47f41390_0;
+E_0x557b47f419c0 .event/or E_0x557b47f419c0/0, E_0x557b47f419c0/1;
+L_0x557b47f92480 .part v0x557b47f912d0_0, 0, 9;
+L_0x557b47f92580 .part v0x557b47f912d0_0, 9, 1;
+L_0x557b47f926a0 .part v0x557b47f912d0_0, 2, 1;
+L_0x557b47f92810 .concat [ 1 9 0 0], L_0x557b47f7aa40, L_0x557b47f92480;
+L_0x557b47f92980 .functor MUXZ 10, v0x557b47f912d0_0, v0x557b47f92140_0, v0x557b47f92310_0, C4<>;
+L_0x557b47f92a70 .functor MUXZ 10, L_0x557b47f92980, L_0x557b47f92810, v0x557b47f91690_0, C4<>;
+LS_0x557b47f92bf0_0_0 .concat [ 1 1 1 1], v0x557b47f91690_0, v0x557b47f91690_0, v0x557b47f91690_0, v0x557b47f91690_0;
+LS_0x557b47f92bf0_0_4 .concat [ 1 1 1 1], v0x557b47f91690_0, v0x557b47f91690_0, v0x557b47f91690_0, v0x557b47f91690_0;
+LS_0x557b47f92bf0_0_8 .concat [ 1 1 0 0], v0x557b47f91690_0, v0x557b47f91690_0;
+L_0x557b47f92bf0 .concat [ 4 4 2 0], LS_0x557b47f92bf0_0_0, LS_0x557b47f92bf0_0_4, LS_0x557b47f92bf0_0_8;
+ .scope S_0x557b47f41050;
+T_0 ;
+ %wait E_0x557b47f419c0;
+ %load/vec4 v0x557b47f91810_0;
+ %cmpi/e 0, 0, 1;
+ %jmp/0xz T_0.0, 4;
+ %pushi/vec4 0, 0, 10;
+ %assign/vec4 v0x557b47f912d0_0, 1000;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x557b47f91690_0, 1000;
+ %jmp T_0.1;
+T_0.0 ;
+ %load/vec4 v0x557b47f913c0_0;
+ %assign/vec4 v0x557b47f912d0_0, 1000;
+ %load/vec4 v0x557b47f915d0_0;
+ %assign/vec4 v0x557b47f91690_0, 1000;
+T_0.1 ;
+ %jmp T_0;
+ .thread T_0;
+ .scope S_0x557b47f79c10;
+T_1 ;
+ %delay 50000, 0;
+ %load/vec4 v0x557b47f91fb0_0;
+ %inv;
+ %store/vec4 v0x557b47f91fb0_0, 0, 1;
+ %jmp T_1;
+ .thread T_1;
+ .scope S_0x557b47f79c10;
+T_2 ;
+ %vpi_call 2 21 "$dumpfile", "tb_Prpg10.vcd" {0 0 0};
+ %vpi_call 2 22 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x557b47f79c10 {0 0 0};
+ %delay 0, 0;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x557b47f91fb0_0, 0, 1;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x557b47f923b0_0, 0, 1;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x557b47f92310_0, 0, 1;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x557b47f92240_0, 0, 1;
+ %pushi/vec4 0, 0, 10;
+ %store/vec4 v0x557b47f92140_0, 0, 10;
+ %delay 1000000, 0;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x557b47f923b0_0, 0, 1;
+ %delay 1000000, 0;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x557b47f923b0_0, 0, 1;
+ %delay 1000000, 0;
+ %pushi/vec4 1, 0, 10;
+ %store/vec4 v0x557b47f92140_0, 0, 10;
+ %delay 1000000, 0;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x557b47f92310_0, 0, 1;
+ %delay 100000, 0;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x557b47f92310_0, 0, 1;
+ %delay 1000000, 0;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x557b47f92240_0, 0, 1;
+ %delay 102400000, 0;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x557b47f92240_0, 0, 1;
+ %delay 1000000, 0;
+ %vpi_call 2 39 "$finish" {0 0 0};
+ %end;
+ .thread T_2;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+ "N/A";
+ "<interactive>";
+ "tb_sample.v";
+ "sample.v";
diff --git a/verilog/rtl/my_design/sample/sample.v b/verilog/rtl/my_design/sample/sample.v
new file mode 100644
index 0000000..1c8aebd
--- /dev/null
+++ b/verilog/rtl/my_design/sample/sample.v
@@ -0,0 +1,38 @@
+`timescale 1ns/1ps
+
+module Prpg10
+ #( // parameters
+ parameter Prpg10_UD = 1 // Unit Delay
+ )
+ ( // ports
+ input wire Clk, // Clock
+ input wire ResetB, // Reset
+ input wire PrpgUpld, // Seed upload
+ input wire PrpgStart, // PRPG start
+ input wire [9:0] PrpgSeed, // Seed input
+ output wire [9:0] PrpgOut // PRPG data output
+ );
+
+ reg [9:0] PrpgReg;
+ wire [9:0] PrpgRegIn;
+ reg PrpgStartReg;
+
+ always @(posedge Clk, negedge ResetB) begin
+ if (ResetB==1'b0) begin // Asynronous reset
+ PrpgReg <= #Prpg10_UD 10'b00_0000_0000;
+ PrpgStartReg <= #Prpg10_UD 1'b0;
+ end
+ else begin // Function
+ PrpgReg <= #Prpg10_UD PrpgRegIn;
+ PrpgStartReg <= #Prpg10_UD PrpgStart;
+ end
+ end
+
+ assign PrpgRegIn =
+ (PrpgStartReg)? {PrpgReg[8:0],(PrpgReg[9]^PrpgReg[2])} : // x^10+ x^3 + 1
+ (PrpgUpld)? PrpgSeed :
+ PrpgReg ;
+
+ assign PrpgOut = PrpgReg & {10{PrpgStartReg}};
+
+endmodule
diff --git a/verilog/rtl/my_design/sample/tb_Prpg10.vcd b/verilog/rtl/my_design/sample/tb_Prpg10.vcd
new file mode 100644
index 0000000..ba2e82b
--- /dev/null
+++ b/verilog/rtl/my_design/sample/tb_Prpg10.vcd
@@ -0,0 +1,9526 @@
+$date
+ Tue May 17 21:06:17 2022
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1ps
+$end
+$scope module tb_Prpg10 $end
+$var wire 10 ! PrpgOut [9:0] $end
+$var reg 1 " Clk $end
+$var reg 10 # PrpgSeed [9:0] $end
+$var reg 1 $ PrpgStart $end
+$var reg 1 % PrpgUpld $end
+$var reg 1 & ResetB $end
+$scope module dut $end
+$var wire 1 " Clk $end
+$var wire 10 ' PrpgOut [9:0] $end
+$var wire 10 ( PrpgSeed [9:0] $end
+$var wire 1 $ PrpgStart $end
+$var wire 1 % PrpgUpld $end
+$var wire 1 & ResetB $end
+$var wire 10 ) PrpgRegIn [9:0] $end
+$var reg 10 * PrpgReg [9:0] $end
+$var reg 1 + PrpgStartReg $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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+#106750000
+1"
+#106751000
+b10000 )
+b1000 !
+b1000 '
+b1000 *
+#106800000
+0"
+#106850000
+1"
+#106851000
+b100000 )
+b10000 !
+b10000 '
+b10000 *
+#106900000
+0"
+#106950000
+1"
+#106951000
+b1000000 )
+b100000 !
+b100000 '
+b100000 *
+#107000000
+0"
+#107050000
+1"
+#107051000
+b10000000 )
+b1000000 !
+b1000000 '
+b1000000 *
+#107100000
+0"
+#107150000
+1"
+#107151000
+b100000000 )
+b10000000 !
+b10000000 '
+b10000000 *
+#107200000
+0"
+#107250000
+1"
+#107251000
+b1000000000 )
+b100000000 !
+b100000000 '
+b100000000 *
+#107300000
+0"
+#107350000
+1"
+#107351000
+b1 )
+b1000000000 !
+b1000000000 '
+b1000000000 *
+#107400000
+0"
+#107450000
+1"
+#107451000
+b10 )
+b1 !
+b1 '
+b1 *
+#107500000
+0"
+0$
+#107550000
+1"
+#107551000
+b0 !
+b0 '
+0+
+b10 *
+#107600000
+0"
+#107650000
+1"
+#107700000
+0"
+#107750000
+1"
+#107800000
+0"
+#107850000
+1"
+#107900000
+0"
+#107950000
+1"
+#108000000
+0"
+#108050000
+1"
+#108100000
+0"
+#108150000
+1"
+#108200000
+0"
+#108250000
+1"
+#108300000
+0"
+#108350000
+1"
+#108400000
+0"
+#108450000
+1"
+#108500000
+0"
diff --git a/verilog/rtl/my_design/sample/tb_sample.v b/verilog/rtl/my_design/sample/tb_sample.v
new file mode 100644
index 0000000..18302d0
--- /dev/null
+++ b/verilog/rtl/my_design/sample/tb_sample.v
@@ -0,0 +1,42 @@
+`timescale 1ns/1ps
+
+module tb_Prpg10;
+ reg Clk, ResetB, PrpgUpld, PrpgStart;
+ reg [9:0] PrpgSeed;
+ wire [9:0] PrpgOut;
+
+ parameter CYC = 100;
+ always #(CYC/2) Clk = ~Clk;
+
+ Prpg10 dut ( // Prpg10のInstance
+ .Clk (Clk),
+ .ResetB (ResetB),
+ .PrpgUpld (PrpgUpld),
+ .PrpgStart (PrpgStart),
+ .PrpgSeed (PrpgSeed),
+ .PrpgOut (PrpgOut)
+ );
+
+ initial begin
+ $dumpfile("tb_Prpg10.vcd"); // vcd file name
+ $dumpvars(0,tb_Prpg10); // dump targetは「全部」
+
+ // Initilai value
+ #(CYC* 0) Clk=0; ResetB=1; PrpgUpld=0;
+ PrpgStart=0; PrpgSeed=0; // step[2]の印加値は最初から入れている
+ // Reset
+ #(CYC*10) ResetB=0; // step[1]
+ #(CYC*10) ResetB=1; // step[3](step[2]は実施済み)
+ // Set seed
+ #(CYC*10) PrpgSeed=10'b00_0000_0001; // step[4]
+ #(CYC*10) PrpgUpld=1; // step[5]1にして
+ #(CYC* 1) PrpgUpld=0; // step[5]0に戻す
+ // Start PRPG
+ #(CYC*10) PrpgStart=1; // step[6]
+ // Stop PRPG after 1024 cyc
+ #(CYC*1024) PrpgStart=0; // (return to start 00_0000_0001) step[7]
+ // Stop simulation
+ #(CYC*10) $finish;
+ end
+
+endmodule
diff --git a/verilog/rtl/my_design/tb_count_monitor.o b/verilog/rtl/my_design/tb_count_monitor.o
new file mode 100755
index 0000000..532c872
--- /dev/null
+++ b/verilog/rtl/my_design/tb_count_monitor.o
@@ -0,0 +1,263 @@
+#! /usr/bin/vvp
+:ivl_version "10.3 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x55a79e658120 .scope module, "tb_count_monitor" "tb_count_monitor" 2 3;
+ .timescale -9 -9;
+v0x55a79e6a3350_0 .var "clk", 0 0;
+v0x55a79e6a3410_0 .net "comp_en", 0 0, v0x55a79e6a2500_0; 1 drivers
+v0x55a79e6a34b0_0 .net "d1", 0 0, v0x55a79e6a25c0_0; 1 drivers
+v0x55a79e6a3550_0 .net "d1b", 0 0, L_0x55a79e6a3f80; 1 drivers
+v0x55a79e6a35f0_0 .net "d2", 0 0, v0x55a79e6a2720_0; 1 drivers
+v0x55a79e6a3690_0 .net "d2b", 0 0, L_0x55a79e6a4040; 1 drivers
+v0x55a79e6a3760_0 .net "d3", 0 0, v0x55a79e6a28f0_0; 1 drivers
+v0x55a79e6a3830_0 .net "d3b", 0 0, L_0x55a79e6a4150; 1 drivers
+v0x55a79e6a3900_0 .net "d4", 0 0, v0x55a79e6a2a70_0; 1 drivers
+v0x55a79e6a39d0_0 .net "d4b", 0 0, L_0x55a79e6a4260; 1 drivers
+v0x55a79e6a3aa0_0 .net "d5", 0 0, v0x55a79e6a2bf0_0; 1 drivers
+v0x55a79e6a3b70_0 .net "d5b", 0 0, L_0x55a79e6a4370; 1 drivers
+v0x55a79e6a3c40_0 .net "d6", 0 0, v0x55a79e6a2d70_0; 1 drivers
+o0x7f0b2a266288 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55a79e6a3d10_0 .net "d6b", 0 0, o0x7f0b2a266288; 0 drivers
+v0x55a79e6a3de0_0 .net "rs", 0 0, v0x55a79e6a2ef0_0; 1 drivers
+v0x55a79e6a3eb0_0 .net "sample", 0 0, v0x55a79e6a2fb0_0; 1 drivers
+S_0x55a79e6582a0 .scope module, "ccc" "count_monitor" 2 8, 3 2 0, S_0x55a79e658120;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "clk"
+ .port_info 1 /OUTPUT 1 "comp_en"
+ .port_info 2 /OUTPUT 1 "sample"
+ .port_info 3 /OUTPUT 1 "d1"
+ .port_info 4 /OUTPUT 1 "d1b"
+ .port_info 5 /OUTPUT 1 "d2"
+ .port_info 6 /OUTPUT 1 "d2b"
+ .port_info 7 /OUTPUT 1 "d3"
+ .port_info 8 /OUTPUT 1 "d3b"
+ .port_info 9 /OUTPUT 1 "d4"
+ .port_info 10 /OUTPUT 1 "d4b"
+ .port_info 11 /OUTPUT 1 "d5"
+ .port_info 12 /OUTPUT 1 "d5b"
+ .port_info 13 /OUTPUT 1 "d6"
+ .port_info 14 /OUTPUT 1 "d6b"
+ .port_info 15 /OUTPUT 1 "rs"
+L_0x55a79e6a3f80 .functor NOT 1, v0x55a79e6a25c0_0, C4<0>, C4<0>, C4<0>;
+L_0x55a79e6a4040 .functor NOT 1, v0x55a79e6a2720_0, C4<0>, C4<0>, C4<0>;
+L_0x55a79e6a4150 .functor NOT 1, v0x55a79e6a28f0_0, C4<0>, C4<0>, C4<0>;
+L_0x55a79e6a4260 .functor NOT 1, v0x55a79e6a2a70_0, C4<0>, C4<0>, C4<0>;
+L_0x55a79e6a4370 .functor NOT 1, v0x55a79e6a2bf0_0, C4<0>, C4<0>, C4<0>;
+v0x55a79e67ff00_0 .net "clk", 0 0, v0x55a79e6a3350_0; 1 drivers
+v0x55a79e6a2500_0 .var "comp_en", 0 0;
+v0x55a79e6a25c0_0 .var "d1", 0 0;
+v0x55a79e6a2660_0 .net "d1b", 0 0, L_0x55a79e6a3f80; alias, 1 drivers
+v0x55a79e6a2720_0 .var "d2", 0 0;
+v0x55a79e6a2830_0 .net "d2b", 0 0, L_0x55a79e6a4040; alias, 1 drivers
+v0x55a79e6a28f0_0 .var "d3", 0 0;
+v0x55a79e6a29b0_0 .net "d3b", 0 0, L_0x55a79e6a4150; alias, 1 drivers
+v0x55a79e6a2a70_0 .var "d4", 0 0;
+v0x55a79e6a2b30_0 .net "d4b", 0 0, L_0x55a79e6a4260; alias, 1 drivers
+v0x55a79e6a2bf0_0 .var "d5", 0 0;
+v0x55a79e6a2cb0_0 .net "d5b", 0 0, L_0x55a79e6a4370; alias, 1 drivers
+v0x55a79e6a2d70_0 .var "d6", 0 0;
+v0x55a79e6a2e30_0 .net "d6b", 0 0, o0x7f0b2a266288; alias, 0 drivers
+v0x55a79e6a2ef0_0 .var "rs", 0 0;
+v0x55a79e6a2fb0_0 .var "sample", 0 0;
+v0x55a79e6a3070_0 .var "sar_counter", 4 0;
+E_0x55a79e682060 .event negedge, v0x55a79e67ff00_0;
+E_0x55a79e682260 .event posedge, v0x55a79e67ff00_0;
+ .scope S_0x55a79e6582a0;
+T_0 ;
+ %pushi/vec4 8, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2500_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2fb0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a25c0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2720_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a28f0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2a70_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2bf0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2d70_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2ef0_0, 0;
+ %end;
+ .thread T_0;
+ .scope S_0x55a79e6582a0;
+T_1 ;
+ %wait E_0x55a79e682260;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 8, 0, 32;
+ %jmp/0xz T_1.0, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2fb0_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.1;
+T_1.0 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 7, 0, 32;
+ %jmp/0xz T_1.2, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2500_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2d70_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.3;
+T_1.2 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 6, 0, 32;
+ %jmp/0xz T_1.4, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2bf0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2d70_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.5;
+T_1.4 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 5, 0, 32;
+ %jmp/0xz T_1.6, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2a70_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2bf0_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.7;
+T_1.6 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 4, 0, 32;
+ %jmp/0xz T_1.8, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a28f0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2a70_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.9;
+T_1.8 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 3, 0, 32;
+ %jmp/0xz T_1.10, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2720_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a28f0_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.11;
+T_1.10 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 2, 0, 32;
+ %jmp/0xz T_1.12, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a25c0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2720_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.13;
+T_1.12 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 1, 0, 32;
+ %jmp/0xz T_1.14, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a25c0_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2500_0, 0;
+ %load/vec4 v0x55a79e6a3070_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+ %jmp T_1.15;
+T_1.14 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 0, 0, 32;
+ %jmp/0xz T_1.16, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2fb0_0, 0;
+ %pushi/vec4 8, 0, 5;
+ %store/vec4 v0x55a79e6a3070_0, 0, 5;
+T_1.16 ;
+T_1.15 ;
+T_1.13 ;
+T_1.11 ;
+T_1.9 ;
+T_1.7 ;
+T_1.5 ;
+T_1.3 ;
+T_1.1 ;
+ %jmp T_1;
+ .thread T_1;
+ .scope S_0x55a79e6582a0;
+T_2 ;
+ %wait E_0x55a79e682060;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 0, 0, 32;
+ %jmp/0xz T_2.0, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2ef0_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55a79e6a2fb0_0, 0;
+ %jmp T_2.1;
+T_2.0 ;
+ %load/vec4 v0x55a79e6a3070_0;
+ %pad/u 32;
+ %cmpi/e 8, 0, 32;
+ %jmp/0xz T_2.2, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a2ef0_0, 0;
+T_2.2 ;
+T_2.1 ;
+ %jmp T_2;
+ .thread T_2;
+ .scope S_0x55a79e658120;
+T_3 ;
+ %delay 10, 0;
+ %load/vec4 v0x55a79e6a3350_0;
+ %inv;
+ %store/vec4 v0x55a79e6a3350_0, 0, 1;
+ %jmp T_3;
+ .thread T_3;
+ .scope S_0x55a79e658120;
+T_4 ;
+ %vpi_call 2 30 "$dumpfile", "tb_count_monitor.vcd" {0 0 0};
+ %vpi_call 2 31 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55a79e658120 {0 0 0};
+ %vpi_call 2 33 "$monitor", "Time = %0t clk = %0d sig = %0d", $time, v0x55a79e6a3350_0, v0x55a79e6a3eb0_0 {0 0 0};
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55a79e6a3350_0, 0;
+ %end;
+ .thread T_4;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+ "N/A";
+ "<interactive>";
+ "tb_counter_monitor.v";
+ "count_monitor.v";
diff --git a/verilog/rtl/my_design/tb_count_monitor.vcd b/verilog/rtl/my_design/tb_count_monitor.vcd
new file mode 100644
index 0000000..412edd3
--- /dev/null
+++ b/verilog/rtl/my_design/tb_count_monitor.vcd
Binary files differ
diff --git a/verilog/rtl/my_design/tb_counter_monitor.v b/verilog/rtl/my_design/tb_counter_monitor.v
new file mode 100644
index 0000000..e3de967
--- /dev/null
+++ b/verilog/rtl/my_design/tb_counter_monitor.v
@@ -0,0 +1,40 @@
+
+`timescale 1ns/1ns
+module tb_count_monitor;
+
+ reg clk;
+
+
+ count_monitor ccc ( .clk(clk),
+ .comp_en (comp_en),
+ .sample (sample),
+ .d1 (d1),
+ .d1b (d1b),
+ .d2 (d2),
+ .d2b (d2b),
+ .d3 (d3),
+ .d3b (d3b),
+ .d4 (d4),
+ .d4b (d4b),
+ .d5 (d5),
+ .d5b (d5b),
+ .d6 (d6),
+ .d6b (d6b),
+ .rs (rs));
+
+
+ // Generate clock
+ always #10 clk = ~clk;
+
+ // Testcase
+ initial begin
+ $dumpfile("tb_count_monitor.vcd"); // vcd file name
+ $dumpvars(0,tb_count_monitor); // dump targetは「全部」
+
+ $monitor("Time = %0t clk = %0d sig = %0d",$time,clk,sample);
+
+ clk <= 0;
+
+
+ end
+endmodule
diff --git a/verilog/rtl/my_design/tb_dff.o b/verilog/rtl/my_design/tb_dff.o
new file mode 100755
index 0000000..f6fade4
--- /dev/null
+++ b/verilog/rtl/my_design/tb_dff.o
@@ -0,0 +1,108 @@
+#! /usr/bin/vvp
+:ivl_version "10.3 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x560b8c55a2d0 .scope module, "tb_dff" "tb_dff" 2 3;
+ .timescale -9 -9;
+v0x560b8c56e730_0 .var "clk", 0 0;
+v0x560b8c56e7f0_0 .var "d", 0 0;
+v0x560b8c56e8c0_0 .var "delay", 2 0;
+v0x560b8c56e990_0 .var "i", 0 0;
+v0x560b8c56ea30_0 .net "q", 0 0, v0x560b8c56e420_0; 1 drivers
+v0x560b8c56eb20_0 .net "qn", 0 0, L_0x560b8c56ecc0; 1 drivers
+v0x560b8c56ebf0_0 .var "rst", 0 0;
+S_0x560b8c55a450 .scope module, "dff0" "dff" 2 10, 3 1 0, S_0x560b8c55a2d0;
+ .timescale 0 0;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x560b8c56ecc0 .functor NOT 1, v0x560b8c56e420_0, C4<0>, C4<0>, C4<0>;
+v0x560b8c5240b0_0 .net "clk", 0 0, v0x560b8c56e730_0; 1 drivers
+v0x560b8c56e360_0 .net "d", 0 0, v0x560b8c56e7f0_0; 1 drivers
+v0x560b8c56e420_0 .var "q", 0 0;
+v0x560b8c56e4c0_0 .net "qn", 0 0, L_0x560b8c56ecc0; alias, 1 drivers
+v0x560b8c56e580_0 .net "rst", 0 0, v0x560b8c56ebf0_0; 1 drivers
+E_0x560b8c55aaa0 .event posedge, v0x560b8c56e580_0, v0x560b8c5240b0_0;
+ .scope S_0x560b8c55a450;
+T_0 ;
+ %wait E_0x560b8c55aaa0;
+ %load/vec4 v0x560b8c56e580_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_0.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x560b8c56e420_0, 0;
+ %jmp T_0.1;
+T_0.0 ;
+ %load/vec4 v0x560b8c56e360_0;
+ %assign/vec4 v0x560b8c56e420_0, 0;
+T_0.1 ;
+ %jmp T_0;
+ .thread T_0;
+ .scope S_0x560b8c55a2d0;
+T_1 ;
+ %delay 10, 0;
+ %load/vec4 v0x560b8c56e730_0;
+ %inv;
+ %store/vec4 v0x560b8c56e730_0, 0, 1;
+ %jmp T_1;
+ .thread T_1;
+ .scope S_0x560b8c55a2d0;
+T_2 ;
+ %delay 15, 0;
+ %load/vec4 v0x560b8c56ebf0_0;
+ %inv;
+ %store/vec4 v0x560b8c56ebf0_0, 0, 1;
+ %jmp T_2;
+ .thread T_2;
+ .scope S_0x560b8c55a2d0;
+T_3 ;
+ %vpi_call 2 22 "$dumpfile", "tb_dff.vcd" {0 0 0};
+ %vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x560b8c55a2d0 {0 0 0};
+ %vpi_call 2 25 "$monitor", "Time = %0t clk = %0d sig = %0d", $time, v0x560b8c56e730_0, v0x560b8c56ea30_0 {0 0 0};
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x560b8c56e730_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x560b8c56e7f0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x560b8c56ebf0_0, 0;
+ %delay 15, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x560b8c56e7f0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x560b8c56e990_0, 0, 1;
+T_3.0 ;
+ %load/vec4 v0x560b8c56e990_0;
+ %pad/u 32;
+ %cmpi/u 5, 0, 32;
+ %jmp/0xz T_3.1, 5;
+ %vpi_func 2 33 "$random" 32 {0 0 0};
+ %pad/s 3;
+ %store/vec4 v0x560b8c56e8c0_0, 0, 3;
+ %load/vec4 v0x560b8c56e8c0_0;
+ %pad/u 64;
+ %muli 1, 0, 64;
+ %ix/vec4 4;
+ %delayx 4;
+ %load/vec4 v0x560b8c56e990_0;
+ %assign/vec4 v0x560b8c56e7f0_0, 0;
+ %load/vec4 v0x560b8c56e990_0;
+ %pad/u 2;
+ %addi 1, 0, 2;
+ %pad/u 1;
+ %store/vec4 v0x560b8c56e990_0, 0, 1;
+ %jmp T_3.0;
+T_3.1 ;
+ %end;
+ .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+ "N/A";
+ "<interactive>";
+ "tb_dff.v";
+ "dff.v";
diff --git a/verilog/rtl/my_design/tb_dff.v b/verilog/rtl/my_design/tb_dff.v
new file mode 100644
index 0000000..28d48a1
--- /dev/null
+++ b/verilog/rtl/my_design/tb_dff.v
@@ -0,0 +1,37 @@
+
+`timescale 1ns/1ns
+module tb_dff;
+ reg clk;
+ reg d;
+ reg rst;
+ reg [2:0] delay;
+ reg i;
+
+ dff dff0 ( .d(d),
+ .rst (rst),
+ .clk (clk),
+ .q (q),
+ .qn (qn));
+
+ // Generate clock
+ always #10 clk = ~clk;
+ always #15 rst = ~rst;
+
+ // Testcase
+ initial begin
+ $dumpfile("tb_dff.vcd"); // vcd file name
+ $dumpvars(0,tb_dff); // dump targetは「全部」
+
+ $monitor("Time = %0t clk = %0d sig = %0d",$time,clk,q);
+
+ clk <= 0;
+ d <= 0;
+ rst <= 0;
+
+ #15 d <= 1;
+ for (i = 0; i < 5; i=i+1) begin
+ delay = $random;
+ #(delay) d <= i;
+ end
+ end
+endmodule
diff --git a/verilog/rtl/my_design/tb_dff.vcd b/verilog/rtl/my_design/tb_dff.vcd
new file mode 100644
index 0000000..101d6d1
--- /dev/null
+++ b/verilog/rtl/my_design/tb_dff.vcd
Binary files differ
diff --git a/verilog/rtl/my_design/tb_main.o b/verilog/rtl/my_design/tb_main.o
new file mode 100755
index 0000000..7fca90d
--- /dev/null
+++ b/verilog/rtl/my_design/tb_main.o
@@ -0,0 +1,884 @@
+#! /usr/bin/vvp
+:ivl_version "10.3 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x55cb3978f5d0 .scope module, "tb_main" "tb_main" 2 3;
+ .timescale -9 -9;
+v0x55cb397b6ff0_0 .var "clk", 0 0;
+v0x55cb397b70b0_0 .net "comp_en", 0 0, v0x55cb39789910_0; 1 drivers
+v0x55cb397b7170_0 .var "comp_in", 0 0;
+v0x55cb397b7320_0 .net "d1", 0 0, v0x55cb39789a10_0; 1 drivers
+v0x55cb397b73c0_0 .net "d1b", 0 0, L_0x55cb397b9070; 1 drivers
+v0x55cb397b7460_0 .net "d2", 0 0, v0x55cb3978a6a0_0; 1 drivers
+v0x55cb397b7500_0 .net "d2b", 0 0, L_0x55cb397b90e0; 1 drivers
+v0x55cb397b75a0_0 .net "d3", 0 0, v0x55cb397841b0_0; 1 drivers
+v0x55cb397b7640_0 .net "d4", 0 0, v0x55cb397ac6a0_0; 1 drivers
+RS_0x7f32a9226168 .resolv tri, L_0x55cb397b9150, L_0x55cb397b91c0;
+v0x55cb397b7770_0 .net8 "d4b", 0 0, RS_0x7f32a9226168; 2 drivers
+v0x55cb397b7920_0 .net "d5", 0 0, v0x55cb397ac800_0; 1 drivers
+v0x55cb397b79c0_0 .net "d5b", 0 0, L_0x55cb397b9260; 1 drivers
+v0x55cb397b7a60_0 .net "d6", 0 0, v0x55cb397ac960_0; 1 drivers
+v0x55cb397b7b00_0 .net "q0", 0 0, v0x55cb397b0fe0_0; 1 drivers
+v0x55cb397b7ba0_0 .net "q1", 0 0, v0x55cb397b1770_0; 1 drivers
+v0x55cb397b7c40_0 .net "q2", 0 0, v0x55cb397b1e40_0; 1 drivers
+v0x55cb397b7ce0_0 .net "q3", 0 0, v0x55cb397b24e0_0; 1 drivers
+v0x55cb397b7e90_0 .net "q4", 0 0, v0x55cb397b2c20_0; 1 drivers
+v0x55cb397b7f30_0 .net "q5", 0 0, v0x55cb397b3310_0; 1 drivers
+v0x55cb397b7fd0_0 .net "r0", 0 0, v0x55cb397ad560_0; 1 drivers
+v0x55cb397b8070_0 .net "r1", 0 0, v0x55cb397adbb0_0; 1 drivers
+v0x55cb397b8110_0 .net "r2", 0 0, v0x55cb397ae370_0; 1 drivers
+v0x55cb397b81b0_0 .net "r3", 0 0, v0x55cb397aea10_0; 1 drivers
+v0x55cb397b8250_0 .net "r4", 0 0, v0x55cb397af160_0; 1 drivers
+v0x55cb397b82f0_0 .net "r5", 0 0, v0x55cb397af870_0; 1 drivers
+v0x55cb397b8390_0 .net "rs", 0 0, v0x55cb397acae0_0; 1 drivers
+v0x55cb397b8430_0 .net "sample", 0 0, v0x55cb397acba0_0; 1 drivers
+v0x55cb397b86e0_0 .net "sw0", 0 0, L_0x55cb397baba0; 1 drivers
+v0x55cb397b8780_0 .net "sw0b", 0 0, L_0x55cb397bad40; 1 drivers
+v0x55cb397b8820_0 .net "sw1", 0 0, L_0x55cb397ba840; 1 drivers
+v0x55cb397b88c0_0 .net "sw1b", 0 0, L_0x55cb397ba740; 1 drivers
+v0x55cb397b8960_0 .net "sw2", 0 0, L_0x55cb397ba560; 1 drivers
+v0x55cb397b8a00_0 .net "sw2b", 0 0, L_0x55cb397ba6b0; 1 drivers
+v0x55cb397b8cb0_0 .net "sw3", 0 0, L_0x55cb397ba290; 1 drivers
+v0x55cb397b8d50_0 .net "sw3b", 0 0, L_0x55cb397ba3e0; 1 drivers
+v0x55cb397b8df0_0 .net "sw4", 0 0, L_0x55cb397ba050; 1 drivers
+v0x55cb397b8e90_0 .net "sw4b", 0 0, L_0x55cb397ba150; 1 drivers
+v0x55cb397b8f30_0 .net "sw5", 0 0, L_0x55cb397b9e70; 1 drivers
+v0x55cb397b8fd0_0 .net "sw5b", 0 0, L_0x55cb397b9f00; 1 drivers
+S_0x55cb3978e9d0 .scope module, "mmm" "sar_logic" 2 9, 3 1 0, S_0x55cb3978f5d0;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "clk"
+ .port_info 1 /INPUT 1 "comp_in"
+ .port_info 2 /OUTPUT 1 "comp_en"
+ .port_info 3 /OUTPUT 1 "sample"
+ .port_info 4 /OUTPUT 1 "q5"
+ .port_info 5 /OUTPUT 1 "q4"
+ .port_info 6 /OUTPUT 1 "q3"
+ .port_info 7 /OUTPUT 1 "q2"
+ .port_info 8 /OUTPUT 1 "q1"
+ .port_info 9 /OUTPUT 1 "q0"
+ .port_info 10 /OUTPUT 1 "sw5"
+ .port_info 11 /OUTPUT 1 "sw5b"
+ .port_info 12 /OUTPUT 1 "sw4"
+ .port_info 13 /OUTPUT 1 "sw4b"
+ .port_info 14 /OUTPUT 1 "sw3"
+ .port_info 15 /OUTPUT 1 "sw3b"
+ .port_info 16 /OUTPUT 1 "sw2"
+ .port_info 17 /OUTPUT 1 "sw2b"
+ .port_info 18 /OUTPUT 1 "sw1"
+ .port_info 19 /OUTPUT 1 "sw1b"
+ .port_info 20 /OUTPUT 1 "sw0"
+ .port_info 21 /OUTPUT 1 "sw0b"
+ .port_info 22 /OUTPUT 1 "rs"
+ .port_info 23 /OUTPUT 1 "r5"
+ .port_info 24 /OUTPUT 1 "r4"
+ .port_info 25 /OUTPUT 1 "r3"
+ .port_info 26 /OUTPUT 1 "r2"
+ .port_info 27 /OUTPUT 1 "r1"
+ .port_info 28 /OUTPUT 1 "r0"
+ .port_info 29 /OUTPUT 1 "d1"
+ .port_info 30 /OUTPUT 1 "d1b"
+ .port_info 31 /OUTPUT 1 "d2"
+ .port_info 32 /OUTPUT 1 "d2b"
+ .port_info 33 /OUTPUT 1 "d3"
+ .port_info 34 /OUTPUT 1 "d3b"
+ .port_info 35 /OUTPUT 1 "d4"
+ .port_info 36 /OUTPUT 1 "d4b"
+ .port_info 37 /OUTPUT 1 "d5"
+ .port_info 38 /OUTPUT 1 "d5b"
+ .port_info 39 /OUTPUT 1 "d6"
+L_0x55cb397b9db0 .functor OR 1, v0x55cb397acba0_0, v0x55cb397af870_0, C4<0>, C4<0>;
+L_0x55cb397b9e70 .functor OR 1, L_0x55cb397b9db0, v0x55cb397ac960_0, C4<0>, C4<0>;
+L_0x55cb397b9f00 .functor NOT 1, L_0x55cb397b9e70, C4<0>, C4<0>, C4<0>;
+L_0x55cb397b9f90 .functor OR 1, v0x55cb397acba0_0, v0x55cb397af160_0, C4<0>, C4<0>;
+L_0x55cb397ba050 .functor OR 1, L_0x55cb397b9f90, v0x55cb397ac800_0, C4<0>, C4<0>;
+L_0x55cb397ba150 .functor NOT 1, L_0x55cb397ba050, C4<0>, C4<0>, C4<0>;
+L_0x55cb397ba200 .functor OR 1, v0x55cb397acba0_0, v0x55cb397aea10_0, C4<0>, C4<0>;
+L_0x55cb397ba290 .functor OR 1, L_0x55cb397ba200, v0x55cb397ac6a0_0, C4<0>, C4<0>;
+L_0x55cb397ba3e0 .functor NOT 1, L_0x55cb397ba290, C4<0>, C4<0>, C4<0>;
+L_0x55cb397ba470 .functor OR 1, v0x55cb397acba0_0, v0x55cb397ae370_0, C4<0>, C4<0>;
+L_0x55cb397ba560 .functor OR 1, L_0x55cb397ba470, v0x55cb397841b0_0, C4<0>, C4<0>;
+L_0x55cb397ba6b0 .functor NOT 1, L_0x55cb397ba560, C4<0>, C4<0>, C4<0>;
+L_0x55cb397ba7b0 .functor OR 1, v0x55cb397acba0_0, v0x55cb397adbb0_0, C4<0>, C4<0>;
+L_0x55cb397ba840 .functor OR 1, L_0x55cb397ba7b0, v0x55cb3978a6a0_0, C4<0>, C4<0>;
+L_0x55cb397ba740 .functor NOT 1, L_0x55cb397ba840, C4<0>, C4<0>, C4<0>;
+L_0x55cb397baa80 .functor OR 1, v0x55cb397acba0_0, v0x55cb397ad560_0, C4<0>, C4<0>;
+L_0x55cb397baba0 .functor OR 1, L_0x55cb397baa80, v0x55cb39789a10_0, C4<0>, C4<0>;
+L_0x55cb397bad40 .functor NOT 1, L_0x55cb397baba0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b4290_0 .net *"_s0", 0 0, L_0x55cb397b9db0; 1 drivers
+v0x55cb397b4390_0 .net *"_s12", 0 0, L_0x55cb397ba200; 1 drivers
+v0x55cb397b4470_0 .net *"_s18", 0 0, L_0x55cb397ba470; 1 drivers
+v0x55cb397b4560_0 .net *"_s24", 0 0, L_0x55cb397ba7b0; 1 drivers
+v0x55cb397b4640_0 .net *"_s30", 0 0, L_0x55cb397baa80; 1 drivers
+v0x55cb397b4720_0 .net *"_s6", 0 0, L_0x55cb397b9f90; 1 drivers
+v0x55cb397b4800_0 .net "clk", 0 0, v0x55cb397b6ff0_0; 1 drivers
+v0x55cb397b48a0_0 .net "comp_en", 0 0, v0x55cb39789910_0; alias, 1 drivers
+v0x55cb397b4970_0 .net "comp_in", 0 0, v0x55cb397b7170_0; 1 drivers
+v0x55cb397b4aa0_0 .net "d1", 0 0, v0x55cb39789a10_0; alias, 1 drivers
+v0x55cb397b4b70_0 .net "d1b", 0 0, L_0x55cb397b9070; alias, 1 drivers
+v0x55cb397b4c10_0 .net "d2", 0 0, v0x55cb3978a6a0_0; alias, 1 drivers
+v0x55cb397b4ce0_0 .net "d2b", 0 0, L_0x55cb397b90e0; alias, 1 drivers
+v0x55cb397b4d80_0 .net "d3", 0 0, v0x55cb397841b0_0; alias, 1 drivers
+v0x55cb397b4e50_0 .net8 "d3b", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397b4ef0_0 .net "d4", 0 0, v0x55cb397ac6a0_0; alias, 1 drivers
+v0x55cb397b4fc0_0 .net8 "d4b", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397b5170_0 .net "d5", 0 0, v0x55cb397ac800_0; alias, 1 drivers
+v0x55cb397b5240_0 .net "d5b", 0 0, L_0x55cb397b9260; alias, 1 drivers
+v0x55cb397b52e0_0 .net "d6", 0 0, v0x55cb397ac960_0; alias, 1 drivers
+o0x7f32a9226258 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55cb397b53b0_0 .net "d6b", 0 0, o0x7f32a9226258; 0 drivers
+v0x55cb397b5450_0 .net "q0", 0 0, v0x55cb397b0fe0_0; alias, 1 drivers
+v0x55cb397b54f0_0 .net "q1", 0 0, v0x55cb397b1770_0; alias, 1 drivers
+v0x55cb397b55e0_0 .net "q2", 0 0, v0x55cb397b1e40_0; alias, 1 drivers
+v0x55cb397b56d0_0 .net "q3", 0 0, v0x55cb397b24e0_0; alias, 1 drivers
+v0x55cb397b57c0_0 .net "q4", 0 0, v0x55cb397b2c20_0; alias, 1 drivers
+v0x55cb397b58b0_0 .net "q5", 0 0, v0x55cb397b3310_0; alias, 1 drivers
+v0x55cb397b59a0_0 .net "r0", 0 0, v0x55cb397ad560_0; alias, 1 drivers
+v0x55cb397b5a40_0 .net "r1", 0 0, v0x55cb397adbb0_0; alias, 1 drivers
+v0x55cb397b5ae0_0 .net "r2", 0 0, v0x55cb397ae370_0; alias, 1 drivers
+v0x55cb397b5c10_0 .net "r3", 0 0, v0x55cb397aea10_0; alias, 1 drivers
+v0x55cb397b5d40_0 .net "r4", 0 0, v0x55cb397af160_0; alias, 1 drivers
+v0x55cb397b5e70_0 .net "r5", 0 0, v0x55cb397af870_0; alias, 1 drivers
+v0x55cb397b61b0_0 .net "rs", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b6250_0 .net "sample", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+v0x55cb397b62f0_0 .net "sw0", 0 0, L_0x55cb397baba0; alias, 1 drivers
+v0x55cb397b6390_0 .net "sw0b", 0 0, L_0x55cb397bad40; alias, 1 drivers
+v0x55cb397b6430_0 .net "sw1", 0 0, L_0x55cb397ba840; alias, 1 drivers
+v0x55cb397b64d0_0 .net "sw1b", 0 0, L_0x55cb397ba740; alias, 1 drivers
+v0x55cb397b6570_0 .net "sw2", 0 0, L_0x55cb397ba560; alias, 1 drivers
+v0x55cb397b6610_0 .net "sw2b", 0 0, L_0x55cb397ba6b0; alias, 1 drivers
+v0x55cb397b66b0_0 .net "sw3", 0 0, L_0x55cb397ba290; alias, 1 drivers
+v0x55cb397b6750_0 .net "sw3b", 0 0, L_0x55cb397ba3e0; alias, 1 drivers
+v0x55cb397b67f0_0 .net "sw4", 0 0, L_0x55cb397ba050; alias, 1 drivers
+v0x55cb397b68b0_0 .net "sw4b", 0 0, L_0x55cb397ba150; alias, 1 drivers
+v0x55cb397b6970_0 .net "sw5", 0 0, L_0x55cb397b9e70; alias, 1 drivers
+v0x55cb397b6a30_0 .net "sw5b", 0 0, L_0x55cb397b9f00; alias, 1 drivers
+S_0x55cb3978ddd0 .scope module, "ccc" "count_monitor" 3 43, 4 2 0, S_0x55cb3978e9d0;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "clk"
+ .port_info 1 /OUTPUT 1 "comp_en"
+ .port_info 2 /OUTPUT 1 "sample"
+ .port_info 3 /OUTPUT 1 "d1"
+ .port_info 4 /OUTPUT 1 "d1b"
+ .port_info 5 /OUTPUT 1 "d2"
+ .port_info 6 /OUTPUT 1 "d2b"
+ .port_info 7 /OUTPUT 1 "d3"
+ .port_info 8 /OUTPUT 1 "d3b"
+ .port_info 9 /OUTPUT 1 "d4"
+ .port_info 10 /OUTPUT 1 "d4b"
+ .port_info 11 /OUTPUT 1 "d5"
+ .port_info 12 /OUTPUT 1 "d5b"
+ .port_info 13 /OUTPUT 1 "d6"
+ .port_info 14 /OUTPUT 1 "d6b"
+ .port_info 15 /OUTPUT 1 "rs"
+L_0x55cb397b9070 .functor NOT 1, v0x55cb39789a10_0, C4<0>, C4<0>, C4<0>;
+L_0x55cb397b90e0 .functor NOT 1, v0x55cb3978a6a0_0, C4<0>, C4<0>, C4<0>;
+L_0x55cb397b9150 .functor NOT 1, v0x55cb397841b0_0, C4<0>, C4<0>, C4<0>;
+L_0x55cb397b91c0 .functor NOT 1, v0x55cb397ac6a0_0, C4<0>, C4<0>, C4<0>;
+L_0x55cb397b9260 .functor NOT 1, v0x55cb397ac800_0, C4<0>, C4<0>, C4<0>;
+v0x55cb39788d80_0 .net "clk", 0 0, v0x55cb397b6ff0_0; alias, 1 drivers
+v0x55cb39789910_0 .var "comp_en", 0 0;
+v0x55cb39789a10_0 .var "d1", 0 0;
+v0x55cb3978a5a0_0 .net "d1b", 0 0, L_0x55cb397b9070; alias, 1 drivers
+v0x55cb3978a6a0_0 .var "d2", 0 0;
+v0x55cb397840b0_0 .net "d2b", 0 0, L_0x55cb397b90e0; alias, 1 drivers
+v0x55cb397841b0_0 .var "d3", 0 0;
+v0x55cb397ac5e0_0 .net8 "d3b", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397ac6a0_0 .var "d4", 0 0;
+v0x55cb397ac760_0 .net8 "d4b", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397ac800_0 .var "d5", 0 0;
+v0x55cb397ac8a0_0 .net "d5b", 0 0, L_0x55cb397b9260; alias, 1 drivers
+v0x55cb397ac960_0 .var "d6", 0 0;
+v0x55cb397aca20_0 .net "d6b", 0 0, o0x7f32a9226258; alias, 0 drivers
+v0x55cb397acae0_0 .var "rs", 0 0;
+v0x55cb397acba0_0 .var "sample", 0 0;
+v0x55cb397acc60_0 .var "sar_counter", 4 0;
+E_0x55cb39763d30 .event negedge, v0x55cb39788d80_0;
+E_0x55cb39763f30 .event posedge, v0x55cb39788d80_0;
+S_0x55cb397acf40 .scope module, "hhh" "hold" 3 60, 5 2 0, S_0x55cb3978e9d0;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "comp_in"
+ .port_info 1 /INPUT 1 "sample"
+ .port_info 2 /INPUT 1 "d1b"
+ .port_info 3 /INPUT 1 "d2b"
+ .port_info 4 /INPUT 1 "d3b"
+ .port_info 5 /INPUT 1 "d4b"
+ .port_info 6 /INPUT 1 "d5b"
+ .port_info 7 /INPUT 1 "d6b"
+ .port_info 8 /OUTPUT 1 "r5"
+ .port_info 9 /OUTPUT 1 "r4"
+ .port_info 10 /OUTPUT 1 "r3"
+ .port_info 11 /OUTPUT 1 "r2"
+ .port_info 12 /OUTPUT 1 "r1"
+ .port_info 13 /OUTPUT 1 "r0"
+v0x55cb397afb70_0 .net "comp_in", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397afc30_0 .net "d1b", 0 0, L_0x55cb397b9070; alias, 1 drivers
+v0x55cb397afd40_0 .net "d2b", 0 0, L_0x55cb397b90e0; alias, 1 drivers
+v0x55cb397afe30_0 .net8 "d3b", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397aff60_0 .net8 "d4b", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397b0000_0 .net "d5b", 0 0, L_0x55cb397b9260; alias, 1 drivers
+v0x55cb397b00f0_0 .net "d6b", 0 0, o0x7f32a9226258; alias, 0 drivers
+v0x55cb397b01e0_0 .net "r0", 0 0, v0x55cb397ad560_0; alias, 1 drivers
+v0x55cb397b0280_0 .net "r1", 0 0, v0x55cb397adbb0_0; alias, 1 drivers
+v0x55cb397b03b0_0 .net "r2", 0 0, v0x55cb397ae370_0; alias, 1 drivers
+v0x55cb397b0450_0 .net "r3", 0 0, v0x55cb397aea10_0; alias, 1 drivers
+v0x55cb397b04f0_0 .net "r4", 0 0, v0x55cb397af160_0; alias, 1 drivers
+v0x55cb397b0590_0 .net "r5", 0 0, v0x55cb397af870_0; alias, 1 drivers
+v0x55cb397b0660_0 .net "sample", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397ad240 .scope module, "dff0" "dff" 5 42, 6 3 0, S_0x55cb397acf40;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9590 .functor NOT 1, v0x55cb397ad560_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397ad400_0 .net "clk", 0 0, L_0x55cb397b9070; alias, 1 drivers
+v0x55cb397ad4c0_0 .net "d", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397ad560_0 .var "q", 0 0;
+v0x55cb397ad600_0 .net "qn", 0 0, L_0x55cb397b9590; 1 drivers
+v0x55cb397ad6c0_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+E_0x55cb39764190 .event posedge, v0x55cb397acba0_0, v0x55cb3978a5a0_0;
+S_0x55cb397ad7e0 .scope module, "dff1" "dff" 5 37, 6 3 0, S_0x55cb397acf40;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b94f0 .functor NOT 1, v0x55cb397adbb0_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397ad9f0_0 .net "clk", 0 0, L_0x55cb397b90e0; alias, 1 drivers
+v0x55cb397adae0_0 .net "d", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397adbb0_0 .var "q", 0 0;
+v0x55cb397adc80_0 .net "qn", 0 0, L_0x55cb397b94f0; 1 drivers
+v0x55cb397add20_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+E_0x55cb39762510 .event posedge, v0x55cb397acba0_0, v0x55cb397840b0_0;
+S_0x55cb397adee0 .scope module, "dff2" "dff" 5 32, 6 3 0, S_0x55cb397acf40;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9450 .functor NOT 1, v0x55cb397ae370_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397ae150_0 .net8 "clk", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397ae260_0 .net "d", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397ae370_0 .var "q", 0 0;
+v0x55cb397ae410_0 .net "qn", 0 0, L_0x55cb397b9450; 1 drivers
+v0x55cb397ae4b0_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+E_0x55cb397644c0 .event posedge, v0x55cb397acba0_0, v0x55cb397ac5e0_0;
+S_0x55cb397ae640 .scope module, "dff3" "dff" 5 27, 6 3 0, S_0x55cb397acf40;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b93b0 .functor NOT 1, v0x55cb397aea10_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397ae890_0 .net8 "clk", 0 0, RS_0x7f32a9226168; alias, 2 drivers
+v0x55cb397ae950_0 .net "d", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397aea10_0 .var "q", 0 0;
+v0x55cb397aeab0_0 .net "qn", 0 0, L_0x55cb397b93b0; 1 drivers
+v0x55cb397aeb50_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397aece0 .scope module, "dff4" "dff" 5 22, 6 3 0, S_0x55cb397acf40;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9340 .functor NOT 1, v0x55cb397af160_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397aef70_0 .net "clk", 0 0, L_0x55cb397b9260; alias, 1 drivers
+v0x55cb397af030_0 .net "d", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397af160_0 .var "q", 0 0;
+v0x55cb397af230_0 .net "qn", 0 0, L_0x55cb397b9340; 1 drivers
+v0x55cb397af2d0_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+E_0x55cb39791e90 .event posedge, v0x55cb397acba0_0, v0x55cb397ac8a0_0;
+S_0x55cb397af410 .scope module, "dff5" "dff" 5 17, 6 3 0, S_0x55cb397acf40;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b92d0 .functor NOT 1, v0x55cb397af870_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397af6e0_0 .net "clk", 0 0, o0x7f32a9226258; alias, 0 drivers
+v0x55cb397af7d0_0 .net "d", 0 0, v0x55cb397b7170_0; alias, 1 drivers
+v0x55cb397af870_0 .var "q", 0 0;
+v0x55cb397af940_0 .net "qn", 0 0, L_0x55cb397b92d0; 1 drivers
+v0x55cb397af9e0_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+E_0x55cb397af660 .event posedge, v0x55cb397acba0_0, v0x55cb397aca20_0;
+S_0x55cb397b0840 .scope module, "qqq" "qout" 3 75, 7 2 0, S_0x55cb3978e9d0;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "sample"
+ .port_info 1 /INPUT 1 "rs"
+ .port_info 2 /INPUT 1 "r5"
+ .port_info 3 /INPUT 1 "r4"
+ .port_info 4 /INPUT 1 "r3"
+ .port_info 5 /INPUT 1 "r2"
+ .port_info 6 /INPUT 1 "r1"
+ .port_info 7 /INPUT 1 "r0"
+ .port_info 8 /OUTPUT 1 "q5"
+ .port_info 9 /OUTPUT 1 "q4"
+ .port_info 10 /OUTPUT 1 "q3"
+ .port_info 11 /OUTPUT 1 "q2"
+ .port_info 12 /OUTPUT 1 "q1"
+ .port_info 13 /OUTPUT 1 "q0"
+v0x55cb397b35e0_0 .net "q0", 0 0, v0x55cb397b0fe0_0; alias, 1 drivers
+v0x55cb397b36a0_0 .net "q1", 0 0, v0x55cb397b1770_0; alias, 1 drivers
+v0x55cb397b3740_0 .net "q2", 0 0, v0x55cb397b1e40_0; alias, 1 drivers
+v0x55cb397b3840_0 .net "q3", 0 0, v0x55cb397b24e0_0; alias, 1 drivers
+v0x55cb397b3910_0 .net "q4", 0 0, v0x55cb397b2c20_0; alias, 1 drivers
+v0x55cb397b3a00_0 .net "q5", 0 0, v0x55cb397b3310_0; alias, 1 drivers
+v0x55cb397b3ad0_0 .net "r0", 0 0, v0x55cb397ad560_0; alias, 1 drivers
+o0x7f32a92270c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55cb397b3bc0_0 .net "r0n", 0 0, o0x7f32a92270c8; 0 drivers
+v0x55cb397b3c60_0 .net "r1", 0 0, v0x55cb397adbb0_0; alias, 1 drivers
+v0x55cb397b3d90_0 .net "r2", 0 0, v0x55cb397ae370_0; alias, 1 drivers
+v0x55cb397b3e30_0 .net "r3", 0 0, v0x55cb397aea10_0; alias, 1 drivers
+v0x55cb397b3ed0_0 .net "r4", 0 0, v0x55cb397af160_0; alias, 1 drivers
+v0x55cb397b3f70_0 .net "r5", 0 0, v0x55cb397af870_0; alias, 1 drivers
+v0x55cb397b4010_0 .net "rs", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b40b0_0 .net "sample", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397b0b50 .scope module, "dff1" "dff" 7 42, 6 3 0, S_0x55cb397b0840;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9c60 .functor NOT 1, v0x55cb397b0fe0_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b0e50_0 .net "clk", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b0f40_0 .net "d", 0 0, o0x7f32a92270c8; alias, 0 drivers
+v0x55cb397b0fe0_0 .var "q", 0 0;
+v0x55cb397b10b0_0 .net "qn", 0 0, L_0x55cb397b9c60; 1 drivers
+v0x55cb397b1170_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+E_0x55cb397b0dd0 .event posedge, v0x55cb397acba0_0, v0x55cb397acae0_0;
+S_0x55cb397b1300 .scope module, "dff2" "dff" 7 37, 6 3 0, S_0x55cb397b0840;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9b10 .functor NOT 1, v0x55cb397b1770_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b1570_0 .net "clk", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b1660_0 .net "d", 0 0, v0x55cb397adbb0_0; alias, 1 drivers
+v0x55cb397b1770_0 .var "q", 0 0;
+v0x55cb397b1810_0 .net "qn", 0 0, L_0x55cb397b9b10; 1 drivers
+v0x55cb397b18b0_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397b1a40 .scope module, "dff3" "dff" 7 32, 6 3 0, S_0x55cb397b0840;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b99c0 .functor NOT 1, v0x55cb397b1e40_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b1c90_0 .net "clk", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b1d30_0 .net "d", 0 0, v0x55cb397ae370_0; alias, 1 drivers
+v0x55cb397b1e40_0 .var "q", 0 0;
+v0x55cb397b1ee0_0 .net "qn", 0 0, L_0x55cb397b99c0; 1 drivers
+v0x55cb397b1f80_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397b2110 .scope module, "dff4" "dff" 7 27, 6 3 0, S_0x55cb397b0840;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9890 .functor NOT 1, v0x55cb397b24e0_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b2360_0 .net "clk", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b2420_0 .net "d", 0 0, v0x55cb397aea10_0; alias, 1 drivers
+v0x55cb397b24e0_0 .var "q", 0 0;
+v0x55cb397b2580_0 .net "qn", 0 0, L_0x55cb397b9890; 1 drivers
+v0x55cb397b2620_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397b27b0 .scope module, "dff5" "dff" 7 22, 6 3 0, S_0x55cb397b0840;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9760 .functor NOT 1, v0x55cb397b2c20_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b2a50_0 .net "clk", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b2b10_0 .net "d", 0 0, v0x55cb397af160_0; alias, 1 drivers
+v0x55cb397b2c20_0 .var "q", 0 0;
+v0x55cb397b2cc0_0 .net "qn", 0 0, L_0x55cb397b9760; 1 drivers
+v0x55cb397b2d60_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+S_0x55cb397b2ef0 .scope module, "dff6" "dff" 7 17, 6 3 0, S_0x55cb397b0840;
+ .timescale -9 -9;
+ .port_info 0 /INPUT 1 "d"
+ .port_info 1 /INPUT 1 "rst"
+ .port_info 2 /INPUT 1 "clk"
+ .port_info 3 /OUTPUT 1 "q"
+ .port_info 4 /OUTPUT 1 "qn"
+L_0x55cb397b9630 .functor NOT 1, v0x55cb397b3310_0, C4<0>, C4<0>, C4<0>;
+v0x55cb397b3140_0 .net "clk", 0 0, v0x55cb397acae0_0; alias, 1 drivers
+v0x55cb397b3200_0 .net "d", 0 0, v0x55cb397af870_0; alias, 1 drivers
+v0x55cb397b3310_0 .var "q", 0 0;
+v0x55cb397b33b0_0 .net "qn", 0 0, L_0x55cb397b9630; 1 drivers
+v0x55cb397b3450_0 .net "rst", 0 0, v0x55cb397acba0_0; alias, 1 drivers
+ .scope S_0x55cb3978ddd0;
+T_0 ;
+ %pushi/vec4 8, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb39789910_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397acba0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb39789a10_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb3978a6a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397841b0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ac6a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ac800_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ac960_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397acae0_0, 0;
+ %end;
+ .thread T_0;
+ .scope S_0x55cb3978ddd0;
+T_1 ;
+ %wait E_0x55cb39763f30;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 8, 0, 32;
+ %jmp/0xz T_1.0, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397acba0_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.1;
+T_1.0 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 7, 0, 32;
+ %jmp/0xz T_1.2, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb39789910_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397ac960_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.3;
+T_1.2 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 6, 0, 32;
+ %jmp/0xz T_1.4, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397ac800_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ac960_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.5;
+T_1.4 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 5, 0, 32;
+ %jmp/0xz T_1.6, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397ac6a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ac800_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.7;
+T_1.6 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 4, 0, 32;
+ %jmp/0xz T_1.8, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397841b0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ac6a0_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.9;
+T_1.8 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 3, 0, 32;
+ %jmp/0xz T_1.10, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb3978a6a0_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397841b0_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.11;
+T_1.10 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 2, 0, 32;
+ %jmp/0xz T_1.12, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb39789a10_0, 0;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb3978a6a0_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.13;
+T_1.12 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 1, 0, 32;
+ %jmp/0xz T_1.14, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb39789a10_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb39789910_0, 0;
+ %load/vec4 v0x55cb397acc60_0;
+ %subi 1, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+ %jmp T_1.15;
+T_1.14 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 0, 0, 32;
+ %jmp/0xz T_1.16, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397acba0_0, 0;
+ %pushi/vec4 8, 0, 5;
+ %store/vec4 v0x55cb397acc60_0, 0, 5;
+T_1.16 ;
+T_1.15 ;
+T_1.13 ;
+T_1.11 ;
+T_1.9 ;
+T_1.7 ;
+T_1.5 ;
+T_1.3 ;
+T_1.1 ;
+ %jmp T_1;
+ .thread T_1;
+ .scope S_0x55cb3978ddd0;
+T_2 ;
+ %wait E_0x55cb39763d30;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 0, 0, 32;
+ %jmp/0xz T_2.0, 4;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397acae0_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397acba0_0, 0;
+ %jmp T_2.1;
+T_2.0 ;
+ %load/vec4 v0x55cb397acc60_0;
+ %pad/u 32;
+ %cmpi/e 8, 0, 32;
+ %jmp/0xz T_2.2, 4;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397acae0_0, 0;
+T_2.2 ;
+T_2.1 ;
+ %jmp T_2;
+ .thread T_2;
+ .scope S_0x55cb397af410;
+T_3 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397af870_0, 0;
+ %end;
+ .thread T_3;
+ .scope S_0x55cb397af410;
+T_4 ;
+ %wait E_0x55cb397af660;
+ %load/vec4 v0x55cb397af9e0_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_4.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397af870_0, 0;
+ %jmp T_4.1;
+T_4.0 ;
+ %load/vec4 v0x55cb397af7d0_0;
+ %assign/vec4 v0x55cb397af870_0, 0;
+T_4.1 ;
+ %jmp T_4;
+ .thread T_4;
+ .scope S_0x55cb397aece0;
+T_5 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397af160_0, 0;
+ %end;
+ .thread T_5;
+ .scope S_0x55cb397aece0;
+T_6 ;
+ %wait E_0x55cb39791e90;
+ %load/vec4 v0x55cb397af2d0_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_6.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397af160_0, 0;
+ %jmp T_6.1;
+T_6.0 ;
+ %load/vec4 v0x55cb397af030_0;
+ %assign/vec4 v0x55cb397af160_0, 0;
+T_6.1 ;
+ %jmp T_6;
+ .thread T_6;
+ .scope S_0x55cb397ae640;
+T_7 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397aea10_0, 0;
+ %end;
+ .thread T_7;
+ .scope S_0x55cb397ae640;
+T_8 ;
+ %wait E_0x55cb397644c0;
+ %load/vec4 v0x55cb397aeb50_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_8.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397aea10_0, 0;
+ %jmp T_8.1;
+T_8.0 ;
+ %load/vec4 v0x55cb397ae950_0;
+ %assign/vec4 v0x55cb397aea10_0, 0;
+T_8.1 ;
+ %jmp T_8;
+ .thread T_8;
+ .scope S_0x55cb397adee0;
+T_9 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ae370_0, 0;
+ %end;
+ .thread T_9;
+ .scope S_0x55cb397adee0;
+T_10 ;
+ %wait E_0x55cb397644c0;
+ %load/vec4 v0x55cb397ae4b0_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_10.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ae370_0, 0;
+ %jmp T_10.1;
+T_10.0 ;
+ %load/vec4 v0x55cb397ae260_0;
+ %assign/vec4 v0x55cb397ae370_0, 0;
+T_10.1 ;
+ %jmp T_10;
+ .thread T_10;
+ .scope S_0x55cb397ad7e0;
+T_11 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397adbb0_0, 0;
+ %end;
+ .thread T_11;
+ .scope S_0x55cb397ad7e0;
+T_12 ;
+ %wait E_0x55cb39762510;
+ %load/vec4 v0x55cb397add20_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_12.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397adbb0_0, 0;
+ %jmp T_12.1;
+T_12.0 ;
+ %load/vec4 v0x55cb397adae0_0;
+ %assign/vec4 v0x55cb397adbb0_0, 0;
+T_12.1 ;
+ %jmp T_12;
+ .thread T_12;
+ .scope S_0x55cb397ad240;
+T_13 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ad560_0, 0;
+ %end;
+ .thread T_13;
+ .scope S_0x55cb397ad240;
+T_14 ;
+ %wait E_0x55cb39764190;
+ %load/vec4 v0x55cb397ad6c0_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_14.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397ad560_0, 0;
+ %jmp T_14.1;
+T_14.0 ;
+ %load/vec4 v0x55cb397ad4c0_0;
+ %assign/vec4 v0x55cb397ad560_0, 0;
+T_14.1 ;
+ %jmp T_14;
+ .thread T_14;
+ .scope S_0x55cb397b2ef0;
+T_15 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b3310_0, 0;
+ %end;
+ .thread T_15;
+ .scope S_0x55cb397b2ef0;
+T_16 ;
+ %wait E_0x55cb397b0dd0;
+ %load/vec4 v0x55cb397b3450_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_16.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b3310_0, 0;
+ %jmp T_16.1;
+T_16.0 ;
+ %load/vec4 v0x55cb397b3200_0;
+ %assign/vec4 v0x55cb397b3310_0, 0;
+T_16.1 ;
+ %jmp T_16;
+ .thread T_16;
+ .scope S_0x55cb397b27b0;
+T_17 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b2c20_0, 0;
+ %end;
+ .thread T_17;
+ .scope S_0x55cb397b27b0;
+T_18 ;
+ %wait E_0x55cb397b0dd0;
+ %load/vec4 v0x55cb397b2d60_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_18.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b2c20_0, 0;
+ %jmp T_18.1;
+T_18.0 ;
+ %load/vec4 v0x55cb397b2b10_0;
+ %assign/vec4 v0x55cb397b2c20_0, 0;
+T_18.1 ;
+ %jmp T_18;
+ .thread T_18;
+ .scope S_0x55cb397b2110;
+T_19 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b24e0_0, 0;
+ %end;
+ .thread T_19;
+ .scope S_0x55cb397b2110;
+T_20 ;
+ %wait E_0x55cb397b0dd0;
+ %load/vec4 v0x55cb397b2620_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_20.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b24e0_0, 0;
+ %jmp T_20.1;
+T_20.0 ;
+ %load/vec4 v0x55cb397b2420_0;
+ %assign/vec4 v0x55cb397b24e0_0, 0;
+T_20.1 ;
+ %jmp T_20;
+ .thread T_20;
+ .scope S_0x55cb397b1a40;
+T_21 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b1e40_0, 0;
+ %end;
+ .thread T_21;
+ .scope S_0x55cb397b1a40;
+T_22 ;
+ %wait E_0x55cb397b0dd0;
+ %load/vec4 v0x55cb397b1f80_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_22.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b1e40_0, 0;
+ %jmp T_22.1;
+T_22.0 ;
+ %load/vec4 v0x55cb397b1d30_0;
+ %assign/vec4 v0x55cb397b1e40_0, 0;
+T_22.1 ;
+ %jmp T_22;
+ .thread T_22;
+ .scope S_0x55cb397b1300;
+T_23 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b1770_0, 0;
+ %end;
+ .thread T_23;
+ .scope S_0x55cb397b1300;
+T_24 ;
+ %wait E_0x55cb397b0dd0;
+ %load/vec4 v0x55cb397b18b0_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_24.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b1770_0, 0;
+ %jmp T_24.1;
+T_24.0 ;
+ %load/vec4 v0x55cb397b1660_0;
+ %assign/vec4 v0x55cb397b1770_0, 0;
+T_24.1 ;
+ %jmp T_24;
+ .thread T_24;
+ .scope S_0x55cb397b0b50;
+T_25 ;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b0fe0_0, 0;
+ %end;
+ .thread T_25;
+ .scope S_0x55cb397b0b50;
+T_26 ;
+ %wait E_0x55cb397b0dd0;
+ %load/vec4 v0x55cb397b1170_0;
+ %flag_set/vec4 8;
+ %jmp/0xz T_26.0, 8;
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b0fe0_0, 0;
+ %jmp T_26.1;
+T_26.0 ;
+ %load/vec4 v0x55cb397b0f40_0;
+ %assign/vec4 v0x55cb397b0fe0_0, 0;
+T_26.1 ;
+ %jmp T_26;
+ .thread T_26;
+ .scope S_0x55cb3978f5d0;
+T_27 ;
+ %delay 10, 0;
+ %load/vec4 v0x55cb397b6ff0_0;
+ %inv;
+ %store/vec4 v0x55cb397b6ff0_0, 0, 1;
+ %jmp T_27;
+ .thread T_27;
+ .scope S_0x55cb3978f5d0;
+T_28 ;
+ %delay 10, 0;
+ %load/vec4 v0x55cb397b7170_0;
+ %inv;
+ %store/vec4 v0x55cb397b7170_0, 0, 1;
+ %jmp T_28;
+ .thread T_28;
+ .scope S_0x55cb3978f5d0;
+T_29 ;
+ %vpi_call 2 57 "$dumpfile", "tb_main.vcd" {0 0 0};
+ %vpi_call 2 58 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55cb3978f5d0 {0 0 0};
+ %vpi_call 2 60 "$monitor", "Time = %0t clk = %0d sig = %0d", $time, v0x55cb397b6ff0_0, v0x55cb397b8430_0 {0 0 0};
+ %pushi/vec4 0, 0, 1;
+ %assign/vec4 v0x55cb397b6ff0_0, 0;
+ %pushi/vec4 1, 0, 1;
+ %assign/vec4 v0x55cb397b7170_0, 0;
+ %end;
+ .thread T_29;
+# The file index is used to find the file name in the following table.
+:file_names 8;
+ "N/A";
+ "<interactive>";
+ "tb_main.v";
+ "main.v";
+ "count_monitor.v";
+ "hold.v";
+ "dff.v";
+ "qout.v";
diff --git a/verilog/rtl/my_design/tb_main.v b/verilog/rtl/my_design/tb_main.v
new file mode 100644
index 0000000..2caa25b
--- /dev/null
+++ b/verilog/rtl/my_design/tb_main.v
@@ -0,0 +1,67 @@
+
+`timescale 1ns/1ns
+module tb_main;
+
+ reg clk;
+ reg comp_in;
+
+
+ sar_logic mmm (.clk(clk),
+ .comp_in(comp_in),
+ .comp_en(comp_en),
+ .sample(sample),
+ .q5(q5),
+ .q4(q4),
+ .q3(q3),
+ .q2(q2),
+ .q1(q1),
+ .q0(q0),
+ .sw5(sw5),
+ .sw5b(sw5b),
+ .sw4(sw4),
+ .sw4b(sw4b),
+ .sw3(sw3),
+ .sw3b(sw3b),
+ .sw2(sw2),
+ .sw2b(sw2b),
+ .sw1(sw1),
+ .sw1b(sw1b),
+ .sw0(sw0),
+ .sw0b(sw0b),
+ .rs(rs),
+ .r5(r5),
+ .r4(r4),
+ .r3(r3),
+ .r2(r2),
+ .r1(r1),
+ .r0(r0),
+ .d1(d1),
+ .d1b(d1b),
+ .d2(d2),
+ .d2b(d2b),
+ .d3(d3),
+ .d3b(d4b),
+ .d4(d4),
+ .d4b(d4b),
+ .d5(d5),
+ .d5b(d5b),
+ .d6(d6));
+
+
+ // Generate clock
+ always #10 clk = ~clk;
+ always #10 comp_in = ~comp_in;
+
+ // Testcase
+ initial begin
+ $dumpfile("tb_main.vcd"); // vcd file name
+ $dumpvars(0,tb_main); // dump targetは「全部」
+
+ $monitor("Time = %0t clk = %0d sig = %0d",$time,clk,sample);
+
+ clk <= 0;
+ comp_in <= 1;
+
+
+ end
+endmodule
diff --git a/verilog/rtl/my_design/tb_main.vcd b/verilog/rtl/my_design/tb_main.vcd
new file mode 100644
index 0000000..65eba69
--- /dev/null
+++ b/verilog/rtl/my_design/tb_main.vcd
@@ -0,0 +1,560473 @@
+$date
+ Thu May 19 22:09:02 2022
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1ns
+$end
+$scope module tb_main $end
+$var wire 1 ! d4b $end
+$var wire 1 " sw5b $end
+$var wire 1 # sw5 $end
+$var wire 1 $ sw4b $end
+$var wire 1 % sw4 $end
+$var wire 1 & sw3b $end
+$var wire 1 ' sw3 $end
+$var wire 1 ( sw2b $end
+$var wire 1 ) sw2 $end
+$var wire 1 * sw1b $end
+$var wire 1 + sw1 $end
+$var wire 1 , sw0b $end
+$var wire 1 - sw0 $end
+$var wire 1 . sample $end
+$var wire 1 / rs $end
+$var wire 1 0 r5 $end
+$var wire 1 1 r4 $end
+$var wire 1 2 r3 $end
+$var wire 1 3 r2 $end
+$var wire 1 4 r1 $end
+$var wire 1 5 r0 $end
+$var wire 1 6 q5 $end
+$var wire 1 7 q4 $end
+$var wire 1 8 q3 $end
+$var wire 1 9 q2 $end
+$var wire 1 : q1 $end
+$var wire 1 ; q0 $end
+$var wire 1 < d6 $end
+$var wire 1 = d5b $end
+$var wire 1 > d5 $end
+$var wire 1 ? d4 $end
+$var wire 1 @ d3 $end
+$var wire 1 A d2b $end
+$var wire 1 B d2 $end
+$var wire 1 C d1b $end
+$var wire 1 D d1 $end
+$var wire 1 E comp_en $end
+$var reg 1 F clk $end
+$var reg 1 G comp_in $end
+$scope module mmm $end
+$var wire 1 F clk $end
+$var wire 1 G comp_in $end
+$var wire 1 ! d3b $end
+$var wire 1 ! d4b $end
+$var wire 1 H d6b $end
+$var wire 1 - sw0 $end
+$var wire 1 , sw0b $end
+$var wire 1 + sw1 $end
+$var wire 1 * sw1b $end
+$var wire 1 ) sw2 $end
+$var wire 1 ( sw2b $end
+$var wire 1 ' sw3 $end
+$var wire 1 & sw3b $end
+$var wire 1 % sw4 $end
+$var wire 1 $ sw4b $end
+$var wire 1 # sw5 $end
+$var wire 1 " sw5b $end
+$var wire 1 . sample $end
+$var wire 1 / rs $end
+$var wire 1 0 r5 $end
+$var wire 1 1 r4 $end
+$var wire 1 2 r3 $end
+$var wire 1 3 r2 $end
+$var wire 1 4 r1 $end
+$var wire 1 5 r0 $end
+$var wire 1 6 q5 $end
+$var wire 1 7 q4 $end
+$var wire 1 8 q3 $end
+$var wire 1 9 q2 $end
+$var wire 1 : q1 $end
+$var wire 1 ; q0 $end
+$var wire 1 < d6 $end
+$var wire 1 = d5b $end
+$var wire 1 > d5 $end
+$var wire 1 ? d4 $end
+$var wire 1 @ d3 $end
+$var wire 1 A d2b $end
+$var wire 1 B d2 $end
+$var wire 1 C d1b $end
+$var wire 1 D d1 $end
+$var wire 1 E comp_en $end
+$scope module ccc $end
+$var wire 1 F clk $end
+$var wire 1 C d1b $end
+$var wire 1 A d2b $end
+$var wire 1 ! d3b $end
+$var wire 1 ! d4b $end
+$var wire 1 = d5b $end
+$var wire 1 H d6b $end
+$var reg 1 E comp_en $end
+$var reg 1 D d1 $end
+$var reg 1 B d2 $end
+$var reg 1 @ d3 $end
+$var reg 1 ? d4 $end
+$var reg 1 > d5 $end
+$var reg 1 < d6 $end
+$var reg 1 / rs $end
+$var reg 1 . sample $end
+$var reg 5 I sar_counter [4:0] $end
+$upscope $end
+$scope module hhh $end
+$var wire 1 G comp_in $end
+$var wire 1 C d1b $end
+$var wire 1 A d2b $end
+$var wire 1 ! d3b $end
+$var wire 1 ! d4b $end
+$var wire 1 = d5b $end
+$var wire 1 H d6b $end
+$var wire 1 . sample $end
+$var wire 1 0 r5 $end
+$var wire 1 1 r4 $end
+$var wire 1 2 r3 $end
+$var wire 1 3 r2 $end
+$var wire 1 4 r1 $end
+$var wire 1 5 r0 $end
+$scope module dff0 $end
+$var wire 1 C clk $end
+$var wire 1 G d $end
+$var wire 1 J qn $end
+$var wire 1 . rst $end
+$var reg 1 5 q $end
+$upscope $end
+$scope module dff1 $end
+$var wire 1 A clk $end
+$var wire 1 G d $end
+$var wire 1 K qn $end
+$var wire 1 . rst $end
+$var reg 1 4 q $end
+$upscope $end
+$scope module dff2 $end
+$var wire 1 ! clk $end
+$var wire 1 G d $end
+$var wire 1 L qn $end
+$var wire 1 . rst $end
+$var reg 1 3 q $end
+$upscope $end
+$scope module dff3 $end
+$var wire 1 ! clk $end
+$var wire 1 G d $end
+$var wire 1 M qn $end
+$var wire 1 . rst $end
+$var reg 1 2 q $end
+$upscope $end
+$scope module dff4 $end
+$var wire 1 = clk $end
+$var wire 1 G d $end
+$var wire 1 N qn $end
+$var wire 1 . rst $end
+$var reg 1 1 q $end
+$upscope $end
+$scope module dff5 $end
+$var wire 1 H clk $end
+$var wire 1 G d $end
+$var wire 1 O qn $end
+$var wire 1 . rst $end
+$var reg 1 0 q $end
+$upscope $end
+$upscope $end
+$scope module qqq $end
+$var wire 1 5 r0 $end
+$var wire 1 P r0n $end
+$var wire 1 4 r1 $end
+$var wire 1 3 r2 $end
+$var wire 1 2 r3 $end
+$var wire 1 1 r4 $end
+$var wire 1 0 r5 $end
+$var wire 1 / rs $end
+$var wire 1 . sample $end
+$var wire 1 6 q5 $end
+$var wire 1 7 q4 $end
+$var wire 1 8 q3 $end
+$var wire 1 9 q2 $end
+$var wire 1 : q1 $end
+$var wire 1 ; q0 $end
+$scope module dff1 $end
+$var wire 1 / clk $end
+$var wire 1 P d $end
+$var wire 1 Q qn $end
+$var wire 1 . rst $end
+$var reg 1 ; q $end
+$upscope $end
+$scope module dff2 $end
+$var wire 1 / clk $end
+$var wire 1 4 d $end
+$var wire 1 R qn $end
+$var wire 1 . rst $end
+$var reg 1 : q $end
+$upscope $end
+$scope module dff3 $end
+$var wire 1 / clk $end
+$var wire 1 3 d $end
+$var wire 1 S qn $end
+$var wire 1 . rst $end
+$var reg 1 9 q $end
+$upscope $end
+$scope module dff4 $end
+$var wire 1 / clk $end
+$var wire 1 2 d $end
+$var wire 1 T qn $end
+$var wire 1 . rst $end
+$var reg 1 8 q $end
+$upscope $end
+$scope module dff5 $end
+$var wire 1 / clk $end
+$var wire 1 1 d $end
+$var wire 1 U qn $end
+$var wire 1 . rst $end
+$var reg 1 7 q $end
+$upscope $end
+$scope module dff6 $end
+$var wire 1 / clk $end
+$var wire 1 0 d $end
+$var wire 1 V qn $end
+$var wire 1 . rst $end
+$var reg 1 6 q $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+1V
+1U
+1T
+1S
+1R
+1Q
+zP
+1O
+0N
+0M
+0L
+0K
+0J
+b1000 I
+zH
+1G
+0F
+1E
+0D
+1C
+0B
+1A
+0@
+0?
+0>
+1=
+0<
+0;
+0:
+09
+08
+07
+06
+15
+14
+13
+12
+11
+00
+0/
+0.
+1-
+0,
+1+
+0*
+1)
+0(
+1'
+0&
+1%
+0$
+0#
+1"
+1!
+$end
+#10
+b111 I
+0G
+1F
+#20
+1G
+0F
+#30
+0"
+1#
+1<
+0E
+b110 I
+0G
+1F
+#40
+1G
+0F
+#50
+1"
+0#
+0=
+0<
+1>
+b101 I
+0G
+1F
+#60
+1G
+0F
+#70
+1$
+0%
+1N
+01
+1=
+x!
+0>
+1?
+b100 I
+0G
+1F
+#80
+1G
+0F
+#90
+1&
+0'
+1L
+1M
+03
+02
+x!
+0?
+1@
+b11 I
+0G
+1F
+#100
+1G
+0F
+#110
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diff --git a/xschem/analog_switch.sch b/xschem/analog_switch.sch
new file mode 100755
index 0000000..b48645a
--- /dev/null
+++ b/xschem/analog_switch.sch
@@ -0,0 +1,40 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 100 -220 330 -220 {
+lab=IN}
+N 400 -330 400 -280 {
+lab=#net1}
+N 470 -220 540 -220 {
+lab=OUT}
+N 360 -330 400 -330 {
+lab=#net1}
+N 100 -330 230 -330 {
+lab=control}
+N 400 -160 400 -80 {}
+N 180 -80 400 -80 {}
+N 180 -330 180 -80 {}
+C {ipin.sym} 110 -220 0 0 {name=p1 lab=IN}
+C {ipin.sym} 110 -330 0 0 {name=p2 lab=control}
+C {opin.sym} 530 -220 0 0 {name=p3 lab=OUT}
+C {transmission_gate.sym} 220 -100 0 0 {name=x1}
+C {not.sym} 380 -330 0 0 {name=x2}
diff --git a/xschem/analog_switch.spice b/xschem/analog_switch.spice
new file mode 100644
index 0000000..a64a310
--- /dev/null
+++ b/xschem/analog_switch.spice
@@ -0,0 +1,43 @@
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sch
+**.subckt analog_switch IN control OUT
+*.ipin IN
+*.ipin control
+*.opin OUT
+x1 control OUT IN net1 transmission_gate
+x2 control net1 not
+**.ends
+
+* expanding symbol: transmission_gate.sym # of pins=4
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sch
+.subckt transmission_gate GP OUT IN GN
+*.opin OUT
+*.ipin IN
+*.ipin GN
+*.ipin GP
+XM1 OUT GN IN GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 OUT GP IN VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: not.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sch
+.subckt not a y
+*.ipin a
+*.opin y
+XM1 y a GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 y a VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.GLOBAL VDD
+.end
diff --git a/xschem/analog_switch.sym b/xschem/analog_switch.sym
new file mode 100755
index 0000000..849f5a0
--- /dev/null
+++ b/xschem/analog_switch.sym
@@ -0,0 +1,24 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -20 -130 20 {}
+L 4 -60 -20 -60 20 {}
+L 4 -150 10 -130 10 {}
+L 4 -60 -10 -40 -10 {}
+L 4 -150 -10 -130 -10 {}
+L 4 -130 -20 -60 -20 {}
+L 4 -130 20 -60 20 {}
+B 5 -152.5 7.5 -147.5 12.5 {name=control dir=in }
+B 5 -42.5 -12.5 -37.5 -7.5 {name=OUT dir=out }
+B 5 -152.5 -12.5 -147.5 -7.5 {name=IN dir=in }
+T {@symname} -176.5 24 0 0 0.3 0.3 {}
+T {@name} -55 -32 0 0 0.2 0.2 {}
+T {control} -125 6 0 0 0.2 0.2 {}
+T {OUT} -65 -14 0 1 0.2 0.2 {}
+T {IN} -125 -14 0 0 0.2 0.2 {}
diff --git a/xschem/bsim4v5.out b/xschem/bsim4v5.out
index 95f5a25..eec78c7 100644
--- a/xschem/bsim4v5.out
+++ b/xschem/bsim4v5.out
@@ -2,4 +2,4 @@
Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++
-Model = x1.xm2:sky130_fd_pr__nfet_01v8_lvt__model.55
+Model = x1.x1.xm1:sky130_fd_pr__nfet_01v8_lvt__model.55
diff --git a/xschem/cap16.sch b/xschem/cap16.sch
new file mode 100755
index 0000000..cf6234c
--- /dev/null
+++ b/xschem/cap16.sch
@@ -0,0 +1,152 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -70 -170 -70 -140 {
+lab=out}
+N -70 -170 40 -170 {
+lab=out}
+N 40 -170 40 -140 {
+lab=out}
+N 40 -80 40 -50 {
+lab=in}
+N -70 -50 40 -50 {
+lab=in}
+N -70 -80 -70 -50 {
+lab=in}
+N 140 -170 140 -140 {
+lab=out}
+N 140 -170 250 -170 {
+lab=out}
+N 250 -170 250 -140 {
+lab=out}
+N 250 -80 250 -50 {
+lab=in}
+N 140 -50 250 -50 {
+lab=in}
+N 140 -80 140 -50 {
+lab=in}
+N 40 -170 140 -170 {
+lab=out}
+N 40 -50 140 -50 {
+lab=in}
+N 350 -170 350 -140 {
+lab=out}
+N 350 -170 460 -170 {
+lab=out}
+N 460 -170 460 -140 {
+lab=out}
+N 460 -80 460 -50 {
+lab=in}
+N 350 -50 460 -50 {
+lab=in}
+N 350 -80 350 -50 {
+lab=in}
+N 560 -170 560 -140 {
+lab=out}
+N 560 -170 670 -170 {
+lab=out}
+N 670 -170 670 -140 {
+lab=out}
+N 670 -80 670 -50 {
+lab=in}
+N 560 -50 670 -50 {
+lab=in}
+N 560 -80 560 -50 {
+lab=in}
+N 460 -170 560 -170 {
+lab=out}
+N 460 -50 560 -50 {
+lab=in}
+N 250 -50 350 -50 {
+lab=in}
+N 250 -170 350 -170 {
+lab=out}
+N 790 -170 790 -140 {
+lab=out}
+N 790 -170 900 -170 {
+lab=out}
+N 900 -170 900 -140 {
+lab=out}
+N 900 -80 900 -50 {
+lab=in}
+N 790 -50 900 -50 {
+lab=in}
+N 790 -80 790 -50 {
+lab=in}
+N 1000 -170 1000 -140 {
+lab=out}
+N 1000 -170 1110 -170 {
+lab=out}
+N 1110 -170 1110 -140 {
+lab=out}
+N 1110 -80 1110 -50 {
+lab=in}
+N 1000 -50 1110 -50 {
+lab=in}
+N 1000 -80 1000 -50 {
+lab=in}
+N 900 -170 1000 -170 {
+lab=out}
+N 900 -50 1000 -50 {
+lab=in}
+N 1210 -170 1210 -140 {
+lab=out}
+N 1210 -170 1320 -170 {
+lab=out}
+N 1320 -170 1320 -140 {
+lab=out}
+N 1320 -80 1320 -50 {
+lab=in}
+N 1210 -50 1320 -50 {
+lab=in}
+N 1210 -80 1210 -50 {
+lab=in}
+N 1420 -170 1420 -140 {
+lab=out}
+N 1420 -170 1530 -170 {
+lab=out}
+N 1530 -170 1530 -140 {
+lab=out}
+N 1530 -80 1530 -50 {
+lab=in}
+N 1420 -50 1530 -50 {
+lab=in}
+N 1420 -80 1420 -50 {
+lab=in}
+N 1320 -170 1420 -170 {
+lab=out}
+N 1320 -50 1420 -50 {
+lab=in}
+N 1110 -50 1210 -50 {
+lab=in}
+N 1110 -170 1210 -170 {
+lab=out}
+N 670 -170 790 -170 {
+lab=out}
+N 670 -50 790 -50 {
+lab=in}
+N 730 -50 730 -10 {
+lab=in}
+N 730 -210 730 -170 {
+lab=out}
+C {ipin.sym} 730 -20 3 0 {name=p5 lab=in}
+C {opin.sym} 730 -200 3 0 {name=p6 lab=out}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -70 -110 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 40 -110 0 0 {name=C2 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 140 -110 0 0 {name=C3 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 250 -110 0 0 {name=C4 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 350 -110 0 0 {name=C5 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 460 -110 0 0 {name=C6 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 560 -110 0 0 {name=C7 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 670 -110 0 0 {name=C8 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 790 -110 0 0 {name=C9 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 900 -110 0 0 {name=C10 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1000 -110 0 0 {name=C11 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1110 -110 0 0 {name=C12 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1210 -110 0 0 {name=C13 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1320 -110 0 0 {name=C14 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1420 -110 0 0 {name=C15 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1530 -110 0 0 {name=C16 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
diff --git a/xschem/cap16.sym b/xschem/cap16.sym
new file mode 100755
index 0000000..ff5ba42
--- /dev/null
+++ b/xschem/cap16.sym
@@ -0,0 +1,18 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -40.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}
+B 5 147.5 -2.5 152.5 2.5 {name=out dir=out }
+L 4 130 0 150 0 {}
+T {out} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=in dir=in }
+L 4 -150 0 -130 0 {}
+T {in} -125 -4 0 0 0.2 0.2 {}
diff --git a/xschem/cap2.sch b/xschem/cap2.sch
new file mode 100755
index 0000000..a147e53
--- /dev/null
+++ b/xschem/cap2.sch
@@ -0,0 +1,26 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 90 -140 90 -110 {
+lab=out}
+N 90 -140 200 -140 {
+lab=out}
+N 200 -140 200 -110 {
+lab=out}
+N 200 -50 200 -20 {
+lab=in}
+N 90 -20 200 -20 {
+lab=in}
+N 90 -50 90 -20 {
+lab=in}
+N 140 -20 140 20 {
+lab=in}
+N 140 -180 140 -140 {
+lab=out}
+C {ipin.sym} 140 10 3 0 {name=p1 lab=in}
+C {opin.sym} 140 -170 3 0 {name=p2 lab=out}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 90 -80 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 200 -80 0 0 {name=C2 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
diff --git a/xschem/cap2.sym b/xschem/cap2.sym
new file mode 100755
index 0000000..09f7e4e
--- /dev/null
+++ b/xschem/cap2.sym
@@ -0,0 +1,17 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -36 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}
+B 5 147.5 -2.5 152.5 2.5 {name=out dir=out }
+L 4 130 0 150 0 {}
+T {out} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=in dir=in }
+L 4 -150 0 -130 0 {}
+T {in} -125 -4 0 0 0.2 0.2 {}
diff --git a/xschem/cap32.sch b/xschem/cap32.sch
new file mode 100755
index 0000000..c5e90c8
--- /dev/null
+++ b/xschem/cap32.sch
@@ -0,0 +1,296 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
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+lab=out}
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+N 40 -90 40 -60 {
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+N 140 -90 250 -90 {
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+lab=out}
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+lab=out}
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+lab=in}
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+lab=in}
+N 2190 -90 2290 -90 {
+lab=out}
+N 2190 30 2290 30 {
+lab=in}
+N 2500 -90 2500 -60 {
+lab=out}
+N 2500 -90 2610 -90 {
+lab=out}
+N 2610 -90 2610 -60 {
+lab=out}
+N 2610 0 2610 30 {
+lab=in}
+N 2500 30 2610 30 {
+lab=in}
+N 2500 0 2500 30 {
+lab=in}
+N 2710 -90 2710 -60 {
+lab=out}
+N 2710 -90 2820 -90 {
+lab=out}
+N 2820 -90 2820 -60 {
+lab=out}
+N 2820 0 2820 30 {
+lab=in}
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+lab=in}
+N 2710 0 2710 30 {
+lab=in}
+N 2610 -90 2710 -90 {
+lab=out}
+N 2610 30 2710 30 {
+lab=in}
+N 2400 30 2500 30 {
+lab=in}
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+lab=out}
+N 1960 -90 2080 -90 {
+lab=out}
+N 1960 30 2080 30 {
+lab=in}
+N 1110 -90 1220 -90 {
+lab=out}
+N 1110 30 1220 30 {
+lab=in}
+C {ipin.sym} 1380 60 3 0 {name=p5 lab=in}
+C {opin.sym} 1380 -120 3 0 {name=p6 lab=out}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -490 -30 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -380 -30 0 0 {name=C2 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -280 -30 0 0 {name=C3 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -170 -30 0 0 {name=C4 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -70 -30 0 0 {name=C5 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 40 -30 0 0 {name=C6 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 140 -30 0 0 {name=C7 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 250 -30 0 0 {name=C8 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 370 -30 0 0 {name=C9 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 480 -30 0 0 {name=C10 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 580 -30 0 0 {name=C11 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 690 -30 0 0 {name=C12 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 790 -30 0 0 {name=C13 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 900 -30 0 0 {name=C14 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1000 -30 0 0 {name=C15 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1110 -30 0 0 {name=C16 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1220 -30 0 0 {name=C17 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1330 -30 0 0 {name=C18 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1430 -30 0 0 {name=C19 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1540 -30 0 0 {name=C20 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1640 -30 0 0 {name=C21 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1750 -30 0 0 {name=C22 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1850 -30 0 0 {name=C23 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1960 -30 0 0 {name=C24 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2080 -30 0 0 {name=C25 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2190 -30 0 0 {name=C26 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2290 -30 0 0 {name=C27 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2400 -30 0 0 {name=C28 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2500 -30 0 0 {name=C29 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2610 -30 0 0 {name=C30 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2710 -30 0 0 {name=C31 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 2820 -30 0 0 {name=C32 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
diff --git a/xschem/cap32.sym b/xschem/cap32.sym
new file mode 100755
index 0000000..ff5ba42
--- /dev/null
+++ b/xschem/cap32.sym
@@ -0,0 +1,18 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -40.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}
+B 5 147.5 -2.5 152.5 2.5 {name=out dir=out }
+L 4 130 0 150 0 {}
+T {out} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=in dir=in }
+L 4 -150 0 -130 0 {}
+T {in} -125 -4 0 0 0.2 0.2 {}
diff --git a/xschem/cap4.sch b/xschem/cap4.sch
new file mode 100755
index 0000000..d0b7b77
--- /dev/null
+++ b/xschem/cap4.sch
@@ -0,0 +1,42 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 130 -140 130 -110 {
+lab=out}
+N 130 -140 240 -140 {
+lab=out}
+N 240 -140 240 -110 {
+lab=out}
+N 240 -50 240 -20 {
+lab=in}
+N 130 -20 240 -20 {
+lab=in}
+N 130 -50 130 -20 {
+lab=in}
+N 290 -20 290 20 {
+lab=in}
+N 290 -180 290 -140 {
+lab=out}
+N 340 -140 340 -110 {
+lab=out}
+N 340 -140 450 -140 {
+lab=out}
+N 450 -140 450 -110 {
+lab=out}
+N 450 -50 450 -20 {
+lab=in}
+N 340 -20 450 -20 {
+lab=in}
+N 340 -50 340 -20 {
+lab=in}
+N 240 -140 340 -140 {}
+N 240 -20 340 -20 {}
+C {ipin.sym} 290 10 3 0 {name=p1 lab=in}
+C {opin.sym} 290 -170 3 0 {name=p2 lab=out}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 130 -80 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 240 -80 0 0 {name=C2 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 340 -80 0 0 {name=C3 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 450 -80 0 0 {name=C4 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
diff --git a/xschem/cap4.sym b/xschem/cap4.sym
new file mode 100755
index 0000000..09f7e4e
--- /dev/null
+++ b/xschem/cap4.sym
@@ -0,0 +1,17 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -36 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}
+B 5 147.5 -2.5 152.5 2.5 {name=out dir=out }
+L 4 130 0 150 0 {}
+T {out} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=in dir=in }
+L 4 -150 0 -130 0 {}
+T {in} -125 -4 0 0 0.2 0.2 {}
diff --git a/xschem/cap8.sch b/xschem/cap8.sch
new file mode 100755
index 0000000..2b28d9c
--- /dev/null
+++ b/xschem/cap8.sch
@@ -0,0 +1,74 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -310 -140 -310 -110 {
+lab=out}
+N -310 -140 -200 -140 {
+lab=out}
+N -200 -140 -200 -110 {
+lab=out}
+N -200 -50 -200 -20 {
+lab=in}
+N -310 -20 -200 -20 {
+lab=in}
+N -310 -50 -310 -20 {
+lab=in}
+N -100 -140 -100 -110 {
+lab=out}
+N -100 -140 10 -140 {
+lab=out}
+N 10 -140 10 -110 {
+lab=out}
+N 10 -50 10 -20 {
+lab=in}
+N -100 -20 10 -20 {
+lab=in}
+N -100 -50 -100 -20 {
+lab=in}
+N -200 -140 -100 -140 {}
+N -200 -20 -100 -20 {}
+N 110 -140 110 -110 {
+lab=out}
+N 110 -140 220 -140 {
+lab=out}
+N 220 -140 220 -110 {
+lab=out}
+N 220 -50 220 -20 {
+lab=in}
+N 110 -20 220 -20 {
+lab=in}
+N 110 -50 110 -20 {
+lab=in}
+N 60 -20 60 20 {
+lab=in}
+N 60 -180 60 -140 {
+lab=out}
+N 320 -140 320 -110 {
+lab=out}
+N 320 -140 430 -140 {
+lab=out}
+N 430 -140 430 -110 {
+lab=out}
+N 430 -50 430 -20 {
+lab=in}
+N 320 -20 430 -20 {
+lab=in}
+N 320 -50 320 -20 {
+lab=in}
+N 220 -140 320 -140 {}
+N 220 -20 320 -20 {}
+N 10 -20 110 -20 {}
+N 10 -140 110 -140 {}
+C {ipin.sym} 60 10 3 0 {name=p3 lab=in}
+C {opin.sym} 60 -170 3 0 {name=p4 lab=out}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -310 -80 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -200 -80 0 0 {name=C2 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} -100 -80 0 0 {name=C3 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 10 -80 0 0 {name=C4 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 110 -80 0 0 {name=C5 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 220 -80 0 0 {name=C6 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 320 -80 0 0 {name=C7 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 430 -80 0 0 {name=C8 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
diff --git a/xschem/cap8.sym b/xschem/cap8.sym
new file mode 100755
index 0000000..09f7e4e
--- /dev/null
+++ b/xschem/cap8.sym
@@ -0,0 +1,17 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -36 -6 0 0 0.3 0.3 {}
+T {@name} 135 -22 0 0 0.2 0.2 {}
+L 4 -130 -10 130 -10 {}
+L 4 -130 10 130 10 {}
+L 4 -130 -10 -130 10 {}
+L 4 130 -10 130 10 {}
+B 5 147.5 -2.5 152.5 2.5 {name=out dir=out }
+L 4 130 0 150 0 {}
+T {out} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=in dir=in }
+L 4 -150 0 -130 0 {}
+T {in} -125 -4 0 0 0.2 0.2 {}
diff --git a/xschem/dacpassgate.sch b/xschem/dacpassgate.sch
new file mode 100755
index 0000000..dc4dd87
--- /dev/null
+++ b/xschem/dacpassgate.sch
@@ -0,0 +1,88 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 210 -470 230 -470 { lab=A}
+N 210 -340 210 -200 { lab=A}
+N 210 -200 230 -200 { lab=A}
+N 290 -200 310 -200 { lab=Z}
+N 290 -470 310 -470 { lab=Z}
+N 150 -340 210 -340 { lab=A}
+N 260 -550 260 -510 { lab=GP}
+N 220 -550 260 -550 { lab=GP}
+N 260 -160 260 -120 { lab=GN}
+N 220 -120 260 -120 { lab=GN}
+N 210 -470 210 -340 { lab=A}
+N 350 -240 350 -200 { lab=Z}
+N 310 -200 350 -200 { lab=Z}
+N 350 -340 350 -300 { lab=Z}
+N 350 -380 350 -340 { lab=Z}
+N 350 -470 350 -440 { lab=Z}
+N 310 -470 350 -470 { lab=Z}
+N 350 -440 350 -380 {
+lab=Z}
+N 350 -300 350 -240 {
+lab=Z}
+N 350 -340 380 -340 {
+lab=Z}
+N 260 -230 260 -200 {
+lab=GND}
+N 260 -230 320 -230 {
+lab=GND}
+N 320 -230 320 -150 {
+lab=GND}
+N 330 -520 330 -440 {}
+N 260 -440 330 -440 {}
+N 260 -470 260 -440 {}
+C {symbols//iopin.sym} 150 -340 0 1 {name=p1 lab=A}
+C {symbols//iopin.sym} 370 -340 0 0 {name=p2 lab=Z}
+C {symbols/ipin.sym} 220 -550 0 0 {name=p3 lab=GP}
+C {symbols/ipin.sym} 220 -120 0 0 {name=p4 lab=GN}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 260 -490 3 1 {name=M2
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 260 -180 1 1 {name=M1
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {gnd.sym} 320 -150 0 0 {name=l2 lab=GND}
+C {vdd.sym} 330 -520 0 0 {name=l1 lab=VDD}
diff --git a/xschem/df4.sch b/xschem/df4.sch
new file mode 100644
index 0000000..b00484c
--- /dev/null
+++ b/xschem/df4.sch
@@ -0,0 +1,31 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 440 -300 490 -300 {
+lab=CLK}
+N 370 -260 420 -260 {
+lab=#net1}
+N 440 -280 490 -280 {
+lab=D}
+N 270 -260 290 -260 {
+lab=RESET}
+N 420 -260 490 -260 {
+lab=#net1}
+N 680 -300 720 -300 {
+lab=Q}
+N 670 -300 680 -300 {
+lab=Q}
+N 680 -280 720 -280 {
+lab=Q_N}
+N 670 -280 680 -280 {
+lab=Q_N}
+C {xschem_sky130/sky130_stdcells/inv_1.sym} 330 -260 0 0 {name=x2 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {ipin.sym} 440 -300 0 0 {name=p5 lab=CLK}
+C {ipin.sym} 440 -280 0 0 {name=p6 lab=D}
+C {ipin.sym} 270 -260 0 0 {name=p7 lab=RESET}
+C {opin.sym} 720 -300 0 0 {name=p8 lab=Q}
+C {opin.sym} 720 -280 0 0 {name=p9 lab=Q_N}
+C {xschem_sky130/sky130_stdcells/dfrbp_1.sym} 580 -280 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
diff --git a/xschem/df4.sym b/xschem/df4.sym
new file mode 100644
index 0000000..e1ec886
--- /dev/null
+++ b/xschem/df4.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -100 -190 -100 -130 {}
+L 4 40 -190 40 -130 {}
+L 4 -120 -140 -100 -140 {}
+L 4 40 -180 60 -180 {}
+L 4 -120 -180 -100 -180 {}
+L 4 40 -140 60 -140 {}
+L 4 -30 -130 -30 -110 {}
+L 4 -100 -190 40 -190 {}
+L 4 -100 -130 40 -130 {}
+B 5 -122.5 -142.5 -117.5 -137.5 {name=CLK dir=in }
+B 5 57.5 -182.5 62.5 -177.5 {name=Q dir=out }
+B 5 -122.5 -182.5 -117.5 -177.5 {name=D dir=in }
+B 5 57.5 -142.5 62.5 -137.5 {name=Q_N dir=out }
+B 5 -32.5 -112.5 -27.5 -107.5 {name=RESET dir=in }
+T {@symname} -15 -126 0 0 0.3 0.3 {}
+T {@name} 45 -202 0 0 0.2 0.2 {}
+T {CLK} -95 -144 0 0 0.2 0.2 {}
+T {Q} 35 -184 0 1 0.2 0.2 {}
+T {D} -95 -184 0 0 0.2 0.2 {}
+T {Q_N} 35 -144 0 1 0.2 0.2 {}
+T {RESET} -44 -145 0 0 0.2 0.2 {}
diff --git a/xschem/my_cdac.sch b/xschem/my_cdac.sch
new file mode 100755
index 0000000..f442323
--- /dev/null
+++ b/xschem/my_cdac.sch
@@ -0,0 +1,226 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 340 -90 440 -90 {
+lab=C6V}
+N 390 -130 390 -110 {
+lab=C6V}
+N 540 -90 640 -90 {
+lab=C5V}
+N 590 -130 590 -110 {
+lab=C5V}
+N 740 -90 840 -90 {
+lab=C4V}
+N 790 -130 790 -110 {
+lab=C4V}
+N 940 -90 1040 -90 {
+lab=C3V}
+N 990 -130 990 -110 {
+lab=C3V}
+N 1140 -90 1240 -90 {
+lab=C2V}
+N 1190 -130 1190 -110 {
+lab=C2V}
+N 1340 -90 1440 -90 {
+lab=C1V}
+N 1390 -130 1390 -110 {
+lab=C1V}
+N 1340 20 1340 120 {
+lab=VCM}
+N 1140 20 1140 120 {
+lab=VCM}
+N 940 20 940 120 {
+lab=VCM}
+N 50 120 1340 120 {
+lab=VCM}
+N 740 20 740 120 {
+lab=VCM}
+N 540 20 540 120 {
+lab=VCM}
+N 340 20 340 120 {
+lab=VCM}
+N 140 20 140 120 {
+lab=VCM}
+N 1440 20 1440 200 {
+lab=CDACin}
+N 50 200 1440 200 {
+lab=CDACin}
+N 240 20 240 200 {
+lab=CDACin}
+N 440 20 440 200 {
+lab=CDACin}
+N 640 20 640 190 {
+lab=CDACin}
+N 640 190 640 200 {
+lab=CDACin}
+N 840 20 840 200 {
+lab=CDACin}
+N 1040 20 1040 200 {
+lab=CDACin}
+N 1240 20 1240 200 {
+lab=CDACin}
+N 360 20 360 60 {
+lab=SW0B}
+N 420 20 420 60 {
+lab=SW0}
+N 560 20 560 60 {
+lab=SW1B}
+N 620 20 620 60 {
+lab=SW1}
+N 760 20 760 60 {
+lab=SW2B}
+N 820 20 820 60 {
+lab=SW2}
+N 960 20 960 60 {
+lab=SW3B}
+N 1020 20 1020 60 {
+lab=SW3}
+N 1160 20 1160 60 {
+lab=SW4B}
+N 1220 20 1220 60 {
+lab=SW4}
+N 1360 20 1360 60 {
+lab=SW5B}
+N 1420 20 1420 60 {
+lab=SW5}
+N 1390 -480 1390 -430 {
+lab=Vref}
+N 1190 -480 1190 -430 {
+lab=Vref}
+N 990 -480 990 -430 {
+lab=Vref}
+N 790 -480 790 -430 {
+lab=Vref}
+N 590 -480 590 -430 {
+lab=Vref}
+N 190 -480 190 -190 {
+lab=Vref}
+N 190 -480 1540 -480 {
+lab=Vref}
+N 390 -480 390 -190 {
+lab=Vref}
+N 140 -90 240 -90 {
+lab=C7V}
+N 190 -130 190 -90 {
+lab=C7V}
+N 1540 -480 1650 -480 {
+lab=Vref}
+N 1590 -480 1590 -440 {
+lab=Vref}
+N 1590 -330 1590 -290 {
+lab=GND}
+N 1570 -330 1570 -270 {
+lab=Sample}
+N 220 20 220 240 {
+lab=Sample}
+N 1570 -270 1570 240 {
+lab=Sample}
+N 390 -110 390 -90 {
+lab=C6V}
+N 590 -110 590 -90 {
+lab=C5V}
+N 790 -110 790 -90 {
+lab=C4V}
+N 990 -110 990 -90 {
+lab=C3V}
+N 1190 -110 1190 -90 {
+lab=C2V}
+N 1390 -110 1390 -90 {
+lab=C1V}
+N -80 200 -80 260 {
+lab=CDACin}
+N -80 200 50 200 {
+lab=CDACin}
+N 40 200 40 260 {
+lab=CDACin}
+N 40 370 40 390 {
+lab=#net1}
+N 40 450 40 470 {
+lab=GND}
+N 20 370 20 510 {
+lab=COMP_ENB}
+N 20 510 160 510 {
+lab=COMP_ENB}
+N 220 240 1570 240 {
+lab=Sample}
+N -60 370 -60 560 {
+lab=Sample}
+N -60 540 220 540 {
+lab=Sample}
+N 220 240 220 540 {
+lab=Sample}
+N 160 20 160 580 {
+lab=COMP_ENB}
+N -80 370 -80 440 {
+lab=VIN}
+C {analog_switch.sym} 150 -130 3 0 {name=xproblem}
+C {analog_switch.sym} 230 -130 1 1 {name=x2}
+C {analog_switch.sym} 350 -130 3 0 {name=x3}
+C {analog_switch.sym} 430 -130 1 1 {name=x4}
+C {analog_switch.sym} 550 -130 3 0 {name=x5}
+C {analog_switch.sym} 630 -130 1 1 {name=x6}
+C {analog_switch.sym} 750 -130 3 0 {name=x7}
+C {analog_switch.sym} 830 -130 1 1 {name=x8}
+C {analog_switch.sym} 950 -130 3 0 {name=x9}
+C {analog_switch.sym} 1030 -130 1 1 {name=x10}
+C {analog_switch.sym} 1150 -130 3 0 {name=x11}
+C {analog_switch.sym} 1230 -130 1 1 {name=x12}
+C {analog_switch.sym} 1350 -130 3 0 {name=x13}
+C {analog_switch.sym} 1430 -130 1 1 {name=x14}
+C {ipin.sym} 60 120 0 0 {name=p1 lab=VCM}
+C {ipin.sym} -80 430 3 0 {name=p2 lab=VIN}
+C {cap2.sym} 590 -280 3 0 {name=x15}
+C {cap4.sym} 790 -280 3 0 {name=x16}
+C {cap8.sym} 990 -280 3 0 {name=x17}
+C {cap16.sym} 1190 -280 3 0 {name=x18}
+C {cap32.sym} 1390 -280 3 0 {name=x19}
+C {ipin.sym} 160 570 3 0 {name=p4 lab=COMP_ENB}
+C {ipin.sym} -60 550 3 0 {name=p5 lab=Sample}
+C {ipin.sym} 420 50 3 0 {name=p6 lab=SW0}
+C {ipin.sym} 360 50 3 0 {name=p7 lab=SW0B}
+C {ipin.sym} 620 50 3 0 {name=p8 lab=SW1}
+C {ipin.sym} 560 50 3 0 {name=p9 lab=SW1B}
+C {ipin.sym} 820 50 3 0 {name=p10 lab=SW2}
+C {ipin.sym} 760 50 3 0 {name=p11 lab=SW2B}
+C {ipin.sym} 1020 50 3 0 {name=p12 lab=SW3}
+C {ipin.sym} 960 50 3 0 {name=p13 lab=SW3B}
+C {ipin.sym} 1220 50 3 0 {name=p14 lab=SW4}
+C {ipin.sym} 1160 50 3 0 {name=p15 lab=SW4B}
+C {ipin.sym} 1420 50 3 0 {name=p16 lab=SW5}
+C {ipin.sym} 1360 50 3 0 {name=p17 lab=SW5B}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 190 -160 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 390 -160 0 0 {name=C2 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {opin.sym} 1650 -480 0 0 {name=p18 lab=Vref}
+C {analog_switch.sym} 1580 -480 1 1 {name=x1}
+C {analog_switch.sym} 30 220 1 1 {name=x20}
+C {analog_switch.sym} -70 220 3 0 {name=x21}
+C {vsource.sym} 40 420 0 0 {name=V1 value=0}
+C {gnd.sym} 40 470 0 0 {name=l2 lab=GND}
+C {gnd.sym} 1590 -290 0 0 {name=l1 lab=GND}
+C {lab_wire.sym} 110 200 0 0 {name=l3 sig_type=std_logic lab=CDACin}
+C {lab_wire.sym} 210 -90 0 1 {name=l4 sig_type=std_logic lab=C7V}
+C {lab_wire.sym} 400 -90 0 1 {name=l5 sig_type=std_logic lab=C6V}
+C {lab_wire.sym} 600 -90 0 1 {name=l6 sig_type=std_logic lab=C5V}
+C {lab_wire.sym} 800 -90 0 1 {name=l7 sig_type=std_logic lab=C4V}
+C {lab_wire.sym} 1000 -90 0 1 {name=l8 sig_type=std_logic lab=C3V}
+C {lab_wire.sym} 1210 -90 0 1 {name=l9 sig_type=std_logic lab=C2V}
+C {lab_wire.sym} 1400 -90 0 1 {name=l10 sig_type=std_logic lab=C1V}
diff --git a/xschem/my_cdac.spice b/xschem/my_cdac.spice
new file mode 100644
index 0000000..c3ce2cb
--- /dev/null
+++ b/xschem/my_cdac.spice
@@ -0,0 +1,199 @@
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_cdac.sch
+**.subckt my_cdac VCM VIN COMP_ENB Sample SW0 SW0B SW1 SW1B SW2 SW2B SW3 SW3B SW4 SW4B SW5 SW5B Vref
+*.ipin VCM
+*.ipin VIN
+*.ipin COMP_ENB
+*.ipin Sample
+*.ipin SW0
+*.ipin SW0B
+*.ipin SW1
+*.ipin SW1B
+*.ipin SW2
+*.ipin SW2B
+*.ipin SW3
+*.ipin SW3B
+*.ipin SW4
+*.ipin SW4B
+*.ipin SW5
+*.ipin SW5B
+*.opin Vref
+xproblem COMP_ENB C7V VCM analog_switch
+x2 Sample C7V CDACin analog_switch
+x3 SW0B C6V VCM analog_switch
+x4 SW0 C6V CDACin analog_switch
+x5 SW1B C5V VCM analog_switch
+x6 SW1 C5V CDACin analog_switch
+x7 SW2B C4V VCM analog_switch
+x8 SW2 C4V CDACin analog_switch
+x9 SW3B C3V VCM analog_switch
+x10 SW3 C3V CDACin analog_switch
+x11 SW4B C2V VCM analog_switch
+x12 SW4 C2V CDACin analog_switch
+x13 SW5B C1V VCM analog_switch
+x14 SW5 C1V CDACin analog_switch
+x15 Vref C5V cap2
+x16 Vref C4V cap4
+x17 Vref C3V cap8
+x18 Vref C2V cap16
+x19 Vref C1V cap32
+XC1 Vref C7V sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 Vref C6V sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+x1 Sample Vref GND analog_switch
+x20 COMP_ENB CDACin net1 analog_switch
+x21 Sample CDACin VIN analog_switch
+V1 net1 GND 0
+**.ends
+
+* expanding symbol: analog_switch.sym # of pins=3
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sch
+.subckt analog_switch control OUT IN
+*.ipin IN
+*.ipin control
+*.opin OUT
+x1 net1 OUT IN control transmission_gate
+x2 control net1 not
+.ends
+
+
+* expanding symbol: cap2.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap2.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap2.sch
+.subckt cap2 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap4.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap4.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap4.sch
+.subckt cap4 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap8.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap8.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap8.sch
+.subckt cap8 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC5 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC6 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC7 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC8 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap16.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap16.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap16.sch
+.subckt cap16 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC5 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC6 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC7 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC8 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC9 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC10 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC11 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC12 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC13 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC14 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC15 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC16 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap32.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap32.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap32.sch
+.subckt cap32 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC5 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC6 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC7 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC8 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC9 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC10 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC11 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC12 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC13 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC14 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC15 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC16 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC17 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC18 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC19 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC20 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC21 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC22 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC23 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC24 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC25 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC26 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC27 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC28 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC29 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC30 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC31 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC32 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: transmission_gate.sym # of pins=4
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sch
+.subckt transmission_gate GP OUT IN GN
+*.opin OUT
+*.ipin IN
+*.ipin GN
+*.ipin GP
+XM1 OUT GN IN GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 OUT GP IN VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: not.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sch
+.subckt not a y
+*.ipin a
+*.opin y
+XM1 y a GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 y a VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.GLOBAL VDD
+.end
diff --git a/xschem/my_cdac.sym b/xschem/my_cdac.sym
new file mode 100755
index 0000000..fadb5e7
--- /dev/null
+++ b/xschem/my_cdac.sym
@@ -0,0 +1,64 @@
+v {xschem version=3.0.0 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -49.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -172 0 0 0.2 0.2 {}
+L 4 -130 -160 130 -160 {}
+L 4 -130 160 130 160 {}
+L 4 -130 -160 -130 160 {}
+L 4 130 -160 130 160 {}
+B 5 147.5 -152.5 152.5 -147.5 {name=Vref dir=out }
+L 4 130 -150 150 -150 {}
+T {Vref} 125 -154 0 1 0.2 0.2 {}
+B 5 -152.5 -152.5 -147.5 -147.5 {name=SW0 dir=in }
+L 4 -150 -150 -130 -150 {}
+T {SW0} -125 -154 0 0 0.2 0.2 {}
+B 5 -152.5 -132.5 -147.5 -127.5 {name=SW1 dir=in }
+L 4 -150 -130 -130 -130 {}
+T {SW1} -125 -134 0 0 0.2 0.2 {}
+B 5 -152.5 -112.5 -147.5 -107.5 {name=Sample dir=in }
+L 4 -150 -110 -130 -110 {}
+T {Sample} -125 -114 0 0 0.2 0.2 {}
+B 5 -152.5 -92.5 -147.5 -87.5 {name=SW3 dir=in }
+L 4 -150 -90 -130 -90 {}
+T {SW3} -125 -94 0 0 0.2 0.2 {}
+B 5 -152.5 -72.5 -147.5 -67.5 {name=SW0B dir=in }
+L 4 -150 -70 -130 -70 {}
+T {SW0B} -125 -74 0 0 0.2 0.2 {}
+B 5 -152.5 -52.5 -147.5 -47.5 {name=COMP_ENB dir=in }
+L 4 -150 -50 -130 -50 {}
+T {COMP_ENB} -125 -54 0 0 0.2 0.2 {}
+B 5 -152.5 -32.5 -147.5 -27.5 {name=SW1B dir=in }
+L 4 -150 -30 -130 -30 {}
+T {SW1B} -125 -34 0 0 0.2 0.2 {}
+B 5 -152.5 -12.5 -147.5 -7.5 {name=SW2 dir=in }
+L 4 -150 -10 -130 -10 {}
+T {SW2} -125 -14 0 0 0.2 0.2 {}
+B 5 -152.5 7.5 -147.5 12.5 {name=SW2B dir=in }
+L 4 -150 10 -130 10 {}
+T {SW2B} -125 6 0 0 0.2 0.2 {}
+B 5 -152.5 27.5 -147.5 32.5 {name=SW5B dir=in }
+L 4 -150 30 -130 30 {}
+T {SW5B} -125 26 0 0 0.2 0.2 {}
+B 5 -152.5 47.5 -147.5 52.5 {name=SW3B dir=in }
+L 4 -150 50 -130 50 {}
+T {SW3B} -125 46 0 0 0.2 0.2 {}
+B 5 -152.5 67.5 -147.5 72.5 {name=SW4 dir=in }
+L 4 -150 70 -130 70 {}
+T {SW4} -125 66 0 0 0.2 0.2 {}
+B 5 -152.5 87.5 -147.5 92.5 {name=SW4B dir=in }
+L 4 -150 90 -130 90 {}
+T {SW4B} -125 86 0 0 0.2 0.2 {}
+B 5 -152.5 107.5 -147.5 112.5 {name=SW5 dir=in }
+L 4 -150 110 -130 110 {}
+T {SW5} -125 106 0 0 0.2 0.2 {}
+B 5 -152.5 127.5 -147.5 132.5 {name=VCM dir=in }
+L 4 -150 130 -130 130 {}
+T {VCM} -125 126 0 0 0.2 0.2 {}
+B 5 -152.5 147.5 -147.5 152.5 {name=VIN dir=in }
+L 4 -150 150 -130 150 {}
+T {VIN} -125 146 0 0 0.2 0.2 {}
diff --git a/xschem/my_comparator.sym b/xschem/my_comparator.sym
index a9a8213..862126f 100644
--- a/xschem/my_comparator.sym
+++ b/xschem/my_comparator.sym
@@ -7,27 +7,27 @@
V {}
S {}
E {}
-L 4 -130 -40 -130 40 {}
-L 4 -90 -60 -90 -40 {}
-L 4 -20 -10 0 -10 {}
-L 4 -20 10 0 10 {}
-L 4 -150 -10 -130 -10 {}
-L 4 -150 10 -130 10 {}
-L 4 -60 -60 -60 -40 {}
-L 4 -130 -40 -20 -40 {}
-L 4 -20 -40 -20 40 {}
-L 4 -130 40 -20 40 {}
-B 5 -92.5 -62.5 -87.5 -57.5 {name=CLK dir=in }
-B 5 -2.5 -12.5 2.5 -7.5 {name=VOUTP dir=out }
-B 5 -2.5 7.5 2.5 12.5 {name=VOUTN dir=out }
-B 5 -152.5 -12.5 -147.5 -7.5 {name=VINP dir=in }
-B 5 -152.5 7.5 -147.5 12.5 {name=VINN dir=in }
-B 5 -62.5 -62.5 -57.5 -57.5 {name=VDD dir=in }
-T {@symname} -126.5 44 0 0 0.3 0.3 {}
-T {@name} -15 -32 0 0 0.2 0.2 {}
-T {CLK} -86 -35 1 0 0.2 0.2 {}
-T {VOUTP} -25 -14 0 1 0.2 0.2 {}
-T {VOUTN} -25 6 0 1 0.2 0.2 {}
-T {VINP} -125 -14 0 0 0.2 0.2 {}
-T {VINN} -125 6 0 0 0.2 0.2 {}
-T {VDD} -56 -35 1 0 0.2 0.2 {}
+L 4 190 -250 190 -230 {}
+L 4 50 -230 310 -230 {}
+L 4 50 -130 310 -130 {}
+L 4 50 -230 50 -130 {}
+L 4 310 -230 310 -130 {}
+L 4 310 -200 330 -200 {}
+L 4 310 -160 330 -160 {}
+L 4 30 -210 50 -210 {}
+L 4 30 -180 50 -180 {}
+L 4 30 -150 50 -150 {}
+B 5 187.5 -252.5 192.5 -247.5 {name=VDD dir=in }
+B 5 327.5 -202.5 332.5 -197.5 {name=VOUTP dir=out }
+B 5 327.5 -162.5 332.5 -157.5 {name=VOUTN dir=out }
+B 5 27.5 -212.5 32.5 -207.5 {name=VINP dir=in }
+B 5 27.5 -182.5 32.5 -177.5 {name=VINN dir=in }
+B 5 27.5 -152.5 32.5 -147.5 {name=CLK dir=in }
+T {VDD} 194 -225 1 0 0.2 0.2 {}
+T {@symname} 94.5 -186 0 0 0.3 0.3 {}
+T {@name} 315 -242 0 0 0.2 0.2 {}
+T {VOUTP} 305 -204 0 1 0.2 0.2 {}
+T {VOUTN} 305 -164 0 1 0.2 0.2 {}
+T {VINP} 55 -214 0 0 0.2 0.2 {}
+T {VINN} 55 -184 0 0 0.2 0.2 {}
+T {CLK} 55 -154 0 0 0.2 0.2 {}
diff --git a/xschem/my_df.sch b/xschem/my_df.sch
new file mode 100755
index 0000000..78368e8
--- /dev/null
+++ b/xschem/my_df.sch
@@ -0,0 +1,26 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 220 -220 270 -220 {
+lab=CLK}
+N 150 -180 200 -180 {
+lab=#net1}
+N 220 -200 270 -200 {
+lab=D}
+N 460 -220 500 -220 {
+lab=Q}
+N 450 -220 460 -220 {
+lab=Q}
+N 50 -180 70 -180 {
+lab=RESET}
+N 200 -180 270 -180 {
+lab=#net1}
+C {xschem_sky130/sky130_stdcells/inv_1.sym} 110 -180 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {ipin.sym} 220 -220 0 0 {name=p1 lab=CLK}
+C {ipin.sym} 220 -200 0 0 {name=p2 lab=D}
+C {ipin.sym} 50 -180 0 0 {name=p3 lab=RESET}
+C {opin.sym} 500 -220 0 0 {name=p4 lab=Q}
+C {xschem_sky130/sky130_stdcells/dfrtp_1.sym} 360 -200 0 0 {name=x3 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
diff --git a/xschem/my_df.sym b/xschem/my_df.sym
new file mode 100755
index 0000000..10c855a
--- /dev/null
+++ b/xschem/my_df.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -80 -150 -80 -90 {}
+L 4 60 -150 60 -90 {}
+L 4 -100 -100 -80 -100 {}
+L 4 60 -140 80 -140 {}
+L 4 -100 -140 -80 -140 {}
+L 4 -10 -90 -10 -70 {}
+L 4 -80 -150 60 -150 {}
+L 4 -80 -90 60 -90 {}
+B 5 -102.5 -102.5 -97.5 -97.5 {name=CLK dir=in }
+B 5 77.5 -142.5 82.5 -137.5 {name=Q dir=out }
+B 5 -102.5 -142.5 -97.5 -137.5 {name=D dir=in }
+B 5 -12.5 -72.5 -7.5 -67.5 {name=RESET dir=in }
+T {@symname} 9.5 -126 0 0 0.3 0.3 {}
+T {@name} 65 -162 0 0 0.2 0.2 {}
+T {CLK} -75 -104 0 0 0.2 0.2 {}
+T {Q} 55 -144 0 1 0.2 0.2 {}
+T {D} -75 -144 0 0 0.2 0.2 {}
+T {RESET} -24 -105 0 0 0.2 0.2 {}
diff --git a/xschem/my_df2.sch b/xschem/my_df2.sch
new file mode 100755
index 0000000..6fb3fd8
--- /dev/null
+++ b/xschem/my_df2.sch
@@ -0,0 +1,36 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -90 -50 -90 {
+lab=CLK}
+N -170 -50 -120 -50 {
+lab=#net1}
+N -100 -70 -50 -70 {
+lab=D}
+N -270 -50 -250 -50 {
+lab=RESET}
+N -120 -50 -50 -50 {
+lab=#net1}
+N 140 -90 180 -90 {
+lab=Q}
+N 130 -90 140 -90 {
+lab=Q}
+N 140 -70 180 -70 {
+lab=Q_N}
+N 130 -70 140 -70 {
+lab=Q_N}
+N -90 -30 -90 10 {
+lab=VDD}
+N -90 -30 -50 -30 {
+lab=VDD}
+C {xschem_sky130/sky130_stdcells/inv_1.sym} -210 -50 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {ipin.sym} -100 -90 0 0 {name=p1 lab=CLK}
+C {ipin.sym} -100 -70 0 0 {name=p2 lab=D}
+C {ipin.sym} -270 -50 0 0 {name=p3 lab=RESET}
+C {opin.sym} 180 -90 0 0 {name=p4 lab=Q}
+C {opin.sym} 180 -70 0 0 {name=p5 lab=Q_N}
+C {xschem_sky130/sky130_stdcells/dfbbp_1.sym} 40 -60 0 0 {name=x2 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {vdd.sym} -90 10 2 0 {name=l1 lab=VDD}
diff --git a/xschem/my_df2.sym b/xschem/my_df2.sym
new file mode 100755
index 0000000..ec90676
--- /dev/null
+++ b/xschem/my_df2.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -30 -130 30 {}
+L 4 10 -30 10 30 {}
+L 4 -150 20 -130 20 {}
+L 4 10 -20 30 -20 {}
+L 4 -150 -20 -130 -20 {}
+L 4 10 20 30 20 {}
+L 4 -60 30 -60 50 {}
+L 4 -130 -30 10 -30 {}
+L 4 -130 30 10 30 {}
+B 5 -152.5 17.5 -147.5 22.5 {name=CLK dir=in }
+B 5 27.5 -22.5 32.5 -17.5 {name=Q dir=out }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=D dir=in }
+B 5 27.5 17.5 32.5 22.5 {name=Q_N dir=out }
+B 5 -62.5 47.5 -57.5 52.5 {name=RESET dir=in }
+T {@symname} -45 34 0 0 0.3 0.3 {}
+T {@name} 15 -42 0 0 0.2 0.2 {}
+T {CLK} -125 16 0 0 0.2 0.2 {}
+T {Q} 5 -24 0 1 0.2 0.2 {}
+T {D} -125 -24 0 0 0.2 0.2 {}
+T {Q_N} 5 16 0 1 0.2 0.2 {}
+T {RESET} -74 15 0 0 0.2 0.2 {}
diff --git a/xschem/my_df3.sch b/xschem/my_df3.sch
new file mode 100644
index 0000000..aec4b21
--- /dev/null
+++ b/xschem/my_df3.sch
@@ -0,0 +1,25 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 280 50 330 50 {
+lab=CLK}
+N 210 90 260 90 {
+lab=VDD}
+N 280 70 330 70 {
+lab=D}
+N 260 90 330 90 {
+lab=VDD}
+N 520 50 560 50 {
+lab=Q}
+N 510 50 520 50 {
+lab=Q}
+N 210 90 210 130 {
+lab=VDD}
+C {ipin.sym} 280 50 0 0 {name=p3 lab=CLK}
+C {ipin.sym} 280 70 0 0 {name=p5 lab=D}
+C {opin.sym} 560 50 0 0 {name=p7 lab=Q}
+C {vdd.sym} 210 130 2 0 {name=l1 lab=VDD}
+C {xschem_sky130/sky130_stdcells/dfrtp_1.sym} 420 70 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
diff --git a/xschem/my_df3.sym b/xschem/my_df3.sym
new file mode 100644
index 0000000..420d9ce
--- /dev/null
+++ b/xschem/my_df3.sym
@@ -0,0 +1,24 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -70 -200 -70 -140 {}
+L 4 70 -200 70 -140 {}
+L 4 -90 -150 -70 -150 {}
+L 4 70 -190 90 -190 {}
+L 4 -90 -190 -70 -190 {}
+L 4 -70 -200 70 -200 {}
+L 4 -70 -140 70 -140 {}
+B 5 -92.5 -152.5 -87.5 -147.5 {name=CLK dir=in }
+B 5 87.5 -192.5 92.5 -187.5 {name=Q dir=out }
+B 5 -92.5 -192.5 -87.5 -187.5 {name=D dir=in }
+T {@symname} 15 -136 0 0 0.3 0.3 {}
+T {@name} 75 -212 0 0 0.2 0.2 {}
+T {CLK} -65 -154 0 0 0.2 0.2 {}
+T {Q} 65 -194 0 1 0.2 0.2 {}
+T {D} -65 -194 0 0 0.2 0.2 {}
diff --git a/xschem/my_dynamic_comp.sym b/xschem/my_dynamic_comp.sym
new file mode 100755
index 0000000..adc67d7
--- /dev/null
+++ b/xschem/my_dynamic_comp.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -50 130 -50 {}
+L 4 -130 50 130 50 {}
+L 4 -130 -50 -130 50 {}
+L 4 130 -50 130 50 {}
+L 4 130 -20 150 -20 {}
+L 4 130 20 150 20 {}
+L 4 -150 -30 -130 -30 {}
+L 4 -150 0 -130 0 {}
+L 4 -150 30 -130 30 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=OUTP dir=out }
+B 5 147.5 17.5 152.5 22.5 {name=OUTN dir=out }
+B 5 -152.5 -32.5 -147.5 -27.5 {name=INP dir=in }
+B 5 -152.5 -2.5 -147.5 2.5 {name=INN dir=in }
+B 5 -152.5 27.5 -147.5 32.5 {name=CLK dir=in }
+T {@symname} -85.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -62 0 0 0.2 0.2 {}
+T {OUTP} 125 -24 0 1 0.2 0.2 {}
+T {OUTN} 125 16 0 1 0.2 0.2 {}
+T {INP} -125 -34 0 0 0.2 0.2 {}
+T {INN} -125 -4 0 0 0.2 0.2 {}
+T {CLK} -125 26 0 0 0.2 0.2 {}
diff --git a/xschem/my_dynamic_comparator2.sch b/xschem/my_dynamic_comparator2.sch
new file mode 100644
index 0000000..e62b52d
--- /dev/null
+++ b/xschem/my_dynamic_comparator2.sch
@@ -0,0 +1,431 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 620 -480 620 -440 {
+lab=#net1}
+N 520 -480 620 -480 {
+lab=#net1}
+N 520 -520 520 -480 {
+lab=#net1}
+N 620 -480 720 -480 {
+lab=#net1}
+N 720 -520 720 -480 {
+lab=#net1}
+N 620 -380 620 -340 {
+lab=vss}
+N 520 -680 520 -580 {
+lab=#net2}
+N 720 -680 720 -580 {
+lab=#net3}
+N 520 -800 520 -740 {
+lab=vdd}
+N 720 -800 720 -740 {
+lab=vdd}
+N 690 -710 720 -710 {
+lab=vdd}
+N 690 -800 690 -710 {
+lab=vdd}
+N 520 -710 550 -710 {
+lab=vdd}
+N 550 -800 550 -710 {
+lab=vdd}
+N 520 -550 720 -550 {
+lab=vss}
+N 680 -550 680 -340 {
+lab=vss}
+N 620 -410 680 -410 {
+lab=vss}
+N 440 -710 480 -710 {
+lab=clk}
+N 760 -710 810 -710 {
+lab=clk}
+N 530 -410 580 -410 {
+lab=clk}
+N 760 -550 810 -550 {
+lab=inn}
+N 430 -550 480 -550 {
+lab=inp}
+N 440 -800 720 -800 {
+lab=vdd}
+N 1170 -680 1170 -640 {
+lab=#net4}
+N 1380 -680 1380 -640 {
+lab=#net5}
+N 620 -340 1550 -340 {
+lab=vss}
+N 1550 -380 1550 -340 {
+lab=vss}
+N 1380 -380 1380 -340 {
+lab=vss}
+N 1170 -380 1170 -340 {
+lab=vss}
+N 1000 -380 1000 -340 {
+lab=vss}
+N 1000 -410 1030 -410 {
+lab=vss}
+N 1030 -410 1030 -350 {
+lab=vss}
+N 1140 -410 1170 -410 {
+lab=vss}
+N 1140 -410 1140 -340 {
+lab=vss}
+N 1030 -350 1030 -340 {
+lab=vss}
+N 1380 -410 1410 -410 {
+lab=vss}
+N 1410 -410 1410 -340 {
+lab=vss}
+N 1520 -410 1550 -410 {
+lab=vss}
+N 1520 -410 1520 -340 {
+lab=vss}
+N 1170 -580 1170 -440 {
+lab=outp}
+N 1380 -580 1380 -440 {
+lab=outn}
+N 1420 -710 1630 -710 {
+lab=#net3}
+N 1630 -710 1630 -410 {
+lab=#net3}
+N 1590 -410 1630 -410 {
+lab=#net3}
+N 1590 -610 1630 -610 {
+lab=#net3}
+N 910 -710 1130 -710 {
+lab=#net2}
+N 910 -710 910 -410 {
+lab=#net2}
+N 910 -410 960 -410 {
+lab=#net2}
+N 910 -610 960 -610 {
+lab=#net2}
+N 1000 -660 1000 -640 {
+lab=#net4}
+N 1000 -660 1170 -660 {
+lab=#net4}
+N 1380 -660 1550 -660 {
+lab=#net5}
+N 1550 -660 1550 -640 {
+lab=#net5}
+N 720 -800 1380 -800 {
+lab=vdd}
+N 1380 -800 1380 -740 {
+lab=vdd}
+N 1170 -800 1170 -740 {
+lab=vdd}
+N 1170 -710 1200 -710 {
+lab=vdd}
+N 1200 -800 1200 -710 {
+lab=vdd}
+N 1350 -710 1380 -710 {
+lab=vdd}
+N 1350 -800 1350 -710 {
+lab=vdd}
+N 1210 -610 1230 -610 {
+lab=outn}
+N 1230 -610 1230 -410 {
+lab=outn}
+N 1210 -410 1230 -410 {
+lab=outn}
+N 1320 -410 1340 -410 {
+lab=outp}
+N 1320 -610 1320 -410 {
+lab=outp}
+N 1320 -610 1340 -610 {
+lab=outp}
+N 1100 -610 1170 -610 {
+lab=vdd}
+N 1100 -800 1100 -610 {
+lab=vdd}
+N 1380 -610 1450 -610 {
+lab=vdd}
+N 1450 -800 1450 -610 {
+lab=vdd}
+N 1380 -800 1450 -800 {
+lab=vdd}
+N 1000 -580 1000 -550 {
+lab=vss}
+N 1000 -610 1020 -610 {
+lab=vss}
+N 1020 -610 1020 -570 {
+lab=vss}
+N 1000 -570 1020 -570 {
+lab=vss}
+N 1550 -580 1550 -550 {
+lab=vss}
+N 1530 -610 1550 -610 {
+lab=vss}
+N 1530 -610 1530 -570 {
+lab=vss}
+N 1530 -570 1550 -570 {
+lab=vss}
+N 440 -340 620 -340 {
+lab=vss}
+N 350 -710 440 -710 {
+lab=clk}
+N 810 -710 810 -660 {
+lab=clk}
+N 370 -660 810 -660 {
+lab=clk}
+N 370 -710 370 -660 {
+lab=clk}
+N 370 -410 530 -410 {
+lab=clk}
+N 370 -660 370 -410 {
+lab=clk}
+N 1000 -550 1080 -550 {
+lab=vss}
+N 1080 -550 1080 -340 {
+lab=vss}
+N 1460 -550 1550 -550 {
+lab=vss}
+N 1460 -550 1460 -340 {
+lab=vss}
+N 1170 -560 1320 -560 {
+lab=outp}
+N 1230 -460 1380 -460 {
+lab=outn}
+N 1170 -500 1680 -500 {
+lab=outp}
+N 1000 -470 1000 -440 {
+lab=outp}
+N 1380 -470 1550 -470 {
+lab=outn}
+N 1550 -470 1550 -440 {
+lab=outn}
+N 1380 -530 1680 -530 {
+lab=outn}
+N 520 -630 910 -630 {
+lab=#net2}
+N 720 -600 840 -600 {
+lab=#net3}
+N 840 -860 840 -600 {
+lab=#net3}
+N 840 -860 1670 -860 {
+lab=#net3}
+N 1670 -860 1670 -640 {
+lab=#net3}
+N 1630 -640 1670 -640 {
+lab=#net3}
+N 1000 -470 1170 -470 {
+lab=outp}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 500 -550 0 0 {name=M1
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 740 -550 0 1 {name=M2
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 600 -410 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 500 -710 0 0 {name=M4
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 740 -710 0 1 {name=M5
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {ipin.sym} 350 -710 0 0 {name=p2 lab=clk}
+C {ipin.sym} 810 -550 0 1 {name=p4 lab=inn}
+C {ipin.sym} 430 -550 2 1 {name=p5 lab=inp}
+C {ipin.sym} 440 -800 0 0 {name=p7 lab=vdd}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 1150 -710 0 0 {name=M6
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 1400 -710 0 1 {name=M7
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 1190 -610 0 1 {name=M8
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 1360 -610 0 0 {name=M9
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 980 -610 0 0 {name=M10
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 1570 -610 0 1 {name=M11
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 980 -410 0 0 {name=M12
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 1190 -410 0 1 {name=M13
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 1360 -410 0 0 {name=M14
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 1570 -410 0 1 {name=M15
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {ipin.sym} 440 -340 0 0 {name=p8 lab=vss}
+C {opin.sym} 1680 -530 0 0 {name=p1 lab=outn}
+C {opin.sym} 1680 -500 0 0 {name=p3 lab=outp}
diff --git a/xschem/my_dynamic_comparator2.sym b/xschem/my_dynamic_comparator2.sym
new file mode 100644
index 0000000..207ec15
--- /dev/null
+++ b/xschem/my_dynamic_comparator2.sym
@@ -0,0 +1,36 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -60 130 -60 {}
+L 4 -130 60 130 60 {}
+L 4 -130 -60 -130 60 {}
+L 4 130 -60 130 60 {}
+L 4 0 -80 0 -60 {}
+L 4 -150 30 -130 30 {}
+L 4 -150 0 -130 0 {}
+L 4 -150 -30 -130 -30 {}
+L 4 130 30 150 30 {}
+L 4 130 -30 150 -30 {}
+L 4 0 60 0 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=in }
+B 5 -152.5 27.5 -147.5 32.5 {name=clk dir=in }
+B 5 -152.5 -2.5 -147.5 2.5 {name=inn dir=in }
+B 5 -152.5 -32.5 -147.5 -27.5 {name=inp dir=in }
+B 5 147.5 27.5 152.5 32.5 {name=outn dir=out }
+B 5 147.5 -32.5 152.5 -27.5 {name=outp dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=vss dir=in }
+T {@symname} -117 -6 0 0 0.3 0.3 {}
+T {@name} 135 -72 0 0 0.2 0.2 {}
+T {vdd} 4 -45 2 0 0.2 0.2 {}
+T {clk} -125 26 0 0 0.2 0.2 {}
+T {inn} -125 -4 0 0 0.2 0.2 {}
+T {inp} -125 -34 0 0 0.2 0.2 {}
+T {outn} 125 26 0 1 0.2 0.2 {}
+T {outp} 125 -34 0 1 0.2 0.2 {}
+T {vss} -14 45 0 0 0.2 0.2 {}
diff --git a/xschem/my_sar_logic.sch b/xschem/my_sar_logic.sch
new file mode 100755
index 0000000..70acf80
--- /dev/null
+++ b/xschem/my_sar_logic.sch
@@ -0,0 +1,622 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 440 -770 470 -770 {
+lab=Sample}
+N 1540 -1110 1540 -1050 {
+lab=Q05}
+N 1820 -1110 1820 -1050 {
+lab=Q04}
+N 2100 -1110 2100 -1050 {
+lab=Q03}
+N 2380 -1110 2380 -1050 {
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+C {my_df2.sym} 1930 -270 0 0 {name=x31}
+C {my_df2.sym} 2210 -270 0 0 {name=x32}
+C {my_df2.sym} 2490 -270 0 0 {name=x33}
+C {ipin.sym} 340 -180 0 0 {name=p2 lab=CLK}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 2520 -180 0 0 {name=x34 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {opin.sym} 920 -80 0 0 {name=p1 lab=COMP_EN}
+C {lab_wire.sym} 1090 -720 0 1 {name=l8 sig_type=std_logic lab=D6B}
+C {lab_wire.sym} 1370 -720 0 1 {name=l30 sig_type=std_logic lab=D5B}
+C {lab_wire.sym} 1650 -720 0 1 {name=l31 sig_type=std_logic lab=D4B}
+C {lab_wire.sym} 1930 -720 0 1 {name=l32 sig_type=std_logic lab=D3B}
+C {lab_wire.sym} 2210 -720 0 1 {name=l33 sig_type=std_logic lab=D2B}
+C {lab_wire.sym} 2490 -720 0 1 {name=l34 sig_type=std_logic lab=D1B}
+C {lab_wire.sym} 390 -380 0 0 {name=l35 sig_type=std_logic lab=VA}
+C {lab_wire.sym} 560 -380 0 0 {name=l36 sig_type=std_logic lab=VB}
+C {lab_wire.sym} 680 -380 0 0 {name=l37 sig_type=std_logic lab=VC}
+C {lab_wire.sym} 960 -380 0 0 {name=l39 sig_type=std_logic lab=VE}
+C {lab_wire.sym} 1100 -380 0 0 {name=l40 sig_type=std_logic lab=VF}
+C {lab_wire.sym} 1240 -380 0 0 {name=l41 sig_type=std_logic lab=VG}
+C {lab_wire.sym} 1390 -380 0 0 {name=l42 sig_type=std_logic lab=VH}
+C {lab_wire.sym} 1520 -380 0 0 {name=l38 sig_type=std_logic lab=VI}
+C {lab_wire.sym} 1670 -380 0 0 {name=l43 sig_type=std_logic lab=VJ
+}
+C {lab_wire.sym} 1800 -380 0 0 {name=l44 sig_type=std_logic lab=VK
+}
+C {lab_wire.sym} 1960 -380 0 0 {name=l45 sig_type=std_logic lab=VL
+}
+C {lab_wire.sym} 2070 -380 0 0 {name=l46 sig_type=std_logic lab=VM
+}
+C {lab_wire.sym} 2230 -380 0 0 {name=l47 sig_type=std_logic lab=VN
+}
+C {lab_wire.sym} 2370 -380 0 0 {name=l48 sig_type=std_logic lab=VO}
+C {lab_wire.sym} 2530 -380 0 0 {name=l49 sig_type=std_logic lab=VP
+}
+C {lab_wire.sym} 2330 -60 0 0 {name=l50 sig_type=std_logic lab=mark}
+C {lab_wire.sym} 2930 -190 0 0 {name=l21 sig_type=std_logic lab=clear}
+C {lab_wire.sym} 2610 -200 0 0 {name=l28 sig_type=std_logic lab=mark2}
+C {my_df3.sym} 2700 -100 0 0 {name=x5}
+C {gnd.sym} 750 -560 2 0 {name=l29 lab=GND}
+C {df4.sym} 500 -110 0 0 {name=x48}
+C {my_df3.sym} 1450 -860 0 0 {name=x1}
+C {my_df3.sym} 1730 -860 0 0 {name=x3}
+C {my_df3.sym} 2010 -860 0 0 {name=x8}
+C {my_df3.sym} 2290 -860 0 0 {name=x11}
+C {my_df3.sym} 2570 -860 0 0 {name=x14}
+C {my_df3.sym} 2850 -860 0 0 {name=x17}
diff --git a/xschem/my_sar_logic.sym b/xschem/my_sar_logic.sym
new file mode 100755
index 0000000..8c96bf8
--- /dev/null
+++ b/xschem/my_sar_logic.sym
@@ -0,0 +1,81 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -200 130 -200 {}
+L 4 -130 200 130 200 {}
+L 4 -130 -200 -130 200 {}
+L 4 130 -200 130 200 {}
+L 4 130 110 150 110 {}
+L 4 130 150 150 150 {}
+L 4 130 10 150 10 {}
+L 4 130 50 150 50 {}
+L 4 130 -30 150 -30 {}
+L 4 130 90 150 90 {}
+L 4 130 -10 150 -10 {}
+L 4 130 30 150 30 {}
+L 4 130 70 150 70 {}
+L 4 130 170 150 170 {}
+L 4 130 190 150 190 {}
+L 4 130 130 150 130 {}
+L 4 130 -110 150 -110 {}
+L 4 130 -90 150 -90 {}
+L 4 130 -170 150 -170 {}
+L 4 130 -70 150 -70 {}
+L 4 130 -150 150 -150 {}
+L 4 130 -130 150 -130 {}
+L 4 -150 20 -130 20 {}
+L 4 130 -50 150 -50 {}
+L 4 -150 -20 -130 -20 {}
+L 4 130 -190 150 -190 {}
+B 5 147.5 107.5 152.5 112.5 {name=SW3B dir=out }
+B 5 147.5 147.5 152.5 152.5 {name=SW4B dir=out }
+B 5 147.5 7.5 152.5 12.5 {name=SW1 dir=out }
+B 5 147.5 47.5 152.5 52.5 {name=SW2 dir=out }
+B 5 147.5 -32.5 152.5 -27.5 {name=SW0 dir=out }
+B 5 147.5 87.5 152.5 92.5 {name=SW3 dir=out }
+B 5 147.5 -12.5 152.5 -7.5 {name=SW0B dir=out }
+B 5 147.5 27.5 152.5 32.5 {name=SW1B dir=out }
+B 5 147.5 67.5 152.5 72.5 {name=SW2B dir=out }
+B 5 147.5 167.5 152.5 172.5 {name=SW5 dir=out }
+B 5 147.5 187.5 152.5 192.5 {name=SW5B dir=out }
+B 5 147.5 127.5 152.5 132.5 {name=SW4 dir=out }
+B 5 147.5 -112.5 152.5 -107.5 {name=Q03 dir=out }
+B 5 147.5 -92.5 152.5 -87.5 {name=Q04 dir=out }
+B 5 147.5 -172.5 152.5 -167.5 {name=Q00 dir=out }
+B 5 147.5 -72.5 152.5 -67.5 {name=Q05 dir=out }
+B 5 147.5 -152.5 152.5 -147.5 {name=Q01 dir=out }
+B 5 147.5 -132.5 152.5 -127.5 {name=Q02 dir=out }
+B 5 -152.5 17.5 -147.5 22.5 {name=COMP_IN dir=in }
+B 5 147.5 -52.5 152.5 -47.5 {name=Sample dir=out }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=CLK dir=in }
+B 5 147.5 -192.5 152.5 -187.5 {name=COMP_EN dir=out }
+T {@symname} -72 -6 0 0 0.3 0.3 {}
+T {@name} 135 -212 0 0 0.2 0.2 {}
+T {SW3B} 125 106 0 1 0.2 0.2 {}
+T {SW4B} 125 146 0 1 0.2 0.2 {}
+T {SW1} 125 6 0 1 0.2 0.2 {}
+T {SW2} 125 46 0 1 0.2 0.2 {}
+T {SW0} 125 -34 0 1 0.2 0.2 {}
+T {SW3} 125 86 0 1 0.2 0.2 {}
+T {SW0B} 125 -14 0 1 0.2 0.2 {}
+T {SW1B} 125 26 0 1 0.2 0.2 {}
+T {SW2B} 125 66 0 1 0.2 0.2 {}
+T {SW5} 125 166 0 1 0.2 0.2 {}
+T {SW5B} 125 186 0 1 0.2 0.2 {}
+T {SW4} 125 126 0 1 0.2 0.2 {}
+T {Q03} 125 -114 0 1 0.2 0.2 {}
+T {Q04} 125 -94 0 1 0.2 0.2 {}
+T {Q00} 125 -174 0 1 0.2 0.2 {}
+T {Q05} 125 -74 0 1 0.2 0.2 {}
+T {Q01} 125 -154 0 1 0.2 0.2 {}
+T {Q02} 125 -134 0 1 0.2 0.2 {}
+T {COMP_IN} -125 16 0 0 0.2 0.2 {}
+T {Sample} 125 -54 0 1 0.2 0.2 {}
+T {CLK} -125 -24 0 0 0.2 0.2 {}
+T {COMP_EN} 125 -194 0 1 0.2 0.2 {}
diff --git a/xschem/my_sr_latch.sch b/xschem/my_sr_latch.sch
new file mode 100644
index 0000000..23d9b1c
--- /dev/null
+++ b/xschem/my_sr_latch.sch
@@ -0,0 +1,36 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 120 -300 220 -300 {
+lab=S}
+N 120 -80 220 -80 {
+lab=R}
+N 340 -280 440 -280 {
+lab=Q}
+N 340 -100 440 -100 {
+lab=QB}
+N 200 -120 220 -120 {
+lab=Q}
+N 200 -220 200 -120 {
+lab=Q}
+N 200 -220 380 -220 {
+lab=Q}
+N 380 -280 380 -220 {
+lab=Q}
+N 180 -260 220 -260 {
+lab=QB}
+N 180 -260 180 -160 {
+lab=QB}
+N 180 -160 380 -160 {
+lab=QB}
+N 380 -160 380 -100 {
+lab=QB}
+C {xschem_sky130/sky130_stdcells/nor2_1.sym} 280 -280 0 0 {name=x1 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {xschem_sky130/sky130_stdcells/nor2_1.sym} 280 -100 0 0 {name=x2 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {ipin.sym} 120 -300 0 0 {name=p1 lab=S}
+C {ipin.sym} 120 -80 0 0 {name=p2 lab=R}
+C {opin.sym} 440 -280 0 0 {name=p3 lab=Q}
+C {opin.sym} 440 -100 0 0 {name=p4 lab=QB}
diff --git a/xschem/not.sch b/xschem/not.sch
new file mode 100755
index 0000000..a9abe0b
--- /dev/null
+++ b/xschem/not.sch
@@ -0,0 +1,70 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {assign #150 y=~a ;}
+S {}
+E {}
+N 420 -260 420 -230 {lab=out}
+N 420 -260 460 -260 {lab=out}
+N 380 -260 380 -200 {lab=a}
+N 340 -260 380 -260 {lab=a}
+N 420 -400 420 -360 {lab=VDD}
+N 420 -160 420 -140 {lab=GND}
+N 420 -200 500 -200 { lab=GND}
+N 500 -200 500 -160 { lab=GND}
+N 420 -160 500 -160 { lab=GND}
+N 420 -360 500 -360 { lab=VDD}
+N 500 -360 500 -320 { lab=VDD}
+N 420 -320 500 -320 { lab=VDD}
+N 380 -320 380 -260 { lab=a}
+N 420 -290 420 -260 {lab=out}
+N 420 -170 420 -160 { lab=GND}
+N 420 -360 420 -350 { lab=VDD}
+C {vdd.sym} 420 -400 0 0 {name=l1 lab=VDD}
+C {gnd.sym} 420 -140 0 0 {name=l2 lab=GND}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 400 -200 0 0 {name=M1
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 400 -320 0 0 {name=M2
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {ipin.sym} 350 -260 0 0 {name=p1 lab=a}
+C {opin.sym} 450 -260 0 0 {name=p2 lab=y}
diff --git a/xschem/not.sym b/xschem/not.sym
new file mode 100755
index 0000000..5947c7a
--- /dev/null
+++ b/xschem/not.sym
@@ -0,0 +1,21 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -150 0 -130 0 {}
+L 4 -40 0 -20 0 {}
+L 4 -130 -30 -130 30 {}
+L 4 -130 -30 -60 0 {}
+L 4 -130 30 -60 0 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=a dir=in }
+B 5 -22.5 -2.5 -17.5 2.5 {name=y verilog_type=wire dir=out }
+A 4 -50 0 10 270 360 {}
+T {@symname} -131.5 34 0 0 0.3 0.3 {}
+T {@name} -65 -32 0 0 0.2 0.2 {}
+T {a} -145 16 0 0 0.2 0.2 {}
+T {y} -25 16 0 1 0.2 0.2 {}
diff --git a/xschem/tb_saradc.raw b/xschem/tb_saradc.raw
new file mode 100644
index 0000000..319e284
--- /dev/null
+++ b/xschem/tb_saradc.raw
Binary files differ
diff --git a/xschem/tb_saradc.sch b/xschem/tb_saradc.sch
new file mode 100755
index 0000000..777b145
--- /dev/null
+++ b/xschem/tb_saradc.sch
@@ -0,0 +1,257 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1730 -770 1780 -770 {
+lab=SW0}
+N 1730 -770 1780 -770 {
+lab=SW0}
+N 1730 -750 1780 -750 {
+lab=SW0B}
+N 1730 -730 1780 -730 {
+lab=SW1}
+N 1730 -730 1780 -730 {
+lab=SW1}
+N 1730 -710 1780 -710 {
+lab=SW1B}
+N 1730 -690 1780 -690 {
+lab=SW2}
+N 1730 -690 1780 -690 {
+lab=SW2}
+N 1730 -670 1780 -670 {
+lab=SW2B}
+N 1730 -650 1780 -650 {
+lab=SW3}
+N 1730 -650 1780 -650 {
+lab=SW3}
+N 1730 -630 1780 -630 {
+lab=SW3B}
+N 1730 -610 1780 -610 {
+lab=SW4}
+N 1730 -610 1780 -610 {
+lab=SW4}
+N 1730 -590 1780 -590 {
+lab=SW4B}
+N 1730 -570 1780 -570 {
+lab=SW5}
+N 1730 -570 1780 -570 {
+lab=SW5}
+N 1730 -550 1780 -550 {
+lab=SW5B}
+N 660 -210 660 -160 {
+lab=SW0}
+N 660 -210 660 -160 {
+lab=SW0}
+N 740 -210 740 -160 {
+lab=SW0B}
+N 680 -210 680 -160 {
+lab=SW1}
+N 680 -210 680 -160 {
+lab=SW1}
+N 780 -210 780 -160 {
+lab=SW1B}
+N 800 -210 800 -160 {
+lab=SW2}
+N 800 -210 800 -160 {
+lab=SW2}
+N 820 -210 820 -160 {
+lab=SW2B}
+N 720 -210 720 -160 {
+lab=SW3}
+N 720 -210 720 -160 {
+lab=SW3}
+N 860 -210 860 -160 {
+lab=SW3B}
+N 880 -210 880 -160 {
+lab=SW4}
+N 880 -210 880 -160 {
+lab=SW4}
+N 900 -210 900 -160 {
+lab=SW4B}
+N 920 -210 920 -160 {
+lab=SW5}
+N 920 -210 920 -160 {
+lab=SW5}
+N 840 -210 840 -160 {
+lab=SW5B}
+N 240 -690 260 -690 {
+lab=CLK}
+N 1410 -760 1430 -760 {
+lab=CLK}
+N 1160 -370 1160 -350 {
+lab=GND}
+N 1160 -450 1160 -430 {
+lab=VIN}
+N 960 -210 960 -160 {
+lab=VIN}
+N 1730 -930 1820 -930 {
+lab=COMP_EN}
+N 1730 -790 1780 -790 {
+lab=Sample}
+N 1730 -790 1780 -790 {
+lab=Sample}
+N 700 -210 700 -160 {
+lab=Sample}
+N 240 -650 260 -650 {
+lab=COMP_EN}
+N 940 -210 940 -160 {
+lab=VCM}
+N 960 -210 960 -160 {
+lab=VIN}
+N 570 -730 610 -730 {
+lab=#net1}
+N 1400 -220 1400 -200 {
+lab=GND}
+N 1400 -300 1400 -280 {
+lab=VCM}
+N 1730 -910 1780 -910 {
+lab=Q00}
+N 1280 -300 1280 -270 {
+lab=VDD}
+N 1280 -210 1280 -200 {
+lab=GND}
+N 1730 -890 1780 -890 {
+lab=Q01}
+N 1730 -870 1780 -870 {
+lab=Q02}
+N 1730 -850 1780 -850 {
+lab=Q03}
+N 1730 -830 1780 -830 {
+lab=Q04}
+N 1730 -810 1780 -810 {
+lab=Q05}
+N 360 -1020 1780 -1020 {
+lab=COMP_EN}
+N 200 -1020 200 -650 {
+lab=COMP_EN}
+N 200 -650 240 -650 {
+lab=COMP_EN}
+N 540 -670 610 -670 {
+lab=#net2}
+N 1030 -650 1030 -630 {
+lab=#net3}
+N 1030 -570 1030 -550 {
+lab=GND}
+N 910 -720 1070 -720 {
+lab=#net4}
+N 1200 -720 1430 -720 {
+lab=COMP_IN}
+N 1900 -930 1930 -930 {
+lab=COMP_ENB}
+N 760 -210 760 -160 {
+lab=COMP_ENB}
+N 1400 -370 1400 -350 {
+lab=GND}
+N 1400 -450 1400 -430 {
+lab=CLK}
+N 660 -560 660 -510 {
+lab=Vref}
+N 570 -700 610 -700 {
+lab=#net5}
+N 200 -1020 360 -1020 {
+lab=COMP_EN}
+N 380 -670 540 -670 {
+lab=#net2}
+N 450 -730 510 -730 {
+lab=VCM}
+N 450 -700 510 -700 {
+lab=Vref}
+N 910 -680 1030 -680 {
+lab=#net3}
+N 1030 -680 1030 -650 {
+lab=#net3}
+N 1780 -1020 1780 -930 {
+lab=COMP_EN}
+N 770 -780 770 -770 {
+lab=VDD}
+N 1070 -720 1200 -720 {}
+C {my_sar_logic.sym} 1580 -740 0 0 {name=x3}
+C {gnd.sym} 1160 -350 0 0 {name=l30 lab=GND}
+C {vsource.sym} 1160 -400 0 0 {name=V2 value="DC pulse(0 1 0 12.8u 0 0.2u 13u)"}
+C {gnd.sym} 1400 -200 0 0 {name=l41 lab=GND}
+C {opin.sym} 1770 -910 0 0 {name=p42 sig_type=std_logic lab=Q00}
+C {code.sym} 1680 -400 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt
+.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
+C {code.sym} 1840 -400 0 0 {name=STIMULI
+only_toplevel=true
+value="
+.options acct list
+.temp 25
+
+.tran 1n 13u
+.control
+save all
+write tb_saradc2.raw
+.endc
+"
+}
+C {vsource.sym} 1280 -240 0 0 {name=V4 value=1.8
+}
+C {gnd.sym} 1280 -200 0 0 {name=l48 lab=GND}
+C {vdd.sym} 1280 -300 0 0 {name=l49 lab=VDD}
+C {opin.sym} 1770 -890 0 0 {name=p1 sig_type=std_logic lab=Q01}
+C {opin.sym} 1770 -870 0 0 {name=p2 sig_type=std_logic lab=Q02}
+C {opin.sym} 1770 -850 0 0 {name=p3 sig_type=std_logic lab=Q03}
+C {opin.sym} 1770 -830 0 0 {name=p4 sig_type=std_logic lab=Q04}
+C {opin.sym} 1770 -810 0 0 {name=p5 sig_type=std_logic lab=Q05}
+C {my_cdac.sym} 810 -360 3 0 {name=x1}
+C {lab_wire.sym} 1160 -450 0 0 {name=l25 sig_type=std_logic lab=VIN}
+C {lab_wire.sym} 960 -160 1 1 {name=l27 sig_type=std_logic lab=VIN}
+C {lab_wire.sym} 1400 -300 0 0 {name=l28 sig_type=std_logic lab=VCM}
+C {lab_wire.sym} 940 -160 1 1 {name=l29 sig_type=std_logic lab=VCM}
+C {lab_wire.sym} 450 -730 0 0 {name=l31 sig_type=std_logic lab=VCM}
+C {lab_wire.sym} 660 -160 1 1 {name=l13 sig_type=std_logic lab=SW0}
+C {lab_wire.sym} 680 -160 1 1 {name=l14 sig_type=std_logic lab=SW1}
+C {lab_wire.sym} 700 -160 1 1 {name=l17 sig_type=std_logic lab=Sample}
+C {lab_wire.sym} 720 -160 1 1 {name=l18 sig_type=std_logic lab=SW3}
+C {lab_wire.sym} 740 -160 1 1 {name=l19 sig_type=std_logic lab=SW0B}
+C {lab_wire.sym} 780 -160 1 1 {name=l21 sig_type=std_logic lab=SW1B}
+C {lab_wire.sym} 900 -160 1 1 {name=l22 sig_type=std_logic lab=SW4B}
+C {lab_wire.sym} 800 -160 1 1 {name=l23 sig_type=std_logic lab=SW2}
+C {lab_wire.sym} 820 -160 1 1 {name=l24 sig_type=std_logic lab=SW2B}
+C {lab_wire.sym} 840 -160 1 1 {name=l37 sig_type=std_logic lab=SW5B
+}
+C {lab_wire.sym} 860 -160 1 1 {name=l38 sig_type=std_logic lab=SW3B}
+C {lab_wire.sym} 880 -160 1 1 {name=l39 sig_type=std_logic lab=SW4}
+C {lab_wire.sym} 920 -160 1 1 {name=l40 sig_type=std_logic lab=SW5}
+C {lab_wire.sym} 1780 -790 0 1 {name=l1 sig_type=std_logic lab=Sample}
+C {lab_wire.sym} 1780 -770 0 1 {name=l2 sig_type=std_logic lab=SW0}
+C {lab_wire.sym} 1780 -750 0 1 {name=l3 sig_type=std_logic lab=SW0B}
+C {lab_wire.sym} 1780 -730 0 1 {name=l4 sig_type=std_logic lab=SW1}
+C {lab_wire.sym} 1780 -710 0 1 {name=l5 sig_type=std_logic lab=SW1B}
+C {lab_wire.sym} 1780 -690 0 1 {name=l6 sig_type=std_logic lab=SW2}
+C {lab_wire.sym} 1780 -670 0 1 {name=l7 sig_type=std_logic lab=SW2B}
+C {lab_wire.sym} 1780 -650 0 1 {name=l8 sig_type=std_logic lab=SW3}
+C {lab_wire.sym} 1780 -630 0 1 {name=l9 sig_type=std_logic lab=SW3B}
+C {lab_wire.sym} 1780 -610 0 1 {name=l10 sig_type=std_logic lab=SW4}
+C {lab_wire.sym} 1780 -590 0 1 {name=l11 sig_type=std_logic lab=SW4B}
+C {lab_wire.sym} 1780 -570 0 1 {name=l12 sig_type=std_logic lab=SW5}
+C {lab_wire.sym} 1780 -550 0 1 {name=l20 sig_type=std_logic lab=SW5B}
+C {gnd.sym} 1030 -550 0 0 {name=l15 lab=GND}
+C {xschem_sky130/sky130_stdcells/nor2_1.sym} 320 -670 0 0 {name=x5 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 1030 -600 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2.15 MF=1 spiceprefix=X}
+C {xschem_sky130/sky130_stdcells/inv_1.sym} 1860 -930 0 0 {name=x4 VGND=GND VNB=GND VPB=VDD VPWR=VDD prefix=sky130_fd_sc_hd__ }
+C {lab_wire.sym} 1930 -930 0 1 {name=l16 sig_type=std_logic lab=COMP_ENB}
+C {lab_wire.sym} 760 -160 1 1 {name=l32 sig_type=std_logic lab=COMP_ENB}
+C {gnd.sym} 1400 -350 0 0 {name=l26 lab=GND}
+C {vsource.sym} 1400 -400 0 0 {name=V1 value="DC pulse(0 1.8 0 100p 100p 11.11n 22.22n)"}
+C {lab_wire.sym} 1400 -450 0 0 {name=l33 sig_type=std_logic lab=CLK}
+C {lab_wire.sym} 1410 -760 0 0 {name=l34 sig_type=std_logic lab=CLK}
+C {lab_wire.sym} 240 -690 0 0 {name=l35 sig_type=std_logic lab=CLK}
+C {lab_wire.sym} 660 -560 0 0 {name=l36 sig_type=std_logic lab=Vref}
+C {lab_wire.sym} 450 -700 0 0 {name=l42 sig_type=std_logic lab=Vref}
+C {vsource.sym} 1400 -250 0 0 {name=V3 value=0
+}
+C {vsource.sym} 540 -730 1 0 {name=V5 value=0.9}
+C {vsource.sym} 540 -700 1 0 {name=V6 value=0.9}
+C {lab_wire.sym} 1300 -720 0 0 {name=l43 sig_type=std_logic lab=COMP_IN}
+C {lab_wire.sym} 1590 -1020 0 1 {name=l44 sig_type=std_logic lab=COMP_EN}
+C {my_comparator.sym} 580 -520 0 0 {name=x2}
+C {vdd.sym} 770 -780 0 0 {name=l45 lab=VDD}
diff --git a/xschem/tb_saradc.spice b/xschem/tb_saradc.spice
new file mode 100644
index 0000000..c7e0c60
--- /dev/null
+++ b/xschem/tb_saradc.spice
@@ -0,0 +1,439 @@
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/tb_saradc.sch
+**.subckt tb_saradc Q00 Q01 Q02 Q03 Q04 Q05
+*.opin Q00
+*.opin Q01
+*.opin Q02
+*.opin Q03
+*.opin Q04
+*.opin Q05
+x3 SW3B SW4B SW1 SW2 SW0 SW3 SW0B SW1B SW2B SW5 SW5B SW4 Q03 Q04 Q00 Q05 Q01 Q02 COMP_IN Sample CLK
++ COMP_EN my_sar_logic
+V2 VIN GND DC pulse(0 1 0 12.8u 0 0.2u 13u)
+V4 VDD GND 1.8
+x1 Vref SW0 SW1 Sample SW3 SW0B COMP_ENB SW1B SW2 SW2B SW5B SW3B SW4 SW4B SW5 VCM VIN my_cdac
+x5 CLK COMP_EN GND GND VDD VDD net2 sky130_fd_sc_hd__nor2_1
+XC1 net3 GND sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+x4 COMP_EN GND GND VDD VDD COMP_ENB sky130_fd_sc_hd__inv_1
+V1 CLK GND DC pulse(0 1.8 0 100p 100p 11.11n 22.22n)
+V3 VCM GND 0
+V5 net1 VCM 0.9
+V6 net4 Vref 0.9
+x2 VDD COMP_IN net3 net1 net4 net2 my_comparator
+**** begin user architecture code
+ .lib /home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+
+.options acct list
+.temp 25
+
+.tran 1n 13u
+.control
+save all
+write tb_saradc2.raw
+.endc
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: my_sar_logic.sym # of pins=22
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_sar_logic.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_sar_logic.sch
+.subckt my_sar_logic SW3B SW4B SW1 SW2 SW0 SW3 SW0B SW1B SW2B SW5 SW5B SW4 Q03 Q04 Q00 Q05 Q01 Q02
++ COMP_IN Sample CLK COMP_EN
+*.opin Sample
+*.ipin COMP_IN
+*.opin Q05
+*.opin Q04
+*.opin Q03
+*.opin Q02
+*.opin Q01
+*.opin Q00
+*.opin SW5
+*.opin SW4
+*.opin SW4B
+*.opin SW3
+*.opin SW3B
+*.opin SW2
+*.opin SW2B
+*.opin SW1
+*.opin SW1B
+*.opin SW0
+*.opin SW0B
+*.opin SW5B
+*.ipin CLK
+*.opin COMP_EN
+x7 SW4 GND GND VDD VDD SW4B sky130_fd_sc_hd__inv_2
+x10 SW5 GND GND VDD VDD SW5B sky130_fd_sc_hd__inv_2
+x13 SW3 GND GND VDD VDD SW3B sky130_fd_sc_hd__inv_2
+x16 SW2 GND GND VDD VDD SW2B sky130_fd_sc_hd__inv_2
+x19 SW1 GND GND VDD VDD SW1B sky130_fd_sc_hd__inv_2
+x43 SW0 GND GND VDD VDD SW0B sky130_fd_sc_hd__inv_2
+x47 Sample D6 5D GND GND VDD VDD SW5 sky130_fd_sc_hd__or3_1
+x37 Sample D5 4D GND GND VDD VDD SW4 sky130_fd_sc_hd__or3_1
+x38 Sample D4 3D GND GND VDD VDD SW3 sky130_fd_sc_hd__or3_1
+x39 Sample D3 2D GND GND VDD VDD SW2 sky130_fd_sc_hd__or3_1
+x40 Sample D2 1D GND GND VDD VDD SW1 sky130_fd_sc_hd__or3_1
+x41 Sample D1 net1 GND GND VDD VDD SW0 sky130_fd_sc_hd__or3_1
+x20 D6B 5D COMP_IN Sample my_df
+x23 D5B 4D COMP_IN Sample my_df
+x25 D4B 3D COMP_IN Sample my_df
+x26 D3B 2D COMP_IN Sample my_df
+x27 D2B 1D COMP_IN Sample my_df
+x35 D1B net1 COMP_IN Sample my_df
+V1 VA GND 1.8
+x22 D6 GND GND VDD VDD D6B sky130_fd_sc_hd__inv_2
+x24 D5 GND GND VDD VDD D5B sky130_fd_sc_hd__inv_2
+x36 D4 GND GND VDD VDD D4B sky130_fd_sc_hd__inv_2
+x44 D3 GND GND VDD VDD D3B sky130_fd_sc_hd__inv_2
+x45 D2 GND GND VDD VDD D2B sky130_fd_sc_hd__inv_2
+x46 D1 GND GND VDD VDD D1B sky130_fd_sc_hd__inv_2
+x42 VA VB GND GND VDD VDD Sample sky130_fd_sc_hd__and2_0
+x2 VC COMP_EN GND GND VDD VDD GND sky130_fd_sc_hd__and2_0
+x4 VE VF GND GND VDD VDD D6 sky130_fd_sc_hd__and2_0
+x6 VG VH GND GND VDD VDD D5 sky130_fd_sc_hd__and2_0
+x9 VI VJ GND GND VDD VDD D4 sky130_fd_sc_hd__and2_0
+x12 VK VL GND GND VDD VDD D3 sky130_fd_sc_hd__and2_0
+x15 VM VN GND GND VDD VDD D2 sky130_fd_sc_hd__and2_0
+x18 VO VP GND GND VDD VDD D1 sky130_fd_sc_hd__and2_0
+x21 CLK VE VC COMP_EN mark my_df2
+x28 CLK VG VE VF clear my_df2
+x29 CLK VI VG VH clear my_df2
+x30 CLK VK VI VJ clear my_df2
+x31 CLK VM VK VL clear my_df2
+x32 CLK VO VM VN clear my_df2
+x33 CLK mark VO VP clear my_df2
+x34 CLK GND GND VDD VDD mark2 sky130_fd_sc_hd__inv_2
+x5 mark2 clear mark my_df3
+x48 CLK VC VA VB clear df4
+x1 clear Q05 5D my_df3
+x3 clear Q04 4D my_df3
+x8 clear Q03 3D my_df3
+x11 clear Q02 2D my_df3
+x14 clear Q01 1D my_df3
+x17 clear Q00 net1 my_df3
+.ends
+
+
+* expanding symbol: my_cdac.sym # of pins=17
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_cdac.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_cdac.sch
+.subckt my_cdac Vref SW0 SW1 Sample SW3 SW0B COMP_ENB SW1B SW2 SW2B SW5B SW3B SW4 SW4B SW5 VCM VIN
+*.ipin VCM
+*.ipin VIN
+*.ipin COMP_ENB
+*.ipin Sample
+*.ipin SW0
+*.ipin SW0B
+*.ipin SW1
+*.ipin SW1B
+*.ipin SW2
+*.ipin SW2B
+*.ipin SW3
+*.ipin SW3B
+*.ipin SW4
+*.ipin SW4B
+*.ipin SW5
+*.ipin SW5B
+*.opin Vref
+xproblem COMP_ENB C7V VCM analog_switch
+x2 Sample C7V CDACin analog_switch
+x3 SW0B C6V VCM analog_switch
+x4 SW0 C6V CDACin analog_switch
+x5 SW1B C5V VCM analog_switch
+x6 SW1 C5V CDACin analog_switch
+x7 SW2B C4V VCM analog_switch
+x8 SW2 C4V CDACin analog_switch
+x9 SW3B C3V VCM analog_switch
+x10 SW3 C3V CDACin analog_switch
+x11 SW4B C2V VCM analog_switch
+x12 SW4 C2V CDACin analog_switch
+x13 SW5B C1V VCM analog_switch
+x14 SW5 C1V CDACin analog_switch
+x15 Vref C5V cap2
+x16 Vref C4V cap4
+x17 Vref C3V cap8
+x18 Vref C2V cap16
+x19 Vref C1V cap32
+XC1 Vref C7V sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 Vref C6V sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+x1 Sample Vref GND analog_switch
+x20 COMP_ENB CDACin net1 analog_switch
+x21 Sample CDACin VIN analog_switch
+V1 net1 GND 0
+.ends
+
+
+* expanding symbol: my_comparator.sym # of pins=6
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_comparator.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_comparator.sch
+.subckt my_comparator VDD VOUTP VOUTN VINP VINN CLK
+*.ipin VDD
+*.opin VOUTN
+*.opin VOUTP
+*.ipin CLK
+*.ipin VINP
+*.ipin VINN
+XM2 net1 VINP net3 GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MN m=MN
+XM4 net1 CLK VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MP m=MP
+**** begin user architecture code
+
+
+.param MP=1
+.param MN=1
+
+
+**** end user architecture code
+XM5 net2 CLK VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MP m=MP
+XM6 net5 net2 VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MP m=MP
+XM7 net4 net1 VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MP m=MP
+XM8 VOUTP VOUTN net4 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=MP m=MP
+XM9 VOUTN VOUTP net5 VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=MP m=MP
+XM1 net2 VINN net3 GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MN m=MN
+XM3 net3 CLK GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MN m=MN
+XM10 net5 net2 GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MN m=MN
+XM11 net4 net1 GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=MN m=MN
+XM12 VOUTP net1 GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=MN m=MN
+XM13 VOUTP VOUTN GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=MN m=MN
+XM14 VOUTN net2 GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=MN m=MN
+XM15 VOUTN VOUTP GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=MN m=MN
+.ends
+
+
+* expanding symbol: my_df.sym # of pins=4
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_df.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_df.sch
+.subckt my_df CLK Q D RESET
+*.ipin CLK
+*.ipin D
+*.ipin RESET
+*.opin Q
+x1 RESET GND GND VDD VDD net1 sky130_fd_sc_hd__inv_1
+x3 CLK D net1 GND GND VDD VDD Q sky130_fd_sc_hd__dfrtp_1
+.ends
+
+
+* expanding symbol: my_df2.sym # of pins=5
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_df2.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_df2.sch
+.subckt my_df2 CLK Q D Q_N RESET
+*.ipin CLK
+*.ipin D
+*.ipin RESET
+*.opin Q
+*.opin Q_N
+x1 RESET GND GND VDD VDD net1 sky130_fd_sc_hd__inv_1
+x2 CLK D net1 VDD GND GND VDD VDD Q Q_N sky130_fd_sc_hd__dfbbp_1
+.ends
+
+
+* expanding symbol: my_df3.sym # of pins=3
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_df3.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/my_df3.sch
+.subckt my_df3 CLK Q D
+*.ipin CLK
+*.ipin D
+*.opin Q
+x1 CLK D VDD GND GND VDD VDD Q sky130_fd_sc_hd__dfrtp_1
+.ends
+
+
+* expanding symbol: df4.sym # of pins=5
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/df4.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/df4.sch
+.subckt df4 CLK Q D Q_N RESET
+*.ipin CLK
+*.ipin D
+*.ipin RESET
+*.opin Q
+*.opin Q_N
+x2 RESET GND GND VDD VDD net1 sky130_fd_sc_hd__inv_1
+x1 CLK D net1 GND GND VDD VDD Q Q_N sky130_fd_sc_hd__dfrbp_1
+.ends
+
+
+* expanding symbol: analog_switch.sym # of pins=3
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sch
+.subckt analog_switch control OUT IN
+*.ipin IN
+*.ipin control
+*.opin OUT
+x1 net1 OUT IN control transmission_gate
+x2 control net1 not
+.ends
+
+
+* expanding symbol: cap2.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap2.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap2.sch
+.subckt cap2 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap4.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap4.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap4.sch
+.subckt cap4 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap8.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap8.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap8.sch
+.subckt cap8 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC5 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC6 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC7 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC8 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap16.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap16.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap16.sch
+.subckt cap16 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC5 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC6 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC7 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC8 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC9 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC10 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC11 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC12 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC13 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC14 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC15 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC16 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: cap32.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap32.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/cap32.sch
+.subckt cap32 out in
+*.ipin in
+*.opin out
+XC1 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC2 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC3 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC4 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC5 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC6 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC7 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC8 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC9 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC10 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC11 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC12 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC13 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC14 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC15 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC16 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC17 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC18 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC19 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC20 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC21 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC22 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC23 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC24 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC25 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC26 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC27 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC28 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC29 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC30 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC31 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+XC32 out in sky130_fd_pr__cap_mim_m3_1 W=2 L=2.15 MF=1 m=1
+.ends
+
+
+* expanding symbol: transmission_gate.sym # of pins=4
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sch
+.subckt transmission_gate GP OUT IN GN
+*.opin OUT
+*.ipin IN
+*.ipin GN
+*.ipin GP
+XM1 OUT GN IN GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 OUT GP IN VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: not.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sch
+.subckt not a y
+*.ipin a
+*.opin y
+XM1 y a GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 y a VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.GLOBAL VDD
+.end
diff --git a/xschem/tb_saradc2.raw b/xschem/tb_saradc2.raw
new file mode 100644
index 0000000..f5debfa
--- /dev/null
+++ b/xschem/tb_saradc2.raw
Binary files differ
diff --git a/xschem/tb_switch.sch b/xschem/tb_switch.sch
new file mode 100755
index 0000000..71c268c
--- /dev/null
+++ b/xschem/tb_switch.sch
@@ -0,0 +1,83 @@
+v {xschem version=3.0.0 file_version=1.2
+
+* Copyright 2021 Stefan Frederik Schippers
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+
+}
+G {}
+K {}
+V {}
+S {}
+E {}
+N -280 10 -280 20 {
+lab=VIN}
+N -150 -20 -60 -20 {
+lab=VIN}
+N -280 80 -280 100 {
+lab=GND}
+N -60 120 -60 140 {
+lab=GND}
+N -60 40 -60 60 {
+lab=#net1}
+N 50 -20 80 -20 {
+lab=VOUT}
+N -220 -140 -220 -130 {
+lab=VDD}
+N -220 -70 -220 -50 {
+lab=GND}
+N -60 0 -60 40 {
+lab=#net1}
+N -280 -20 -150 -20 {
+lab=VIN}
+N -280 -20 -280 10 {
+lab=VIN}
+N 70 60 70 80 {
+lab=GND}
+N 70 -20 70 -0 {
+lab=VOUT}
+C {gnd.sym} -280 100 0 0 {name=l1 lab=GND}
+C {gnd.sym} -60 140 0 0 {name=l26 lab=GND}
+C {vsource.sym} -60 90 0 0 {name=V2 value="DC pulse(0 1.8 0 30p 30p 5.555n 11.11n)"}
+C {lab_wire.sym} 80 -20 0 1 {name=l2 sig_type=std_logic lab=VOUT}
+C {vsource.sym} -280 50 0 0 {name=V3 value="DC pulse(1 1 0 12.8u 0 0.2u 13u)"}
+C {gnd.sym} -220 -50 0 0 {name=l3 lab=GND}
+C {vsource.sym} -220 -100 0 0 {name=V1 value=1.8}
+C {vdd.sym} -220 -140 0 0 {name=l4 lab=VDD}
+C {code.sym} 250 20 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt
+.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice
+"
+spice_ignore=false}
+C {code.sym} 410 20 0 0 {name=STIMULI
+only_toplevel=true
+value="
+.options acct list
+.temp 25
+.control
+tran 10n 13u
+write tb_saradc.raw
+plot VIN VOUT
+.endc
+"
+}
+C {analog_switch.sym} 90 -10 0 0 {name=x1}
+C {lab_wire.sym} -140 -20 0 0 {name=l5 sig_type=std_logic lab=VIN}
+C {gnd.sym} 70 80 0 0 {name=l6 lab=GND}
+C {capa.sym} 70 30 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
diff --git a/xschem/tb_switch.spice b/xschem/tb_switch.spice
new file mode 100644
index 0000000..39ed1ba
--- /dev/null
+++ b/xschem/tb_switch.spice
@@ -0,0 +1,71 @@
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/tb_switch.sch
+**.subckt tb_switch
+V2 net1 GND DC pulse(0 1.8 0 30p 30p 5.555n 11.11n)
+V3 VIN GND DC pulse(1 1 0 12.8u 0 0.2u 13u)
+V1 VDD GND 1.8
+x1 net1 VOUT VIN analog_switch
+C1 VOUT GND 10f m=1
+**** begin user architecture code
+ .lib /home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+
+.options acct list
+.temp 25
+.control
+tran 10n 13u
+write tb_saradc.raw
+plot VIN VOUT
+.endc
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: analog_switch.sym # of pins=3
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/analog_switch.sch
+.subckt analog_switch control OUT IN
+*.ipin IN
+*.ipin control
+*.opin OUT
+x1 net1 OUT IN control transmission_gate
+x2 control net1 not
+.ends
+
+
+* expanding symbol: transmission_gate.sym # of pins=4
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/transmission_gate.sch
+.subckt transmission_gate GP OUT IN GN
+*.opin OUT
+*.ipin IN
+*.ipin GN
+*.ipin GP
+XM1 OUT GN IN GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 OUT GP IN VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: not.sym # of pins=2
+** sym_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sym
+** sch_path: /home/oe23ranan/caravel_user_project_analog/xschem/not.sch
+.subckt not a y
+*.ipin a
+*.opin y
+XM1 y a GND GND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 y a VDD VDD sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.GLOBAL VDD
+.end
diff --git a/xschem/transmission_gate.sch b/xschem/transmission_gate.sch
new file mode 100755
index 0000000..1c67e39
--- /dev/null
+++ b/xschem/transmission_gate.sch
@@ -0,0 +1,67 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 400 -150 460 -150 {
+lab=IN}
+N 400 -390 400 -150 {
+lab=IN}
+N 400 -390 460 -390 {
+lab=IN}
+N 520 -390 580 -390 {
+lab=OUT}
+N 580 -390 580 -150 {
+lab=OUT}
+N 520 -150 580 -150 {
+lab=OUT}
+N 340 -270 400 -270 {
+lab=IN}
+N 580 -270 640 -270 {
+lab=OUT}
+N 490 -470 490 -430 {
+lab=GP}
+N 490 -110 490 -80 {
+lab=GN}
+N 490 -390 490 -350 {
+lab=VDD}
+N 490 -200 490 -150 {
+lab=GND}
+N 490 -350 490 -330 {
+lab=VDD}
+C {opin.sym} 630 -270 0 0 {name=p1 lab=OUT}
+C {ipin.sym} 350 -270 0 0 {name=p2 lab=IN}
+C {ipin.sym} 490 -90 3 0 {name=p3 lab=GN}
+C {ipin.sym} 490 -460 1 0 {name=p4 lab=GP
+}
+C {gnd.sym} 490 -200 2 0 {name=l1 lab=GND}
+C {vdd.sym} 490 -330 2 0 {name=l2 lab=VDD}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 490 -130 1 1 {name=M1
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/pfet_01v8_lvt.sym} 490 -410 3 1 {name=M2
+L=0.35
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
diff --git a/xschem/transmission_gate.sym b/xschem/transmission_gate.sym
new file mode 100755
index 0000000..8cd1081
--- /dev/null
+++ b/xschem/transmission_gate.sym
@@ -0,0 +1,30 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 180 -180 180 -160 {}
+L 4 230 -120 250 -120 {}
+L 4 110 -120 130 -120 {}
+L 4 130 -160 130 -80 {}
+L 4 130 -80 230 -120 {}
+L 4 130 -160 230 -120 {}
+L 4 130 -120 230 -160 {}
+L 4 230 -160 230 -80 {}
+L 4 130 -120 230 -80 {}
+L 4 180 -100 180 -60 {}
+B 5 177.5 -182.5 182.5 -177.5 {name=GP dir=in }
+B 5 247.5 -122.5 252.5 -117.5 {name=OUT dir=out }
+B 5 107.5 -122.5 112.5 -117.5 {name=IN dir=in }
+B 5 177.5 -62.5 182.5 -57.5 {name=GN dir=in }
+A 4 180 -150 10 270 360 {}
+T {@symname} 125.5 -36 0 0 0.3 0.3 {}
+T {@name} 235 -152 0 0 0.2 0.2 {}
+T {GP} 194 -185 2 0 0.2 0.2 {}
+T {OUT} 265 -114 0 1 0.2 0.2 {}
+T {IN} 105 -114 0 0 0.2 0.2 {}
+T {GN} 175 -54 0 0 0.2 0.2 {}
diff --git a/xschem/xschemrc b/xschem/xschemrc
index 985eea7..2289e77 100644
--- a/xschem/xschemrc
+++ b/xschem/xschemrc
@@ -29,6 +29,7 @@
if {[catch {set PDKPATH $env(PDKPATH)}]} {
set PDKPATH "/usr/share/pdk/sky130A"
}
+set PDKPATH "/home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A"
#### Flush any previous definition
set XSCHEM_LIBRARY_PATH {}
#### include devices/*.sym
@@ -292,5 +293,7 @@
## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation
# set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice
# set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
+# set SKYWATER_MODELS /home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.tech/ngspice
set SKYWATER_MODELS $PDKPATH/libs.tech/ngspice
+# set SKYWATER_STDCELLS /home/oe23ranan/pdk/volare/sky130/versions/41c0908b47130d5675ff8484255b43f66463a7d6/sky130A/libs.ref/sky130_fd_sc_hd/spice
set SKYWATER_STDCELLS $PDKPATH/libs.ref/sky130_fd_sc_hd/spice
