openlane/designs/salsa20/config.tcl

set ::env(DESIGN_NAME) "salsa20"

set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/salsa20.v"

set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)

set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}