blob: 570ea67681d6662d24dd8bbaa5ffb45ee979a526 [file] [log] [blame]
# Design
# User config
set ::env(DESIGN_NAME) wbqspiflash
# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
# Fill this
set ::env(CLOCK_PORT) "i_clk"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}