Variables information

This page describes configuration variables and their default values.

Required variables

VariableDescription
DESIGN_NAMEThe name of the top level module of the design
VERILOG_FILESThe path of the design's verilog files
CLOCK_PERIODThe clock period for the design in ns
CLOCK_NETThe name of the Net input to root clock buffer used in Clock Tree Synthesis.
CLOCK_PORTThe name of the design's clock port used in Static Timing Analysis.

Optional variables

These variables are optional that can be specified in the design configuration file.

Synthesis

VariableDescription
SYNTH_BINThe yosys binary used in the flow.
(Default: yosys)
LIB_SYNTHThe library used for synthesis by yosys.
(Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__tt_025C_1v80.lib)
SYNTH_DRIVING_CELLThe cell to drive the input ports.
(Default: sky130_fd_sc_hd__inv_1)
SYNTH_DRIVING_CELL_PINThe name of the SYNTH_DRIVING_CELL output pin.
(Default: Y)
SYNTH_CAP_LOADThe capacitive load on the output ports in femtofarads.
(Default: 33.5 ff)
SYNTH_MAX_FANOUTThe max load that the output ports can drive.
(Default: 5 cells)
SYNTH_MAX_TRANThe max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis
(Default: Calculated at runtime as 10% of the provided clock period, unless this exceeds a set DEFAULT_MAX_TRAN, in which case it will be used as is).
SYNTH_CLOCK_UNCERTAINITYSpecifies a value for the clock uncertainity in the pre-CTS stages.
(Default: 0.25)
SYNTH_CLOCK_TRANSITIONSpecifies a value for the clock transition in the pre-CTS stages.
(Default: 0.15)
SYNTH_TIMING_DERATESpecifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing.
(Default: +5%/-5%)
SYNTH_STRATEGYStrategies for abc logic synthesis and technology mapping
Possible values are DELAY/AREA 0-4/0-3; the first part refers to the optimization target of the synthesis strategy (area vs. delay) and the second one is an index.
(Default: AREA 0)
SYNTH_BUFFERINGEnables abc cell buffering
Enabled = 1, Disabled = 0
(Default: 1)
SYNTH_SIZINGEnables abc cell sizing (instead of buffering)
Enabled = 1, Disabled = 0
(Default: 0)
SYNTH_READ_BLACKBOX_LIBA flag that enable reading the full(untrimmed) liberty file as a blackbox for synthesis. Please note that this is not used in technology mapping. This should only be used when trying to preserve gate instances in the rtl of the design.
Enabled = 1, Disabled = 0
(Default: 0)
SYNTH_NO_FLATA flag that disables flattening the hierarchy during synthesis, only flattening it after synthesis, mapping and optimizations.
Enabled = 1, Disabled = 0
(Default: 0)
SYNTH_SHARE_RESOURCESA flag that enables yosys to reduce the number of cells by determining shareable resources and merging them.
Enabled = 1, Disabled = 0
(Default: 1)
SYNTH_ADDER_TYPEAdder type to which the $add and $sub operators are mapped to.
Possible values are YOSYS/FA/RCA/CSA; where YOSYS refers to using Yosys internal adder definition, FA refers to full-adder structure, RCA refers to ripple carry adder structure, and CSA refers to carry select adder.
(Default: YOSYS)
SYNTH_EXTRA_MAPPING_FILEPoints to extra techmap file for yosys that runs right after yosys synth before generic techmap.
(Default: "")
LIB_FASTESTPoints to the lib file, corresponding to the slowest corner, for max delay calculation during STA.
(Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib)
LIB_SLOWESTPoints to the lib file, corresponding to the fastest corner, for min delay calculation during STA.
(Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ss_100C_1v60.lib)
LIB_TYPICALLibrary used for typical delay calculation during STA.
(DefaultLIB_SYNTH)
CLOCK_BUFFER_FANOUTFanout of clock tree buffers.
(Default: 16)
ROOT_CLK_BUFFERRoot clock buffer of the clock tree.
(Default: sky130_fd_sc_hd__clkbuf_16)
CLK_BUFFERClock buffer used for inner nodes of the clock tree.
(Default: sky130_fd_sc_hd__clkbuf_4)
CLK_BUFFER_INPUTInput pin of the clock tree buffer.
(Default: A)
CLK_BUFFER_OUTPUTOutput pin of the clock tree buffer.
(Default: X)
BASE_SDC_FILESpecifies the base sdc file to source before running Static Timing Analysis.
(Default: $::env(OPENLANE_ROOT)/scripts/base.sdc)
VERILOG_INCLUDE_DIRSSpecifies the verilog includes directories.
Optional.
SYNTH_FLAT_TOPSpecifies whether or not the top level should be flattened during elaboration. 1 = True, 0= False
Default: 0.
IO_PCTSpecifies the percentage of the clock period used in the input/output delays. Ranges from 0 to 1.0.
(Default: 0.2)
VERILOG_FILES_BLACKBOXTo point at the blackboxes (the hardened macros). Ideally, this should include all the other verilog files

Floorplanning

VariableDescription
FP_CORE_UTILThe core utilization percentage.
(Default: 50 percent)
FP_ASPECT_RATIOThe core's aspect ratio (height / width).
(Default: 1)
FP_SIZINGWhether to use relative sizing by making use of FP_CORE_UTIL or absolute one using DIE_AREA.
(Default: "relative" - accepts “absolute” as well)
DIE_AREASpecific die area to be used in floorplanning. Specified as a 4-corner rectangle “x0 y0 x1 y1”. Units in um
(Default: unset)
FP_IO_MODEDecides the mode of the random IO placement option. 0=matching mode, 1=random equidistant mode
(Default: 1)
FP_WELLTAP_CELLThe name of the welltap cell during welltap insertion.
FP_ENDCAP_CELLThe name of the endcap cell during endcap insertion.
FP_PDN_VOFFSETThe offset of the vertical power stripes on the metal layer 4 in the power distribution network
(Default: 16.32)
FP_PDN_VPITCHThe pitch of the vertical power stripes on the metal layer 4 in the power distribution network
(Default: 153.6)
FP_PDN_HOFFSETThe offset of the horizontal power stripes on the metal layer 5 in the power distribution network
(Default: 16.65)
FP_PDN_HPITCHThe pitch of the horizontal power stripes on the metal layer 5 in the power distribution network
(Default: 153.18)
FP_PDN_AUTO_ADJUSTDecides whether or not the flow should attempt to re-adjust the power grid, in order for it to fit inside the core area of the design, if needed.
1=enabled, 0 =disabled (Default: 1)
FP_TAPCELL_DISTThe horizontal distance between two tapcell columns
(Default: 14)
FP_IO_VEXTENDExtends the vertical io pins outside of the die by the specified units
(Default: -1 Disabled)
FP_IO_HEXTENDExtends the horizontal io pins outside of the die by the specified units
(Default: -1 Disabled)
FP_IO_VLENGTHThe length of the vertical IOs in microns.
(Default: 4)
FP_IO_HLENGTHThe length of the horizontal IOs in microns.
(Default: 4)
FP_IO_VTHICKNESS_MULTA multiplier for vertical pin thickness. Base thickness is the pins layer minwidth
(Default: 2)
FP_IO_HTHICKNESS_MULTA multiplier for horizontal pin thickness. Base thickness is the pins layer minwidth
(Default: 2)
FP_IO_UNMATCHED_ERRORExit on unmatched pins in a provided FP_PIN_ORDER_CFG file. 0=Disable 1=Enable.
(Default: 1 Enabled)
BOTTOM_MARGIN_MULTThe core margin, in multiples of site heights, from the bottom boundary.
(Default: 4)
TOP_MARGIN_MULTThe core margin, in multiples of site heights, from the top boundary.
(Default: 4)
LEFT_MARGIN_MULTThe core margin, in multiples of site widths, from the left boundary.
(Default: 12)
RIGHT_MARGIN_MULTThe core margin, in multiples of site widths, from the right boundary.
(Default: 12)
FP_PDN_CORE_RINGEnables adding a core ring around the design. More details on the control variables in the pdk configurations documentation. 0=Disable 1=Enable.
(Default: 0)
FP_PDN_ENABLE_RAILSEnables the creation of rails in the power grid. 0=Disable 1=Enable.
(Default: 1)
FP_PDN_ENABLE_MACROS_GRIDEnables the connection of macros to the top level power grid. 0=Disable 1=Enable.
(Default: 1)
FP_PDN_MACRO_HOOKSSpecifies explicit power connections of internal macros to the top level power grid. Comma separated list of macro instance names and power domain vdd and ground net names: <instance_name> <vdd_net> <gnd_net>
FP_PDN_CHECK_NODESEnables checking for unconnected nodes in the power grid. 0=Disable 1=Enable.
(Default: 1)
FP_TAP_HORIZONTAL_HALOSpecify the horizontal halo size around macros during tap insertion. The value provided is in microns.
Default: 10
FP_TAP_VERTICAL_HALOSpecify the vertical halo size around macros during tap insertion. The value provided is in microns.
Default: set to the value of FP_TAP_HORIZONTAL_HALO
FP_PDN_HORIZONTAL_HALOSets the horizontal halo around the macros during power grid insertion. The value provided is in microns.
Default: 10
FP_PDN_VERTICAL_HALOSets the vertical halo around the macros during power grid insertion. The value provided is in microns.
Default: set to the value of FP_PDN_HORIZONTAL_HALO
DESIGN_IS_COREControls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro
(Default: 1)
FP_PIN_ORDER_CFGPoints to the pin order configuration file to set the pins in specific directions (S, W, E, N). Check this file as an example. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations.
(Default: NONE)
FP_CONTEXT_DEFPoints to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with FP_CONTEXT_LEF, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations.
(Default: NONE)
FP_CONTEXT_LEFPoints to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with FP_CONTEXT_DEF, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations.
(Default: NONE)
FP_DEF_TEMPLATEPoints to the DEF file to be used as a template when running apply_def_template. This will be used to exctract pin names, locations, shapes -excluding power and ground pins- as well as the die area and replicate all this information in the CURRENT_DEF.
VDD_NETSSpecifies the power nets/pins to be used when creating the power grid for the design.
GND_NETSSpecifies the ground nets/pins to be used when creating the power grid for the design.
SYNTH_USE_PG_PINS_DEFINESSpecifies the power guard used in the verilog source code to specify the power and ground pins. This is used to automatically extract VDD_NETS and GND_NET variables from the verilog, with the assumption that they will be order inout vdd1, inout gnd1, inout vdd2, inout gnd2, ....
FP_PDN_IRDROPEnable calculation of power grid IR drop during PDN generation.
(Default: 1)
FP_IO_MIN_DISTANCEThe minmimum distance between the IOs in microns.
(Default: 3)

Deprecated I/O Layer variables

These variables worked initially, but they were too sky130 specific and will be removed. Currently, if you define them in your design, they‘ll be used, but it’s recommended to update your configuration to use FP_IO_HLAYER and FP_IO_VLAYER, which are defined in the PDK.

VariableDescription
FP_IO_HMETALThe metal layer on which to place the io pins horizontally (top and bottom of the die).
(Default: 4)
FP_IO_VMETALThe metal layer on which to place the io pins vertically (sides of the die)
(Default: 3)

Placement

VariableDescription
PL_TARGET_DENSITYThe desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread
(Default: 0.55)
PL_TIME_DRIVENSpecifies whether the placer should use time driven placement. 0 = false, 1 = true
(Default: 1)
PL_LIBSpecifies the library for time driven placement
(Default: LIB_TYPICAL)
PL_BASIC_PLACEMENTSpecifies whether the placer should run basic placement or not (by running initial placement, increasing the minimum overflow to 0.9, and limiting the number of iterations to 20). 0 = false, 1 = true
(Default: 0)
PL_SKIP_INITIAL_PLACEMENTSpecifies whether the placer should run initial placement or not. 0 = false, 1 = true
(Default: 0)
PL_RANDOM_GLB_PLACEMENTSpecifies whether the placer should run random placement or not. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true
(Default: 0)
PL_RANDOM_INITIAL_PLACEMENTSpecifies whether the placer should run random placement or not followed by replace's initial placement. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true
(Default: 0)
PL_ROUTABILITY_DRIVENSpecifies whether the placer should use routability driven placement. 0 = false, 1 = true
(Default: 1)
PL_RESIZER_DESIGN_OPTIMIZATIONSSpecifies whether resizer design optimizations should be performed or not. 0 = false, 1 = true
(Default: 1)
PL_RESIZER_TIMING_OPTIMIZATIONSSpecifies whether resizer timing optimizations should be performed or not. 0 = false, 1 = true
(Default: 1)
PL_RESIZER_MAX_WIRE_LENGTHSpecifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns.
(Default: 0)
PL_RESIZER_MAX_SLEW_MARGINSpecifies a margin for the slews in percentage.
(Default: 20)
PL_RESIZER_MAX_CAP_MARGINSpecifies a margin for the capacitances in percentage.
(Default: 20)
PL_RESIZER_HOLD_SLACK_MARGINSpecifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix.
(Default: 0.1ns.)
PL_RESIZER_SETUP_SLACK_MARGINSpecifies a time margin for the slack when fixing setup violations.
(Default: 0.05ns)
PL_RESIZER_HOLD_MAX_BUFFER_PERCENTSpecifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design.
(Default: 50)
PL_RESIZER_SETUP_MAX_BUFFER_PERCENTSpecifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design.
(Default: 50)
PL_RESIZER_ALLOW_SETUP_VIOSAllows setup violations when fixing hold.
(Default: 0)
LIB_RESIZER_OPTPoints to the lib file, corresponding to the typical corner, that is used during resizer optimizations. This is copy of LIB_SYNTH_COMPLETE.
Default: $::env(synthesis_tmpfiles)/resizer_<library-name>.lib
DONT_USE_CELLSThe list of cells to not use during resizer optimizations.
Default: the contents of DRC_EXCLUDE_CELL_LIST.
PL_ESTIMATE_PARASITICSSpecifies whether or not to run STA after global placement using OpenROAD's estimate_parasitics -placement and generates reports under logs/placement. 1 = Enabled, 0 = Disabled.
(Default: 1)
PL_OPTIMIZE_MIRRORINGSpecifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. 1 = Enabled, 0 = Disabled.
(Default: 1)
PL_RESIZER_BUFFER_INPUT_PORTSSpecifies whether or not to insert buffers on input ports whenever resizer optimizations are run. For this to be used, PL_RESIZER_DESIGN_OPTIMIZATIONS must be set to 1. 1 = Enabled, 0 = Disabled.
(Default: 1)
PL_RESIZER_BUFFER_OUTPUT_PORTSSpecifies whether or not to insert buffers on output ports whenever resizer optimizations are run. For this to be used, PL_RESIZER_DESIGN_OPTIMIZATIONS must be set to 1. 1 = Enabled, 0 = Disabled.
(Default: 1)
PL_RESIZER_REPAIR_TIE_FANOUTSpecifies whether or not to repair tie cells fanout whenever resizer optimizations are run. For this to be used, PL_RESIZER_DESIGN_OPTIMIZATIONS must be set to 1. 1 = Enabled, 0 = Disabled.
(Default: 1)
PL_MAX_DISPLACEMENT_XSpecifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.
(Default: 500um)
PL_MAX_DISPLACEMENT_YSpecifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.
(Default: 100um)
PL_MACRO_HALOMacro placement halo. Format: {Horizontal} {Vertical}
(Default: 0 0um).
PL_MACRO_CHANNELChannel widths between macros. Format: {Horizontal} {Vertical}
(Default: 0 0um).
MACRO_PLACEMENT_CFGSpecifies the path a file specifying how openlane should place certain macros
LIB_OPTRemoved: Points to the lib file, corresponding to the slowest corner, for max delay calculation during OpenPhySyn optimizations. This is usually a trimmed version of LIB_SYNTH.
Default: $::env(TMP_DIR)/opt.lib
PL_DIAMOND_SEARCH_HEIGHTRemoved: Use PL_MAX_DISPLACEMENT_(X/Y) instead: Specifies the diamond search height used for legalizing the cells during detailed placement. The search width is calculated internally as heigh*5. For designs that contain big macros, increasing this value to above 400 will allow for more search space and more potentail for successful legalization.
(Default: 100)
PL_OPENPHYSYN_OPTIMIZATIONSRemoved: Specifies whether OpenPhySyn should be used to perform timing optimizations or not. 0 = false, 1 = true
(Default: 0)
PSN_ENABLE_RESIZINGRemoved: Enables driver resizing by OpenPhySyn. 0 = Disabled, 1 = Enabled
(Default: 1)
PSN_ENABLE_PIN_SWAPRemoved: Enables pin swapping for timing optimization by OpenPhySyn. 0 = Disabled, 1 = Enabled
(Default: 1)

CTS

VariableDescription
CTS_TARGET_SKEWThe target clock skew in picoseconds.
(Default: 200ps)
CTS_ROOT_BUFFERThe name of cell inserted at the root of the clock tree.
CLOCK_TREE_SYNTHEnable clock tree synthesis.
(Default: 1)
RUN_SIMPLE_CTSRuns an alternative simple clock tree synthesis after synthesis instead of TritonCTS. 1 = Enabled, 0 = Disabled
(Default: 0)
FILL_INSERTIONEnables fill cells insertion after cts (if enabled). 1 = Enabled, 0 = Disabled
(Default: 1)
CTS_TOLERANCEAn integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR
(Default: 100)
CTS_SINK_CLUSTERING_SIZESpecifies the maximum number of sinks per cluster.
(Default: 25)
CTS_SINK_CLUSTERING_MAX_DIAMETERSpecifies maximum diameter (in micron) of sink cluster.
(Default: 50)
CTS_REPORT_TIMINGSpecifies whether or not to run STA after clock tree synthesis using OpenROAD's estimate_parasitics -placement and generates reports under logs/cts. 1 = Enabled, 0 = Disabled.
(Default: 1)
CTS_CLK_MAX_WIRE_LENGTHSpecifies the maximum wire length on the clock net. Value in microns.
(Default: 0)
CTS_DISABLE_POST_PROCESSINGSpecifies whether or not to disable post cts processing for outlier sinks.
(Default: 0)
CTS_DISTANCE_BETWEEN_BUFFERSSpecifies the distance (in microns) between buffers when creating the clock tree (Default: 0)
LIB_CTSThe liberty file used for CTS. By default, this is the LIB_SYNTH_COMPLETE minus the cells with drc errors as specified by the drc exclude list.
(Default: $::env(cts_tmpfiles)/cts.lib)

Routing

VariableDescription
GLOBAL_ROUTERSpecifies which global router to use. Values: fastroute or cugr.
(Default: fastroute)
DETAILED_ROUTERSpecifies which detailed router to use. Values: tritonroute, tritonroute_or (identical to tritonroute, deprecated) or drcu.
(Default: tritonroute)
ROUTING_CORESSpecifies the number of threads to be used in TritonRoute. Can be overriden via environment variable.
(Default: 2)
RT_CLOCK_MIN_LAYERThe name of lowest layer to be used in routing the clock net.
(Default: RT_MIN_LAYER)
RT_CLOCK_MAX_LAYERThe name of highest layer to be used in routing the clock net.
(Default: RT_MAX_LAYER)
GLB_RT_ALLOW_CONGESTIONAllow congestion in the resulting guides. 0 = false, 1 = true
(Default: 0)
GLB_RT_OVERFLOW_ITERSThe maximum number of iterations waiting for the overflow to reach the desired value.
(Default: 50)
GLB_RT_ANT_ITERSThe maximum number of iterations for global router repair_antenna. This option is only available in DIODE_INSERTION_STRATEGY = 3.
(Default: 3)
GLB_RT_ESTIMATE_PARASITICSSpecifies whether or not to run STA after global routing using OpenROAD's estimate_parasitics -global_routing and generates reports under logs/routing. 1 = Enabled, 0 = Disabled.
(Default: 1)
GLB_RT_MAX_DIODE_INS_ITERSControls the maximum number of iterations at which re-running Fastroute for diode insertion stops. Each iteration ARC detects the violations and FastRoute fixes them by inserting diodes, then producing the new DEF. The number of antenna violations is compared with the previous iteration and if they are equal or the number is greater the iterations stop and the DEF from the previous iteration is used in the rest of the flow. If the current antenna violations reach zero, the current def will be used and the iterations will not continue. This option is only available in DIODE_INSERTION_STRATEGY = 3.
(Default: 1)
GLB_RT_OBSSpecifies custom obstruction to be added prior to global routing. Comma separated list of layer and coordinates: layer llx lly urx ury.
(Example: li1 0 100 1000 300, met5 0 0 1000 500)
(Default: unset)
GLB_RESIZER_TIMING_OPTIMIZATIONSSpecifies whether resizer timing optimizations should be performed after global routing or not. 0 = false, 1 = true
(Default: 1)
GLB_RESIZER_MAX_WIRE_LENGTHSpecifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns.
(Default: 0)
GLB_RESIZER_MAX_SLEW_MARGINSpecifies a margin for the slews.
(Default: 10)
GLB_RESIZER_MAX_CAP_MARGINSpecifies a margin for the capacitances.
(Default: 10)
GLB_RESIZER_HOLD_SLACK_MARGINSpecifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix.
(Default: 0.1ns)
GLB_RESIZER_SETUP_SLACK_MARGINSpecifies a time margin for the slack when fixing setup violations.
(Default: 0.05ns)
GLB_RESIZER_HOLD_MAX_BUFFER_PERCENTSpecifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design.
(Default: 50)
GLB_RESIZER_SETUP_MAX_BUFFER_PERCENTSpecifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design.
(Default: 50)
GLB_RESIZER_ALLOW_SETUP_VIOSAllows setup violations when fixing hold.
(Default: 0)
GLB_OPTIMIZE_MIRRORINGSpecifies whether or not to run an optimize_mirroring pass whenever detailed placement happens after Routing timing optimization. This pass will mirror the cells whenever possible to optimize the design. 1 = Enabled, 0 = Disabled.
(Default: 1)
GLB_RT_ADJUSTMENTReduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1.
1 = most reduction, 0 = least reduction
(Default: 0.3)
GLB_RT_MACRO_EXTENSIONSets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.
(Default: 0)
DRT_MIN_LAYERAn optional override to the lowest layer used in detailed routing. For example, in sky130, you may want global routing to avoid li1, but let detailed routing use li1 if it has to.
(Default: RT_MIN_LAYER)
DRT_MAX_LAYERAn optional override to the highest layer used in detailed routing.
(Default: RT_MAX_LAYER)
DRT_OPT_ITERSSpecifies the maximum number of optimization iterations during Detailed Routing in TritonRoute.
(Default: 64)
ROUTING_OPT_ITERSDeprecated: Use DRT_OPT_ITERS: Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute.
(Default: 64)

Deprecated Layer Adjustment Variables

These variables worked initially, but they were too sky130 specific and will be removed. Currently, if you define them in your design, they‘ll be concatenated into GLB_RT_LAYER_ADJUSTMENTS, but it’s recommended to update your configuration to use GLB_RT_LAYER_ADJUSTMENTS, which is defined in the PDK.

VariableDescription
GLB_RT_L1_ADJUSTMENTDeprecated: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in sky130A. Values range from 0 to 1
(Default: 0.99)
GLB_RT_L2_ADJUSTMENTDeprecated: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in sky130A. Values range from 0 to 1
(Default: 0)
GLB_RT_L3_ADJUSTMENTDeprecated: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met2 in sky130A. Values range from 0 to 1
(Default: 0)
GLB_RT_L4_ADJUSTMENTDeprecated: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met3 in sky130A. Values range from 0 to 1
(Default: 0)
GLB_RT_L5_ADJUSTMENTDeprecated: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met4 in sky130A. Values range from 0 to 1
(Default: 0)
GLB_RT_L6_ADJUSTMENTDeprecated: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met5 in sky130A. Values range from 0 to 1
(Default: 0)

Deprecated Min/Max Layer Variables

These variables worked initially, but they were too sky130 specific and will be removed. Currently, if you define them in your design, they'll be translated to the correct variables, RT_{MIN/MAX}_LAYER and RT_CLOCK_{MIN/MAX}_LAYER.

VariableDescription
GLB_RT_MINLAYERDeprecated: The number of lowest layer to be used in routing.
(Default: 1)
GLB_RT_MAXLAYERDeprecated: The number of highest layer to be used in routing.
(Default: 6)
GLB_RT_CLOCK_MINLAYERDeprecated: The number of lowest layer to be used in routing the clock net.
(Default: GLB_RT_MINLAYER)
GLB_RT_CLOCK_MAXLAYERDeprecated: The number of highest layer to be used in routing the clock net.
(Default: GLB_RT_MAXLAYER)

Removed

VariableDescription
GLB_RT_UNIDIRECTIONALRemoved: Allow unidirectional routing. 0 = false, 1 = true
(Default: 1)
GLB_RT_TILESRemoved: The size of the GCELL used by Fastroute during global routing.
(Default: 15)

RC Extraction

VariableDescription
SPEF_EXTRACTORSpecifies which spef extractor to use. Values: openrcx or (removed: def2spef).
(Default: openrcx)
RCX_MERGE_VIA_WIRE_RESSpecifies whether to merge the via resistance with the wire resistance or separate it from the wire resistance. 1 = Merge via resistance, 0 = Separate via resistance
(Default: 1)
SPEF_WIRE_MODELSpecifies the wire model used in SPEF extraction. Options are L or Pi
(Default: L)
SPEF_EDGE_CAP_FACTORSpecifies the edge capacitance factor used in SPEF extraction. Ranges from 0 to 1
(Default: 1)
RCX_CORNER_COUNTRemoved: Specifies the number of corners used during the parasitic extractions.
(Default: 1)
RCX_MAX_RESISTANCERemoved: Specifies the maximum threshold value for combining resistors in series. Resistors in series are combined up to this value. Units in ohms
(Default: 50)
RCX_COUPLING_THRESHOLDRemoved: Specifies the maximum threshold value for grounding coupling values. Coupling values below this threshold are grounded. Units in fF
(Default: 0.1)
RCX_CC_MODELRemoved: Specifies the maximum number of tracks on the same routing level. Coupling is calculated within the RCX_CC_MODEL distance.
(Default: 10)
RCX_CONTEXT_DEPTHRemoved: Specifies the number of levels considered when calculating the capacitance.
(Default: 5)

Magic

VariableDescription
MAGIC_PADA flag to pad the views generated by magic (.mag, .lef, .gds) with one site. 1 = Enabled, 0 = Disabled
(Default: 0 )
MAGIC_ZEROIZE_ORIGINA flag to move the layout such that it's origin in the lef generated by magic is 0,0. 1 = Enabled, 0 = Disabled
(Default: 1 )
MAGIC_GENERATE_GDSA flag to generate gds view via magic . 1 = Enabled, 0 = Disabled
(Default: 1 )
MAGIC_GENERATE_LEFA flag to generate lef view via magic . 1 = Enabled, 0 = Disabled
(Default: 1 )
MAGIC_GENERATE_MAGLEFA flag to generate maglef view via magic . 1 = Enabled, 0 = Disabled
(Default: 1 )
MAGIC_WRITE_FULL_LEFA flag to specify whether or not the output LEF should include all shapes inside the macro or an abstracted view of the macro lef view via magic . 1 = Full View, 0 = Abstracted View
(Default: 0 )
MAGIC_DRC_USE_GDSA flag to choose whether to run the magic DRC checks on GDS or not. If not, then the checks will be done on the DEF/LEF. 1 = GDS, 0 = DEF/LEF
(Default: 1 )
MAGIC_EXT_USE_GDSA flag to choose whether to run the magic extractions on GDS or DEF/LEF. If GDS was used Device Level LVS will be run. Otherwise, blackbox LVS will be run. 1 = GDS, 0 = DEF/LEF
(Default: 0 )
MAGIC_INCLUDE_GDS_POINTERSA flag to choose whether to include GDS pointers in the generated mag files or not. 1 = Enabled, 0 = Disabled
(Default: 0 )
MAGIC_DISABLE_HIER_GDSA flag to disable cif hier and array during GDS-II writing.* 1=Enabled <so this hier gds will be disabled>, 0=Disabled <so this hier gds will be enabled>.
(Default: 1 )
  • Tim Edwards's Explanation on disabling hier gds: The following is an explanation by Tim Edwards, provided in a slack thread, on how this affects the GDS writing process: “Magic can take a very long time writing out GDS while checking hierarchical interactions in a standard cell layout. If your design is all digital, I recommend using “gds *hier write disable” before “gds write” so that it does not try to resolve hierarchical interactions (since by definition, standard cells are designed to just sit next to each other without creating DRC issues). That can actually make the difference between a 20 hour GDS write and a 2 minute GDS write. For a standard cell design that takes up the majority of the user space, a > 24 hour write time (without disabling the hierarchy checks) would not surprise me.”

LVS

VariableDescription
LVS_INSERT_POWER_PINSEnables power pins insertion before running lvs. 1 = Enabled, 0 = Disabled
(Default: 1 )
LVS_CONNECT_BY_LABELEnables connections by label in LVS by skipping extract unique in magic extractions.
Default: 0
YOSYS_REWRITE_VERILOGEnables yosys to rewrite the verilog before LVS producing a canonical verilog netlist with verbose wire declarations. This flag will be ignored if LEC_ENABLE is 1, and it will be rewritten anyways. 1 = Enabled, 0 = Disabled
(Default: 0 )

Misc

VariableDescription
PDKSpecifies the process design kit (PDK).
(Default: sky130A )
STD_CELL_LIBRARYSpecifies the standard cell library to be used under the specified PDK.
(Default: sky130_fd_sc_hd )
STD_CELL_LIBRARY_OPTSpecifies the standard cell library to be used during resizer optimizations.
(Default: $STD_CELL_LIBRARY )
PDK_ROOTSpecifies the folder path of the PDK. It searches for a config.tcl in $PDK_ROOT/$PDK/libs.tech/openlane/ directory and at least have one standard cell library config defined in $PDK_ROOT/$PDK/libs.tech/openlane/$STD_CELL_LIBRARY.
CELL_PADCell padding; increases the width of cells.
(Default: 4 microns -- 4 sites)
DIODE_PADDINGDiode cell padding; increases the width of diode cells during placement checks.
(Default: 2 microns -- 2 sites)
MERGED_LEF_UNPADDEDPoints to merged_unpadded.lef by default. it contains the technology LEF for the used STD_CELL_LIBRARY merged with the LEF file for all the cells.
MERGED_LEFpoints to merged.lef, which is merged_unpadded.lef but with cell padding. This is controlled by CELL_PAD.
NO_SYNTH_CELL_LISTSpecifies the file that contains the don‘t-use-cell-list to be excluded from the liberty file during synthesis. If it’s not defined, this path is searched $::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells and if it's not found, then the original liberty will be used as is.
DRC_EXCLUDE_CELL_LISTSpecifies the file that contains the don‘t-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it’s not defined, this path is searched $::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells and if it's not found, then the original liberty will be used as is. In other words, DRC_EXCLUDE_CELL_LIST contain the only excluded cell list in timing optimizations.
EXTRA_LEFSSpecifies LEF files of pre-hardened macros to be merged in the design currently getting hardened
EXTRA_GDS_FILESSpecifies GDS files of pre-hardened macros to be merged in the design currently getting hardened
SAVE_FINAL_VIEWSSpecifies whether OpenLane should save all final views to a specific folder or not. (Default: 0)
TEST_MISMATCHESTest for mismatches between the OpenLane tool versions and the current environment. all tests all mismatches. tools tests all except the PDK. pdk only tests the PDK. none disables the check.
(Default: all)
QUIT_ON_MISMATCHESWhether to halt the flow execution or not if mismatches are found. (Default: 1)

Flow control

VariableDescription
USE_GPIO_PADSDecides whether or not to use the gpio pads in routing by merging their LEF file set in ::env(USE_GPIO_ROUTING_LEF) and blackboxing their verilog modules set in ::env(GPIO_PADS_VERILOG). 1=Enabled, 0=Disabled.
(Default: 0)
LEC_ENABLEEnables logic verification using yosys, for comparing each netlist at each stage of the flow with the previous netlist and verifying that they are logically equivalent. Warning: this will increase the runtime significantly. 1 = Enabled, 0 = Disabled
(Default: 0)
RUN_ROUTING_DETAILEDEnables detailed routing. 1 = Enabled, 0 = Disabled
(Default: 1)
RUN_LVSEnables running LVS. 1 = Enabled, 0 = Disabled
(Default: 1)
PRIMARY_SIGNOFF_TOOLDetermines whether magic or klayout is the primary signoff tool.
(Default: magic)
RUN_MAGICEnables running magic and GDSII streaming. 1 = Enabled, 0 = Disabled
(Default: 1)
RUN_MAGIC_DRCEnables running magic DRC on GDS-II produced by magic. 1 = Enabled, 0 = Disabled
(Default: 1)
RUN_KLAYOUTEnables running Klayout and GDSII streaming. 1 = Enabled, 0 = Disabled
(Default: 1)
RUN_KLAYOUT_DRCEnables running Klayout DRC on GDS-II produced by magic. 1 = Enabled, 0 = Disabled
(Default: 0)
KLAYOUT_DRC_KLAYOUT_GDSEnables running Klayout DRC on GDS-II produced by Klayout. 1 = Enabled, 0 = Disabled
(Default: 0)
RUN_KLAYOUT_XOREnables running Klayout XOR on 2 GDS-IIs, the defaults are the one produced by magic vs the one produced by klayout. 1 = Enabled, 0 = Disabled
(Default: 1)
KLAYOUT_XOR_GDSIf RUN_KLAYOUT_XOR is enabled, this will enable producing a GDS output from the XOR along with it's PNG export. 1 = Enabled, 0 = Disabled
(Default: 1)
KLAYOUT_XOR_XMLIf RUN_KLAYOUT_XOR is enabled, this will enable producing an XML output from the XOR. 1 = Enabled, 0 = Disabled
(Default: 1)
TAKE_LAYOUT_SCROTEnables running Klayout to take a PNG screenshot of the produced layout (currently configured to run on the results of each stage).1 = Enabled, 0 = Disabled
(Default: 0)
TAP_DECAP_INSERTIONEnables tap and decap cells insertion after floorplanning (if enabled) .1 = Enabled, 0 = Disabled
(Default: 1)
DIODE_INSERTION_STRATEGYSpecifies the insertion strategy of diodes to be used in the flow. 0 = No diode insertion, 1 = Spray diodes, 2 = insert fake diodes and replace them with real diodes if needed. 3= use FastRoute Antenna Avoidance flow, 4 = Use Sylvian's Custom Script for diode insertion on design pins and smartly inserting needed diodes inside the design, 5 = a mix of strategy 2 and 4.
(Default: 3)
WIDEN_SITESpecifies the new virtual width of the site to be used in all stages up to diode insertion, then switched back to the original site width. It can be either a factor or an absolute value controlled by WIDEN_SITE_IS_FACTOR
(Default: 1)
WIDEN_SITE_IS_FACTORSpecifies whether the given WIDEN_SITE should be treated as a factor or an absolute value. 0 = absolute, 1 = factor
(Default: 1)
USE_ARC_ANTENNA_CHECKSpecifies whether to use the openroad ARC antenna checker or magic antenna checker. 0=magic antenna checker, 1=ARC OR antenna checker
(Default: 1)
RUN_SPEF_EXTRACTIONSpecifies whether or not to run SPEF extraction on the routed DEF. 1=enabled 0=disabled
Default: 1
GENERATE_FINAL_SUMMARY_REPORTSpecifies whether or not to generate a final summary report after the run is completed. Check command generate_final_summary_report. 1=enabled 0=disabled
Default: 1
MAGIC_CONVERT_DRC_TO_RDBSpecifies whether or not generate a Calibre RDB out of the magic.drc report. Result is saved in <run_path>/results/magic/. 1=enabled 0=disabled
Default: 1
RUN_CVCRuns CVC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. Thus, it controls the command run_lef_cvc. 1=Enabled, 0=Disabled.
Default: 1

Checkers

VariableDescription
CHECK_UNMAPPED_CELLSChecks if there are unmapped cells after synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled
(Default: 1)
CHECK_ASSIGN_STATEMENTSChecks for assign statement in the generated gate level netlist and aborts of any was found.1 = Enabled, 0 = Disabled
(Default: 0)
QUIT_ON_TR_DRCChecks for DRC violations after routing and exits the flow if any was found. 1 = Enabled, 0 = Disabled
(Default: 1)
QUIT_ON_MAGIC_DRCChecks for DRC violations after magic DRC is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled
(Default: 1)
QUIT_ON_ILLEGAL_OVERLAPSChecks for illegal overlaps during magic extraction. In some cases, these imply existing undetected shorts in the design. It also exits the flow if any was found. 1 = Enabled, 0 = Disabled
(Default: 1)
QUIT_ON_LVS_ERRORChecks for LVS errors after netgen LVS is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled
(Default: 1)