commit	e6a8abc243bd11eabf0712ce709a64879b7cebfb	[log] [tgz]
author	ranan-usp <oe23ranan@ec.usp.ac.jp>	Mon May 23 07:01:33 2022 +0900
committer	ranan-usp <oe23ranan@ec.usp.ac.jp>	Mon May 23 07:01:33 2022 +0900
tree	95ea718a27681904064d1b1e53490a211d49cb2a
parent	473abe5332a4bf67756a220f8e710c3bdfaba7f9 [diff]

update

caravel[diff]
openlane/.flake8[Added - diff]
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openlane/CONTRIBUTING.md[Added - diff]
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openlane/LICENSE[Added - diff]
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openlane/dependencies/verify_versions.py[Added - diff]
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openlane/designs/APU/config.tcl[Added - diff]
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openlane/designs/aes_core/sky130A_sky130_fd_sc_hd_config.tcl[Added - diff]
openlane/designs/aes_core/sky130A_sky130_fd_sc_hdll_config.tcl[Added - diff]
openlane/designs/aes_core/sky130A_sky130_fd_sc_hs_config.tcl[Added - diff]
openlane/designs/aes_core/sky130A_sky130_fd_sc_ls_config.tcl[Added - diff]
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openlane/designs/blabla/sky130A_sky130_fd_sc_hdll_config.tcl[Added - diff]
openlane/designs/blabla/sky130A_sky130_fd_sc_hs_config.tcl[Added - diff]
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openlane/designs/caravel_upw/config.tcl[Added - diff]
openlane/designs/caravel_upw/macro.cfg[Added - diff]
openlane/designs/caravel_upw/macros/user_proj_example.gds[Added - diff]
openlane/designs/caravel_upw/macros/user_proj_example.lef[Added - diff]
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openlane/designs/caravel_upw/macros/user_proj_example2.lef[Added - diff]
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openlane/designs/caravel_upw/src/user_proj_example.v[Added - diff]
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openlane/designs/caravel_upw/src/user_project_wrapper.v[Added - diff]
openlane/designs/gcd/asap7_asap7sc7p5t_config.tcl[Added - diff]
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openlane/designs/inverter/src/inverter.v[Added - diff]
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openlane/designs/manual_macro_placement_test/macro_placement.cfg[Added - diff]
openlane/designs/manual_macro_placement_test/macros/gds/spm.gds[Added - diff]
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openlane/designs/manual_macro_placement_test/sky130A_sky130_fd_sc_hs_config.tcl[Added - diff]
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openlane/designs/picorv32a/sky130A_sky130_fd_sc_hd_config.tcl[Added - diff]
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openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hd_config.tcl[Added - diff]
openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hdll_config.tcl[Added - diff]
openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_hs_config.tcl[Added - diff]
openlane/designs/usb_cdc_core/sky130A_sky130_fd_sc_ls_config.tcl[Added - diff]
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openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_hd_config.tcl[Added - diff]
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openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ls_config.tcl[Added - diff]
openlane/designs/wbqspiflash/sky130A_sky130_fd_sc_ms_config.tcl[Added - diff]
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openlane/designs/xtea/sky130A_sky130_fd_sc_hd_config.tcl[Added - diff]
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openlane/designs/y_huff/sky130A_sky130_fd_sc_hd_config.tcl[Added - diff]
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openlane/designs/y_huff/sky130A_sky130_fd_sc_hs_config.tcl[Added - diff]
openlane/designs/y_huff/sky130A_sky130_fd_sc_ls_config.tcl[Added - diff]
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openlane/scripts/klayout/run_drc.sh[Added - diff]
openlane/scripts/klayout/scrotLayout.py[Added - diff]
openlane/scripts/klayout/scrotLayout.sh[Added - diff]
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openlane/scripts/libtrim.py[Added - diff]
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openlane/scripts/manual_macro_place.py[Added - diff]
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openlane/scripts/most_recent_run.py[Added - diff]
openlane/scripts/new_tracks.py[Added - diff]
openlane/scripts/obs.py[Added - diff]
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openlane/scripts/openroad/basic_mp.tcl[Added - diff]
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openlane/scripts/openroad/sta.tcl[Added - diff]
openlane/scripts/openroad/sta_multi_corner.tcl[Added - diff]
openlane/scripts/openroad/tapcell.tcl[Added - diff]
openlane/scripts/openroad/write_verilog.tcl[Added - diff]
openlane/scripts/or_issue.py[Added - diff]
openlane/scripts/padframe_extract_area.sh[Added - diff]
openlane/scripts/padframe_generator.py[Added - diff]
openlane/scripts/padringer.py[Added - diff]
openlane/scripts/parse_klayout_xor_log.py[Added - diff]
openlane/scripts/pdk-linker.py[Added - diff]
openlane/scripts/place_diodes.py[Added - diff]
openlane/scripts/power_route.py[Added - diff]
openlane/scripts/random_place.py[Added - diff]
openlane/scripts/rectify.py[Added - diff]
openlane/scripts/reorg_reports.sh[Added - diff]
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openlane/scripts/replicate_design_configs.py[Added - diff]
openlane/scripts/report/get_best.py[Added - diff]
openlane/scripts/report/get_file_name.py[Added - diff]
openlane/scripts/report/report.py[Added - diff]
openlane/scripts/report/report_routing.py[Added - diff]
openlane/scripts/set_layer_tracks.py[Added - diff]
openlane/scripts/simple_cts.py[Added - diff]
openlane/scripts/synth_exp/analyze.py[Added - diff]
openlane/scripts/synth_exp/table.css[Added - diff]
openlane/scripts/synth_exp/utils.js[Added - diff]
openlane/scripts/tcl_commands/README.md[Added - diff]
openlane/scripts/tcl_commands/all.tcl[Added - diff]
openlane/scripts/tcl_commands/checkers.tcl[Added - diff]
openlane/scripts/tcl_commands/cts.tcl[Added - diff]
openlane/scripts/tcl_commands/cvc.tcl[Added - diff]
openlane/scripts/tcl_commands/eco.tcl[Added - diff]
openlane/scripts/tcl_commands/floorplan.tcl[Added - diff]
openlane/scripts/tcl_commands/init_design.tcl[Added - diff]
openlane/scripts/tcl_commands/klayout.tcl[Added - diff]
openlane/scripts/tcl_commands/lvs.tcl[Added - diff]
openlane/scripts/tcl_commands/magic.tcl[Added - diff]
openlane/scripts/tcl_commands/pkgIndex.tcl[Added - diff]
openlane/scripts/tcl_commands/placement.tcl[Added - diff]
openlane/scripts/tcl_commands/refresh.tcl[Added - diff]
openlane/scripts/tcl_commands/routing.tcl[Added - diff]
openlane/scripts/tcl_commands/sta.tcl[Added - diff]
openlane/scripts/tcl_commands/synthesis.tcl[Added - diff]
openlane/scripts/topModuleGen/README.md[Added - diff]
openlane/scripts/topModuleGen/src/TopModuleGen.py[Added - diff]
openlane/scripts/topModuleGen/src/padHelper.py[Added - diff]
openlane/scripts/tr_drc_to_klayout_drc.py[Added - diff]
openlane/scripts/update_design_configs.py[Added - diff]
openlane/scripts/utils/__init__.py[Added - diff]
openlane/scripts/utils/deflef_utils.tcl[Added - diff]
openlane/scripts/utils/fake_display_buffer.tcl[Added - diff]
openlane/scripts/utils/pkgIndex.tcl[Added - diff]
openlane/scripts/utils/utils.py[Added - diff]
openlane/scripts/utils/utils.tcl[Added - diff]
openlane/scripts/widen_site_lef.py[Added - diff]
openlane/scripts/write_powered_def.py[Added - diff]
openlane/scripts/write_runtime.py[Added - diff]
openlane/scripts/yosys/logic_equiv_check.tcl[Added - diff]
openlane/scripts/yosys/rewrite_verilog.tcl[Added - diff]
openlane/scripts/yosys/synth.tcl[Added - diff]
openlane/scripts/yosys/synth_top.tcl[Added - diff]
openlane/scripts/zeroize_origin_lef.py[Added - diff]
openlane/tests/.gitignore[Added - diff]
openlane/tests/1007/.gitignore[Added - diff]
openlane/tests/1007/config.tcl[Added - diff]
openlane/tests/1007/hooks/post_run.py[Added - diff]
openlane/tests/1007/in.def[Added - diff]
openlane/tests/1007/interactive.tcl[Added - diff]
openlane/tests/892/Readme.txt[Added - diff]
openlane/tests/892/config.tcl[Added - diff]
openlane/tests/892/def_test.def[Added - diff]
openlane/tests/892/hooks/post_run.py[Added - diff]
openlane/tests/892/src/def_test.v[Added - diff]
openlane/tests/912/config.tcl[Added - diff]
openlane/tests/912/def_test.def[Added - diff]
openlane/tests/912/issue_regression.py[Added - diff]
openlane/tests/912/src[Added - diff]
openlane/tests/Readme.md[Added - diff]
verilog/rtl/my_design/count_monitor.v[Added - diff]
verilog/rtl/my_design/dff.v[Added - diff]
verilog/rtl/my_design/hold.v[Added - diff]
verilog/rtl/my_design/main.v[Added - diff]
verilog/rtl/my_design/qout.v[Added - diff]
verilog/rtl/my_design/sample/sample.o[Added - diff]
verilog/rtl/my_design/sample/sample.v[Added - diff]
verilog/rtl/my_design/sample/tb_Prpg10.vcd[Added - diff]
verilog/rtl/my_design/sample/tb_sample.v[Added - diff]
verilog/rtl/my_design/tb_count_monitor.o[Added - diff]
verilog/rtl/my_design/tb_count_monitor.vcd[Added - diff]
verilog/rtl/my_design/tb_counter_monitor.v[Added - diff]
verilog/rtl/my_design/tb_dff.o[Added - diff]
verilog/rtl/my_design/tb_dff.v[Added - diff]
verilog/rtl/my_design/tb_dff.vcd[Added - diff]
verilog/rtl/my_design/tb_main.o[Added - diff]
verilog/rtl/my_design/tb_main.v[Added - diff]
verilog/rtl/my_design/tb_main.vcd[Added - diff]
xschem/analog_switch.sch[Added - diff]
xschem/analog_switch.spice[Added - diff]
xschem/analog_switch.sym[Added - diff]
xschem/bsim4v5.out[diff]
xschem/cap16.sch[Added - diff]
xschem/cap16.sym[Added - diff]
xschem/cap2.sch[Added - diff]
xschem/cap2.sym[Added - diff]
xschem/cap32.sch[Added - diff]
xschem/cap32.sym[Added - diff]
xschem/cap4.sch[Added - diff]
xschem/cap4.sym[Added - diff]
xschem/cap8.sch[Added - diff]
xschem/cap8.sym[Added - diff]
xschem/dacpassgate.sch[Added - diff]
xschem/df4.sch[Added - diff]
xschem/df4.sym[Added - diff]
xschem/my_cdac.sch[Added - diff]
xschem/my_cdac.spice[Added - diff]
xschem/my_cdac.sym[Added - diff]
xschem/my_comparator.sym[diff]
xschem/my_df.sch[Added - diff]
xschem/my_df.sym[Added - diff]
xschem/my_df2.sch[Added - diff]
xschem/my_df2.sym[Added - diff]
xschem/my_df3.sch[Added - diff]
xschem/my_df3.sym[Added - diff]
xschem/my_dynamic_comp.sym[Added - diff]
xschem/my_dynamic_comparator2.sch[Added - diff]
xschem/my_dynamic_comparator2.sym[Added - diff]
xschem/my_sar_logic.sch[Added - diff]
xschem/my_sar_logic.sym[Added - diff]
xschem/my_sr_latch.sch[Added - diff]
xschem/not.sch[Added - diff]
xschem/not.sym[Added - diff]
xschem/tb_saradc.raw[Added - diff]
xschem/tb_saradc.sch[Added - diff]
xschem/tb_saradc.spice[Added - diff]
xschem/tb_saradc2.raw[Added - diff]
xschem/tb_switch.sch[Added - diff]
xschem/tb_switch.spice[Added - diff]
xschem/transmission_gate.sch[Added - diff]
xschem/transmission_gate.sym[Added - diff]
xschem/xschemrc[diff]

523 files changed

tree: 95ea718a27681904064d1b1e53490a211d49cb2a

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.