unwanted file deleted
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..c4985e9
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,4 @@
+precheck_results
+*/tmp
+*/*/tmp
+*.vcd
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
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diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..d97988b
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,177 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CARAVEL_ROOT?=$(PWD)/caravel
+PRECHECK_ROOT?=${HOME}/mpw_precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_BRANCH := main
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_BRANCH := master
+endif
+
+# Install caravel as submodule, (1): submodule, (0): clone
+SUBMODULE?=1
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/%
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+ cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ifeq ($(SUBMODULE),1)
+ @echo "Installing $(CARAVEL_NAME) as a submodule.."
+# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
+ $(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
+ @if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
+ @git submodule update --init
+ @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
+ $(MAKE) simlink
+else
+ @echo "Installing $(CARAVEL_NAME).."
+ @git clone $(CARAVEL_REPO) $(CARAVEL_ROOT)
+ @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
+endif
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ mkdir -p openlane
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ifeq ($(SUBMODULE),1)
+ @git submodule update --init --recursive
+ cd $(CARAVEL_ROOT) && \
+ git checkout $(CARAVEL_BRANCH) && \
+ git pull
+else
+ cd $(CARAVEL_ROOT)/ && \
+ git checkout $(CARAVEL_BRANCH) && \
+ git pull
+endif
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ifeq ($(SUBMODULE),1)
+ git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)"
+ git add .gitmodules
+ git submodule deinit -f $(CARAVEL_ROOT)
+ git rm --cached $(CARAVEL_ROOT)
+ rm -rf .git/modules/$(CARAVEL_NAME)
+ rm -rf $(CARAVEL_ROOT)
+else
+ rm -rf $(CARAVEL_ROOT)
+endif
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone https://github.com/efabless/mpw_precheck.git --depth=1 $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-precheck check-pdk check-caravel
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT)"
+
+# Install PDK using OL's Docker Image
+.PHONY: pdk-nonnative
+pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks
+ docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
+
+# Clean
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/README.md b/README.md
index ea75bbf..d834db6 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,159 @@
-# caravel_avsdopamp_3v3_sky130_v2
-OPAMP project with caravel wrapper
+# Caravel Analog User
+
+
+# Two Stage CMOS OPAMP with Frequency Compensation
+CMOS OPAMP is Basic building block of analog and Mixed signal circuits. It is used in many applications such as ADC, DAC and Instrumentation Amplifier.
+It basically amplifies the difference between two input signals.
+# Instumentation Amplifier: An Application Of CMOS OPAMP
+<img width="661" alt="Instru-Amp" src="https://user-images.githubusercontent.com/88900482/130283601-f840c5fe-f285-4f46-92b2-f93b9e5e9480.PNG">
+
+# Performance parameters of Bandgap Reference IP
+<img width="515" alt="Perfor-para" src="https://user-images.githubusercontent.com/88900482/130284019-6360918c-f9c1-4a17-8416-c410cce3271c.PNG">
+
+# Block Diagram of CMOS OPAMP IP
+<img width="345" alt="OPAMP-Block Dig" src="https://user-images.githubusercontent.com/88900482/130284202-28dce16c-5f7b-45a7-916d-11d1ce77082a.PNG">
+
+# Downloading the files on your System
+The files from this repository can be downloaded and used by the following commands :-
+
+sudo apt install -y git
+
+git clone https://github.com/MadhuriKadam9/Cmosopamp.git
+
+
+# Pre-Layout Simulation of CMOS OPAMP IP
+## 1. Schematic of CMOS OPAMP IP designd in eSim
+Install the eSim tool using this https://esim.fossee.in/downloads
+Note: You can also refer to the eSim Spoken Tutorialwebsite https://spoken-tutorial.org/tutorial-search/?search_foss=eSim
+
+<img width="573" alt="Combined_ckt" src="https://user-images.githubusercontent.com/88900482/130285141-6a033032-0108-4130-aff0-3394034cd5aa.png">
+
+## 2. Ngspice Simulation Results
+Ngspice is an open source mixed-signal circuit simulator. To install Ngspice on Ubuntu, open terminal window and type :-
+
+sudo apt-get install -y ngspice
+
+After successful installation, to invoke Ngspice type the following command on the terminal window.
+
+ngspice "circuit file to be simulated"
+
+### A) Transient Response of Two stage OPAMP
+To get the transient response of two stage OPAMP run the following file in ngspice: Opamp_TRAN.cir.out
+
+<img width="921" alt="Vin-tran" src="https://user-images.githubusercontent.com/88900482/130285858-8b30650b-a886-4e35-972b-5ece61a7e057.PNG">
+
+
+<img width="945" alt="Vout-tran" src="https://user-images.githubusercontent.com/88900482/130286285-eb1cbb5c-641b-47d3-a2c8-aef8183c81c9.PNG">
+
+### B) AC Response of Two stage OPAMP
+To get the transient response of two stage OPAMP run the following file in ngspice: Opamp_AC.cir.out
+
+Magnitude Response Vout-dB i.e. ADM
+<img width="937" alt="vout-ac-magres" src="https://user-images.githubusercontent.com/88900482/130286370-f3c78ccf-c60a-47b1-aaed-abaa6ee4a8da.PNG">
+
+Phase Response Vout-Ph
+<img width="930" alt="vout-ac-phres" src="https://user-images.githubusercontent.com/88900482/130286446-a1fc6d44-0ce5-4ee9-9e3a-4a0a2d990779.PNG">
+
+Phase Margin Plot of Vout
+<img width="930" alt="vout-ac-pm (2)" src="https://user-images.githubusercontent.com/88900482/130286501-edc307f8-15bb-4a09-b437-c6735b6a2be5.PNG">
+
+# Layout with Magic Tool
+## MAGIC Tool installation:
+The Layout for the circuit was done using Magic Layout editor tool. To observe the layout, install magic using the following commands :-
+
+sudo wget "http://opencircuitdesign.com/magic/archive/magic-8.3.122.tgz"
+
+tar -xvzf magic-8.3.122.tgz
+
+cd magic-8.3.122
+
+sudo ./configure
+
+sudo make
+
+sudo make install
+
+
+## Resistor
+After successful installation, To open Resistor layout in magic type following in terminal window:-
+
+cd Cmosopamp/OPAMP_Layout_Files/
+
+magic -T ../libs/sky130A.tech res.mag
+
+
+<img width="258" alt="Resistor" src="https://user-images.githubusercontent.com/88900482/130286663-1837abf3-2aca-4d53-a730-280819ec12bf.PNG">
+
+## Capacitor
+To see capacitor layout give command magic -T ../libs/sky130A.tech mimcapt.mag
+
+<img width="277" alt="Mimcap" src="https://user-images.githubusercontent.com/88900482/130286698-14e366b5-dc1c-45ad-94a3-79a59edd8f5d.PNG">
+
+
+## Single stage OPAMP
+To see opamp1 layout give command magic -T ../libs/sky130A.tech opamp1.mag
+<img width="553" alt="OPAMP1" src="https://user-images.githubusercontent.com/88900482/130286722-b432a8a2-be15-4cbd-bd4b-abca911322af.PNG">
+
+## Dual Stage OPAMP
+To see opamp2 layout give command magic -T ../libs/sky130A.tech opamp2.mag
+<img width="730" alt="Opamp2" src="https://user-images.githubusercontent.com/88900482/130286739-103c6a5f-bd6a-4d54-ab49-cc80a09e2f53.PNG">
+
+
+# Post-Layout Simulation of CMOS OPAMP IP
+## Single Stage OPAMP
+### Transient Response
+Run the following file in ngspice: opamp1_tran.spice
+
+1) Vinp, Vinm Waveforms
+<img width="868" alt="Vin-tran" src="https://user-images.githubusercontent.com/88900482/130287209-24711fbb-40fe-4797-a4ff-fcc74efb5505.PNG">
+
+2) Vo waveform
+<img width="875" alt="Vo-trans" src="https://user-images.githubusercontent.com/88900482/130287239-f1b2c2e3-7a19-42c9-8544-f86af1b419c6.PNG">
+
+### AC Response
+Run the following file in ngspice: opamp1_ac.spice
+
+1) Magnitude Response i.e. VodB
+<img width="878" alt="VOdb-AC" src="https://user-images.githubusercontent.com/88900482/130287350-8175c75a-4065-4f4d-ab6b-f6c3e8ab263d.PNG">
+
+2) Phase Response i.e Vo-ph
+<img width="876" alt="VOph-AC" src="https://user-images.githubusercontent.com/88900482/130287374-d6f46cc4-0f6e-4399-a0eb-017c5a781fe3.PNG">
+
+3) All AC Response of OPAMP1
+<img width="878" alt="opamp1-AC-Resp" src="https://user-images.githubusercontent.com/88900482/130287970-b1949a3f-873d-4ea8-90af-07356268da8b.PNG">
+
+## Dual Stage OPAMP
+### Transient Response
+Run the following file in ngspice: opamp2_tran.spice
+
+1) Vinp, Vinm Waveforms
+<img width="868" alt="Vin-tran" src="https://user-images.githubusercontent.com/88900482/130287567-9cfc3728-4d51-4f84-a56c-f71e3167649c.PNG">
+
+2) Vout waveform
+<img width="878" alt="Vout-tran" src="https://user-images.githubusercontent.com/88900482/130287597-8f22aa3b-eda8-46aa-95bb-41b2ed678176.PNG">
+
+### AC Response
+Run the following file in ngspice: opamp2_ac.spice
+
+1) Magnitude Response i.e. VodB
+<img width="876" alt="opamp2_AC-mag_res" src="https://user-images.githubusercontent.com/88900482/130287719-117cb295-2d9b-4cad-82f7-2fb370f8bbc7.PNG">
+
+2) Phase Response Vout-ph
+<img width="875" alt="opamp2-AC-Ph-Res" src="https://user-images.githubusercontent.com/88900482/130287767-eff4a4db-afab-443c-a475-ad30fdbd437d.PNG">
+
+3) Phase Margin Plot Vout-PM
+<img width="877" alt="opamp2-AC-PM" src="https://user-images.githubusercontent.com/88900482/130287784-ea5c4ec1-8b6e-4697-9691-99effbd20cf7.PNG">
+
+4) All AC Response
+<img width="914" alt="Opamp2_AC_Res" src="https://user-images.githubusercontent.com/88900482/130287875-db3e9379-5af6-4ca3-85f8-f5bfe4da26e4.PNG">
+
+# Further Work
+From the postlayout transient response of Two stage opamp it can be obsereved that the negative peak of vout is flattened. This results in reduction of overall voltage swing at the output. So with proper design this problem can be solved.
+
+# Contributors
+1) Mrs. Madhuri H. Kadam, Assistant Professor, Shree L. R. Tiwari college of Engineering, Mira Rd (E) - madhurib.saksham@gmail.com
+2) Kunal Ghosh, Co-Founder of VLSI System Design (VSD) Corp. Pvt. Ltd. - kunalpghosh@gmail.com
+
+# Acknowledgements
+Kunal Ghosh, Co-Founder of VLSI System Design (VSD) Corp. Pvt. Ltd. - kunalpghosh@gmail.com
+
diff --git a/caravel/LICENSE b/caravel/LICENSE
new file mode 100644
index 0000000..d645695
--- /dev/null
+++ b/caravel/LICENSE
@@ -0,0 +1,202 @@
+
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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diff --git a/caravel/Makefile b/caravel/Makefile
new file mode 100644
index 0000000..f5b7702
--- /dev/null
+++ b/caravel/Makefile
@@ -0,0 +1,675 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# cannot commit files larger than 100 MB to GitHub
+FILE_SIZE_LIMIT_MB = 100
+
+# Commands to be used to compress/uncompress files
+# they must operate **in place** (otherwise, modify the target to delete the
+# intermediate file/archive)
+COMPRESS ?= gzip -n --best
+UNCOMPRESS ?= gzip -d
+ARCHIVE_EXT ?= gz
+
+# The following variables are to build static pattern rules
+
+# Needed to rebuild archives that were previously split
+SPLIT_FILES := $(shell find . -type f -name "*.$(ARCHIVE_EXT).00.split")
+SPLIT_FILES_SOURCES := $(basename $(basename $(basename $(SPLIT_FILES))))
+
+# Needed to uncompress the existing archives
+ARCHIVES := $(shell find . -type f -name "*.$(ARCHIVE_EXT)")
+ARCHIVE_SOURCES := $(basename $(ARCHIVES))
+
+# Needed to compress and split files/archives that are too large
+LARGE_FILES := $(shell find ./gds -type f -name "*.gds")
+LARGE_FILES += $(shell find . -type f -size +$(FILE_SIZE_LIMIT_MB)M -not -path "./.git/*" -not -path "./gds/*" -not -path "./openlane/*")
+LARGE_FILES_GZ := $(addsuffix .$(ARCHIVE_EXT), $(LARGE_FILES))
+LARGE_FILES_GZ_SPLIT := $(addsuffix .$(ARCHIVE_EXT).00.split, $(LARGE_FILES))
+# consider splitting existing archives
+LARGE_FILES_GZ_SPLIT += $(addsuffix .00.split, $(ARCHIVES))
+
+# Caravel Root (Default: pwd)
+# Need to be overwritten if running the makefile from UPRJ_ROOT,
+# If caravel is sub-moduled in the user project, run export CARAVEL_ROOT=$(pwd)/caravel
+CARAVEL_ROOT ?= $(shell pwd)
+
+# User project root
+UPRJ_ROOT ?= $(shell pwd)
+
+# Build tasks such as make ship, make generate_fill, make set_user_id, make final run in the foreground (1) or background (0)
+FOREGROUND ?= 1
+
+# PDK setup configs
+THREADS ?= $(shell nproc)
+STD_CELL_LIBRARY ?= sky130_fd_sc_hd
+SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
+IO_LIBRARY ?= sky130_fd_io
+PRIMITIVES_LIBRARY ?= sky130_fd_pr
+SKYWATER_COMMIT ?= c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+OPEN_PDKS_COMMIT ?= 6c05bc48dc88784f9d98b89d6791cdfd91526676
+INSTALL_SRAM ?= disabled
+
+.DEFAULT_GOAL := ship
+# We need portable GDS_FILE pointers...
+.PHONY: ship
+ship: check-env uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ @echo "Running make ship in the foreground..."
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __ship
+ @echo "Make ship completed." 2>&1 | tee -a ./signoff/build/make_ship.out
+else
+ @echo "Running make ship in the background..."
+ nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __ship >/dev/null 2>&1 &
+ tail -f signoff/build/make_ship.out
+ @echo "Make ship completed." 2>&1 | tee -a ./signoff/build/make_ship.out
+endif
+
+__ship:
+ @echo "###############################################"
+ @echo "Generating Caravel GDS (sources are in the 'gds' directory)"
+ @sleep 1
+#### Runs from the CARAVEL_ROOT mag directory
+ @echo "\
+ random seed `$(CARAVEL_ROOT)/scripts/set_user_id.py -report`; \
+ drc off; \
+ crashbackups stop; \
+ gds readonly true; \
+ gds rescale false; \
+ cif *hier write disable; \
+ cif *array write disable; \
+ gds read $(UPRJ_ROOT)/gds/user_project_wrapper.gds; \
+ load caravel -dereference;\
+ cellname list filepath user_id_programming $(UPRJ_ROOT)/mag;\
+ cellname list filepath user_id_textblock $(UPRJ_ROOT)/mag;\
+ flush user_id_programming;\
+ flush user_id_textblock;\
+ select top cell;\
+ gds write $(UPRJ_ROOT)/gds/caravel.gds; \
+ exit;" > $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl
+### Runs from CARAVEL_ROOT
+ @mkdir -p ./signoff/build
+ @cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/sky130A magic -noc -dnull $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_ship.out
+### @rm $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl
+
+truck: check-env uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ @echo "Running make truck in the foreground..."
+ mkdir -p ./signoff
+ mkdir -p ./build
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __truck
+ @echo "Make truck completed." 2>&1 | tee -a ./signoff/build/make_truck.out
+else
+ @echo "Running make truck in the background..."
+ mkdir -p ./signoff
+ mkdir -p ./build
+ nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __truck >/dev/null 2>&1 &
+ tail -f signoff/build/make_truck.out
+ @echo "Make truck completed." 2>&1 | tee -a ./signoff/build/make_truck.out
+endif
+
+__truck:
+ @echo "###############################################"
+ @echo "Generating Caravan GDS (sources are in the 'gds' directory)"
+ @sleep 1
+#### Runs from the CARAVEL_ROOT mag directory
+ @echo "\
+ random seed `$(CARAVEL_ROOT)/scripts/set_user_id.py -report`; \
+ drc off; \
+ crashbackups stop; \
+ gds readonly true; \
+ gds rescale false; \
+ cif *hier write disable; \
+ cif *array write disable; \
+ gds read $(UPRJ_ROOT)/gds/user_analog_project_wrapper.gds; \
+ load caravan -dereference;\
+ cellname list filepath user_id_programming $(UPRJ_ROOT)/mag;\
+ cellname list filepath user_id_textblock $(UPRJ_ROOT)/mag;\
+ flush user_id_programming;\
+ flush user_id_textblock;\
+ select top cell;\
+ gds write $(UPRJ_ROOT)/gds/caravan.gds; \
+ exit;" > $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl
+### Runs from CARAVEL_ROOT
+ @mkdir -p ./signoff/build
+ @cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/sky130A magic -noc -dnull $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_truck.out
+### @rm $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl
+
+.PHONY: clean
+clean:
+ cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \
+ $(MAKE) -j$(THREADS) clean
+ cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \
+ $(MAKE) -j$(THREADS) clean
+
+
+.PHONY: verify
+verify:
+ cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \
+ $(MAKE) -j$(THREADS) all
+ cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \
+ $(MAKE) -j$(THREADS) all
+
+
+
+#####
+$(LARGE_FILES_GZ): %.$(ARCHIVE_EXT): %
+ @if ! [ $(suffix $<) = ".$(ARCHIVE_EXT)" ]; then\
+ $(COMPRESS) $< > /dev/null &&\
+ echo "$< -> $@";\
+ fi
+
+$(LARGE_FILES_GZ_SPLIT): %.$(ARCHIVE_EXT).00.split: %.$(ARCHIVE_EXT)
+ @if [ -n "$$(find "$<" -prune -size +$(FILE_SIZE_LIMIT_MB)M)" ]; then\
+ split $< -b $(FILE_SIZE_LIMIT_MB)M $<. -d &&\
+ rm $< &&\
+ for file in $$(ls $<.*); do mv "$$file" "$$file.split"; done &&\
+ echo -n "$< -> $$(ls $<.*.split)" | tr '\n' ' ' && echo "";\
+ fi
+
+# This target compresses all files larger than $(FILE_SIZE_LIMIT_MB) MB
+.PHONY: compress
+compress: $(LARGE_FILES_GZ) $(LARGE_FILES_GZ_SPLIT)
+ @echo "Files larger than $(FILE_SIZE_LIMIT_MB) MBytes are compressed!"
+
+
+
+#####
+$(ARCHIVE_SOURCES): %: %.$(ARCHIVE_EXT)
+ @$(UNCOMPRESS) $<
+ @echo "$< -> $@"
+
+.SECONDEXPANSION:
+$(SPLIT_FILES_SOURCES): %: $$(sort $$(wildcard %.$(ARCHIVE_EXT).*.split))
+ @cat $? > $@.$(ARCHIVE_EXT)
+ @rm $?
+ @echo "$? -> $@.$(ARCHIVE_EXT)"
+ @$(UNCOMPRESS) $@.$(ARCHIVE_EXT)
+ @echo "$@.$(ARCHIVE_EXT) -> $@"
+
+
+.PHONY: uncompress
+uncompress: $(SPLIT_FILES_SOURCES) $(ARCHIVE_SOURCES)
+ @echo "All files are uncompressed!"
+
+# Needed for targets that are run from UPRJ_ROOT for which caravel isn't submoduled.
+.PHONY: uncompress-caravel
+uncompress-caravel:
+ cd $(CARAVEL_ROOT) && \
+ $(MAKE) uncompress
+
+# Digital Wrapper
+# verify that the wrapper was respected
+xor-wrapper: uncompress uncompress-caravel
+### first erase the user's user_project_wrapper.gds
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh gds/user_project_wrapper.gds 0 0 2920 3520
+### do the same for the empty wrapper
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh $(CARAVEL_ROOT)/gds/user_project_wrapper_empty.gds 0 0 2920 3520
+ mkdir -p signoff/user_project_wrapper_xor
+### XOR the two resulting layouts
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds \
+ user_project_wrapper user_project_wrapper.xor.xml
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds \
+ user_project_wrapper gds/user_project_wrapper.xor.gds > signoff/user_project_wrapper_xor/xor.log
+ rm $(CARAVEL_ROOT)/gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds
+ mv gds/user_project_wrapper.xor.gds gds/user_project_wrapper.xor.xml signoff/user_project_wrapper_xor
+ python $(CARAVEL_ROOT)/utils/parse_klayout_xor_log.py \
+ -l signoff/user_project_wrapper_xor/xor.log \
+ -o signoff/user_project_wrapper_xor/total.txt
+### screenshot the result for convenience
+ sh $(CARAVEL_ROOT)/utils/scrotLayout.sh \
+ $(PDK_ROOT)/sky130A/libs.tech/klayout/sky130A.lyt \
+ signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds
+ @cat signoff/user_project_wrapper_xor/total.txt
+
+# Analog Wrapper
+# verify that the wrapper was respected
+xor-analog-wrapper: uncompress uncompress-caravel
+### first erase the user's user_project_wrapper.gds
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh gds/user_analog_project_wrapper.gds 0 0 2920 3520 -8 -8
+### do the same for the empty wrapper
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty.gds 0 0 2920 3520 -8 -8
+ mkdir -p signoff/user_analog_project_wrapper_xor
+### XOR the two resulting layouts
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty_erased.gds gds/user_analog_project_wrapper_erased.gds \
+ user_analog_project_wrapper user_analog_project_wrapper.xor.xml
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty_erased.gds gds/user_analog_project_wrapper_erased.gds \
+ user_analog_project_wrapper gds/user_analog_project_wrapper.xor.gds > signoff/user_analog_project_wrapper_xor/xor.log
+ rm $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty_erased.gds gds/user_analog_project_wrapper_erased.gds
+ mv gds/user_analog_project_wrapper.xor.gds gds/user_analog_project_wrapper.xor.xml signoff/user_analog_project_wrapper_xor
+ python $(CARAVEL_ROOT)/utils/parse_klayout_xor_log.py \
+ -l signoff/user_analog_project_wrapper_xor/xor.log \
+ -o signoff/user_analog_project_wrapper_xor/total.txt
+### screenshot the result for convenience
+ sh $(CARAVEL_ROOT)/utils/scrotLayout.sh \
+ $(PDK_ROOT)/sky130A/libs.tech/klayout/sky130A.lyt \
+ signoff/user_analog_project_wrapper_xor/user_analog_project_wrapper.xor.gds
+ @cat signoff/user_analog_project_wrapper_xor/total.txt
+
+# LVS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./mag/tmp
+ echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+ addpath $(CARAVEL_ROOT)/subcells/simple_por/mag;\
+ addpath \$$PDKPATH/libs.ref/sky130_ml_xx_hd/mag;\
+ load $* -dereference;\
+ select top cell;\
+ foreach cell [cellname list children] {\
+ load \$$cell -dereference;\
+ property LEFview TRUE;\
+ };\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract unique;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && \
+ export MAGTYPE=maglef; \
+ magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull extract_$*.tcl < /dev/null
+ mv ./mag/$*.spice ./spi/lvs
+ rm ./mag/*.ext
+ mv -f ./mag/extract_$*.tcl ./mag/tmp
+ mv -f ./mag/extract_$*.log ./mag/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.lvs.summary.log
+ mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+
+LVS_GDS_BLOCKS = $(foreach block, $(BLOCKS), lvs-gds-$(block))
+$(LVS_GDS_BLOCKS): lvs-gds-% : ./gds/%.gds ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./gds/tmp
+ echo "gds read ./$*.gds;\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract unique;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./gds/extract_$*.tcl
+ cd gds && \
+ magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull extract_$*.tcl < /dev/null
+ mv ./gds/$*.spice ./spi/lvs
+ rm ./gds/*.ext
+ mv -f ./gds/extract_$*.tcl ./gds/tmp
+ mv -f ./gds/extract_$*.log ./gds/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ MAGIC_EXT_USE_GDS=1 sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.lvs.summary.log
+ mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+
+# connect-by-label is enabled here!
+LVS_MAGLEF_BLOCKS = $(foreach block, $(BLOCKS), lvs-maglef-$(block))
+$(LVS_MAGLEF_BLOCKS): lvs-maglef-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./maglef/tmp
+ echo "load $* -dereference;\
+ select top cell;\
+ foreach cell [cellname list children] {\
+ load \$$cell -dereference;\
+ property LEFview TRUE;\
+ };\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && export MAGTYPE=maglef; magic -noc -dnull extract_$*.tcl < /dev/null
+ mv ./mag/$*.spice ./spi/lvs
+ rm ./maglef/*.ext
+ mv -f ./mag/extract_$*.tcl ./maglef/tmp
+ mv -f ./mag/extract_$*.log ./maglef/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.maglef.lvs.summary.log
+ mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+# DRC
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+DRC_BLOCKS = $(foreach block, $(BLOCKS), drc-$(block))
+$(DRC_BLOCKS): drc-% : ./gds/%.gds
+ echo "Running DRC on $*"
+ mkdir -p ./gds/tmp
+ cd gds && export DESIGN_IN_DRC=$* && export MAGTYPE=mag; magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull $(CARAVEL_ROOT)/gds/drc_on_gds.tcl < /dev/null
+ @echo "DRC result: ./gds/tmp/$*.drc"
+
+# Antenna
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+ANTENNA_BLOCKS = $(foreach block, $(BLOCKS), antenna-$(block))
+$(ANTENNA_BLOCKS): antenna-% : ./gds/%.gds
+ echo "Running Antenna Checks on $*"
+ mkdir -p ./gds/tmp
+ cd gds && export DESIGN_IN_ANTENNA=$* && export MAGTYPE=mag; magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull $(CARAVEL_ROOT)/gds/antenna_on_gds.tcl < /dev/null 2>&1 | tee ./tmp/$*.antenna
+ mv -f ./gds/*.ext ./gds/tmp/
+ @echo "Antenna result: ./gds/tmp/$*.antenna"
+
+# MAG2GDS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+MAG_BLOCKS = $(foreach block, $(BLOCKS), mag2gds-$(block))
+$(MAG_BLOCKS): mag2gds-% : ./mag/%.mag uncompress
+ echo "Converting mag file $* to GDS..."
+ echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag;\
+ addpath ${CARAVEL_ROOT}/subcells/simple_por/mag;\
+ drc off;\
+ gds rescale false;\
+ load $* -dereference;\
+ select top cell;\
+ expand;\
+ cif *hier write disable;\
+ gds write $*.gds;\
+ exit;" > ./mag/mag2gds_$*.tcl
+ cd ./mag && magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull mag2gds_$*.tcl < /dev/null
+ rm ./mag/mag2gds_$*.tcl
+ mv -f ./mag/$*.gds ./gds/
+
+.PHONY: help
+help:
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+# RCX Extraction
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+RCX_BLOCKS = $(foreach block, $(BLOCKS), rcx-$(block))
+OPENLANE_IMAGE_NAME=efabless/openlane:2021.09.16_03.28.21
+$(RCX_BLOCKS): rcx-% : ./def/%.def
+ echo "Running RC Extraction on $*"
+ mkdir -p ./def/tmp
+ # merge techlef and standard cell lef files
+ python3 $(OPENLANE_ROOT)/scripts/mergeLef.py -i $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/techlef/$(STD_CELL_LIBRARY).tlef $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lef/*.lef -o ./def/tmp/merged.lef
+ echo "\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lib/$(STD_CELL_LIBRARY)__tt_025C_1v80.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30.lib;\
+ set std_cell_lef ./def/tmp/merged.lef;\
+ if {[catch {read_lef \$$std_cell_lef} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ foreach lef_file [glob ./lef/*.lef] {\
+ if {[catch {read_lef \$$lef_file} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ }\
+ };\
+ if {[catch {read_def -order_wires ./def/$*.def} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ read_sdc ./openlane/$*/base.sdc;\
+ set_propagated_clock [all_clocks];\
+ set rc_values \"mcon 9.249146E-3,via 4.5E-3,via2 3.368786E-3,via3 0.376635E-3,via4 0.00580E-3\";\
+ set vias_rc [split \$$rc_values ","];\
+ foreach via_rc \$$vias_rc {\
+ set layer_name [lindex \$$via_rc 0];\
+ set resistance [lindex \$$via_rc 1];\
+ set_layer_rc -via \$$layer_name -resistance \$$resistance;\
+ };\
+ set_wire_rc -signal -layer met2;\
+ set_wire_rc -clock -layer met5;\
+ define_process_corner -ext_model_index 0 X;\
+ extract_parasitics -ext_model_file ${PDK_ROOT}/sky130A/libs.tech/openlane/rcx_rules.info -corner_cnt 1 -max_res 50 -coupling_threshold 0.1 -cc_model 10 -context_depth 5;\
+ write_spef ./def/tmp/$*.spef" > ./def/tmp/or_rcx_$*.tcl
+## Generate Spef file
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow -v $(PDK_ROOT):$(PDK_ROOT) -v $(PWD):/caravel -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) \
+ sh -c " cd /caravel; openroad -exit ./def/tmp/or_rcx_$*.tcl |& tee ./def/tmp/or_rcx_$*.log"
+## Run OpenSTA
+ echo "\
+ set std_cell_lef ./def/tmp/merged.lef;\
+ if {[catch {read_lef \$$std_cell_lef} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ foreach lef_file [glob ./lef/*.lef] {\
+ if {[catch {read_lef \$$lef_file} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ }\
+ };\
+ set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um;\
+ read_liberty -min ${PDK_ROOT}/sky130A/libs.ref/${STD_CELL_LIBRARY}/lib/${STD_CELL_LIBRARY}__ff_n40C_1v95.lib;\
+ read_liberty -max ${PDK_ROOT}/sky130A/libs.ref/${STD_CELL_LIBRARY}/lib/${STD_CELL_LIBRARY}__ss_100C_1v60.lib;\
+ read_verilog ./verilog/gl/$*.v;\
+ link_design $*;\
+ read_spef ./def/tmp/$*.spef;\
+ read_sdc -echo ./openlane/$*/base.sdc;\
+ report_checks -fields {capacitance slew input_pins nets fanout} -path_delay min_max;\
+ " > ./def/tmp/or_sta_$*.tcl
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow -v $(PDK_ROOT):$(PDK_ROOT) -v $(PWD):/caravel -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) \
+ sh -c "cd /caravel; openroad -exit ./def/tmp/or_sta_$*.tcl |& tee ./def/tmp/or_sta_$*.log"
+
+###########################################################################
+.PHONY: generate_fill
+generate_fill: check-env check-uid check-project uncompress
+ifeq ($(FOREGROUND),1)
+ @echo "Running generate_fill in the foreground..."
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __generate_fill
+ @echo "Generate fill completed." 2>&1 | tee -a ./signoff/build/generate_fill.out
+else
+ @echo "Running generate_fill in the background..."
+ @nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __generate_fill >/dev/null 2>&1 &
+ tail -f signoff/build/generate_fill.out
+ @echo "Generate fill completed." | tee -a signoff/build/generate_fill.out
+endif
+
+__generate_fill:
+ @mkdir -p ./signoff/build
+ @cp -r $(CARAVEL_ROOT)/mag/.magicrc $(shell pwd)/mag
+ python3 $(CARAVEL_ROOT)/scripts/generate_fill.py $(USER_ID) $(PROJECT) $(shell pwd) -dist 2>&1 | tee ./signoff/build/generate_fill.out
+ #python3 $(CARAVEL_ROOT)/scripts/generate_fill.py $(USER_ID) $(PROJECT) $(shell pwd) -keep 2>&1 | tee ./signoff/build/generate_fill.out
+
+
+.PHONY: final
+final: check-env check-uid check-project uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __final
+ @echo "Final build completed." 2>&1 | tee -a ./signoff/build/final_build.out
+else
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __final >/dev/null 2>&1 &
+ tail -f signoff/build/final_build.out
+ @echo "Final build completed." 2>&1 | tee -a ./signoff/build/final_build.out
+endif
+
+__final:
+ python3 $(CARAVEL_ROOT)/scripts/compositor.py $(USER_ID) $(PROJECT) $(shell pwd) $(CARAVEL_ROOT)/mag $(shell pwd)/gds -keep
+ #mv $(CARAVEL_ROOT)/mag/caravel_$(USER_ID).mag ./mag/
+ @rm -rf ./mag/tmp
+
+.PHONY: set_user_id
+set_user_id: check-env check-uid uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __set_user_id
+ @echo "Set user ID completed." 2>&1 | tee -a ./signoff/build/set_user_id.out
+else
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __set_user_id >/dev/null 2>&1 &
+ tail -f signoff/build/set_user_id.out
+ @echo "Set user ID completed." 2>&1 | tee -a ./signoff/build/set_user_id.out
+endif
+
+__set_user_id:
+ mkdir -p ./signoff/build
+ # Update info.yaml
+ # sed -r "s/^(\s*project_id\s*:\s*).*/\1${USER_ID}/" -i info.yaml
+ cp $(CARAVEL_ROOT)/gds/user_id_programming.gds ./gds/user_id_programming.gds
+ cp $(CARAVEL_ROOT)/mag/user_id_programming.mag ./mag/user_id_programming.mag
+ cp $(CARAVEL_ROOT)/mag/user_id_textblock.mag ./mag/user_id_textblock.mag
+ cp $(CARAVEL_ROOT)/verilog/rtl/caravel.v ./verilog/rtl/caravel.v
+ python3 $(CARAVEL_ROOT)/scripts/set_user_id.py $(USER_ID) $(shell pwd) 2>&1 | tee ./signoff/build/set_user_id.out
+
+.PHONY: update_caravel
+update_caravel:
+ cd caravel/ && \
+ git checkout master && \
+ git pull
+
+###########################################################################
+.PHONY: pdk
+pdk: skywater-pdk skywater-library skywater-timing open_pdks build-pdk gen-sources
+
+$(PDK_ROOT)/skywater-pdk:
+ git clone https://github.com/google/skywater-pdk.git $(PDK_ROOT)/skywater-pdk
+
+.PHONY: skywater-pdk
+skywater-pdk: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git checkout main && git pull && \
+ git checkout -qf $(SKYWATER_COMMIT)
+
+.PHONY: skywater-library
+skywater-library: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git submodule update --init libraries/$(STD_CELL_LIBRARY)/latest && \
+ git submodule update --init libraries/$(IO_LIBRARY)/latest && \
+ git submodule update --init libraries/$(SPECIAL_VOLTAGE_LIBRARY)/latest && \
+ git submodule update --init libraries/$(PRIMITIVES_LIBRARY)/latest
+
+gen-sources: $(PDK_ROOT)/sky130A
+ touch $(PDK_ROOT)/sky130A/SOURCES
+ echo -ne "skywater-pdk " >> $(PDK_ROOT)/sky130A/SOURCES
+ cd $(PDK_ROOT)/skywater-pdk && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
+ echo -ne "open_pdks " >> $(PDK_ROOT)/sky130A/SOURCES
+ cd $(PDK_ROOT)/open_pdks && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
+
+skywater-timing: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ $(MAKE) timing
+### OPEN_PDKS
+$(PDK_ROOT)/open_pdks:
+ git clone git://opencircuitdesign.com/open_pdks $(PDK_ROOT)/open_pdks
+
+.PHONY: open_pdks
+open_pdks: check-env $(PDK_ROOT)/open_pdks
+ cd $(PDK_ROOT)/open_pdks && \
+ git checkout master && git pull && \
+ git checkout -qf $(OPEN_PDKS_COMMIT)
+
+.PHONY: build-pdk
+build-pdk: check-env $(PDK_ROOT)/open_pdks $(PDK_ROOT)/skywater-pdk
+ [ -d $(PDK_ROOT)/sky130A ] && \
+ (echo "Warning: A sky130A build already exists under $(PDK_ROOT). It will be deleted first!" && \
+ sleep 5 && \
+ rm -rf $(PDK_ROOT)/sky130A) || \
+ true
+ cd $(PDK_ROOT)/open_pdks && \
+ ./configure --enable-sky130-pdk=$(PDK_ROOT)/skywater-pdk/libraries --with-sky130-local-path=$(PDK_ROOT) --enable-sram-sky130=$(INSTALL_SRAM) && \
+ cd sky130 && \
+ $(MAKE) veryclean && \
+ $(MAKE) && \
+ make SHARED_PDKS_PATH=$(PDK_ROOT) install && \
+ $(MAKE) clean
+
+.RECIPE: manifest
+manifest: mag/ maglef/ verilog/rtl/ Makefile
+ touch manifest && \
+ find verilog/rtl/* -type f ! -name "caravel_netlists.v" ! -name "user_*.v" ! -name "README" ! -name "defines.v" -exec shasum {} \; > manifest && \
+ shasum scripts/set_user_id.py scripts/generate_fill.py scripts/compositor.py >> manifest
+# shasum lef/user_project_wrapper_empty.lef >> manifest
+# find maglef/*.mag -type f ! -name "user_project_wrapper.mag" -exec shasum {} \; >> manifest && \
+# shasum mag/caravel.mag mag/.magicrc >> manifest
+
+.RECIPE: master_manifest
+master_manifest:
+ find verilog/rtl/* -type f -exec shasum {} \; > master_manifest && \
+ find verilog/gl/* -type f -exec shasum {} \; >> master_manifest && \
+ shasum scripts/set_user_id.py scripts/generate_fill.py scripts/compositor.py >> master_manifest && \
+ find lef/*.lef -type f -exec shasum {} \; >> master_manifest && \
+ find def/*.def -type f -exec shasum {} \; >> master_manifest && \
+ find mag/*.mag -type f -exec shasum {} \; >> master_manifest && \
+ find maglef/*.mag -type f -exec shasum {} \; >> master_manifest && \
+ find spi/lvs/*.spice -type f -exec shasum {} \; >> master_manifest && \
+ find gds/*.gds -type f -exec shasum {} \; >> master_manifest
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+check-uid:
+ifndef USER_ID
+ $(error USER_ID is undefined, please export it before running make set_user_id)
+else
+ @echo USER_ID is set to $(USER_ID)
+endif
+
+check-project:
+ifndef PROJECT
+ $(error PROJECT is undefined, please export it before running make generate_fill or make final)
+else
+ @echo PROJECT is set to $(PROJECT)
+endif
+
+# Make README.rst
+README.rst: README.src.rst docs/source/getting-started.rst docs/source/tool-versioning.rst openlane/README.src.rst docs/source/caravel-with-openlane.rst Makefile
+ pip -q install rst_include && \
+ rm -f README.rst && \
+ rst_include include README.src.rst - | \
+ sed \
+ -e's@\.\/\_static@\/docs\/source\/\_static@g' \
+ -e's@:doc:`tool-versioning`@`tool-versioning.rst <./docs/source/tool-versioning.rst>`__@g' \
+ -e's@.. note::@**NOTE:**@g' \
+ -e's@.. warning::@**WARNING:**@g' \
+ > README.rst && \
+ rst_include include openlane/README.src.rst - | \
+ sed \
+ -e's@https://github.com/efabless/caravel/blob/master/verilog@../verilog@g' \
+ -e's@:ref:`getting-started`@`README.rst <../README.rst>`__@g' \
+ -e's@https://github.com/efabless/caravel/blob/master/openlane/@./@g' \
+ -e's@.. note::@**NOTE:**@g' \
+ -e's@.. warning::@**WARNING:**@g' \
+ > openlane/README.rst
diff --git a/caravel/gds/antenna_on_gds.tcl b/caravel/gds/antenna_on_gds.tcl
new file mode 100644
index 0000000..5f379c6
--- /dev/null
+++ b/caravel/gds/antenna_on_gds.tcl
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+gds read $::env(DESIGN_IN_ANTENNA).gds
+select top cell
+extract do local
+extract no capacitance
+extract no coupling
+extract no resistance
+extract no adjust
+extract unique
+# extract warn all
+extract
+feedback save ./tmp/$::env(DESIGN_IN_ANTENNA)_ext2spice.antenna.feedback.txt
+antennacheck debug
+antennacheck
diff --git a/caravel/gds/drc_on_gds.tcl b/caravel/gds/drc_on_gds.tcl
new file mode 100644
index 0000000..8bb3035
--- /dev/null
+++ b/caravel/gds/drc_on_gds.tcl
@@ -0,0 +1,61 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+gds read $::env(DESIGN_IN_DRC).gds
+set fout [open ./tmp/$::env(DESIGN_IN_DRC).drc w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_IN_DRC)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $::env(DESIGN_IN_DRC)\n"
+flush stdout
+load $::env(DESIGN_IN_DRC)
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+set count 0
+puts $fout "$::env(DESIGN_IN_DRC)"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE (./tmp/$::env(DESIGN_IN_DRC).drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors(./tmp/$::env(DESIGN_IN_DRC).drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save ./tmp/$::env(DESIGN_IN_DRC).drc.drc.mag
+puts stdout "\[INFO\]: Saved"
diff --git a/caravel/gds/gds2mag-all.sh b/caravel/gds/gds2mag-all.sh
new file mode 100755
index 0000000..b9ca6f2
--- /dev/null
+++ b/caravel/gds/gds2mag-all.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+gunzip *.gz
+mv sram_1rw1r_32_256_8_sky130_lp1.gds sram_1rw1r_32_256_8_sky130.gds
+
+o-gds2mag-mag.sh simple_por.gds
+o-gds2mag-mag.sh gpio_control_block.gds
+o-gds2mag-mag.sh digital_pll.gds
+o-gds2mag-mag.sh storage.gds
+o-gds2mag-mag.sh mgmt_core.gds
+o-gds2mag-mag.sh chip_io.gds
+o-gds2mag-mag.sh sram_1rw1r_32_256_8_sky130.gds
+
+mv -f *.mag ../mag
+
+gzip -9 storage.gds mgmt_core.gds chip_io.gds
+
+
diff --git a/caravel/gds/user_analog_project_wrapper_empty.gds b/caravel/gds/user_analog_project_wrapper_empty.gds
new file mode 100644
index 0000000..6bb65fc
--- /dev/null
+++ b/caravel/gds/user_analog_project_wrapper_empty.gds
Binary files differ
diff --git a/caravel/gds/user_project_wrapper_empty.gds b/caravel/gds/user_project_wrapper_empty.gds
new file mode 100644
index 0000000..83ec0b4
--- /dev/null
+++ b/caravel/gds/user_project_wrapper_empty.gds
Binary files differ
diff --git a/caravel/info.yaml b/caravel/info.yaml
new file mode 100644
index 0000000..06b19bf
--- /dev/null
+++ b/caravel/info.yaml
@@ -0,0 +1,18 @@
+project:
+ description: "Two Stage CMOS OPAMP with Frequency Compensation"
+ foundry: "SkyWater"
+ git_url: https://github.com/MadhuriKadam9/avsdopamp_3v3_sky130_v2.git"
+ organization: "VSD Corp. Pvt. Ltd."
+ organization_url: "https://www.vlsisystemdesign.com/"
+ owner: "Madhuri Kadam"
+ process: "SKY130"
+ project_name: "CMOS OPAMP"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Test Harness"
+ category: "Test Harness"
+ top_level_netlist: "caravel/spi/lvs/caravan.spice"
+ user_level_netlist: "netgen/user_analog_project_wrapper.spice"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/caravel/lef/user_analog_project_wrapper_empty.lef b/caravel/lef/user_analog_project_wrapper_empty.lef
new file mode 100644
index 0000000..ea34f13
--- /dev/null
+++ b/caravel/lef/user_analog_project_wrapper_empty.lef
@@ -0,0 +1,5436 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO user_analog_project_wrapper
+ CLASS BLOCK ;
+ FOREIGN user_analog_project_wrapper ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2920.000 BY 3520.000 ;
+ PIN gpio_analog[0]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1346.150 2924.000 1346.710 ;
+ END
+ END gpio_analog[0]
+ PIN gpio_analog[10]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1909.320 2.400 1909.880 ;
+ END
+ END gpio_analog[10]
+ PIN gpio_analog[11]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1693.210 2.400 1693.770 ;
+ END
+ END gpio_analog[11]
+ PIN gpio_analog[12]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1477.100 2.400 1477.660 ;
+ END
+ END gpio_analog[12]
+ PIN gpio_analog[13]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1261.990 2.400 1262.550 ;
+ END
+ END gpio_analog[13]
+ PIN gpio_analog[14]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 623.880 2.400 624.440 ;
+ END
+ END gpio_analog[14]
+ PIN gpio_analog[15]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 407.770 2.400 408.330 ;
+ END
+ END gpio_analog[15]
+ PIN gpio_analog[16]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 191.660 2.400 192.220 ;
+ END
+ END gpio_analog[16]
+ PIN gpio_analog[17]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 84.550 2.400 85.110 ;
+ END
+ END gpio_analog[17]
+ PIN gpio_analog[1]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1568.260 2924.000 1568.820 ;
+ END
+ END gpio_analog[1]
+ PIN gpio_analog[2]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1794.370 2924.000 1794.930 ;
+ END
+ END gpio_analog[2]
+ PIN gpio_analog[3]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2026.480 2924.000 2027.040 ;
+ END
+ END gpio_analog[3]
+ PIN gpio_analog[4]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2248.590 2924.000 2249.150 ;
+ END
+ END gpio_analog[4]
+ PIN gpio_analog[5]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2470.700 2924.000 2471.260 ;
+ END
+ END gpio_analog[5]
+ PIN gpio_analog[6]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2917.810 2924.000 2918.370 ;
+ END
+ END gpio_analog[6]
+ PIN gpio_analog[7]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2557.650 2.400 2558.210 ;
+ END
+ END gpio_analog[7]
+ PIN gpio_analog[8]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2341.540 2.400 2342.100 ;
+ END
+ END gpio_analog[8]
+ PIN gpio_analog[9]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2125.430 2.400 2125.990 ;
+ END
+ END gpio_analog[9]
+ PIN gpio_noesd[0]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1352.060 2924.000 1352.620 ;
+ END
+ END gpio_noesd[0]
+ PIN gpio_noesd[10]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1903.410 2.400 1903.970 ;
+ END
+ END gpio_noesd[10]
+ PIN gpio_noesd[11]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1687.300 2.400 1687.860 ;
+ END
+ END gpio_noesd[11]
+ PIN gpio_noesd[12]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1471.190 2.400 1471.750 ;
+ END
+ END gpio_noesd[12]
+ PIN gpio_noesd[13]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1256.080 2.400 1256.640 ;
+ END
+ END gpio_noesd[13]
+ PIN gpio_noesd[14]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 617.970 2.400 618.530 ;
+ END
+ END gpio_noesd[14]
+ PIN gpio_noesd[15]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 401.860 2.400 402.420 ;
+ END
+ END gpio_noesd[15]
+ PIN gpio_noesd[16]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 185.750 2.400 186.310 ;
+ END
+ END gpio_noesd[16]
+ PIN gpio_noesd[17]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 78.640 2.400 79.200 ;
+ END
+ END gpio_noesd[17]
+ PIN gpio_noesd[1]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1574.170 2924.000 1574.730 ;
+ END
+ END gpio_noesd[1]
+ PIN gpio_noesd[2]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1800.280 2924.000 1800.840 ;
+ END
+ END gpio_noesd[2]
+ PIN gpio_noesd[3]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2032.390 2924.000 2032.950 ;
+ END
+ END gpio_noesd[3]
+ PIN gpio_noesd[4]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2254.500 2924.000 2255.060 ;
+ END
+ END gpio_noesd[4]
+ PIN gpio_noesd[5]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2476.610 2924.000 2477.170 ;
+ END
+ END gpio_noesd[5]
+ PIN gpio_noesd[6]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2923.720 2924.000 2924.280 ;
+ END
+ END gpio_noesd[6]
+ PIN gpio_noesd[7]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2551.740 2.400 2552.300 ;
+ END
+ END gpio_noesd[7]
+ PIN gpio_noesd[8]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2335.630 2.400 2336.190 ;
+ END
+ END gpio_noesd[8]
+ PIN gpio_noesd[9]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2119.520 2.400 2120.080 ;
+ END
+ END gpio_noesd[9]
+ PIN io_analog[0]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.500 3389.920 2920.000 3414.920 ;
+ END
+ END io_analog[0]
+ PIN io_analog[10]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 3401.210 8.500 3426.210 ;
+ END
+ END io_analog[10]
+ PIN io_analog[1]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2832.970 3511.500 2857.970 3520.000 ;
+ END
+ END io_analog[1]
+ PIN io_analog[2]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2326.970 3511.500 2351.970 3520.000 ;
+ END
+ END io_analog[2]
+ PIN io_analog[3]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2066.970 3511.500 2091.970 3520.000 ;
+ END
+ END io_analog[3]
+ PIN io_analog[4]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1646.470 3511.500 1671.470 3520.000 ;
+ END
+ END io_analog[4]
+ PIN io_analog[5]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1137.970 3511.500 1162.970 3520.000 ;
+ END
+ END io_analog[5]
+ PIN io_analog[6]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 879.470 3511.500 904.470 3520.000 ;
+ END
+ END io_analog[6]
+ PIN io_analog[7]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 600.970 3511.500 625.970 3520.000 ;
+ END
+ END io_analog[7]
+ PIN io_analog[8]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 340.970 3511.500 365.970 3520.000 ;
+ END
+ END io_analog[8]
+ PIN io_analog[9]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 80.970 3511.500 105.970 3520.000 ;
+ END
+ END io_analog[9]
+ PIN io_analog[4]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1594.970 3511.500 1619.970 3520.000 ;
+ END
+ END io_analog[4]
+ PIN io_analog[5]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1086.470 3511.500 1111.470 3520.000 ;
+ END
+ END io_analog[5]
+ PIN io_analog[6]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 827.970 3511.500 852.970 3520.000 ;
+ END
+ END io_analog[6]
+ PIN io_clamp_high[0]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1633.970 3511.500 1644.970 3520.000 ;
+ END
+ END io_clamp_high[0]
+ PIN io_clamp_high[1]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1125.470 3511.500 1136.470 3520.000 ;
+ END
+ END io_clamp_high[1]
+ PIN io_clamp_high[2]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 866.970 3511.500 877.970 3520.000 ;
+ END
+ END io_clamp_high[2]
+ PIN io_clamp_low[0]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1621.470 3511.500 1632.470 3520.000 ;
+ END
+ END io_clamp_low[0]
+ PIN io_clamp_low[1]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 1112.970 3511.500 1123.970 3520.000 ;
+ END
+ END io_clamp_low[1]
+ PIN io_clamp_low[2]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 854.470 3511.500 865.470 3520.000 ;
+ END
+ END io_clamp_low[2]
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 13.630 2924.000 14.190 ;
+ END
+ END io_in[0]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2044.210 2924.000 2044.770 ;
+ END
+ END io_in[10]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2266.320 2924.000 2266.880 ;
+ END
+ END io_in[11]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2488.430 2924.000 2488.990 ;
+ END
+ END io_in[12]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2935.540 2924.000 2936.100 ;
+ END
+ END io_in[13]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2539.920 2.400 2540.480 ;
+ END
+ END io_in[14]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2323.810 2.400 2324.370 ;
+ END
+ END io_in[15]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2107.700 2.400 2108.260 ;
+ END
+ END io_in[16]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1891.590 2.400 1892.150 ;
+ END
+ END io_in[17]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1675.480 2.400 1676.040 ;
+ END
+ END io_in[18]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1459.370 2.400 1459.930 ;
+ END
+ END io_in[19]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 37.270 2924.000 37.830 ;
+ END
+ END io_in[1]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1244.260 2.400 1244.820 ;
+ END
+ END io_in[20]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 606.150 2.400 606.710 ;
+ END
+ END io_in[21]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 390.040 2.400 390.600 ;
+ END
+ END io_in[22]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 173.930 2.400 174.490 ;
+ END
+ END io_in[23]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 66.820 2.400 67.380 ;
+ END
+ END io_in[24]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 43.180 2.400 43.740 ;
+ END
+ END io_in[25]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 19.540 2.400 20.100 ;
+ END
+ END io_in[26]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 60.910 2924.000 61.470 ;
+ END
+ END io_in[2]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 84.550 2924.000 85.110 ;
+ END
+ END io_in[3]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 108.190 2924.000 108.750 ;
+ END
+ END io_in[4]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 240.480 2924.000 241.040 ;
+ END
+ END io_in[5]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 463.770 2924.000 464.330 ;
+ END
+ END io_in[6]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1363.880 2924.000 1364.440 ;
+ END
+ END io_in[7]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1585.990 2924.000 1586.550 ;
+ END
+ END io_in[8]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1812.100 2924.000 1812.660 ;
+ END
+ END io_in[9]
+ PIN io_in_3v3[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 7.720 2924.000 8.280 ;
+ END
+ END io_in_3v3[0]
+ PIN io_in_3v3[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2038.300 2924.000 2038.860 ;
+ END
+ END io_in_3v3[10]
+ PIN io_in_3v3[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2260.410 2924.000 2260.970 ;
+ END
+ END io_in_3v3[11]
+ PIN io_in_3v3[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2482.520 2924.000 2483.080 ;
+ END
+ END io_in_3v3[12]
+ PIN io_in_3v3[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2929.630 2924.000 2930.190 ;
+ END
+ END io_in_3v3[13]
+ PIN io_in_3v3[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2545.830 2.400 2546.390 ;
+ END
+ END io_in_3v3[14]
+ PIN io_in_3v3[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2329.720 2.400 2330.280 ;
+ END
+ END io_in_3v3[15]
+ PIN io_in_3v3[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2113.610 2.400 2114.170 ;
+ END
+ END io_in_3v3[16]
+ PIN io_in_3v3[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1897.500 2.400 1898.060 ;
+ END
+ END io_in_3v3[17]
+ PIN io_in_3v3[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1681.390 2.400 1681.950 ;
+ END
+ END io_in_3v3[18]
+ PIN io_in_3v3[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1465.280 2.400 1465.840 ;
+ END
+ END io_in_3v3[19]
+ PIN io_in_3v3[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 31.360 2924.000 31.920 ;
+ END
+ END io_in_3v3[1]
+ PIN io_in_3v3[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1250.170 2.400 1250.730 ;
+ END
+ END io_in_3v3[20]
+ PIN io_in_3v3[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 612.060 2.400 612.620 ;
+ END
+ END io_in_3v3[21]
+ PIN io_in_3v3[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 395.950 2.400 396.510 ;
+ END
+ END io_in_3v3[22]
+ PIN io_in_3v3[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 179.840 2.400 180.400 ;
+ END
+ END io_in_3v3[23]
+ PIN io_in_3v3[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 72.730 2.400 73.290 ;
+ END
+ END io_in_3v3[24]
+ PIN io_in_3v3[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 49.090 2.400 49.650 ;
+ END
+ END io_in_3v3[25]
+ PIN io_in_3v3[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 25.450 2.400 26.010 ;
+ END
+ END io_in_3v3[26]
+ PIN io_in_3v3[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 55.000 2924.000 55.560 ;
+ END
+ END io_in_3v3[2]
+ PIN io_in_3v3[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 78.640 2924.000 79.200 ;
+ END
+ END io_in_3v3[3]
+ PIN io_in_3v3[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 102.280 2924.000 102.840 ;
+ END
+ END io_in_3v3[4]
+ PIN io_in_3v3[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 234.570 2924.000 235.130 ;
+ END
+ END io_in_3v3[5]
+ PIN io_in_3v3[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 457.860 2924.000 458.420 ;
+ END
+ END io_in_3v3[6]
+ PIN io_in_3v3[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1357.970 2924.000 1358.530 ;
+ END
+ END io_in_3v3[7]
+ PIN io_in_3v3[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1580.080 2924.000 1580.640 ;
+ END
+ END io_in_3v3[8]
+ PIN io_in_3v3[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1806.190 2924.000 1806.750 ;
+ END
+ END io_in_3v3[9]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 25.450 2924.000 26.010 ;
+ END
+ END io_oeb[0]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2056.030 2924.000 2056.590 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2278.140 2924.000 2278.700 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2500.250 2924.000 2500.810 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2947.360 2924.000 2947.920 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2528.100 2.400 2528.660 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2311.990 2.400 2312.550 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2095.880 2.400 2096.440 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1879.770 2.400 1880.330 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1663.660 2.400 1664.220 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1447.550 2.400 1448.110 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 49.090 2924.000 49.650 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1232.440 2.400 1233.000 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 594.330 2.400 594.890 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 378.220 2.400 378.780 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 162.110 2.400 162.670 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 55.000 2.400 55.560 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 31.360 2.400 31.920 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 7.720 2.400 8.280 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 72.730 2924.000 73.290 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 96.370 2924.000 96.930 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 120.010 2924.000 120.570 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 252.300 2924.000 252.860 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 475.590 2924.000 476.150 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1375.700 2924.000 1376.260 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1597.810 2924.000 1598.370 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1823.920 2924.000 1824.480 ;
+ END
+ END io_oeb[9]
+ PIN io_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 19.540 2924.000 20.100 ;
+ END
+ END io_out[0]
+ PIN io_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2050.120 2924.000 2050.680 ;
+ END
+ END io_out[10]
+ PIN io_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2272.230 2924.000 2272.790 ;
+ END
+ END io_out[11]
+ PIN io_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2494.340 2924.000 2494.900 ;
+ END
+ END io_out[12]
+ PIN io_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2941.450 2924.000 2942.010 ;
+ END
+ END io_out[13]
+ PIN io_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2534.010 2.400 2534.570 ;
+ END
+ END io_out[14]
+ PIN io_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2317.900 2.400 2318.460 ;
+ END
+ END io_out[15]
+ PIN io_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 2101.790 2.400 2102.350 ;
+ END
+ END io_out[16]
+ PIN io_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1885.680 2.400 1886.240 ;
+ END
+ END io_out[17]
+ PIN io_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1669.570 2.400 1670.130 ;
+ END
+ END io_out[18]
+ PIN io_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1453.460 2.400 1454.020 ;
+ END
+ END io_out[19]
+ PIN io_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 43.180 2924.000 43.740 ;
+ END
+ END io_out[1]
+ PIN io_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 1238.350 2.400 1238.910 ;
+ END
+ END io_out[20]
+ PIN io_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 600.240 2.400 600.800 ;
+ END
+ END io_out[21]
+ PIN io_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 384.130 2.400 384.690 ;
+ END
+ END io_out[22]
+ PIN io_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 168.020 2.400 168.580 ;
+ END
+ END io_out[23]
+ PIN io_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 60.910 2.400 61.470 ;
+ END
+ END io_out[24]
+ PIN io_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 37.270 2.400 37.830 ;
+ END
+ END io_out[25]
+ PIN io_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.000 13.630 2.400 14.190 ;
+ END
+ END io_out[26]
+ PIN io_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 66.820 2924.000 67.380 ;
+ END
+ END io_out[2]
+ PIN io_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 90.460 2924.000 91.020 ;
+ END
+ END io_out[3]
+ PIN io_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 114.100 2924.000 114.660 ;
+ END
+ END io_out[4]
+ PIN io_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 246.390 2924.000 246.950 ;
+ END
+ END io_out[5]
+ PIN io_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 469.680 2924.000 470.240 ;
+ END
+ END io_out[6]
+ PIN io_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1369.790 2924.000 1370.350 ;
+ END
+ END io_out[7]
+ PIN io_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1591.900 2924.000 1592.460 ;
+ END
+ END io_out[8]
+ PIN io_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1818.010 2924.000 1818.570 ;
+ END
+ END io_out[9]
+ PIN la_data_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 629.080 -4.000 629.640 2.400 ;
+ END
+ END la_data_in[0]
+ PIN la_data_in[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2402.080 -4.000 2402.640 2.400 ;
+ END
+ END la_data_in[100]
+ PIN la_data_in[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2419.810 -4.000 2420.370 2.400 ;
+ END
+ END la_data_in[101]
+ PIN la_data_in[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2437.540 -4.000 2438.100 2.400 ;
+ END
+ END la_data_in[102]
+ PIN la_data_in[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2455.270 -4.000 2455.830 2.400 ;
+ END
+ END la_data_in[103]
+ PIN la_data_in[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2473.000 -4.000 2473.560 2.400 ;
+ END
+ END la_data_in[104]
+ PIN la_data_in[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2490.730 -4.000 2491.290 2.400 ;
+ END
+ END la_data_in[105]
+ PIN la_data_in[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2508.460 -4.000 2509.020 2.400 ;
+ END
+ END la_data_in[106]
+ PIN la_data_in[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2526.190 -4.000 2526.750 2.400 ;
+ END
+ END la_data_in[107]
+ PIN la_data_in[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2543.920 -4.000 2544.480 2.400 ;
+ END
+ END la_data_in[108]
+ PIN la_data_in[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2561.650 -4.000 2562.210 2.400 ;
+ END
+ END la_data_in[109]
+ PIN la_data_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 806.380 -4.000 806.940 2.400 ;
+ END
+ END la_data_in[10]
+ PIN la_data_in[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2579.380 -4.000 2579.940 2.400 ;
+ END
+ END la_data_in[110]
+ PIN la_data_in[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2597.110 -4.000 2597.670 2.400 ;
+ END
+ END la_data_in[111]
+ PIN la_data_in[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2614.840 -4.000 2615.400 2.400 ;
+ END
+ END la_data_in[112]
+ PIN la_data_in[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2632.570 -4.000 2633.130 2.400 ;
+ END
+ END la_data_in[113]
+ PIN la_data_in[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2650.300 -4.000 2650.860 2.400 ;
+ END
+ END la_data_in[114]
+ PIN la_data_in[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2668.030 -4.000 2668.590 2.400 ;
+ END
+ END la_data_in[115]
+ PIN la_data_in[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2685.760 -4.000 2686.320 2.400 ;
+ END
+ END la_data_in[116]
+ PIN la_data_in[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2703.490 -4.000 2704.050 2.400 ;
+ END
+ END la_data_in[117]
+ PIN la_data_in[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2721.220 -4.000 2721.780 2.400 ;
+ END
+ END la_data_in[118]
+ PIN la_data_in[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2738.950 -4.000 2739.510 2.400 ;
+ END
+ END la_data_in[119]
+ PIN la_data_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 824.110 -4.000 824.670 2.400 ;
+ END
+ END la_data_in[11]
+ PIN la_data_in[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2756.680 -4.000 2757.240 2.400 ;
+ END
+ END la_data_in[120]
+ PIN la_data_in[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2774.410 -4.000 2774.970 2.400 ;
+ END
+ END la_data_in[121]
+ PIN la_data_in[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2792.140 -4.000 2792.700 2.400 ;
+ END
+ END la_data_in[122]
+ PIN la_data_in[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2809.870 -4.000 2810.430 2.400 ;
+ END
+ END la_data_in[123]
+ PIN la_data_in[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2827.600 -4.000 2828.160 2.400 ;
+ END
+ END la_data_in[124]
+ PIN la_data_in[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2845.330 -4.000 2845.890 2.400 ;
+ END
+ END la_data_in[125]
+ PIN la_data_in[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2863.060 -4.000 2863.620 2.400 ;
+ END
+ END la_data_in[126]
+ PIN la_data_in[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2880.790 -4.000 2881.350 2.400 ;
+ END
+ END la_data_in[127]
+ PIN la_data_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 841.840 -4.000 842.400 2.400 ;
+ END
+ END la_data_in[12]
+ PIN la_data_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 859.570 -4.000 860.130 2.400 ;
+ END
+ END la_data_in[13]
+ PIN la_data_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 877.300 -4.000 877.860 2.400 ;
+ END
+ END la_data_in[14]
+ PIN la_data_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 895.030 -4.000 895.590 2.400 ;
+ END
+ END la_data_in[15]
+ PIN la_data_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 912.760 -4.000 913.320 2.400 ;
+ END
+ END la_data_in[16]
+ PIN la_data_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 930.490 -4.000 931.050 2.400 ;
+ END
+ END la_data_in[17]
+ PIN la_data_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 948.220 -4.000 948.780 2.400 ;
+ END
+ END la_data_in[18]
+ PIN la_data_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 965.950 -4.000 966.510 2.400 ;
+ END
+ END la_data_in[19]
+ PIN la_data_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 646.810 -4.000 647.370 2.400 ;
+ END
+ END la_data_in[1]
+ PIN la_data_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 983.680 -4.000 984.240 2.400 ;
+ END
+ END la_data_in[20]
+ PIN la_data_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1001.410 -4.000 1001.970 2.400 ;
+ END
+ END la_data_in[21]
+ PIN la_data_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1019.140 -4.000 1019.700 2.400 ;
+ END
+ END la_data_in[22]
+ PIN la_data_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1036.870 -4.000 1037.430 2.400 ;
+ END
+ END la_data_in[23]
+ PIN la_data_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1054.600 -4.000 1055.160 2.400 ;
+ END
+ END la_data_in[24]
+ PIN la_data_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1072.330 -4.000 1072.890 2.400 ;
+ END
+ END la_data_in[25]
+ PIN la_data_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1090.060 -4.000 1090.620 2.400 ;
+ END
+ END la_data_in[26]
+ PIN la_data_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1107.790 -4.000 1108.350 2.400 ;
+ END
+ END la_data_in[27]
+ PIN la_data_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1125.520 -4.000 1126.080 2.400 ;
+ END
+ END la_data_in[28]
+ PIN la_data_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1143.250 -4.000 1143.810 2.400 ;
+ END
+ END la_data_in[29]
+ PIN la_data_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 664.540 -4.000 665.100 2.400 ;
+ END
+ END la_data_in[2]
+ PIN la_data_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1160.980 -4.000 1161.540 2.400 ;
+ END
+ END la_data_in[30]
+ PIN la_data_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1178.710 -4.000 1179.270 2.400 ;
+ END
+ END la_data_in[31]
+ PIN la_data_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1196.440 -4.000 1197.000 2.400 ;
+ END
+ END la_data_in[32]
+ PIN la_data_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1214.170 -4.000 1214.730 2.400 ;
+ END
+ END la_data_in[33]
+ PIN la_data_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1231.900 -4.000 1232.460 2.400 ;
+ END
+ END la_data_in[34]
+ PIN la_data_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1249.630 -4.000 1250.190 2.400 ;
+ END
+ END la_data_in[35]
+ PIN la_data_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1267.360 -4.000 1267.920 2.400 ;
+ END
+ END la_data_in[36]
+ PIN la_data_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1285.090 -4.000 1285.650 2.400 ;
+ END
+ END la_data_in[37]
+ PIN la_data_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1302.820 -4.000 1303.380 2.400 ;
+ END
+ END la_data_in[38]
+ PIN la_data_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1320.550 -4.000 1321.110 2.400 ;
+ END
+ END la_data_in[39]
+ PIN la_data_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 682.270 -4.000 682.830 2.400 ;
+ END
+ END la_data_in[3]
+ PIN la_data_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1338.280 -4.000 1338.840 2.400 ;
+ END
+ END la_data_in[40]
+ PIN la_data_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1356.010 -4.000 1356.570 2.400 ;
+ END
+ END la_data_in[41]
+ PIN la_data_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1373.740 -4.000 1374.300 2.400 ;
+ END
+ END la_data_in[42]
+ PIN la_data_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1391.470 -4.000 1392.030 2.400 ;
+ END
+ END la_data_in[43]
+ PIN la_data_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1409.200 -4.000 1409.760 2.400 ;
+ END
+ END la_data_in[44]
+ PIN la_data_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1426.930 -4.000 1427.490 2.400 ;
+ END
+ END la_data_in[45]
+ PIN la_data_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1444.660 -4.000 1445.220 2.400 ;
+ END
+ END la_data_in[46]
+ PIN la_data_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1462.390 -4.000 1462.950 2.400 ;
+ END
+ END la_data_in[47]
+ PIN la_data_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1480.120 -4.000 1480.680 2.400 ;
+ END
+ END la_data_in[48]
+ PIN la_data_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1497.850 -4.000 1498.410 2.400 ;
+ END
+ END la_data_in[49]
+ PIN la_data_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 700.000 -4.000 700.560 2.400 ;
+ END
+ END la_data_in[4]
+ PIN la_data_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1515.580 -4.000 1516.140 2.400 ;
+ END
+ END la_data_in[50]
+ PIN la_data_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1533.310 -4.000 1533.870 2.400 ;
+ END
+ END la_data_in[51]
+ PIN la_data_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1551.040 -4.000 1551.600 2.400 ;
+ END
+ END la_data_in[52]
+ PIN la_data_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1568.770 -4.000 1569.330 2.400 ;
+ END
+ END la_data_in[53]
+ PIN la_data_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1586.500 -4.000 1587.060 2.400 ;
+ END
+ END la_data_in[54]
+ PIN la_data_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1604.230 -4.000 1604.790 2.400 ;
+ END
+ END la_data_in[55]
+ PIN la_data_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1621.960 -4.000 1622.520 2.400 ;
+ END
+ END la_data_in[56]
+ PIN la_data_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1639.690 -4.000 1640.250 2.400 ;
+ END
+ END la_data_in[57]
+ PIN la_data_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1657.420 -4.000 1657.980 2.400 ;
+ END
+ END la_data_in[58]
+ PIN la_data_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1675.150 -4.000 1675.710 2.400 ;
+ END
+ END la_data_in[59]
+ PIN la_data_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 717.730 -4.000 718.290 2.400 ;
+ END
+ END la_data_in[5]
+ PIN la_data_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1692.880 -4.000 1693.440 2.400 ;
+ END
+ END la_data_in[60]
+ PIN la_data_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1710.610 -4.000 1711.170 2.400 ;
+ END
+ END la_data_in[61]
+ PIN la_data_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1728.340 -4.000 1728.900 2.400 ;
+ END
+ END la_data_in[62]
+ PIN la_data_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1746.070 -4.000 1746.630 2.400 ;
+ END
+ END la_data_in[63]
+ PIN la_data_in[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1763.800 -4.000 1764.360 2.400 ;
+ END
+ END la_data_in[64]
+ PIN la_data_in[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1781.530 -4.000 1782.090 2.400 ;
+ END
+ END la_data_in[65]
+ PIN la_data_in[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1799.260 -4.000 1799.820 2.400 ;
+ END
+ END la_data_in[66]
+ PIN la_data_in[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1816.990 -4.000 1817.550 2.400 ;
+ END
+ END la_data_in[67]
+ PIN la_data_in[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1834.720 -4.000 1835.280 2.400 ;
+ END
+ END la_data_in[68]
+ PIN la_data_in[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1852.450 -4.000 1853.010 2.400 ;
+ END
+ END la_data_in[69]
+ PIN la_data_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 735.460 -4.000 736.020 2.400 ;
+ END
+ END la_data_in[6]
+ PIN la_data_in[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1870.180 -4.000 1870.740 2.400 ;
+ END
+ END la_data_in[70]
+ PIN la_data_in[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1887.910 -4.000 1888.470 2.400 ;
+ END
+ END la_data_in[71]
+ PIN la_data_in[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1905.640 -4.000 1906.200 2.400 ;
+ END
+ END la_data_in[72]
+ PIN la_data_in[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1923.370 -4.000 1923.930 2.400 ;
+ END
+ END la_data_in[73]
+ PIN la_data_in[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1941.100 -4.000 1941.660 2.400 ;
+ END
+ END la_data_in[74]
+ PIN la_data_in[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1958.830 -4.000 1959.390 2.400 ;
+ END
+ END la_data_in[75]
+ PIN la_data_in[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1976.560 -4.000 1977.120 2.400 ;
+ END
+ END la_data_in[76]
+ PIN la_data_in[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1994.290 -4.000 1994.850 2.400 ;
+ END
+ END la_data_in[77]
+ PIN la_data_in[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2012.020 -4.000 2012.580 2.400 ;
+ END
+ END la_data_in[78]
+ PIN la_data_in[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2029.750 -4.000 2030.310 2.400 ;
+ END
+ END la_data_in[79]
+ PIN la_data_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 753.190 -4.000 753.750 2.400 ;
+ END
+ END la_data_in[7]
+ PIN la_data_in[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2047.480 -4.000 2048.040 2.400 ;
+ END
+ END la_data_in[80]
+ PIN la_data_in[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2065.210 -4.000 2065.770 2.400 ;
+ END
+ END la_data_in[81]
+ PIN la_data_in[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2082.940 -4.000 2083.500 2.400 ;
+ END
+ END la_data_in[82]
+ PIN la_data_in[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2100.670 -4.000 2101.230 2.400 ;
+ END
+ END la_data_in[83]
+ PIN la_data_in[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2118.400 -4.000 2118.960 2.400 ;
+ END
+ END la_data_in[84]
+ PIN la_data_in[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2136.130 -4.000 2136.690 2.400 ;
+ END
+ END la_data_in[85]
+ PIN la_data_in[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2153.860 -4.000 2154.420 2.400 ;
+ END
+ END la_data_in[86]
+ PIN la_data_in[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2171.590 -4.000 2172.150 2.400 ;
+ END
+ END la_data_in[87]
+ PIN la_data_in[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2189.320 -4.000 2189.880 2.400 ;
+ END
+ END la_data_in[88]
+ PIN la_data_in[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2207.050 -4.000 2207.610 2.400 ;
+ END
+ END la_data_in[89]
+ PIN la_data_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 770.920 -4.000 771.480 2.400 ;
+ END
+ END la_data_in[8]
+ PIN la_data_in[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2224.780 -4.000 2225.340 2.400 ;
+ END
+ END la_data_in[90]
+ PIN la_data_in[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2242.510 -4.000 2243.070 2.400 ;
+ END
+ END la_data_in[91]
+ PIN la_data_in[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2260.240 -4.000 2260.800 2.400 ;
+ END
+ END la_data_in[92]
+ PIN la_data_in[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2277.970 -4.000 2278.530 2.400 ;
+ END
+ END la_data_in[93]
+ PIN la_data_in[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2295.700 -4.000 2296.260 2.400 ;
+ END
+ END la_data_in[94]
+ PIN la_data_in[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2313.430 -4.000 2313.990 2.400 ;
+ END
+ END la_data_in[95]
+ PIN la_data_in[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2331.160 -4.000 2331.720 2.400 ;
+ END
+ END la_data_in[96]
+ PIN la_data_in[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2348.890 -4.000 2349.450 2.400 ;
+ END
+ END la_data_in[97]
+ PIN la_data_in[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2366.620 -4.000 2367.180 2.400 ;
+ END
+ END la_data_in[98]
+ PIN la_data_in[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2384.350 -4.000 2384.910 2.400 ;
+ END
+ END la_data_in[99]
+ PIN la_data_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 788.650 -4.000 789.210 2.400 ;
+ END
+ END la_data_in[9]
+ PIN la_data_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 634.990 -4.000 635.550 2.400 ;
+ END
+ END la_data_out[0]
+ PIN la_data_out[100]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2407.990 -4.000 2408.550 2.400 ;
+ END
+ END la_data_out[100]
+ PIN la_data_out[101]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2425.720 -4.000 2426.280 2.400 ;
+ END
+ END la_data_out[101]
+ PIN la_data_out[102]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2443.450 -4.000 2444.010 2.400 ;
+ END
+ END la_data_out[102]
+ PIN la_data_out[103]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2461.180 -4.000 2461.740 2.400 ;
+ END
+ END la_data_out[103]
+ PIN la_data_out[104]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2478.910 -4.000 2479.470 2.400 ;
+ END
+ END la_data_out[104]
+ PIN la_data_out[105]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2496.640 -4.000 2497.200 2.400 ;
+ END
+ END la_data_out[105]
+ PIN la_data_out[106]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2514.370 -4.000 2514.930 2.400 ;
+ END
+ END la_data_out[106]
+ PIN la_data_out[107]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2532.100 -4.000 2532.660 2.400 ;
+ END
+ END la_data_out[107]
+ PIN la_data_out[108]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2549.830 -4.000 2550.390 2.400 ;
+ END
+ END la_data_out[108]
+ PIN la_data_out[109]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2567.560 -4.000 2568.120 2.400 ;
+ END
+ END la_data_out[109]
+ PIN la_data_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 812.290 -4.000 812.850 2.400 ;
+ END
+ END la_data_out[10]
+ PIN la_data_out[110]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2585.290 -4.000 2585.850 2.400 ;
+ END
+ END la_data_out[110]
+ PIN la_data_out[111]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2603.020 -4.000 2603.580 2.400 ;
+ END
+ END la_data_out[111]
+ PIN la_data_out[112]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2620.750 -4.000 2621.310 2.400 ;
+ END
+ END la_data_out[112]
+ PIN la_data_out[113]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2638.480 -4.000 2639.040 2.400 ;
+ END
+ END la_data_out[113]
+ PIN la_data_out[114]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2656.210 -4.000 2656.770 2.400 ;
+ END
+ END la_data_out[114]
+ PIN la_data_out[115]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2673.940 -4.000 2674.500 2.400 ;
+ END
+ END la_data_out[115]
+ PIN la_data_out[116]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2691.670 -4.000 2692.230 2.400 ;
+ END
+ END la_data_out[116]
+ PIN la_data_out[117]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2709.400 -4.000 2709.960 2.400 ;
+ END
+ END la_data_out[117]
+ PIN la_data_out[118]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2727.130 -4.000 2727.690 2.400 ;
+ END
+ END la_data_out[118]
+ PIN la_data_out[119]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2744.860 -4.000 2745.420 2.400 ;
+ END
+ END la_data_out[119]
+ PIN la_data_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 830.020 -4.000 830.580 2.400 ;
+ END
+ END la_data_out[11]
+ PIN la_data_out[120]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2762.590 -4.000 2763.150 2.400 ;
+ END
+ END la_data_out[120]
+ PIN la_data_out[121]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2780.320 -4.000 2780.880 2.400 ;
+ END
+ END la_data_out[121]
+ PIN la_data_out[122]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2798.050 -4.000 2798.610 2.400 ;
+ END
+ END la_data_out[122]
+ PIN la_data_out[123]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2815.780 -4.000 2816.340 2.400 ;
+ END
+ END la_data_out[123]
+ PIN la_data_out[124]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2833.510 -4.000 2834.070 2.400 ;
+ END
+ END la_data_out[124]
+ PIN la_data_out[125]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2851.240 -4.000 2851.800 2.400 ;
+ END
+ END la_data_out[125]
+ PIN la_data_out[126]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2868.970 -4.000 2869.530 2.400 ;
+ END
+ END la_data_out[126]
+ PIN la_data_out[127]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2886.700 -4.000 2887.260 2.400 ;
+ END
+ END la_data_out[127]
+ PIN la_data_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 847.750 -4.000 848.310 2.400 ;
+ END
+ END la_data_out[12]
+ PIN la_data_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 865.480 -4.000 866.040 2.400 ;
+ END
+ END la_data_out[13]
+ PIN la_data_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 883.210 -4.000 883.770 2.400 ;
+ END
+ END la_data_out[14]
+ PIN la_data_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 900.940 -4.000 901.500 2.400 ;
+ END
+ END la_data_out[15]
+ PIN la_data_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 918.670 -4.000 919.230 2.400 ;
+ END
+ END la_data_out[16]
+ PIN la_data_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 936.400 -4.000 936.960 2.400 ;
+ END
+ END la_data_out[17]
+ PIN la_data_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 954.130 -4.000 954.690 2.400 ;
+ END
+ END la_data_out[18]
+ PIN la_data_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 971.860 -4.000 972.420 2.400 ;
+ END
+ END la_data_out[19]
+ PIN la_data_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 652.720 -4.000 653.280 2.400 ;
+ END
+ END la_data_out[1]
+ PIN la_data_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 989.590 -4.000 990.150 2.400 ;
+ END
+ END la_data_out[20]
+ PIN la_data_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1007.320 -4.000 1007.880 2.400 ;
+ END
+ END la_data_out[21]
+ PIN la_data_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1025.050 -4.000 1025.610 2.400 ;
+ END
+ END la_data_out[22]
+ PIN la_data_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1042.780 -4.000 1043.340 2.400 ;
+ END
+ END la_data_out[23]
+ PIN la_data_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1060.510 -4.000 1061.070 2.400 ;
+ END
+ END la_data_out[24]
+ PIN la_data_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1078.240 -4.000 1078.800 2.400 ;
+ END
+ END la_data_out[25]
+ PIN la_data_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1095.970 -4.000 1096.530 2.400 ;
+ END
+ END la_data_out[26]
+ PIN la_data_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1113.700 -4.000 1114.260 2.400 ;
+ END
+ END la_data_out[27]
+ PIN la_data_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1131.430 -4.000 1131.990 2.400 ;
+ END
+ END la_data_out[28]
+ PIN la_data_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1149.160 -4.000 1149.720 2.400 ;
+ END
+ END la_data_out[29]
+ PIN la_data_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 670.450 -4.000 671.010 2.400 ;
+ END
+ END la_data_out[2]
+ PIN la_data_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1166.890 -4.000 1167.450 2.400 ;
+ END
+ END la_data_out[30]
+ PIN la_data_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1184.620 -4.000 1185.180 2.400 ;
+ END
+ END la_data_out[31]
+ PIN la_data_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1202.350 -4.000 1202.910 2.400 ;
+ END
+ END la_data_out[32]
+ PIN la_data_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1220.080 -4.000 1220.640 2.400 ;
+ END
+ END la_data_out[33]
+ PIN la_data_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1237.810 -4.000 1238.370 2.400 ;
+ END
+ END la_data_out[34]
+ PIN la_data_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1255.540 -4.000 1256.100 2.400 ;
+ END
+ END la_data_out[35]
+ PIN la_data_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1273.270 -4.000 1273.830 2.400 ;
+ END
+ END la_data_out[36]
+ PIN la_data_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1291.000 -4.000 1291.560 2.400 ;
+ END
+ END la_data_out[37]
+ PIN la_data_out[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1308.730 -4.000 1309.290 2.400 ;
+ END
+ END la_data_out[38]
+ PIN la_data_out[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1326.460 -4.000 1327.020 2.400 ;
+ END
+ END la_data_out[39]
+ PIN la_data_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 688.180 -4.000 688.740 2.400 ;
+ END
+ END la_data_out[3]
+ PIN la_data_out[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1344.190 -4.000 1344.750 2.400 ;
+ END
+ END la_data_out[40]
+ PIN la_data_out[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1361.920 -4.000 1362.480 2.400 ;
+ END
+ END la_data_out[41]
+ PIN la_data_out[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1379.650 -4.000 1380.210 2.400 ;
+ END
+ END la_data_out[42]
+ PIN la_data_out[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1397.380 -4.000 1397.940 2.400 ;
+ END
+ END la_data_out[43]
+ PIN la_data_out[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1415.110 -4.000 1415.670 2.400 ;
+ END
+ END la_data_out[44]
+ PIN la_data_out[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1432.840 -4.000 1433.400 2.400 ;
+ END
+ END la_data_out[45]
+ PIN la_data_out[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1450.570 -4.000 1451.130 2.400 ;
+ END
+ END la_data_out[46]
+ PIN la_data_out[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1468.300 -4.000 1468.860 2.400 ;
+ END
+ END la_data_out[47]
+ PIN la_data_out[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1486.030 -4.000 1486.590 2.400 ;
+ END
+ END la_data_out[48]
+ PIN la_data_out[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1503.760 -4.000 1504.320 2.400 ;
+ END
+ END la_data_out[49]
+ PIN la_data_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 705.910 -4.000 706.470 2.400 ;
+ END
+ END la_data_out[4]
+ PIN la_data_out[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1521.490 -4.000 1522.050 2.400 ;
+ END
+ END la_data_out[50]
+ PIN la_data_out[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1539.220 -4.000 1539.780 2.400 ;
+ END
+ END la_data_out[51]
+ PIN la_data_out[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1556.950 -4.000 1557.510 2.400 ;
+ END
+ END la_data_out[52]
+ PIN la_data_out[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1574.680 -4.000 1575.240 2.400 ;
+ END
+ END la_data_out[53]
+ PIN la_data_out[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1592.410 -4.000 1592.970 2.400 ;
+ END
+ END la_data_out[54]
+ PIN la_data_out[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1610.140 -4.000 1610.700 2.400 ;
+ END
+ END la_data_out[55]
+ PIN la_data_out[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1627.870 -4.000 1628.430 2.400 ;
+ END
+ END la_data_out[56]
+ PIN la_data_out[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1645.600 -4.000 1646.160 2.400 ;
+ END
+ END la_data_out[57]
+ PIN la_data_out[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1663.330 -4.000 1663.890 2.400 ;
+ END
+ END la_data_out[58]
+ PIN la_data_out[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1681.060 -4.000 1681.620 2.400 ;
+ END
+ END la_data_out[59]
+ PIN la_data_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 723.640 -4.000 724.200 2.400 ;
+ END
+ END la_data_out[5]
+ PIN la_data_out[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1698.790 -4.000 1699.350 2.400 ;
+ END
+ END la_data_out[60]
+ PIN la_data_out[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1716.520 -4.000 1717.080 2.400 ;
+ END
+ END la_data_out[61]
+ PIN la_data_out[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1734.250 -4.000 1734.810 2.400 ;
+ END
+ END la_data_out[62]
+ PIN la_data_out[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1751.980 -4.000 1752.540 2.400 ;
+ END
+ END la_data_out[63]
+ PIN la_data_out[64]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1769.710 -4.000 1770.270 2.400 ;
+ END
+ END la_data_out[64]
+ PIN la_data_out[65]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1787.440 -4.000 1788.000 2.400 ;
+ END
+ END la_data_out[65]
+ PIN la_data_out[66]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1805.170 -4.000 1805.730 2.400 ;
+ END
+ END la_data_out[66]
+ PIN la_data_out[67]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1822.900 -4.000 1823.460 2.400 ;
+ END
+ END la_data_out[67]
+ PIN la_data_out[68]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1840.630 -4.000 1841.190 2.400 ;
+ END
+ END la_data_out[68]
+ PIN la_data_out[69]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1858.360 -4.000 1858.920 2.400 ;
+ END
+ END la_data_out[69]
+ PIN la_data_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 741.370 -4.000 741.930 2.400 ;
+ END
+ END la_data_out[6]
+ PIN la_data_out[70]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1876.090 -4.000 1876.650 2.400 ;
+ END
+ END la_data_out[70]
+ PIN la_data_out[71]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1893.820 -4.000 1894.380 2.400 ;
+ END
+ END la_data_out[71]
+ PIN la_data_out[72]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1911.550 -4.000 1912.110 2.400 ;
+ END
+ END la_data_out[72]
+ PIN la_data_out[73]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1929.280 -4.000 1929.840 2.400 ;
+ END
+ END la_data_out[73]
+ PIN la_data_out[74]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1947.010 -4.000 1947.570 2.400 ;
+ END
+ END la_data_out[74]
+ PIN la_data_out[75]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1964.740 -4.000 1965.300 2.400 ;
+ END
+ END la_data_out[75]
+ PIN la_data_out[76]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1982.470 -4.000 1983.030 2.400 ;
+ END
+ END la_data_out[76]
+ PIN la_data_out[77]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2000.200 -4.000 2000.760 2.400 ;
+ END
+ END la_data_out[77]
+ PIN la_data_out[78]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2017.930 -4.000 2018.490 2.400 ;
+ END
+ END la_data_out[78]
+ PIN la_data_out[79]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2035.660 -4.000 2036.220 2.400 ;
+ END
+ END la_data_out[79]
+ PIN la_data_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 759.100 -4.000 759.660 2.400 ;
+ END
+ END la_data_out[7]
+ PIN la_data_out[80]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2053.390 -4.000 2053.950 2.400 ;
+ END
+ END la_data_out[80]
+ PIN la_data_out[81]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2071.120 -4.000 2071.680 2.400 ;
+ END
+ END la_data_out[81]
+ PIN la_data_out[82]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2088.850 -4.000 2089.410 2.400 ;
+ END
+ END la_data_out[82]
+ PIN la_data_out[83]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2106.580 -4.000 2107.140 2.400 ;
+ END
+ END la_data_out[83]
+ PIN la_data_out[84]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2124.310 -4.000 2124.870 2.400 ;
+ END
+ END la_data_out[84]
+ PIN la_data_out[85]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2142.040 -4.000 2142.600 2.400 ;
+ END
+ END la_data_out[85]
+ PIN la_data_out[86]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2159.770 -4.000 2160.330 2.400 ;
+ END
+ END la_data_out[86]
+ PIN la_data_out[87]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2177.500 -4.000 2178.060 2.400 ;
+ END
+ END la_data_out[87]
+ PIN la_data_out[88]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2195.230 -4.000 2195.790 2.400 ;
+ END
+ END la_data_out[88]
+ PIN la_data_out[89]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2212.960 -4.000 2213.520 2.400 ;
+ END
+ END la_data_out[89]
+ PIN la_data_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 776.830 -4.000 777.390 2.400 ;
+ END
+ END la_data_out[8]
+ PIN la_data_out[90]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2230.690 -4.000 2231.250 2.400 ;
+ END
+ END la_data_out[90]
+ PIN la_data_out[91]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2248.420 -4.000 2248.980 2.400 ;
+ END
+ END la_data_out[91]
+ PIN la_data_out[92]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2266.150 -4.000 2266.710 2.400 ;
+ END
+ END la_data_out[92]
+ PIN la_data_out[93]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2283.880 -4.000 2284.440 2.400 ;
+ END
+ END la_data_out[93]
+ PIN la_data_out[94]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2301.610 -4.000 2302.170 2.400 ;
+ END
+ END la_data_out[94]
+ PIN la_data_out[95]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2319.340 -4.000 2319.900 2.400 ;
+ END
+ END la_data_out[95]
+ PIN la_data_out[96]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2337.070 -4.000 2337.630 2.400 ;
+ END
+ END la_data_out[96]
+ PIN la_data_out[97]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2354.800 -4.000 2355.360 2.400 ;
+ END
+ END la_data_out[97]
+ PIN la_data_out[98]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2372.530 -4.000 2373.090 2.400 ;
+ END
+ END la_data_out[98]
+ PIN la_data_out[99]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2390.260 -4.000 2390.820 2.400 ;
+ END
+ END la_data_out[99]
+ PIN la_data_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 794.560 -4.000 795.120 2.400 ;
+ END
+ END la_data_out[9]
+ PIN la_oenb[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 640.900 -4.000 641.460 2.400 ;
+ END
+ END la_oenb[0]
+ PIN la_oenb[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2413.900 -4.000 2414.460 2.400 ;
+ END
+ END la_oenb[100]
+ PIN la_oenb[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2431.630 -4.000 2432.190 2.400 ;
+ END
+ END la_oenb[101]
+ PIN la_oenb[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2449.360 -4.000 2449.920 2.400 ;
+ END
+ END la_oenb[102]
+ PIN la_oenb[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2467.090 -4.000 2467.650 2.400 ;
+ END
+ END la_oenb[103]
+ PIN la_oenb[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2484.820 -4.000 2485.380 2.400 ;
+ END
+ END la_oenb[104]
+ PIN la_oenb[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2502.550 -4.000 2503.110 2.400 ;
+ END
+ END la_oenb[105]
+ PIN la_oenb[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2520.280 -4.000 2520.840 2.400 ;
+ END
+ END la_oenb[106]
+ PIN la_oenb[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2538.010 -4.000 2538.570 2.400 ;
+ END
+ END la_oenb[107]
+ PIN la_oenb[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2555.740 -4.000 2556.300 2.400 ;
+ END
+ END la_oenb[108]
+ PIN la_oenb[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2573.470 -4.000 2574.030 2.400 ;
+ END
+ END la_oenb[109]
+ PIN la_oenb[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 818.200 -4.000 818.760 2.400 ;
+ END
+ END la_oenb[10]
+ PIN la_oenb[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2591.200 -4.000 2591.760 2.400 ;
+ END
+ END la_oenb[110]
+ PIN la_oenb[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2608.930 -4.000 2609.490 2.400 ;
+ END
+ END la_oenb[111]
+ PIN la_oenb[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2626.660 -4.000 2627.220 2.400 ;
+ END
+ END la_oenb[112]
+ PIN la_oenb[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2644.390 -4.000 2644.950 2.400 ;
+ END
+ END la_oenb[113]
+ PIN la_oenb[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2662.120 -4.000 2662.680 2.400 ;
+ END
+ END la_oenb[114]
+ PIN la_oenb[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2679.850 -4.000 2680.410 2.400 ;
+ END
+ END la_oenb[115]
+ PIN la_oenb[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2697.580 -4.000 2698.140 2.400 ;
+ END
+ END la_oenb[116]
+ PIN la_oenb[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2715.310 -4.000 2715.870 2.400 ;
+ END
+ END la_oenb[117]
+ PIN la_oenb[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2733.040 -4.000 2733.600 2.400 ;
+ END
+ END la_oenb[118]
+ PIN la_oenb[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2750.770 -4.000 2751.330 2.400 ;
+ END
+ END la_oenb[119]
+ PIN la_oenb[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 835.930 -4.000 836.490 2.400 ;
+ END
+ END la_oenb[11]
+ PIN la_oenb[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2768.500 -4.000 2769.060 2.400 ;
+ END
+ END la_oenb[120]
+ PIN la_oenb[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2786.230 -4.000 2786.790 2.400 ;
+ END
+ END la_oenb[121]
+ PIN la_oenb[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2803.960 -4.000 2804.520 2.400 ;
+ END
+ END la_oenb[122]
+ PIN la_oenb[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2821.690 -4.000 2822.250 2.400 ;
+ END
+ END la_oenb[123]
+ PIN la_oenb[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2839.420 -4.000 2839.980 2.400 ;
+ END
+ END la_oenb[124]
+ PIN la_oenb[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2857.150 -4.000 2857.710 2.400 ;
+ END
+ END la_oenb[125]
+ PIN la_oenb[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2874.880 -4.000 2875.440 2.400 ;
+ END
+ END la_oenb[126]
+ PIN la_oenb[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2892.610 -4.000 2893.170 2.400 ;
+ END
+ END la_oenb[127]
+ PIN la_oenb[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 853.660 -4.000 854.220 2.400 ;
+ END
+ END la_oenb[12]
+ PIN la_oenb[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 871.390 -4.000 871.950 2.400 ;
+ END
+ END la_oenb[13]
+ PIN la_oenb[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 889.120 -4.000 889.680 2.400 ;
+ END
+ END la_oenb[14]
+ PIN la_oenb[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 906.850 -4.000 907.410 2.400 ;
+ END
+ END la_oenb[15]
+ PIN la_oenb[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 924.580 -4.000 925.140 2.400 ;
+ END
+ END la_oenb[16]
+ PIN la_oenb[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 942.310 -4.000 942.870 2.400 ;
+ END
+ END la_oenb[17]
+ PIN la_oenb[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 960.040 -4.000 960.600 2.400 ;
+ END
+ END la_oenb[18]
+ PIN la_oenb[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 977.770 -4.000 978.330 2.400 ;
+ END
+ END la_oenb[19]
+ PIN la_oenb[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 658.630 -4.000 659.190 2.400 ;
+ END
+ END la_oenb[1]
+ PIN la_oenb[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 995.500 -4.000 996.060 2.400 ;
+ END
+ END la_oenb[20]
+ PIN la_oenb[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1013.230 -4.000 1013.790 2.400 ;
+ END
+ END la_oenb[21]
+ PIN la_oenb[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1030.960 -4.000 1031.520 2.400 ;
+ END
+ END la_oenb[22]
+ PIN la_oenb[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1048.690 -4.000 1049.250 2.400 ;
+ END
+ END la_oenb[23]
+ PIN la_oenb[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1066.420 -4.000 1066.980 2.400 ;
+ END
+ END la_oenb[24]
+ PIN la_oenb[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1084.150 -4.000 1084.710 2.400 ;
+ END
+ END la_oenb[25]
+ PIN la_oenb[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1101.880 -4.000 1102.440 2.400 ;
+ END
+ END la_oenb[26]
+ PIN la_oenb[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1119.610 -4.000 1120.170 2.400 ;
+ END
+ END la_oenb[27]
+ PIN la_oenb[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1137.340 -4.000 1137.900 2.400 ;
+ END
+ END la_oenb[28]
+ PIN la_oenb[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1155.070 -4.000 1155.630 2.400 ;
+ END
+ END la_oenb[29]
+ PIN la_oenb[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 676.360 -4.000 676.920 2.400 ;
+ END
+ END la_oenb[2]
+ PIN la_oenb[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1172.800 -4.000 1173.360 2.400 ;
+ END
+ END la_oenb[30]
+ PIN la_oenb[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1190.530 -4.000 1191.090 2.400 ;
+ END
+ END la_oenb[31]
+ PIN la_oenb[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1208.260 -4.000 1208.820 2.400 ;
+ END
+ END la_oenb[32]
+ PIN la_oenb[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1225.990 -4.000 1226.550 2.400 ;
+ END
+ END la_oenb[33]
+ PIN la_oenb[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1243.720 -4.000 1244.280 2.400 ;
+ END
+ END la_oenb[34]
+ PIN la_oenb[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1261.450 -4.000 1262.010 2.400 ;
+ END
+ END la_oenb[35]
+ PIN la_oenb[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1279.180 -4.000 1279.740 2.400 ;
+ END
+ END la_oenb[36]
+ PIN la_oenb[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1296.910 -4.000 1297.470 2.400 ;
+ END
+ END la_oenb[37]
+ PIN la_oenb[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1314.640 -4.000 1315.200 2.400 ;
+ END
+ END la_oenb[38]
+ PIN la_oenb[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1332.370 -4.000 1332.930 2.400 ;
+ END
+ END la_oenb[39]
+ PIN la_oenb[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 694.090 -4.000 694.650 2.400 ;
+ END
+ END la_oenb[3]
+ PIN la_oenb[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1350.100 -4.000 1350.660 2.400 ;
+ END
+ END la_oenb[40]
+ PIN la_oenb[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1367.830 -4.000 1368.390 2.400 ;
+ END
+ END la_oenb[41]
+ PIN la_oenb[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1385.560 -4.000 1386.120 2.400 ;
+ END
+ END la_oenb[42]
+ PIN la_oenb[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1403.290 -4.000 1403.850 2.400 ;
+ END
+ END la_oenb[43]
+ PIN la_oenb[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1421.020 -4.000 1421.580 2.400 ;
+ END
+ END la_oenb[44]
+ PIN la_oenb[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1438.750 -4.000 1439.310 2.400 ;
+ END
+ END la_oenb[45]
+ PIN la_oenb[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1456.480 -4.000 1457.040 2.400 ;
+ END
+ END la_oenb[46]
+ PIN la_oenb[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1474.210 -4.000 1474.770 2.400 ;
+ END
+ END la_oenb[47]
+ PIN la_oenb[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1491.940 -4.000 1492.500 2.400 ;
+ END
+ END la_oenb[48]
+ PIN la_oenb[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1509.670 -4.000 1510.230 2.400 ;
+ END
+ END la_oenb[49]
+ PIN la_oenb[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 711.820 -4.000 712.380 2.400 ;
+ END
+ END la_oenb[4]
+ PIN la_oenb[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1527.400 -4.000 1527.960 2.400 ;
+ END
+ END la_oenb[50]
+ PIN la_oenb[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1545.130 -4.000 1545.690 2.400 ;
+ END
+ END la_oenb[51]
+ PIN la_oenb[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1562.860 -4.000 1563.420 2.400 ;
+ END
+ END la_oenb[52]
+ PIN la_oenb[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1580.590 -4.000 1581.150 2.400 ;
+ END
+ END la_oenb[53]
+ PIN la_oenb[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1598.320 -4.000 1598.880 2.400 ;
+ END
+ END la_oenb[54]
+ PIN la_oenb[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1616.050 -4.000 1616.610 2.400 ;
+ END
+ END la_oenb[55]
+ PIN la_oenb[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1633.780 -4.000 1634.340 2.400 ;
+ END
+ END la_oenb[56]
+ PIN la_oenb[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1651.510 -4.000 1652.070 2.400 ;
+ END
+ END la_oenb[57]
+ PIN la_oenb[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1669.240 -4.000 1669.800 2.400 ;
+ END
+ END la_oenb[58]
+ PIN la_oenb[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1686.970 -4.000 1687.530 2.400 ;
+ END
+ END la_oenb[59]
+ PIN la_oenb[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 729.550 -4.000 730.110 2.400 ;
+ END
+ END la_oenb[5]
+ PIN la_oenb[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1704.700 -4.000 1705.260 2.400 ;
+ END
+ END la_oenb[60]
+ PIN la_oenb[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1722.430 -4.000 1722.990 2.400 ;
+ END
+ END la_oenb[61]
+ PIN la_oenb[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1740.160 -4.000 1740.720 2.400 ;
+ END
+ END la_oenb[62]
+ PIN la_oenb[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1757.890 -4.000 1758.450 2.400 ;
+ END
+ END la_oenb[63]
+ PIN la_oenb[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1775.620 -4.000 1776.180 2.400 ;
+ END
+ END la_oenb[64]
+ PIN la_oenb[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1793.350 -4.000 1793.910 2.400 ;
+ END
+ END la_oenb[65]
+ PIN la_oenb[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1811.080 -4.000 1811.640 2.400 ;
+ END
+ END la_oenb[66]
+ PIN la_oenb[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1828.810 -4.000 1829.370 2.400 ;
+ END
+ END la_oenb[67]
+ PIN la_oenb[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1846.540 -4.000 1847.100 2.400 ;
+ END
+ END la_oenb[68]
+ PIN la_oenb[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1864.270 -4.000 1864.830 2.400 ;
+ END
+ END la_oenb[69]
+ PIN la_oenb[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 747.280 -4.000 747.840 2.400 ;
+ END
+ END la_oenb[6]
+ PIN la_oenb[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1882.000 -4.000 1882.560 2.400 ;
+ END
+ END la_oenb[70]
+ PIN la_oenb[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1899.730 -4.000 1900.290 2.400 ;
+ END
+ END la_oenb[71]
+ PIN la_oenb[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1917.460 -4.000 1918.020 2.400 ;
+ END
+ END la_oenb[72]
+ PIN la_oenb[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1935.190 -4.000 1935.750 2.400 ;
+ END
+ END la_oenb[73]
+ PIN la_oenb[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1952.920 -4.000 1953.480 2.400 ;
+ END
+ END la_oenb[74]
+ PIN la_oenb[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1970.650 -4.000 1971.210 2.400 ;
+ END
+ END la_oenb[75]
+ PIN la_oenb[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1988.380 -4.000 1988.940 2.400 ;
+ END
+ END la_oenb[76]
+ PIN la_oenb[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2006.110 -4.000 2006.670 2.400 ;
+ END
+ END la_oenb[77]
+ PIN la_oenb[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2023.840 -4.000 2024.400 2.400 ;
+ END
+ END la_oenb[78]
+ PIN la_oenb[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2041.570 -4.000 2042.130 2.400 ;
+ END
+ END la_oenb[79]
+ PIN la_oenb[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 765.010 -4.000 765.570 2.400 ;
+ END
+ END la_oenb[7]
+ PIN la_oenb[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2059.300 -4.000 2059.860 2.400 ;
+ END
+ END la_oenb[80]
+ PIN la_oenb[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2077.030 -4.000 2077.590 2.400 ;
+ END
+ END la_oenb[81]
+ PIN la_oenb[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2094.760 -4.000 2095.320 2.400 ;
+ END
+ END la_oenb[82]
+ PIN la_oenb[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2112.490 -4.000 2113.050 2.400 ;
+ END
+ END la_oenb[83]
+ PIN la_oenb[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2130.220 -4.000 2130.780 2.400 ;
+ END
+ END la_oenb[84]
+ PIN la_oenb[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2147.950 -4.000 2148.510 2.400 ;
+ END
+ END la_oenb[85]
+ PIN la_oenb[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2165.680 -4.000 2166.240 2.400 ;
+ END
+ END la_oenb[86]
+ PIN la_oenb[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2183.410 -4.000 2183.970 2.400 ;
+ END
+ END la_oenb[87]
+ PIN la_oenb[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2201.140 -4.000 2201.700 2.400 ;
+ END
+ END la_oenb[88]
+ PIN la_oenb[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2218.870 -4.000 2219.430 2.400 ;
+ END
+ END la_oenb[89]
+ PIN la_oenb[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 782.740 -4.000 783.300 2.400 ;
+ END
+ END la_oenb[8]
+ PIN la_oenb[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2236.600 -4.000 2237.160 2.400 ;
+ END
+ END la_oenb[90]
+ PIN la_oenb[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2254.330 -4.000 2254.890 2.400 ;
+ END
+ END la_oenb[91]
+ PIN la_oenb[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2272.060 -4.000 2272.620 2.400 ;
+ END
+ END la_oenb[92]
+ PIN la_oenb[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2289.790 -4.000 2290.350 2.400 ;
+ END
+ END la_oenb[93]
+ PIN la_oenb[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2307.520 -4.000 2308.080 2.400 ;
+ END
+ END la_oenb[94]
+ PIN la_oenb[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2325.250 -4.000 2325.810 2.400 ;
+ END
+ END la_oenb[95]
+ PIN la_oenb[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2342.980 -4.000 2343.540 2.400 ;
+ END
+ END la_oenb[96]
+ PIN la_oenb[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2360.710 -4.000 2361.270 2.400 ;
+ END
+ END la_oenb[97]
+ PIN la_oenb[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2378.440 -4.000 2379.000 2.400 ;
+ END
+ END la_oenb[98]
+ PIN la_oenb[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2396.170 -4.000 2396.730 2.400 ;
+ END
+ END la_oenb[99]
+ PIN la_oenb[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 800.470 -4.000 801.030 2.400 ;
+ END
+ END la_oenb[9]
+ PIN user_clock2
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2898.520 -4.000 2899.080 2.400 ;
+ END
+ END user_clock2
+ PIN user_irq[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2904.430 -4.000 2904.990 2.400 ;
+ END
+ END user_irq[0]
+ PIN user_irq[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2910.340 -4.000 2910.900 2.400 ;
+ END
+ END user_irq[1]
+ PIN user_irq[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2916.250 -4.000 2916.810 2.400 ;
+ END
+ END user_irq[2]
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 3198.920 2920.000 3222.920 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 3148.920 2920.000 3172.920 ;
+ END
+ END vccd1
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 3219.210 8.300 3243.210 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 3169.210 8.300 3193.210 ;
+ END
+ END vccd2
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 2702.810 2920.000 2726.810 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 2752.810 2920.000 2776.810 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 1176.150 2920.000 1200.150 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 1126.150 2920.000 1150.150 ;
+ END
+ END vdda1
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1024.440 8.300 1048.440 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1074.440 8.300 1098.440 ;
+ END
+ END vdda2
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2602.970 3511.700 2626.970 3520.000 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2552.970 3511.700 2576.970 3520.000 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 734.150 2920.000 758.150 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 684.150 2920.000 708.150 ;
+ END
+ END vssa1
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 2797.210 8.300 2821.210 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 2747.210 8.300 2771.210 ;
+ END
+ END vssa2
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 957.150 2920.000 981.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2911.700 907.150 2920.000 931.150 ;
+ END
+ END vssd1
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 864.440 8.300 888.440 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 814.440 8.300 838.440 ;
+ END
+ END vssd2
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2.620 -4.000 3.180 2.400 ;
+ END
+ END wb_clk_i
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 8.530 -4.000 9.090 2.400 ;
+ END
+ END wb_rst_i
+ PIN wbs_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 14.440 -4.000 15.000 2.400 ;
+ END
+ END wbs_ack_o
+ PIN wbs_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 38.080 -4.000 38.640 2.400 ;
+ END
+ END wbs_adr_i[0]
+ PIN wbs_adr_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 239.020 -4.000 239.580 2.400 ;
+ END
+ END wbs_adr_i[10]
+ PIN wbs_adr_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 256.750 -4.000 257.310 2.400 ;
+ END
+ END wbs_adr_i[11]
+ PIN wbs_adr_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 274.480 -4.000 275.040 2.400 ;
+ END
+ END wbs_adr_i[12]
+ PIN wbs_adr_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.210 -4.000 292.770 2.400 ;
+ END
+ END wbs_adr_i[13]
+ PIN wbs_adr_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 309.940 -4.000 310.500 2.400 ;
+ END
+ END wbs_adr_i[14]
+ PIN wbs_adr_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.670 -4.000 328.230 2.400 ;
+ END
+ END wbs_adr_i[15]
+ PIN wbs_adr_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.400 -4.000 345.960 2.400 ;
+ END
+ END wbs_adr_i[16]
+ PIN wbs_adr_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 363.130 -4.000 363.690 2.400 ;
+ END
+ END wbs_adr_i[17]
+ PIN wbs_adr_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 380.860 -4.000 381.420 2.400 ;
+ END
+ END wbs_adr_i[18]
+ PIN wbs_adr_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 398.590 -4.000 399.150 2.400 ;
+ END
+ END wbs_adr_i[19]
+ PIN wbs_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 61.720 -4.000 62.280 2.400 ;
+ END
+ END wbs_adr_i[1]
+ PIN wbs_adr_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.320 -4.000 416.880 2.400 ;
+ END
+ END wbs_adr_i[20]
+ PIN wbs_adr_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.050 -4.000 434.610 2.400 ;
+ END
+ END wbs_adr_i[21]
+ PIN wbs_adr_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 451.780 -4.000 452.340 2.400 ;
+ END
+ END wbs_adr_i[22]
+ PIN wbs_adr_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.510 -4.000 470.070 2.400 ;
+ END
+ END wbs_adr_i[23]
+ PIN wbs_adr_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 487.240 -4.000 487.800 2.400 ;
+ END
+ END wbs_adr_i[24]
+ PIN wbs_adr_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 504.970 -4.000 505.530 2.400 ;
+ END
+ END wbs_adr_i[25]
+ PIN wbs_adr_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 522.700 -4.000 523.260 2.400 ;
+ END
+ END wbs_adr_i[26]
+ PIN wbs_adr_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 540.430 -4.000 540.990 2.400 ;
+ END
+ END wbs_adr_i[27]
+ PIN wbs_adr_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 558.160 -4.000 558.720 2.400 ;
+ END
+ END wbs_adr_i[28]
+ PIN wbs_adr_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 575.890 -4.000 576.450 2.400 ;
+ END
+ END wbs_adr_i[29]
+ PIN wbs_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 85.360 -4.000 85.920 2.400 ;
+ END
+ END wbs_adr_i[2]
+ PIN wbs_adr_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 593.620 -4.000 594.180 2.400 ;
+ END
+ END wbs_adr_i[30]
+ PIN wbs_adr_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 611.350 -4.000 611.910 2.400 ;
+ END
+ END wbs_adr_i[31]
+ PIN wbs_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 109.000 -4.000 109.560 2.400 ;
+ END
+ END wbs_adr_i[3]
+ PIN wbs_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 132.640 -4.000 133.200 2.400 ;
+ END
+ END wbs_adr_i[4]
+ PIN wbs_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 150.370 -4.000 150.930 2.400 ;
+ END
+ END wbs_adr_i[5]
+ PIN wbs_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 168.100 -4.000 168.660 2.400 ;
+ END
+ END wbs_adr_i[6]
+ PIN wbs_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 185.830 -4.000 186.390 2.400 ;
+ END
+ END wbs_adr_i[7]
+ PIN wbs_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 203.560 -4.000 204.120 2.400 ;
+ END
+ END wbs_adr_i[8]
+ PIN wbs_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 221.290 -4.000 221.850 2.400 ;
+ END
+ END wbs_adr_i[9]
+ PIN wbs_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 20.350 -4.000 20.910 2.400 ;
+ END
+ END wbs_cyc_i
+ PIN wbs_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 43.990 -4.000 44.550 2.400 ;
+ END
+ END wbs_dat_i[0]
+ PIN wbs_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 244.930 -4.000 245.490 2.400 ;
+ END
+ END wbs_dat_i[10]
+ PIN wbs_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 262.660 -4.000 263.220 2.400 ;
+ END
+ END wbs_dat_i[11]
+ PIN wbs_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 280.390 -4.000 280.950 2.400 ;
+ END
+ END wbs_dat_i[12]
+ PIN wbs_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 298.120 -4.000 298.680 2.400 ;
+ END
+ END wbs_dat_i[13]
+ PIN wbs_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 315.850 -4.000 316.410 2.400 ;
+ END
+ END wbs_dat_i[14]
+ PIN wbs_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 333.580 -4.000 334.140 2.400 ;
+ END
+ END wbs_dat_i[15]
+ PIN wbs_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.310 -4.000 351.870 2.400 ;
+ END
+ END wbs_dat_i[16]
+ PIN wbs_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 369.040 -4.000 369.600 2.400 ;
+ END
+ END wbs_dat_i[17]
+ PIN wbs_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 386.770 -4.000 387.330 2.400 ;
+ END
+ END wbs_dat_i[18]
+ PIN wbs_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 404.500 -4.000 405.060 2.400 ;
+ END
+ END wbs_dat_i[19]
+ PIN wbs_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 67.630 -4.000 68.190 2.400 ;
+ END
+ END wbs_dat_i[1]
+ PIN wbs_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 422.230 -4.000 422.790 2.400 ;
+ END
+ END wbs_dat_i[20]
+ PIN wbs_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 439.960 -4.000 440.520 2.400 ;
+ END
+ END wbs_dat_i[21]
+ PIN wbs_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 457.690 -4.000 458.250 2.400 ;
+ END
+ END wbs_dat_i[22]
+ PIN wbs_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 475.420 -4.000 475.980 2.400 ;
+ END
+ END wbs_dat_i[23]
+ PIN wbs_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 493.150 -4.000 493.710 2.400 ;
+ END
+ END wbs_dat_i[24]
+ PIN wbs_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 510.880 -4.000 511.440 2.400 ;
+ END
+ END wbs_dat_i[25]
+ PIN wbs_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 528.610 -4.000 529.170 2.400 ;
+ END
+ END wbs_dat_i[26]
+ PIN wbs_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 546.340 -4.000 546.900 2.400 ;
+ END
+ END wbs_dat_i[27]
+ PIN wbs_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 564.070 -4.000 564.630 2.400 ;
+ END
+ END wbs_dat_i[28]
+ PIN wbs_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 581.800 -4.000 582.360 2.400 ;
+ END
+ END wbs_dat_i[29]
+ PIN wbs_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 91.270 -4.000 91.830 2.400 ;
+ END
+ END wbs_dat_i[2]
+ PIN wbs_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 599.530 -4.000 600.090 2.400 ;
+ END
+ END wbs_dat_i[30]
+ PIN wbs_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 617.260 -4.000 617.820 2.400 ;
+ END
+ END wbs_dat_i[31]
+ PIN wbs_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 114.910 -4.000 115.470 2.400 ;
+ END
+ END wbs_dat_i[3]
+ PIN wbs_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 138.550 -4.000 139.110 2.400 ;
+ END
+ END wbs_dat_i[4]
+ PIN wbs_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 156.280 -4.000 156.840 2.400 ;
+ END
+ END wbs_dat_i[5]
+ PIN wbs_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 174.010 -4.000 174.570 2.400 ;
+ END
+ END wbs_dat_i[6]
+ PIN wbs_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 191.740 -4.000 192.300 2.400 ;
+ END
+ END wbs_dat_i[7]
+ PIN wbs_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.470 -4.000 210.030 2.400 ;
+ END
+ END wbs_dat_i[8]
+ PIN wbs_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 227.200 -4.000 227.760 2.400 ;
+ END
+ END wbs_dat_i[9]
+ PIN wbs_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 49.900 -4.000 50.460 2.400 ;
+ END
+ END wbs_dat_o[0]
+ PIN wbs_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 250.840 -4.000 251.400 2.400 ;
+ END
+ END wbs_dat_o[10]
+ PIN wbs_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 268.570 -4.000 269.130 2.400 ;
+ END
+ END wbs_dat_o[11]
+ PIN wbs_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 286.300 -4.000 286.860 2.400 ;
+ END
+ END wbs_dat_o[12]
+ PIN wbs_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 304.030 -4.000 304.590 2.400 ;
+ END
+ END wbs_dat_o[13]
+ PIN wbs_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 321.760 -4.000 322.320 2.400 ;
+ END
+ END wbs_dat_o[14]
+ PIN wbs_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 339.490 -4.000 340.050 2.400 ;
+ END
+ END wbs_dat_o[15]
+ PIN wbs_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 357.220 -4.000 357.780 2.400 ;
+ END
+ END wbs_dat_o[16]
+ PIN wbs_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.950 -4.000 375.510 2.400 ;
+ END
+ END wbs_dat_o[17]
+ PIN wbs_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 392.680 -4.000 393.240 2.400 ;
+ END
+ END wbs_dat_o[18]
+ PIN wbs_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 410.410 -4.000 410.970 2.400 ;
+ END
+ END wbs_dat_o[19]
+ PIN wbs_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 73.540 -4.000 74.100 2.400 ;
+ END
+ END wbs_dat_o[1]
+ PIN wbs_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 428.140 -4.000 428.700 2.400 ;
+ END
+ END wbs_dat_o[20]
+ PIN wbs_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.870 -4.000 446.430 2.400 ;
+ END
+ END wbs_dat_o[21]
+ PIN wbs_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 463.600 -4.000 464.160 2.400 ;
+ END
+ END wbs_dat_o[22]
+ PIN wbs_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 481.330 -4.000 481.890 2.400 ;
+ END
+ END wbs_dat_o[23]
+ PIN wbs_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 499.060 -4.000 499.620 2.400 ;
+ END
+ END wbs_dat_o[24]
+ PIN wbs_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 516.790 -4.000 517.350 2.400 ;
+ END
+ END wbs_dat_o[25]
+ PIN wbs_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 534.520 -4.000 535.080 2.400 ;
+ END
+ END wbs_dat_o[26]
+ PIN wbs_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 552.250 -4.000 552.810 2.400 ;
+ END
+ END wbs_dat_o[27]
+ PIN wbs_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 569.980 -4.000 570.540 2.400 ;
+ END
+ END wbs_dat_o[28]
+ PIN wbs_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 587.710 -4.000 588.270 2.400 ;
+ END
+ END wbs_dat_o[29]
+ PIN wbs_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 97.180 -4.000 97.740 2.400 ;
+ END
+ END wbs_dat_o[2]
+ PIN wbs_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 605.440 -4.000 606.000 2.400 ;
+ END
+ END wbs_dat_o[30]
+ PIN wbs_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 623.170 -4.000 623.730 2.400 ;
+ END
+ END wbs_dat_o[31]
+ PIN wbs_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 120.820 -4.000 121.380 2.400 ;
+ END
+ END wbs_dat_o[3]
+ PIN wbs_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 144.460 -4.000 145.020 2.400 ;
+ END
+ END wbs_dat_o[4]
+ PIN wbs_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 162.190 -4.000 162.750 2.400 ;
+ END
+ END wbs_dat_o[5]
+ PIN wbs_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 179.920 -4.000 180.480 2.400 ;
+ END
+ END wbs_dat_o[6]
+ PIN wbs_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 197.650 -4.000 198.210 2.400 ;
+ END
+ END wbs_dat_o[7]
+ PIN wbs_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 215.380 -4.000 215.940 2.400 ;
+ END
+ END wbs_dat_o[8]
+ PIN wbs_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 233.110 -4.000 233.670 2.400 ;
+ END
+ END wbs_dat_o[9]
+ PIN wbs_sel_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 55.810 -4.000 56.370 2.400 ;
+ END
+ END wbs_sel_i[0]
+ PIN wbs_sel_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 79.450 -4.000 80.010 2.400 ;
+ END
+ END wbs_sel_i[1]
+ PIN wbs_sel_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 103.090 -4.000 103.650 2.400 ;
+ END
+ END wbs_sel_i[2]
+ PIN wbs_sel_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 126.730 -4.000 127.290 2.400 ;
+ END
+ END wbs_sel_i[3]
+ PIN wbs_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 26.260 -4.000 26.820 2.400 ;
+ END
+ END wbs_stb_i
+ PIN wbs_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 32.170 -4.000 32.730 2.400 ;
+ END
+ END wbs_we_i
+END user_analog_project_wrapper
+END LIBRARY
+
diff --git a/caravel/lef/user_project_wrapper_empty.lef b/caravel/lef/user_project_wrapper_empty.lef
new file mode 100644
index 0000000..bd3a60f
--- /dev/null
+++ b/caravel/lef/user_project_wrapper_empty.lef
@@ -0,0 +1,7660 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO user_project_wrapper
+ CLASS BLOCK ;
+ FOREIGN user_project_wrapper ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 2920.000 BY 3520.000 ;
+ PIN analog_io[0]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1426.380 2924.800 1427.580 ;
+ END
+ END analog_io[0]
+ PIN analog_io[10]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2230.490 3517.600 2231.050 3524.800 ;
+ END
+ END analog_io[10]
+ PIN analog_io[11]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1905.730 3517.600 1906.290 3524.800 ;
+ END
+ END analog_io[11]
+ PIN analog_io[12]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1581.430 3517.600 1581.990 3524.800 ;
+ END
+ END analog_io[12]
+ PIN analog_io[13]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1257.130 3517.600 1257.690 3524.800 ;
+ END
+ END analog_io[13]
+ PIN analog_io[14]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 932.370 3517.600 932.930 3524.800 ;
+ END
+ END analog_io[14]
+ PIN analog_io[15]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 608.070 3517.600 608.630 3524.800 ;
+ END
+ END analog_io[15]
+ PIN analog_io[16]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 283.770 3517.600 284.330 3524.800 ;
+ END
+ END analog_io[16]
+ PIN analog_io[17]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3486.100 2.400 3487.300 ;
+ END
+ END analog_io[17]
+ PIN analog_io[18]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3224.980 2.400 3226.180 ;
+ END
+ END analog_io[18]
+ PIN analog_io[19]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2964.540 2.400 2965.740 ;
+ END
+ END analog_io[19]
+ PIN analog_io[1]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1692.260 2924.800 1693.460 ;
+ END
+ END analog_io[1]
+ PIN analog_io[20]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2703.420 2.400 2704.620 ;
+ END
+ END analog_io[20]
+ PIN analog_io[21]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2442.980 2.400 2444.180 ;
+ END
+ END analog_io[21]
+ PIN analog_io[22]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2182.540 2.400 2183.740 ;
+ END
+ END analog_io[22]
+ PIN analog_io[23]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1921.420 2.400 1922.620 ;
+ END
+ END analog_io[23]
+ PIN analog_io[24]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1660.980 2.400 1662.180 ;
+ END
+ END analog_io[24]
+ PIN analog_io[25]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1399.860 2.400 1401.060 ;
+ END
+ END analog_io[25]
+ PIN analog_io[26]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1139.420 2.400 1140.620 ;
+ END
+ END analog_io[26]
+ PIN analog_io[27]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 878.980 2.400 880.180 ;
+ END
+ END analog_io[27]
+ PIN analog_io[28]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 617.860 2.400 619.060 ;
+ END
+ END analog_io[28]
+ PIN analog_io[2]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1958.140 2924.800 1959.340 ;
+ END
+ END analog_io[2]
+ PIN analog_io[3]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2223.340 2924.800 2224.540 ;
+ END
+ END analog_io[3]
+ PIN analog_io[4]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2489.220 2924.800 2490.420 ;
+ END
+ END analog_io[4]
+ PIN analog_io[5]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2755.100 2924.800 2756.300 ;
+ END
+ END analog_io[5]
+ PIN analog_io[6]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3020.300 2924.800 3021.500 ;
+ END
+ END analog_io[6]
+ PIN analog_io[7]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3286.180 2924.800 3287.380 ;
+ END
+ END analog_io[7]
+ PIN analog_io[8]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2879.090 3517.600 2879.650 3524.800 ;
+ END
+ END analog_io[8]
+ PIN analog_io[9]
+ DIRECTION INOUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2554.790 3517.600 2555.350 3524.800 ;
+ END
+ END analog_io[9]
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 32.380 2924.800 33.580 ;
+ END
+ END io_in[0]
+ PIN io_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 98.340 2924.800 99.540 ;
+ END
+ END io_out[0]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2289.980 2924.800 2291.180 ;
+ END
+ END io_in[10]
+ PIN io_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2356.620 2924.800 2357.820 ;
+ END
+ END io_out[10]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2555.860 2924.800 2557.060 ;
+ END
+ END io_in[11]
+ PIN io_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2621.820 2924.800 2623.020 ;
+ END
+ END io_out[11]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2821.060 2924.800 2822.260 ;
+ END
+ END io_in[12]
+ PIN io_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2887.700 2924.800 2888.900 ;
+ END
+ END io_out[12]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3086.940 2924.800 3088.140 ;
+ END
+ END io_in[13]
+ PIN io_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3153.580 2924.800 3154.780 ;
+ END
+ END io_out[13]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3352.820 2924.800 3354.020 ;
+ END
+ END io_in[14]
+ PIN io_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3418.780 2924.800 3419.980 ;
+ END
+ END io_out[14]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2798.130 3517.600 2798.690 3524.800 ;
+ END
+ END io_in[15]
+ PIN io_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2717.170 3517.600 2717.730 3524.800 ;
+ END
+ END io_out[15]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2473.830 3517.600 2474.390 3524.800 ;
+ END
+ END io_in[16]
+ PIN io_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2392.410 3517.600 2392.970 3524.800 ;
+ END
+ END io_out[16]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2149.070 3517.600 2149.630 3524.800 ;
+ END
+ END io_in[17]
+ PIN io_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2068.110 3517.600 2068.670 3524.800 ;
+ END
+ END io_out[17]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1824.770 3517.600 1825.330 3524.800 ;
+ END
+ END io_in[18]
+ PIN io_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1743.810 3517.600 1744.370 3524.800 ;
+ END
+ END io_out[18]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1500.470 3517.600 1501.030 3524.800 ;
+ END
+ END io_in[19]
+ PIN io_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1419.050 3517.600 1419.610 3524.800 ;
+ END
+ END io_out[19]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 230.940 2924.800 232.140 ;
+ END
+ END io_in[1]
+ PIN io_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 297.580 2924.800 298.780 ;
+ END
+ END io_out[1]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1175.710 3517.600 1176.270 3524.800 ;
+ END
+ END io_in[20]
+ PIN io_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1094.750 3517.600 1095.310 3524.800 ;
+ END
+ END io_out[20]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 851.410 3517.600 851.970 3524.800 ;
+ END
+ END io_in[21]
+ PIN io_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 770.450 3517.600 771.010 3524.800 ;
+ END
+ END io_out[21]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 527.110 3517.600 527.670 3524.800 ;
+ END
+ END io_in[22]
+ PIN io_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.690 3517.600 446.250 3524.800 ;
+ END
+ END io_out[22]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.350 3517.600 202.910 3524.800 ;
+ END
+ END io_in[23]
+ PIN io_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 121.390 3517.600 121.950 3524.800 ;
+ END
+ END io_out[23]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3420.820 2.400 3422.020 ;
+ END
+ END io_in[24]
+ PIN io_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3355.540 2.400 3356.740 ;
+ END
+ END io_out[24]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3159.700 2.400 3160.900 ;
+ END
+ END io_in[25]
+ PIN io_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3095.100 2.400 3096.300 ;
+ END
+ END io_out[25]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2899.260 2.400 2900.460 ;
+ END
+ END io_in[26]
+ PIN io_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2833.980 2.400 2835.180 ;
+ END
+ END io_out[26]
+ PIN io_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2638.820 2.400 2640.020 ;
+ END
+ END io_in[27]
+ PIN io_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2573.540 2.400 2574.740 ;
+ END
+ END io_out[27]
+ PIN io_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2377.700 2.400 2378.900 ;
+ END
+ END io_in[28]
+ PIN io_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2312.420 2.400 2313.620 ;
+ END
+ END io_out[28]
+ PIN io_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2117.260 2.400 2118.460 ;
+ END
+ END io_in[29]
+ PIN io_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2051.980 2.400 2053.180 ;
+ END
+ END io_out[29]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 430.180 2924.800 431.380 ;
+ END
+ END io_in[2]
+ PIN io_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 496.820 2924.800 498.020 ;
+ END
+ END io_out[2]
+ PIN io_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1856.140 2.400 1857.340 ;
+ END
+ END io_in[30]
+ PIN io_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1791.540 2.400 1792.740 ;
+ END
+ END io_out[30]
+ PIN io_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1595.700 2.400 1596.900 ;
+ END
+ END io_in[31]
+ PIN io_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1530.420 2.400 1531.620 ;
+ END
+ END io_out[31]
+ PIN io_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1335.260 2.400 1336.460 ;
+ END
+ END io_in[32]
+ PIN io_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1269.980 2.400 1271.180 ;
+ END
+ END io_out[32]
+ PIN io_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1074.140 2.400 1075.340 ;
+ END
+ END io_in[33]
+ PIN io_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1008.860 2.400 1010.060 ;
+ END
+ END io_out[33]
+ PIN io_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 813.700 2.400 814.900 ;
+ END
+ END io_in[34]
+ PIN io_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 748.420 2.400 749.620 ;
+ END
+ END io_out[34]
+ PIN io_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 552.580 2.400 553.780 ;
+ END
+ END io_in[35]
+ PIN io_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 487.300 2.400 488.500 ;
+ END
+ END io_out[35]
+ PIN io_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 357.420 2.400 358.620 ;
+ END
+ END io_in[36]
+ PIN io_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 292.140 2.400 293.340 ;
+ END
+ END io_out[36]
+ PIN io_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 161.580 2.400 162.780 ;
+ END
+ END io_in[37]
+ PIN io_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 96.300 2.400 97.500 ;
+ END
+ END io_out[37]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 629.420 2924.800 630.620 ;
+ END
+ END io_in[3]
+ PIN io_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 696.060 2924.800 697.260 ;
+ END
+ END io_out[3]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 828.660 2924.800 829.860 ;
+ END
+ END io_in[4]
+ PIN io_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 895.300 2924.800 896.500 ;
+ END
+ END io_out[4]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1027.900 2924.800 1029.100 ;
+ END
+ END io_in[5]
+ PIN io_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1094.540 2924.800 1095.740 ;
+ END
+ END io_out[5]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1227.140 2924.800 1228.340 ;
+ END
+ END io_in[6]
+ PIN io_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1293.780 2924.800 1294.980 ;
+ END
+ END io_out[6]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1493.020 2924.800 1494.220 ;
+ END
+ END io_in[7]
+ PIN io_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1559.660 2924.800 1560.860 ;
+ END
+ END io_out[7]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1758.900 2924.800 1760.100 ;
+ END
+ END io_in[8]
+ PIN io_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1824.860 2924.800 1826.060 ;
+ END
+ END io_out[8]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2024.100 2924.800 2025.300 ;
+ END
+ END io_in[9]
+ PIN io_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2090.740 2924.800 2091.940 ;
+ END
+ END io_out[9]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 164.980 2924.800 166.180 ;
+ END
+ END io_oeb[0]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2422.580 2924.800 2423.780 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2688.460 2924.800 2689.660 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2954.340 2924.800 2955.540 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3219.540 2924.800 3220.740 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 3485.420 2924.800 3486.620 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2635.750 3517.600 2636.310 3524.800 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2311.450 3517.600 2312.010 3524.800 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1987.150 3517.600 1987.710 3524.800 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1662.390 3517.600 1662.950 3524.800 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1338.090 3517.600 1338.650 3524.800 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 364.220 2924.800 365.420 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1013.790 3517.600 1014.350 3524.800 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 689.030 3517.600 689.590 3524.800 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 364.730 3517.600 365.290 3524.800 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 40.430 3517.600 40.990 3524.800 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3290.260 2.400 3291.460 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 3029.820 2.400 3031.020 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2768.700 2.400 2769.900 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2508.260 2.400 2509.460 ;
+ END
+ END io_oeb[27]
+ PIN io_oeb[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 2247.140 2.400 2248.340 ;
+ END
+ END io_oeb[28]
+ PIN io_oeb[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1986.700 2.400 1987.900 ;
+ END
+ END io_oeb[29]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 563.460 2924.800 564.660 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1726.260 2.400 1727.460 ;
+ END
+ END io_oeb[30]
+ PIN io_oeb[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1465.140 2.400 1466.340 ;
+ END
+ END io_oeb[31]
+ PIN io_oeb[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 1204.700 2.400 1205.900 ;
+ END
+ END io_oeb[32]
+ PIN io_oeb[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 943.580 2.400 944.780 ;
+ END
+ END io_oeb[33]
+ PIN io_oeb[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 683.140 2.400 684.340 ;
+ END
+ END io_oeb[34]
+ PIN io_oeb[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 422.700 2.400 423.900 ;
+ END
+ END io_oeb[35]
+ PIN io_oeb[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 226.860 2.400 228.060 ;
+ END
+ END io_oeb[36]
+ PIN io_oeb[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT -4.800 31.700 2.400 32.900 ;
+ END
+ END io_oeb[37]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 762.700 2924.800 763.900 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 961.940 2924.800 963.140 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1161.180 2924.800 1162.380 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1360.420 2924.800 1361.620 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1625.620 2924.800 1626.820 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 1891.500 2924.800 1892.700 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2917.600 2157.380 2924.800 2158.580 ;
+ END
+ END io_oeb[9]
+ PIN la_data_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 629.230 -4.800 629.790 2.400 ;
+ END
+ END la_data_in[0]
+ PIN la_data_in[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2402.530 -4.800 2403.090 2.400 ;
+ END
+ END la_data_in[100]
+ PIN la_data_in[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2420.010 -4.800 2420.570 2.400 ;
+ END
+ END la_data_in[101]
+ PIN la_data_in[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2437.950 -4.800 2438.510 2.400 ;
+ END
+ END la_data_in[102]
+ PIN la_data_in[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2455.430 -4.800 2455.990 2.400 ;
+ END
+ END la_data_in[103]
+ PIN la_data_in[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2473.370 -4.800 2473.930 2.400 ;
+ END
+ END la_data_in[104]
+ PIN la_data_in[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2490.850 -4.800 2491.410 2.400 ;
+ END
+ END la_data_in[105]
+ PIN la_data_in[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2508.790 -4.800 2509.350 2.400 ;
+ END
+ END la_data_in[106]
+ PIN la_data_in[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2526.730 -4.800 2527.290 2.400 ;
+ END
+ END la_data_in[107]
+ PIN la_data_in[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2544.210 -4.800 2544.770 2.400 ;
+ END
+ END la_data_in[108]
+ PIN la_data_in[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2562.150 -4.800 2562.710 2.400 ;
+ END
+ END la_data_in[109]
+ PIN la_data_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 806.330 -4.800 806.890 2.400 ;
+ END
+ END la_data_in[10]
+ PIN la_data_in[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2579.630 -4.800 2580.190 2.400 ;
+ END
+ END la_data_in[110]
+ PIN la_data_in[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2597.570 -4.800 2598.130 2.400 ;
+ END
+ END la_data_in[111]
+ PIN la_data_in[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2615.050 -4.800 2615.610 2.400 ;
+ END
+ END la_data_in[112]
+ PIN la_data_in[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2632.990 -4.800 2633.550 2.400 ;
+ END
+ END la_data_in[113]
+ PIN la_data_in[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2650.470 -4.800 2651.030 2.400 ;
+ END
+ END la_data_in[114]
+ PIN la_data_in[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2668.410 -4.800 2668.970 2.400 ;
+ END
+ END la_data_in[115]
+ PIN la_data_in[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2685.890 -4.800 2686.450 2.400 ;
+ END
+ END la_data_in[116]
+ PIN la_data_in[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2703.830 -4.800 2704.390 2.400 ;
+ END
+ END la_data_in[117]
+ PIN la_data_in[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2721.770 -4.800 2722.330 2.400 ;
+ END
+ END la_data_in[118]
+ PIN la_data_in[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2739.250 -4.800 2739.810 2.400 ;
+ END
+ END la_data_in[119]
+ PIN la_data_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 824.270 -4.800 824.830 2.400 ;
+ END
+ END la_data_in[11]
+ PIN la_data_in[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2757.190 -4.800 2757.750 2.400 ;
+ END
+ END la_data_in[120]
+ PIN la_data_in[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2774.670 -4.800 2775.230 2.400 ;
+ END
+ END la_data_in[121]
+ PIN la_data_in[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2792.610 -4.800 2793.170 2.400 ;
+ END
+ END la_data_in[122]
+ PIN la_data_in[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2810.090 -4.800 2810.650 2.400 ;
+ END
+ END la_data_in[123]
+ PIN la_data_in[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2828.030 -4.800 2828.590 2.400 ;
+ END
+ END la_data_in[124]
+ PIN la_data_in[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2845.510 -4.800 2846.070 2.400 ;
+ END
+ END la_data_in[125]
+ PIN la_data_in[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2863.450 -4.800 2864.010 2.400 ;
+ END
+ END la_data_in[126]
+ PIN la_data_in[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2881.390 -4.800 2881.950 2.400 ;
+ END
+ END la_data_in[127]
+ PIN la_data_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 841.750 -4.800 842.310 2.400 ;
+ END
+ END la_data_in[12]
+ PIN la_data_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 859.690 -4.800 860.250 2.400 ;
+ END
+ END la_data_in[13]
+ PIN la_data_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 877.170 -4.800 877.730 2.400 ;
+ END
+ END la_data_in[14]
+ PIN la_data_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 895.110 -4.800 895.670 2.400 ;
+ END
+ END la_data_in[15]
+ PIN la_data_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 912.590 -4.800 913.150 2.400 ;
+ END
+ END la_data_in[16]
+ PIN la_data_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 930.530 -4.800 931.090 2.400 ;
+ END
+ END la_data_in[17]
+ PIN la_data_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 948.470 -4.800 949.030 2.400 ;
+ END
+ END la_data_in[18]
+ PIN la_data_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 965.950 -4.800 966.510 2.400 ;
+ END
+ END la_data_in[19]
+ PIN la_data_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 646.710 -4.800 647.270 2.400 ;
+ END
+ END la_data_in[1]
+ PIN la_data_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 983.890 -4.800 984.450 2.400 ;
+ END
+ END la_data_in[20]
+ PIN la_data_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1001.370 -4.800 1001.930 2.400 ;
+ END
+ END la_data_in[21]
+ PIN la_data_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1019.310 -4.800 1019.870 2.400 ;
+ END
+ END la_data_in[22]
+ PIN la_data_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1036.790 -4.800 1037.350 2.400 ;
+ END
+ END la_data_in[23]
+ PIN la_data_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1054.730 -4.800 1055.290 2.400 ;
+ END
+ END la_data_in[24]
+ PIN la_data_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1072.210 -4.800 1072.770 2.400 ;
+ END
+ END la_data_in[25]
+ PIN la_data_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1090.150 -4.800 1090.710 2.400 ;
+ END
+ END la_data_in[26]
+ PIN la_data_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1107.630 -4.800 1108.190 2.400 ;
+ END
+ END la_data_in[27]
+ PIN la_data_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1125.570 -4.800 1126.130 2.400 ;
+ END
+ END la_data_in[28]
+ PIN la_data_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1143.510 -4.800 1144.070 2.400 ;
+ END
+ END la_data_in[29]
+ PIN la_data_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 664.650 -4.800 665.210 2.400 ;
+ END
+ END la_data_in[2]
+ PIN la_data_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1160.990 -4.800 1161.550 2.400 ;
+ END
+ END la_data_in[30]
+ PIN la_data_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1178.930 -4.800 1179.490 2.400 ;
+ END
+ END la_data_in[31]
+ PIN la_data_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1196.410 -4.800 1196.970 2.400 ;
+ END
+ END la_data_in[32]
+ PIN la_data_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1214.350 -4.800 1214.910 2.400 ;
+ END
+ END la_data_in[33]
+ PIN la_data_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1231.830 -4.800 1232.390 2.400 ;
+ END
+ END la_data_in[34]
+ PIN la_data_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1249.770 -4.800 1250.330 2.400 ;
+ END
+ END la_data_in[35]
+ PIN la_data_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1267.250 -4.800 1267.810 2.400 ;
+ END
+ END la_data_in[36]
+ PIN la_data_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1285.190 -4.800 1285.750 2.400 ;
+ END
+ END la_data_in[37]
+ PIN la_data_in[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1303.130 -4.800 1303.690 2.400 ;
+ END
+ END la_data_in[38]
+ PIN la_data_in[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1320.610 -4.800 1321.170 2.400 ;
+ END
+ END la_data_in[39]
+ PIN la_data_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 682.130 -4.800 682.690 2.400 ;
+ END
+ END la_data_in[3]
+ PIN la_data_in[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1338.550 -4.800 1339.110 2.400 ;
+ END
+ END la_data_in[40]
+ PIN la_data_in[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1356.030 -4.800 1356.590 2.400 ;
+ END
+ END la_data_in[41]
+ PIN la_data_in[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1373.970 -4.800 1374.530 2.400 ;
+ END
+ END la_data_in[42]
+ PIN la_data_in[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1391.450 -4.800 1392.010 2.400 ;
+ END
+ END la_data_in[43]
+ PIN la_data_in[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1409.390 -4.800 1409.950 2.400 ;
+ END
+ END la_data_in[44]
+ PIN la_data_in[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1426.870 -4.800 1427.430 2.400 ;
+ END
+ END la_data_in[45]
+ PIN la_data_in[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1444.810 -4.800 1445.370 2.400 ;
+ END
+ END la_data_in[46]
+ PIN la_data_in[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1462.750 -4.800 1463.310 2.400 ;
+ END
+ END la_data_in[47]
+ PIN la_data_in[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1480.230 -4.800 1480.790 2.400 ;
+ END
+ END la_data_in[48]
+ PIN la_data_in[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1498.170 -4.800 1498.730 2.400 ;
+ END
+ END la_data_in[49]
+ PIN la_data_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 700.070 -4.800 700.630 2.400 ;
+ END
+ END la_data_in[4]
+ PIN la_data_in[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1515.650 -4.800 1516.210 2.400 ;
+ END
+ END la_data_in[50]
+ PIN la_data_in[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1533.590 -4.800 1534.150 2.400 ;
+ END
+ END la_data_in[51]
+ PIN la_data_in[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1551.070 -4.800 1551.630 2.400 ;
+ END
+ END la_data_in[52]
+ PIN la_data_in[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1569.010 -4.800 1569.570 2.400 ;
+ END
+ END la_data_in[53]
+ PIN la_data_in[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1586.490 -4.800 1587.050 2.400 ;
+ END
+ END la_data_in[54]
+ PIN la_data_in[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1604.430 -4.800 1604.990 2.400 ;
+ END
+ END la_data_in[55]
+ PIN la_data_in[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1621.910 -4.800 1622.470 2.400 ;
+ END
+ END la_data_in[56]
+ PIN la_data_in[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1639.850 -4.800 1640.410 2.400 ;
+ END
+ END la_data_in[57]
+ PIN la_data_in[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1657.790 -4.800 1658.350 2.400 ;
+ END
+ END la_data_in[58]
+ PIN la_data_in[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1675.270 -4.800 1675.830 2.400 ;
+ END
+ END la_data_in[59]
+ PIN la_data_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 717.550 -4.800 718.110 2.400 ;
+ END
+ END la_data_in[5]
+ PIN la_data_in[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1693.210 -4.800 1693.770 2.400 ;
+ END
+ END la_data_in[60]
+ PIN la_data_in[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1710.690 -4.800 1711.250 2.400 ;
+ END
+ END la_data_in[61]
+ PIN la_data_in[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1728.630 -4.800 1729.190 2.400 ;
+ END
+ END la_data_in[62]
+ PIN la_data_in[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1746.110 -4.800 1746.670 2.400 ;
+ END
+ END la_data_in[63]
+ PIN la_data_in[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1764.050 -4.800 1764.610 2.400 ;
+ END
+ END la_data_in[64]
+ PIN la_data_in[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1781.530 -4.800 1782.090 2.400 ;
+ END
+ END la_data_in[65]
+ PIN la_data_in[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1799.470 -4.800 1800.030 2.400 ;
+ END
+ END la_data_in[66]
+ PIN la_data_in[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1817.410 -4.800 1817.970 2.400 ;
+ END
+ END la_data_in[67]
+ PIN la_data_in[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1834.890 -4.800 1835.450 2.400 ;
+ END
+ END la_data_in[68]
+ PIN la_data_in[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1852.830 -4.800 1853.390 2.400 ;
+ END
+ END la_data_in[69]
+ PIN la_data_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 735.490 -4.800 736.050 2.400 ;
+ END
+ END la_data_in[6]
+ PIN la_data_in[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1870.310 -4.800 1870.870 2.400 ;
+ END
+ END la_data_in[70]
+ PIN la_data_in[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1888.250 -4.800 1888.810 2.400 ;
+ END
+ END la_data_in[71]
+ PIN la_data_in[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1905.730 -4.800 1906.290 2.400 ;
+ END
+ END la_data_in[72]
+ PIN la_data_in[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1923.670 -4.800 1924.230 2.400 ;
+ END
+ END la_data_in[73]
+ PIN la_data_in[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1941.150 -4.800 1941.710 2.400 ;
+ END
+ END la_data_in[74]
+ PIN la_data_in[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1959.090 -4.800 1959.650 2.400 ;
+ END
+ END la_data_in[75]
+ PIN la_data_in[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1976.570 -4.800 1977.130 2.400 ;
+ END
+ END la_data_in[76]
+ PIN la_data_in[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1994.510 -4.800 1995.070 2.400 ;
+ END
+ END la_data_in[77]
+ PIN la_data_in[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2012.450 -4.800 2013.010 2.400 ;
+ END
+ END la_data_in[78]
+ PIN la_data_in[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2029.930 -4.800 2030.490 2.400 ;
+ END
+ END la_data_in[79]
+ PIN la_data_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 752.970 -4.800 753.530 2.400 ;
+ END
+ END la_data_in[7]
+ PIN la_data_in[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2047.870 -4.800 2048.430 2.400 ;
+ END
+ END la_data_in[80]
+ PIN la_data_in[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2065.350 -4.800 2065.910 2.400 ;
+ END
+ END la_data_in[81]
+ PIN la_data_in[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2083.290 -4.800 2083.850 2.400 ;
+ END
+ END la_data_in[82]
+ PIN la_data_in[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2100.770 -4.800 2101.330 2.400 ;
+ END
+ END la_data_in[83]
+ PIN la_data_in[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2118.710 -4.800 2119.270 2.400 ;
+ END
+ END la_data_in[84]
+ PIN la_data_in[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2136.190 -4.800 2136.750 2.400 ;
+ END
+ END la_data_in[85]
+ PIN la_data_in[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2154.130 -4.800 2154.690 2.400 ;
+ END
+ END la_data_in[86]
+ PIN la_data_in[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2172.070 -4.800 2172.630 2.400 ;
+ END
+ END la_data_in[87]
+ PIN la_data_in[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2189.550 -4.800 2190.110 2.400 ;
+ END
+ END la_data_in[88]
+ PIN la_data_in[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2207.490 -4.800 2208.050 2.400 ;
+ END
+ END la_data_in[89]
+ PIN la_data_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 770.910 -4.800 771.470 2.400 ;
+ END
+ END la_data_in[8]
+ PIN la_data_in[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2224.970 -4.800 2225.530 2.400 ;
+ END
+ END la_data_in[90]
+ PIN la_data_in[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2242.910 -4.800 2243.470 2.400 ;
+ END
+ END la_data_in[91]
+ PIN la_data_in[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2260.390 -4.800 2260.950 2.400 ;
+ END
+ END la_data_in[92]
+ PIN la_data_in[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2278.330 -4.800 2278.890 2.400 ;
+ END
+ END la_data_in[93]
+ PIN la_data_in[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2295.810 -4.800 2296.370 2.400 ;
+ END
+ END la_data_in[94]
+ PIN la_data_in[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2313.750 -4.800 2314.310 2.400 ;
+ END
+ END la_data_in[95]
+ PIN la_data_in[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2331.230 -4.800 2331.790 2.400 ;
+ END
+ END la_data_in[96]
+ PIN la_data_in[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2349.170 -4.800 2349.730 2.400 ;
+ END
+ END la_data_in[97]
+ PIN la_data_in[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2367.110 -4.800 2367.670 2.400 ;
+ END
+ END la_data_in[98]
+ PIN la_data_in[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2384.590 -4.800 2385.150 2.400 ;
+ END
+ END la_data_in[99]
+ PIN la_data_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 788.850 -4.800 789.410 2.400 ;
+ END
+ END la_data_in[9]
+ PIN la_data_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 634.750 -4.800 635.310 2.400 ;
+ END
+ END la_data_out[0]
+ PIN la_data_out[100]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2408.510 -4.800 2409.070 2.400 ;
+ END
+ END la_data_out[100]
+ PIN la_data_out[101]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2425.990 -4.800 2426.550 2.400 ;
+ END
+ END la_data_out[101]
+ PIN la_data_out[102]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2443.930 -4.800 2444.490 2.400 ;
+ END
+ END la_data_out[102]
+ PIN la_data_out[103]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2461.410 -4.800 2461.970 2.400 ;
+ END
+ END la_data_out[103]
+ PIN la_data_out[104]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2479.350 -4.800 2479.910 2.400 ;
+ END
+ END la_data_out[104]
+ PIN la_data_out[105]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2496.830 -4.800 2497.390 2.400 ;
+ END
+ END la_data_out[105]
+ PIN la_data_out[106]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2514.770 -4.800 2515.330 2.400 ;
+ END
+ END la_data_out[106]
+ PIN la_data_out[107]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2532.250 -4.800 2532.810 2.400 ;
+ END
+ END la_data_out[107]
+ PIN la_data_out[108]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2550.190 -4.800 2550.750 2.400 ;
+ END
+ END la_data_out[108]
+ PIN la_data_out[109]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2567.670 -4.800 2568.230 2.400 ;
+ END
+ END la_data_out[109]
+ PIN la_data_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 812.310 -4.800 812.870 2.400 ;
+ END
+ END la_data_out[10]
+ PIN la_data_out[110]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2585.610 -4.800 2586.170 2.400 ;
+ END
+ END la_data_out[110]
+ PIN la_data_out[111]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2603.550 -4.800 2604.110 2.400 ;
+ END
+ END la_data_out[111]
+ PIN la_data_out[112]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2621.030 -4.800 2621.590 2.400 ;
+ END
+ END la_data_out[112]
+ PIN la_data_out[113]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2638.970 -4.800 2639.530 2.400 ;
+ END
+ END la_data_out[113]
+ PIN la_data_out[114]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2656.450 -4.800 2657.010 2.400 ;
+ END
+ END la_data_out[114]
+ PIN la_data_out[115]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2674.390 -4.800 2674.950 2.400 ;
+ END
+ END la_data_out[115]
+ PIN la_data_out[116]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2691.870 -4.800 2692.430 2.400 ;
+ END
+ END la_data_out[116]
+ PIN la_data_out[117]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2709.810 -4.800 2710.370 2.400 ;
+ END
+ END la_data_out[117]
+ PIN la_data_out[118]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2727.290 -4.800 2727.850 2.400 ;
+ END
+ END la_data_out[118]
+ PIN la_data_out[119]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2745.230 -4.800 2745.790 2.400 ;
+ END
+ END la_data_out[119]
+ PIN la_data_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 830.250 -4.800 830.810 2.400 ;
+ END
+ END la_data_out[11]
+ PIN la_data_out[120]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2763.170 -4.800 2763.730 2.400 ;
+ END
+ END la_data_out[120]
+ PIN la_data_out[121]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2780.650 -4.800 2781.210 2.400 ;
+ END
+ END la_data_out[121]
+ PIN la_data_out[122]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2798.590 -4.800 2799.150 2.400 ;
+ END
+ END la_data_out[122]
+ PIN la_data_out[123]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2816.070 -4.800 2816.630 2.400 ;
+ END
+ END la_data_out[123]
+ PIN la_data_out[124]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2834.010 -4.800 2834.570 2.400 ;
+ END
+ END la_data_out[124]
+ PIN la_data_out[125]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2851.490 -4.800 2852.050 2.400 ;
+ END
+ END la_data_out[125]
+ PIN la_data_out[126]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2869.430 -4.800 2869.990 2.400 ;
+ END
+ END la_data_out[126]
+ PIN la_data_out[127]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2886.910 -4.800 2887.470 2.400 ;
+ END
+ END la_data_out[127]
+ PIN la_data_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 847.730 -4.800 848.290 2.400 ;
+ END
+ END la_data_out[12]
+ PIN la_data_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 865.670 -4.800 866.230 2.400 ;
+ END
+ END la_data_out[13]
+ PIN la_data_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 883.150 -4.800 883.710 2.400 ;
+ END
+ END la_data_out[14]
+ PIN la_data_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 901.090 -4.800 901.650 2.400 ;
+ END
+ END la_data_out[15]
+ PIN la_data_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 918.570 -4.800 919.130 2.400 ;
+ END
+ END la_data_out[16]
+ PIN la_data_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 936.510 -4.800 937.070 2.400 ;
+ END
+ END la_data_out[17]
+ PIN la_data_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 953.990 -4.800 954.550 2.400 ;
+ END
+ END la_data_out[18]
+ PIN la_data_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 971.930 -4.800 972.490 2.400 ;
+ END
+ END la_data_out[19]
+ PIN la_data_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 652.690 -4.800 653.250 2.400 ;
+ END
+ END la_data_out[1]
+ PIN la_data_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 989.410 -4.800 989.970 2.400 ;
+ END
+ END la_data_out[20]
+ PIN la_data_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1007.350 -4.800 1007.910 2.400 ;
+ END
+ END la_data_out[21]
+ PIN la_data_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1025.290 -4.800 1025.850 2.400 ;
+ END
+ END la_data_out[22]
+ PIN la_data_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1042.770 -4.800 1043.330 2.400 ;
+ END
+ END la_data_out[23]
+ PIN la_data_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1060.710 -4.800 1061.270 2.400 ;
+ END
+ END la_data_out[24]
+ PIN la_data_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1078.190 -4.800 1078.750 2.400 ;
+ END
+ END la_data_out[25]
+ PIN la_data_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1096.130 -4.800 1096.690 2.400 ;
+ END
+ END la_data_out[26]
+ PIN la_data_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1113.610 -4.800 1114.170 2.400 ;
+ END
+ END la_data_out[27]
+ PIN la_data_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1131.550 -4.800 1132.110 2.400 ;
+ END
+ END la_data_out[28]
+ PIN la_data_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1149.030 -4.800 1149.590 2.400 ;
+ END
+ END la_data_out[29]
+ PIN la_data_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 670.630 -4.800 671.190 2.400 ;
+ END
+ END la_data_out[2]
+ PIN la_data_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1166.970 -4.800 1167.530 2.400 ;
+ END
+ END la_data_out[30]
+ PIN la_data_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1184.910 -4.800 1185.470 2.400 ;
+ END
+ END la_data_out[31]
+ PIN la_data_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1202.390 -4.800 1202.950 2.400 ;
+ END
+ END la_data_out[32]
+ PIN la_data_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1220.330 -4.800 1220.890 2.400 ;
+ END
+ END la_data_out[33]
+ PIN la_data_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1237.810 -4.800 1238.370 2.400 ;
+ END
+ END la_data_out[34]
+ PIN la_data_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1255.750 -4.800 1256.310 2.400 ;
+ END
+ END la_data_out[35]
+ PIN la_data_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1273.230 -4.800 1273.790 2.400 ;
+ END
+ END la_data_out[36]
+ PIN la_data_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1291.170 -4.800 1291.730 2.400 ;
+ END
+ END la_data_out[37]
+ PIN la_data_out[38]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1308.650 -4.800 1309.210 2.400 ;
+ END
+ END la_data_out[38]
+ PIN la_data_out[39]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1326.590 -4.800 1327.150 2.400 ;
+ END
+ END la_data_out[39]
+ PIN la_data_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 688.110 -4.800 688.670 2.400 ;
+ END
+ END la_data_out[3]
+ PIN la_data_out[40]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1344.070 -4.800 1344.630 2.400 ;
+ END
+ END la_data_out[40]
+ PIN la_data_out[41]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1362.010 -4.800 1362.570 2.400 ;
+ END
+ END la_data_out[41]
+ PIN la_data_out[42]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1379.950 -4.800 1380.510 2.400 ;
+ END
+ END la_data_out[42]
+ PIN la_data_out[43]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1397.430 -4.800 1397.990 2.400 ;
+ END
+ END la_data_out[43]
+ PIN la_data_out[44]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1415.370 -4.800 1415.930 2.400 ;
+ END
+ END la_data_out[44]
+ PIN la_data_out[45]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1432.850 -4.800 1433.410 2.400 ;
+ END
+ END la_data_out[45]
+ PIN la_data_out[46]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1450.790 -4.800 1451.350 2.400 ;
+ END
+ END la_data_out[46]
+ PIN la_data_out[47]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1468.270 -4.800 1468.830 2.400 ;
+ END
+ END la_data_out[47]
+ PIN la_data_out[48]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1486.210 -4.800 1486.770 2.400 ;
+ END
+ END la_data_out[48]
+ PIN la_data_out[49]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1503.690 -4.800 1504.250 2.400 ;
+ END
+ END la_data_out[49]
+ PIN la_data_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 706.050 -4.800 706.610 2.400 ;
+ END
+ END la_data_out[4]
+ PIN la_data_out[50]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1521.630 -4.800 1522.190 2.400 ;
+ END
+ END la_data_out[50]
+ PIN la_data_out[51]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1539.570 -4.800 1540.130 2.400 ;
+ END
+ END la_data_out[51]
+ PIN la_data_out[52]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1557.050 -4.800 1557.610 2.400 ;
+ END
+ END la_data_out[52]
+ PIN la_data_out[53]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1574.990 -4.800 1575.550 2.400 ;
+ END
+ END la_data_out[53]
+ PIN la_data_out[54]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1592.470 -4.800 1593.030 2.400 ;
+ END
+ END la_data_out[54]
+ PIN la_data_out[55]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1610.410 -4.800 1610.970 2.400 ;
+ END
+ END la_data_out[55]
+ PIN la_data_out[56]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1627.890 -4.800 1628.450 2.400 ;
+ END
+ END la_data_out[56]
+ PIN la_data_out[57]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1645.830 -4.800 1646.390 2.400 ;
+ END
+ END la_data_out[57]
+ PIN la_data_out[58]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1663.310 -4.800 1663.870 2.400 ;
+ END
+ END la_data_out[58]
+ PIN la_data_out[59]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1681.250 -4.800 1681.810 2.400 ;
+ END
+ END la_data_out[59]
+ PIN la_data_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 723.530 -4.800 724.090 2.400 ;
+ END
+ END la_data_out[5]
+ PIN la_data_out[60]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1699.190 -4.800 1699.750 2.400 ;
+ END
+ END la_data_out[60]
+ PIN la_data_out[61]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1716.670 -4.800 1717.230 2.400 ;
+ END
+ END la_data_out[61]
+ PIN la_data_out[62]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1734.610 -4.800 1735.170 2.400 ;
+ END
+ END la_data_out[62]
+ PIN la_data_out[63]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1752.090 -4.800 1752.650 2.400 ;
+ END
+ END la_data_out[63]
+ PIN la_data_out[64]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1770.030 -4.800 1770.590 2.400 ;
+ END
+ END la_data_out[64]
+ PIN la_data_out[65]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1787.510 -4.800 1788.070 2.400 ;
+ END
+ END la_data_out[65]
+ PIN la_data_out[66]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1805.450 -4.800 1806.010 2.400 ;
+ END
+ END la_data_out[66]
+ PIN la_data_out[67]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1822.930 -4.800 1823.490 2.400 ;
+ END
+ END la_data_out[67]
+ PIN la_data_out[68]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1840.870 -4.800 1841.430 2.400 ;
+ END
+ END la_data_out[68]
+ PIN la_data_out[69]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1858.350 -4.800 1858.910 2.400 ;
+ END
+ END la_data_out[69]
+ PIN la_data_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 741.470 -4.800 742.030 2.400 ;
+ END
+ END la_data_out[6]
+ PIN la_data_out[70]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1876.290 -4.800 1876.850 2.400 ;
+ END
+ END la_data_out[70]
+ PIN la_data_out[71]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1894.230 -4.800 1894.790 2.400 ;
+ END
+ END la_data_out[71]
+ PIN la_data_out[72]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1911.710 -4.800 1912.270 2.400 ;
+ END
+ END la_data_out[72]
+ PIN la_data_out[73]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1929.650 -4.800 1930.210 2.400 ;
+ END
+ END la_data_out[73]
+ PIN la_data_out[74]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1947.130 -4.800 1947.690 2.400 ;
+ END
+ END la_data_out[74]
+ PIN la_data_out[75]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1965.070 -4.800 1965.630 2.400 ;
+ END
+ END la_data_out[75]
+ PIN la_data_out[76]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1982.550 -4.800 1983.110 2.400 ;
+ END
+ END la_data_out[76]
+ PIN la_data_out[77]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2000.490 -4.800 2001.050 2.400 ;
+ END
+ END la_data_out[77]
+ PIN la_data_out[78]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2017.970 -4.800 2018.530 2.400 ;
+ END
+ END la_data_out[78]
+ PIN la_data_out[79]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2035.910 -4.800 2036.470 2.400 ;
+ END
+ END la_data_out[79]
+ PIN la_data_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 758.950 -4.800 759.510 2.400 ;
+ END
+ END la_data_out[7]
+ PIN la_data_out[80]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2053.850 -4.800 2054.410 2.400 ;
+ END
+ END la_data_out[80]
+ PIN la_data_out[81]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2071.330 -4.800 2071.890 2.400 ;
+ END
+ END la_data_out[81]
+ PIN la_data_out[82]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2089.270 -4.800 2089.830 2.400 ;
+ END
+ END la_data_out[82]
+ PIN la_data_out[83]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2106.750 -4.800 2107.310 2.400 ;
+ END
+ END la_data_out[83]
+ PIN la_data_out[84]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2124.690 -4.800 2125.250 2.400 ;
+ END
+ END la_data_out[84]
+ PIN la_data_out[85]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2142.170 -4.800 2142.730 2.400 ;
+ END
+ END la_data_out[85]
+ PIN la_data_out[86]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2160.110 -4.800 2160.670 2.400 ;
+ END
+ END la_data_out[86]
+ PIN la_data_out[87]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2177.590 -4.800 2178.150 2.400 ;
+ END
+ END la_data_out[87]
+ PIN la_data_out[88]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2195.530 -4.800 2196.090 2.400 ;
+ END
+ END la_data_out[88]
+ PIN la_data_out[89]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2213.010 -4.800 2213.570 2.400 ;
+ END
+ END la_data_out[89]
+ PIN la_data_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 776.890 -4.800 777.450 2.400 ;
+ END
+ END la_data_out[8]
+ PIN la_data_out[90]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2230.950 -4.800 2231.510 2.400 ;
+ END
+ END la_data_out[90]
+ PIN la_data_out[91]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2248.890 -4.800 2249.450 2.400 ;
+ END
+ END la_data_out[91]
+ PIN la_data_out[92]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2266.370 -4.800 2266.930 2.400 ;
+ END
+ END la_data_out[92]
+ PIN la_data_out[93]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2284.310 -4.800 2284.870 2.400 ;
+ END
+ END la_data_out[93]
+ PIN la_data_out[94]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2301.790 -4.800 2302.350 2.400 ;
+ END
+ END la_data_out[94]
+ PIN la_data_out[95]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2319.730 -4.800 2320.290 2.400 ;
+ END
+ END la_data_out[95]
+ PIN la_data_out[96]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2337.210 -4.800 2337.770 2.400 ;
+ END
+ END la_data_out[96]
+ PIN la_data_out[97]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2355.150 -4.800 2355.710 2.400 ;
+ END
+ END la_data_out[97]
+ PIN la_data_out[98]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2372.630 -4.800 2373.190 2.400 ;
+ END
+ END la_data_out[98]
+ PIN la_data_out[99]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2390.570 -4.800 2391.130 2.400 ;
+ END
+ END la_data_out[99]
+ PIN la_data_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 794.370 -4.800 794.930 2.400 ;
+ END
+ END la_data_out[9]
+ PIN la_oenb[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 640.730 -4.800 641.290 2.400 ;
+ END
+ END la_oenb[0]
+ PIN la_oenb[100]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2414.030 -4.800 2414.590 2.400 ;
+ END
+ END la_oenb[100]
+ PIN la_oenb[101]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2431.970 -4.800 2432.530 2.400 ;
+ END
+ END la_oenb[101]
+ PIN la_oenb[102]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2449.450 -4.800 2450.010 2.400 ;
+ END
+ END la_oenb[102]
+ PIN la_oenb[103]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2467.390 -4.800 2467.950 2.400 ;
+ END
+ END la_oenb[103]
+ PIN la_oenb[104]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2485.330 -4.800 2485.890 2.400 ;
+ END
+ END la_oenb[104]
+ PIN la_oenb[105]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2502.810 -4.800 2503.370 2.400 ;
+ END
+ END la_oenb[105]
+ PIN la_oenb[106]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2520.750 -4.800 2521.310 2.400 ;
+ END
+ END la_oenb[106]
+ PIN la_oenb[107]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2538.230 -4.800 2538.790 2.400 ;
+ END
+ END la_oenb[107]
+ PIN la_oenb[108]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2556.170 -4.800 2556.730 2.400 ;
+ END
+ END la_oenb[108]
+ PIN la_oenb[109]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2573.650 -4.800 2574.210 2.400 ;
+ END
+ END la_oenb[109]
+ PIN la_oenb[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 818.290 -4.800 818.850 2.400 ;
+ END
+ END la_oenb[10]
+ PIN la_oenb[110]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2591.590 -4.800 2592.150 2.400 ;
+ END
+ END la_oenb[110]
+ PIN la_oenb[111]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2609.070 -4.800 2609.630 2.400 ;
+ END
+ END la_oenb[111]
+ PIN la_oenb[112]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2627.010 -4.800 2627.570 2.400 ;
+ END
+ END la_oenb[112]
+ PIN la_oenb[113]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2644.950 -4.800 2645.510 2.400 ;
+ END
+ END la_oenb[113]
+ PIN la_oenb[114]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2662.430 -4.800 2662.990 2.400 ;
+ END
+ END la_oenb[114]
+ PIN la_oenb[115]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2680.370 -4.800 2680.930 2.400 ;
+ END
+ END la_oenb[115]
+ PIN la_oenb[116]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2697.850 -4.800 2698.410 2.400 ;
+ END
+ END la_oenb[116]
+ PIN la_oenb[117]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2715.790 -4.800 2716.350 2.400 ;
+ END
+ END la_oenb[117]
+ PIN la_oenb[118]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2733.270 -4.800 2733.830 2.400 ;
+ END
+ END la_oenb[118]
+ PIN la_oenb[119]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2751.210 -4.800 2751.770 2.400 ;
+ END
+ END la_oenb[119]
+ PIN la_oenb[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 835.770 -4.800 836.330 2.400 ;
+ END
+ END la_oenb[11]
+ PIN la_oenb[120]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2768.690 -4.800 2769.250 2.400 ;
+ END
+ END la_oenb[120]
+ PIN la_oenb[121]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2786.630 -4.800 2787.190 2.400 ;
+ END
+ END la_oenb[121]
+ PIN la_oenb[122]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2804.110 -4.800 2804.670 2.400 ;
+ END
+ END la_oenb[122]
+ PIN la_oenb[123]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2822.050 -4.800 2822.610 2.400 ;
+ END
+ END la_oenb[123]
+ PIN la_oenb[124]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2839.990 -4.800 2840.550 2.400 ;
+ END
+ END la_oenb[124]
+ PIN la_oenb[125]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2857.470 -4.800 2858.030 2.400 ;
+ END
+ END la_oenb[125]
+ PIN la_oenb[126]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2875.410 -4.800 2875.970 2.400 ;
+ END
+ END la_oenb[126]
+ PIN la_oenb[127]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2892.890 -4.800 2893.450 2.400 ;
+ END
+ END la_oenb[127]
+ PIN la_oenb[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 853.710 -4.800 854.270 2.400 ;
+ END
+ END la_oenb[12]
+ PIN la_oenb[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 871.190 -4.800 871.750 2.400 ;
+ END
+ END la_oenb[13]
+ PIN la_oenb[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 889.130 -4.800 889.690 2.400 ;
+ END
+ END la_oenb[14]
+ PIN la_oenb[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 907.070 -4.800 907.630 2.400 ;
+ END
+ END la_oenb[15]
+ PIN la_oenb[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 924.550 -4.800 925.110 2.400 ;
+ END
+ END la_oenb[16]
+ PIN la_oenb[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 942.490 -4.800 943.050 2.400 ;
+ END
+ END la_oenb[17]
+ PIN la_oenb[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 959.970 -4.800 960.530 2.400 ;
+ END
+ END la_oenb[18]
+ PIN la_oenb[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 977.910 -4.800 978.470 2.400 ;
+ END
+ END la_oenb[19]
+ PIN la_oenb[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 658.670 -4.800 659.230 2.400 ;
+ END
+ END la_oenb[1]
+ PIN la_oenb[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 995.390 -4.800 995.950 2.400 ;
+ END
+ END la_oenb[20]
+ PIN la_oenb[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1013.330 -4.800 1013.890 2.400 ;
+ END
+ END la_oenb[21]
+ PIN la_oenb[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1030.810 -4.800 1031.370 2.400 ;
+ END
+ END la_oenb[22]
+ PIN la_oenb[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1048.750 -4.800 1049.310 2.400 ;
+ END
+ END la_oenb[23]
+ PIN la_oenb[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1066.690 -4.800 1067.250 2.400 ;
+ END
+ END la_oenb[24]
+ PIN la_oenb[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1084.170 -4.800 1084.730 2.400 ;
+ END
+ END la_oenb[25]
+ PIN la_oenb[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1102.110 -4.800 1102.670 2.400 ;
+ END
+ END la_oenb[26]
+ PIN la_oenb[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1119.590 -4.800 1120.150 2.400 ;
+ END
+ END la_oenb[27]
+ PIN la_oenb[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1137.530 -4.800 1138.090 2.400 ;
+ END
+ END la_oenb[28]
+ PIN la_oenb[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1155.010 -4.800 1155.570 2.400 ;
+ END
+ END la_oenb[29]
+ PIN la_oenb[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 676.150 -4.800 676.710 2.400 ;
+ END
+ END la_oenb[2]
+ PIN la_oenb[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1172.950 -4.800 1173.510 2.400 ;
+ END
+ END la_oenb[30]
+ PIN la_oenb[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1190.430 -4.800 1190.990 2.400 ;
+ END
+ END la_oenb[31]
+ PIN la_oenb[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1208.370 -4.800 1208.930 2.400 ;
+ END
+ END la_oenb[32]
+ PIN la_oenb[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1225.850 -4.800 1226.410 2.400 ;
+ END
+ END la_oenb[33]
+ PIN la_oenb[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1243.790 -4.800 1244.350 2.400 ;
+ END
+ END la_oenb[34]
+ PIN la_oenb[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1261.730 -4.800 1262.290 2.400 ;
+ END
+ END la_oenb[35]
+ PIN la_oenb[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1279.210 -4.800 1279.770 2.400 ;
+ END
+ END la_oenb[36]
+ PIN la_oenb[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1297.150 -4.800 1297.710 2.400 ;
+ END
+ END la_oenb[37]
+ PIN la_oenb[38]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1314.630 -4.800 1315.190 2.400 ;
+ END
+ END la_oenb[38]
+ PIN la_oenb[39]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1332.570 -4.800 1333.130 2.400 ;
+ END
+ END la_oenb[39]
+ PIN la_oenb[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 694.090 -4.800 694.650 2.400 ;
+ END
+ END la_oenb[3]
+ PIN la_oenb[40]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1350.050 -4.800 1350.610 2.400 ;
+ END
+ END la_oenb[40]
+ PIN la_oenb[41]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1367.990 -4.800 1368.550 2.400 ;
+ END
+ END la_oenb[41]
+ PIN la_oenb[42]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1385.470 -4.800 1386.030 2.400 ;
+ END
+ END la_oenb[42]
+ PIN la_oenb[43]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1403.410 -4.800 1403.970 2.400 ;
+ END
+ END la_oenb[43]
+ PIN la_oenb[44]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1421.350 -4.800 1421.910 2.400 ;
+ END
+ END la_oenb[44]
+ PIN la_oenb[45]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1438.830 -4.800 1439.390 2.400 ;
+ END
+ END la_oenb[45]
+ PIN la_oenb[46]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1456.770 -4.800 1457.330 2.400 ;
+ END
+ END la_oenb[46]
+ PIN la_oenb[47]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1474.250 -4.800 1474.810 2.400 ;
+ END
+ END la_oenb[47]
+ PIN la_oenb[48]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1492.190 -4.800 1492.750 2.400 ;
+ END
+ END la_oenb[48]
+ PIN la_oenb[49]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1509.670 -4.800 1510.230 2.400 ;
+ END
+ END la_oenb[49]
+ PIN la_oenb[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 712.030 -4.800 712.590 2.400 ;
+ END
+ END la_oenb[4]
+ PIN la_oenb[50]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1527.610 -4.800 1528.170 2.400 ;
+ END
+ END la_oenb[50]
+ PIN la_oenb[51]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1545.090 -4.800 1545.650 2.400 ;
+ END
+ END la_oenb[51]
+ PIN la_oenb[52]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1563.030 -4.800 1563.590 2.400 ;
+ END
+ END la_oenb[52]
+ PIN la_oenb[53]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1580.970 -4.800 1581.530 2.400 ;
+ END
+ END la_oenb[53]
+ PIN la_oenb[54]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1598.450 -4.800 1599.010 2.400 ;
+ END
+ END la_oenb[54]
+ PIN la_oenb[55]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1616.390 -4.800 1616.950 2.400 ;
+ END
+ END la_oenb[55]
+ PIN la_oenb[56]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1633.870 -4.800 1634.430 2.400 ;
+ END
+ END la_oenb[56]
+ PIN la_oenb[57]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1651.810 -4.800 1652.370 2.400 ;
+ END
+ END la_oenb[57]
+ PIN la_oenb[58]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1669.290 -4.800 1669.850 2.400 ;
+ END
+ END la_oenb[58]
+ PIN la_oenb[59]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1687.230 -4.800 1687.790 2.400 ;
+ END
+ END la_oenb[59]
+ PIN la_oenb[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 729.510 -4.800 730.070 2.400 ;
+ END
+ END la_oenb[5]
+ PIN la_oenb[60]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1704.710 -4.800 1705.270 2.400 ;
+ END
+ END la_oenb[60]
+ PIN la_oenb[61]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1722.650 -4.800 1723.210 2.400 ;
+ END
+ END la_oenb[61]
+ PIN la_oenb[62]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1740.130 -4.800 1740.690 2.400 ;
+ END
+ END la_oenb[62]
+ PIN la_oenb[63]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1758.070 -4.800 1758.630 2.400 ;
+ END
+ END la_oenb[63]
+ PIN la_oenb[64]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1776.010 -4.800 1776.570 2.400 ;
+ END
+ END la_oenb[64]
+ PIN la_oenb[65]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1793.490 -4.800 1794.050 2.400 ;
+ END
+ END la_oenb[65]
+ PIN la_oenb[66]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1811.430 -4.800 1811.990 2.400 ;
+ END
+ END la_oenb[66]
+ PIN la_oenb[67]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1828.910 -4.800 1829.470 2.400 ;
+ END
+ END la_oenb[67]
+ PIN la_oenb[68]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1846.850 -4.800 1847.410 2.400 ;
+ END
+ END la_oenb[68]
+ PIN la_oenb[69]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1864.330 -4.800 1864.890 2.400 ;
+ END
+ END la_oenb[69]
+ PIN la_oenb[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 747.450 -4.800 748.010 2.400 ;
+ END
+ END la_oenb[6]
+ PIN la_oenb[70]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1882.270 -4.800 1882.830 2.400 ;
+ END
+ END la_oenb[70]
+ PIN la_oenb[71]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1899.750 -4.800 1900.310 2.400 ;
+ END
+ END la_oenb[71]
+ PIN la_oenb[72]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1917.690 -4.800 1918.250 2.400 ;
+ END
+ END la_oenb[72]
+ PIN la_oenb[73]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1935.630 -4.800 1936.190 2.400 ;
+ END
+ END la_oenb[73]
+ PIN la_oenb[74]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1953.110 -4.800 1953.670 2.400 ;
+ END
+ END la_oenb[74]
+ PIN la_oenb[75]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1971.050 -4.800 1971.610 2.400 ;
+ END
+ END la_oenb[75]
+ PIN la_oenb[76]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1988.530 -4.800 1989.090 2.400 ;
+ END
+ END la_oenb[76]
+ PIN la_oenb[77]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2006.470 -4.800 2007.030 2.400 ;
+ END
+ END la_oenb[77]
+ PIN la_oenb[78]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2023.950 -4.800 2024.510 2.400 ;
+ END
+ END la_oenb[78]
+ PIN la_oenb[79]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2041.890 -4.800 2042.450 2.400 ;
+ END
+ END la_oenb[79]
+ PIN la_oenb[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 764.930 -4.800 765.490 2.400 ;
+ END
+ END la_oenb[7]
+ PIN la_oenb[80]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2059.370 -4.800 2059.930 2.400 ;
+ END
+ END la_oenb[80]
+ PIN la_oenb[81]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2077.310 -4.800 2077.870 2.400 ;
+ END
+ END la_oenb[81]
+ PIN la_oenb[82]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2094.790 -4.800 2095.350 2.400 ;
+ END
+ END la_oenb[82]
+ PIN la_oenb[83]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2112.730 -4.800 2113.290 2.400 ;
+ END
+ END la_oenb[83]
+ PIN la_oenb[84]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2130.670 -4.800 2131.230 2.400 ;
+ END
+ END la_oenb[84]
+ PIN la_oenb[85]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2148.150 -4.800 2148.710 2.400 ;
+ END
+ END la_oenb[85]
+ PIN la_oenb[86]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2166.090 -4.800 2166.650 2.400 ;
+ END
+ END la_oenb[86]
+ PIN la_oenb[87]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2183.570 -4.800 2184.130 2.400 ;
+ END
+ END la_oenb[87]
+ PIN la_oenb[88]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2201.510 -4.800 2202.070 2.400 ;
+ END
+ END la_oenb[88]
+ PIN la_oenb[89]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2218.990 -4.800 2219.550 2.400 ;
+ END
+ END la_oenb[89]
+ PIN la_oenb[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 782.870 -4.800 783.430 2.400 ;
+ END
+ END la_oenb[8]
+ PIN la_oenb[90]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2236.930 -4.800 2237.490 2.400 ;
+ END
+ END la_oenb[90]
+ PIN la_oenb[91]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2254.410 -4.800 2254.970 2.400 ;
+ END
+ END la_oenb[91]
+ PIN la_oenb[92]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2272.350 -4.800 2272.910 2.400 ;
+ END
+ END la_oenb[92]
+ PIN la_oenb[93]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2290.290 -4.800 2290.850 2.400 ;
+ END
+ END la_oenb[93]
+ PIN la_oenb[94]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2307.770 -4.800 2308.330 2.400 ;
+ END
+ END la_oenb[94]
+ PIN la_oenb[95]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2325.710 -4.800 2326.270 2.400 ;
+ END
+ END la_oenb[95]
+ PIN la_oenb[96]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2343.190 -4.800 2343.750 2.400 ;
+ END
+ END la_oenb[96]
+ PIN la_oenb[97]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2361.130 -4.800 2361.690 2.400 ;
+ END
+ END la_oenb[97]
+ PIN la_oenb[98]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2378.610 -4.800 2379.170 2.400 ;
+ END
+ END la_oenb[98]
+ PIN la_oenb[99]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2396.550 -4.800 2397.110 2.400 ;
+ END
+ END la_oenb[99]
+ PIN la_oenb[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 800.350 -4.800 800.910 2.400 ;
+ END
+ END la_oenb[9]
+ PIN user_clock2
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2898.870 -4.800 2899.430 2.400 ;
+ END
+ END user_clock2
+ PIN user_irq[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2904.850 -4.800 2905.410 2.400 ;
+ END
+ END user_irq[0]
+ PIN user_irq[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2910.830 -4.800 2911.390 2.400 ;
+ END
+ END user_irq[1]
+ PIN user_irq[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2916.810 -4.800 2917.370 2.400 ;
+ END
+ END user_irq[2]
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 2.710 -4.800 3.270 2.400 ;
+ END
+ END wb_clk_i
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 8.230 -4.800 8.790 2.400 ;
+ END
+ END wb_rst_i
+ PIN wbs_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 14.210 -4.800 14.770 2.400 ;
+ END
+ END wbs_ack_o
+ PIN wbs_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 38.130 -4.800 38.690 2.400 ;
+ END
+ END wbs_adr_i[0]
+ PIN wbs_adr_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 239.150 -4.800 239.710 2.400 ;
+ END
+ END wbs_adr_i[10]
+ PIN wbs_adr_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 256.630 -4.800 257.190 2.400 ;
+ END
+ END wbs_adr_i[11]
+ PIN wbs_adr_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 274.570 -4.800 275.130 2.400 ;
+ END
+ END wbs_adr_i[12]
+ PIN wbs_adr_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 292.050 -4.800 292.610 2.400 ;
+ END
+ END wbs_adr_i[13]
+ PIN wbs_adr_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 309.990 -4.800 310.550 2.400 ;
+ END
+ END wbs_adr_i[14]
+ PIN wbs_adr_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.470 -4.800 328.030 2.400 ;
+ END
+ END wbs_adr_i[15]
+ PIN wbs_adr_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 345.410 -4.800 345.970 2.400 ;
+ END
+ END wbs_adr_i[16]
+ PIN wbs_adr_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 362.890 -4.800 363.450 2.400 ;
+ END
+ END wbs_adr_i[17]
+ PIN wbs_adr_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 380.830 -4.800 381.390 2.400 ;
+ END
+ END wbs_adr_i[18]
+ PIN wbs_adr_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 398.310 -4.800 398.870 2.400 ;
+ END
+ END wbs_adr_i[19]
+ PIN wbs_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 61.590 -4.800 62.150 2.400 ;
+ END
+ END wbs_adr_i[1]
+ PIN wbs_adr_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 416.250 -4.800 416.810 2.400 ;
+ END
+ END wbs_adr_i[20]
+ PIN wbs_adr_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.190 -4.800 434.750 2.400 ;
+ END
+ END wbs_adr_i[21]
+ PIN wbs_adr_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 451.670 -4.800 452.230 2.400 ;
+ END
+ END wbs_adr_i[22]
+ PIN wbs_adr_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 469.610 -4.800 470.170 2.400 ;
+ END
+ END wbs_adr_i[23]
+ PIN wbs_adr_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 487.090 -4.800 487.650 2.400 ;
+ END
+ END wbs_adr_i[24]
+ PIN wbs_adr_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 505.030 -4.800 505.590 2.400 ;
+ END
+ END wbs_adr_i[25]
+ PIN wbs_adr_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 522.510 -4.800 523.070 2.400 ;
+ END
+ END wbs_adr_i[26]
+ PIN wbs_adr_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 540.450 -4.800 541.010 2.400 ;
+ END
+ END wbs_adr_i[27]
+ PIN wbs_adr_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 557.930 -4.800 558.490 2.400 ;
+ END
+ END wbs_adr_i[28]
+ PIN wbs_adr_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 575.870 -4.800 576.430 2.400 ;
+ END
+ END wbs_adr_i[29]
+ PIN wbs_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 85.050 -4.800 85.610 2.400 ;
+ END
+ END wbs_adr_i[2]
+ PIN wbs_adr_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 593.810 -4.800 594.370 2.400 ;
+ END
+ END wbs_adr_i[30]
+ PIN wbs_adr_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 611.290 -4.800 611.850 2.400 ;
+ END
+ END wbs_adr_i[31]
+ PIN wbs_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 108.970 -4.800 109.530 2.400 ;
+ END
+ END wbs_adr_i[3]
+ PIN wbs_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 132.430 -4.800 132.990 2.400 ;
+ END
+ END wbs_adr_i[4]
+ PIN wbs_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 150.370 -4.800 150.930 2.400 ;
+ END
+ END wbs_adr_i[5]
+ PIN wbs_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 167.850 -4.800 168.410 2.400 ;
+ END
+ END wbs_adr_i[6]
+ PIN wbs_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 185.790 -4.800 186.350 2.400 ;
+ END
+ END wbs_adr_i[7]
+ PIN wbs_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 203.270 -4.800 203.830 2.400 ;
+ END
+ END wbs_adr_i[8]
+ PIN wbs_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 221.210 -4.800 221.770 2.400 ;
+ END
+ END wbs_adr_i[9]
+ PIN wbs_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 20.190 -4.800 20.750 2.400 ;
+ END
+ END wbs_cyc_i
+ PIN wbs_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 43.650 -4.800 44.210 2.400 ;
+ END
+ END wbs_dat_i[0]
+ PIN wbs_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 244.670 -4.800 245.230 2.400 ;
+ END
+ END wbs_dat_i[10]
+ PIN wbs_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 262.610 -4.800 263.170 2.400 ;
+ END
+ END wbs_dat_i[11]
+ PIN wbs_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 280.090 -4.800 280.650 2.400 ;
+ END
+ END wbs_dat_i[12]
+ PIN wbs_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 298.030 -4.800 298.590 2.400 ;
+ END
+ END wbs_dat_i[13]
+ PIN wbs_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 315.970 -4.800 316.530 2.400 ;
+ END
+ END wbs_dat_i[14]
+ PIN wbs_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 333.450 -4.800 334.010 2.400 ;
+ END
+ END wbs_dat_i[15]
+ PIN wbs_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 351.390 -4.800 351.950 2.400 ;
+ END
+ END wbs_dat_i[16]
+ PIN wbs_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 368.870 -4.800 369.430 2.400 ;
+ END
+ END wbs_dat_i[17]
+ PIN wbs_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 386.810 -4.800 387.370 2.400 ;
+ END
+ END wbs_dat_i[18]
+ PIN wbs_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 404.290 -4.800 404.850 2.400 ;
+ END
+ END wbs_dat_i[19]
+ PIN wbs_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 67.570 -4.800 68.130 2.400 ;
+ END
+ END wbs_dat_i[1]
+ PIN wbs_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 422.230 -4.800 422.790 2.400 ;
+ END
+ END wbs_dat_i[20]
+ PIN wbs_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 439.710 -4.800 440.270 2.400 ;
+ END
+ END wbs_dat_i[21]
+ PIN wbs_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 457.650 -4.800 458.210 2.400 ;
+ END
+ END wbs_dat_i[22]
+ PIN wbs_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 475.590 -4.800 476.150 2.400 ;
+ END
+ END wbs_dat_i[23]
+ PIN wbs_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 493.070 -4.800 493.630 2.400 ;
+ END
+ END wbs_dat_i[24]
+ PIN wbs_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 511.010 -4.800 511.570 2.400 ;
+ END
+ END wbs_dat_i[25]
+ PIN wbs_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 528.490 -4.800 529.050 2.400 ;
+ END
+ END wbs_dat_i[26]
+ PIN wbs_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 546.430 -4.800 546.990 2.400 ;
+ END
+ END wbs_dat_i[27]
+ PIN wbs_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 563.910 -4.800 564.470 2.400 ;
+ END
+ END wbs_dat_i[28]
+ PIN wbs_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 581.850 -4.800 582.410 2.400 ;
+ END
+ END wbs_dat_i[29]
+ PIN wbs_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 91.030 -4.800 91.590 2.400 ;
+ END
+ END wbs_dat_i[2]
+ PIN wbs_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 599.330 -4.800 599.890 2.400 ;
+ END
+ END wbs_dat_i[30]
+ PIN wbs_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 617.270 -4.800 617.830 2.400 ;
+ END
+ END wbs_dat_i[31]
+ PIN wbs_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 114.950 -4.800 115.510 2.400 ;
+ END
+ END wbs_dat_i[3]
+ PIN wbs_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 138.410 -4.800 138.970 2.400 ;
+ END
+ END wbs_dat_i[4]
+ PIN wbs_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 156.350 -4.800 156.910 2.400 ;
+ END
+ END wbs_dat_i[5]
+ PIN wbs_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 173.830 -4.800 174.390 2.400 ;
+ END
+ END wbs_dat_i[6]
+ PIN wbs_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 191.770 -4.800 192.330 2.400 ;
+ END
+ END wbs_dat_i[7]
+ PIN wbs_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.250 -4.800 209.810 2.400 ;
+ END
+ END wbs_dat_i[8]
+ PIN wbs_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 227.190 -4.800 227.750 2.400 ;
+ END
+ END wbs_dat_i[9]
+ PIN wbs_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 49.630 -4.800 50.190 2.400 ;
+ END
+ END wbs_dat_o[0]
+ PIN wbs_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 250.650 -4.800 251.210 2.400 ;
+ END
+ END wbs_dat_o[10]
+ PIN wbs_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 268.590 -4.800 269.150 2.400 ;
+ END
+ END wbs_dat_o[11]
+ PIN wbs_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 286.070 -4.800 286.630 2.400 ;
+ END
+ END wbs_dat_o[12]
+ PIN wbs_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 304.010 -4.800 304.570 2.400 ;
+ END
+ END wbs_dat_o[13]
+ PIN wbs_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 321.490 -4.800 322.050 2.400 ;
+ END
+ END wbs_dat_o[14]
+ PIN wbs_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 339.430 -4.800 339.990 2.400 ;
+ END
+ END wbs_dat_o[15]
+ PIN wbs_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 357.370 -4.800 357.930 2.400 ;
+ END
+ END wbs_dat_o[16]
+ PIN wbs_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 374.850 -4.800 375.410 2.400 ;
+ END
+ END wbs_dat_o[17]
+ PIN wbs_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 392.790 -4.800 393.350 2.400 ;
+ END
+ END wbs_dat_o[18]
+ PIN wbs_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 410.270 -4.800 410.830 2.400 ;
+ END
+ END wbs_dat_o[19]
+ PIN wbs_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 73.550 -4.800 74.110 2.400 ;
+ END
+ END wbs_dat_o[1]
+ PIN wbs_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 428.210 -4.800 428.770 2.400 ;
+ END
+ END wbs_dat_o[20]
+ PIN wbs_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 445.690 -4.800 446.250 2.400 ;
+ END
+ END wbs_dat_o[21]
+ PIN wbs_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 463.630 -4.800 464.190 2.400 ;
+ END
+ END wbs_dat_o[22]
+ PIN wbs_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 481.110 -4.800 481.670 2.400 ;
+ END
+ END wbs_dat_o[23]
+ PIN wbs_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 499.050 -4.800 499.610 2.400 ;
+ END
+ END wbs_dat_o[24]
+ PIN wbs_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 516.530 -4.800 517.090 2.400 ;
+ END
+ END wbs_dat_o[25]
+ PIN wbs_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 534.470 -4.800 535.030 2.400 ;
+ END
+ END wbs_dat_o[26]
+ PIN wbs_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 552.410 -4.800 552.970 2.400 ;
+ END
+ END wbs_dat_o[27]
+ PIN wbs_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 569.890 -4.800 570.450 2.400 ;
+ END
+ END wbs_dat_o[28]
+ PIN wbs_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 587.830 -4.800 588.390 2.400 ;
+ END
+ END wbs_dat_o[29]
+ PIN wbs_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 97.010 -4.800 97.570 2.400 ;
+ END
+ END wbs_dat_o[2]
+ PIN wbs_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 605.310 -4.800 605.870 2.400 ;
+ END
+ END wbs_dat_o[30]
+ PIN wbs_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 623.250 -4.800 623.810 2.400 ;
+ END
+ END wbs_dat_o[31]
+ PIN wbs_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 120.930 -4.800 121.490 2.400 ;
+ END
+ END wbs_dat_o[3]
+ PIN wbs_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 144.390 -4.800 144.950 2.400 ;
+ END
+ END wbs_dat_o[4]
+ PIN wbs_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 161.870 -4.800 162.430 2.400 ;
+ END
+ END wbs_dat_o[5]
+ PIN wbs_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 179.810 -4.800 180.370 2.400 ;
+ END
+ END wbs_dat_o[6]
+ PIN wbs_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 197.750 -4.800 198.310 2.400 ;
+ END
+ END wbs_dat_o[7]
+ PIN wbs_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 215.230 -4.800 215.790 2.400 ;
+ END
+ END wbs_dat_o[8]
+ PIN wbs_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 233.170 -4.800 233.730 2.400 ;
+ END
+ END wbs_dat_o[9]
+ PIN wbs_sel_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 55.610 -4.800 56.170 2.400 ;
+ END
+ END wbs_sel_i[0]
+ PIN wbs_sel_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 79.530 -4.800 80.090 2.400 ;
+ END
+ END wbs_sel_i[1]
+ PIN wbs_sel_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 102.990 -4.800 103.550 2.400 ;
+ END
+ END wbs_sel_i[2]
+ PIN wbs_sel_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 126.450 -4.800 127.010 2.400 ;
+ END
+ END wbs_sel_i[3]
+ PIN wbs_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 26.170 -4.800 26.730 2.400 ;
+ END
+ END wbs_stb_i
+ PIN wbs_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 32.150 -4.800 32.710 2.400 ;
+ END
+ END wbs_we_i
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2888.970 -9.470 2892.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2708.970 -9.470 2712.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2528.970 -9.470 2532.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2348.970 -9.470 2352.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2168.970 -9.470 2172.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1988.970 -9.470 1992.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1808.970 -9.470 1812.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1628.970 -9.470 1632.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1448.970 -9.470 1452.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1268.970 -9.470 1272.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1088.970 -9.470 1092.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 908.970 -9.470 912.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 728.970 -9.470 732.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 548.970 -9.470 552.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 368.970 -9.470 372.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 188.970 -9.470 192.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 8.970 -9.470 12.070 3529.150 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2926.550 -4.670 2929.650 3524.350 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT -10.030 -4.670 -6.930 3524.350 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -10.030 3521.250 2929.650 3524.350 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 3434.090 2934.450 3437.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 3254.090 2934.450 3257.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 3074.090 2934.450 3077.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2894.090 2934.450 2897.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2714.090 2934.450 2717.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2534.090 2934.450 2537.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2354.090 2934.450 2357.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2174.090 2934.450 2177.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1994.090 2934.450 1997.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1814.090 2934.450 1817.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1634.090 2934.450 1637.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1454.090 2934.450 1457.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1274.090 2934.450 1277.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1094.090 2934.450 1097.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 914.090 2934.450 917.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 734.090 2934.450 737.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 554.090 2934.450 557.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 374.090 2934.450 377.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 194.090 2934.450 197.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 14.090 2934.450 17.190 ;
+ END
+ END vccd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -10.030 -4.670 2929.650 -1.570 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2931.350 -9.470 2934.450 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2798.970 -9.470 2802.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2618.970 -9.470 2622.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2438.970 -9.470 2442.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2258.970 -9.470 2262.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2078.970 -9.470 2082.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1898.970 -9.470 1902.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1718.970 -9.470 1722.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1538.970 -9.470 1542.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1358.970 -9.470 1362.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1178.970 -9.470 1182.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 998.970 -9.470 1002.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 818.970 -9.470 822.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 638.970 -9.470 642.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 458.970 -9.470 462.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 278.970 -9.470 282.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 98.970 -9.470 102.070 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT -14.830 -9.470 -11.730 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 3526.050 2934.450 3529.150 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 3344.090 2934.450 3347.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 3164.090 2934.450 3167.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2984.090 2934.450 2987.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2804.090 2934.450 2807.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2624.090 2934.450 2627.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2444.090 2934.450 2447.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2264.090 2934.450 2267.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 2084.090 2934.450 2087.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1904.090 2934.450 1907.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1724.090 2934.450 1727.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1544.090 2934.450 1547.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1364.090 2934.450 1367.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1184.090 2934.450 1187.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 1004.090 2934.450 1007.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 824.090 2934.450 827.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 644.090 2934.450 647.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 464.090 2934.450 467.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 284.090 2934.450 287.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 104.090 2934.450 107.190 ;
+ END
+ END vssd1
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -14.830 -9.470 2934.450 -6.370 ;
+ END
+ END vssd1
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2907.570 -19.070 2910.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2727.570 -19.070 2730.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2547.570 -19.070 2550.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2367.570 -19.070 2370.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2187.570 -19.070 2190.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2007.570 -19.070 2010.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1827.570 -19.070 1830.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1647.570 -19.070 1650.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1467.570 -19.070 1470.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1287.570 -19.070 1290.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1107.570 -19.070 1110.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 927.570 -19.070 930.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 747.570 -19.070 750.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 567.570 -19.070 570.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 387.570 -19.070 390.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 207.570 -19.070 210.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 27.570 -19.070 30.670 3538.750 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2936.150 -14.270 2939.250 3533.950 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT -19.630 -14.270 -16.530 3533.950 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -19.630 3530.850 2939.250 3533.950 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3452.930 2944.050 3456.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3272.930 2944.050 3276.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3092.930 2944.050 3096.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2912.930 2944.050 2916.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2732.930 2944.050 2736.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2552.930 2944.050 2556.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2372.930 2944.050 2376.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2192.930 2944.050 2196.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2012.930 2944.050 2016.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1832.930 2944.050 1836.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1652.930 2944.050 1656.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1472.930 2944.050 1476.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1292.930 2944.050 1296.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1112.930 2944.050 1116.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 932.930 2944.050 936.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 752.930 2944.050 756.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 572.930 2944.050 576.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 392.930 2944.050 396.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 212.930 2944.050 216.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 32.930 2944.050 36.030 ;
+ END
+ END vccd2
+ PIN vccd2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -19.630 -14.270 2939.250 -11.170 ;
+ END
+ END vccd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2940.950 -19.070 2944.050 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2817.570 -19.070 2820.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2637.570 -19.070 2640.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2457.570 -19.070 2460.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2277.570 -19.070 2280.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2097.570 -19.070 2100.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1917.570 -19.070 1920.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1737.570 -19.070 1740.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1557.570 -19.070 1560.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1377.570 -19.070 1380.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1197.570 -19.070 1200.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1017.570 -19.070 1020.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 837.570 -19.070 840.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 657.570 -19.070 660.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 477.570 -19.070 480.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 297.570 -19.070 300.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 117.570 -19.070 120.670 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT -24.430 -19.070 -21.330 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3535.650 2944.050 3538.750 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3362.930 2944.050 3366.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3182.930 2944.050 3186.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 3002.930 2944.050 3006.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2822.930 2944.050 2826.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2642.930 2944.050 2646.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2462.930 2944.050 2466.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2282.930 2944.050 2286.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 2102.930 2944.050 2106.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1922.930 2944.050 1926.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1742.930 2944.050 1746.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1562.930 2944.050 1566.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1382.930 2944.050 1386.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1202.930 2944.050 1206.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 1022.930 2944.050 1026.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 842.930 2944.050 846.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 662.930 2944.050 666.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 482.930 2944.050 486.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 302.930 2944.050 306.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 122.930 2944.050 126.030 ;
+ END
+ END vssd2
+ PIN vssd2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -24.430 -19.070 2944.050 -15.970 ;
+ END
+ END vssd2
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2746.170 -28.670 2749.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2566.170 -28.670 2569.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2386.170 -28.670 2389.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2206.170 -28.670 2209.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2026.170 -28.670 2029.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1846.170 -28.670 1849.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1666.170 -28.670 1669.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1486.170 -28.670 1489.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1306.170 -28.670 1309.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1126.170 -28.670 1129.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 946.170 -28.670 949.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 766.170 -28.670 769.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 586.170 -28.670 589.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 406.170 -28.670 409.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 226.170 -28.670 229.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 46.170 -28.670 49.270 3548.350 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2945.750 -23.870 2948.850 3543.550 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT -29.230 -23.870 -26.130 3543.550 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -29.230 3540.450 2948.850 3543.550 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3471.530 2953.650 3474.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3291.530 2953.650 3294.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3111.530 2953.650 3114.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2931.530 2953.650 2934.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2751.530 2953.650 2754.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2571.530 2953.650 2574.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2391.530 2953.650 2394.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2211.530 2953.650 2214.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2031.530 2953.650 2034.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1851.530 2953.650 1854.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1671.530 2953.650 1674.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1491.530 2953.650 1494.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1311.530 2953.650 1314.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1131.530 2953.650 1134.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 951.530 2953.650 954.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 771.530 2953.650 774.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 591.530 2953.650 594.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 411.530 2953.650 414.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 231.530 2953.650 234.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 51.530 2953.650 54.630 ;
+ END
+ END vdda1
+ PIN vdda1
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -29.230 -23.870 2948.850 -20.770 ;
+ END
+ END vdda1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2950.550 -28.670 2953.650 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2836.170 -28.670 2839.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2656.170 -28.670 2659.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2476.170 -28.670 2479.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2296.170 -28.670 2299.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2116.170 -28.670 2119.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1936.170 -28.670 1939.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1756.170 -28.670 1759.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1576.170 -28.670 1579.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1396.170 -28.670 1399.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1216.170 -28.670 1219.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1036.170 -28.670 1039.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 856.170 -28.670 859.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 676.170 -28.670 679.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 496.170 -28.670 499.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 316.170 -28.670 319.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 136.170 -28.670 139.270 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT -34.030 -28.670 -30.930 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3545.250 2953.650 3548.350 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3381.530 2953.650 3384.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3201.530 2953.650 3204.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 3021.530 2953.650 3024.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2841.530 2953.650 2844.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2661.530 2953.650 2664.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2481.530 2953.650 2484.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2301.530 2953.650 2304.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 2121.530 2953.650 2124.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1941.530 2953.650 1944.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1761.530 2953.650 1764.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1581.530 2953.650 1584.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1401.530 2953.650 1404.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1221.530 2953.650 1224.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 1041.530 2953.650 1044.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 861.530 2953.650 864.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 681.530 2953.650 684.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 501.530 2953.650 504.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 321.530 2953.650 324.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 141.530 2953.650 144.630 ;
+ END
+ END vssa1
+ PIN vssa1
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -34.030 -28.670 2953.650 -25.570 ;
+ END
+ END vssa1
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2764.770 -38.270 2767.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2584.770 -38.270 2587.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2404.770 -38.270 2407.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2224.770 -38.270 2227.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2044.770 -38.270 2047.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1864.770 -38.270 1867.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1684.770 -38.270 1687.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1504.770 -38.270 1507.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1324.770 -38.270 1327.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 1144.770 -38.270 1147.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 964.770 -38.270 967.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 784.770 -38.270 787.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 604.770 -38.270 607.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 424.770 -38.270 427.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 244.770 -38.270 247.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 64.770 -38.270 67.870 3557.950 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 2955.350 -33.470 2958.450 3553.150 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT -38.830 -33.470 -35.730 3553.150 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -38.830 3550.050 2958.450 3553.150 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3490.130 2963.250 3493.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3310.130 2963.250 3313.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3130.130 2963.250 3133.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2950.130 2963.250 2953.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2770.130 2963.250 2773.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2590.130 2963.250 2593.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2410.130 2963.250 2413.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2230.130 2963.250 2233.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2050.130 2963.250 2053.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1870.130 2963.250 1873.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1690.130 2963.250 1693.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1510.130 2963.250 1513.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1330.130 2963.250 1333.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1150.130 2963.250 1153.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 970.130 2963.250 973.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 790.130 2963.250 793.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 610.130 2963.250 613.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 430.130 2963.250 433.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 250.130 2963.250 253.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 70.130 2963.250 73.230 ;
+ END
+ END vdda2
+ PIN vdda2
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT -38.830 -33.470 2958.450 -30.370 ;
+ END
+ END vdda2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2960.150 -38.270 2963.250 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2854.770 -38.270 2857.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2674.770 -38.270 2677.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2494.770 -38.270 2497.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2314.770 -38.270 2317.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 2134.770 -38.270 2137.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1954.770 -38.270 1957.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1774.770 -38.270 1777.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1594.770 -38.270 1597.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1414.770 -38.270 1417.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1234.770 -38.270 1237.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 1054.770 -38.270 1057.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 874.770 -38.270 877.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 694.770 -38.270 697.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 514.770 -38.270 517.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 334.770 -38.270 337.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 154.770 -38.270 157.870 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT -43.630 -38.270 -40.530 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3554.850 2963.250 3557.950 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3400.130 2963.250 3403.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3220.130 2963.250 3223.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 3040.130 2963.250 3043.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2860.130 2963.250 2863.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2680.130 2963.250 2683.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2500.130 2963.250 2503.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2320.130 2963.250 2323.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 2140.130 2963.250 2143.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1960.130 2963.250 1963.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1780.130 2963.250 1783.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1600.130 2963.250 1603.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1420.130 2963.250 1423.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1240.130 2963.250 1243.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 1060.130 2963.250 1063.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 880.130 2963.250 883.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 700.130 2963.250 703.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 520.130 2963.250 523.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 340.130 2963.250 343.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 160.130 2963.250 163.230 ;
+ END
+ END vssa2
+ PIN vssa2
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT -43.630 -38.270 2963.250 -35.170 ;
+ END
+ END vssa2
+ OBS
+ LAYER met1 ;
+ RECT 5.520 10.640 2914.100 3509.040 ;
+ LAYER met2 ;
+ RECT 9.110 10.640 2891.930 3509.040 ;
+ LAYER met3 ;
+ RECT 8.970 10.715 2892.070 3508.965 ;
+ END
+END user_project_wrapper
+END LIBRARY
+
diff --git a/caravel/mag/user_analog_project_wrapper_empty.mag b/caravel/mag/user_analog_project_wrapper_empty.mag
new file mode 120000
index 0000000..7aab9c6
--- /dev/null
+++ b/caravel/mag/user_analog_project_wrapper_empty.mag
@@ -0,0 +1 @@
+user_analog_project_wrapper.mag
\ No newline at end of file
diff --git a/caravel/manifest b/caravel/manifest
new file mode 100644
index 0000000..3e2ffa7
--- /dev/null
+++ b/caravel/manifest
@@ -0,0 +1,48 @@
+0ca19fc3c20b483c8691ba25ed131648e6c194d3 verilog/rtl/DFFRAM.v
+216d603c97eb28f4e8957e534116c0caa5711bbd verilog/rtl/DFFRAMBB.v
+535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
+87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
+684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
+b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
+7c25df2bd392893aa5b6fb0074332ea605ac3ed7 verilog/rtl/caravan.v
+e7d48588820f78c23284f663e99def4e43e59af3 verilog/rtl/caravan_netlists.v
+8623f6eace1f0d16dea0f1dfcc6357ddb7657781 verilog/rtl/caravel.v
+b2feeb2a098894d5d731a5b011858a471e855d73 verilog/rtl/caravel_clocking.v
+b707ae2325692f0441dfcd27272a9ad8611771bd verilog/rtl/chip_io.v
+614e2abd6759e927bc1c0bae4149169b0a444165 verilog/rtl/chip_io_alt.v
+d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c verilog/rtl/clock_div.v
+f937b52e53d45bdbe41bcbd07c65b41104c21756 verilog/rtl/convert_gpio_sigs.v
+21204dc96bdb3c1295dd06375293ee3d811d2f7e verilog/rtl/counter_timer_high.v
+6b9b2ab85a85f73d6ce686c67fc85e59d9623ee6 verilog/rtl/counter_timer_low.v
+fff2d08e49701312c2ebd6714b7425baf83f3d35 verilog/rtl/digital_pll.v
+ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
+a1878558828b746a90d391bfe72ff0c1fadc2d92 verilog/rtl/gpio_control_block.v
+32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
+57554b3586f306944b31718a8c52526fa9a8a574 verilog/rtl/gpio_wb.v
+240d94f4783872b541879e8a7a0c6d9144aa8a91 verilog/rtl/housekeeping_spi.v
+6c11ee92e0b2995982041d8a599b5d46b7dde838 verilog/rtl/la_wb.v
+e04eb60b98cf1c0ab1aeca22cbe985080b6e3d47 verilog/rtl/mem_wb.v
+45d465b5cec158d2ad6d6b9a8595a58326fa12bb verilog/rtl/mgmt_core.v
+e12b24540b26523131cfed8f17e79df5ba2f067e verilog/rtl/mgmt_protect.v
+3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
+cc5704c74e5c46a73b96ba6804ff9ed1e3d4594c verilog/rtl/mgmt_soc.v
+9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
+4b76489a9d03c0411d16dbad9c38cdcfef8d0f72 verilog/rtl/mprj_ctrl.v
+a61f5566f5d369d879c47d6b65f99cf297debe8f verilog/rtl/mprj_io.v
+b928ab6205a267f6ac83c603965c6f34a486724e verilog/rtl/mprj_logic_high.v
+eac1e6d413cdfbc2f802e229ae5058828e01be1e verilog/rtl/pads.v
+b5aff2fda5078cfda377b98337fcc91040815fc2 verilog/rtl/picorv32.v
+669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
+6864cc10dacfd3edb4c66825b7a301ab097cea0d verilog/rtl/simple_por.v
+cf08cb295ed068ccb521b9203a8dee2bb83446ee verilog/rtl/simple_spi_master.v
+d43221ffa0f2d760991d8b911b4a5292911203f5 verilog/rtl/simpleuart.v
+46bca62460c4dbfac30233318b24c3d526a40058 verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+eb0c856ab69e8c364c04bdc149db9d82ae67b39d verilog/rtl/spimemio.v
+ff5fd967e7401e07ecce4e973746568354a6dcb8 verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+cee5f1b535ce1f483fa69678255b543c408f1fb7 verilog/rtl/storage.v
+7e8d789570ed224df49cf61f69593cc738790a5d verilog/rtl/storage_bridge_wb.v
+5e314e94a13d7291117123395ae088e1d17cf487 verilog/rtl/sysctrl.v
+e6246df6bbf0860a331b3547d64f7d235b0eca9a verilog/rtl/wb_intercon.v
+9d06bd68e8ec6918cd3ef5467cb8cee44e7e3a26 scripts/set_user_id.py
+e20a41180aef509c5dc06f15c4458eed90651c5a scripts/generate_fill.py
+b676e0bf6f1c287d0a67ca4cd2d7ef0760284be1 scripts/compositor.py
diff --git a/caravel/openlane/Makefile b/caravel/openlane/Makefile
new file mode 100644
index 0000000..9398841
--- /dev/null
+++ b/caravel/openlane/Makefile
@@ -0,0 +1,90 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= 2021.09.19_20.25.16
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+ @echo "Missing $@. Please create a configuration for that design"
+ @exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
+ @sleep 1
+
+ @if [ -f ./$*/interactive.tcl ]; then\
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:/project \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+ else\
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:/project \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+ fi
+ mkdir -p ../signoff/$*/
+ cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ make openlane
+
+FORCE:
+
+clean:
+ @echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+ rm -rf runs/$*
+ rm -rf ../gds/$**
+ rm -rf ../mag/$**
+ rm -rf ../lef/$**
diff --git a/caravel/openlane/user_analog_project_wrapper_empty/config.tcl b/caravel/openlane/user_analog_project_wrapper_empty/config.tcl
new file mode 100644
index 0000000..6e1414a
--- /dev/null
+++ b/caravel/openlane/user_analog_project_wrapper_empty/config.tcl
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+source $script_dir/fixed_wrapper_cfgs.tcl
+
+set ::env(DESIGN_NAME) user_analog_project_wrapper
+
+set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
+ met2 0 0 $::env(DIE_AREA),\
+ met3 0 0 $::env(DIE_AREA),\
+ met4 0 0 $::env(DIE_AREA),\
+ met5 0 0 $::env(DIE_AREA)"
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
+
+set ::env(MAGIC_WRITE_FULL_LEF) 1
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/__user_analog_project_wrapper.v"
diff --git a/caravel/openlane/user_analog_project_wrapper_empty/fixed_wrapper_cfgs.tcl b/caravel/openlane/user_analog_project_wrapper_empty/fixed_wrapper_cfgs.tcl
new file mode 100644
index 0000000..a4778c7
--- /dev/null
+++ b/caravel/openlane/user_analog_project_wrapper_empty/fixed_wrapper_cfgs.tcl
@@ -0,0 +1,41 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+# Pin Configurations. DON'T TOUCH
+set ::unit 2.4
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 0
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
\ No newline at end of file
diff --git a/caravel/openlane/user_analog_project_wrapper_empty/interactive.tcl b/caravel/openlane/user_analog_project_wrapper_empty/interactive.tcl
new file mode 100644
index 0000000..f67a7d7
--- /dev/null
+++ b/caravel/openlane/user_analog_project_wrapper_empty/interactive.tcl
@@ -0,0 +1,65 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag user_analog_project_wrapper_empty -overwrite
+set save_path $script_dir/../..
+
+verilog_elaborate
+
+init_floorplan
+
+# making it "empty"
+remove_nets -input $::env(CURRENT_DEF)
+remove_components -input $::env(CURRENT_DEF)
+
+set ::env(SAVE_DEF) [index_file $::env(ioPlacer_tmp_file_tag).def]
+try_catch openroad -exit $script_dir/or_ioplace.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(ioPlacer_log_file_tag).log 0]
+set_def $::env(SAVE_DEF)
+
+# rename "duplicate" pins
+exec /bin/bash $script_dir/../../utils/rename_pins.sh $::env(SAVE_DEF) "io_analog_1_4,io_analog_1_5,io_analog_1_6,vdda1_1,vdda1_2,vdda1_3,vdda2_1,vssa1_1,vssa1_2,vssa1_3,vssa2_1,vccd1_1,vccd2_1,vssd1_1,vssd2_1" "io_analog\[4\],io_analog\[5\],io_analog\[6\],vdda1,vdda1,vdda1,vdda2,vssa1,vssa1,vssa1,vssa2,vccd1,vccd2,vssd1,vssd2"
+
+run_magic
+
+run_magic_drc
+
+save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(CURRENT_DEF) \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -save_path $save_path \
+ -tag $::env(RUN_TAG)
+
+# make pin labels visible in the magview
+exec /bin/bash $script_dir/../../utils/export_pin_labels.sh $script_dir/../../mag/$::env(RUN_TAG).mag 0 3498 2920 3520 0 -20 2920 4 >@stdout 2>@stderr
+
+# Draw Boundary in the magview
+exec /bin/bash $script_dir/../../utils/draw_boundary.sh $script_dir/../../mag/$::env(RUN_TAG).mag 0 0 2920 3520 >@stdout 2>@stderr
+
+# produce "obstructed" LEF to be used for routing
+set gap 0.4
+set llx [expr [lindex $::env(DIE_AREA) 0]-$gap]
+set lly [expr [lindex $::env(DIE_AREA) 1]-$gap]
+set urx [expr [lindex $::env(DIE_AREA) 2]+$gap]
+set ury [expr [lindex $::env(DIE_AREA) 3]+$gap]
+exec python3 $::env(OPENLANE_ROOT)/scripts/rectify.py $llx $lly $urx $ury \
+ < $::env(magic_result_file_tag).lef \
+ | python3 $::env(OPENLANE_ROOT)/scripts/obs.py {*}$::env(DIE_AREA) li1 met1 met2 met3 \
+ | python3 $::env(OPENLANE_ROOT)/scripts/obs.py -42.88 -37.53 2962.50 3557.21 met4 met5 \
+ > $::env(magic_result_file_tag).obstructed.lef
+file copy -force $::env(magic_result_file_tag).obstructed.lef $save_path/lef
\ No newline at end of file
diff --git a/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl b/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl
new file mode 100644
index 0000000..65abbe2
--- /dev/null
+++ b/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl
@@ -0,0 +1,279 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+## Needs OpenRoad Commit: 29db63fdda643f01d5a7705606a96681ab855a68
+
+if {[catch {read_lef $::env(MERGED_LEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+ppl::set_hor_length $::env(FP_IO_HLENGTH)
+ppl::set_ver_length $::env(FP_IO_VLENGTH)
+ppl::set_hor_length_extend $::env(FP_IO_VEXTEND)
+ppl::set_ver_length_extend $::env(FP_IO_HEXTEND)
+ppl::set_ver_thick_multiplier $::env(FP_IO_VTHICKNESS_MULT)
+ppl::set_hor_thick_multiplier $::env(FP_IO_HTHICKNESS_MULT)
+
+## Config
+set core_area_x 2920
+set core_area_y 3520
+
+set analog_pin_size 25
+lappend analog_pin_size 8.5
+
+set clamp_pin_size 11
+lappend clamp_pin_size 8.5
+
+set power_pin_size 24
+lappend power_pin_size 8.3
+
+set pin_width 0.56
+set pin_height 2.40
+set pin_extension 4
+
+set regular_pin_size $pin_width
+lappend regular_pin_size [expr {$pin_height + $pin_extension}]
+
+set power_pins {vdda1 vdda1_1 vdda1_2 vdda1_3 vdda2 vdda2_1 vssa1 vssa1_1 vssa1_2 vssa1_3 vssa2 vssa2_1 vccd1 vccd1_1 vccd2 vccd2_1 vssd1 vssd1_1 vssd2 vssd2_1}
+
+## North Pins
+set north_pins { io_analog[1] vssa1 vssa1_1 io_analog[2] io_analog[3]
+ io_analog[4] io_clamp_high[0] io_clamp_low[0] io_analog_1_4
+ io_analog[5] io_clamp_high[1] io_clamp_low[1] io_analog_1_5
+ io_analog[6] io_clamp_high[2] io_clamp_low[2] io_analog_1_6
+ io_analog[7] io_analog[8] io_analog[9] }
+
+set offset_x 80.97
+set min_distance 235
+set clamp_min_distance 1.5
+set io_5to4_distance 432
+set io_4to3_distance 395.5
+
+set spacing_list [list 0 235 235 202 1.5 1.5 1.5 182 1.5 1.5 1.5 $io_5to4_distance 1.5 1.5 1.5 $io_4to3_distance 235 201 26 206]
+
+set i 0
+foreach pin [lreverse $north_pins] {
+
+ if {[string match "io_clamp*" $pin]} {
+ set pin_size $clamp_pin_size
+ } elseif { $pin in $power_pins} {
+ set pin_size $power_pin_size
+ } else {
+ set pin_size $analog_pin_size
+ }
+
+ set loc_y [expr {$core_area_y - [lindex $pin_size 1] / 2.0}]
+
+ if { $i==0 } {
+ set location [expr {$offset_x + [lindex $pin_size 0] / 2.0}]
+ } else {
+ set loc_x [expr {[lindex $prev_pin_size 0] / 2.0 + [lindex $pin_size 0] / 2.0 + [lindex $spacing_list $i] + [lindex $location 0]}]
+ set location $loc_x
+ }
+
+ lappend location $loc_y
+ puts $location
+ place_pin -pin_name $pin -layer met3 -location $location -pin_size $pin_size
+ set i [expr {$i + 1}]
+ set prev_pin_size $pin_size
+}
+
+## East Pins
+set east_pins { io_analog[0]
+ vccd1 vccd1_1
+ io_oeb[13] io_out[13] io_in[13] io_in_3v3[13] gpio_noesd[6] gpio_analog[6]
+ vdda1_1 vdda1
+ io_oeb[12] io_out[12] io_in[12] io_in_3v3[12] gpio_noesd[5] gpio_analog[5]
+ io_oeb[11] io_out[11] io_in[11] io_in_3v3[11] gpio_noesd[4] gpio_analog[4]
+ io_oeb[10] io_out[10] io_in[10] io_in_3v3[10] gpio_noesd[3] gpio_analog[3]
+ io_oeb[9] io_out[9] io_in[9] io_in_3v3[9] gpio_noesd[2] gpio_analog[2]
+ io_oeb[8] io_out[8] io_in[8] io_in_3v3[8] gpio_noesd[1] gpio_analog[1]
+ io_oeb[7] io_out[7] io_in[7] io_in_3v3[7] gpio_noesd[0] gpio_analog[0]
+ vdda1_2 vdda1_3
+ vssd1 vssd1_1
+ vssa1_2 vssa1_3
+ io_oeb[6] io_out[6] io_in[6] io_in_3v3[6]
+ io_oeb[5] io_out[5] io_in[5] io_in_3v3[5]
+ io_oeb[4] io_out[4] io_in[4] io_in_3v3[4]
+ io_oeb[3] io_out[3] io_in[3] io_in_3v3[3]
+ io_oeb[2] io_out[2] io_in[2] io_in_3v3[2]
+ io_oeb[1] io_out[1] io_in[1] io_in_3v3[1]
+ io_oeb[0] io_out[0] io_in[0] io_in_3v3[0]
+}
+
+set min_distance 5.35
+
+set spacing_list " 0
+ $min_distance $min_distance $min_distance $min_distance
+ $min_distance $min_distance $min_distance $min_distance
+ $min_distance $min_distance $min_distance $min_distance
+ $min_distance $min_distance $min_distance $min_distance
+ $min_distance $min_distance $min_distance 114
+ $min_distance $min_distance $min_distance 205
+ $min_distance $min_distance $min_distance 208
+ 26 149
+ 26 145
+ 26 146
+ $min_distance $min_distance $min_distance $min_distance $min_distance 192
+ $min_distance $min_distance $min_distance $min_distance $min_distance 196
+ $min_distance $min_distance $min_distance $min_distance $min_distance 202
+ $min_distance $min_distance $min_distance $min_distance $min_distance 192
+ $min_distance $min_distance $min_distance $min_distance $min_distance 192
+ $min_distance $min_distance $min_distance $min_distance $min_distance 202
+ 26 141
+ $min_distance $min_distance $min_distance $min_distance $min_distance 201
+ 26 167 "
+
+set offset_y 8
+
+set size $pin_height
+lappend size $pin_width
+
+
+set i 0
+set location 0
+lappend location $offset_y
+
+foreach pin [lreverse $east_pins] {
+
+ if {[string match "io_analog*" $pin]} {
+ set pin_size [lreverse $analog_pin_size]
+ set loc_x [expr {$core_area_x - [lindex $pin_size 0] / 2.0 }]
+ } elseif { $pin in $power_pins } {
+ set pin_size [lreverse $power_pin_size]
+ set loc_x [expr {$core_area_x - [lindex $pin_size 0] / 2.0 }]
+ } else {
+ set pin_size [lreverse $regular_pin_size]
+ set loc_x [expr {$core_area_x - [lindex $pin_size 0] / 2.0 + $pin_extension}]
+ }
+
+ if {$i == 0} {
+ set location $loc_x
+ lappend location $offset_y
+ } else {
+ set loc_y [expr { [lindex $prev_pin_size 1] / 2.0 + [lindex $pin_size 1] / 2.0 + + [lindex $spacing_list $i] + [lindex $location 1]}]
+ set location $loc_x
+ lappend location $loc_y
+ }
+
+ place_pin -pin_name $pin -layer met3 -location $location -pin_size $pin_size
+ set i [expr {$i + 1}]
+ set prev_pin_size $pin_size
+}
+
+## West Pins
+set west_pins {
+ io_analog[10]
+ vccd2 vccd2_1
+ vssa2 vssa2_1
+ gpio_analog[7] gpio_noesd[7] io_in_3v3[14] io_in[14] io_out[14] io_oeb[14]
+ gpio_analog[8] gpio_noesd[8] io_in_3v3[15] io_in[15] io_out[15] io_oeb[15]
+ gpio_analog[9] gpio_noesd[9] io_in_3v3[16] io_in[16] io_out[16] io_oeb[16]
+ gpio_analog[10] gpio_noesd[10] io_in_3v3[17] io_in[17] io_out[17] io_oeb[17]
+ gpio_analog[11] gpio_noesd[11] io_in_3v3[18] io_in[18] io_out[18] io_oeb[18]
+ gpio_analog[12] gpio_noesd[12] io_in_3v3[19] io_in[19] io_out[19] io_oeb[19]
+ gpio_analog[13] gpio_noesd[13] io_in_3v3[20] io_in[20] io_out[20] io_oeb[20]
+ vdda2_1 vdda2
+ vssd2 vssd2_1
+ gpio_analog[14] gpio_noesd[14] io_in_3v3[21] io_in[21] io_out[21] io_oeb[21]
+ gpio_analog[15] gpio_noesd[15] io_in_3v3[22] io_in[22] io_out[22] io_oeb[22]
+ gpio_analog[16] gpio_noesd[16] io_in_3v3[23] io_in[23] io_out[23] io_oeb[23]
+ gpio_analog[17] gpio_noesd[17] io_in_3v3[24] io_in[24] io_out[24] io_oeb[24]
+ io_in_3v3[25] io_in[25] io_out[25] io_oeb[25]
+ io_in_3v3[26] io_in[26] io_out[26] io_oeb[26]
+}
+
+set min_distance 5.35
+
+set spacing_list " 0
+ $min_distance $min_distance $min_distance $min_distance
+ $min_distance $min_distance $min_distance $min_distance
+ $min_distance $min_distance $min_distance $min_distance $min_distance 77
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 190
+ 26 136
+ 26 134
+ $min_distance $min_distance $min_distance $min_distance $min_distance 185
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 186
+ $min_distance $min_distance $min_distance $min_distance $min_distance 189
+ 26 348
+ 26 158"
+
+set offset_y 8
+set size $pin_height
+lappend size $pin_width
+
+
+set i 0
+foreach pin [lreverse $west_pins] {
+
+ if {[string match "io_analog*" $pin]} {
+ set pin_size [lreverse $analog_pin_size]
+ set loc_x [expr {[ lindex $pin_size 0] / 2.0 }]
+ } elseif { $pin in $power_pins } {
+ set pin_size [lreverse $power_pin_size]
+ set loc_x [expr {[ lindex $pin_size 0] / 2.0 }]
+ } else {
+ set pin_size [lreverse $regular_pin_size]
+ set loc_x [expr {[lindex $pin_size 0] / 2.0 - $pin_extension}]
+ }
+
+ if {$i == 0} {
+ set location $loc_x
+ lappend location $offset_y
+ } else {
+ set loc_y [expr { [lindex $prev_pin_size 1] / 2.0 + [lindex $pin_size 1] / 2.0 + [lindex $spacing_list $i] + [lindex $location 1]}]
+ set location $loc_x
+ lappend location $loc_y
+ }
+
+ place_pin -pin_name $pin -layer met3 -location $location -pin_size $pin_size
+ set i [expr {$i + 1}]
+ set prev_pin_size $pin_size
+}
+
+
+## South Pins
+set south_pins { wb_clk_i wb_rst_i wbs_ack_o wbs_cyc_i wbs_stb_i wbs_we_i wbs_adr_i[0] wbs_dat_i[0] wbs_dat_o[0] wbs_sel_i[0] wbs_adr_i[1] wbs_dat_i[1] wbs_dat_o[1] wbs_sel_i[1] wbs_adr_i[2] wbs_dat_i[2] wbs_dat_o[2] wbs_sel_i[2] wbs_adr_i[3] wbs_dat_i[3] wbs_dat_o[3] wbs_sel_i[3] wbs_adr_i[4] wbs_dat_i[4] wbs_dat_o[4] wbs_adr_i[5] wbs_dat_i[5] wbs_dat_o[5] wbs_adr_i[6] wbs_dat_i[6] wbs_dat_o[6] wbs_adr_i[7] wbs_dat_i[7] wbs_dat_o[7] wbs_adr_i[8] wbs_dat_i[8] wbs_dat_o[8] wbs_adr_i[9] wbs_dat_i[9] wbs_dat_o[9] wbs_adr_i[10] wbs_dat_i[10] wbs_dat_o[10] wbs_adr_i[11] wbs_dat_i[11] wbs_dat_o[11] wbs_adr_i[12] wbs_dat_i[12] wbs_dat_o[12] wbs_adr_i[13] wbs_dat_i[13] wbs_dat_o[13] wbs_adr_i[14] wbs_dat_i[14] wbs_dat_o[14] wbs_adr_i[15] wbs_dat_i[15] wbs_dat_o[15] wbs_adr_i[16] wbs_dat_i[16] wbs_dat_o[16] wbs_adr_i[17] wbs_dat_i[17] wbs_dat_o[17] wbs_adr_i[18] wbs_dat_i[18] wbs_dat_o[18] wbs_adr_i[19] wbs_dat_i[19] wbs_dat_o[19] wbs_adr_i[20] wbs_dat_i[20] wbs_dat_o[20] wbs_adr_i[21] wbs_dat_i[21] wbs_dat_o[21] wbs_adr_i[22] wbs_dat_i[22] wbs_dat_o[22] wbs_adr_i[23] wbs_dat_i[23] wbs_dat_o[23] wbs_adr_i[24] wbs_dat_i[24] wbs_dat_o[24] wbs_adr_i[25] wbs_dat_i[25] wbs_dat_o[25] wbs_adr_i[26] wbs_dat_i[26] wbs_dat_o[26] wbs_adr_i[27] wbs_dat_i[27] wbs_dat_o[27] wbs_adr_i[28] wbs_dat_i[28] wbs_dat_o[28] wbs_adr_i[29] wbs_dat_i[29] wbs_dat_o[29] wbs_adr_i[30] wbs_dat_i[30] wbs_dat_o[30] wbs_adr_i[31] wbs_dat_i[31] wbs_dat_o[31] la_data_in[0] la_data_out[0] la_oenb[0] la_data_in[1] la_data_out[1] la_oenb[1] la_data_in[2] la_data_out[2] la_oenb[2] la_data_in[3] la_data_out[3] la_oenb[3] la_data_in[4] la_data_out[4] la_oenb[4] la_data_in[5] la_data_out[5] la_oenb[5] la_data_in[6] la_data_out[6] la_oenb[6] la_data_in[7] la_data_out[7] la_oenb[7] la_data_in[8] la_data_out[8] la_oenb[8] la_data_in[9] la_data_out[9] la_oenb[9] la_data_in[10] la_data_out[10] la_oenb[10] la_data_in[11] la_data_out[11] la_oenb[11] la_data_in[12] la_data_out[12] la_oenb[12] la_data_in[13] la_data_out[13] la_oenb[13] la_data_in[14] la_data_out[14] la_oenb[14] la_data_in[15] la_data_out[15] la_oenb[15] la_data_in[16] la_data_out[16] la_oenb[16] la_data_in[17] la_data_out[17] la_oenb[17] la_data_in[18] la_data_out[18] la_oenb[18] la_data_in[19] la_data_out[19] la_oenb[19] la_data_in[20] la_data_out[20] la_oenb[20] la_data_in[21] la_data_out[21] la_oenb[21] la_data_in[22] la_data_out[22] la_oenb[22] la_data_in[23] la_data_out[23] la_oenb[23] la_data_in[24] la_data_out[24] la_oenb[24] la_data_in[25] la_data_out[25] la_oenb[25] la_data_in[26] la_data_out[26] la_oenb[26] la_data_in[27] la_data_out[27] la_oenb[27] la_data_in[28] la_data_out[28] la_oenb[28] la_data_in[29] la_data_out[29] la_oenb[29] la_data_in[30] la_data_out[30] la_oenb[30] la_data_in[31] la_data_out[31] la_oenb[31] la_data_in[32] la_data_out[32] la_oenb[32] la_data_in[33] la_data_out[33] la_oenb[33] la_data_in[34] la_data_out[34] la_oenb[34] la_data_in[35] la_data_out[35] la_oenb[35] la_data_in[36] la_data_out[36] la_oenb[36] la_data_in[37] la_data_out[37] la_oenb[37] la_data_in[38] la_data_out[38] la_oenb[38] la_data_in[39] la_data_out[39] la_oenb[39] la_data_in[40] la_data_out[40] la_oenb[40] la_data_in[41] la_data_out[41] la_oenb[41] la_data_in[42] la_data_out[42] la_oenb[42] la_data_in[43] la_data_out[43] la_oenb[43] la_data_in[44] la_data_out[44] la_oenb[44] la_data_in[45] la_data_out[45] la_oenb[45] la_data_in[46] la_data_out[46] la_oenb[46] la_data_in[47] la_data_out[47] la_oenb[47] la_data_in[48] la_data_out[48] la_oenb[48] la_data_in[49] la_data_out[49] la_oenb[49] la_data_in[50] la_data_out[50] la_oenb[50] la_data_in[51] la_data_out[51] la_oenb[51] la_data_in[52] la_data_out[52] la_oenb[52] la_data_in[53] la_data_out[53] la_oenb[53] la_data_in[54] la_data_out[54] la_oenb[54] la_data_in[55] la_data_out[55] la_oenb[55] la_data_in[56] la_data_out[56] la_oenb[56] la_data_in[57] la_data_out[57] la_oenb[57] la_data_in[58] la_data_out[58] la_oenb[58] la_data_in[59] la_data_out[59] la_oenb[59] la_data_in[60] la_data_out[60] la_oenb[60] la_data_in[61] la_data_out[61] la_oenb[61] la_data_in[62] la_data_out[62] la_oenb[62] la_data_in[63] la_data_out[63] la_oenb[63] la_data_in[64] la_data_out[64] la_oenb[64] la_data_in[65] la_data_out[65] la_oenb[65] la_data_in[66] la_data_out[66] la_oenb[66] la_data_in[67] la_data_out[67] la_oenb[67] la_data_in[68] la_data_out[68] la_oenb[68] la_data_in[69] la_data_out[69] la_oenb[69] la_data_in[70] la_data_out[70] la_oenb[70] la_data_in[71] la_data_out[71] la_oenb[71] la_data_in[72] la_data_out[72] la_oenb[72] la_data_in[73] la_data_out[73] la_oenb[73] la_data_in[74] la_data_out[74] la_oenb[74] la_data_in[75] la_data_out[75] la_oenb[75] la_data_in[76] la_data_out[76] la_oenb[76] la_data_in[77] la_data_out[77] la_oenb[77] la_data_in[78] la_data_out[78] la_oenb[78] la_data_in[79] la_data_out[79] la_oenb[79] la_data_in[80] la_data_out[80] la_oenb[80] la_data_in[81] la_data_out[81] la_oenb[81] la_data_in[82] la_data_out[82] la_oenb[82] la_data_in[83] la_data_out[83] la_oenb[83] la_data_in[84] la_data_out[84] la_oenb[84] la_data_in[85] la_data_out[85] la_oenb[85] la_data_in[86] la_data_out[86] la_oenb[86] la_data_in[87] la_data_out[87] la_oenb[87] la_data_in[88] la_data_out[88] la_oenb[88] la_data_in[89] la_data_out[89] la_oenb[89] la_data_in[90] la_data_out[90] la_oenb[90] la_data_in[91] la_data_out[91] la_oenb[91] la_data_in[92] la_data_out[92] la_oenb[92] la_data_in[93] la_data_out[93] la_oenb[93] la_data_in[94] la_data_out[94] la_oenb[94] la_data_in[95] la_data_out[95] la_oenb[95] la_data_in[96] la_data_out[96] la_oenb[96] la_data_in[97] la_data_out[97] la_oenb[97] la_data_in[98] la_data_out[98] la_oenb[98] la_data_in[99] la_data_out[99] la_oenb[99] la_data_in[100] la_data_out[100] la_oenb[100] la_data_in[101] la_data_out[101] la_oenb[101] la_data_in[102] la_data_out[102] la_oenb[102] la_data_in[103] la_data_out[103] la_oenb[103] la_data_in[104] la_data_out[104] la_oenb[104] la_data_in[105] la_data_out[105] la_oenb[105] la_data_in[106] la_data_out[106] la_oenb[106] la_data_in[107] la_data_out[107] la_oenb[107] la_data_in[108] la_data_out[108] la_oenb[108] la_data_in[109] la_data_out[109] la_oenb[109] la_data_in[110] la_data_out[110] la_oenb[110] la_data_in[111] la_data_out[111] la_oenb[111] la_data_in[112] la_data_out[112] la_oenb[112] la_data_in[113] la_data_out[113] la_oenb[113] la_data_in[114] la_data_out[114] la_oenb[114] la_data_in[115] la_data_out[115] la_oenb[115] la_data_in[116] la_data_out[116] la_oenb[116] la_data_in[117] la_data_out[117] la_oenb[117] la_data_in[118] la_data_out[118] la_oenb[118] la_data_in[119] la_data_out[119] la_oenb[119] la_data_in[120] la_data_out[120] la_oenb[120] la_data_in[121] la_data_out[121] la_oenb[121] la_data_in[122] la_data_out[122] la_oenb[122] la_data_in[123] la_data_out[123] la_oenb[123] la_data_in[124] la_data_out[124] la_oenb[124] la_data_in[125] la_data_out[125] la_oenb[125] la_data_in[126] la_data_out[126] la_oenb[126] la_data_in[127] la_data_out[127] la_oenb[127] user_clock2 user_irq[0] user_irq[1] user_irq[2] }
+set min_distance 5.35
+set offset_x 2.9
+
+set size $pin_width
+lappend size [expr {$pin_height + $pin_extension}]
+
+set i 0
+foreach pin $south_pins {
+ if {$i == 0} {
+ set location $offset_x
+ } else {
+ set location [expr {[lindex $location 0] + $min_distance + $pin_width}]
+ }
+ lappend location [expr {$pin_height / 2.0 - $pin_extension / 2.0}]
+ puts $location
+ place_pin -pin_name $pin -layer met2 -location $location -pin_size $size
+ set i [expr {$i + 1}]
+}
+
+write_def $::env(SAVE_DEF)
diff --git a/caravel/openlane/user_analog_project_wrapper_empty/pin_order.cfg b/caravel/openlane/user_analog_project_wrapper_empty/pin_order.cfg
new file mode 100644
index 0000000..cae55d2
--- /dev/null
+++ b/caravel/openlane/user_analog_project_wrapper_empty/pin_order.cfg
@@ -0,0 +1,178 @@
+#BUS_SORT
+#NR
+io_analog\[1\]
+io_analog\[2\]
+io_analog\[3\]
+io_clamp_high\[0\]
+io_clamp_low\[0\]
+io_analog\[4\]
+io_clamp_high\[1\]
+io_clamp_low\[1\]
+io_analog\[5\]
+io_clamp_high\[2\]
+io_clamp_low\[2\]
+io_analog\[6\]
+io_analog\[7\]
+io_analog\[8\]
+io_analog\[9\]
+
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in_3v3\[0\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in_3v3\[1\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in_3v3\[2\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in_3v3\[3\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in_3v3\[4\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in_3v3\[5\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in_3v3\[6\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+gpio_analog\[0\]
+gpio_noesd\[0\]
+io_in_3v3\[7\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+gpio_analog\[1\]
+gpio_noesd\[1\]
+io_in_3v3\[8\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+gpio_analog\[2\]
+gpio_noesd\[2\]
+io_in_3v3\[9\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+gpio_analog\[3\]
+gpio_noesd\[3\]
+io_in_3v3\[10\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+gpio_analog\[4\]
+gpio_noesd\[4\]
+io_in_3v3\[11\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+gpio_analog\[5\]
+gpio_noesd\[5\]
+io_in_3v3\[12\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+gpio_analog\[6\]
+gpio_noesd\[6\]
+io_in_3v3\[13\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+
+io_analog\[0\]
+
+#WR
+io_analog\[10\]
+gpio_analog\[7\]
+gpio_noesd\[7\]
+gpio_analog\[8\]
+gpio_noesd\[8\]
+io_in_3v3\[14\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+gpio_analog\[9\]
+gpio_noesd\[9\]
+io_in_3v3\[15\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+gpio_analog\[10\]
+gpio_noesd\[10\]
+io_in_3v3\[16\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+gpio_analog\[11\]
+gpio_noesd\[11\]
+io_in_3v3\[17\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+gpio_analog\[12\]
+gpio_noesd\[12\]
+io_in_3v3\[18\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+gpio_analog\[13\]
+gpio_noesd\[13\]
+io_in_3v3\[19\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+gpio_analog\[14\]
+gpio_noesd\[14\]
+io_in_3v3\[20\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+gpio_analog\[15\]
+gpio_noesd\[15\]
+io_in_3v3\[21\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+gpio_analog\[16\]
+gpio_noesd\[16\]
+io_in_3v3\[22\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+gpio_analog\[17\]
+gpio_noesd\[17\]
+io_in_3v3\[23\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+gpio_analog\[18\]
+gpio_noesd\[18\]
+io_in_3v3\[24\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+io_in_3v3\[25\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in_3v3\[26\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
diff --git a/caravel/openlane/user_project_wrapper_empty/config.tcl b/caravel/openlane/user_project_wrapper_empty/config.tcl
new file mode 100644
index 0000000..c6ad019
--- /dev/null
+++ b/caravel/openlane/user_project_wrapper_empty/config.tcl
@@ -0,0 +1,43 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+source $script_dir/fixed_wrapper_cfgs.tcl
+source $script_dir/default_wrapper_cfgs.tcl
+
+set ::env(DESIGN_NAME) user_project_wrapper
+
+set ::env(FP_PDN_CHECK_NODES) 0
+set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
+ met2 0 0 $::env(DIE_AREA),\
+ met3 0 0 $::env(DIE_AREA),\
+ met4 0 0 $::env(DIE_AREA),\
+ met5 0 0 $::env(DIE_AREA)"
+
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "mprj.clk"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+set ::env(MAGIC_WRITE_FULL_LEF) 0
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/__user_project_wrapper.v"
diff --git a/caravel/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl b/caravel/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
new file mode 100644
index 0000000..4a4f8a2
--- /dev/null
+++ b/caravel/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
@@ -0,0 +1,24 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
\ No newline at end of file
diff --git a/caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl b/caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
new file mode 100644
index 0000000..3f078eb
--- /dev/null
+++ b/caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+set script_dir [file dirname [file normalize [info script]]]
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+# Pin Configurations. DON'T TOUCH
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_VOFFSET) 14
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
diff --git a/caravel/openlane/user_project_wrapper_empty/interactive.tcl b/caravel/openlane/user_project_wrapper_empty/interactive.tcl
new file mode 100755
index 0000000..b9074e5
--- /dev/null
+++ b/caravel/openlane/user_project_wrapper_empty/interactive.tcl
@@ -0,0 +1,69 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag user_project_wrapper -overwrite
+set save_path $script_dir/../..
+
+verilog_elaborate
+
+init_floorplan
+
+# making it "empty"
+remove_nets -input $::env(CURRENT_DEF)
+remove_components -input $::env(CURRENT_DEF)
+
+place_io_ol
+
+apply_route_obs
+
+run_power_grid_generation
+
+# pdngen-related hack
+# remove .extra\d+ "pins" so that magic
+# generates shapes for each stripes without the ".extra" postfix
+# until OpenDB can understand this syntax...
+exec sed \
+ -i -E {/^PINS/,/^END PINS/ s/\.extra[[:digit:]]+(.*USE (GROUND|POWER))/\1/g} \
+ $::env(CURRENT_DEF)
+
+
+run_magic
+
+save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(CURRENT_DEF) \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -save_path $save_path \
+ -tag $::env(RUN_TAG)
+
+# produce "obstructed" LEF to be used for routing
+set gap 0.4
+set llx [expr [lindex $::env(DIE_AREA) 0]-$gap]
+set lly [expr [lindex $::env(DIE_AREA) 1]-$gap]
+set urx [expr [lindex $::env(DIE_AREA) 2]+$gap]
+set ury [expr [lindex $::env(DIE_AREA) 3]+$gap]
+
+exec python3 $::env(OPENLANE_ROOT)/scripts/rectify.py $llx $lly $urx $ury \
+ < $::env(magic_result_file_tag).lef \
+ | python3 $::env(OPENLANE_ROOT)/scripts/obs.py -42.88 -37.53 2962.50 3557.21 met4,met5 \
+ | python3 $::env(OPENLANE_ROOT)/scripts/obs.py {*}$::env(DIE_AREA) li1,met1,met2,met3 \
+ > $::env(magic_result_file_tag).obstructed.lef
+file copy -force $::env(magic_result_file_tag).obstructed.lef $save_path/lef
+
+generate_final_summary_report
\ No newline at end of file
diff --git a/caravel/openlane/user_project_wrapper_empty/pin_order.cfg b/caravel/openlane/user_project_wrapper_empty/pin_order.cfg
new file mode 100644
index 0000000..90cde69
--- /dev/null
+++ b/caravel/openlane/user_project_wrapper_empty/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/caravel/scripts/check_density.py b/caravel/scripts/check_density.py
new file mode 100755
index 0000000..25f44ba
--- /dev/null
+++ b/caravel/scripts/check_density.py
@@ -0,0 +1,616 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# check_density.py ---
+#
+# Run density checks on the final (filled) GDS.
+#
+
+import sys
+import os
+import re
+import select
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("check_density.py [<path_to_project>] [-keep]")
+ print("")
+ print("where:")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the check script.")
+ return 0
+
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 1:
+ print("Wrong number of arguments given to check_density.py.")
+ usage()
+ sys.exit(0)
+
+ if len(arguments) == 1:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ # Check for valid user path
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ user_id_value = None
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ if user_id_value:
+ project = 'caravel'
+ project_with_id = 'caravel_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ with open(magpath + '/check_density.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('crashbackups stop', file=ofile)
+ print('drc off', file=ofile)
+ print('snap internal', file=ofile)
+
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started reading GDS: $starttime"', file=ofile)
+ print('', file=ofile)
+ print('flush stdout', file=ofile)
+ print('update idletasks', file=ofile)
+
+ # Read final project from .gds
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/' + project_with_id + '.gds', file=ofile)
+ print('', file=ofile)
+
+ print('set midtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Starting density checks: $midtime"', file=ofile)
+ print('', file=ofile)
+ print('flush stdout', file=ofile)
+ print('update idletasks', file=ofile)
+
+ # Get step box dimensions (700um for size and 70um for FOM step)
+ # Use 350um for stepping on other layers.
+ print('box values 0 0 0 0', file=ofile)
+ # print('box size 700um 700um', file=ofile)
+ # print('set stepbox [box values]', file=ofile)
+ # print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ # print('set stepheight [lindex $stepbox 3]', file=ofile)
+
+ print('box size 70um 70um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepsizex [lindex $stepbox 2]', file=ofile)
+ print('set stepsizey [lindex $stepbox 3]', file=ofile)
+
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+
+ # Modify the box to be inside the seal ring area (shrink 5um)
+ print('box grow c -5um', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepsizex))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepsizey))}]', file=ofile)
+ print('box size $stepsizex $stepsizey', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ print('puts stdout "XTILES: $xtiles"', file=ofile)
+ print('puts stdout "YTILES: $ytiles"', file=ofile)
+ print('', file=ofile)
+
+ # Need to know what fraction of a full tile is the last row and column
+ print('set xfrac [expr {($xtiles * $stepsizex - $fullwidth + 0.0) / $stepsizex}]', file=ofile)
+ print('set yfrac [expr {($ytiles * $stepsizey - $fullheight + 0.0) / $stepsizey}]', file=ofile)
+ print('puts stdout "XFRAC: $xfrac"', file=ofile)
+ print('puts stdout "YFRAC: $yfrac"', file=ofile)
+
+ print('cif ostyle density', file=ofile)
+
+ # Process density at steps. For efficiency, this is done in 70x70 um
+ # areas, dumped to a file, and then aggregated into the 700x700 areas.
+
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepsizex]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepsizey]', file=ofile)
+ print(' set xhi [expr $xlo + $stepsizex]', file=ofile)
+ print(' set yhi [expr $ylo + $stepsizey]', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+
+ # Flatten this area
+ print(' flatten -dobbox -nolabels tile', file=ofile)
+ print(' load tile', file=ofile)
+ print(' select top cell', file=ofile)
+
+ # Run density check for each layer
+ print(' puts stdout "Density results for tile x=$x y=$y"', file=ofile)
+
+ print(' set fdens [cif list cover fom_all]', file=ofile)
+ print(' set pdens [cif list cover poly_all]', file=ofile)
+ print(' set ldens [cif list cover li_all]', file=ofile)
+ print(' set m1dens [cif list cover m1_all]', file=ofile)
+ print(' set m2dens [cif list cover m2_all]', file=ofile)
+ print(' set m3dens [cif list cover m3_all]', file=ofile)
+ print(' set m4dens [cif list cover m4_all]', file=ofile)
+ print(' set m5dens [cif list cover m5_all]', file=ofile)
+ print(' puts stdout "FOM: $fdens"', file=ofile)
+ print(' puts stdout "POLY: $pdens"', file=ofile)
+ print(' puts stdout "LI1: $ldens"', file=ofile)
+ print(' puts stdout "MET1: $m1dens"', file=ofile)
+ print(' puts stdout "MET2: $m2dens"', file=ofile)
+ print(' puts stdout "MET3: $m3dens"', file=ofile)
+ print(' puts stdout "MET4: $m4dens"', file=ofile)
+ print(' puts stdout "MET5: $m5dens"', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+
+ print(' load ' + project_with_id, file=ofile)
+ print(' cellname delete tile', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('', file=ofile)
+
+
+ myenv = os.environ.copy()
+ # Real views are necessary for the DRC checks
+ myenv['MAGTYPE'] = 'mag'
+
+ print('Running density checks on file ' + project_with_id + '.gds', flush=True)
+
+ mproc = subprocess.Popen(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/check_density.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+
+ # Use signal to poll the process and generate any output as it arrives
+
+ dlines = []
+
+ while mproc:
+ status = mproc.poll()
+ if status != None:
+ try:
+ output = mproc.communicate(timeout=1)
+ except ValueError:
+ print('Magic forced stop, status ' + str(status))
+ sys.exit(1)
+ else:
+ outlines = output[0]
+ errlines = output[1]
+ for line in outlines.splitlines():
+ dlines.append(line)
+ print(line)
+ for line in errlines.splitlines():
+ print(line)
+ print('Magic exited with status ' + str(status))
+ if int(status) != 0:
+ sys.exit(int(status))
+ else:
+ break
+ else:
+ n = 0
+ while True:
+ n += 1
+ if n > 100:
+ n = 0
+ status = mproc.poll()
+ if status != None:
+ break
+ sresult = select.select([mproc.stdout, mproc.stderr], [], [], 0.5)[0]
+ if mproc.stdout in sresult:
+ outstring = mproc.stdout.readline().strip()
+ dlines.append(outstring)
+ print(outstring)
+ elif mproc.stderr in sresult:
+ outstring = mproc.stderr.readline().strip()
+ print(outstring)
+ else:
+ break
+
+ fomfill = []
+ polyfill = []
+ lifill = []
+ met1fill = []
+ met2fill = []
+ met3fill = []
+ met4fill = []
+ met5fill = []
+ xtiles = 0
+ ytiles = 0
+ xfrac = 0.0
+ yfrac = 0.0
+
+ for line in dlines:
+ dpair = line.split(':')
+ if len(dpair) == 2:
+ layer = dpair[0]
+ try:
+ density = float(dpair[1].strip())
+ except:
+ continue
+ if layer == 'FOM':
+ fomfill.append(density)
+ elif layer == 'POLY':
+ polyfill.append(density)
+ elif layer == 'LI1':
+ lifill.append(density)
+ elif layer == 'MET1':
+ met1fill.append(density)
+ elif layer == 'MET2':
+ met2fill.append(density)
+ elif layer == 'MET3':
+ met3fill.append(density)
+ elif layer == 'MET4':
+ met4fill.append(density)
+ elif layer == 'MET5':
+ met5fill.append(density)
+ elif layer == 'XTILES':
+ xtiles = int(dpair[1].strip())
+ elif layer == 'YTILES':
+ ytiles = int(dpair[1].strip())
+ elif layer == 'XFRAC':
+ xfrac = float(dpair[1].strip())
+ elif layer == 'YFRAC':
+ yfrac = float(dpair[1].strip())
+
+ if ytiles == 0 or xtiles == 0:
+ print('Failed to read XTILES or YTILES from output.')
+ sys.exit(1)
+
+ total_tiles = (ytiles - 9) * (xtiles - 9)
+
+ print('')
+ print('Density results (total tiles = ' + str(total_tiles) + '):')
+
+ # For FOM, step at 70um intervals (same as 70um check area)
+ fomstep = 1
+
+ # For poly, step only at 700um intervals (10 * 70um check area)
+ polystep = 10
+
+ # For all metals, step only at 350um intervals (5 * 70um check area)
+ metalstep = 5
+
+ # Full areas are 10 x 10 tiles = 100. But the right and top sides are
+ # not full tiles, so the full area must be prorated.
+
+ sideadjust = 90.0 + (10.0 * xfrac)
+ topadjust = 90.0 + (10.0 * yfrac)
+ corneradjust = 81.0 + (9.0 * xfrac) + (9.0 * yfrac) + (xfrac * yfrac)
+
+ print('')
+ print('FOM Density:')
+ for y in range(0, ytiles - 9, fomstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, fomstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ fomaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ fomaccum += sum(fomfill[base : base + 10])
+
+ fomaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(fomaccum))
+ if fomaccum < 0.33:
+ print('***Error: FOM Density < 33%')
+ elif fomaccum > 0.57:
+ print('***Error: FOM Density > 57%')
+
+ print('')
+ print('POLY Density:')
+ for y in range(0, ytiles - 9, polystep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, polystep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ polyaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ polyaccum += sum(polyfill[base : base + 10])
+
+ polyaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(polyaccum))
+
+ print('')
+ print('LI Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ liaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ liaccum += sum(lifill[base : base + 10])
+
+ liaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(liaccum))
+ if liaccum < 0.35:
+ print('***Error: LI Density < 35%')
+ elif liaccum > 0.60:
+ print('***Error: LI Density > 60%')
+
+ print('')
+ print('MET1 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met1accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met1accum += sum(met1fill[base : base + 10])
+
+ met1accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met1accum))
+ if met1accum < 0.35:
+ print('***Error: MET1 Density < 35%')
+ elif met1accum > 0.60:
+ print('***Error: MET1 Density > 60%')
+
+ print('')
+ print('MET2 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met2accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met2accum += sum(met2fill[base : base + 10])
+
+ met2accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met2accum))
+ if met2accum < 0.35:
+ print('***Error: MET2 Density < 35%')
+ elif met2accum > 0.60:
+ print('***Error: MET2 Density > 60%')
+
+ print('')
+ print('MET3 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met3accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met3accum += sum(met3fill[base : base + 10])
+
+ met3accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met3accum))
+ if met3accum < 0.35:
+ print('***Error: MET3 Density < 35%')
+ elif met3accum > 0.60:
+ print('***Error: MET3 Density > 60%')
+
+ print('')
+ print('MET4 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met4accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met4accum += sum(met4fill[base : base + 10])
+
+ met4accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met4accum))
+ if met4accum < 0.35:
+ print('***Error: MET4 Density < 35%')
+ elif met4accum > 0.60:
+ print('***Error: MET4 Density > 60%')
+
+ print('')
+ print('MET5 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met5accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met5accum += sum(met5fill[base : base + 10])
+
+ met5accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met5accum))
+ if met5accum < 0.45:
+ print('***Error: MET5 Density < 45%')
+ elif met5accum > 0.76:
+ print('***Error: MET5 Density > 76%')
+
+ print('')
+ print('Whole-chip density results:')
+
+ atotal = ((xtiles - 1.0) * (ytiles - 1.0)) + ((ytiles - 1.0) * xfrac) + ((xtiles - 1.0) * yfrac) + (xfrac * yfrac)
+
+ fomaccum = sum(fomfill) / atotal
+ print('')
+ print('FOM Density: ' + str(fomaccum))
+ if fomaccum < 0.33:
+ print('***Error: FOM Density < 33%')
+ elif fomaccum > 0.57:
+ print('***Error: FOM Density > 57%')
+
+ polyaccum = sum(polyfill) / atotal
+ print('')
+ print('POLY Density: ' + str(polyaccum))
+
+ liaccum = sum(lifill) / atotal
+ print('')
+ print('LI Density: ' + str(liaccum))
+ if liaccum < 0.35:
+ print('***Error: LI Density < 35%')
+ elif liaccum > 0.60:
+ print('***Error: LI Density > 60%')
+
+ met1accum = sum(met1fill) / atotal
+ print('')
+ print('MET1 Density: ' + str(met1accum))
+ if met1accum < 0.35:
+ print('***Error: MET1 Density < 35%')
+ elif met1accum > 0.60:
+ print('***Error: MET1 Density > 60%')
+
+ met2accum = sum(met2fill) / atotal
+ print('')
+ print('MET2 Density: ' + str(met2accum))
+ if met2accum < 0.35:
+ print('***Error: MET2 Density < 35%')
+ elif met2accum > 0.60:
+ print('***Error: MET2 Density > 60%')
+
+ met3accum = sum(met3fill) / atotal
+ print('')
+ print('MET3 Density: ' + str(met3accum))
+ if met3accum < 0.35:
+ print('***Error: MET3 Density < 35%')
+ elif met3accum > 0.60:
+ print('***Error: MET3 Density > 60%')
+
+ met4accum = sum(met4fill) / atotal
+ print('')
+ print('MET4 Density: ' + str(met4accum))
+ if met4accum < 0.35:
+ print('***Error: MET4 Density < 35%')
+ elif met4accum > 0.60:
+ print('***Error: MET4 Density > 60%')
+
+ met5accum = sum(met5fill) / atotal
+ print('')
+ print('MET5 Density: ' + str(met5accum))
+ if met5accum < 0.45:
+ print('***Error: MET5 Density < 45%')
+ elif met5accum > 0.76:
+ print('***Error: MET5 Density > 76%')
+
+ if not keepmode:
+ if os.path.isfile(magpath + '/check_density.tcl'):
+ os.remove(magpath + '/check_density.tcl')
+
+ print('')
+ print('Done!')
+ sys.exit(0)
diff --git a/caravel/scripts/compositor.py b/caravel/scripts/compositor.py
new file mode 100755
index 0000000..efa0b4e
--- /dev/null
+++ b/caravel/scripts/compositor.py
@@ -0,0 +1,253 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# compositor.py ---
+#
+# Compose the final GDS for caravel from the caravel GDS, seal ring
+# GDS, and fill GDS.
+#
+
+import sys
+import os
+import re
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("compositor.py <user_id_value> <project> <path_to_project> <path_to_mag_dir> <path_to_gds_dir [-keep]")
+ print("")
+ print("where:")
+ print(" <user_id_value> is a character string of eight hex digits, and")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print(" <path_to_mag_dir> is the path to the mag directory.")
+ print(" <path_to_gds_dir> is the path to the gds directory.")
+ print("")
+ print(" If <user_id_value> is not given, then it must exist in the info.yaml file.")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If <path_to_mag_dir> is not given, then it is assumed to be the <path_to_project>/tmp.")
+ print(" If <path_to_gds_dir> is not given, then it is assumed to be the <path_to_project>/gds.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ return 0
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) != 5:
+ print("Wrong number of arguments given to compositor.py.")
+ usage()
+ sys.exit(0)
+
+ user_id_value = arguments[0]
+ project = arguments[1]
+ user_project_path = arguments[2]
+ mag_dir_path = arguments[3]
+ gds_dir_path = arguments[4]
+
+ # if len(arguments) > 0:
+ # user_id_value = arguments[0]
+
+ # Convert to binary
+ try:
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+ except:
+ print("User ID not recognized")
+ usage()
+ sys.exit(1)
+
+ # if len(arguments) == 2 and user_project_path == None:
+ # user_project_path = arguments[1]
+ # mag_dir_path = user_project_path + "/mag"
+ # gds_dir_path = "../gds"
+ # if len(arguments) == 3 and user_project_path == None:
+ # user_project_path = arguments[1]
+ # mag_dir_path = arguments[2]
+ # gds_dir_path = "../gds"
+ # if len(arguments) == 4:
+ # user_project_path = arguments[1]
+ # mag_dir_path = arguments[2]
+ # gds_dir_path = arguments[3]
+ # elif len(arguments) == 3 and user_project_path != None:
+ # mag_dir_path = arguments[1]
+ # gds_dir_path = arguments[2]
+ # else:
+ # user_project_path = os.getcwd()
+ # mag_dir_path = user_project_path + "/mag"
+ # gds_dir_path = "../gds"
+
+ # Check for valid user path
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid mag path
+
+ if not os.path.isdir(mag_dir_path):
+ print('Error: Mag directory path "' + mag_dir_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid gds path
+
+ if not os.path.isdir(gds_dir_path):
+ print('Error: GDS directory path "' + gds_dir_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ # if not user_id_value:
+ # if os.path.isfile(user_project_path + '/info.yaml'):
+ # with open(user_project_path + '/info.yaml', 'r') as ifile:
+ # infolines = ifile.read().splitlines()
+ # for line in infolines:
+ # kvpair = line.split(':')
+ # if len(kvpair) == 2:
+ # key = kvpair[0].strip()
+ # value = kvpair[1].strip()
+ # if key == 'project_id':
+ # user_id_value = value.strip('"\'')
+ # break
+
+ if user_id_value:
+ # project = 'caravel'
+ # project_with_id = project + '_' + user_id_value
+ project_with_id = 'caravel_' + user_id_value
+ user_id_decimal = str(int(user_id_value, 16))
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+
+ magpath = mag_dir_path
+ rcfile = magpath + '/.magicrc'
+
+ gdspath = gds_dir_path
+
+ # The compositor script will create <project_with_id>.mag, but is uses
+ # "load", so the file must not already exist.
+
+ if os.path.isfile(user_project_path + '/mag/' + project_with_id + '.mag'):
+ print('Error: File ' + project_with_id + '.mag exists already! Exiting. . .')
+ sys.exit(1)
+
+ with open(user_project_path + '/mag/compose_final.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ # Set the random seed from the project ID
+ print('random seed ' + user_id_decimal, file=ofile)
+
+ # Read project from .mag but set GDS properties so that it points
+ # to the GDS file created by "make ship".
+ print('load ' + project + ' -dereference', file=ofile)
+ print('property GDS_FILE ' + gdspath + '/' + project + '.gds', file=ofile)
+ print('property GDS_START 0', file=ofile)
+ print('select top cell', file=ofile)
+ print('set bbox [box values]', file=ofile)
+
+ # Ceate a cell to represent the generated fill. There are
+ # no magic layers corresponding to the fill shape data, and
+ # it's gigabytes anyway, so we don't want to deal with any
+ # actual data. So it's just a placeholder.
+
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values {*}$bbox', file=ofile)
+ print('paint comment', file=ofile)
+ print('property GDS_FILE ' + gdspath + '/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('property GDS_START 0', file=ofile)
+ print('property FIXED_BBOX "$bbox"', file=ofile)
+
+ # Create a new project top level and place the fill cell.
+ print('load ' + project_with_id + ' -quiet', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box position 6um 6um', file=ofile)
+ print('getcell ' + project + ' child 0 0', file=ofile)
+ print('getcell ' + project_with_id + '_fill_pattern child 0 0', file=ofile)
+
+ # Move existing origin to (6um, 6um) for seal ring placement
+ # print('move origin -6um -6um', file=ofile)
+
+ # Read in abstract view of seal ring
+ print('box position 0 0', file=ofile)
+ print('getcell advSeal_6um_gen', file=ofile)
+
+ # Write out completed project as "caravel_" + the user ID
+ # print('save ' + user_project_path + '/mag/' + project_with_id, file=ofile)
+
+ # Generate final GDS
+ print('puts stdout "Writing final GDS. . . "', file=ofile)
+ print('flush stdout', file=ofile)
+ print('gds undefined allow', file=ofile)
+ print('cif *hier write disable', file=ofile)
+ print('gds write ' + gdspath + '/' + project_with_id + '.gds', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ myenv = os.environ.copy()
+ # Abstract views are appropriate for final composition
+ myenv['MAGTYPE'] = 'maglef'
+
+ print('Building final GDS file ' + project_with_id + '.gds', flush=True)
+
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, user_project_path + '/mag/compose_final.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ # NOTE: Until there is a "load -quiet" option in magic, loading
+ # a new cell generates an error. This code ignores the error.
+ newlines = []
+ for line in mproc.stderr.splitlines():
+ if line.endswith("_fill_pattern.mag couldn't be read"):
+ continue
+ if line.startswith("No such file or directory"):
+ continue
+ else:
+ newlines.append(line)
+
+ if len(newlines) > 0:
+ print('Error message output from magic:')
+ for line in newlines:
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ os.remove(user_project_path + '/mag/compose_final.tcl')
+
+ print('Done!')
+ exit(0)
diff --git a/caravel/scripts/count_lvs.py b/caravel/scripts/count_lvs.py
new file mode 100644
index 0000000..2362e01
--- /dev/null
+++ b/caravel/scripts/count_lvs.py
@@ -0,0 +1,121 @@
+#!ENV_PATH python3
+#
+#---------------------------------------------------------
+# LVS failure check
+#
+# This is a Python script that parses the comp.json
+# output from netgen and reports on the number of
+# errors in the top-level netlist.
+#
+#---------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Pulled from qflow GUI as standalone script Aug 20, 2018
+#---------------------------------------------------------
+
+import os
+import re
+import sys
+import json
+import argparse
+
+def count_LVS_failures(filename):
+ with open(filename, 'r') as cfile:
+ lvsdata = json.load(cfile)
+
+ # Count errors in the JSON file
+ failures = 0
+ devfail = 0
+ netfail = 0
+ pinfail = 0
+ propfail = 0
+ netdiff = 0
+ devdiff = 0
+ ncells = len(lvsdata)
+ for c in range(0, ncells):
+ cellrec = lvsdata[c]
+
+ if c == ncells - 1:
+ topcell = True
+ else:
+ topcell = False
+
+ # Most errors must only be counted for the top cell, because individual
+ # failing cells are flattened and the matching attempted again on the
+ # flattened netlist.
+
+ if topcell:
+ if 'devices' in cellrec:
+ devices = cellrec['devices']
+ devlist = [val for pair in zip(devices[0], devices[1]) for val in pair]
+ devpair = list(devlist[p:p + 2] for p in range(0, len(devlist), 2))
+ for dev in devpair:
+ c1dev = dev[0]
+ c2dev = dev[1]
+ diffdevs = abs(c1dev[1] - c2dev[1])
+ failures += diffdevs
+ devdiff += diffdevs
+
+ if 'nets' in cellrec:
+ nets = cellrec['nets']
+ diffnets = abs(nets[0] - nets[1])
+ failures += diffnets
+ netdiff += diffnets
+
+ if 'badnets' in cellrec:
+ badnets = cellrec['badnets']
+ failures += len(badnets)
+ netfail += len(badnets)
+
+ if 'badelements' in cellrec:
+ badelements = cellrec['badelements']
+ failures += len(badelements)
+ devfail += len(badelements)
+
+ if 'pins' in cellrec:
+ pins = cellrec['pins']
+ pinlist = [val for pair in zip(pins[0], pins[1]) for val in pair]
+ pinpair = list(pinlist[p:p + 2] for p in range(0, len(pinlist), 2))
+ for pin in pinpair:
+ # Avoid flagging global vs. local names, e.g., "gnd" vs. "gnd!,"
+ # and ignore case when comparing pins.
+ pin0 = re.sub('!$', '', pin[0].lower())
+ pin1 = re.sub('!$', '', pin[1].lower())
+ if pin0 != pin1:
+ # The text "(no pin)" indicates a missing pin that can be
+ # ignored because the pin in the other netlist is a no-connect
+ if pin0 != '(no pin)' and pin1 != '(no pin)':
+ failures += 1
+ pinfail += 1
+
+ # Property errors must be counted for every cell
+ if 'properties' in cellrec:
+ properties = cellrec['properties']
+ failures += len(properties)
+ propfail += len(properties)
+
+ return [failures, netfail, devfail, pinfail, propfail, netdiff, devdiff]
+
+if __name__ == '__main__':
+
+ parser = argparse.ArgumentParser(description='Parses netgen lvs')
+ parser.add_argument('--file', '-f', required=True)
+ args = parser.parse_args()
+ failures = count_LVS_failures(args.file)
+
+ total = failures[0]
+ if total > 0:
+ failed = True
+ print('LVS reports:')
+ print(' net count difference = ' + str(failures[5]))
+ print(' device count difference = ' + str(failures[6]))
+ print(' unmatched nets = ' + str(failures[1]))
+ print(' unmatched devices = ' + str(failures[2]))
+ print(' unmatched pins = ' + str(failures[3]))
+ print(' property failures = ' + str(failures[4]))
+ else:
+ print('LVS reports no net, device, pin, or property mismatches.')
+
+ print('')
+ print('Total errors = ' + str(total))
+
\ No newline at end of file
diff --git a/caravel/scripts/create-caravel-diagram.py b/caravel/scripts/create-caravel-diagram.py
new file mode 100644
index 0000000..bfb4e3c
--- /dev/null
+++ b/caravel/scripts/create-caravel-diagram.py
@@ -0,0 +1,126 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+import sys
+import os
+import subprocess
+from pathlib import Path
+import argparse
+from tempfile import mkstemp
+import re
+
+
+def remove_inouts(jsonpath, replacewith='input'):
+ """Replaces inouts with either input or output statements.
+
+ Netlistsvg does not parse inout ports as for now, so they need to be
+ replaced with either input or output to produce a diagram.
+
+ Parameters
+ ----------
+ jsonpath : str
+ Path to JSON file to fix
+ replacewith : str
+ The string to replace 'inout', can be 'input' or 'output'
+ """
+ assert replacewith in ['input', 'output']
+ with open(jsonpath, 'r') as withinouts:
+ lines = withinouts.readlines()
+ with open(jsonpath, 'w') as withoutinouts:
+ for line in lines:
+ withoutinouts.write(re.sub('inout', replacewith, line))
+
+
+def main(argv):
+ parser = argparse.ArgumentParser(argv[0])
+ parser.add_argument(
+ 'verilog_rtl_dir',
+ help="Path to the project's verilog/rtl directory",
+ type=Path)
+ parser.add_argument(
+ 'output',
+ help="Path to the output SVG file",
+ type=Path)
+ parser.add_argument(
+ '--num-iopads',
+ help='Number of iopads to render',
+ type=int,
+ default=38)
+ parser.add_argument(
+ '--yosys-executable',
+ help='Path to yosys executable',
+ type=Path,
+ default='yosys')
+ parser.add_argument(
+ '--netlistsvg-executable',
+ help='Path to netlistsvg executable',
+ type=Path,
+ default='netlistsvg')
+ parser.add_argument(
+ '--inouts-as',
+ help='To what kind of IO should inout ports be replaced',
+ choices=['input', 'output'],
+ default='input'
+ )
+
+ args = parser.parse_args(argv[1:])
+
+ fd, jsonpath = mkstemp(suffix='-yosys.json')
+ os.close(fd)
+
+ yosyscommand = [
+ f'{str(args.yosys_executable)}',
+ '-p',
+ 'read_verilog pads.v defines.v; ' +
+ 'read_verilog -lib -overwrite *.v; ' +
+ f'verilog_defines -DMPRJ_IO_PADS={args.num_iopads}; ' +
+ 'read_verilog -overwrite caravel.v; ' +
+ 'hierarchy -top caravel; ' +
+ 'proc; ' +
+ 'opt; ' +
+ f'write_json {jsonpath}; '
+ ]
+
+ result = subprocess.run(
+ yosyscommand,
+ cwd=args.verilog_rtl_dir,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT
+ )
+
+ exitcode = 0
+ if result.returncode != 0:
+ print(f'Failed to run: {" ".join(yosyscommand)}', file=sys.stderr)
+ print(result.stdout.decode())
+ exitcode = result.returncode
+ else:
+ # TODO once netlistsvg supports inout ports, this should be removed
+ remove_inouts(jsonpath, args.inouts_as)
+ command = f'{args.netlistsvg_executable} {jsonpath} -o {args.output}'
+ result = subprocess.run(
+ command.split(),
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT
+ )
+ if result.returncode != 0:
+ print(f'Failed to run: {command}', file=sys.stderr)
+ print(result.stdout.decode())
+ exitcode = result.returncode
+
+ os.unlink(jsonpath)
+ sys.exit(exitcode)
+
+
+if __name__ == '__main__':
+ sys.exit(main(sys.argv))
diff --git a/caravel/scripts/generate_fill.py b/caravel/scripts/generate_fill.py
new file mode 100755
index 0000000..c03a9f2
--- /dev/null
+++ b/caravel/scripts/generate_fill.py
@@ -0,0 +1,416 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# generate_fill.py ---
+#
+# Run the fill generation on a layout top level.
+#
+
+import sys
+import os
+import re
+import glob
+import subprocess
+import multiprocessing
+
+def usage():
+ print("Usage:")
+ print("generate_fill.py <user_id_value> <project> <path_to_project> [-keep] [-test] [-dist]")
+ print("")
+ print("where:")
+ print(" <user_id_value> is a character string of eight hex digits, and")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <user_id_value> is not given, then it must exist in the info.yaml file.")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ print(" If '-test' is specified, then create but do not run the generation script.")
+ print(" If '-dist' is specified, then run distributed (multi-processing).")
+
+ return 0
+
+def makegds(file):
+ # Procedure for multiprocessing run only: Run the distributed processing
+ # script to load a .mag file of one flattened square area of the layout,
+ # and run the fill generator to produce a .gds file output from it.
+
+ magpath = os.path.split(file)[0]
+ filename = os.path.split(file)[1]
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill_dist.tcl',
+ filename],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+ testmode = False
+ distmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) < 3:
+ print("Wrong number of arguments given to generate_fill.py.")
+ usage()
+ sys.exit(1)
+
+ user_id_value = arguments[0]
+ project = arguments[1]
+ user_project_path = arguments[2]
+
+ try:
+ # Convert to binary
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+
+ except:
+ print("User ID not recognized")
+ usage()
+ sys.exit(1)
+
+ # if len(arguments) == 0:
+ # user_project_path = os.getcwd()
+ # elif len(arguments) == 2:
+ # user_project_path = arguments[1]
+ # elif user_project_path == None:
+ # user_project_path = arguments[0]
+ # else:
+ # user_project_path = os.getcwd()
+
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ # if not user_id_value:
+ # if os.path.isfile(user_project_path + '/info.yaml'):
+ # with open(user_project_path + '/info.yaml', 'r') as ifile:
+ # infolines = ifile.read().splitlines()
+ # for line in infolines:
+ # kvpair = line.split(':')
+ # if len(kvpair) == 2:
+ # key = kvpair[0].strip()
+ # value = kvpair[1].strip()
+ # if key == 'project_id':
+ # user_id_value = value.strip('"\'')
+ # break
+
+ if user_id_value:
+ project_with_id = 'caravel_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+ if '-test' in optionlist:
+ testmode = True
+ if '-dist' in optionlist:
+ distmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ if not os.path.isfile(rcfile):
+ rcfile = None
+
+ topdir = user_project_path
+ gdsdir = topdir + '/gds'
+ hasgdsdir = True if os.path.isdir(gdsdir) else False
+
+ ofile = open(magpath + '/generate_fill.tcl', 'w')
+
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box size 700um 700um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ print('set stepheight [lindex $stepbox 3]', file=ofile)
+ print('', file=ofile)
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started: $starttime"', file=ofile)
+ print('', file=ofile)
+ # Read the user project from GDS, as there is not necessarily a magic database file
+ # to go along with this.
+ # print('gds read ../gds/user_project_wrapper', file=ofile)
+ # Now read the full caravel project
+ # print('load ' + project + ' -dereference', file=ofile)
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/' + project, file=ofile)
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+ if not distmode:
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepwidth))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepheight))}]', file=ofile)
+ print('box size $stepwidth $stepheight', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ # Break layout into tiles and process each separately
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' if {$xhi > $fullwidth} {set xhi $fullwidth}', file=ofile)
+ print(' if {$yhi > $fullheight} {set yhi $fullheight}', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ # The flattened area must be larger than the fill tile by >1.5um
+ print(' box grow c 1.6um', file=ofile)
+
+ # Flatten into a cell with a new name
+ print(' puts stdout "Flattening layout of tile x=$x y=$y. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' flatten -dobox -nolabels ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ # Remove any GDS_FILE reference (there should not be any?)
+ print(' property GDS_FILE ""', file=ofile)
+ # Set boundary using comment layer, to the size of the step box
+ # This corresponds to the "topbox" rule in the wafflefill(tiled) style
+ print(' select top cell', file=ofile)
+ print(' erase comment', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+
+ if not distmode:
+ print(' puts stdout "Writing GDS. . . "', file=ofile)
+
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+
+ if distmode:
+ print(' writeall force ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ else:
+ print(' gds write ' + project_with_id + '_fill_pattern_${x}_$y.gds', file=ofile)
+ # Reload project top
+ print(' load ' + project, file=ofile)
+
+ # Remove last generated cell to save memory
+ print(' cellname delete ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ if distmode:
+ print('set ofile [open fill_gen_info.txt w]', file=ofile)
+ print('puts $ofile "$stepwidth"', file=ofile)
+ print('puts $ofile "$stepheight"', file=ofile)
+ print('puts $ofile "$xtiles"', file=ofile)
+ print('puts $ofile "$ytiles"', file=ofile)
+ print('puts $ofile "$xbase"', file=ofile)
+ print('puts $ofile "$ybase"', file=ofile)
+ print('close $ofile', file=ofile)
+ print('quit -noprompt', file=ofile)
+ ofile.close()
+
+ with open(magpath + '/generate_fill_dist.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('set filename [file root [lindex $argv $argc-1]]', file=ofile)
+ print('load $filename', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('gds write [file root $filename].gds', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ ofile = open(magpath + '/generate_fill_final.tcl', 'w')
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+
+ print('set ifile [open fill_gen_info.txt r]', file=ofile)
+ print('gets $ifile stepwidth', file=ofile)
+ print('gets $ifile stepheight', file=ofile)
+ print('gets $ifile xtiles', file=ofile)
+ print('gets $ifile ytiles', file=ofile)
+ print('gets $ifile xbase', file=ofile)
+ print('gets $ifile ybase', file=ofile)
+ print('close $ifile', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+
+ # Now create simple "fake" views of all the tiles.
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y -quiet', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' property FIXED_BBOX "$xlo $ylo $xhi $yhi"', file=ofile)
+ print(' property GDS_FILE ' + project_with_id + '_fill_pattern_${x}_${y}.gds', file=ofile)
+ print(' property GDS_START 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now tile everything back together
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' box values 0 0 0 0', file=ofile)
+ print(' getcell ' + project_with_id + '_fill_pattern_${x}_$y child 0 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # And write final GDS
+ print('puts stdout "Writing final GDS"', file=ofile)
+
+ print('cif *hier write disable', file=ofile)
+ print('cif *array write disable', file=ofile)
+ if hasgdsdir:
+ print('gds write ../gds/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ else:
+ print('gds write ' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('quit -noprompt', file=ofile)
+ ofile.close()
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ if not testmode:
+ # Diagnostic
+ # print('This script will generate file ' + project_with_id + '_fill_pattern.gds')
+ print('This script will generate files ' + project_with_id + '_fill_pattern_x_y.gds')
+ print('Now generating fill patterns. This may take. . . quite. . . a while.', flush=True)
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if distmode:
+ # If using distributed mode, then run magic on each of the generated
+ # layout files
+ pool = multiprocessing.Pool()
+ magfiles = glob.glob(magpath + '/' + project_with_id + '_fill_pattern_*.mag')
+ # NOTE: Adding 'x' to the end of each filename, or else magic will
+ # try to read it from the command line as well as passing it as an
+ # argument to the script. We only want it passed as an argument.
+ magxfiles = list(item + 'x' for item in magfiles)
+ pool.map(makegds, magxfiles)
+
+ # If using distributed mode, then remove all of the temporary .mag files
+ # and then run the final generation script.
+ for file in magfiles:
+ os.remove(file)
+
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill_final.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ # Remove fill generation script
+ os.remove(magpath + '/generate_fill.tcl')
+ # Remove all individual fill tiles, leaving only the composite GDS.
+ filelist = os.listdir(magpath)
+ for file in filelist:
+ if os.path.splitext(magpath + '/' + file)[1] == '.gds':
+ if file.startswith(project_with_id + '_fill_pattern_'):
+ os.remove(magpath + '/' + file)
+
+ if distmode:
+ os.remove(magpath + '/generate_fill_dist.tcl')
+ os.remove(magpath + '/generate_fill_final.tcl')
+ os.remove(magpath + '/fill_gen_info.txt')
+ if testmode:
+ magfiles = glob.glob(magpath + '/' + project_with_id + '_fill_pattern_*.mag')
+ for file in magfiles:
+ os.remove(file)
+
+ print('Done!')
+ exit(0)
diff --git a/caravel/scripts/generate_fill_orig.py b/caravel/scripts/generate_fill_orig.py
new file mode 100755
index 0000000..3a43a8c
--- /dev/null
+++ b/caravel/scripts/generate_fill_orig.py
@@ -0,0 +1,268 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# generate_fill_orig.py ---
+#
+# Run the fill generation on a layout top level.
+# This is the older version that does not have a "-dist" option for
+# distributed (multiprocessing) operation.
+#
+
+import sys
+import os
+import re
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("generate_fill_orig.py [<path_to_project>] [-keep] [-test]")
+ print("")
+ print("where:")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ print(" If '-test' is specified, then create but do not run the generation script.")
+ return 0
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+ testmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 1:
+ print("Wrong number of arguments given to generate_fill_orig.py.")
+ usage()
+ sys.exit(1)
+
+ if len(arguments) == 1:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ user_id_value = None
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ project = 'caravel'
+ if user_id_value:
+ project_with_id = project + '_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+ if '-test' in optionlist:
+ testmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ if not os.path.isfile(rcfile):
+ rcfile = None
+
+ topdir = user_project_path
+ gdsdir = topdir + '/gds'
+ hasgdsdir = True if os.path.isdir(gdsdir) else False
+
+ with open(magpath + '/generate_fill.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box size 700um 700um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ print('set stepheight [lindex $stepbox 3]', file=ofile)
+ print('', file=ofile)
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started: $starttime"', file=ofile)
+ print('', file=ofile)
+ # Read the user project from GDS, as there is not necessarily a magic database file
+ # to go along with this.
+ # print('gds read ../gds/user_project_wrapper', file=ofile)
+ # Now read the full caravel project
+ # print('load ' + project + ' -dereference', file=ofile)
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/caravel', file=ofile)
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepwidth))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepheight))}]', file=ofile)
+ print('box size $stepwidth $stepheight', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ # Break layout into tiles and process each separately
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' if {$xhi > $fullwidth} {set xhi $fullwidth}', file=ofile)
+ print(' if {$yhi > $fullheight} {set yhi $fullheight}', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ # The flattened area must be larger than the fill tile by >1.5um
+ print(' box grow c 1.6um', file=ofile)
+
+ # Flatten into a cell with a new name
+ print(' puts stdout "Flattening layout of tile x=$x y=$y. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' flatten -dobox -nolabels ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ # Remove any GDS_FILE reference (there should not be any?)
+ print(' property GDS_FILE ""', file=ofile)
+ # Set boundary using comment layer, to the size of the step box
+ # This corresponds to the "topbox" rule in the wafflefill(tiled) style
+ print(' select top cell', file=ofile)
+ print(' erase comment', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' puts stdout "Writing GDS. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' gds write ' + project_with_id + '_fill_pattern_${x}_$y.gds', file=ofile)
+
+ # Reload project top
+ print(' load ' + project, file=ofile)
+
+ # Remove last generated cell to save memory
+ print(' cellname delete ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now create simple "fake" views of all the tiles.
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y -quiet', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' property FIXED_BBOX "$xlo $ylo $xhi $yhi"', file=ofile)
+ print(' property GDS_FILE ' + project_with_id + '_fill_pattern_${x}_${y}.gds', file=ofile)
+ print(' property GDS_START 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now tile everything back together
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' box values 0 0 0 0', file=ofile)
+ print(' getcell ' + project_with_id + '_fill_pattern_${x}_$y child 0 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # And write final GDS
+ print('puts stdout "Writing final GDS"', file=ofile)
+
+ print('cif *hier write disable', file=ofile)
+ print('cif *array write disable', file=ofile)
+ if hasgdsdir:
+ print('gds write ../gds/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ else:
+ print('gds write ' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ if not testmode:
+ # Diagnostic
+ # print('This script will generate file ' + project_with_id + '_fill_pattern.gds')
+ print('This script will generate files ' + project_with_id + '_fill_pattern_x_y.gds')
+ print('Now generating fill patterns. This may take. . . quite. . . a while.', flush=True)
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ # Remove fill generation script
+ os.remove(magpath + '/generate_fill.tcl')
+ # Remove all individual fill tiles, leaving only the composite GDS.
+ filelist = os.listdir(magpath)
+ for file in filelist:
+ if os.path.splitext(magpath + '/' + file)[1] == '.gds':
+ if file.startswith(project + '_fill_pattern_'):
+ os.remove(magpath + '/' + file)
+
+ print('Done!')
+ exit(0)
diff --git a/caravel/scripts/make_bump_bonds.tcl b/caravel/scripts/make_bump_bonds.tcl
new file mode 100644
index 0000000..ade81d6
--- /dev/null
+++ b/caravel/scripts/make_bump_bonds.tcl
@@ -0,0 +1,702 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+#----------------------------------------------------------------------
+# Assumes running magic -T micross using the micross technology file
+# from the open_pdks installation of sky130A
+#----------------------------------------------------------------------
+# bump bond pitch is 500um. Bump diameter is set by the technology
+
+namespace path {::tcl::mathop ::tcl::mathfunc}
+
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+source $PDKPATH/libs.tech/magic/current/bump_bond_generator/bump_bond.tcl
+
+# Caravel dimensions, in microns
+set chipwidth 3588
+set chipheight 5188
+
+set halfwidth [/ $chipwidth 2]
+set halfheight [/ $chipheight 2]
+
+set columns 6
+set rows 10
+
+set bump_pitch 500
+
+set llx [- $halfwidth [* [- [/ $columns 2] 0.5] $bump_pitch]]
+set lly [- $halfheight [* [- [/ $rows 2] 0.5] $bump_pitch]]
+
+# Create a new cell
+load caravel_bump_bond -quiet
+
+# Build the bump cells
+make_bump_bond 0
+make_bump_bond 45
+
+# View the whole chip during generation. This is not strictly
+# necessary, but looks nice!
+snap internal
+box values 0 0 ${chipwidth}um ${chipheight}um
+paint glass
+view
+erase glass
+box values 0 0 0 0
+grid 250um 250um 45um 95um
+
+# Starting from the bottom left-hand corner and scanning across and up,
+# these are the orientations of the bump bond pad tapers:
+set tapers {}
+lappend tapers 180 225 270 270 270 270
+lappend tapers 180 135 225 270 0 0
+lappend tapers 180 135 135 270 315 0
+lappend tapers 180 135 135 315 315 0
+lappend tapers 135 135 0 180 315 0
+lappend tapers 180 135 0 180 315 0
+lappend tapers 180 135 180 315 315 0
+lappend tapers 180 180 135 45 315 0
+lappend tapers 135 135 135 45 45 45
+lappend tapers 90 90 90 90 45 90
+
+box values 0 0 0 0
+set t 0
+for {set y 0} {$y < $rows} {incr y} {
+ for {set x 0} {$x < $columns} {incr x} {
+ set xpos [+ $llx [* $x $bump_pitch]]
+ set ypos [+ $lly [* $y $bump_pitch]]
+ draw_bump_bond $xpos $ypos [lindex $tapers $t]
+ incr t
+ }
+}
+
+# The pad at E6 has wires exiting two sides, so put another pad down
+# at the other orientation.
+set y 4
+set x 4
+set xpos [+ $llx [* $x $bump_pitch]]
+set ypos [+ $lly [* $y $bump_pitch]]
+draw_bump_bond $xpos $ypos 180
+
+select top cell
+expand
+
+# These are the pad Y positions on the left side from bottom to top
+
+set leftpads {}
+lappend leftpads 377.5 588.5 950.5 1166.5 1382.5 1598.5 1814.5
+lappend leftpads 2030.5 2241.5 2452.5 2668.5 2884.5 3100.5
+lappend leftpads 3316.5 3532.5 3748.5 3964.5 4175.5 4386.5 4597.5 4813.5
+
+# These are the pad X positions on the top side from left to right
+
+set toppads {}
+lappend toppads 423.5 680.5 937.5 1194.5 1452.5 1704.5 1961.5 2406.5
+lappend toppads 2663.5 2915.5 3172.5
+
+# These are the pad Y positions on the right side from bottom to top
+
+set rightpads {}
+lappend rightpads 537.5 763.5 988.5 1214.5 1439.5 1664.5 1890.5
+lappend rightpads 2115.5 2336.5 2556.5 2776.5 3002.5 3227.5 3453.5
+lappend rightpads 3678.5 3903.5 4129.5 4349.5 4575.5 4795.5
+
+# These are the pad X positions on the bottom side from left to right
+
+set bottompads {}
+lappend bottompads 431.5 700.5 969.5 1243.5 1512.5 1786.5 2060.5
+lappend bottompads 2334.5 2608.5 2882.5 3151.5
+
+set leftpadx 64.6
+set rightpadx 3523.78
+set bottompady 64.6
+set toppady 5123.78
+
+set xpos $leftpadx
+for {set y 0} {$y < [llength $leftpads]} {incr y} {
+ set ypos [lindex $leftpads $y]
+ draw_pad_bond $xpos $ypos
+}
+
+set ypos $toppady
+for {set x 0} {$x < [llength $toppads]} {incr x} {
+ set xpos [lindex $toppads $x]
+ draw_pad_bond $xpos $ypos
+}
+
+set xpos $rightpadx
+for {set y 0} {$y < [llength $rightpads]} {incr y} {
+ set ypos [lindex $rightpads $y]
+ draw_pad_bond $xpos $ypos
+}
+
+set ypos $bottompady
+for {set x 0} {$x < [llength $bottompads]} {incr x} {
+ set xpos [lindex $bottompads $x]
+ draw_pad_bond $xpos $ypos
+}
+
+# Now route between the wirebond pads and the bump bond pads
+# routes start centered on the wirebond pad and align to grid points
+# on a 1/2 ball pitch, although positions do not need to be on
+# integer values. The overlaid grid starts 1/2 pitch to the left
+# and below the center of the bottom left bump bond. Grid columns
+# are numbered 0 to 12, and grid rows are numbered 0 to 20. To
+# convert to a micron unit coordinate, use the to_grid procedure
+# defined below.
+
+set gridllx [- $llx 250.0]
+set gridlly [- $lly 250.0]
+set gridpitchx 250.0
+set gridpitchy 250.0
+
+proc to_grid {x y} {
+ global gridllx gridlly
+ set coords []
+ catch {lappend coords [+ $gridllx [* 250.0 $x]]}
+ catch {lappend coords [+ $gridlly [* 250.0 $y]]}
+ return $coords
+}
+
+# Detailed routing, scanning left to right and from bottom to top.
+# (This really needs to be automated. . .)
+
+set wire_width 40.0
+
+# A10 vccd
+set coords [list $leftpadx [lindex $leftpads 0]]
+lappend coords {*}[to_grid -0.8 1]
+lappend coords {*}[to_grid 1 1]
+draw_pad_route $coords $wire_width
+
+# B10 resetb
+set coords [list [lindex $bottompads 1] $bottompady]
+lappend coords {*}[to_grid 1.9 0.2]
+lappend coords {*}[to_grid 2.2 0.2]
+lappend coords {*}[to_grid 3 1]
+draw_pad_route $coords $wire_width
+
+# C10 flash csb
+set coords [list [lindex $bottompads 4] $bottompady]
+lappend coords {*}[to_grid 5 0]
+lappend coords {*}[to_grid 5 1]
+draw_pad_route $coords $wire_width
+
+# D10 flash io0
+set coords [list [lindex $bottompads 6] $bottompady]
+lappend coords {*}[to_grid 7 0]
+lappend coords {*}[to_grid 7 1]
+draw_pad_route $coords $wire_width
+
+# E10 gpio
+set coords [list [lindex $bottompads 8] $bottompady]
+lappend coords {*}[to_grid 9 0.2]
+lappend coords {*}[to_grid 9 1]
+draw_pad_route $coords $wire_width
+
+# F10 vdda
+set coords [list [lindex $bottompads 10] $bottompady]
+lappend coords {*}[to_grid 11 0.3]
+lappend coords {*}[to_grid 11 1]
+draw_pad_route $coords $wire_width
+
+# A9 mprj_io[37]
+set coords [list $leftpadx [lindex $leftpads 2]]
+lappend coords {*}[to_grid -0.5 3]
+lappend coords {*}[to_grid 1 3]
+draw_pad_route $coords $wire_width
+
+# B9 mprj_io[36]
+set coords [list $leftpadx [lindex $leftpads 3]]
+lappend coords {*}[to_grid -0.6 4]
+lappend coords {*}[to_grid 2 4]
+lappend coords {*}[to_grid 3 3]
+draw_pad_route $coords $wire_width
+
+# C9 clock
+set coords [list [lindex $bottompads 2] $bottompady]
+lappend coords {*}[to_grid 3 0.2]
+lappend coords {*}[to_grid 3.4 0.2]
+lappend coords {*}[to_grid 3.8 0.6]
+lappend coords {*}[to_grid 3.8 1.6]
+lappend coords {*}[to_grid 4.5 2.3]
+lappend coords {*}[to_grid 4.5 2.5]
+lappend coords {*}[to_grid 5 3]
+draw_pad_route $coords $wire_width
+
+# D9 flash io1
+set coords [list [lindex $bottompads 7] $bottompady]
+lappend coords {*}[to_grid 8 0.1]
+lappend coords {*}[to_grid 8 1.3]
+lappend coords {*}[to_grid 7 2.3]
+lappend coords {*}[to_grid 7 3]
+draw_pad_route $coords $wire_width
+
+# E9 mprj_io[1]/SDO
+set coords [list $rightpadx [lindex $rightpads 1]]
+lappend coords {*}[to_grid 12.4 2.2]
+lappend coords {*}[to_grid 10.5 2.2]
+lappend coords {*}[to_grid 9.7 3]
+lappend coords {*}[to_grid 9 3]
+draw_pad_route $coords $wire_width
+
+# F9 mprj_io[2]/SDI
+set coords [list $rightpadx [lindex $rightpads 2]]
+lappend coords {*}[to_grid 12.3 3]
+lappend coords {*}[to_grid 11 3]
+draw_pad_route $coords $wire_width
+
+# A8 mprj_io[35]
+set coords [list $leftpadx [lindex $leftpads 4]]
+lappend coords {*}[to_grid -0.7 5]
+lappend coords {*}[to_grid 1 5]
+draw_pad_route $coords $wire_width
+
+# B8 mprj_io[34]
+set coords [list $leftpadx [lindex $leftpads 5]]
+lappend coords {*}[to_grid -0.7 5.8]
+lappend coords {*}[to_grid 2.2 5.8]
+lappend coords {*}[to_grid 3 5]
+draw_pad_route $coords $wire_width
+
+# C8 mprj_io[33]
+set coords [list $leftpadx [lindex $leftpads 6]]
+lappend coords {*}[to_grid -0.3 6.2]
+lappend coords {*}[to_grid 3.8 6.2]
+lappend coords {*}[to_grid 5 5]
+draw_pad_route $coords $wire_width
+
+# D8 flash clk
+set coords [list [lindex $bottompads 5] $bottompady]
+lappend coords {*}[to_grid 6 0]
+lappend coords {*}[to_grid 6 1]
+lappend coords {*}[to_grid 6.2 1.2]
+lappend coords {*}[to_grid 6.2 3.5]
+lappend coords {*}[to_grid 7 4.3]
+lappend coords {*}[to_grid 7 5]
+draw_pad_route $coords $wire_width
+
+# E8 mprj_io[3]/CSB
+set coords [list $rightpadx [lindex $rightpads 3]]
+lappend coords {*}[to_grid 12.4 4]
+lappend coords {*}[to_grid 10 4]
+lappend coords {*}[to_grid 9 5]
+draw_pad_route $coords $wire_width
+
+# F8 mrpj_io[4]/SCK
+set coords [list $rightpadx [lindex $rightpads 4]]
+lappend coords {*}[to_grid 12.5 5]
+lappend coords {*}[to_grid 11 5]
+draw_pad_route $coords $wire_width
+
+# A7 mrpj_io[32]
+set coords [list $leftpadx [lindex $leftpads 7]]
+lappend coords {*}[to_grid -0.2 7]
+lappend coords {*}[to_grid 1 7]
+draw_pad_route $coords $wire_width
+
+# B7 vssd2
+set coords [list $leftpadx [lindex $leftpads 8]]
+lappend coords {*}[to_grid -0.1 7.8]
+lappend coords {*}[to_grid 2.2 7.8]
+lappend coords {*}[to_grid 3 7]
+draw_pad_route $coords $wire_width
+
+# C7 vdda2
+set coords [list $leftpadx [lindex $leftpads 9]]
+lappend coords {*}[to_grid 0.3 8.2]
+lappend coords {*}[to_grid 2.3 8.2]
+lappend coords {*}[to_grid 2.5 8]
+lappend coords {*}[to_grid 4 8]
+lappend coords {*}[to_grid 5 7]
+draw_pad_route $coords $wire_width
+
+# D7 mrpj_io[0]/JTAG
+set coords [list $rightpadx [lindex $rightpads 0]]
+lappend coords {*}[to_grid 12.8 1.8]
+lappend coords {*}[to_grid 10.2 1.8]
+lappend coords {*}[to_grid 9.8 2.2]
+lappend coords {*}[to_grid 8.6 2.2]
+lappend coords {*}[to_grid 8.2 2.6]
+lappend coords {*}[to_grid 8.2 5.8]
+lappend coords {*}[to_grid 7 7]
+draw_pad_route $coords $wire_width
+
+# E7 mrpj_io[5]/ser_rx
+set coords [list $rightpadx [lindex $rightpads 5]]
+lappend coords {*}[to_grid 12.6 6]
+lappend coords {*}[to_grid 10 6]
+lappend coords {*}[to_grid 9 7]
+draw_pad_route $coords $wire_width
+
+# F7 mprj_io[6]/ser_tx
+set coords [list $rightpadx [lindex $rightpads 6]]
+lappend coords {*}[to_grid 12.7 7]
+lappend coords {*}[to_grid 11 7]
+draw_pad_route $coords $wire_width
+
+# A6 mprj_io[31]
+set coords [list $leftpadx [lindex $leftpads 10]]
+lappend coords {*}[to_grid -0.3 10.3]
+lappend coords {*}[to_grid 1 9]
+draw_pad_route $coords $wire_width
+
+# B6 mprj_io[30]
+set coords [list $leftpadx [lindex $leftpads 11]]
+lappend coords {*}[to_grid -0.5 10.8]
+lappend coords {*}[to_grid -0.3 10.8]
+lappend coords {*}[to_grid 0.5 10]
+lappend coords {*}[to_grid 2 10]
+lappend coords {*}[to_grid 3 9]
+draw_pad_route $coords $wire_width
+
+# C6 vssio/vssa/vssd: Connects to D6, D5, C5
+set coords [to_grid 5 9]
+lappend coords {*}[to_grid 5.65 9]
+lappend coords {*}[to_grid 5.85 9.2]
+lappend coords {*}[to_grid 6 9.2]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd
+set coords [to_grid 7 9]
+lappend coords {*}[to_grid 6.35 9]
+lappend coords {*}[to_grid 6.15 8.8]
+lappend coords {*}[to_grid 6 8.8]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $bottompads 0] $bottompady]
+lappend coords {*}[to_grid 0.9 0.2]
+lappend coords {*}[to_grid 1.3 0.2]
+lappend coords {*}[to_grid 2 0.9]
+lappend coords {*}[to_grid 2 1.5]
+lappend coords {*}[to_grid 2.3 1.8]
+lappend coords {*}[to_grid 3.5 1.8]
+lappend coords {*}[to_grid 4.2 2.5]
+lappend coords {*}[to_grid 4.2 3.5]
+lappend coords {*}[to_grid 4.5 3.8]
+lappend coords {*}[to_grid 5.3 3.8]
+lappend coords {*}[to_grid 5.8 3.3]
+lappend coords {*}[to_grid 5.8 2.5]
+lappend coords {*}[to_grid 5.3 2]
+lappend coords {*}[to_grid 4.8 2]
+lappend coords {*}[to_grid 4.2 1.4]
+lappend coords {*}[to_grid 4.2 0.3]
+lappend coords {*}[list [lindex $bottompads 3] $bottompady]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $bottompads 9] $bottompady]
+lappend coords {*}[to_grid 10 0.3]
+lappend coords {*}[to_grid 10 1.4]
+lappend coords {*}[to_grid 9.6 1.8]
+lappend coords {*}[to_grid 8.5 1.8]
+lappend coords {*}[to_grid 7.8 2.5]
+lappend coords {*}[to_grid 7.8 5.5]
+lappend coords {*}[to_grid 7.3 6]
+lappend coords {*}[to_grid 6.2 6]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $toppads 5] $toppady]
+lappend coords {*}[to_grid 6 19.7]
+lappend coords {*}[to_grid 6 16]
+lappend coords {*}[to_grid 5.8 15.8]
+lappend coords {*}[to_grid 5.8 12.2]
+lappend coords {*}[to_grid 6 12]
+lappend coords {*}[to_grid 6 8]
+lappend coords {*}[to_grid 6.2 7.8]
+lappend coords {*}[to_grid 6.2 4.3]
+lappend coords {*}[to_grid 5.5 3.6]
+draw_pad_route $coords $wire_width
+
+# E6 vssa1
+set coords [list $rightpadx [lindex $rightpads 7]]
+lappend coords {*}[to_grid 12.8 8]
+lappend coords {*}[to_grid 10 8]
+lappend coords {*}[to_grid 9 9]
+draw_pad_route $coords $wire_width
+
+# E6 vssa1 also goes to
+set coords [list [lindex $toppads 9] $toppady]
+lappend coords {*}[to_grid 10 19.5]
+lappend coords {*}[to_grid 10 18.5]
+lappend coords {*}[to_grid 9.5 18]
+lappend coords {*}[to_grid 8.5 18]
+lappend coords {*}[to_grid 8 17.5]
+lappend coords {*}[to_grid 8 16.5]
+lappend coords {*}[to_grid 7.5 16]
+lappend coords {*}[to_grid 6.7 16]
+lappend coords {*}[to_grid 6.2 15.5]
+lappend coords {*}[to_grid 6.2 12.6]
+lappend coords {*}[to_grid 6.7 12]
+lappend coords {*}[to_grid 7.3 12]
+lappend coords {*}[to_grid 7.8 11.5]
+lappend coords {*}[to_grid 7.8 10.2]
+lappend coords {*}[to_grid 8 10]
+lappend coords {*}[to_grid 8 9.3]
+lappend coords {*}[to_grid 8.3 9]
+lappend coords {*}[to_grid 9 9]
+draw_pad_route $coords $wire_width
+
+# F6 vssd1
+set coords [list $rightpadx [lindex $rightpads 8]]
+lappend coords {*}[to_grid 12.9 9]
+lappend coords {*}[to_grid 11 9]
+draw_pad_route $coords $wire_width
+
+# A5 mprj_io[29]
+set coords [list $leftpadx [lindex $leftpads 12]]
+lappend coords {*}[to_grid 0.2 11]
+lappend coords {*}[to_grid 1 11]
+draw_pad_route $coords $wire_width
+
+# B5 mprj_io[28]
+set coords [list $leftpadx [lindex $leftpads 13]]
+lappend coords {*}[to_grid 0 12]
+lappend coords {*}[to_grid 2 12]
+lappend coords {*}[to_grid 3 11]
+draw_pad_route $coords $wire_width
+
+# C5 vssio/vssa/vssd : Connects to D6, C6, D5
+set coords [to_grid 5 11]
+lappend coords {*}[to_grid 5.65 11]
+lappend coords {*}[to_grid 5.85 11.2]
+lappend coords {*}[to_grid 6 11.2]
+draw_pad_route $coords $wire_width
+
+# D5 vssio/vssa/vssd : Connects to D6, C6, C5
+set coords [to_grid 7 11]
+lappend coords {*}[to_grid 6.35 11]
+lappend coords {*}[to_grid 6.15 10.8]
+lappend coords {*}[to_grid 6 10.8]
+draw_pad_route $coords $wire_width
+
+# E5 mprj_io[7]/irq
+set coords [list $rightpadx [lindex $rightpads 10]]
+lappend coords {*}[to_grid 12.4 10.2]
+lappend coords {*}[to_grid 9.8 10.2]
+lappend coords {*}[to_grid 9 11]
+draw_pad_route $coords $wire_width
+
+# F5 mprj_io[8]/flash2 csb
+set coords [list $rightpadx [lindex $rightpads 11]]
+lappend coords {*}[to_grid 12.3 11]
+lappend coords {*}[to_grid 11 11]
+draw_pad_route $coords $wire_width
+
+# A4 mprj_io[27]
+set coords [list $leftpadx [lindex $leftpads 14]]
+lappend coords {*}[to_grid -0.1 13]
+lappend coords {*}[to_grid 1 13]
+draw_pad_route $coords $wire_width
+
+# B4 mprj_io[26]
+set coords [list $leftpadx [lindex $leftpads 15]]
+lappend coords {*}[to_grid -0.2 14]
+lappend coords {*}[to_grid 2 14]
+lappend coords {*}[to_grid 3 13]
+draw_pad_route $coords $wire_width
+
+# C4 vddio
+set coords [list $leftpadx [lindex $leftpads 1]]
+lappend coords {*}[to_grid -0.8 2]
+lappend coords {*}[to_grid 1.8 2]
+lappend coords {*}[to_grid 2 2.2]
+lappend coords {*}[to_grid 3.3 2.2]
+lappend coords {*}[to_grid 3.8 2.7]
+lappend coords {*}[to_grid 3.8 3.7]
+lappend coords {*}[to_grid 4.3 4.2]
+lappend coords {*}[to_grid 5.3 4.2]
+lappend coords {*}[to_grid 5.8 4.7]
+lappend coords {*}[to_grid 5.8 7.4]
+lappend coords {*}[to_grid 5.2 8]
+lappend coords {*}[to_grid 4.7 8]
+lappend coords {*}[to_grid 4 8.7]
+lappend coords {*}[to_grid 4 13]
+draw_pad_route $coords $wire_width
+
+# C4 vddio is also:
+set coords [list $leftpadx [lindex $leftpads 18]]
+lappend coords {*}[to_grid 0.1 16.2]
+lappend coords {*}[to_grid 1.6 16.2]
+lappend coords {*}[to_grid 2 15.8]
+lappend coords {*}[to_grid 3.4 15.8]
+lappend coords {*}[to_grid 4 15.2]
+lappend coords {*}[to_grid 4 13]
+lappend coords {*}[to_grid 5 13]
+draw_pad_route $coords $wire_width
+
+# D4 vdda1
+set coords [list $rightpadx [lindex $rightpads 9]]
+lappend coords {*}[to_grid 12.8 9.8]
+lappend coords {*}[to_grid 9.7 9.8]
+lappend coords {*}[to_grid 9.5 10]
+lappend coords {*}[to_grid 8.8 10]
+lappend coords {*}[to_grid 8.2 10.6]
+lappend coords {*}[to_grid 8.2 11.8]
+lappend coords {*}[to_grid 7 13]
+draw_pad_route $coords $wire_width
+
+# D4 vdda1 is also:
+set coords [list $rightpadx [lindex $rightpads 16]]
+lappend coords {*}[to_grid 12.6 15.8]
+lappend coords {*}[to_grid 8.4 15.8]
+lappend coords {*}[to_grid 8 15.4]
+lappend coords {*}[to_grid 8 12.4]
+lappend coords {*}[to_grid 7.8 12.2]
+draw_pad_route $coords $wire_width
+
+# E4 mprj_io[9]/flash2 sck
+set coords [list $rightpadx [lindex $rightpads 12]]
+lappend coords {*}[to_grid 12.4 12]
+lappend coords {*}[to_grid 10 12]
+lappend coords {*}[to_grid 9 13]
+draw_pad_route $coords $wire_width
+
+# F4 mprj_io[10]/flash2 io0
+set coords [list $rightpadx [lindex $rightpads 13]]
+lappend coords {*}[to_grid 12.5 13]
+lappend coords {*}[to_grid 11 13]
+draw_pad_route $coords $wire_width
+
+# A3 mprj_io[25]
+set coords [list $leftpadx [lindex $leftpads 16]]
+lappend coords {*}[to_grid -0.4 15]
+lappend coords {*}[to_grid 1 15]
+draw_pad_route $coords $wire_width
+
+# B3 vssa2
+set coords [list $leftpadx [lindex $leftpads 17]]
+lappend coords {*}[to_grid -0.4 15.8]
+lappend coords {*}[to_grid 0 15.8]
+lappend coords {*}[to_grid 1.3 15.8]
+lappend coords {*}[to_grid 2.2 15]
+lappend coords {*}[to_grid 3 15]
+draw_pad_route $coords $wire_width
+
+# C3 mprj_io[24]
+set coords [list $leftpadx [lindex $leftpads 20]]
+lappend coords {*}[to_grid 0 18]
+lappend coords {*}[to_grid 1.5 18]
+lappend coords {*}[to_grid 2 17.5]
+lappend coords {*}[to_grid 2 16.5]
+lappend coords {*}[to_grid 2.3 16.2]
+lappend coords {*}[to_grid 3.8 16.2]
+lappend coords {*}[to_grid 5 15]
+draw_pad_route $coords $wire_width
+
+# D3 mprj_io[13]
+set coords [list $rightpadx [lindex $rightpads 17]]
+lappend coords {*}[to_grid 12 16.2]
+lappend coords {*}[to_grid 8.2 16.2]
+lappend coords {*}[to_grid 7 15]
+draw_pad_route $coords $wire_width
+
+# E3 mprj_io[11]/flash2 io1
+set coords [list $rightpadx [lindex $rightpads 14]]
+lappend coords {*}[to_grid 12.6 14]
+lappend coords {*}[to_grid 10 14]
+lappend coords {*}[to_grid 9 15]
+draw_pad_route $coords $wire_width
+
+# F3 mprj_io[12]
+set coords [list $rightpadx [lindex $rightpads 15]]
+lappend coords {*}[to_grid 12.7 15]
+lappend coords {*}[to_grid 11 15]
+draw_pad_route $coords $wire_width
+
+# A2 vccd2
+set coords [list $leftpadx [lindex $leftpads 19]]
+lappend coords {*}[to_grid -0.4 17.5]
+lappend coords {*}[to_grid 0.5 17.5]
+lappend coords {*}[to_grid 1 17]
+draw_pad_route $coords $wire_width
+
+# B2 mprj_io[22]
+set coords [list [lindex $toppads 1] $toppady]
+lappend coords {*}[to_grid 2 19.7]
+lappend coords {*}[to_grid 2 18]
+lappend coords {*}[to_grid 3 17]
+draw_pad_route $coords $wire_width
+
+# C2 mprj_io[20]
+set coords [list [lindex $toppads 3] $toppady]
+lappend coords {*}[to_grid 4 19.7]
+lappend coords {*}[to_grid 4 18]
+lappend coords {*}[to_grid 5 17]
+draw_pad_route $coords $wire_width
+
+# D2 mprj_io[17]
+set coords [list [lindex $toppads 7] $toppady]
+lappend coords {*}[to_grid 8 19.7]
+lappend coords {*}[to_grid 8 18]
+lappend coords {*}[to_grid 7 17]
+draw_pad_route $coords $wire_width
+
+# E2 mprj_io[14]
+set coords [list $rightpadx [lindex $rightpads 19]]
+lappend coords {*}[to_grid 12.6 18.5]
+lappend coords {*}[to_grid 12 18.5]
+lappend coords {*}[to_grid 11.5 18]
+lappend coords {*}[to_grid 10 18]
+lappend coords {*}[to_grid 9 17]
+draw_pad_route $coords $wire_width
+
+# F2 vccd1
+set coords [list $rightpadx [lindex $rightpads 18]]
+lappend coords {*}[to_grid 12.5 17.5]
+lappend coords {*}[to_grid 11.5 17.5]
+lappend coords {*}[to_grid 11 17]
+draw_pad_route $coords $wire_width
+
+# A1 mprj_io[23]
+set coords [list [lindex $toppads 0] $toppady]
+lappend coords {*}[to_grid 1 19.7]
+lappend coords {*}[to_grid 1 19]
+draw_pad_route $coords $wire_width
+
+# B1 mprj_io[21]
+set coords [list [lindex $toppads 2] $toppady]
+lappend coords {*}[to_grid 3 19.7]
+lappend coords {*}[to_grid 3 19]
+draw_pad_route $coords $wire_width
+
+# C1 mprj_io[19]
+set coords [list [lindex $toppads 4] $toppady]
+lappend coords {*}[to_grid 5 19.7]
+lappend coords {*}[to_grid 5 19]
+draw_pad_route $coords $wire_width
+
+# D1 mrpj_io[18]
+set coords [list [lindex $toppads 6] $toppady]
+lappend coords {*}[to_grid 7 19.7]
+lappend coords {*}[to_grid 7 19]
+draw_pad_route $coords $wire_width
+
+# E1 mprj_io[16]
+set coords [list [lindex $toppads 8] $toppady]
+lappend coords {*}[to_grid 9.5 20]
+lappend coords {*}[to_grid 9.5 19.5]
+lappend coords {*}[to_grid 9 19]
+draw_pad_route $coords $wire_width
+
+# F1 mprj_io[15]
+set coords [list [lindex $toppads 10] $toppady]
+lappend coords {*}[to_grid 11 19.7]
+lappend coords {*}[to_grid 11 19]
+draw_pad_route $coords $wire_width
+
diff --git a/caravel/scripts/set_user_id.py b/caravel/scripts/set_user_id.py
new file mode 100755
index 0000000..6596bd0
--- /dev/null
+++ b/caravel/scripts/set_user_id.py
@@ -0,0 +1,348 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#----------------------------------------------------------------------
+#
+# set_user_id.py ---
+#
+# Manipulate the magic database, GDS, and verilog source files for the
+# user_id_programming block to set the user ID number.
+#
+# The user ID number is a 32-bit value that is passed to this routine
+# as an 8-digit hex number. If not given as an option, then the script
+# will look for the value of the key "project_id" in the info.yaml file
+# in the project top level directory
+#
+# user_id_programming layout map:
+# Positions marked (in microns) for value = 0. For value = 1, move
+# the via 0.92um to the left.
+#
+# Layout grid is 0.46um x 0.34um with half-pitch offset (0.23um, 0.17um)
+#
+# Signal Via position (um)
+# name X Y
+#--------------------------------
+# mask_rev[0] 14.49 9.35
+# mask_rev[1] 16.33 9.35
+# mask_rev[2] 10.35 20.23
+# mask_rev[3] 8.05 9.35
+# mask_rev[4] 28.29 9.35
+# mask_rev[5] 21.85 25.67
+# mask_rev[6] 8.05 20.23
+# mask_rev[7] 20.47 9.35
+# mask_rev[8] 17.25 17.85
+# mask_rev[9] 25.53 12.07
+# mask_rev[10] 22.31 20.23
+# mask_rev[11] 13.11 9.35
+# mask_rev[12] 23.69 23.29
+# mask_rev[13] 24.15 12.07
+# mask_rev[14] 13.57 17.85
+# mask_rev[15] 23.23 6.97
+# mask_rev[16] 24.15 17.85
+# mask_rev[17] 8.51 17.85
+# mask_rev[18] 23.69 20.23
+# mask_rev[19] 10.81 23.29
+# mask_rev[20] 14.95 6.97
+# mask_rev[21] 18.17 23.29
+# mask_rev[22] 21.39 17.85
+# mask_rev[23] 26.45 25.67
+# mask_rev[24] 9.89 17.85
+# mask_rev[25] 15.87 17.85
+# mask_rev[26] 26.45 17.85
+# mask_rev[27] 8.51 6.97
+# mask_rev[28] 10.81 9.35
+# mask_rev[29] 27.83 20.23
+# mask_rev[30] 16.33 23.29
+# mask_rev[31] 8.05 14.79
+#----------------------------------------------------------------------
+
+import os
+import sys
+import re
+
+def usage():
+ print("Usage:")
+ print("set_user_id.py [<user_id_value>] [<path_to_project>]")
+ print("")
+ print("where:")
+ print(" <user_id_value> is a character string of eight hex digits, and")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <user_id_value> is not given, then it must exist in the info.yaml file.")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ return 0
+
+if __name__ == '__main__':
+
+ # Coordinate pairs in microns for the zero position on each bit
+ mask_rev = (
+ (14.49, 9.35), (16.33, 9.35), (10.35, 20.23), ( 8.05, 9.35),
+ (28.29, 9.35), (21.85, 25.67), ( 8.05, 20.23), (20.47, 9.35),
+ (17.25, 17.85), (25.53, 12.07), (22.31, 20.23), (13.11, 9.35),
+ (23.69, 23.29), (24.15, 12.07), (13.57, 17.85), (23.23, 6.97),
+ (24.15, 17.85), ( 8.51, 17.85), (23.69, 20.23), (10.81, 23.29),
+ (14.95, 6.97), (18.17, 23.29), (21.39, 17.85), (26.45, 25.67),
+ ( 9.89, 17.85), (15.87, 17.85), (26.45, 17.85), ( 8.51, 6.97),
+ (10.81, 9.35), (27.83, 20.23), (16.33, 23.29), ( 8.05, 14.79));
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ reportmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 2:
+ print("Wrong number of arguments given to set_user_id.py.")
+ usage()
+ sys.exit(0)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-report' in optionlist:
+ reportmode = True
+
+ user_id_value = None
+ user_project_path = None
+
+ if len(arguments) > 0:
+ user_id_value = arguments[0]
+
+ # Convert to binary
+ try:
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+ except:
+ user_project_path = arguments[0]
+
+ if len(arguments) == 0:
+ user_project_path = os.getcwd()
+ elif len(arguments) == 2:
+ user_project_path = arguments[1]
+ elif user_project_path == None:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid directories
+
+ if not user_id_value:
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ if not user_id_value:
+ print('Error: No project_id key:value pair found in project info.yaml.')
+ sys.exit(1)
+
+ try:
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+ except:
+ print('Error: Cannot parse user ID "' + user_id_value + '" as an 8-digit hex number.')
+ sys.exit(1)
+
+ else:
+ print('Error: No info.yaml file and no user ID argument given.')
+ sys.exit(1)
+
+ if reportmode:
+ print(str(user_id_int))
+ sys.exit(0)
+
+ print('Setting project user ID to: ' + user_id_value)
+
+ magpath = user_project_path + '/mag'
+ gdspath = user_project_path + '/gds'
+ vpath = user_project_path + '/verilog'
+ errors = 0
+
+ if not os.path.isdir(gdspath):
+ print('No directory ' + gdspath + ' found (path to GDS).')
+ sys.exit(1)
+
+ if not os.path.isdir(vpath):
+ print('No directory ' + vpath + ' found (path to verilog).')
+ sys.exit(1)
+
+ if not os.path.isdir(magpath):
+ print('No directory ' + magpath + ' found (path to magic databases).')
+ sys.exit(1)
+
+ print('Step 1: Modify GDS of the user_id_programming subcell')
+
+ # Bytes leading up to via position are:
+ viarec = "00 06 0d 02 00 43 00 06 0e 02 00 2c 00 2c 10 03 "
+ viabytes = bytes.fromhex(viarec)
+
+ # Read the GDS file. If a backup was made of the zero-value
+ # program, then use it.
+
+ gdsbak = gdspath + '/user_id_prog_zero.gds'
+ gdsfile = gdspath + '/user_id_programming.gds'
+
+ if os.path.isfile(gdsbak):
+ with open(gdsbak, 'rb') as ifile:
+ gdsdata = ifile.read()
+ else:
+ with open(gdsfile, 'rb') as ifile:
+ gdsdata = ifile.read()
+
+ for i in range(0,32):
+ # Ignore any zero bits.
+ if user_id_bits[i] == '0':
+ continue
+
+ coords = mask_rev[i]
+ xum = coords[0]
+ yum = coords[1]
+
+ # Contact is 0.17 x 0.17, so add and subtract 0.085 to get
+ # the corner positions.
+
+ xllum = xum - 0.085
+ yllum = yum - 0.085
+ xurum = xum + 0.085
+ yurum = yum + 0.085
+
+ # Get the 4-byte hex values for the corner coordinates
+ xllnm = round(xllum * 1000)
+ yllnm = round(yllum * 1000)
+ xllhex = '{0:08x}'.format(xllnm)
+ yllhex = '{0:08x}'.format(yllnm)
+ xurnm = round(xurum * 1000)
+ yurnm = round(yurum * 1000)
+ xurhex = '{0:08x}'.format(xurnm)
+ yurhex = '{0:08x}'.format(yurnm)
+
+ # Magic's GDS output for vias always starts at the lower left
+ # corner and goes counterclockwise, repeating the first point.
+ viaoldposdata = viarec + xllhex + yllhex + xurhex + yllhex
+ viaoldposdata += xurhex + yurhex + xllhex + yurhex + xllhex + yllhex
+
+ # For "one" bits, the X position is moved 0.92 microns to the left
+ newxllum = xllum - 0.92
+ newxurum = xurum - 0.92
+
+ # Get the 4-byte hex values for the new corner coordinates
+ newxllnm = round(newxllum * 1000)
+ newxllhex = '{0:08x}'.format(newxllnm)
+ newxurnm = round(newxurum * 1000)
+ newxurhex = '{0:08x}'.format(newxurnm)
+
+ vianewposdata = viarec + newxllhex + yllhex + newxurhex + yllhex
+ vianewposdata += newxurhex + yurhex + newxllhex + yurhex + newxllhex + yllhex
+
+ # Diagnostic
+ if debugmode:
+ print('Bit ' + str(i) + ':')
+ print('Via position ({0:3.2f}, {1:3.2f}) to ({2:3.2f}, {3:3.2f})'.format(xllum, yllum, xurum, yurum))
+ print('Old hex string = ' + viaoldposdata)
+ print('New hex string = ' + vianewposdata)
+
+ # Convert hex strings to byte arrays
+ viaoldbytedata = bytearray.fromhex(viaoldposdata)
+ vianewbytedata = bytearray.fromhex(vianewposdata)
+
+ # Replace the old data with the new
+ if viaoldbytedata not in gdsdata:
+ print('Error: via not found for bit position ' + str(i))
+ errors += 1
+ else:
+ gdsdata = gdsdata.replace(viaoldbytedata, vianewbytedata)
+
+ if errors == 0:
+ # Keep a copy of the original
+ if not os.path.isfile(gdsbak):
+ os.rename(gdsfile, gdsbak)
+
+ with open(gdsfile, 'wb') as ofile:
+ ofile.write(gdsdata)
+
+ print('Done!')
+
+ else:
+ print('There were errors in processing. No file written.')
+ print('Ending process.')
+ sys.exit(1)
+
+ print('Step 2: Add user project ID parameter to verilog.')
+
+ changed = False
+ with open(vpath + '/rtl/caravel.v', 'r') as ifile:
+ vlines = ifile.read().splitlines()
+ outlines = []
+ for line in vlines:
+ oline = re.sub("parameter USER_PROJECT_ID = 32'h[0-9A-F]+;",
+ "parameter USER_PROJECT_ID = 32'h" + user_id_value + ";",
+ line)
+ if oline != line:
+ changed = True
+ outlines.append(oline)
+
+ if changed:
+ with open(vpath + '/rtl/caravel.v', 'w') as ofile:
+ for line in outlines:
+ print(line, file=ofile)
+ print('Done!')
+ else:
+ print('Error: No substitutions done on verilog/rtl/caravel.v.')
+ print('Ending process.')
+ sys.exit(1)
+
+ print('Step 3: Add user project ID text to top level layout.')
+
+ with open(magpath + '/user_id_textblock.mag', 'r') as ifile:
+ maglines = ifile.read().splitlines()
+ outlines = []
+ digit = 0
+ for line in maglines:
+ if 'alphaX_' in line:
+ dchar = user_id_value[digit].upper()
+ oline = re.sub('alpha_[0-9A-F]', 'alpha_' + dchar, line)
+ outlines.append(oline)
+ digit += 1
+ else:
+ outlines.append(line)
+
+ if digit == 8:
+ with open(magpath + '/user_id_textblock.mag', 'w') as ofile:
+ for line in outlines:
+ print(line, file=ofile)
+ print('Done!')
+ elif digit == 0:
+ print('Error: No digits were replaced in the layout.')
+ else:
+ print('Error: Only ' + str(digit) + ' digits were replaced in the layout.')
+
+ sys.exit(0)
diff --git a/caravel/spi/lvs/caravan.spice b/caravel/spi/lvs/caravan.spice
new file mode 100644
index 0000000..57b9c7d
--- /dev/null
+++ b/caravel/spi/lvs/caravan.spice
@@ -0,0 +1,1818 @@
+* NGSPICE file created from caravan.ext - technology: sky130A
+
+* Black-box entry subcircuit for gpio_control_block abstract view
+.subckt gpio_control_block mgmt_gpio_in mgmt_gpio_oeb mgmt_gpio_out one pad_gpio_ana_en
++ pad_gpio_ana_pol pad_gpio_ana_sel pad_gpio_dm[0] pad_gpio_dm[1] pad_gpio_dm[2] pad_gpio_holdover
++ pad_gpio_ib_mode_sel pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel
++ pad_gpio_vtrip_sel resetn resetn_out serial_clock serial_clock_out serial_data_in
++ serial_data_out user_gpio_in user_gpio_oeb user_gpio_out zero vccd vssd vccd1 vssd1
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_20um abstract view
+.subckt sky130_ef_io__com_bus_slice_20um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__gpiov2_pad_wrapped abstract view
+.subckt sky130_ef_io__gpiov2_pad_wrapped IN_H PAD_A_NOESD_H PAD_A_ESD_0_H PAD_A_ESD_1_H
++ PAD DM[2] DM[1] DM[0] HLD_H_N IN INP_DIS IB_MODE_SEL ENABLE_H ENABLE_VDDA_H ENABLE_INP_H
++ OE_N TIE_HI_ESD TIE_LO_ESD SLOW VTRIP_SEL HLD_OVR ANALOG_EN ANALOG_SEL ENABLE_VDDIO
++ ENABLE_VSWITCH_H ANALOG_POL OUT AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q VCCHIB
++ VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_1um abstract view
+.subckt sky130_ef_io__com_bus_slice_1um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_10um abstract view
+.subckt sky130_ef_io__com_bus_slice_10um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vccd_lvc_clamped_pad abstract view
+.subckt sky130_ef_io__vccd_lvc_clamped_pad AMUXBUS_A AMUXBUS_B VCCD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_5um abstract view
+.subckt sky130_ef_io__com_bus_slice_5um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__analog_pad abstract view
+.subckt sky130_ef_io__analog_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO
++ VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__disconnect_vdda_slice_5um abstract view
+.subckt sky130_ef_io__disconnect_vdda_slice_5um AMUXBUS_A AMUXBUS_B VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__corner_pad abstract view
+.subckt sky130_ef_io__corner_pad AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q VCCHIB
++ VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vddio_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vddio_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VDDIO_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssio_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vssio_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VSSIO_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um abstract view
+.subckt sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um AMUXBUS_A AMUXBUS_B
++ VSSA VDDA VDDIO_Q VDDIO VCCD VSSIO VSSD VSSIO_Q VSWITCH VCCHIB
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vdda_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vdda_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VDDA_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__top_power_hvc abstract view
+.subckt sky130_ef_io__top_power_hvc AMUXBUS_A AMUXBUS_B DRN_HVC P_CORE P_PAD SRC_BDY_HVC
++ VSSA VDDA VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vccd_lvc_clamped2_pad abstract view
+.subckt sky130_ef_io__vccd_lvc_clamped2_pad AMUXBUS_A AMUXBUS_B VCCD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssa_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vssa_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VSSA_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__disconnect_vccd_slice_5um abstract view
+.subckt sky130_ef_io__disconnect_vccd_slice_5um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH
++ VDDIO_Q VCCHIB VDDIO VSSIO VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_fd_io__top_xres4v2 abstract view
+.subckt sky130_fd_io__top_xres4v2 PAD_A_ESD_H XRES_H_N FILT_IN_H ENABLE_VDDIO TIE_WEAK_HI_H
++ ENABLE_H PULLUP_H EN_VDDIO_SIG_H TIE_LO_ESD TIE_HI_ESD DISABLE_PULLUP_H INP_SEL_H
++ VSSIO VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO VSWITCH VDDA VCCD VCCHIB VSSIO_Q
++ PAD
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssd_lvc_clamped2_pad abstract view
+.subckt sky130_ef_io__vssd_lvc_clamped2_pad AMUXBUS_A AMUXBUS_B VSSD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssd_lvc_clamped_pad abstract view
+.subckt sky130_ef_io__vssd_lvc_clamped_pad AMUXBUS_A AMUXBUS_B VSSD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for chip_io_alt abstract view
+.subckt chip_io_alt clock clock_core por flash_clk flash_csb flash_io0 flash_io0_di_core
++ flash_io0_do_core flash_io0_ieb_core flash_io0_oeb_core flash_io1 flash_io1_di_core
++ flash_io1_do_core flash_io1_ieb_core flash_io1_oeb_core gpio gpio_in_core gpio_inenb_core
++ gpio_mode0_core gpio_mode1_core gpio_out_core gpio_outenb_core vccd_pad vdda_pad
++ vddio_pad vddio_pad2 vssa_pad vssd_pad vssio_pad vssio_pad2 mprj_io[0] mprj_io_analog_en[0]
++ mprj_io_analog_pol[0] mprj_io_analog_sel[0] mprj_io_dm[0] mprj_io_dm[1] mprj_io_dm[2]
++ mprj_io_holdover[0] mprj_io_ib_mode_sel[0] mprj_io_inp_dis[0] mprj_io_oeb[0] mprj_io_out[0]
++ mprj_io_slow_sel[0] mprj_io_vtrip_sel[0] mprj_io_in[0] mprj_io_in_3v3[0] mprj_gpio_analog[3]
++ mprj_gpio_noesd[3] mprj_io[10] mprj_io_analog_en[10] mprj_io_analog_pol[10] mprj_io_analog_sel[10]
++ mprj_io_dm[30] mprj_io_dm[31] mprj_io_dm[32] mprj_io_holdover[10] mprj_io_ib_mode_sel[10]
++ mprj_io_inp_dis[10] mprj_io_oeb[10] mprj_io_out[10] mprj_io_slow_sel[10] mprj_io_vtrip_sel[10]
++ mprj_io_in[10] mprj_io_in_3v3[10] mprj_gpio_analog[4] mprj_gpio_noesd[4] mprj_io[11]
++ mprj_io_analog_en[11] mprj_io_analog_pol[11] mprj_io_analog_sel[11] mprj_io_dm[33]
++ mprj_io_dm[34] mprj_io_dm[35] mprj_io_holdover[11] mprj_io_ib_mode_sel[11] mprj_io_inp_dis[11]
++ mprj_io_oeb[11] mprj_io_out[11] mprj_io_slow_sel[11] mprj_io_vtrip_sel[11] mprj_io_in[11]
++ mprj_io_in_3v3[11] mprj_gpio_analog[5] mprj_gpio_noesd[5] mprj_io[12] mprj_io_analog_en[12]
++ mprj_io_analog_pol[12] mprj_io_analog_sel[12] mprj_io_dm[36] mprj_io_dm[37] mprj_io_dm[38]
++ mprj_io_holdover[12] mprj_io_ib_mode_sel[12] mprj_io_inp_dis[12] mprj_io_oeb[12]
++ mprj_io_out[12] mprj_io_slow_sel[12] mprj_io_vtrip_sel[12] mprj_io_in[12] mprj_io_in_3v3[12]
++ mprj_gpio_analog[6] mprj_gpio_noesd[6] mprj_io[13] mprj_io_analog_en[13] mprj_io_analog_pol[13]
++ mprj_io_analog_sel[13] mprj_io_dm[39] mprj_io_dm[40] mprj_io_dm[41] mprj_io_holdover[13]
++ mprj_io_ib_mode_sel[13] mprj_io_inp_dis[13] mprj_io_oeb[13] mprj_io_out[13] mprj_io_slow_sel[13]
++ mprj_io_vtrip_sel[13] mprj_io_in[13] mprj_io_in_3v3[13] mprj_io[1] mprj_io_analog_en[1]
++ mprj_io_analog_pol[1] mprj_io_analog_sel[1] mprj_io_dm[3] mprj_io_dm[4] mprj_io_dm[5]
++ mprj_io_holdover[1] mprj_io_ib_mode_sel[1] mprj_io_inp_dis[1] mprj_io_oeb[1] mprj_io_out[1]
++ mprj_io_slow_sel[1] mprj_io_vtrip_sel[1] mprj_io_in[1] mprj_io_in_3v3[1] mprj_io[2]
++ mprj_io_analog_en[2] mprj_io_analog_pol[2] mprj_io_analog_sel[2] mprj_io_dm[6] mprj_io_dm[7]
++ mprj_io_dm[8] mprj_io_holdover[2] mprj_io_ib_mode_sel[2] mprj_io_inp_dis[2] mprj_io_oeb[2]
++ mprj_io_out[2] mprj_io_slow_sel[2] mprj_io_vtrip_sel[2] mprj_io_in[2] mprj_io_in_3v3[2]
++ mprj_io[3] mprj_io_analog_en[3] mprj_io_analog_pol[3] mprj_io_analog_sel[3] mprj_io_dm[10]
++ mprj_io_dm[11] mprj_io_dm[9] mprj_io_holdover[3] mprj_io_ib_mode_sel[3] mprj_io_inp_dis[3]
++ mprj_io_oeb[3] mprj_io_out[3] mprj_io_slow_sel[3] mprj_io_vtrip_sel[3] mprj_io_in[3]
++ mprj_io_in_3v3[3] mprj_io[4] mprj_io_analog_en[4] mprj_io_analog_pol[4] mprj_io_analog_sel[4]
++ mprj_io_dm[12] mprj_io_dm[13] mprj_io_dm[14] mprj_io_holdover[4] mprj_io_ib_mode_sel[4]
++ mprj_io_inp_dis[4] mprj_io_oeb[4] mprj_io_out[4] mprj_io_slow_sel[4] mprj_io_vtrip_sel[4]
++ mprj_io_in[4] mprj_io_in_3v3[4] mprj_io[5] mprj_io_analog_en[5] mprj_io_analog_pol[5]
++ mprj_io_analog_sel[5] mprj_io_dm[15] mprj_io_dm[16] mprj_io_dm[17] mprj_io_holdover[5]
++ mprj_io_ib_mode_sel[5] mprj_io_inp_dis[5] mprj_io_oeb[5] mprj_io_out[5] mprj_io_slow_sel[5]
++ mprj_io_vtrip_sel[5] mprj_io_in[5] mprj_io_in_3v3[5] mprj_io[6] mprj_io_analog_en[6]
++ mprj_io_analog_pol[6] mprj_io_analog_sel[6] mprj_io_dm[18] mprj_io_dm[19] mprj_io_dm[20]
++ mprj_io_holdover[6] mprj_io_ib_mode_sel[6] mprj_io_inp_dis[6] mprj_io_oeb[6] mprj_io_out[6]
++ mprj_io_slow_sel[6] mprj_io_vtrip_sel[6] mprj_io_in[6] mprj_io_in_3v3[6] mprj_gpio_analog[0]
++ mprj_gpio_noesd[0] mprj_io[7] mprj_io_analog_en[7] mprj_io_analog_pol[7] mprj_io_analog_sel[7]
++ mprj_io_dm[21] mprj_io_dm[22] mprj_io_dm[23] mprj_io_holdover[7] mprj_io_ib_mode_sel[7]
++ mprj_io_inp_dis[7] mprj_io_oeb[7] mprj_io_out[7] mprj_io_slow_sel[7] mprj_io_vtrip_sel[7]
++ mprj_io_in[7] mprj_io_in_3v3[7] mprj_gpio_analog[1] mprj_gpio_noesd[1] mprj_io[8]
++ mprj_io_analog_en[8] mprj_io_analog_pol[8] mprj_io_analog_sel[8] mprj_io_dm[24]
++ mprj_io_dm[25] mprj_io_dm[26] mprj_io_holdover[8] mprj_io_ib_mode_sel[8] mprj_io_inp_dis[8]
++ mprj_io_oeb[8] mprj_io_out[8] mprj_io_slow_sel[8] mprj_io_vtrip_sel[8] mprj_io_in[8]
++ mprj_io_in_3v3[8] mprj_gpio_analog[2] mprj_gpio_noesd[2] mprj_io[9] mprj_io_analog_en[9]
++ mprj_io_analog_pol[9] mprj_io_analog_sel[9] mprj_io_dm[27] mprj_io_dm[28] mprj_io_dm[29]
++ mprj_io_holdover[9] mprj_io_ib_mode_sel[9] mprj_io_inp_dis[9] mprj_io_oeb[9] mprj_io_out[9]
++ mprj_io_slow_sel[9] mprj_io_vtrip_sel[9] mprj_io_in[9] mprj_io_in_3v3[9] mprj_gpio_analog[7]
++ mprj_gpio_noesd[7] mprj_io[25] mprj_io_analog_en[14] mprj_io_analog_pol[14] mprj_io_analog_sel[14]
++ mprj_io_dm[42] mprj_io_dm[43] mprj_io_dm[44] mprj_io_holdover[14] mprj_io_ib_mode_sel[14]
++ mprj_io_inp_dis[14] mprj_io_oeb[14] mprj_io_out[14] mprj_io_slow_sel[14] mprj_io_vtrip_sel[14]
++ mprj_io_in[14] mprj_io_in_3v3[14] mprj_gpio_analog[17] mprj_gpio_noesd[17] mprj_io[35]
++ mprj_io_analog_en[24] mprj_io_analog_pol[24] mprj_io_analog_sel[24] mprj_io_dm[72]
++ mprj_io_dm[73] mprj_io_dm[74] mprj_io_holdover[24] mprj_io_ib_mode_sel[24] mprj_io_inp_dis[24]
++ mprj_io_oeb[24] mprj_io_out[24] mprj_io_slow_sel[24] mprj_io_vtrip_sel[24] mprj_io_in[24]
++ mprj_io_in_3v3[24] mprj_io[36] mprj_io_analog_en[25] mprj_io_analog_pol[25] mprj_io_analog_sel[25]
++ mprj_io_dm[75] mprj_io_dm[76] mprj_io_dm[77] mprj_io_holdover[25] mprj_io_ib_mode_sel[25]
++ mprj_io_inp_dis[25] mprj_io_oeb[25] mprj_io_out[25] mprj_io_slow_sel[25] mprj_io_vtrip_sel[25]
++ mprj_io_in[25] mprj_io_in_3v3[25] mprj_io[37] mprj_io_analog_en[26] mprj_io_analog_pol[26]
++ mprj_io_analog_sel[26] mprj_io_dm[78] mprj_io_dm[79] mprj_io_dm[80] mprj_io_holdover[26]
++ mprj_io_ib_mode_sel[26] mprj_io_inp_dis[26] mprj_io_oeb[26] mprj_io_out[26] mprj_io_slow_sel[26]
++ mprj_io_vtrip_sel[26] mprj_io_in[26] mprj_io_in_3v3[26] mprj_gpio_analog[8] mprj_gpio_noesd[8]
++ mprj_io[26] mprj_io_analog_en[15] mprj_io_analog_pol[15] mprj_io_analog_sel[15]
++ mprj_io_dm[45] mprj_io_dm[46] mprj_io_dm[47] mprj_io_holdover[15] mprj_io_ib_mode_sel[15]
++ mprj_io_inp_dis[15] mprj_io_oeb[15] mprj_io_out[15] mprj_io_slow_sel[15] mprj_io_vtrip_sel[15]
++ mprj_io_in[15] mprj_io_in_3v3[15] mprj_gpio_analog[9] mprj_gpio_noesd[9] mprj_io[27]
++ mprj_io_analog_en[16] mprj_io_analog_pol[16] mprj_io_analog_sel[16] mprj_io_dm[48]
++ mprj_io_dm[49] mprj_io_dm[50] mprj_io_holdover[16] mprj_io_ib_mode_sel[16] mprj_io_inp_dis[16]
++ mprj_io_oeb[16] mprj_io_out[16] mprj_io_slow_sel[16] mprj_io_vtrip_sel[16] mprj_io_in[16]
++ mprj_io_in_3v3[16] mprj_gpio_analog[10] mprj_gpio_noesd[10] mprj_io[28] mprj_io_analog_en[17]
++ mprj_io_analog_pol[17] mprj_io_analog_sel[17] mprj_io_dm[51] mprj_io_dm[52] mprj_io_dm[53]
++ mprj_io_holdover[17] mprj_io_ib_mode_sel[17] mprj_io_inp_dis[17] mprj_io_oeb[17]
++ mprj_io_out[17] mprj_io_slow_sel[17] mprj_io_vtrip_sel[17] mprj_io_in[17] mprj_io_in_3v3[17]
++ mprj_gpio_analog[11] mprj_gpio_noesd[11] mprj_io[29] mprj_io_analog_en[18] mprj_io_analog_pol[18]
++ mprj_io_analog_sel[18] mprj_io_dm[54] mprj_io_dm[55] mprj_io_dm[56] mprj_io_holdover[18]
++ mprj_io_ib_mode_sel[18] mprj_io_inp_dis[18] mprj_io_oeb[18] mprj_io_out[18] mprj_io_slow_sel[18]
++ mprj_io_vtrip_sel[18] mprj_io_in[18] mprj_io_in_3v3[18] mprj_gpio_analog[12] mprj_gpio_noesd[12]
++ mprj_io[30] mprj_io_analog_en[19] mprj_io_analog_pol[19] mprj_io_analog_sel[19]
++ mprj_io_dm[57] mprj_io_dm[58] mprj_io_dm[59] mprj_io_holdover[19] mprj_io_ib_mode_sel[19]
++ mprj_io_inp_dis[19] mprj_io_oeb[19] mprj_io_out[19] mprj_io_slow_sel[19] mprj_io_vtrip_sel[19]
++ mprj_io_in[19] mprj_io_in_3v3[19] mprj_gpio_analog[13] mprj_gpio_noesd[13] mprj_io[31]
++ mprj_io_analog_en[20] mprj_io_analog_pol[20] mprj_io_analog_sel[20] mprj_io_dm[60]
++ mprj_io_dm[61] mprj_io_dm[62] mprj_io_holdover[20] mprj_io_ib_mode_sel[20] mprj_io_inp_dis[20]
++ mprj_io_oeb[20] mprj_io_out[20] mprj_io_slow_sel[20] mprj_io_vtrip_sel[20] mprj_io_in[20]
++ mprj_io_in_3v3[20] mprj_gpio_analog[14] mprj_gpio_noesd[14] mprj_io[32] mprj_io_analog_en[21]
++ mprj_io_analog_pol[21] mprj_io_analog_sel[21] mprj_io_dm[63] mprj_io_dm[64] mprj_io_dm[65]
++ mprj_io_holdover[21] mprj_io_ib_mode_sel[21] mprj_io_inp_dis[21] mprj_io_oeb[21]
++ mprj_io_out[21] mprj_io_slow_sel[21] mprj_io_vtrip_sel[21] mprj_io_in[21] mprj_io_in_3v3[21]
++ mprj_gpio_analog[15] mprj_gpio_noesd[15] mprj_io[33] mprj_io_analog_en[22] mprj_io_analog_pol[22]
++ mprj_io_analog_sel[22] mprj_io_dm[66] mprj_io_dm[67] mprj_io_dm[68] mprj_io_holdover[22]
++ mprj_io_ib_mode_sel[22] mprj_io_inp_dis[22] mprj_io_oeb[22] mprj_io_out[22] mprj_io_slow_sel[22]
++ mprj_io_vtrip_sel[22] mprj_io_in[22] mprj_io_in_3v3[22] mprj_gpio_analog[16] mprj_gpio_noesd[16]
++ mprj_io[34] mprj_io_analog_en[23] mprj_io_analog_pol[23] mprj_io_analog_sel[23]
++ mprj_io_dm[69] mprj_io_dm[70] mprj_io_dm[71] mprj_io_holdover[23] mprj_io_ib_mode_sel[23]
++ mprj_io_inp_dis[23] mprj_io_oeb[23] mprj_io_out[23] mprj_io_slow_sel[23] mprj_io_vtrip_sel[23]
++ mprj_io_in[23] mprj_io_in_3v3[23] porb_h resetb resetb_core_h vdda vssa vssd mprj_analog[0]
++ mprj_io[15] mprj_analog[1] mprj_io[16] mprj_analog[2] mprj_io[17] mprj_analog[3]
++ mprj_io[14] mprj_analog[4] mprj_clamp_high[0] mprj_clamp_low[0] mprj_io[18] vccd1_pad
++ vdda1_pad vdda1_pad2 vssa1_pad vssa1_pad2 vccd1 vdda1 vssa1 vssd1 vssd1_pad mprj_analog[7]
++ mprj_io[21] mprj_analog[8] mprj_io[22] mprj_analog[9] mprj_io[23] mprj_analog[10]
++ mprj_io[24] mprj_analog[5] mprj_clamp_high[1] mprj_clamp_low[1] mprj_io[19] mprj_analog[6]
++ mprj_clamp_high[2] mprj_clamp_low[2] mprj_io[20] vccd2_pad vdda2_pad vssa2_pad vccd
++ vccd2 vdda2 vddio vssa2 vssd2 vssd2_pad vssio flash_csb_core flash_clk_ieb_core
++ flash_clk_oeb_core flash_clk_core flash_csb_oeb_core flash_csb_ieb_core
+.ends
+
+* Black-box entry subcircuit for mgmt_core abstract view
+.subckt mgmt_core clock core_clk core_rstn flash_clk flash_clk_ieb flash_clk_oeb flash_csb
++ flash_csb_ieb flash_csb_oeb flash_io0_di flash_io0_do flash_io0_ieb flash_io0_oeb
++ flash_io1_di flash_io1_do flash_io1_ieb flash_io1_oeb flash_io2_oeb flash_io3_oeb
++ gpio_in_pad gpio_inenb_pad gpio_mode0_pad gpio_mode1_pad gpio_out_pad gpio_outenb_pad
++ jtag_out jtag_outenb la_iena[0] la_iena[100] la_iena[101] la_iena[102] la_iena[103]
++ la_iena[104] la_iena[105] la_iena[106] la_iena[107] la_iena[108] la_iena[109] la_iena[10]
++ la_iena[110] la_iena[111] la_iena[112] la_iena[113] la_iena[114] la_iena[115] la_iena[116]
++ la_iena[117] la_iena[118] la_iena[119] la_iena[11] la_iena[120] la_iena[121] la_iena[122]
++ la_iena[123] la_iena[124] la_iena[125] la_iena[126] la_iena[127] la_iena[12] la_iena[13]
++ la_iena[14] la_iena[15] la_iena[16] la_iena[17] la_iena[18] la_iena[19] la_iena[1]
++ la_iena[20] la_iena[21] la_iena[22] la_iena[23] la_iena[24] la_iena[25] la_iena[26]
++ la_iena[27] la_iena[28] la_iena[29] la_iena[2] la_iena[30] la_iena[31] la_iena[32]
++ la_iena[33] la_iena[34] la_iena[35] la_iena[36] la_iena[37] la_iena[38] la_iena[39]
++ la_iena[3] la_iena[40] la_iena[41] la_iena[42] la_iena[43] la_iena[44] la_iena[45]
++ la_iena[46] la_iena[47] la_iena[48] la_iena[49] la_iena[4] la_iena[50] la_iena[51]
++ la_iena[52] la_iena[53] la_iena[54] la_iena[55] la_iena[56] la_iena[57] la_iena[58]
++ la_iena[59] la_iena[5] la_iena[60] la_iena[61] la_iena[62] la_iena[63] la_iena[64]
++ la_iena[65] la_iena[66] la_iena[67] la_iena[68] la_iena[69] la_iena[6] la_iena[70]
++ la_iena[71] la_iena[72] la_iena[73] la_iena[74] la_iena[75] la_iena[76] la_iena[77]
++ la_iena[78] la_iena[79] la_iena[7] la_iena[80] la_iena[81] la_iena[82] la_iena[83]
++ la_iena[84] la_iena[85] la_iena[86] la_iena[87] la_iena[88] la_iena[89] la_iena[8]
++ la_iena[90] la_iena[91] la_iena[92] la_iena[93] la_iena[94] la_iena[95] la_iena[96]
++ la_iena[97] la_iena[98] la_iena[99] la_iena[9] la_input[0] la_input[100] la_input[101]
++ la_input[102] la_input[103] la_input[104] la_input[105] la_input[106] la_input[107]
++ la_input[108] la_input[109] la_input[10] la_input[110] la_input[111] la_input[112]
++ la_input[113] la_input[114] la_input[115] la_input[116] la_input[117] la_input[118]
++ la_input[119] la_input[11] la_input[120] la_input[121] la_input[122] la_input[123]
++ la_input[124] la_input[125] la_input[126] la_input[127] la_input[12] la_input[13]
++ la_input[14] la_input[15] la_input[16] la_input[17] la_input[18] la_input[19] la_input[1]
++ la_input[20] la_input[21] la_input[22] la_input[23] la_input[24] la_input[25] la_input[26]
++ la_input[27] la_input[28] la_input[29] la_input[2] la_input[30] la_input[31] la_input[32]
++ la_input[33] la_input[34] la_input[35] la_input[36] la_input[37] la_input[38] la_input[39]
++ la_input[3] la_input[40] la_input[41] la_input[42] la_input[43] la_input[44] la_input[45]
++ la_input[46] la_input[47] la_input[48] la_input[49] la_input[4] la_input[50] la_input[51]
++ la_input[52] la_input[53] la_input[54] la_input[55] la_input[56] la_input[57] la_input[58]
++ la_input[59] la_input[5] la_input[60] la_input[61] la_input[62] la_input[63] la_input[64]
++ la_input[65] la_input[66] la_input[67] la_input[68] la_input[69] la_input[6] la_input[70]
++ la_input[71] la_input[72] la_input[73] la_input[74] la_input[75] la_input[76] la_input[77]
++ la_input[78] la_input[79] la_input[7] la_input[80] la_input[81] la_input[82] la_input[83]
++ la_input[84] la_input[85] la_input[86] la_input[87] la_input[88] la_input[89] la_input[8]
++ la_input[90] la_input[91] la_input[92] la_input[93] la_input[94] la_input[95] la_input[96]
++ la_input[97] la_input[98] la_input[99] la_input[9] la_oenb[0] la_oenb[100] la_oenb[101]
++ la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108]
++ la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114]
++ la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120]
++ la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127]
++ la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18]
++ la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24]
++ la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30]
++ la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37]
++ la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43]
++ la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4]
++ la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56]
++ la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62]
++ la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69]
++ la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75]
++ la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81]
++ la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88]
++ la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94]
++ la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] la_output[0]
++ la_output[100] la_output[101] la_output[102] la_output[103] la_output[104] la_output[105]
++ la_output[106] la_output[107] la_output[108] la_output[109] la_output[10] la_output[110]
++ la_output[111] la_output[112] la_output[113] la_output[114] la_output[115] la_output[116]
++ la_output[117] la_output[118] la_output[119] la_output[11] la_output[120] la_output[121]
++ la_output[122] la_output[123] la_output[124] la_output[125] la_output[126] la_output[127]
++ la_output[12] la_output[13] la_output[14] la_output[15] la_output[16] la_output[17]
++ la_output[18] la_output[19] la_output[1] la_output[20] la_output[21] la_output[22]
++ la_output[23] la_output[24] la_output[25] la_output[26] la_output[27] la_output[28]
++ la_output[29] la_output[2] la_output[30] la_output[31] la_output[32] la_output[33]
++ la_output[34] la_output[35] la_output[36] la_output[37] la_output[38] la_output[39]
++ la_output[3] la_output[40] la_output[41] la_output[42] la_output[43] la_output[44]
++ la_output[45] la_output[46] la_output[47] la_output[48] la_output[49] la_output[4]
++ la_output[50] la_output[51] la_output[52] la_output[53] la_output[54] la_output[55]
++ la_output[56] la_output[57] la_output[58] la_output[59] la_output[5] la_output[60]
++ la_output[61] la_output[62] la_output[63] la_output[64] la_output[65] la_output[66]
++ la_output[67] la_output[68] la_output[69] la_output[6] la_output[70] la_output[71]
++ la_output[72] la_output[73] la_output[74] la_output[75] la_output[76] la_output[77]
++ la_output[78] la_output[79] la_output[7] la_output[80] la_output[81] la_output[82]
++ la_output[83] la_output[84] la_output[85] la_output[86] la_output[87] la_output[88]
++ la_output[89] la_output[8] la_output[90] la_output[91] la_output[92] la_output[93]
++ la_output[94] la_output[95] la_output[96] la_output[97] la_output[98] la_output[99]
++ la_output[9] mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13] mask_rev[14]
++ mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1] mask_rev[20]
++ mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26] mask_rev[27]
++ mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3] mask_rev[4]
++ mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] mgmt_addr[0] mgmt_addr[1]
++ mgmt_addr[2] mgmt_addr[3] mgmt_addr[4] mgmt_addr[5] mgmt_addr[6] mgmt_addr[7] mgmt_addr_ro[0]
++ mgmt_addr_ro[1] mgmt_addr_ro[2] mgmt_addr_ro[3] mgmt_addr_ro[4] mgmt_addr_ro[5]
++ mgmt_addr_ro[6] mgmt_addr_ro[7] mgmt_ena[0] mgmt_ena[1] mgmt_ena_ro mgmt_in_data[0]
++ mgmt_in_data[10] mgmt_in_data[11] mgmt_in_data[12] mgmt_in_data[13] mgmt_in_data[14]
++ mgmt_in_data[15] mgmt_in_data[16] mgmt_in_data[17] mgmt_in_data[18] mgmt_in_data[19]
++ mgmt_in_data[1] mgmt_in_data[20] mgmt_in_data[21] mgmt_in_data[22] mgmt_in_data[23]
++ mgmt_in_data[24] mgmt_in_data[25] mgmt_in_data[26] mgmt_in_data[27] mgmt_in_data[28]
++ mgmt_in_data[29] mgmt_in_data[2] mgmt_in_data[30] mgmt_in_data[31] mgmt_in_data[32]
++ mgmt_in_data[33] mgmt_in_data[34] mgmt_in_data[35] mgmt_in_data[36] mgmt_in_data[37]
++ mgmt_in_data[3] mgmt_in_data[4] mgmt_in_data[5] mgmt_in_data[6] mgmt_in_data[7]
++ mgmt_in_data[8] mgmt_in_data[9] mgmt_out_data[0] mgmt_out_data[10] mgmt_out_data[11]
++ mgmt_out_data[12] mgmt_out_data[13] mgmt_out_data[14] mgmt_out_data[15] mgmt_out_data[16]
++ mgmt_out_data[17] mgmt_out_data[18] mgmt_out_data[19] mgmt_out_data[1] mgmt_out_data[20]
++ mgmt_out_data[21] mgmt_out_data[22] mgmt_out_data[23] mgmt_out_data[24] mgmt_out_data[25]
++ mgmt_out_data[26] mgmt_out_data[27] mgmt_out_data[28] mgmt_out_data[29] mgmt_out_data[2]
++ mgmt_out_data[30] mgmt_out_data[31] mgmt_out_data[32] mgmt_out_data[33] mgmt_out_data[34]
++ mgmt_out_data[35] mgmt_out_data[36] mgmt_out_data[37] mgmt_out_data[3] mgmt_out_data[4]
++ mgmt_out_data[5] mgmt_out_data[6] mgmt_out_data[7] mgmt_out_data[8] mgmt_out_data[9]
++ mgmt_rdata[0] mgmt_rdata[10] mgmt_rdata[11] mgmt_rdata[12] mgmt_rdata[13] mgmt_rdata[14]
++ mgmt_rdata[15] mgmt_rdata[16] mgmt_rdata[17] mgmt_rdata[18] mgmt_rdata[19] mgmt_rdata[1]
++ mgmt_rdata[20] mgmt_rdata[21] mgmt_rdata[22] mgmt_rdata[23] mgmt_rdata[24] mgmt_rdata[25]
++ mgmt_rdata[26] mgmt_rdata[27] mgmt_rdata[28] mgmt_rdata[29] mgmt_rdata[2] mgmt_rdata[30]
++ mgmt_rdata[31] mgmt_rdata[32] mgmt_rdata[33] mgmt_rdata[34] mgmt_rdata[35] mgmt_rdata[36]
++ mgmt_rdata[37] mgmt_rdata[38] mgmt_rdata[39] mgmt_rdata[3] mgmt_rdata[40] mgmt_rdata[41]
++ mgmt_rdata[42] mgmt_rdata[43] mgmt_rdata[44] mgmt_rdata[45] mgmt_rdata[46] mgmt_rdata[47]
++ mgmt_rdata[48] mgmt_rdata[49] mgmt_rdata[4] mgmt_rdata[50] mgmt_rdata[51] mgmt_rdata[52]
++ mgmt_rdata[53] mgmt_rdata[54] mgmt_rdata[55] mgmt_rdata[56] mgmt_rdata[57] mgmt_rdata[58]
++ mgmt_rdata[59] mgmt_rdata[5] mgmt_rdata[60] mgmt_rdata[61] mgmt_rdata[62] mgmt_rdata[63]
++ mgmt_rdata[6] mgmt_rdata[7] mgmt_rdata[8] mgmt_rdata[9] mgmt_rdata_ro[0] mgmt_rdata_ro[10]
++ mgmt_rdata_ro[11] mgmt_rdata_ro[12] mgmt_rdata_ro[13] mgmt_rdata_ro[14] mgmt_rdata_ro[15]
++ mgmt_rdata_ro[16] mgmt_rdata_ro[17] mgmt_rdata_ro[18] mgmt_rdata_ro[19] mgmt_rdata_ro[1]
++ mgmt_rdata_ro[20] mgmt_rdata_ro[21] mgmt_rdata_ro[22] mgmt_rdata_ro[23] mgmt_rdata_ro[24]
++ mgmt_rdata_ro[25] mgmt_rdata_ro[26] mgmt_rdata_ro[27] mgmt_rdata_ro[28] mgmt_rdata_ro[29]
++ mgmt_rdata_ro[2] mgmt_rdata_ro[30] mgmt_rdata_ro[31] mgmt_rdata_ro[3] mgmt_rdata_ro[4]
++ mgmt_rdata_ro[5] mgmt_rdata_ro[6] mgmt_rdata_ro[7] mgmt_rdata_ro[8] mgmt_rdata_ro[9]
++ mgmt_wdata[0] mgmt_wdata[10] mgmt_wdata[11] mgmt_wdata[12] mgmt_wdata[13] mgmt_wdata[14]
++ mgmt_wdata[15] mgmt_wdata[16] mgmt_wdata[17] mgmt_wdata[18] mgmt_wdata[19] mgmt_wdata[1]
++ mgmt_wdata[20] mgmt_wdata[21] mgmt_wdata[22] mgmt_wdata[23] mgmt_wdata[24] mgmt_wdata[25]
++ mgmt_wdata[26] mgmt_wdata[27] mgmt_wdata[28] mgmt_wdata[29] mgmt_wdata[2] mgmt_wdata[30]
++ mgmt_wdata[31] mgmt_wdata[3] mgmt_wdata[4] mgmt_wdata[5] mgmt_wdata[6] mgmt_wdata[7]
++ mgmt_wdata[8] mgmt_wdata[9] mgmt_wen[0] mgmt_wen[1] mgmt_wen_mask[0] mgmt_wen_mask[1]
++ mgmt_wen_mask[2] mgmt_wen_mask[3] mgmt_wen_mask[4] mgmt_wen_mask[5] mgmt_wen_mask[6]
++ mgmt_wen_mask[7] mprj2_vcc_pwrgood mprj2_vdd_pwrgood mprj_ack_i mprj_adr_o[0] mprj_adr_o[10]
++ mprj_adr_o[11] mprj_adr_o[12] mprj_adr_o[13] mprj_adr_o[14] mprj_adr_o[15] mprj_adr_o[16]
++ mprj_adr_o[17] mprj_adr_o[18] mprj_adr_o[19] mprj_adr_o[1] mprj_adr_o[20] mprj_adr_o[21]
++ mprj_adr_o[22] mprj_adr_o[23] mprj_adr_o[24] mprj_adr_o[25] mprj_adr_o[26] mprj_adr_o[27]
++ mprj_adr_o[28] mprj_adr_o[29] mprj_adr_o[2] mprj_adr_o[30] mprj_adr_o[31] mprj_adr_o[3]
++ mprj_adr_o[4] mprj_adr_o[5] mprj_adr_o[6] mprj_adr_o[7] mprj_adr_o[8] mprj_adr_o[9]
++ mprj_cyc_o mprj_dat_i[0] mprj_dat_i[10] mprj_dat_i[11] mprj_dat_i[12] mprj_dat_i[13]
++ mprj_dat_i[14] mprj_dat_i[15] mprj_dat_i[16] mprj_dat_i[17] mprj_dat_i[18] mprj_dat_i[19]
++ mprj_dat_i[1] mprj_dat_i[20] mprj_dat_i[21] mprj_dat_i[22] mprj_dat_i[23] mprj_dat_i[24]
++ mprj_dat_i[25] mprj_dat_i[26] mprj_dat_i[27] mprj_dat_i[28] mprj_dat_i[29] mprj_dat_i[2]
++ mprj_dat_i[30] mprj_dat_i[31] mprj_dat_i[3] mprj_dat_i[4] mprj_dat_i[5] mprj_dat_i[6]
++ mprj_dat_i[7] mprj_dat_i[8] mprj_dat_i[9] mprj_dat_o[0] mprj_dat_o[10] mprj_dat_o[11]
++ mprj_dat_o[12] mprj_dat_o[13] mprj_dat_o[14] mprj_dat_o[15] mprj_dat_o[16] mprj_dat_o[17]
++ mprj_dat_o[18] mprj_dat_o[19] mprj_dat_o[1] mprj_dat_o[20] mprj_dat_o[21] mprj_dat_o[22]
++ mprj_dat_o[23] mprj_dat_o[24] mprj_dat_o[25] mprj_dat_o[26] mprj_dat_o[27] mprj_dat_o[28]
++ mprj_dat_o[29] mprj_dat_o[2] mprj_dat_o[30] mprj_dat_o[31] mprj_dat_o[3] mprj_dat_o[4]
++ mprj_dat_o[5] mprj_dat_o[6] mprj_dat_o[7] mprj_dat_o[8] mprj_dat_o[9] mprj_io_loader_clock
++ mprj_io_loader_data_1 mprj_io_loader_data_2 mprj_io_loader_resetn mprj_sel_o[0]
++ mprj_sel_o[1] mprj_sel_o[2] mprj_sel_o[3] mprj_stb_o mprj_vcc_pwrgood mprj_vdd_pwrgood
++ mprj_we_o porb pwr_ctrl_out[0] pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3] resetb
++ sdo_out sdo_outenb user_clk user_irq[0] user_irq[1] user_irq[2] user_irq_ena[0]
++ user_irq_ena[1] user_irq_ena[2] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for user_id_textblock abstract view
+.subckt user_id_textblock VSUBS
+.ends
+
+* Black-box entry subcircuit for simple_por abstract view
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+.ends
+
+* Black-box entry subcircuit for user_id_programming abstract view
+.subckt user_id_programming mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13]
++ mask_rev[14] mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1]
++ mask_rev[20] mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26]
++ mask_rev[27] mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3]
++ mask_rev[4] mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for open_source abstract view
+.subckt open_source VSUBS
+.ends
+
+* Black-box entry subcircuit for mgmt_protect abstract view
+.subckt mgmt_protect caravel_clk caravel_clk2 caravel_rstn la_data_in_core[0] la_data_in_core[100]
++ la_data_in_core[101] la_data_in_core[102] la_data_in_core[103] la_data_in_core[104]
++ la_data_in_core[105] la_data_in_core[106] la_data_in_core[107] la_data_in_core[108]
++ la_data_in_core[109] la_data_in_core[10] la_data_in_core[110] la_data_in_core[111]
++ la_data_in_core[112] la_data_in_core[113] la_data_in_core[114] la_data_in_core[115]
++ la_data_in_core[116] la_data_in_core[117] la_data_in_core[118] la_data_in_core[119]
++ la_data_in_core[11] la_data_in_core[120] la_data_in_core[121] la_data_in_core[122]
++ la_data_in_core[123] la_data_in_core[124] la_data_in_core[125] la_data_in_core[126]
++ la_data_in_core[127] la_data_in_core[12] la_data_in_core[13] la_data_in_core[14]
++ la_data_in_core[15] la_data_in_core[16] la_data_in_core[17] la_data_in_core[18]
++ la_data_in_core[19] la_data_in_core[1] la_data_in_core[20] la_data_in_core[21] la_data_in_core[22]
++ la_data_in_core[23] la_data_in_core[24] la_data_in_core[25] la_data_in_core[26]
++ la_data_in_core[27] la_data_in_core[28] la_data_in_core[29] la_data_in_core[2] la_data_in_core[30]
++ la_data_in_core[31] la_data_in_core[32] la_data_in_core[33] la_data_in_core[34]
++ la_data_in_core[35] la_data_in_core[36] la_data_in_core[37] la_data_in_core[38]
++ la_data_in_core[39] la_data_in_core[3] la_data_in_core[40] la_data_in_core[41] la_data_in_core[42]
++ la_data_in_core[43] la_data_in_core[44] la_data_in_core[45] la_data_in_core[46]
++ la_data_in_core[47] la_data_in_core[48] la_data_in_core[49] la_data_in_core[4] la_data_in_core[50]
++ la_data_in_core[51] la_data_in_core[52] la_data_in_core[53] la_data_in_core[54]
++ la_data_in_core[55] la_data_in_core[56] la_data_in_core[57] la_data_in_core[58]
++ la_data_in_core[59] la_data_in_core[5] la_data_in_core[60] la_data_in_core[61] la_data_in_core[62]
++ la_data_in_core[63] la_data_in_core[64] la_data_in_core[65] la_data_in_core[66]
++ la_data_in_core[67] la_data_in_core[68] la_data_in_core[69] la_data_in_core[6] la_data_in_core[70]
++ la_data_in_core[71] la_data_in_core[72] la_data_in_core[73] la_data_in_core[74]
++ la_data_in_core[75] la_data_in_core[76] la_data_in_core[77] la_data_in_core[78]
++ la_data_in_core[79] la_data_in_core[7] la_data_in_core[80] la_data_in_core[81] la_data_in_core[82]
++ la_data_in_core[83] la_data_in_core[84] la_data_in_core[85] la_data_in_core[86]
++ la_data_in_core[87] la_data_in_core[88] la_data_in_core[89] la_data_in_core[8] la_data_in_core[90]
++ la_data_in_core[91] la_data_in_core[92] la_data_in_core[93] la_data_in_core[94]
++ la_data_in_core[95] la_data_in_core[96] la_data_in_core[97] la_data_in_core[98]
++ la_data_in_core[99] la_data_in_core[9] la_data_in_mprj[0] la_data_in_mprj[100] la_data_in_mprj[101]
++ la_data_in_mprj[102] la_data_in_mprj[103] la_data_in_mprj[104] la_data_in_mprj[105]
++ la_data_in_mprj[106] la_data_in_mprj[107] la_data_in_mprj[108] la_data_in_mprj[109]
++ la_data_in_mprj[10] la_data_in_mprj[110] la_data_in_mprj[111] la_data_in_mprj[112]
++ la_data_in_mprj[113] la_data_in_mprj[114] la_data_in_mprj[115] la_data_in_mprj[116]
++ la_data_in_mprj[117] la_data_in_mprj[118] la_data_in_mprj[119] la_data_in_mprj[11]
++ la_data_in_mprj[120] la_data_in_mprj[121] la_data_in_mprj[122] la_data_in_mprj[123]
++ la_data_in_mprj[124] la_data_in_mprj[125] la_data_in_mprj[126] la_data_in_mprj[127]
++ la_data_in_mprj[12] la_data_in_mprj[13] la_data_in_mprj[14] la_data_in_mprj[15]
++ la_data_in_mprj[16] la_data_in_mprj[17] la_data_in_mprj[18] la_data_in_mprj[19]
++ la_data_in_mprj[1] la_data_in_mprj[20] la_data_in_mprj[21] la_data_in_mprj[22] la_data_in_mprj[23]
++ la_data_in_mprj[24] la_data_in_mprj[25] la_data_in_mprj[26] la_data_in_mprj[27]
++ la_data_in_mprj[28] la_data_in_mprj[29] la_data_in_mprj[2] la_data_in_mprj[30] la_data_in_mprj[31]
++ la_data_in_mprj[32] la_data_in_mprj[33] la_data_in_mprj[34] la_data_in_mprj[35]
++ la_data_in_mprj[36] la_data_in_mprj[37] la_data_in_mprj[38] la_data_in_mprj[39]
++ la_data_in_mprj[3] la_data_in_mprj[40] la_data_in_mprj[41] la_data_in_mprj[42] la_data_in_mprj[43]
++ la_data_in_mprj[44] la_data_in_mprj[45] la_data_in_mprj[46] la_data_in_mprj[47]
++ la_data_in_mprj[48] la_data_in_mprj[49] la_data_in_mprj[4] la_data_in_mprj[50] la_data_in_mprj[51]
++ la_data_in_mprj[52] la_data_in_mprj[53] la_data_in_mprj[54] la_data_in_mprj[55]
++ la_data_in_mprj[56] la_data_in_mprj[57] la_data_in_mprj[58] la_data_in_mprj[59]
++ la_data_in_mprj[5] la_data_in_mprj[60] la_data_in_mprj[61] la_data_in_mprj[62] la_data_in_mprj[63]
++ la_data_in_mprj[64] la_data_in_mprj[65] la_data_in_mprj[66] la_data_in_mprj[67]
++ la_data_in_mprj[68] la_data_in_mprj[69] la_data_in_mprj[6] la_data_in_mprj[70] la_data_in_mprj[71]
++ la_data_in_mprj[72] la_data_in_mprj[73] la_data_in_mprj[74] la_data_in_mprj[75]
++ la_data_in_mprj[76] la_data_in_mprj[77] la_data_in_mprj[78] la_data_in_mprj[79]
++ la_data_in_mprj[7] la_data_in_mprj[80] la_data_in_mprj[81] la_data_in_mprj[82] la_data_in_mprj[83]
++ la_data_in_mprj[84] la_data_in_mprj[85] la_data_in_mprj[86] la_data_in_mprj[87]
++ la_data_in_mprj[88] la_data_in_mprj[89] la_data_in_mprj[8] la_data_in_mprj[90] la_data_in_mprj[91]
++ la_data_in_mprj[92] la_data_in_mprj[93] la_data_in_mprj[94] la_data_in_mprj[95]
++ la_data_in_mprj[96] la_data_in_mprj[97] la_data_in_mprj[98] la_data_in_mprj[99]
++ la_data_in_mprj[9] la_data_out_core[0] la_data_out_core[100] la_data_out_core[101]
++ la_data_out_core[102] la_data_out_core[103] la_data_out_core[104] la_data_out_core[105]
++ la_data_out_core[106] la_data_out_core[107] la_data_out_core[108] la_data_out_core[109]
++ la_data_out_core[10] la_data_out_core[110] la_data_out_core[111] la_data_out_core[112]
++ la_data_out_core[113] la_data_out_core[114] la_data_out_core[115] la_data_out_core[116]
++ la_data_out_core[117] la_data_out_core[118] la_data_out_core[119] la_data_out_core[11]
++ la_data_out_core[120] la_data_out_core[121] la_data_out_core[122] la_data_out_core[123]
++ la_data_out_core[124] la_data_out_core[125] la_data_out_core[126] la_data_out_core[127]
++ la_data_out_core[12] la_data_out_core[13] la_data_out_core[14] la_data_out_core[15]
++ la_data_out_core[16] la_data_out_core[17] la_data_out_core[18] la_data_out_core[19]
++ la_data_out_core[1] la_data_out_core[20] la_data_out_core[21] la_data_out_core[22]
++ la_data_out_core[23] la_data_out_core[24] la_data_out_core[25] la_data_out_core[26]
++ la_data_out_core[27] la_data_out_core[28] la_data_out_core[29] la_data_out_core[2]
++ la_data_out_core[30] la_data_out_core[31] la_data_out_core[32] la_data_out_core[33]
++ la_data_out_core[34] la_data_out_core[35] la_data_out_core[36] la_data_out_core[37]
++ la_data_out_core[38] la_data_out_core[39] la_data_out_core[3] la_data_out_core[40]
++ la_data_out_core[41] la_data_out_core[42] la_data_out_core[43] la_data_out_core[44]
++ la_data_out_core[45] la_data_out_core[46] la_data_out_core[47] la_data_out_core[48]
++ la_data_out_core[49] la_data_out_core[4] la_data_out_core[50] la_data_out_core[51]
++ la_data_out_core[52] la_data_out_core[53] la_data_out_core[54] la_data_out_core[55]
++ la_data_out_core[56] la_data_out_core[57] la_data_out_core[58] la_data_out_core[59]
++ la_data_out_core[5] la_data_out_core[60] la_data_out_core[61] la_data_out_core[62]
++ la_data_out_core[63] la_data_out_core[64] la_data_out_core[65] la_data_out_core[66]
++ la_data_out_core[67] la_data_out_core[68] la_data_out_core[69] la_data_out_core[6]
++ la_data_out_core[70] la_data_out_core[71] la_data_out_core[72] la_data_out_core[73]
++ la_data_out_core[74] la_data_out_core[75] la_data_out_core[76] la_data_out_core[77]
++ la_data_out_core[78] la_data_out_core[79] la_data_out_core[7] la_data_out_core[80]
++ la_data_out_core[81] la_data_out_core[82] la_data_out_core[83] la_data_out_core[84]
++ la_data_out_core[85] la_data_out_core[86] la_data_out_core[87] la_data_out_core[88]
++ la_data_out_core[89] la_data_out_core[8] la_data_out_core[90] la_data_out_core[91]
++ la_data_out_core[92] la_data_out_core[93] la_data_out_core[94] la_data_out_core[95]
++ la_data_out_core[96] la_data_out_core[97] la_data_out_core[98] la_data_out_core[99]
++ la_data_out_core[9] la_data_out_mprj[0] la_data_out_mprj[100] la_data_out_mprj[101]
++ la_data_out_mprj[102] la_data_out_mprj[103] la_data_out_mprj[104] la_data_out_mprj[105]
++ la_data_out_mprj[106] la_data_out_mprj[107] la_data_out_mprj[108] la_data_out_mprj[109]
++ la_data_out_mprj[10] la_data_out_mprj[110] la_data_out_mprj[111] la_data_out_mprj[112]
++ la_data_out_mprj[113] la_data_out_mprj[114] la_data_out_mprj[115] la_data_out_mprj[116]
++ la_data_out_mprj[117] la_data_out_mprj[118] la_data_out_mprj[119] la_data_out_mprj[11]
++ la_data_out_mprj[120] la_data_out_mprj[121] la_data_out_mprj[122] la_data_out_mprj[123]
++ la_data_out_mprj[124] la_data_out_mprj[125] la_data_out_mprj[126] la_data_out_mprj[127]
++ la_data_out_mprj[12] la_data_out_mprj[13] la_data_out_mprj[14] la_data_out_mprj[15]
++ la_data_out_mprj[16] la_data_out_mprj[17] la_data_out_mprj[18] la_data_out_mprj[19]
++ la_data_out_mprj[1] la_data_out_mprj[20] la_data_out_mprj[21] la_data_out_mprj[22]
++ la_data_out_mprj[23] la_data_out_mprj[24] la_data_out_mprj[25] la_data_out_mprj[26]
++ la_data_out_mprj[27] la_data_out_mprj[28] la_data_out_mprj[29] la_data_out_mprj[2]
++ la_data_out_mprj[30] la_data_out_mprj[31] la_data_out_mprj[32] la_data_out_mprj[33]
++ la_data_out_mprj[34] la_data_out_mprj[35] la_data_out_mprj[36] la_data_out_mprj[37]
++ la_data_out_mprj[38] la_data_out_mprj[39] la_data_out_mprj[3] la_data_out_mprj[40]
++ la_data_out_mprj[41] la_data_out_mprj[42] la_data_out_mprj[43] la_data_out_mprj[44]
++ la_data_out_mprj[45] la_data_out_mprj[46] la_data_out_mprj[47] la_data_out_mprj[48]
++ la_data_out_mprj[49] la_data_out_mprj[4] la_data_out_mprj[50] la_data_out_mprj[51]
++ la_data_out_mprj[52] la_data_out_mprj[53] la_data_out_mprj[54] la_data_out_mprj[55]
++ la_data_out_mprj[56] la_data_out_mprj[57] la_data_out_mprj[58] la_data_out_mprj[59]
++ la_data_out_mprj[5] la_data_out_mprj[60] la_data_out_mprj[61] la_data_out_mprj[62]
++ la_data_out_mprj[63] la_data_out_mprj[64] la_data_out_mprj[65] la_data_out_mprj[66]
++ la_data_out_mprj[67] la_data_out_mprj[68] la_data_out_mprj[69] la_data_out_mprj[6]
++ la_data_out_mprj[70] la_data_out_mprj[71] la_data_out_mprj[72] la_data_out_mprj[73]
++ la_data_out_mprj[74] la_data_out_mprj[75] la_data_out_mprj[76] la_data_out_mprj[77]
++ la_data_out_mprj[78] la_data_out_mprj[79] la_data_out_mprj[7] la_data_out_mprj[80]
++ la_data_out_mprj[81] la_data_out_mprj[82] la_data_out_mprj[83] la_data_out_mprj[84]
++ la_data_out_mprj[85] la_data_out_mprj[86] la_data_out_mprj[87] la_data_out_mprj[88]
++ la_data_out_mprj[89] la_data_out_mprj[8] la_data_out_mprj[90] la_data_out_mprj[91]
++ la_data_out_mprj[92] la_data_out_mprj[93] la_data_out_mprj[94] la_data_out_mprj[95]
++ la_data_out_mprj[96] la_data_out_mprj[97] la_data_out_mprj[98] la_data_out_mprj[99]
++ la_data_out_mprj[9] la_iena_mprj[0] la_iena_mprj[100] la_iena_mprj[101] la_iena_mprj[102]
++ la_iena_mprj[103] la_iena_mprj[104] la_iena_mprj[105] la_iena_mprj[106] la_iena_mprj[107]
++ la_iena_mprj[108] la_iena_mprj[109] la_iena_mprj[10] la_iena_mprj[110] la_iena_mprj[111]
++ la_iena_mprj[112] la_iena_mprj[113] la_iena_mprj[114] la_iena_mprj[115] la_iena_mprj[116]
++ la_iena_mprj[117] la_iena_mprj[118] la_iena_mprj[119] la_iena_mprj[11] la_iena_mprj[120]
++ la_iena_mprj[121] la_iena_mprj[122] la_iena_mprj[123] la_iena_mprj[124] la_iena_mprj[125]
++ la_iena_mprj[126] la_iena_mprj[127] la_iena_mprj[12] la_iena_mprj[13] la_iena_mprj[14]
++ la_iena_mprj[15] la_iena_mprj[16] la_iena_mprj[17] la_iena_mprj[18] la_iena_mprj[19]
++ la_iena_mprj[1] la_iena_mprj[20] la_iena_mprj[21] la_iena_mprj[22] la_iena_mprj[23]
++ la_iena_mprj[24] la_iena_mprj[25] la_iena_mprj[26] la_iena_mprj[27] la_iena_mprj[28]
++ la_iena_mprj[29] la_iena_mprj[2] la_iena_mprj[30] la_iena_mprj[31] la_iena_mprj[32]
++ la_iena_mprj[33] la_iena_mprj[34] la_iena_mprj[35] la_iena_mprj[36] la_iena_mprj[37]
++ la_iena_mprj[38] la_iena_mprj[39] la_iena_mprj[3] la_iena_mprj[40] la_iena_mprj[41]
++ la_iena_mprj[42] la_iena_mprj[43] la_iena_mprj[44] la_iena_mprj[45] la_iena_mprj[46]
++ la_iena_mprj[47] la_iena_mprj[48] la_iena_mprj[49] la_iena_mprj[4] la_iena_mprj[50]
++ la_iena_mprj[51] la_iena_mprj[52] la_iena_mprj[53] la_iena_mprj[54] la_iena_mprj[55]
++ la_iena_mprj[56] la_iena_mprj[57] la_iena_mprj[58] la_iena_mprj[59] la_iena_mprj[5]
++ la_iena_mprj[60] la_iena_mprj[61] la_iena_mprj[62] la_iena_mprj[63] la_iena_mprj[64]
++ la_iena_mprj[65] la_iena_mprj[66] la_iena_mprj[67] la_iena_mprj[68] la_iena_mprj[69]
++ la_iena_mprj[6] la_iena_mprj[70] la_iena_mprj[71] la_iena_mprj[72] la_iena_mprj[73]
++ la_iena_mprj[74] la_iena_mprj[75] la_iena_mprj[76] la_iena_mprj[77] la_iena_mprj[78]
++ la_iena_mprj[79] la_iena_mprj[7] la_iena_mprj[80] la_iena_mprj[81] la_iena_mprj[82]
++ la_iena_mprj[83] la_iena_mprj[84] la_iena_mprj[85] la_iena_mprj[86] la_iena_mprj[87]
++ la_iena_mprj[88] la_iena_mprj[89] la_iena_mprj[8] la_iena_mprj[90] la_iena_mprj[91]
++ la_iena_mprj[92] la_iena_mprj[93] la_iena_mprj[94] la_iena_mprj[95] la_iena_mprj[96]
++ la_iena_mprj[97] la_iena_mprj[98] la_iena_mprj[99] la_iena_mprj[9] la_oenb_core[0]
++ la_oenb_core[100] la_oenb_core[101] la_oenb_core[102] la_oenb_core[103] la_oenb_core[104]
++ la_oenb_core[105] la_oenb_core[106] la_oenb_core[107] la_oenb_core[108] la_oenb_core[109]
++ la_oenb_core[10] la_oenb_core[110] la_oenb_core[111] la_oenb_core[112] la_oenb_core[113]
++ la_oenb_core[114] la_oenb_core[115] la_oenb_core[116] la_oenb_core[117] la_oenb_core[118]
++ la_oenb_core[119] la_oenb_core[11] la_oenb_core[120] la_oenb_core[121] la_oenb_core[122]
++ la_oenb_core[123] la_oenb_core[124] la_oenb_core[125] la_oenb_core[126] la_oenb_core[127]
++ la_oenb_core[12] la_oenb_core[13] la_oenb_core[14] la_oenb_core[15] la_oenb_core[16]
++ la_oenb_core[17] la_oenb_core[18] la_oenb_core[19] la_oenb_core[1] la_oenb_core[20]
++ la_oenb_core[21] la_oenb_core[22] la_oenb_core[23] la_oenb_core[24] la_oenb_core[25]
++ la_oenb_core[26] la_oenb_core[27] la_oenb_core[28] la_oenb_core[29] la_oenb_core[2]
++ la_oenb_core[30] la_oenb_core[31] la_oenb_core[32] la_oenb_core[33] la_oenb_core[34]
++ la_oenb_core[35] la_oenb_core[36] la_oenb_core[37] la_oenb_core[38] la_oenb_core[39]
++ la_oenb_core[3] la_oenb_core[40] la_oenb_core[41] la_oenb_core[42] la_oenb_core[43]
++ la_oenb_core[44] la_oenb_core[45] la_oenb_core[46] la_oenb_core[47] la_oenb_core[48]
++ la_oenb_core[49] la_oenb_core[4] la_oenb_core[50] la_oenb_core[51] la_oenb_core[52]
++ la_oenb_core[53] la_oenb_core[54] la_oenb_core[55] la_oenb_core[56] la_oenb_core[57]
++ la_oenb_core[58] la_oenb_core[59] la_oenb_core[5] la_oenb_core[60] la_oenb_core[61]
++ la_oenb_core[62] la_oenb_core[63] la_oenb_core[64] la_oenb_core[65] la_oenb_core[66]
++ la_oenb_core[67] la_oenb_core[68] la_oenb_core[69] la_oenb_core[6] la_oenb_core[70]
++ la_oenb_core[71] la_oenb_core[72] la_oenb_core[73] la_oenb_core[74] la_oenb_core[75]
++ la_oenb_core[76] la_oenb_core[77] la_oenb_core[78] la_oenb_core[79] la_oenb_core[7]
++ la_oenb_core[80] la_oenb_core[81] la_oenb_core[82] la_oenb_core[83] la_oenb_core[84]
++ la_oenb_core[85] la_oenb_core[86] la_oenb_core[87] la_oenb_core[88] la_oenb_core[89]
++ la_oenb_core[8] la_oenb_core[90] la_oenb_core[91] la_oenb_core[92] la_oenb_core[93]
++ la_oenb_core[94] la_oenb_core[95] la_oenb_core[96] la_oenb_core[97] la_oenb_core[98]
++ la_oenb_core[99] la_oenb_core[9] la_oenb_mprj[0] la_oenb_mprj[100] la_oenb_mprj[101]
++ la_oenb_mprj[102] la_oenb_mprj[103] la_oenb_mprj[104] la_oenb_mprj[105] la_oenb_mprj[106]
++ la_oenb_mprj[107] la_oenb_mprj[108] la_oenb_mprj[109] la_oenb_mprj[10] la_oenb_mprj[110]
++ la_oenb_mprj[111] la_oenb_mprj[112] la_oenb_mprj[113] la_oenb_mprj[114] la_oenb_mprj[115]
++ la_oenb_mprj[116] la_oenb_mprj[117] la_oenb_mprj[118] la_oenb_mprj[119] la_oenb_mprj[11]
++ la_oenb_mprj[120] la_oenb_mprj[121] la_oenb_mprj[122] la_oenb_mprj[123] la_oenb_mprj[124]
++ la_oenb_mprj[125] la_oenb_mprj[126] la_oenb_mprj[127] la_oenb_mprj[12] la_oenb_mprj[13]
++ la_oenb_mprj[14] la_oenb_mprj[15] la_oenb_mprj[16] la_oenb_mprj[17] la_oenb_mprj[18]
++ la_oenb_mprj[19] la_oenb_mprj[1] la_oenb_mprj[20] la_oenb_mprj[21] la_oenb_mprj[22]
++ la_oenb_mprj[23] la_oenb_mprj[24] la_oenb_mprj[25] la_oenb_mprj[26] la_oenb_mprj[27]
++ la_oenb_mprj[28] la_oenb_mprj[29] la_oenb_mprj[2] la_oenb_mprj[30] la_oenb_mprj[31]
++ la_oenb_mprj[32] la_oenb_mprj[33] la_oenb_mprj[34] la_oenb_mprj[35] la_oenb_mprj[36]
++ la_oenb_mprj[37] la_oenb_mprj[38] la_oenb_mprj[39] la_oenb_mprj[3] la_oenb_mprj[40]
++ la_oenb_mprj[41] la_oenb_mprj[42] la_oenb_mprj[43] la_oenb_mprj[44] la_oenb_mprj[45]
++ la_oenb_mprj[46] la_oenb_mprj[47] la_oenb_mprj[48] la_oenb_mprj[49] la_oenb_mprj[4]
++ la_oenb_mprj[50] la_oenb_mprj[51] la_oenb_mprj[52] la_oenb_mprj[53] la_oenb_mprj[54]
++ la_oenb_mprj[55] la_oenb_mprj[56] la_oenb_mprj[57] la_oenb_mprj[58] la_oenb_mprj[59]
++ la_oenb_mprj[5] la_oenb_mprj[60] la_oenb_mprj[61] la_oenb_mprj[62] la_oenb_mprj[63]
++ la_oenb_mprj[64] la_oenb_mprj[65] la_oenb_mprj[66] la_oenb_mprj[67] la_oenb_mprj[68]
++ la_oenb_mprj[69] la_oenb_mprj[6] la_oenb_mprj[70] la_oenb_mprj[71] la_oenb_mprj[72]
++ la_oenb_mprj[73] la_oenb_mprj[74] la_oenb_mprj[75] la_oenb_mprj[76] la_oenb_mprj[77]
++ la_oenb_mprj[78] la_oenb_mprj[79] la_oenb_mprj[7] la_oenb_mprj[80] la_oenb_mprj[81]
++ la_oenb_mprj[82] la_oenb_mprj[83] la_oenb_mprj[84] la_oenb_mprj[85] la_oenb_mprj[86]
++ la_oenb_mprj[87] la_oenb_mprj[88] la_oenb_mprj[89] la_oenb_mprj[8] la_oenb_mprj[90]
++ la_oenb_mprj[91] la_oenb_mprj[92] la_oenb_mprj[93] la_oenb_mprj[94] la_oenb_mprj[95]
++ la_oenb_mprj[96] la_oenb_mprj[97] la_oenb_mprj[98] la_oenb_mprj[99] la_oenb_mprj[9]
++ mprj_adr_o_core[0] mprj_adr_o_core[10] mprj_adr_o_core[11] mprj_adr_o_core[12] mprj_adr_o_core[13]
++ mprj_adr_o_core[14] mprj_adr_o_core[15] mprj_adr_o_core[16] mprj_adr_o_core[17]
++ mprj_adr_o_core[18] mprj_adr_o_core[19] mprj_adr_o_core[1] mprj_adr_o_core[20] mprj_adr_o_core[21]
++ mprj_adr_o_core[22] mprj_adr_o_core[23] mprj_adr_o_core[24] mprj_adr_o_core[25]
++ mprj_adr_o_core[26] mprj_adr_o_core[27] mprj_adr_o_core[28] mprj_adr_o_core[29]
++ mprj_adr_o_core[2] mprj_adr_o_core[30] mprj_adr_o_core[31] mprj_adr_o_core[3] mprj_adr_o_core[4]
++ mprj_adr_o_core[5] mprj_adr_o_core[6] mprj_adr_o_core[7] mprj_adr_o_core[8] mprj_adr_o_core[9]
++ mprj_adr_o_user[0] mprj_adr_o_user[10] mprj_adr_o_user[11] mprj_adr_o_user[12] mprj_adr_o_user[13]
++ mprj_adr_o_user[14] mprj_adr_o_user[15] mprj_adr_o_user[16] mprj_adr_o_user[17]
++ mprj_adr_o_user[18] mprj_adr_o_user[19] mprj_adr_o_user[1] mprj_adr_o_user[20] mprj_adr_o_user[21]
++ mprj_adr_o_user[22] mprj_adr_o_user[23] mprj_adr_o_user[24] mprj_adr_o_user[25]
++ mprj_adr_o_user[26] mprj_adr_o_user[27] mprj_adr_o_user[28] mprj_adr_o_user[29]
++ mprj_adr_o_user[2] mprj_adr_o_user[30] mprj_adr_o_user[31] mprj_adr_o_user[3] mprj_adr_o_user[4]
++ mprj_adr_o_user[5] mprj_adr_o_user[6] mprj_adr_o_user[7] mprj_adr_o_user[8] mprj_adr_o_user[9]
++ mprj_cyc_o_core mprj_cyc_o_user mprj_dat_o_core[0] mprj_dat_o_core[10] mprj_dat_o_core[11]
++ mprj_dat_o_core[12] mprj_dat_o_core[13] mprj_dat_o_core[14] mprj_dat_o_core[15]
++ mprj_dat_o_core[16] mprj_dat_o_core[17] mprj_dat_o_core[18] mprj_dat_o_core[19]
++ mprj_dat_o_core[1] mprj_dat_o_core[20] mprj_dat_o_core[21] mprj_dat_o_core[22] mprj_dat_o_core[23]
++ mprj_dat_o_core[24] mprj_dat_o_core[25] mprj_dat_o_core[26] mprj_dat_o_core[27]
++ mprj_dat_o_core[28] mprj_dat_o_core[29] mprj_dat_o_core[2] mprj_dat_o_core[30] mprj_dat_o_core[31]
++ mprj_dat_o_core[3] mprj_dat_o_core[4] mprj_dat_o_core[5] mprj_dat_o_core[6] mprj_dat_o_core[7]
++ mprj_dat_o_core[8] mprj_dat_o_core[9] mprj_dat_o_user[0] mprj_dat_o_user[10] mprj_dat_o_user[11]
++ mprj_dat_o_user[12] mprj_dat_o_user[13] mprj_dat_o_user[14] mprj_dat_o_user[15]
++ mprj_dat_o_user[16] mprj_dat_o_user[17] mprj_dat_o_user[18] mprj_dat_o_user[19]
++ mprj_dat_o_user[1] mprj_dat_o_user[20] mprj_dat_o_user[21] mprj_dat_o_user[22] mprj_dat_o_user[23]
++ mprj_dat_o_user[24] mprj_dat_o_user[25] mprj_dat_o_user[26] mprj_dat_o_user[27]
++ mprj_dat_o_user[28] mprj_dat_o_user[29] mprj_dat_o_user[2] mprj_dat_o_user[30] mprj_dat_o_user[31]
++ mprj_dat_o_user[3] mprj_dat_o_user[4] mprj_dat_o_user[5] mprj_dat_o_user[6] mprj_dat_o_user[7]
++ mprj_dat_o_user[8] mprj_dat_o_user[9] mprj_sel_o_core[0] mprj_sel_o_core[1] mprj_sel_o_core[2]
++ mprj_sel_o_core[3] mprj_sel_o_user[0] mprj_sel_o_user[1] mprj_sel_o_user[2] mprj_sel_o_user[3]
++ mprj_stb_o_core mprj_stb_o_user mprj_we_o_core mprj_we_o_user user1_vcc_powergood
++ user1_vdd_powergood user2_vcc_powergood user2_vdd_powergood user_clock user_clock2
++ user_irq[0] user_irq[1] user_irq[2] user_irq_core[0] user_irq_core[1] user_irq_core[2]
++ user_irq_ena[0] user_irq_ena[1] user_irq_ena[2] user_reset vccd vssd vccd1 vssd1
++ vccd2 vssd2 vdda1 vssa1 vdda2 vssa2
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped abstract view
+.subckt sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped A X VPWR VGND LVPWR LVGND
+.ends
+
+* Black-box entry subcircuit for copyright_block_a abstract view
+.subckt copyright_block_a VSUBS
+.ends
+
+* Black-box entry subcircuit for caravan_power_routing abstract view
+.subckt caravan_power_routing VSUBS m3_199417_950425# m3_440141_944424# vccd1_core
++ vssd_core vdda1_core m3_1241_921436# m3_201917_950457# m3_351041_944010# m3_249341_944424#
++ m3_611184_917994# m3_197018_950418# m3_94941_944424# vssd2_core vssio_core m3_182439_958470#
++ m3_235039_958470# m3_491583_949958# vssa2_core m3_146383_949202# vddio_core vccd2_core
++ m3_254341_944424# vdda2_core m3_42941_944424# vssd1_core vccd_core m3_251841_944424#
++ m3_356041_944010# m3_593341_944349# m3_353541_944010# m3_336839_958489# vssa1_core
+.ends
+
+* Black-box entry subcircuit for user_analog_project_wrapper abstract view
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+.ends
+
+* Black-box entry subcircuit for storage abstract view
+.subckt storage mgmt_addr[0] mgmt_addr[1] mgmt_addr[2] mgmt_addr[3] mgmt_addr[4] mgmt_addr[5]
++ mgmt_addr[6] mgmt_addr[7] mgmt_addr_ro[0] mgmt_addr_ro[1] mgmt_addr_ro[2] mgmt_addr_ro[3]
++ mgmt_addr_ro[4] mgmt_addr_ro[5] mgmt_addr_ro[6] mgmt_addr_ro[7] mgmt_clk mgmt_ena[0]
++ mgmt_ena[1] mgmt_ena_ro mgmt_rdata[0] mgmt_rdata[10] mgmt_rdata[11] mgmt_rdata[12]
++ mgmt_rdata[13] mgmt_rdata[14] mgmt_rdata[15] mgmt_rdata[16] mgmt_rdata[17] mgmt_rdata[18]
++ mgmt_rdata[19] mgmt_rdata[1] mgmt_rdata[20] mgmt_rdata[21] mgmt_rdata[22] mgmt_rdata[23]
++ mgmt_rdata[24] mgmt_rdata[25] mgmt_rdata[26] mgmt_rdata[27] mgmt_rdata[28] mgmt_rdata[29]
++ mgmt_rdata[2] mgmt_rdata[30] mgmt_rdata[31] mgmt_rdata[32] mgmt_rdata[33] mgmt_rdata[34]
++ mgmt_rdata[35] mgmt_rdata[36] mgmt_rdata[37] mgmt_rdata[38] mgmt_rdata[39] mgmt_rdata[3]
++ mgmt_rdata[40] mgmt_rdata[41] mgmt_rdata[42] mgmt_rdata[43] mgmt_rdata[44] mgmt_rdata[45]
++ mgmt_rdata[46] mgmt_rdata[47] mgmt_rdata[48] mgmt_rdata[49] mgmt_rdata[4] mgmt_rdata[50]
++ mgmt_rdata[51] mgmt_rdata[52] mgmt_rdata[53] mgmt_rdata[54] mgmt_rdata[55] mgmt_rdata[56]
++ mgmt_rdata[57] mgmt_rdata[58] mgmt_rdata[59] mgmt_rdata[5] mgmt_rdata[60] mgmt_rdata[61]
++ mgmt_rdata[62] mgmt_rdata[63] mgmt_rdata[6] mgmt_rdata[7] mgmt_rdata[8] mgmt_rdata[9]
++ mgmt_rdata_ro[0] mgmt_rdata_ro[10] mgmt_rdata_ro[11] mgmt_rdata_ro[12] mgmt_rdata_ro[13]
++ mgmt_rdata_ro[14] mgmt_rdata_ro[15] mgmt_rdata_ro[16] mgmt_rdata_ro[17] mgmt_rdata_ro[18]
++ mgmt_rdata_ro[19] mgmt_rdata_ro[1] mgmt_rdata_ro[20] mgmt_rdata_ro[21] mgmt_rdata_ro[22]
++ mgmt_rdata_ro[23] mgmt_rdata_ro[24] mgmt_rdata_ro[25] mgmt_rdata_ro[26] mgmt_rdata_ro[27]
++ mgmt_rdata_ro[28] mgmt_rdata_ro[29] mgmt_rdata_ro[2] mgmt_rdata_ro[30] mgmt_rdata_ro[31]
++ mgmt_rdata_ro[3] mgmt_rdata_ro[4] mgmt_rdata_ro[5] mgmt_rdata_ro[6] mgmt_rdata_ro[7]
++ mgmt_rdata_ro[8] mgmt_rdata_ro[9] mgmt_wdata[0] mgmt_wdata[10] mgmt_wdata[11] mgmt_wdata[12]
++ mgmt_wdata[13] mgmt_wdata[14] mgmt_wdata[15] mgmt_wdata[16] mgmt_wdata[17] mgmt_wdata[18]
++ mgmt_wdata[19] mgmt_wdata[1] mgmt_wdata[20] mgmt_wdata[21] mgmt_wdata[22] mgmt_wdata[23]
++ mgmt_wdata[24] mgmt_wdata[25] mgmt_wdata[26] mgmt_wdata[27] mgmt_wdata[28] mgmt_wdata[29]
++ mgmt_wdata[2] mgmt_wdata[30] mgmt_wdata[31] mgmt_wdata[3] mgmt_wdata[4] mgmt_wdata[5]
++ mgmt_wdata[6] mgmt_wdata[7] mgmt_wdata[8] mgmt_wdata[9] mgmt_wen[0] mgmt_wen[1]
++ mgmt_wen_mask[0] mgmt_wen_mask[1] mgmt_wen_mask[2] mgmt_wen_mask[3] mgmt_wen_mask[4]
++ mgmt_wen_mask[5] mgmt_wen_mask[6] mgmt_wen_mask[7] VPWR VGND
+.ends
+
+.subckt caravan clock flash_clk flash_csb flash_io0 flash_io1 gpio mprj_io[0] mprj_io[10]
++ mprj_io[11] mprj_io[12] mprj_io[13] mprj_io[18] mprj_io[15] mprj_io[16] mprj_io[17]
++ mprj_io[14] mprj_io[19] mprj_io[1] mprj_io[20] mprj_io[21] mprj_io[22] mprj_io[23]
++ mprj_io[24] mprj_io[25] mprj_io[26] mprj_io[27] mprj_io[28] mprj_io[29] mprj_io[2]
++ mprj_io[30] mprj_io[31] mprj_io[32] mprj_io[33] mprj_io[34] mprj_io[35] mprj_io[36]
++ mprj_io[37] mprj_io[3] mprj_io[4] mprj_io[5] mprj_io[6] mprj_io[7] mprj_io[8] mprj_io[9]
++ resetb vccd1 vccd2 vdda vdda1 vdda1_2 vdda2 vddio_2 vssa1 vssa1_2 vssa2 vssd1 vssd2
++ vssio_2 vddio vssio vssa vccd vssd pwr_ctrl_out[0] pwr_ctrl_out[1] pwr_ctrl_out[2]
++ pwr_ctrl_out[3]
+Xgpio_control_in_2\[0\] soc/mgmt_in_data[25] gpio_control_in_2\[0\]/one soc/mgmt_in_data[25]
++ gpio_control_in_2\[0\]/one padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14]
++ padframe/mprj_io_analog_sel[14] padframe/mprj_io_dm[42] padframe/mprj_io_dm[43]
++ padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14] padframe/mprj_io_ib_mode_sel[14]
++ padframe/mprj_io_in[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_out[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14] soc/mprj_io_loader_resetn
++ gpio_control_in_2\[1\]/resetn soc/mprj_io_loader_clock gpio_control_in_2\[1\]/serial_clock
++ gpio_control_in_2\[0\]/serial_data_in gpio_control_in_2\[0\]/serial_data_out mprj/io_in[14]
++ mprj/io_oeb[14] mprj/io_out[14] gpio_control_in_2\[0\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[6\] soc/mgmt_in_data[8] gpio_control_in_1\[6\]/one soc/mgmt_in_data[8]
++ gpio_control_in_1\[6\]/one padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8]
++ padframe/mprj_io_analog_sel[8] padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26]
++ padframe/mprj_io_holdover[8] padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_in[8]
++ padframe/mprj_io_inp_dis[8] padframe/mprj_io_out[8] padframe/mprj_io_oeb[8] padframe/mprj_io_slow_sel[8]
++ padframe/mprj_io_vtrip_sel[8] gpio_control_in_2\[8\]/resetn gpio_control_in_2\[9\]/resetn
++ gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[6\]/serial_data_in
++ gpio_control_in_1\[7\]/serial_data_in mprj/io_in[8] mprj/io_oeb[8] mprj/io_out[8]
++ gpio_control_in_1\[6\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xpadframe clock soc/clock por/por_l flash_clk flash_csb flash_io0 soc/flash_io0_di
++ soc/flash_io0_do soc/flash_io0_ieb soc/flash_io0_oeb flash_io1 soc/flash_io1_di
++ soc/flash_io1_do soc/flash_io1_ieb soc/flash_io1_oeb gpio soc/gpio_in_pad soc/gpio_inenb_pad
++ soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad vccd
++ vdda vddio vddio_2 vssa vssd vssio vssio_2 mprj_io[0] padframe/mprj_io_analog_en[0]
++ padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0] padframe/mprj_io_dm[0]
++ padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0] padframe/mprj_io_ib_mode_sel[0]
++ padframe/mprj_io_inp_dis[0] padframe/mprj_io_oeb[0] padframe/mprj_io_out[0] padframe/mprj_io_slow_sel[0]
++ padframe/mprj_io_vtrip_sel[0] padframe/mprj_io_in[0] mprj/io_in_3v3[0] mprj/gpio_analog[3]
++ mprj/gpio_noesd[3] mprj_io[10] padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10]
++ padframe/mprj_io_analog_sel[10] padframe/mprj_io_dm[30] padframe/mprj_io_dm[31]
++ padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10] padframe/mprj_io_ib_mode_sel[10]
++ padframe/mprj_io_inp_dis[10] padframe/mprj_io_oeb[10] padframe/mprj_io_out[10] padframe/mprj_io_slow_sel[10]
++ padframe/mprj_io_vtrip_sel[10] padframe/mprj_io_in[10] mprj/io_in_3v3[10] mprj/gpio_analog[4]
++ mprj/gpio_noesd[4] mprj_io[11] padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11]
++ padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33] padframe/mprj_io_dm[34]
++ padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11] padframe/mprj_io_ib_mode_sel[11]
++ padframe/mprj_io_inp_dis[11] padframe/mprj_io_oeb[11] padframe/mprj_io_out[11] padframe/mprj_io_slow_sel[11]
++ padframe/mprj_io_vtrip_sel[11] padframe/mprj_io_in[11] mprj/io_in_3v3[11] mprj/gpio_analog[5]
++ mprj/gpio_noesd[5] mprj_io[12] padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12]
++ padframe/mprj_io_analog_sel[12] padframe/mprj_io_dm[36] padframe/mprj_io_dm[37]
++ padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12] padframe/mprj_io_ib_mode_sel[12]
++ padframe/mprj_io_inp_dis[12] padframe/mprj_io_oeb[12] padframe/mprj_io_out[12] padframe/mprj_io_slow_sel[12]
++ padframe/mprj_io_vtrip_sel[12] padframe/mprj_io_in[12] mprj/io_in_3v3[12] mprj/gpio_analog[6]
++ mprj/gpio_noesd[6] mprj_io[13] padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13]
++ padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39] padframe/mprj_io_dm[40]
++ padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13] padframe/mprj_io_ib_mode_sel[13]
++ padframe/mprj_io_inp_dis[13] padframe/mprj_io_oeb[13] padframe/mprj_io_out[13] padframe/mprj_io_slow_sel[13]
++ padframe/mprj_io_vtrip_sel[13] padframe/mprj_io_in[13] mprj/io_in_3v3[13] mprj_io[1]
++ padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1] padframe/mprj_io_analog_sel[1]
++ padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5] padframe/mprj_io_holdover[1]
++ padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_inp_dis[1] padframe/mprj_io_oeb[1]
++ padframe/mprj_io_out[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ padframe/mprj_io_in[1] mprj/io_in_3v3[1] mprj_io[2] padframe/mprj_io_analog_en[2]
++ padframe/mprj_io_analog_pol[2] padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6]
++ padframe/mprj_io_dm[7] padframe/mprj_io_dm[8] padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2]
++ padframe/mprj_io_inp_dis[2] padframe/mprj_io_oeb[2] padframe/mprj_io_out[2] padframe/mprj_io_slow_sel[2]
++ padframe/mprj_io_vtrip_sel[2] padframe/mprj_io_in[2] mprj/io_in_3v3[2] mprj_io[3]
++ padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3] padframe/mprj_io_analog_sel[3]
++ padframe/mprj_io_dm[10] padframe/mprj_io_dm[11] padframe/mprj_io_dm[9] padframe/mprj_io_holdover[3]
++ padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_inp_dis[3] padframe/mprj_io_oeb[3]
++ padframe/mprj_io_out[3] padframe/mprj_io_slow_sel[3] padframe/mprj_io_vtrip_sel[3]
++ padframe/mprj_io_in[3] mprj/io_in_3v3[3] mprj_io[4] padframe/mprj_io_analog_en[4]
++ padframe/mprj_io_analog_pol[4] padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12]
++ padframe/mprj_io_dm[13] padframe/mprj_io_dm[14] padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4]
++ padframe/mprj_io_inp_dis[4] padframe/mprj_io_oeb[4] padframe/mprj_io_out[4] padframe/mprj_io_slow_sel[4]
++ padframe/mprj_io_vtrip_sel[4] padframe/mprj_io_in[4] mprj/io_in_3v3[4] mprj_io[5]
++ padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5] padframe/mprj_io_analog_sel[5]
++ padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17] padframe/mprj_io_holdover[5]
++ padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_inp_dis[5] padframe/mprj_io_oeb[5]
++ padframe/mprj_io_out[5] padframe/mprj_io_slow_sel[5] padframe/mprj_io_vtrip_sel[5]
++ padframe/mprj_io_in[5] mprj/io_in_3v3[5] mprj_io[6] padframe/mprj_io_analog_en[6]
++ padframe/mprj_io_analog_pol[6] padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18]
++ padframe/mprj_io_dm[19] padframe/mprj_io_dm[20] padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6]
++ padframe/mprj_io_inp_dis[6] padframe/mprj_io_oeb[6] padframe/mprj_io_out[6] padframe/mprj_io_slow_sel[6]
++ padframe/mprj_io_vtrip_sel[6] padframe/mprj_io_in[6] mprj/io_in_3v3[6] mprj/gpio_analog[0]
++ mprj/gpio_noesd[0] mprj_io[7] padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7]
++ padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23]
++ padframe/mprj_io_holdover[7] padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_inp_dis[7]
++ padframe/mprj_io_oeb[7] padframe/mprj_io_out[7] padframe/mprj_io_slow_sel[7] padframe/mprj_io_vtrip_sel[7]
++ padframe/mprj_io_in[7] mprj/io_in_3v3[7] mprj/gpio_analog[1] mprj/gpio_noesd[1]
++ mprj_io[8] padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8]
++ padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_inp_dis[8] padframe/mprj_io_oeb[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ padframe/mprj_io_in[8] mprj/io_in_3v3[8] mprj/gpio_analog[2] mprj/gpio_noesd[2]
++ mprj_io[9] padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9]
++ padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] padframe/mprj_io_holdover[9]
++ padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_inp_dis[9] padframe/mprj_io_oeb[9]
++ padframe/mprj_io_out[9] padframe/mprj_io_slow_sel[9] padframe/mprj_io_vtrip_sel[9]
++ padframe/mprj_io_in[9] mprj/io_in_3v3[9] mprj/gpio_analog[7] mprj/gpio_noesd[7]
++ mprj_io[25] padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14]
++ padframe/mprj_io_dm[42] padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14]
++ padframe/mprj_io_in[14] mprj/io_in_3v3[14] mprj/gpio_analog[17] mprj/gpio_noesd[17]
++ mprj_io[35] padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24]
++ padframe/mprj_io_dm[72] padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24]
++ padframe/mprj_io_ib_mode_sel[24] padframe/mprj_io_inp_dis[24] padframe/mprj_io_oeb[24]
++ padframe/mprj_io_out[24] padframe/mprj_io_slow_sel[24] padframe/mprj_io_vtrip_sel[24]
++ padframe/mprj_io_in[24] mprj/io_in_3v3[24] mprj_io[36] padframe/mprj_io_analog_en[25]
++ padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25] padframe/mprj_io_dm[75]
++ padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25] padframe/mprj_io_ib_mode_sel[25]
++ padframe/mprj_io_inp_dis[25] padframe/mprj_io_oeb[25] padframe/mprj_io_out[25] padframe/mprj_io_slow_sel[25]
++ padframe/mprj_io_vtrip_sel[25] padframe/mprj_io_in[25] mprj/io_in_3v3[25] mprj_io[37]
++ padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26]
++ padframe/mprj_io_dm[78] padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26]
++ padframe/mprj_io_ib_mode_sel[26] padframe/mprj_io_inp_dis[26] padframe/mprj_io_oeb[26]
++ padframe/mprj_io_out[26] padframe/mprj_io_slow_sel[26] padframe/mprj_io_vtrip_sel[26]
++ padframe/mprj_io_in[26] mprj/io_in_3v3[26] mprj/gpio_analog[8] mprj/gpio_noesd[8]
++ mprj_io[26] padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15]
++ padframe/mprj_io_dm[45] padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15]
++ padframe/mprj_io_ib_mode_sel[15] padframe/mprj_io_inp_dis[15] padframe/mprj_io_oeb[15]
++ padframe/mprj_io_out[15] padframe/mprj_io_slow_sel[15] padframe/mprj_io_vtrip_sel[15]
++ padframe/mprj_io_in[15] mprj/io_in_3v3[15] mprj/gpio_analog[9] mprj/gpio_noesd[9]
++ mprj_io[27] padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16]
++ padframe/mprj_io_dm[48] padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16]
++ padframe/mprj_io_in[16] mprj/io_in_3v3[16] mprj/gpio_analog[10] mprj/gpio_noesd[10]
++ mprj_io[28] padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17]
++ padframe/mprj_io_dm[51] padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17]
++ padframe/mprj_io_ib_mode_sel[17] padframe/mprj_io_inp_dis[17] padframe/mprj_io_oeb[17]
++ padframe/mprj_io_out[17] padframe/mprj_io_slow_sel[17] padframe/mprj_io_vtrip_sel[17]
++ padframe/mprj_io_in[17] mprj/io_in_3v3[17] mprj/gpio_analog[11] mprj/gpio_noesd[11]
++ mprj_io[29] padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18]
++ padframe/mprj_io_dm[54] padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18]
++ padframe/mprj_io_in[18] mprj/io_in_3v3[18] mprj/gpio_analog[12] mprj/gpio_noesd[12]
++ mprj_io[30] padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19]
++ padframe/mprj_io_dm[57] padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19]
++ padframe/mprj_io_in[19] mprj/io_in_3v3[19] mprj/gpio_analog[13] mprj/gpio_noesd[13]
++ mprj_io[31] padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20]
++ padframe/mprj_io_dm[60] padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20]
++ padframe/mprj_io_ib_mode_sel[20] padframe/mprj_io_inp_dis[20] padframe/mprj_io_oeb[20]
++ padframe/mprj_io_out[20] padframe/mprj_io_slow_sel[20] padframe/mprj_io_vtrip_sel[20]
++ padframe/mprj_io_in[20] mprj/io_in_3v3[20] mprj/gpio_analog[14] mprj/gpio_noesd[14]
++ mprj_io[32] padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21]
++ padframe/mprj_io_dm[63] padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21]
++ padframe/mprj_io_in[21] mprj/io_in_3v3[21] mprj/gpio_analog[15] mprj/gpio_noesd[15]
++ mprj_io[33] padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22]
++ padframe/mprj_io_dm[66] padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22]
++ padframe/mprj_io_ib_mode_sel[22] padframe/mprj_io_inp_dis[22] padframe/mprj_io_oeb[22]
++ padframe/mprj_io_out[22] padframe/mprj_io_slow_sel[22] padframe/mprj_io_vtrip_sel[22]
++ padframe/mprj_io_in[22] mprj/io_in_3v3[22] mprj/gpio_analog[16] mprj/gpio_noesd[16]
++ mprj_io[34] padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23]
++ padframe/mprj_io_dm[69] padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23]
++ padframe/mprj_io_in[23] mprj/io_in_3v3[23] por/porb_h resetb rstb_level/A padframe/vdda
++ padframe/vssa vssd_core mprj/io_analog[1] mprj_io[15] mprj/io_analog[2] mprj_io[16]
++ mprj/io_analog[3] mprj_io[17] mprj/io_analog[0] mprj_io[14] mprj/io_analog[4] mprj/io_clamp_high[0]
++ mprj/io_clamp_low[0] mprj_io[18] vccd1 vdda1 vdda1_2 vssa1 vssa1_2 vccd1_core vdda1_core
++ vssa1_core vssd1_core vssd1 mprj/io_analog[7] mprj_io[21] mprj/io_analog[8] mprj_io[22]
++ mprj/io_analog[9] mprj_io[23] mprj/io_analog[10] mprj_io[24] mprj/io_analog[5] mprj/io_clamp_high[1]
++ mprj/io_clamp_low[1] mprj_io[19] mprj/io_analog[6] mprj/io_clamp_high[2] mprj/io_clamp_low[2]
++ mprj_io[20] vccd2 vdda2 vssa2 vccd_core vccd2_core vdda2_core vddio_core vssa2_core
++ vssd2_core vssd2 vssio_core soc/flash_csb soc/flash_clk_ieb soc/flash_clk_oeb soc/flash_clk
++ soc/flash_csb_oeb soc/flash_csb_ieb chip_io_alt
+Xgpio_control_bidir_2\[0\] soc/mgmt_in_data[36] soc/flash_io2_oeb soc/mgmt_out_data[36]
++ gpio_control_bidir_2\[0\]/one padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25]
++ padframe/mprj_io_analog_sel[25] padframe/mprj_io_dm[75] padframe/mprj_io_dm[76]
++ padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25] padframe/mprj_io_ib_mode_sel[25]
++ padframe/mprj_io_in[25] padframe/mprj_io_inp_dis[25] padframe/mprj_io_out[25] padframe/mprj_io_oeb[25]
++ padframe/mprj_io_slow_sel[25] padframe/mprj_io_vtrip_sel[25] gpio_control_in_1\[9\]/resetn
++ gpio_control_in_1\[10\]/resetn gpio_control_in_1\[9\]/serial_clock gpio_control_in_1\[10\]/serial_clock
++ gpio_control_bidir_2\[0\]/serial_data_in gpio_control_in_2\[10\]/serial_data_in
++ mprj/io_in[25] mprj/io_oeb[25] mprj/io_out[25] gpio_control_bidir_2\[0\]/zero vccd_core
++ vssd_core vccd1_core vssd1_core gpio_control_block
+Xsoc soc/clock soc/core_clk soc/core_rstn soc/flash_clk soc/flash_clk_ieb soc/flash_clk_oeb
++ soc/flash_csb soc/flash_csb_ieb soc/flash_csb_oeb soc/flash_io0_di soc/flash_io0_do
++ soc/flash_io0_ieb soc/flash_io0_oeb soc/flash_io1_di soc/flash_io1_do soc/flash_io1_ieb
++ soc/flash_io1_oeb soc/flash_io2_oeb soc/flash_io3_oeb soc/gpio_in_pad soc/gpio_inenb_pad
++ soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad soc/jtag_out
++ soc/jtag_outenb soc/la_iena[0] soc/la_iena[100] soc/la_iena[101] soc/la_iena[102]
++ soc/la_iena[103] soc/la_iena[104] soc/la_iena[105] soc/la_iena[106] soc/la_iena[107]
++ soc/la_iena[108] soc/la_iena[109] soc/la_iena[10] soc/la_iena[110] soc/la_iena[111]
++ soc/la_iena[112] soc/la_iena[113] soc/la_iena[114] soc/la_iena[115] soc/la_iena[116]
++ soc/la_iena[117] soc/la_iena[118] soc/la_iena[119] soc/la_iena[11] soc/la_iena[120]
++ soc/la_iena[121] soc/la_iena[122] soc/la_iena[123] soc/la_iena[124] soc/la_iena[125]
++ soc/la_iena[126] soc/la_iena[127] soc/la_iena[12] soc/la_iena[13] soc/la_iena[14]
++ soc/la_iena[15] soc/la_iena[16] soc/la_iena[17] soc/la_iena[18] soc/la_iena[19]
++ soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22] soc/la_iena[23] soc/la_iena[24]
++ soc/la_iena[25] soc/la_iena[26] soc/la_iena[27] soc/la_iena[28] soc/la_iena[29]
++ soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32] soc/la_iena[33] soc/la_iena[34]
++ soc/la_iena[35] soc/la_iena[36] soc/la_iena[37] soc/la_iena[38] soc/la_iena[39]
++ soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42] soc/la_iena[43] soc/la_iena[44]
++ soc/la_iena[45] soc/la_iena[46] soc/la_iena[47] soc/la_iena[48] soc/la_iena[49]
++ soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52] soc/la_iena[53] soc/la_iena[54]
++ soc/la_iena[55] soc/la_iena[56] soc/la_iena[57] soc/la_iena[58] soc/la_iena[59]
++ soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62] soc/la_iena[63] soc/la_iena[64]
++ soc/la_iena[65] soc/la_iena[66] soc/la_iena[67] soc/la_iena[68] soc/la_iena[69]
++ soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72] soc/la_iena[73] soc/la_iena[74]
++ soc/la_iena[75] soc/la_iena[76] soc/la_iena[77] soc/la_iena[78] soc/la_iena[79]
++ soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82] soc/la_iena[83] soc/la_iena[84]
++ soc/la_iena[85] soc/la_iena[86] soc/la_iena[87] soc/la_iena[88] soc/la_iena[89]
++ soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92] soc/la_iena[93] soc/la_iena[94]
++ soc/la_iena[95] soc/la_iena[96] soc/la_iena[97] soc/la_iena[98] soc/la_iena[99]
++ soc/la_iena[9] soc/la_input[0] soc/la_input[100] soc/la_input[101] soc/la_input[102]
++ soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106] soc/la_input[107]
++ soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110] soc/la_input[111]
++ soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115] soc/la_input[116]
++ soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11] soc/la_input[120]
++ soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124] soc/la_input[125]
++ soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13] soc/la_input[14]
++ soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18] soc/la_input[19]
++ soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22] soc/la_input[23]
++ soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27] soc/la_input[28]
++ soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31] soc/la_input[32]
++ soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36] soc/la_input[37]
++ soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40] soc/la_input[41]
++ soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45] soc/la_input[46]
++ soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4] soc/la_input[50]
++ soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54] soc/la_input[55]
++ soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59] soc/la_input[5]
++ soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63] soc/la_input[64]
++ soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68] soc/la_input[69]
++ soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72] soc/la_input[73]
++ soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77] soc/la_input[78]
++ soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81] soc/la_input[82]
++ soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86] soc/la_input[87]
++ soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90] soc/la_input[91]
++ soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95] soc/la_input[96]
++ soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9] soc/la_oenb[0]
++ soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102] soc/la_oenb[103] soc/la_oenb[104]
++ soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107] soc/la_oenb[108] soc/la_oenb[109]
++ soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111] soc/la_oenb[112] soc/la_oenb[113]
++ soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116] soc/la_oenb[117] soc/la_oenb[118]
++ soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120] soc/la_oenb[121] soc/la_oenb[122]
++ soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125] soc/la_oenb[126] soc/la_oenb[127]
++ soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14] soc/la_oenb[15] soc/la_oenb[16]
++ soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19] soc/la_oenb[1] soc/la_oenb[20] soc/la_oenb[21]
++ soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24] soc/la_oenb[25] soc/la_oenb[26]
++ soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29] soc/la_oenb[2] soc/la_oenb[30] soc/la_oenb[31]
++ soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34] soc/la_oenb[35] soc/la_oenb[36]
++ soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39] soc/la_oenb[3] soc/la_oenb[40] soc/la_oenb[41]
++ soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44] soc/la_oenb[45] soc/la_oenb[46]
++ soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49] soc/la_oenb[4] soc/la_oenb[50] soc/la_oenb[51]
++ soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54] soc/la_oenb[55] soc/la_oenb[56]
++ soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59] soc/la_oenb[5] soc/la_oenb[60] soc/la_oenb[61]
++ soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64] soc/la_oenb[65] soc/la_oenb[66]
++ soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69] soc/la_oenb[6] soc/la_oenb[70] soc/la_oenb[71]
++ soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74] soc/la_oenb[75] soc/la_oenb[76]
++ soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79] soc/la_oenb[7] soc/la_oenb[80] soc/la_oenb[81]
++ soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84] soc/la_oenb[85] soc/la_oenb[86]
++ soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89] soc/la_oenb[8] soc/la_oenb[90] soc/la_oenb[91]
++ soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94] soc/la_oenb[95] soc/la_oenb[96]
++ soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99] soc/la_oenb[9] soc/la_output[0]
++ soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103] soc/la_output[104]
++ soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108] soc/la_output[109]
++ soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112] soc/la_output[113]
++ soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117] soc/la_output[118]
++ soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121] soc/la_output[122]
++ soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126] soc/la_output[127]
++ soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15] soc/la_output[16]
++ soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1] soc/la_output[20]
++ soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24] soc/la_output[25]
++ soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29] soc/la_output[2]
++ soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33] soc/la_output[34]
++ soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38] soc/la_output[39]
++ soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42] soc/la_output[43]
++ soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47] soc/la_output[48]
++ soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51] soc/la_output[52]
++ soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56] soc/la_output[57]
++ soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60] soc/la_output[61]
++ soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65] soc/la_output[66]
++ soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6] soc/la_output[70]
++ soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74] soc/la_output[75]
++ soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79] soc/la_output[7]
++ soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83] soc/la_output[84]
++ soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88] soc/la_output[89]
++ soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92] soc/la_output[93]
++ soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97] soc/la_output[98]
++ soc/la_output[99] soc/la_output[9] soc/mask_rev[0] soc/mask_rev[10] soc/mask_rev[11]
++ soc/mask_rev[12] soc/mask_rev[13] soc/mask_rev[14] soc/mask_rev[15] soc/mask_rev[16]
++ soc/mask_rev[17] soc/mask_rev[18] soc/mask_rev[19] soc/mask_rev[1] soc/mask_rev[20]
++ soc/mask_rev[21] soc/mask_rev[22] soc/mask_rev[23] soc/mask_rev[24] soc/mask_rev[25]
++ soc/mask_rev[26] soc/mask_rev[27] soc/mask_rev[28] soc/mask_rev[29] soc/mask_rev[2]
++ soc/mask_rev[30] soc/mask_rev[31] soc/mask_rev[3] soc/mask_rev[4] soc/mask_rev[5]
++ soc/mask_rev[6] soc/mask_rev[7] soc/mask_rev[8] soc/mask_rev[9] soc/mgmt_addr[0]
++ soc/mgmt_addr[1] soc/mgmt_addr[2] soc/mgmt_addr[3] soc/mgmt_addr[4] soc/mgmt_addr[5]
++ soc/mgmt_addr[6] soc/mgmt_addr[7] soc/mgmt_addr_ro[0] soc/mgmt_addr_ro[1] soc/mgmt_addr_ro[2]
++ soc/mgmt_addr_ro[3] soc/mgmt_addr_ro[4] soc/mgmt_addr_ro[5] soc/mgmt_addr_ro[6]
++ soc/mgmt_addr_ro[7] soc/mgmt_ena[0] soc/mgmt_ena[1] soc/mgmt_ena_ro soc/mgmt_in_data[0]
++ soc/mgmt_in_data[10] soc/mgmt_in_data[11] soc/mgmt_in_data[12] soc/mgmt_in_data[13]
++ soc/mgmt_in_data[14] soc/mgmt_in_data[15] soc/mgmt_in_data[16] soc/mgmt_in_data[17]
++ soc/mgmt_in_data[18] soc/mgmt_in_data[19] soc/mgmt_in_data[1] soc/mgmt_in_data[20]
++ soc/mgmt_in_data[21] soc/mgmt_in_data[22] soc/mgmt_in_data[23] soc/mgmt_in_data[24]
++ soc/mgmt_in_data[25] soc/mgmt_in_data[26] soc/mgmt_in_data[27] soc/mgmt_in_data[28]
++ soc/mgmt_in_data[29] soc/mgmt_in_data[2] soc/mgmt_in_data[30] soc/mgmt_in_data[31]
++ soc/mgmt_in_data[32] soc/mgmt_in_data[33] soc/mgmt_in_data[34] soc/mgmt_in_data[35]
++ soc/mgmt_in_data[36] soc/mgmt_in_data[37] soc/mgmt_in_data[3] soc/mgmt_in_data[4]
++ soc/mgmt_in_data[5] soc/mgmt_in_data[6] soc/mgmt_in_data[7] soc/mgmt_in_data[8]
++ soc/mgmt_in_data[9] soc/mgmt_out_data[0] soc/mgmt_in_data[10] soc/mgmt_in_data[11]
++ soc/mgmt_in_data[12] soc/mgmt_in_data[13] soc/mgmt_in_data[14] soc/mgmt_in_data[15]
++ soc/mgmt_in_data[16] soc/mgmt_in_data[17] soc/mgmt_in_data[18] soc/mgmt_in_data[19]
++ soc/mgmt_out_data[1] soc/mgmt_in_data[20] soc/mgmt_in_data[21] soc/mgmt_in_data[22]
++ soc/mgmt_in_data[23] soc/mgmt_in_data[24] soc/mgmt_in_data[25] soc/mgmt_in_data[26]
++ soc/mgmt_in_data[27] soc/mgmt_in_data[28] soc/mgmt_in_data[29] soc/mgmt_in_data[2]
++ soc/mgmt_in_data[30] soc/mgmt_in_data[31] soc/mgmt_in_data[32] soc/mgmt_in_data[33]
++ soc/mgmt_in_data[34] soc/mgmt_in_data[35] soc/mgmt_out_data[36] soc/mgmt_out_data[37]
++ soc/mgmt_in_data[3] soc/mgmt_in_data[4] soc/mgmt_in_data[5] soc/mgmt_in_data[6]
++ soc/mgmt_in_data[7] soc/mgmt_in_data[8] soc/mgmt_in_data[9] soc/mgmt_rdata[0] soc/mgmt_rdata[10]
++ soc/mgmt_rdata[11] soc/mgmt_rdata[12] soc/mgmt_rdata[13] soc/mgmt_rdata[14] soc/mgmt_rdata[15]
++ soc/mgmt_rdata[16] soc/mgmt_rdata[17] soc/mgmt_rdata[18] soc/mgmt_rdata[19] soc/mgmt_rdata[1]
++ soc/mgmt_rdata[20] soc/mgmt_rdata[21] soc/mgmt_rdata[22] soc/mgmt_rdata[23] soc/mgmt_rdata[24]
++ soc/mgmt_rdata[25] soc/mgmt_rdata[26] soc/mgmt_rdata[27] soc/mgmt_rdata[28] soc/mgmt_rdata[29]
++ soc/mgmt_rdata[2] soc/mgmt_rdata[30] soc/mgmt_rdata[31] soc/mgmt_rdata[32] soc/mgmt_rdata[33]
++ soc/mgmt_rdata[34] soc/mgmt_rdata[35] soc/mgmt_rdata[36] soc/mgmt_rdata[37] soc/mgmt_rdata[38]
++ soc/mgmt_rdata[39] soc/mgmt_rdata[3] soc/mgmt_rdata[40] soc/mgmt_rdata[41] soc/mgmt_rdata[42]
++ soc/mgmt_rdata[43] soc/mgmt_rdata[44] soc/mgmt_rdata[45] soc/mgmt_rdata[46] soc/mgmt_rdata[47]
++ soc/mgmt_rdata[48] soc/mgmt_rdata[49] soc/mgmt_rdata[4] soc/mgmt_rdata[50] soc/mgmt_rdata[51]
++ soc/mgmt_rdata[52] soc/mgmt_rdata[53] soc/mgmt_rdata[54] soc/mgmt_rdata[55] soc/mgmt_rdata[56]
++ soc/mgmt_rdata[57] soc/mgmt_rdata[58] soc/mgmt_rdata[59] soc/mgmt_rdata[5] soc/mgmt_rdata[60]
++ soc/mgmt_rdata[61] soc/mgmt_rdata[62] soc/mgmt_rdata[63] soc/mgmt_rdata[6] soc/mgmt_rdata[7]
++ soc/mgmt_rdata[8] soc/mgmt_rdata[9] soc/mgmt_rdata_ro[0] soc/mgmt_rdata_ro[10] soc/mgmt_rdata_ro[11]
++ soc/mgmt_rdata_ro[12] soc/mgmt_rdata_ro[13] soc/mgmt_rdata_ro[14] soc/mgmt_rdata_ro[15]
++ soc/mgmt_rdata_ro[16] soc/mgmt_rdata_ro[17] soc/mgmt_rdata_ro[18] soc/mgmt_rdata_ro[19]
++ soc/mgmt_rdata_ro[1] soc/mgmt_rdata_ro[20] soc/mgmt_rdata_ro[21] soc/mgmt_rdata_ro[22]
++ soc/mgmt_rdata_ro[23] soc/mgmt_rdata_ro[24] soc/mgmt_rdata_ro[25] soc/mgmt_rdata_ro[26]
++ soc/mgmt_rdata_ro[27] soc/mgmt_rdata_ro[28] soc/mgmt_rdata_ro[29] soc/mgmt_rdata_ro[2]
++ soc/mgmt_rdata_ro[30] soc/mgmt_rdata_ro[31] soc/mgmt_rdata_ro[3] soc/mgmt_rdata_ro[4]
++ soc/mgmt_rdata_ro[5] soc/mgmt_rdata_ro[6] soc/mgmt_rdata_ro[7] soc/mgmt_rdata_ro[8]
++ soc/mgmt_rdata_ro[9] soc/mgmt_wdata[0] soc/mgmt_wdata[10] soc/mgmt_wdata[11] soc/mgmt_wdata[12]
++ soc/mgmt_wdata[13] soc/mgmt_wdata[14] soc/mgmt_wdata[15] soc/mgmt_wdata[16] soc/mgmt_wdata[17]
++ soc/mgmt_wdata[18] soc/mgmt_wdata[19] soc/mgmt_wdata[1] soc/mgmt_wdata[20] soc/mgmt_wdata[21]
++ soc/mgmt_wdata[22] soc/mgmt_wdata[23] soc/mgmt_wdata[24] soc/mgmt_wdata[25] soc/mgmt_wdata[26]
++ soc/mgmt_wdata[27] soc/mgmt_wdata[28] soc/mgmt_wdata[29] soc/mgmt_wdata[2] soc/mgmt_wdata[30]
++ soc/mgmt_wdata[31] soc/mgmt_wdata[3] soc/mgmt_wdata[4] soc/mgmt_wdata[5] soc/mgmt_wdata[6]
++ soc/mgmt_wdata[7] soc/mgmt_wdata[8] soc/mgmt_wdata[9] soc/mgmt_wen[0] soc/mgmt_wen[1]
++ soc/mgmt_wen_mask[0] soc/mgmt_wen_mask[1] soc/mgmt_wen_mask[2] soc/mgmt_wen_mask[3]
++ soc/mgmt_wen_mask[4] soc/mgmt_wen_mask[5] soc/mgmt_wen_mask[6] soc/mgmt_wen_mask[7]
++ soc/mprj2_vcc_pwrgood soc/mprj2_vdd_pwrgood soc/mprj_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10]
++ soc/mprj_adr_o[11] soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15]
++ soc/mprj_adr_o[16] soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1]
++ soc/mprj_adr_o[20] soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24]
++ soc/mprj_adr_o[25] soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29]
++ soc/mprj_adr_o[2] soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4]
++ soc/mprj_adr_o[5] soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9]
++ soc/mprj_cyc_o soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12]
++ soc/mprj_dat_i[13] soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17]
++ soc/mprj_dat_i[18] soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21]
++ soc/mprj_dat_i[22] soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26]
++ soc/mprj_dat_i[27] soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30]
++ soc/mprj_dat_i[31] soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6]
++ soc/mprj_dat_i[7] soc/mprj_dat_i[8] soc/mprj_dat_i[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ soc/mprj_io_loader_clock soc/mprj_io_loader_data_1 soc/mprj_io_loader_data_2 soc/mprj_io_loader_resetn
++ soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] soc/mprj_stb_o
++ soc/mprj_vcc_pwrgood soc/mprj_vdd_pwrgood soc/mprj_we_o soc/porb pwr_ctrl_out[0]
++ pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3] soc/resetb soc/sdo_out soc/sdo_outenb
++ soc/user_clk soc/user_irq[0] soc/user_irq[1] soc/user_irq[2] soc/user_irq_ena[0]
++ soc/user_irq_ena[1] soc/user_irq_ena[2] vccd_core vssd_core mgmt_core
+Xgpio_control_in_2\[9\] soc/mgmt_in_data[34] gpio_control_in_2\[9\]/one soc/mgmt_in_data[34]
++ gpio_control_in_2\[9\]/one padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23]
++ padframe/mprj_io_analog_sel[23] padframe/mprj_io_dm[69] padframe/mprj_io_dm[70]
++ padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23] padframe/mprj_io_ib_mode_sel[23]
++ padframe/mprj_io_in[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_out[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23] gpio_control_in_2\[9\]/resetn
++ gpio_control_in_1\[8\]/resetn gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[8\]/serial_clock
++ gpio_control_in_2\[9\]/serial_data_in gpio_control_in_2\[8\]/serial_data_in mprj/io_in[23]
++ mprj/io_oeb[23] mprj/io_out[23] gpio_control_in_2\[9\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xuser_id_textblock_0 VSUBS user_id_textblock
+Xgpio_control_in_1\[4\] soc/mgmt_in_data[6] gpio_control_in_1\[4\]/one soc/mgmt_in_data[6]
++ gpio_control_in_1\[4\]/one padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6]
++ padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20]
++ padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_in[6]
++ padframe/mprj_io_inp_dis[6] padframe/mprj_io_out[6] padframe/mprj_io_oeb[6] padframe/mprj_io_slow_sel[6]
++ padframe/mprj_io_vtrip_sel[6] gpio_control_in_2\[6\]/resetn gpio_control_in_2\[7\]/resetn
++ gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[7\]/serial_clock gpio_control_in_1\[4\]/serial_data_in
++ gpio_control_in_1\[5\]/serial_data_in mprj/io_in[6] mprj/io_oeb[6] mprj/io_out[6]
++ gpio_control_in_1\[4\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xpor vddio_core vccd_core vssio_core por/porb_h por/por_l soc/porb simple_por
+Xgpio_control_in_2\[7\] soc/mgmt_in_data[32] gpio_control_in_2\[7\]/one soc/mgmt_in_data[32]
++ gpio_control_in_2\[7\]/one padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21]
++ padframe/mprj_io_analog_sel[21] padframe/mprj_io_dm[63] padframe/mprj_io_dm[64]
++ padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21] padframe/mprj_io_ib_mode_sel[21]
++ padframe/mprj_io_in[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_out[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21] gpio_control_in_2\[7\]/resetn
++ gpio_control_in_2\[8\]/resetn gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[8\]/serial_clock
++ gpio_control_in_2\[7\]/serial_data_in gpio_control_in_2\[6\]/serial_data_in mprj/io_in[21]
++ mprj/io_oeb[21] mprj/io_out[21] gpio_control_in_2\[7\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[2\] soc/mgmt_in_data[4] gpio_control_in_1\[2\]/one soc/mgmt_in_data[4]
++ gpio_control_in_1\[2\]/one padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4]
++ padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14]
++ padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_in[4]
++ padframe/mprj_io_inp_dis[4] padframe/mprj_io_out[4] padframe/mprj_io_oeb[4] padframe/mprj_io_slow_sel[4]
++ padframe/mprj_io_vtrip_sel[4] gpio_control_in_2\[4\]/resetn gpio_control_in_2\[5\]/resetn
++ gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock gpio_control_in_1\[2\]/serial_data_in
++ gpio_control_in_1\[3\]/serial_data_in mprj/io_in[4] mprj/io_oeb[4] mprj/io_out[4]
++ gpio_control_in_1\[2\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[10\] soc/mgmt_in_data[35] gpio_control_in_2\[10\]/one soc/mgmt_in_data[35]
++ gpio_control_in_2\[10\]/one padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24]
++ padframe/mprj_io_analog_sel[24] padframe/mprj_io_dm[72] padframe/mprj_io_dm[73]
++ padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24] padframe/mprj_io_ib_mode_sel[24]
++ padframe/mprj_io_in[24] padframe/mprj_io_inp_dis[24] padframe/mprj_io_out[24] padframe/mprj_io_oeb[24]
++ padframe/mprj_io_slow_sel[24] padframe/mprj_io_vtrip_sel[24] gpio_control_in_1\[8\]/resetn
++ gpio_control_in_1\[9\]/resetn gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[9\]/serial_clock
++ gpio_control_in_2\[10\]/serial_data_in gpio_control_in_2\[9\]/serial_data_in mprj/io_in[24]
++ mprj/io_oeb[24] mprj/io_out[24] gpio_control_in_2\[10\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[10\] soc/mgmt_in_data[12] gpio_control_in_1\[10\]/one soc/mgmt_in_data[12]
++ gpio_control_in_1\[10\]/one padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12]
++ padframe/mprj_io_analog_sel[12] padframe/mprj_io_dm[36] padframe/mprj_io_dm[37]
++ padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12] padframe/mprj_io_ib_mode_sel[12]
++ padframe/mprj_io_in[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_out[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12] gpio_control_in_1\[10\]/resetn
++ gpio_control_in_1\[11\]/resetn gpio_control_in_1\[10\]/serial_clock gpio_control_in_1\[11\]/serial_clock
++ gpio_control_in_1\[9\]/serial_data_out gpio_control_in_1\[11\]/serial_data_in mprj/io_in[12]
++ mprj/io_oeb[12] mprj/io_out[12] gpio_control_in_1\[10\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[5\] soc/mgmt_in_data[30] gpio_control_in_2\[5\]/one soc/mgmt_in_data[30]
++ gpio_control_in_2\[5\]/one padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19]
++ padframe/mprj_io_analog_sel[19] padframe/mprj_io_dm[57] padframe/mprj_io_dm[58]
++ padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19] padframe/mprj_io_ib_mode_sel[19]
++ padframe/mprj_io_in[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_out[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19] gpio_control_in_2\[5\]/resetn
++ gpio_control_in_2\[6\]/resetn gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[6\]/serial_clock
++ gpio_control_in_2\[5\]/serial_data_in gpio_control_in_2\[4\]/serial_data_in mprj/io_in[19]
++ mprj/io_oeb[19] mprj/io_out[19] gpio_control_in_2\[5\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[0\] soc/mgmt_in_data[2] gpio_control_in_1\[0\]/one soc/mgmt_in_data[2]
++ gpio_control_in_1\[0\]/one padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2]
++ padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8]
++ padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_in[2]
++ padframe/mprj_io_inp_dis[2] padframe/mprj_io_out[2] padframe/mprj_io_oeb[2] padframe/mprj_io_slow_sel[2]
++ padframe/mprj_io_vtrip_sel[2] gpio_control_in_2\[2\]/resetn gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock gpio_control_in_1\[0\]/serial_data_in
++ gpio_control_in_1\[1\]/serial_data_in mprj/io_in[2] mprj/io_oeb[2] mprj/io_out[2]
++ gpio_control_in_1\[0\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xuser_id_value soc/mask_rev[0] soc/mask_rev[10] soc/mask_rev[11] soc/mask_rev[12]
++ soc/mask_rev[13] soc/mask_rev[14] soc/mask_rev[15] soc/mask_rev[16] soc/mask_rev[17]
++ soc/mask_rev[18] soc/mask_rev[19] soc/mask_rev[1] soc/mask_rev[20] soc/mask_rev[21]
++ soc/mask_rev[22] soc/mask_rev[23] soc/mask_rev[24] soc/mask_rev[25] soc/mask_rev[26]
++ soc/mask_rev[27] soc/mask_rev[28] soc/mask_rev[29] soc/mask_rev[2] soc/mask_rev[30]
++ soc/mask_rev[31] soc/mask_rev[3] soc/mask_rev[4] soc/mask_rev[5] soc/mask_rev[6]
++ soc/mask_rev[7] soc/mask_rev[8] soc/mask_rev[9] vccd_core vssd_core user_id_programming
+Xgpio_control_in_2\[3\] soc/mgmt_in_data[28] gpio_control_in_2\[3\]/one soc/mgmt_in_data[28]
++ gpio_control_in_2\[3\]/one padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17]
++ padframe/mprj_io_analog_sel[17] padframe/mprj_io_dm[51] padframe/mprj_io_dm[52]
++ padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17] padframe/mprj_io_ib_mode_sel[17]
++ padframe/mprj_io_in[17] padframe/mprj_io_inp_dis[17] padframe/mprj_io_out[17] padframe/mprj_io_oeb[17]
++ padframe/mprj_io_slow_sel[17] padframe/mprj_io_vtrip_sel[17] gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[4\]/resetn gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock
++ gpio_control_in_2\[3\]/serial_data_in gpio_control_in_2\[2\]/serial_data_in mprj/io_in[17]
++ mprj/io_oeb[17] mprj/io_out[17] gpio_control_in_2\[3\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_bidir_1\[0\] soc/mgmt_in_data[0] soc/jtag_outenb soc/jtag_out gpio_control_bidir_1\[0\]/one
++ padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0]
++ padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0]
++ padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_in[0] padframe/mprj_io_inp_dis[0]
++ padframe/mprj_io_out[0] padframe/mprj_io_oeb[0] padframe/mprj_io_slow_sel[0] padframe/mprj_io_vtrip_sel[0]
++ soc/mprj_io_loader_resetn gpio_control_in_2\[1\]/resetn soc/mprj_io_loader_clock
++ gpio_control_in_2\[1\]/serial_clock soc/mprj_io_loader_data_1 gpio_control_bidir_1\[1\]/serial_data_in
++ mprj/io_in[0] mprj/io_oeb[0] mprj/io_out[0] gpio_control_bidir_1\[0\]/zero vccd_core
++ vssd_core vccd1_core vssd1_core gpio_control_block
+Xopen_source_0 VSUBS open_source
+Xgpio_control_in_1\[9\] soc/mgmt_in_data[11] gpio_control_in_1\[9\]/one soc/mgmt_in_data[11]
++ gpio_control_in_1\[9\]/one padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11]
++ padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33] padframe/mprj_io_dm[34]
++ padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11] padframe/mprj_io_ib_mode_sel[11]
++ padframe/mprj_io_in[11] padframe/mprj_io_inp_dis[11] padframe/mprj_io_out[11] padframe/mprj_io_oeb[11]
++ padframe/mprj_io_slow_sel[11] padframe/mprj_io_vtrip_sel[11] gpio_control_in_1\[9\]/resetn
++ gpio_control_in_1\[10\]/resetn gpio_control_in_1\[9\]/serial_clock gpio_control_in_1\[10\]/serial_clock
++ gpio_control_in_1\[9\]/serial_data_in gpio_control_in_1\[9\]/serial_data_out mprj/io_in[11]
++ mprj/io_oeb[11] mprj/io_out[11] gpio_control_in_1\[9\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[1\] soc/mgmt_in_data[26] gpio_control_in_2\[1\]/one soc/mgmt_in_data[26]
++ gpio_control_in_2\[1\]/one padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15]
++ padframe/mprj_io_analog_sel[15] padframe/mprj_io_dm[45] padframe/mprj_io_dm[46]
++ padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15] padframe/mprj_io_ib_mode_sel[15]
++ padframe/mprj_io_in[15] padframe/mprj_io_inp_dis[15] padframe/mprj_io_out[15] padframe/mprj_io_oeb[15]
++ padframe/mprj_io_slow_sel[15] padframe/mprj_io_vtrip_sel[15] gpio_control_in_2\[1\]/resetn
++ gpio_control_in_2\[2\]/resetn gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[2\]/serial_clock
++ gpio_control_in_2\[1\]/serial_data_in gpio_control_in_2\[0\]/serial_data_in mprj/io_in[15]
++ mprj/io_oeb[15] mprj/io_out[15] gpio_control_in_2\[1\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[7\] soc/mgmt_in_data[9] gpio_control_in_1\[7\]/one soc/mgmt_in_data[9]
++ gpio_control_in_1\[7\]/one padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9]
++ padframe/mprj_io_analog_sel[9] padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29]
++ padframe/mprj_io_holdover[9] padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_in[9]
++ padframe/mprj_io_inp_dis[9] padframe/mprj_io_out[9] padframe/mprj_io_oeb[9] padframe/mprj_io_slow_sel[9]
++ padframe/mprj_io_vtrip_sel[9] gpio_control_in_2\[9\]/resetn gpio_control_in_1\[8\]/resetn
++ gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[7\]/serial_data_in
++ gpio_control_in_1\[8\]/serial_data_in mprj/io_in[9] mprj/io_oeb[9] mprj/io_out[9]
++ gpio_control_in_1\[7\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xmgmt_buffers soc/core_clk soc/user_clk soc/core_rstn mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ mprj/la_data_out[0] mprj/la_data_out[100] mprj/la_data_out[101] mprj/la_data_out[102]
++ mprj/la_data_out[103] mprj/la_data_out[104] mprj/la_data_out[105] mprj/la_data_out[106]
++ mprj/la_data_out[107] mprj/la_data_out[108] mprj/la_data_out[109] mprj/la_data_out[10]
++ mprj/la_data_out[110] mprj/la_data_out[111] mprj/la_data_out[112] mprj/la_data_out[113]
++ mprj/la_data_out[114] mprj/la_data_out[115] mprj/la_data_out[116] mprj/la_data_out[117]
++ mprj/la_data_out[118] mprj/la_data_out[119] mprj/la_data_out[11] mprj/la_data_out[120]
++ mprj/la_data_out[121] mprj/la_data_out[122] mprj/la_data_out[123] mprj/la_data_out[124]
++ mprj/la_data_out[125] mprj/la_data_out[126] mprj/la_data_out[127] mprj/la_data_out[12]
++ mprj/la_data_out[13] mprj/la_data_out[14] mprj/la_data_out[15] mprj/la_data_out[16]
++ mprj/la_data_out[17] mprj/la_data_out[18] mprj/la_data_out[19] mprj/la_data_out[1]
++ mprj/la_data_out[20] mprj/la_data_out[21] mprj/la_data_out[22] mprj/la_data_out[23]
++ mprj/la_data_out[24] mprj/la_data_out[25] mprj/la_data_out[26] mprj/la_data_out[27]
++ mprj/la_data_out[28] mprj/la_data_out[29] mprj/la_data_out[2] mprj/la_data_out[30]
++ mprj/la_data_out[31] mprj/la_data_out[32] mprj/la_data_out[33] mprj/la_data_out[34]
++ mprj/la_data_out[35] mprj/la_data_out[36] mprj/la_data_out[37] mprj/la_data_out[38]
++ mprj/la_data_out[39] mprj/la_data_out[3] mprj/la_data_out[40] mprj/la_data_out[41]
++ mprj/la_data_out[42] mprj/la_data_out[43] mprj/la_data_out[44] mprj/la_data_out[45]
++ mprj/la_data_out[46] mprj/la_data_out[47] mprj/la_data_out[48] mprj/la_data_out[49]
++ mprj/la_data_out[4] mprj/la_data_out[50] mprj/la_data_out[51] mprj/la_data_out[52]
++ mprj/la_data_out[53] mprj/la_data_out[54] mprj/la_data_out[55] mprj/la_data_out[56]
++ mprj/la_data_out[57] mprj/la_data_out[58] mprj/la_data_out[59] mprj/la_data_out[5]
++ mprj/la_data_out[60] mprj/la_data_out[61] mprj/la_data_out[62] mprj/la_data_out[63]
++ mprj/la_data_out[64] mprj/la_data_out[65] mprj/la_data_out[66] mprj/la_data_out[67]
++ mprj/la_data_out[68] mprj/la_data_out[69] mprj/la_data_out[6] mprj/la_data_out[70]
++ mprj/la_data_out[71] mprj/la_data_out[72] mprj/la_data_out[73] mprj/la_data_out[74]
++ mprj/la_data_out[75] mprj/la_data_out[76] mprj/la_data_out[77] mprj/la_data_out[78]
++ mprj/la_data_out[79] mprj/la_data_out[7] mprj/la_data_out[80] mprj/la_data_out[81]
++ mprj/la_data_out[82] mprj/la_data_out[83] mprj/la_data_out[84] mprj/la_data_out[85]
++ mprj/la_data_out[86] mprj/la_data_out[87] mprj/la_data_out[88] mprj/la_data_out[89]
++ mprj/la_data_out[8] mprj/la_data_out[90] mprj/la_data_out[91] mprj/la_data_out[92]
++ mprj/la_data_out[93] mprj/la_data_out[94] mprj/la_data_out[95] mprj/la_data_out[96]
++ mprj/la_data_out[97] mprj/la_data_out[98] mprj/la_data_out[99] mprj/la_data_out[9]
++ soc/la_output[0] soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103]
++ soc/la_output[104] soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108]
++ soc/la_output[109] soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112]
++ soc/la_output[113] soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117]
++ soc/la_output[118] soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121]
++ soc/la_output[122] soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126]
++ soc/la_output[127] soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15]
++ soc/la_output[16] soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1]
++ soc/la_output[20] soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24]
++ soc/la_output[25] soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29]
++ soc/la_output[2] soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33]
++ soc/la_output[34] soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38]
++ soc/la_output[39] soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42]
++ soc/la_output[43] soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47]
++ soc/la_output[48] soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51]
++ soc/la_output[52] soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56]
++ soc/la_output[57] soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60]
++ soc/la_output[61] soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65]
++ soc/la_output[66] soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6]
++ soc/la_output[70] soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74]
++ soc/la_output[75] soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79]
++ soc/la_output[7] soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83]
++ soc/la_output[84] soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88]
++ soc/la_output[89] soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92]
++ soc/la_output[93] soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97]
++ soc/la_output[98] soc/la_output[99] soc/la_output[9] soc/la_iena[0] soc/la_iena[100]
++ soc/la_iena[101] soc/la_iena[102] soc/la_iena[103] soc/la_iena[104] soc/la_iena[105]
++ soc/la_iena[106] soc/la_iena[107] soc/la_iena[108] soc/la_iena[109] soc/la_iena[10]
++ soc/la_iena[110] soc/la_iena[111] soc/la_iena[112] soc/la_iena[113] soc/la_iena[114]
++ soc/la_iena[115] soc/la_iena[116] soc/la_iena[117] soc/la_iena[118] soc/la_iena[119]
++ soc/la_iena[11] soc/la_iena[120] soc/la_iena[121] soc/la_iena[122] soc/la_iena[123]
++ soc/la_iena[124] soc/la_iena[125] soc/la_iena[126] soc/la_iena[127] soc/la_iena[12]
++ soc/la_iena[13] soc/la_iena[14] soc/la_iena[15] soc/la_iena[16] soc/la_iena[17]
++ soc/la_iena[18] soc/la_iena[19] soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22]
++ soc/la_iena[23] soc/la_iena[24] soc/la_iena[25] soc/la_iena[26] soc/la_iena[27]
++ soc/la_iena[28] soc/la_iena[29] soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32]
++ soc/la_iena[33] soc/la_iena[34] soc/la_iena[35] soc/la_iena[36] soc/la_iena[37]
++ soc/la_iena[38] soc/la_iena[39] soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42]
++ soc/la_iena[43] soc/la_iena[44] soc/la_iena[45] soc/la_iena[46] soc/la_iena[47]
++ soc/la_iena[48] soc/la_iena[49] soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52]
++ soc/la_iena[53] soc/la_iena[54] soc/la_iena[55] soc/la_iena[56] soc/la_iena[57]
++ soc/la_iena[58] soc/la_iena[59] soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62]
++ soc/la_iena[63] soc/la_iena[64] soc/la_iena[65] soc/la_iena[66] soc/la_iena[67]
++ soc/la_iena[68] soc/la_iena[69] soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72]
++ soc/la_iena[73] soc/la_iena[74] soc/la_iena[75] soc/la_iena[76] soc/la_iena[77]
++ soc/la_iena[78] soc/la_iena[79] soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82]
++ soc/la_iena[83] soc/la_iena[84] soc/la_iena[85] soc/la_iena[86] soc/la_iena[87]
++ soc/la_iena[88] soc/la_iena[89] soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92]
++ soc/la_iena[93] soc/la_iena[94] soc/la_iena[95] soc/la_iena[96] soc/la_iena[97]
++ soc/la_iena[98] soc/la_iena[99] soc/la_iena[9] mprj/la_oenb[0] mprj/la_oenb[100]
++ mprj/la_oenb[101] mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105]
++ mprj/la_oenb[106] mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10]
++ mprj/la_oenb[110] mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114]
++ mprj/la_oenb[115] mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119]
++ mprj/la_oenb[11] mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123]
++ mprj/la_oenb[124] mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12]
++ mprj/la_oenb[13] mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17]
++ mprj/la_oenb[18] mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21]
++ mprj/la_oenb[22] mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26]
++ mprj/la_oenb[27] mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30]
++ mprj/la_oenb[31] mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35]
++ mprj/la_oenb[36] mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3]
++ mprj/la_oenb[40] mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44]
++ mprj/la_oenb[45] mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49]
++ mprj/la_oenb[4] mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53]
++ mprj/la_oenb[54] mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58]
++ mprj/la_oenb[59] mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62]
++ mprj/la_oenb[63] mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67]
++ mprj/la_oenb[68] mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71]
++ mprj/la_oenb[72] mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76]
++ mprj/la_oenb[77] mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80]
++ mprj/la_oenb[81] mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85]
++ mprj/la_oenb[86] mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8]
++ mprj/la_oenb[90] mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94]
++ mprj/la_oenb[95] mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99]
++ mprj/la_oenb[9] soc/la_oenb[0] soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102]
++ soc/la_oenb[103] soc/la_oenb[104] soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107]
++ soc/la_oenb[108] soc/la_oenb[109] soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111]
++ soc/la_oenb[112] soc/la_oenb[113] soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116]
++ soc/la_oenb[117] soc/la_oenb[118] soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120]
++ soc/la_oenb[121] soc/la_oenb[122] soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125]
++ soc/la_oenb[126] soc/la_oenb[127] soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14]
++ soc/la_oenb[15] soc/la_oenb[16] soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19]
++ soc/la_oenb[1] soc/la_oenb[20] soc/la_oenb[21] soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24]
++ soc/la_oenb[25] soc/la_oenb[26] soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29]
++ soc/la_oenb[2] soc/la_oenb[30] soc/la_oenb[31] soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34]
++ soc/la_oenb[35] soc/la_oenb[36] soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39]
++ soc/la_oenb[3] soc/la_oenb[40] soc/la_oenb[41] soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44]
++ soc/la_oenb[45] soc/la_oenb[46] soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49]
++ soc/la_oenb[4] soc/la_oenb[50] soc/la_oenb[51] soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54]
++ soc/la_oenb[55] soc/la_oenb[56] soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59]
++ soc/la_oenb[5] soc/la_oenb[60] soc/la_oenb[61] soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64]
++ soc/la_oenb[65] soc/la_oenb[66] soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69]
++ soc/la_oenb[6] soc/la_oenb[70] soc/la_oenb[71] soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74]
++ soc/la_oenb[75] soc/la_oenb[76] soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79]
++ soc/la_oenb[7] soc/la_oenb[80] soc/la_oenb[81] soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84]
++ soc/la_oenb[85] soc/la_oenb[86] soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89]
++ soc/la_oenb[8] soc/la_oenb[90] soc/la_oenb[91] soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94]
++ soc/la_oenb[95] soc/la_oenb[96] soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99]
++ soc/la_oenb[9] soc/mprj_adr_o[0] soc/mprj_adr_o[10] soc/mprj_adr_o[11] soc/mprj_adr_o[12]
++ soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15] soc/mprj_adr_o[16] soc/mprj_adr_o[17]
++ soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1] soc/mprj_adr_o[20] soc/mprj_adr_o[21]
++ soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24] soc/mprj_adr_o[25] soc/mprj_adr_o[26]
++ soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29] soc/mprj_adr_o[2] soc/mprj_adr_o[30]
++ soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4] soc/mprj_adr_o[5] soc/mprj_adr_o[6]
++ soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9] mprj/wbs_adr_i[0] mprj/wbs_adr_i[10]
++ mprj/wbs_adr_i[11] mprj/wbs_adr_i[12] mprj/wbs_adr_i[13] mprj/wbs_adr_i[14] mprj/wbs_adr_i[15]
++ mprj/wbs_adr_i[16] mprj/wbs_adr_i[17] mprj/wbs_adr_i[18] mprj/wbs_adr_i[19] mprj/wbs_adr_i[1]
++ mprj/wbs_adr_i[20] mprj/wbs_adr_i[21] mprj/wbs_adr_i[22] mprj/wbs_adr_i[23] mprj/wbs_adr_i[24]
++ mprj/wbs_adr_i[25] mprj/wbs_adr_i[26] mprj/wbs_adr_i[27] mprj/wbs_adr_i[28] mprj/wbs_adr_i[29]
++ mprj/wbs_adr_i[2] mprj/wbs_adr_i[30] mprj/wbs_adr_i[31] mprj/wbs_adr_i[3] mprj/wbs_adr_i[4]
++ mprj/wbs_adr_i[5] mprj/wbs_adr_i[6] mprj/wbs_adr_i[7] mprj/wbs_adr_i[8] mprj/wbs_adr_i[9]
++ soc/mprj_cyc_o mprj/wbs_cyc_i soc/mprj_dat_o[0] soc/mprj_dat_o[10] soc/mprj_dat_o[11]
++ soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15] soc/mprj_dat_o[16]
++ soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1] soc/mprj_dat_o[20]
++ soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24] soc/mprj_dat_o[25]
++ soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29] soc/mprj_dat_o[2]
++ soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4] soc/mprj_dat_o[5]
++ soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9] mprj/wbs_dat_i[0]
++ mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13] mprj/wbs_dat_i[14]
++ mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18] mprj/wbs_dat_i[19]
++ mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22] mprj/wbs_dat_i[23]
++ mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27] mprj/wbs_dat_i[28]
++ mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31] mprj/wbs_dat_i[3]
++ mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7] mprj/wbs_dat_i[8]
++ mprj/wbs_dat_i[9] soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3]
++ mprj/wbs_sel_i[0] mprj/wbs_sel_i[1] mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] soc/mprj_stb_o
++ mprj/wbs_stb_i soc/mprj_we_o mprj/wbs_we_i soc/mprj_vcc_pwrgood soc/mprj_vdd_pwrgood
++ soc/mprj2_vcc_pwrgood soc/mprj2_vdd_pwrgood mprj/wb_clk_i mprj/user_clock2 soc/user_irq[0]
++ soc/user_irq[1] soc/user_irq[2] mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2]
++ soc/user_irq_ena[0] soc/user_irq_ena[1] soc/user_irq_ena[2] mprj/wb_rst_i vccd_core
++ vssd_core vccd1_core vssd1_core vccd2_core vssd2_core vdda1_core vssa1_core vdda2_core
++ vssa2_core mgmt_protect
+Xrstb_level rstb_level/A soc/resetb vddio_core vssio_core vccd_core vssd_core sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Xgpio_control_bidir_2\[1\] soc/mgmt_in_data[37] soc/flash_io3_oeb soc/mgmt_out_data[37]
++ gpio_control_bidir_2\[1\]/one padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26]
++ padframe/mprj_io_analog_sel[26] padframe/mprj_io_dm[78] padframe/mprj_io_dm[79]
++ padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26] padframe/mprj_io_ib_mode_sel[26]
++ padframe/mprj_io_in[26] padframe/mprj_io_inp_dis[26] padframe/mprj_io_out[26] padframe/mprj_io_oeb[26]
++ padframe/mprj_io_slow_sel[26] padframe/mprj_io_vtrip_sel[26] gpio_control_in_1\[10\]/resetn
++ gpio_control_in_1\[11\]/resetn gpio_control_in_1\[10\]/serial_clock gpio_control_in_1\[11\]/serial_clock
++ soc/mprj_io_loader_data_2 gpio_control_bidir_2\[0\]/serial_data_in mprj/io_in[26]
++ mprj/io_oeb[26] mprj/io_out[26] gpio_control_bidir_2\[1\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[5\] soc/mgmt_in_data[7] gpio_control_in_1\[5\]/one soc/mgmt_in_data[7]
++ gpio_control_in_1\[5\]/one padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7]
++ padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23]
++ padframe/mprj_io_holdover[7] padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_in[7]
++ padframe/mprj_io_inp_dis[7] padframe/mprj_io_out[7] padframe/mprj_io_oeb[7] padframe/mprj_io_slow_sel[7]
++ padframe/mprj_io_vtrip_sel[7] gpio_control_in_2\[7\]/resetn gpio_control_in_2\[8\]/resetn
++ gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[8\]/serial_clock gpio_control_in_1\[5\]/serial_data_in
++ gpio_control_in_1\[6\]/serial_data_in mprj/io_in[7] mprj/io_oeb[7] mprj/io_out[7]
++ gpio_control_in_1\[5\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xcopyright_block_a_0 VSUBS copyright_block_a
+Xgpio_control_in_2\[8\] soc/mgmt_in_data[33] gpio_control_in_2\[8\]/one soc/mgmt_in_data[33]
++ gpio_control_in_2\[8\]/one padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22]
++ padframe/mprj_io_analog_sel[22] padframe/mprj_io_dm[66] padframe/mprj_io_dm[67]
++ padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22] padframe/mprj_io_ib_mode_sel[22]
++ padframe/mprj_io_in[22] padframe/mprj_io_inp_dis[22] padframe/mprj_io_out[22] padframe/mprj_io_oeb[22]
++ padframe/mprj_io_slow_sel[22] padframe/mprj_io_vtrip_sel[22] gpio_control_in_2\[8\]/resetn
++ gpio_control_in_2\[9\]/resetn gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[9\]/serial_clock
++ gpio_control_in_2\[8\]/serial_data_in gpio_control_in_2\[7\]/serial_data_in mprj/io_in[22]
++ mprj/io_oeb[22] mprj/io_out[22] gpio_control_in_2\[8\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[3\] soc/mgmt_in_data[5] gpio_control_in_1\[3\]/one soc/mgmt_in_data[5]
++ gpio_control_in_1\[3\]/one padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5]
++ padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17]
++ padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_in[5]
++ padframe/mprj_io_inp_dis[5] padframe/mprj_io_out[5] padframe/mprj_io_oeb[5] padframe/mprj_io_slow_sel[5]
++ padframe/mprj_io_vtrip_sel[5] gpio_control_in_2\[5\]/resetn gpio_control_in_2\[6\]/resetn
++ gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[6\]/serial_clock gpio_control_in_1\[3\]/serial_data_in
++ gpio_control_in_1\[4\]/serial_data_in mprj/io_in[5] mprj/io_oeb[5] mprj/io_out[5]
++ gpio_control_in_1\[3\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[11\] soc/mgmt_in_data[13] gpio_control_in_1\[11\]/one soc/mgmt_in_data[13]
++ gpio_control_in_1\[11\]/one padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13]
++ padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39] padframe/mprj_io_dm[40]
++ padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13] padframe/mprj_io_ib_mode_sel[13]
++ padframe/mprj_io_in[13] padframe/mprj_io_inp_dis[13] padframe/mprj_io_out[13] padframe/mprj_io_oeb[13]
++ padframe/mprj_io_slow_sel[13] padframe/mprj_io_vtrip_sel[13] gpio_control_in_1\[11\]/resetn
++ gpio_control_in_1\[11\]/resetn_out gpio_control_in_1\[11\]/serial_clock gpio_control_in_1\[11\]/serial_clock_out
++ gpio_control_in_1\[11\]/serial_data_in gpio_control_in_1\[11\]/serial_data_out mprj/io_in[13]
++ mprj/io_oeb[13] mprj/io_out[13] gpio_control_in_1\[11\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[6\] soc/mgmt_in_data[31] gpio_control_in_2\[6\]/one soc/mgmt_in_data[31]
++ gpio_control_in_2\[6\]/one padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20]
++ padframe/mprj_io_analog_sel[20] padframe/mprj_io_dm[60] padframe/mprj_io_dm[61]
++ padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20] padframe/mprj_io_ib_mode_sel[20]
++ padframe/mprj_io_in[20] padframe/mprj_io_inp_dis[20] padframe/mprj_io_out[20] padframe/mprj_io_oeb[20]
++ padframe/mprj_io_slow_sel[20] padframe/mprj_io_vtrip_sel[20] gpio_control_in_2\[6\]/resetn
++ gpio_control_in_2\[7\]/resetn gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[7\]/serial_clock
++ gpio_control_in_2\[6\]/serial_data_in gpio_control_in_2\[5\]/serial_data_in mprj/io_in[20]
++ mprj/io_oeb[20] mprj/io_out[20] gpio_control_in_2\[6\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xcaravan_power_routing_0 VSUBS mprj/io_clamp_high[2] mprj/io_analog[3] vccd1_core
++ vssd_core vdda1_core mprj/io_analog[10] mprj/io_analog[6] mprj/io_clamp_low[0] mprj/io_clamp_low[1]
++ mprj/io_analog[0] mprj/io_clamp_low[2] mprj/io_analog[8] vssd2_core vssio_core mprj/io_analog[6]
++ mprj/io_analog[5] mprj/io_analog[2] vssa2_core mprj/io_analog[7] vddio_core vccd2_core
++ mprj/io_analog[5] vdda2_core mprj/io_analog[9] vssd1_core vccd_core mprj/io_clamp_high[1]
++ mprj/io_analog[4] mprj/io_analog[1] mprj/io_clamp_high[0] mprj/io_analog[4] vssa1_core
++ caravan_power_routing
+Xgpio_control_in_1\[1\] soc/mgmt_in_data[3] gpio_control_in_1\[1\]/one soc/mgmt_in_data[3]
++ gpio_control_in_1\[1\]/one padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3]
++ padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[9] padframe/mprj_io_dm[10] padframe/mprj_io_dm[11]
++ padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_in[3]
++ padframe/mprj_io_inp_dis[3] padframe/mprj_io_out[3] padframe/mprj_io_oeb[3] padframe/mprj_io_slow_sel[3]
++ padframe/mprj_io_vtrip_sel[3] gpio_control_in_2\[3\]/resetn gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock gpio_control_in_1\[1\]/serial_data_in
++ gpio_control_in_1\[2\]/serial_data_in mprj/io_in[3] mprj/io_oeb[3] mprj/io_out[3]
++ gpio_control_in_1\[1\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xmprj mprj/gpio_analog[0] mprj/gpio_analog[10] mprj/gpio_analog[11] mprj/gpio_analog[12]
++ mprj/gpio_analog[13] mprj/gpio_analog[14] mprj/gpio_analog[15] mprj/gpio_analog[16]
++ mprj/gpio_analog[17] mprj/gpio_analog[1] mprj/gpio_analog[2] mprj/gpio_analog[3]
++ mprj/gpio_analog[4] mprj/gpio_analog[5] mprj/gpio_analog[6] mprj/gpio_analog[7]
++ mprj/gpio_analog[8] mprj/gpio_analog[9] mprj/gpio_noesd[0] mprj/gpio_noesd[10] mprj/gpio_noesd[11]
++ mprj/gpio_noesd[12] mprj/gpio_noesd[13] mprj/gpio_noesd[14] mprj/gpio_noesd[15]
++ mprj/gpio_noesd[16] mprj/gpio_noesd[17] mprj/gpio_noesd[1] mprj/gpio_noesd[2] mprj/gpio_noesd[3]
++ mprj/gpio_noesd[4] mprj/gpio_noesd[5] mprj/gpio_noesd[6] mprj/gpio_noesd[7] mprj/gpio_noesd[8]
++ mprj/gpio_noesd[9] mprj/io_analog[0] mprj/io_analog[10] mprj/io_analog[1] mprj/io_analog[2]
++ mprj/io_analog[3] mprj/io_analog[7] mprj/io_analog[8] mprj/io_analog[9] mprj/io_analog[4]
++ mprj/io_analog[5] mprj/io_analog[6] mprj/io_clamp_high[0] mprj/io_clamp_high[1]
++ mprj/io_clamp_high[2] mprj/io_clamp_low[0] mprj/io_clamp_low[1] mprj/io_clamp_low[2]
++ mprj/io_in[0] mprj/io_in[10] mprj/io_in[11] mprj/io_in[12] mprj/io_in[13] mprj/io_in[14]
++ mprj/io_in[15] mprj/io_in[16] mprj/io_in[17] mprj/io_in[18] mprj/io_in[19] mprj/io_in[1]
++ mprj/io_in[20] mprj/io_in[21] mprj/io_in[22] mprj/io_in[23] mprj/io_in[24] mprj/io_in[25]
++ mprj/io_in[26] mprj/io_in[2] mprj/io_in[3] mprj/io_in[4] mprj/io_in[5] mprj/io_in[6]
++ mprj/io_in[7] mprj/io_in[8] mprj/io_in[9] mprj/io_in_3v3[0] mprj/io_in_3v3[10] mprj/io_in_3v3[11]
++ mprj/io_in_3v3[12] mprj/io_in_3v3[13] mprj/io_in_3v3[14] mprj/io_in_3v3[15] mprj/io_in_3v3[16]
++ mprj/io_in_3v3[17] mprj/io_in_3v3[18] mprj/io_in_3v3[19] mprj/io_in_3v3[1] mprj/io_in_3v3[20]
++ mprj/io_in_3v3[21] mprj/io_in_3v3[22] mprj/io_in_3v3[23] mprj/io_in_3v3[24] mprj/io_in_3v3[25]
++ mprj/io_in_3v3[26] mprj/io_in_3v3[2] mprj/io_in_3v3[3] mprj/io_in_3v3[4] mprj/io_in_3v3[5]
++ mprj/io_in_3v3[6] mprj/io_in_3v3[7] mprj/io_in_3v3[8] mprj/io_in_3v3[9] mprj/io_oeb[0]
++ mprj/io_oeb[10] mprj/io_oeb[11] mprj/io_oeb[12] mprj/io_oeb[13] mprj/io_oeb[14]
++ mprj/io_oeb[15] mprj/io_oeb[16] mprj/io_oeb[17] mprj/io_oeb[18] mprj/io_oeb[19]
++ mprj/io_oeb[1] mprj/io_oeb[20] mprj/io_oeb[21] mprj/io_oeb[22] mprj/io_oeb[23] mprj/io_oeb[24]
++ mprj/io_oeb[25] mprj/io_oeb[26] mprj/io_oeb[2] mprj/io_oeb[3] mprj/io_oeb[4] mprj/io_oeb[5]
++ mprj/io_oeb[6] mprj/io_oeb[7] mprj/io_oeb[8] mprj/io_oeb[9] mprj/io_out[0] mprj/io_out[10]
++ mprj/io_out[11] mprj/io_out[12] mprj/io_out[13] mprj/io_out[14] mprj/io_out[15]
++ mprj/io_out[16] mprj/io_out[17] mprj/io_out[18] mprj/io_out[19] mprj/io_out[1] mprj/io_out[20]
++ mprj/io_out[21] mprj/io_out[22] mprj/io_out[23] mprj/io_out[24] mprj/io_out[25]
++ mprj/io_out[26] mprj/io_out[2] mprj/io_out[3] mprj/io_out[4] mprj/io_out[5] mprj/io_out[6]
++ mprj/io_out[7] mprj/io_out[8] mprj/io_out[9] mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] mprj/la_data_out[0] mprj/la_data_out[100]
++ mprj/la_data_out[101] mprj/la_data_out[102] mprj/la_data_out[103] mprj/la_data_out[104]
++ mprj/la_data_out[105] mprj/la_data_out[106] mprj/la_data_out[107] mprj/la_data_out[108]
++ mprj/la_data_out[109] mprj/la_data_out[10] mprj/la_data_out[110] mprj/la_data_out[111]
++ mprj/la_data_out[112] mprj/la_data_out[113] mprj/la_data_out[114] mprj/la_data_out[115]
++ mprj/la_data_out[116] mprj/la_data_out[117] mprj/la_data_out[118] mprj/la_data_out[119]
++ mprj/la_data_out[11] mprj/la_data_out[120] mprj/la_data_out[121] mprj/la_data_out[122]
++ mprj/la_data_out[123] mprj/la_data_out[124] mprj/la_data_out[125] mprj/la_data_out[126]
++ mprj/la_data_out[127] mprj/la_data_out[12] mprj/la_data_out[13] mprj/la_data_out[14]
++ mprj/la_data_out[15] mprj/la_data_out[16] mprj/la_data_out[17] mprj/la_data_out[18]
++ mprj/la_data_out[19] mprj/la_data_out[1] mprj/la_data_out[20] mprj/la_data_out[21]
++ mprj/la_data_out[22] mprj/la_data_out[23] mprj/la_data_out[24] mprj/la_data_out[25]
++ mprj/la_data_out[26] mprj/la_data_out[27] mprj/la_data_out[28] mprj/la_data_out[29]
++ mprj/la_data_out[2] mprj/la_data_out[30] mprj/la_data_out[31] mprj/la_data_out[32]
++ mprj/la_data_out[33] mprj/la_data_out[34] mprj/la_data_out[35] mprj/la_data_out[36]
++ mprj/la_data_out[37] mprj/la_data_out[38] mprj/la_data_out[39] mprj/la_data_out[3]
++ mprj/la_data_out[40] mprj/la_data_out[41] mprj/la_data_out[42] mprj/la_data_out[43]
++ mprj/la_data_out[44] mprj/la_data_out[45] mprj/la_data_out[46] mprj/la_data_out[47]
++ mprj/la_data_out[48] mprj/la_data_out[49] mprj/la_data_out[4] mprj/la_data_out[50]
++ mprj/la_data_out[51] mprj/la_data_out[52] mprj/la_data_out[53] mprj/la_data_out[54]
++ mprj/la_data_out[55] mprj/la_data_out[56] mprj/la_data_out[57] mprj/la_data_out[58]
++ mprj/la_data_out[59] mprj/la_data_out[5] mprj/la_data_out[60] mprj/la_data_out[61]
++ mprj/la_data_out[62] mprj/la_data_out[63] mprj/la_data_out[64] mprj/la_data_out[65]
++ mprj/la_data_out[66] mprj/la_data_out[67] mprj/la_data_out[68] mprj/la_data_out[69]
++ mprj/la_data_out[6] mprj/la_data_out[70] mprj/la_data_out[71] mprj/la_data_out[72]
++ mprj/la_data_out[73] mprj/la_data_out[74] mprj/la_data_out[75] mprj/la_data_out[76]
++ mprj/la_data_out[77] mprj/la_data_out[78] mprj/la_data_out[79] mprj/la_data_out[7]
++ mprj/la_data_out[80] mprj/la_data_out[81] mprj/la_data_out[82] mprj/la_data_out[83]
++ mprj/la_data_out[84] mprj/la_data_out[85] mprj/la_data_out[86] mprj/la_data_out[87]
++ mprj/la_data_out[88] mprj/la_data_out[89] mprj/la_data_out[8] mprj/la_data_out[90]
++ mprj/la_data_out[91] mprj/la_data_out[92] mprj/la_data_out[93] mprj/la_data_out[94]
++ mprj/la_data_out[95] mprj/la_data_out[96] mprj/la_data_out[97] mprj/la_data_out[98]
++ mprj/la_data_out[99] mprj/la_data_out[9] mprj/la_oenb[0] mprj/la_oenb[100] mprj/la_oenb[101]
++ mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105] mprj/la_oenb[106]
++ mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10] mprj/la_oenb[110]
++ mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114] mprj/la_oenb[115]
++ mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119] mprj/la_oenb[11]
++ mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123] mprj/la_oenb[124]
++ mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12] mprj/la_oenb[13]
++ mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17] mprj/la_oenb[18]
++ mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21] mprj/la_oenb[22]
++ mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26] mprj/la_oenb[27]
++ mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30] mprj/la_oenb[31]
++ mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35] mprj/la_oenb[36]
++ mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3] mprj/la_oenb[40]
++ mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44] mprj/la_oenb[45]
++ mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49] mprj/la_oenb[4]
++ mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53] mprj/la_oenb[54]
++ mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58] mprj/la_oenb[59]
++ mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62] mprj/la_oenb[63]
++ mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67] mprj/la_oenb[68]
++ mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71] mprj/la_oenb[72]
++ mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76] mprj/la_oenb[77]
++ mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80] mprj/la_oenb[81]
++ mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85] mprj/la_oenb[86]
++ mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8] mprj/la_oenb[90]
++ mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94] mprj/la_oenb[95]
++ mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99] mprj/la_oenb[9]
++ mprj/user_clock2 mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2] vccd1_core vccd2_core
++ vdda1_core vdda2_core vssa1_core vssa2_core vssd1_core vssd2_core mprj/wb_clk_i
++ mprj/wb_rst_i soc/mprj_ack_i mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11]
++ mprj/wbs_adr_i[12] mprj/wbs_adr_i[13] mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16]
++ mprj/wbs_adr_i[17] mprj/wbs_adr_i[18] mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20]
++ mprj/wbs_adr_i[21] mprj/wbs_adr_i[22] mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25]
++ mprj/wbs_adr_i[26] mprj/wbs_adr_i[27] mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2]
++ mprj/wbs_adr_i[30] mprj/wbs_adr_i[31] mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5]
++ mprj/wbs_adr_i[6] mprj/wbs_adr_i[7] mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] mprj/wbs_cyc_i
++ mprj/wbs_dat_i[0] mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13]
++ mprj/wbs_dat_i[14] mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18]
++ mprj/wbs_dat_i[19] mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22]
++ mprj/wbs_dat_i[23] mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27]
++ mprj/wbs_dat_i[28] mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31]
++ mprj/wbs_dat_i[3] mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7]
++ mprj/wbs_dat_i[8] mprj/wbs_dat_i[9] soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11]
++ soc/mprj_dat_i[12] soc/mprj_dat_i[13] soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16]
++ soc/mprj_dat_i[17] soc/mprj_dat_i[18] soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20]
++ soc/mprj_dat_i[21] soc/mprj_dat_i[22] soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25]
++ soc/mprj_dat_i[26] soc/mprj_dat_i[27] soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2]
++ soc/mprj_dat_i[30] soc/mprj_dat_i[31] soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5]
++ soc/mprj_dat_i[6] soc/mprj_dat_i[7] soc/mprj_dat_i[8] soc/mprj_dat_i[9] mprj/wbs_sel_i[0]
++ mprj/wbs_sel_i[1] mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] mprj/wbs_stb_i mprj/wbs_we_i
++ user_analog_project_wrapper
+Xgpio_control_in_2\[4\] soc/mgmt_in_data[29] gpio_control_in_2\[4\]/one soc/mgmt_in_data[29]
++ gpio_control_in_2\[4\]/one padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18]
++ padframe/mprj_io_analog_sel[18] padframe/mprj_io_dm[54] padframe/mprj_io_dm[55]
++ padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18] padframe/mprj_io_ib_mode_sel[18]
++ padframe/mprj_io_in[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_out[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18] gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[5\]/resetn gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock
++ gpio_control_in_2\[4\]/serial_data_in gpio_control_in_2\[3\]/serial_data_in mprj/io_in[18]
++ mprj/io_oeb[18] mprj/io_out[18] gpio_control_in_2\[4\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_bidir_1\[1\] soc/mgmt_in_data[1] soc/sdo_outenb soc/sdo_out gpio_control_bidir_1\[1\]/one
++ padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1] padframe/mprj_io_analog_sel[1]
++ padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5] padframe/mprj_io_holdover[1]
++ padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_in[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_out[1] padframe/mprj_io_oeb[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ gpio_control_in_2\[1\]/resetn gpio_control_in_2\[2\]/resetn gpio_control_in_2\[1\]/serial_clock
++ gpio_control_in_2\[2\]/serial_clock gpio_control_bidir_1\[1\]/serial_data_in gpio_control_in_1\[0\]/serial_data_in
++ mprj/io_in[1] mprj/io_oeb[1] mprj/io_out[1] gpio_control_bidir_1\[1\]/zero vccd_core
++ vssd_core vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[2\] soc/mgmt_in_data[27] gpio_control_in_2\[2\]/one soc/mgmt_in_data[27]
++ gpio_control_in_2\[2\]/one padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16]
++ padframe/mprj_io_analog_sel[16] padframe/mprj_io_dm[48] padframe/mprj_io_dm[49]
++ padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16] padframe/mprj_io_ib_mode_sel[16]
++ padframe/mprj_io_in[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_out[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16] gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[3\]/resetn gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock
++ gpio_control_in_2\[2\]/serial_data_in gpio_control_in_2\[1\]/serial_data_in mprj/io_in[16]
++ mprj/io_oeb[16] mprj/io_out[16] gpio_control_in_2\[2\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xstorage soc/mgmt_addr[0] soc/mgmt_addr[1] soc/mgmt_addr[2] soc/mgmt_addr[3] soc/mgmt_addr[4]
++ soc/mgmt_addr[5] soc/mgmt_addr[6] soc/mgmt_addr[7] soc/mgmt_addr_ro[0] soc/mgmt_addr_ro[1]
++ soc/mgmt_addr_ro[2] soc/mgmt_addr_ro[3] soc/mgmt_addr_ro[4] soc/mgmt_addr_ro[5]
++ soc/mgmt_addr_ro[6] soc/mgmt_addr_ro[7] soc/core_clk soc/mgmt_ena[0] soc/mgmt_ena[1]
++ soc/mgmt_ena_ro soc/mgmt_rdata[0] soc/mgmt_rdata[10] soc/mgmt_rdata[11] soc/mgmt_rdata[12]
++ soc/mgmt_rdata[13] soc/mgmt_rdata[14] soc/mgmt_rdata[15] soc/mgmt_rdata[16] soc/mgmt_rdata[17]
++ soc/mgmt_rdata[18] soc/mgmt_rdata[19] soc/mgmt_rdata[1] soc/mgmt_rdata[20] soc/mgmt_rdata[21]
++ soc/mgmt_rdata[22] soc/mgmt_rdata[23] soc/mgmt_rdata[24] soc/mgmt_rdata[25] soc/mgmt_rdata[26]
++ soc/mgmt_rdata[27] soc/mgmt_rdata[28] soc/mgmt_rdata[29] soc/mgmt_rdata[2] soc/mgmt_rdata[30]
++ soc/mgmt_rdata[31] soc/mgmt_rdata[32] soc/mgmt_rdata[33] soc/mgmt_rdata[34] soc/mgmt_rdata[35]
++ soc/mgmt_rdata[36] soc/mgmt_rdata[37] soc/mgmt_rdata[38] soc/mgmt_rdata[39] soc/mgmt_rdata[3]
++ soc/mgmt_rdata[40] soc/mgmt_rdata[41] soc/mgmt_rdata[42] soc/mgmt_rdata[43] soc/mgmt_rdata[44]
++ soc/mgmt_rdata[45] soc/mgmt_rdata[46] soc/mgmt_rdata[47] soc/mgmt_rdata[48] soc/mgmt_rdata[49]
++ soc/mgmt_rdata[4] soc/mgmt_rdata[50] soc/mgmt_rdata[51] soc/mgmt_rdata[52] soc/mgmt_rdata[53]
++ soc/mgmt_rdata[54] soc/mgmt_rdata[55] soc/mgmt_rdata[56] soc/mgmt_rdata[57] soc/mgmt_rdata[58]
++ soc/mgmt_rdata[59] soc/mgmt_rdata[5] soc/mgmt_rdata[60] soc/mgmt_rdata[61] soc/mgmt_rdata[62]
++ soc/mgmt_rdata[63] soc/mgmt_rdata[6] soc/mgmt_rdata[7] soc/mgmt_rdata[8] soc/mgmt_rdata[9]
++ soc/mgmt_rdata_ro[0] soc/mgmt_rdata_ro[10] soc/mgmt_rdata_ro[11] soc/mgmt_rdata_ro[12]
++ soc/mgmt_rdata_ro[13] soc/mgmt_rdata_ro[14] soc/mgmt_rdata_ro[15] soc/mgmt_rdata_ro[16]
++ soc/mgmt_rdata_ro[17] soc/mgmt_rdata_ro[18] soc/mgmt_rdata_ro[19] soc/mgmt_rdata_ro[1]
++ soc/mgmt_rdata_ro[20] soc/mgmt_rdata_ro[21] soc/mgmt_rdata_ro[22] soc/mgmt_rdata_ro[23]
++ soc/mgmt_rdata_ro[24] soc/mgmt_rdata_ro[25] soc/mgmt_rdata_ro[26] soc/mgmt_rdata_ro[27]
++ soc/mgmt_rdata_ro[28] soc/mgmt_rdata_ro[29] soc/mgmt_rdata_ro[2] soc/mgmt_rdata_ro[30]
++ soc/mgmt_rdata_ro[31] soc/mgmt_rdata_ro[3] soc/mgmt_rdata_ro[4] soc/mgmt_rdata_ro[5]
++ soc/mgmt_rdata_ro[6] soc/mgmt_rdata_ro[7] soc/mgmt_rdata_ro[8] soc/mgmt_rdata_ro[9]
++ soc/mgmt_wdata[0] soc/mgmt_wdata[10] soc/mgmt_wdata[11] soc/mgmt_wdata[12] soc/mgmt_wdata[13]
++ soc/mgmt_wdata[14] soc/mgmt_wdata[15] soc/mgmt_wdata[16] soc/mgmt_wdata[17] soc/mgmt_wdata[18]
++ soc/mgmt_wdata[19] soc/mgmt_wdata[1] soc/mgmt_wdata[20] soc/mgmt_wdata[21] soc/mgmt_wdata[22]
++ soc/mgmt_wdata[23] soc/mgmt_wdata[24] soc/mgmt_wdata[25] soc/mgmt_wdata[26] soc/mgmt_wdata[27]
++ soc/mgmt_wdata[28] soc/mgmt_wdata[29] soc/mgmt_wdata[2] soc/mgmt_wdata[30] soc/mgmt_wdata[31]
++ soc/mgmt_wdata[3] soc/mgmt_wdata[4] soc/mgmt_wdata[5] soc/mgmt_wdata[6] soc/mgmt_wdata[7]
++ soc/mgmt_wdata[8] soc/mgmt_wdata[9] soc/mgmt_wen[0] soc/mgmt_wen[1] soc/mgmt_wen_mask[0]
++ soc/mgmt_wen_mask[1] soc/mgmt_wen_mask[2] soc/mgmt_wen_mask[3] soc/mgmt_wen_mask[4]
++ soc/mgmt_wen_mask[5] soc/mgmt_wen_mask[6] soc/mgmt_wen_mask[7] vccd_core vssd_core
++ storage
+Xgpio_control_in_1\[8\] soc/mgmt_in_data[10] gpio_control_in_1\[8\]/one soc/mgmt_in_data[10]
++ gpio_control_in_1\[8\]/one padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10]
++ padframe/mprj_io_analog_sel[10] padframe/mprj_io_dm[30] padframe/mprj_io_dm[31]
++ padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10] padframe/mprj_io_ib_mode_sel[10]
++ padframe/mprj_io_in[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_out[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10] gpio_control_in_1\[8\]/resetn
++ gpio_control_in_1\[9\]/resetn gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[9\]/serial_clock
++ gpio_control_in_1\[8\]/serial_data_in gpio_control_in_1\[9\]/serial_data_in mprj/io_in[10]
++ mprj/io_oeb[10] mprj/io_out[10] gpio_control_in_1\[8\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+.ends
+
diff --git a/caravel/spi/lvs/caravel.spice b/caravel/spi/lvs/caravel.spice
new file mode 100644
index 0000000..799a5df
--- /dev/null
+++ b/caravel/spi/lvs/caravel.spice
@@ -0,0 +1,1953 @@
+* NGSPICE file created from caravel.ext - technology: sky130A
+
+* Black-box entry subcircuit for gpio_control_block abstract view
+.subckt gpio_control_block mgmt_gpio_in mgmt_gpio_oeb mgmt_gpio_out one pad_gpio_ana_en
++ pad_gpio_ana_pol pad_gpio_ana_sel pad_gpio_dm[0] pad_gpio_dm[1] pad_gpio_dm[2] pad_gpio_holdover
++ pad_gpio_ib_mode_sel pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel
++ pad_gpio_vtrip_sel resetn resetn_out serial_clock serial_clock_out serial_data_in
++ serial_data_out user_gpio_in user_gpio_oeb user_gpio_out zero vccd vssd vccd1 vssd1
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_5um abstract view
+.subckt sky130_ef_io__com_bus_slice_5um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_10um abstract view
+.subckt sky130_ef_io__com_bus_slice_10um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_20um abstract view
+.subckt sky130_ef_io__com_bus_slice_20um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__gpiov2_pad_wrapped abstract view
+.subckt sky130_ef_io__gpiov2_pad_wrapped IN_H PAD_A_NOESD_H PAD_A_ESD_0_H PAD_A_ESD_1_H
++ PAD DM[2] DM[1] DM[0] HLD_H_N IN INP_DIS IB_MODE_SEL ENABLE_H ENABLE_VDDA_H ENABLE_INP_H
++ OE_N TIE_HI_ESD TIE_LO_ESD SLOW VTRIP_SEL HLD_OVR ANALOG_EN ANALOG_SEL ENABLE_VDDIO
++ ENABLE_VSWITCH_H ANALOG_POL OUT AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q VCCHIB
++ VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__com_bus_slice_1um abstract view
+.subckt sky130_ef_io__com_bus_slice_1um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vccd_lvc_clamped_pad abstract view
+.subckt sky130_ef_io__vccd_lvc_clamped_pad AMUXBUS_A AMUXBUS_B VCCD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__disconnect_vdda_slice_5um abstract view
+.subckt sky130_ef_io__disconnect_vdda_slice_5um AMUXBUS_A AMUXBUS_B VSWITCH VDDIO_Q
++ VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__corner_pad abstract view
+.subckt sky130_ef_io__corner_pad AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH VDDIO_Q VCCHIB
++ VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vddio_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vddio_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VDDIO_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssio_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vssio_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VSSIO_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um abstract view
+.subckt sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um AMUXBUS_A AMUXBUS_B
++ VSSA VDDA VDDIO_Q VDDIO VCCD VSSIO VSSD VSSIO_Q VSWITCH VCCHIB
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vdda_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vdda_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VDDA_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vccd_lvc_clamped2_pad abstract view
+.subckt sky130_ef_io__vccd_lvc_clamped2_pad AMUXBUS_A AMUXBUS_B VCCD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssa_hvc_clamped_pad abstract view
+.subckt sky130_ef_io__vssa_hvc_clamped_pad AMUXBUS_A AMUXBUS_B VSSA_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__disconnect_vccd_slice_5um abstract view
+.subckt sky130_ef_io__disconnect_vccd_slice_5um AMUXBUS_A AMUXBUS_B VSSA VDDA VSWITCH
++ VDDIO_Q VCCHIB VDDIO VSSIO VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_fd_io__top_xres4v2 abstract view
+.subckt sky130_fd_io__top_xres4v2 PAD_A_ESD_H XRES_H_N FILT_IN_H ENABLE_VDDIO TIE_WEAK_HI_H
++ ENABLE_H PULLUP_H EN_VDDIO_SIG_H TIE_LO_ESD TIE_HI_ESD DISABLE_PULLUP_H INP_SEL_H
++ VSSIO VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO VSWITCH VDDA VCCD VCCHIB VSSIO_Q
++ PAD
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssd_lvc_clamped2_pad abstract view
+.subckt sky130_ef_io__vssd_lvc_clamped2_pad AMUXBUS_A AMUXBUS_B VSSD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for sky130_ef_io__vssd_lvc_clamped_pad abstract view
+.subckt sky130_ef_io__vssd_lvc_clamped_pad AMUXBUS_A AMUXBUS_B VSSD_PAD VSSA VDDA
++ VSWITCH VDDIO_Q VCCHIB VDDIO VCCD VSSIO VSSD VSSIO_Q
+.ends
+
+* Black-box entry subcircuit for chip_io abstract view
+.subckt chip_io clock clock_core por flash_clk flash_clk_core flash_clk_ieb_core flash_clk_oeb_core
++ flash_csb flash_csb_core flash_csb_ieb_core flash_csb_oeb_core flash_io0 flash_io0_di_core
++ flash_io0_do_core flash_io0_ieb_core flash_io0_oeb_core flash_io1 flash_io1_di_core
++ flash_io1_do_core flash_io1_ieb_core flash_io1_oeb_core gpio gpio_in_core gpio_inenb_core
++ gpio_mode0_core gpio_mode1_core gpio_out_core gpio_outenb_core vccd_pad vdda_pad
++ vddio_pad vddio_pad2 vssa_pad vssd_pad vssio_pad vssio_pad2 mprj_io[0] mprj_io_analog_en[0]
++ mprj_io_analog_pol[0] mprj_io_analog_sel[0] mprj_io_dm[0] mprj_io_dm[1] mprj_io_dm[2]
++ mprj_io_holdover[0] mprj_io_ib_mode_sel[0] mprj_io_inp_dis[0] mprj_io_oeb[0] mprj_io_out[0]
++ mprj_io_slow_sel[0] mprj_io_vtrip_sel[0] mprj_io_in[0] mprj_analog_io[3] mprj_io[10]
++ mprj_io_analog_en[10] mprj_io_analog_pol[10] mprj_io_analog_sel[10] mprj_io_dm[30]
++ mprj_io_dm[31] mprj_io_dm[32] mprj_io_holdover[10] mprj_io_ib_mode_sel[10] mprj_io_inp_dis[10]
++ mprj_io_oeb[10] mprj_io_out[10] mprj_io_slow_sel[10] mprj_io_vtrip_sel[10] mprj_io_in[10]
++ mprj_analog_io[4] mprj_io[11] mprj_io_analog_en[11] mprj_io_analog_pol[11] mprj_io_analog_sel[11]
++ mprj_io_dm[33] mprj_io_dm[34] mprj_io_dm[35] mprj_io_holdover[11] mprj_io_ib_mode_sel[11]
++ mprj_io_inp_dis[11] mprj_io_oeb[11] mprj_io_out[11] mprj_io_slow_sel[11] mprj_io_vtrip_sel[11]
++ mprj_io_in[11] mprj_analog_io[5] mprj_io[12] mprj_io_analog_en[12] mprj_io_analog_pol[12]
++ mprj_io_analog_sel[12] mprj_io_dm[36] mprj_io_dm[37] mprj_io_dm[38] mprj_io_holdover[12]
++ mprj_io_ib_mode_sel[12] mprj_io_inp_dis[12] mprj_io_oeb[12] mprj_io_out[12] mprj_io_slow_sel[12]
++ mprj_io_vtrip_sel[12] mprj_io_in[12] mprj_analog_io[6] mprj_io[13] mprj_io_analog_en[13]
++ mprj_io_analog_pol[13] mprj_io_analog_sel[13] mprj_io_dm[39] mprj_io_dm[40] mprj_io_dm[41]
++ mprj_io_holdover[13] mprj_io_ib_mode_sel[13] mprj_io_inp_dis[13] mprj_io_oeb[13]
++ mprj_io_out[13] mprj_io_slow_sel[13] mprj_io_vtrip_sel[13] mprj_io_in[13] mprj_analog_io[7]
++ mprj_io[14] mprj_io_analog_en[14] mprj_io_analog_pol[14] mprj_io_analog_sel[14]
++ mprj_io_dm[42] mprj_io_dm[43] mprj_io_dm[44] mprj_io_holdover[14] mprj_io_ib_mode_sel[14]
++ mprj_io_inp_dis[14] mprj_io_oeb[14] mprj_io_out[14] mprj_io_slow_sel[14] mprj_io_vtrip_sel[14]
++ mprj_io_in[14] mprj_analog_io[8] mprj_io[15] mprj_io_analog_en[15] mprj_io_analog_pol[15]
++ mprj_io_analog_sel[15] mprj_io_dm[45] mprj_io_dm[46] mprj_io_dm[47] mprj_io_holdover[15]
++ mprj_io_ib_mode_sel[15] mprj_io_inp_dis[15] mprj_io_oeb[15] mprj_io_out[15] mprj_io_slow_sel[15]
++ mprj_io_vtrip_sel[15] mprj_io_in[15] mprj_analog_io[9] mprj_io[16] mprj_io_analog_en[16]
++ mprj_io_analog_pol[16] mprj_io_analog_sel[16] mprj_io_dm[48] mprj_io_dm[49] mprj_io_dm[50]
++ mprj_io_holdover[16] mprj_io_ib_mode_sel[16] mprj_io_inp_dis[16] mprj_io_oeb[16]
++ mprj_io_out[16] mprj_io_slow_sel[16] mprj_io_vtrip_sel[16] mprj_io_in[16] mprj_analog_io[10]
++ mprj_io[17] mprj_io_analog_en[17] mprj_io_analog_pol[17] mprj_io_analog_sel[17]
++ mprj_io_dm[51] mprj_io_dm[52] mprj_io_dm[53] mprj_io_holdover[17] mprj_io_ib_mode_sel[17]
++ mprj_io_inp_dis[17] mprj_io_oeb[17] mprj_io_out[17] mprj_io_slow_sel[17] mprj_io_vtrip_sel[17]
++ mprj_io_in[17] mprj_analog_io[11] mprj_io[18] mprj_io_analog_en[18] mprj_io_analog_pol[18]
++ mprj_io_analog_sel[18] mprj_io_dm[54] mprj_io_dm[55] mprj_io_dm[56] mprj_io_holdover[18]
++ mprj_io_ib_mode_sel[18] mprj_io_inp_dis[18] mprj_io_oeb[18] mprj_io_out[18] mprj_io_slow_sel[18]
++ mprj_io_vtrip_sel[18] mprj_io_in[18] mprj_io[1] mprj_io_analog_en[1] mprj_io_analog_pol[1]
++ mprj_io_analog_sel[1] mprj_io_dm[3] mprj_io_dm[4] mprj_io_dm[5] mprj_io_holdover[1]
++ mprj_io_ib_mode_sel[1] mprj_io_inp_dis[1] mprj_io_oeb[1] mprj_io_out[1] mprj_io_slow_sel[1]
++ mprj_io_vtrip_sel[1] mprj_io_in[1] mprj_io[2] mprj_io_analog_en[2] mprj_io_analog_pol[2]
++ mprj_io_analog_sel[2] mprj_io_dm[6] mprj_io_dm[7] mprj_io_dm[8] mprj_io_holdover[2]
++ mprj_io_ib_mode_sel[2] mprj_io_inp_dis[2] mprj_io_oeb[2] mprj_io_out[2] mprj_io_slow_sel[2]
++ mprj_io_vtrip_sel[2] mprj_io_in[2] mprj_io[3] mprj_io_analog_en[3] mprj_io_analog_pol[3]
++ mprj_io_analog_sel[3] mprj_io_dm[10] mprj_io_dm[11] mprj_io_dm[9] mprj_io_holdover[3]
++ mprj_io_ib_mode_sel[3] mprj_io_inp_dis[3] mprj_io_oeb[3] mprj_io_out[3] mprj_io_slow_sel[3]
++ mprj_io_vtrip_sel[3] mprj_io_in[3] mprj_io[4] mprj_io_analog_en[4] mprj_io_analog_pol[4]
++ mprj_io_analog_sel[4] mprj_io_dm[12] mprj_io_dm[13] mprj_io_dm[14] mprj_io_holdover[4]
++ mprj_io_ib_mode_sel[4] mprj_io_inp_dis[4] mprj_io_oeb[4] mprj_io_out[4] mprj_io_slow_sel[4]
++ mprj_io_vtrip_sel[4] mprj_io_in[4] mprj_io[5] mprj_io_analog_en[5] mprj_io_analog_pol[5]
++ mprj_io_analog_sel[5] mprj_io_dm[15] mprj_io_dm[16] mprj_io_dm[17] mprj_io_holdover[5]
++ mprj_io_ib_mode_sel[5] mprj_io_inp_dis[5] mprj_io_oeb[5] mprj_io_out[5] mprj_io_slow_sel[5]
++ mprj_io_vtrip_sel[5] mprj_io_in[5] mprj_io[6] mprj_io_analog_en[6] mprj_io_analog_pol[6]
++ mprj_io_analog_sel[6] mprj_io_dm[18] mprj_io_dm[19] mprj_io_dm[20] mprj_io_holdover[6]
++ mprj_io_ib_mode_sel[6] mprj_io_inp_dis[6] mprj_io_oeb[6] mprj_io_out[6] mprj_io_slow_sel[6]
++ mprj_io_vtrip_sel[6] mprj_io_in[6] mprj_analog_io[0] mprj_io[7] mprj_io_analog_en[7]
++ mprj_io_analog_pol[7] mprj_io_analog_sel[7] mprj_io_dm[21] mprj_io_dm[22] mprj_io_dm[23]
++ mprj_io_holdover[7] mprj_io_ib_mode_sel[7] mprj_io_inp_dis[7] mprj_io_oeb[7] mprj_io_out[7]
++ mprj_io_slow_sel[7] mprj_io_vtrip_sel[7] mprj_io_in[7] mprj_analog_io[1] mprj_io[8]
++ mprj_io_analog_en[8] mprj_io_analog_pol[8] mprj_io_analog_sel[8] mprj_io_dm[24]
++ mprj_io_dm[25] mprj_io_dm[26] mprj_io_holdover[8] mprj_io_ib_mode_sel[8] mprj_io_inp_dis[8]
++ mprj_io_oeb[8] mprj_io_out[8] mprj_io_slow_sel[8] mprj_io_vtrip_sel[8] mprj_io_in[8]
++ mprj_analog_io[2] mprj_io[9] mprj_io_analog_en[9] mprj_io_analog_pol[9] mprj_io_analog_sel[9]
++ mprj_io_dm[27] mprj_io_dm[28] mprj_io_dm[29] mprj_io_holdover[9] mprj_io_ib_mode_sel[9]
++ mprj_io_inp_dis[9] mprj_io_oeb[9] mprj_io_out[9] mprj_io_slow_sel[9] mprj_io_vtrip_sel[9]
++ mprj_io_in[9] mprj_analog_io[12] mprj_io[19] mprj_io_analog_en[19] mprj_io_analog_pol[19]
++ mprj_io_analog_sel[19] mprj_io_dm[57] mprj_io_dm[58] mprj_io_dm[59] mprj_io_holdover[19]
++ mprj_io_ib_mode_sel[19] mprj_io_inp_dis[19] mprj_io_oeb[19] mprj_io_out[19] mprj_io_slow_sel[19]
++ mprj_io_vtrip_sel[19] mprj_io_in[19] mprj_analog_io[22] mprj_io[29] mprj_io_analog_en[29]
++ mprj_io_analog_pol[29] mprj_io_analog_sel[29] mprj_io_dm[87] mprj_io_dm[88] mprj_io_dm[89]
++ mprj_io_holdover[29] mprj_io_ib_mode_sel[29] mprj_io_inp_dis[29] mprj_io_oeb[29]
++ mprj_io_out[29] mprj_io_slow_sel[29] mprj_io_vtrip_sel[29] mprj_io_in[29] mprj_analog_io[23]
++ mprj_io[30] mprj_io_analog_en[30] mprj_io_analog_pol[30] mprj_io_analog_sel[30]
++ mprj_io_dm[90] mprj_io_dm[91] mprj_io_dm[92] mprj_io_holdover[30] mprj_io_ib_mode_sel[30]
++ mprj_io_inp_dis[30] mprj_io_oeb[30] mprj_io_out[30] mprj_io_slow_sel[30] mprj_io_vtrip_sel[30]
++ mprj_io_in[30] mprj_analog_io[24] mprj_io[31] mprj_io_analog_en[31] mprj_io_analog_pol[31]
++ mprj_io_analog_sel[31] mprj_io_dm[93] mprj_io_dm[94] mprj_io_dm[95] mprj_io_holdover[31]
++ mprj_io_ib_mode_sel[31] mprj_io_inp_dis[31] mprj_io_oeb[31] mprj_io_out[31] mprj_io_slow_sel[31]
++ mprj_io_vtrip_sel[31] mprj_io_in[31] mprj_analog_io[25] mprj_io[32] mprj_io_analog_en[32]
++ mprj_io_analog_pol[32] mprj_io_analog_sel[32] mprj_io_dm[96] mprj_io_dm[97] mprj_io_dm[98]
++ mprj_io_holdover[32] mprj_io_ib_mode_sel[32] mprj_io_inp_dis[32] mprj_io_oeb[32]
++ mprj_io_out[32] mprj_io_slow_sel[32] mprj_io_vtrip_sel[32] mprj_io_in[32] mprj_analog_io[26]
++ mprj_io[33] mprj_io_analog_en[33] mprj_io_analog_pol[33] mprj_io_analog_sel[33]
++ mprj_io_dm[100] mprj_io_dm[101] mprj_io_dm[99] mprj_io_holdover[33] mprj_io_ib_mode_sel[33]
++ mprj_io_inp_dis[33] mprj_io_oeb[33] mprj_io_out[33] mprj_io_slow_sel[33] mprj_io_vtrip_sel[33]
++ mprj_io_in[33] mprj_analog_io[27] mprj_io[34] mprj_io_analog_en[34] mprj_io_analog_pol[34]
++ mprj_io_analog_sel[34] mprj_io_dm[102] mprj_io_dm[103] mprj_io_dm[104] mprj_io_holdover[34]
++ mprj_io_ib_mode_sel[34] mprj_io_inp_dis[34] mprj_io_oeb[34] mprj_io_out[34] mprj_io_slow_sel[34]
++ mprj_io_vtrip_sel[34] mprj_io_in[34] mprj_analog_io[28] mprj_io[35] mprj_io_analog_en[35]
++ mprj_io_analog_pol[35] mprj_io_analog_sel[35] mprj_io_dm[105] mprj_io_dm[106] mprj_io_dm[107]
++ mprj_io_holdover[35] mprj_io_ib_mode_sel[35] mprj_io_inp_dis[35] mprj_io_oeb[35]
++ mprj_io_out[35] mprj_io_slow_sel[35] mprj_io_vtrip_sel[35] mprj_io_in[35] mprj_io[36]
++ mprj_io_analog_en[36] mprj_io_analog_pol[36] mprj_io_analog_sel[36] mprj_io_dm[108]
++ mprj_io_dm[109] mprj_io_dm[110] mprj_io_holdover[36] mprj_io_ib_mode_sel[36] mprj_io_inp_dis[36]
++ mprj_io_oeb[36] mprj_io_out[36] mprj_io_slow_sel[36] mprj_io_vtrip_sel[36] mprj_io_in[36]
++ mprj_io[37] mprj_io_analog_en[37] mprj_io_analog_pol[37] mprj_io_analog_sel[37]
++ mprj_io_dm[111] mprj_io_dm[112] mprj_io_dm[113] mprj_io_holdover[37] mprj_io_ib_mode_sel[37]
++ mprj_io_inp_dis[37] mprj_io_oeb[37] mprj_io_out[37] mprj_io_slow_sel[37] mprj_io_vtrip_sel[37]
++ mprj_io_in[37] mprj_analog_io[13] mprj_io[20] mprj_io_analog_en[20] mprj_io_analog_pol[20]
++ mprj_io_analog_sel[20] mprj_io_dm[60] mprj_io_dm[61] mprj_io_dm[62] mprj_io_holdover[20]
++ mprj_io_ib_mode_sel[20] mprj_io_inp_dis[20] mprj_io_oeb[20] mprj_io_out[20] mprj_io_slow_sel[20]
++ mprj_io_vtrip_sel[20] mprj_io_in[20] mprj_analog_io[14] mprj_io[21] mprj_io_analog_en[21]
++ mprj_io_analog_pol[21] mprj_io_analog_sel[21] mprj_io_dm[63] mprj_io_dm[64] mprj_io_dm[65]
++ mprj_io_holdover[21] mprj_io_ib_mode_sel[21] mprj_io_inp_dis[21] mprj_io_oeb[21]
++ mprj_io_out[21] mprj_io_slow_sel[21] mprj_io_vtrip_sel[21] mprj_io_in[21] mprj_analog_io[15]
++ mprj_io[22] mprj_io_analog_en[22] mprj_io_analog_pol[22] mprj_io_analog_sel[22]
++ mprj_io_dm[66] mprj_io_dm[67] mprj_io_dm[68] mprj_io_holdover[22] mprj_io_ib_mode_sel[22]
++ mprj_io_inp_dis[22] mprj_io_oeb[22] mprj_io_out[22] mprj_io_slow_sel[22] mprj_io_vtrip_sel[22]
++ mprj_io_in[22] mprj_analog_io[16] mprj_io[23] mprj_io_analog_en[23] mprj_io_analog_pol[23]
++ mprj_io_analog_sel[23] mprj_io_dm[69] mprj_io_dm[70] mprj_io_dm[71] mprj_io_holdover[23]
++ mprj_io_ib_mode_sel[23] mprj_io_inp_dis[23] mprj_io_oeb[23] mprj_io_out[23] mprj_io_slow_sel[23]
++ mprj_io_vtrip_sel[23] mprj_io_in[23] mprj_analog_io[17] mprj_io[24] mprj_io_analog_en[24]
++ mprj_io_analog_pol[24] mprj_io_analog_sel[24] mprj_io_dm[72] mprj_io_dm[73] mprj_io_dm[74]
++ mprj_io_holdover[24] mprj_io_ib_mode_sel[24] mprj_io_inp_dis[24] mprj_io_oeb[24]
++ mprj_io_out[24] mprj_io_slow_sel[24] mprj_io_vtrip_sel[24] mprj_io_in[24] mprj_analog_io[18]
++ mprj_io[25] mprj_io_analog_en[25] mprj_io_analog_pol[25] mprj_io_analog_sel[25]
++ mprj_io_dm[75] mprj_io_dm[76] mprj_io_dm[77] mprj_io_holdover[25] mprj_io_ib_mode_sel[25]
++ mprj_io_inp_dis[25] mprj_io_oeb[25] mprj_io_out[25] mprj_io_slow_sel[25] mprj_io_vtrip_sel[25]
++ mprj_io_in[25] mprj_analog_io[19] mprj_io[26] mprj_io_analog_en[26] mprj_io_analog_pol[26]
++ mprj_io_analog_sel[26] mprj_io_dm[78] mprj_io_dm[79] mprj_io_dm[80] mprj_io_holdover[26]
++ mprj_io_ib_mode_sel[26] mprj_io_inp_dis[26] mprj_io_oeb[26] mprj_io_out[26] mprj_io_slow_sel[26]
++ mprj_io_vtrip_sel[26] mprj_io_in[26] mprj_analog_io[20] mprj_io[27] mprj_io_analog_en[27]
++ mprj_io_analog_pol[27] mprj_io_analog_sel[27] mprj_io_dm[81] mprj_io_dm[82] mprj_io_dm[83]
++ mprj_io_holdover[27] mprj_io_ib_mode_sel[27] mprj_io_inp_dis[27] mprj_io_oeb[27]
++ mprj_io_out[27] mprj_io_slow_sel[27] mprj_io_vtrip_sel[27] mprj_io_in[27] mprj_analog_io[21]
++ mprj_io[28] mprj_io_analog_en[28] mprj_io_analog_pol[28] mprj_io_analog_sel[28]
++ mprj_io_dm[84] mprj_io_dm[85] mprj_io_dm[86] mprj_io_holdover[28] mprj_io_ib_mode_sel[28]
++ mprj_io_inp_dis[28] mprj_io_oeb[28] mprj_io_out[28] mprj_io_slow_sel[28] mprj_io_vtrip_sel[28]
++ mprj_io_in[28] porb_h resetb resetb_core_h vdda vssa vssd vccd1_pad vdda1_pad vdda1_pad2
++ vssa1_pad vssa1_pad2 vccd1 vdda1 vssa1 vssd1 vssd1_pad vccd2_pad vdda2_pad vssa2_pad
++ vccd vccd2 vdda2 vddio vssa2 vssd2 vssd2_pad vssio
+.ends
+
+* Black-box entry subcircuit for mgmt_core abstract view
+.subckt mgmt_core clock core_clk core_rstn flash_clk flash_clk_ieb flash_clk_oeb flash_csb
++ flash_csb_ieb flash_csb_oeb flash_io0_di flash_io0_do flash_io0_ieb flash_io0_oeb
++ flash_io1_di flash_io1_do flash_io1_ieb flash_io1_oeb flash_io2_oeb flash_io3_oeb
++ gpio_in_pad gpio_inenb_pad gpio_mode0_pad gpio_mode1_pad gpio_out_pad gpio_outenb_pad
++ jtag_out jtag_outenb la_iena[0] la_iena[100] la_iena[101] la_iena[102] la_iena[103]
++ la_iena[104] la_iena[105] la_iena[106] la_iena[107] la_iena[108] la_iena[109] la_iena[10]
++ la_iena[110] la_iena[111] la_iena[112] la_iena[113] la_iena[114] la_iena[115] la_iena[116]
++ la_iena[117] la_iena[118] la_iena[119] la_iena[11] la_iena[120] la_iena[121] la_iena[122]
++ la_iena[123] la_iena[124] la_iena[125] la_iena[126] la_iena[127] la_iena[12] la_iena[13]
++ la_iena[14] la_iena[15] la_iena[16] la_iena[17] la_iena[18] la_iena[19] la_iena[1]
++ la_iena[20] la_iena[21] la_iena[22] la_iena[23] la_iena[24] la_iena[25] la_iena[26]
++ la_iena[27] la_iena[28] la_iena[29] la_iena[2] la_iena[30] la_iena[31] la_iena[32]
++ la_iena[33] la_iena[34] la_iena[35] la_iena[36] la_iena[37] la_iena[38] la_iena[39]
++ la_iena[3] la_iena[40] la_iena[41] la_iena[42] la_iena[43] la_iena[44] la_iena[45]
++ la_iena[46] la_iena[47] la_iena[48] la_iena[49] la_iena[4] la_iena[50] la_iena[51]
++ la_iena[52] la_iena[53] la_iena[54] la_iena[55] la_iena[56] la_iena[57] la_iena[58]
++ la_iena[59] la_iena[5] la_iena[60] la_iena[61] la_iena[62] la_iena[63] la_iena[64]
++ la_iena[65] la_iena[66] la_iena[67] la_iena[68] la_iena[69] la_iena[6] la_iena[70]
++ la_iena[71] la_iena[72] la_iena[73] la_iena[74] la_iena[75] la_iena[76] la_iena[77]
++ la_iena[78] la_iena[79] la_iena[7] la_iena[80] la_iena[81] la_iena[82] la_iena[83]
++ la_iena[84] la_iena[85] la_iena[86] la_iena[87] la_iena[88] la_iena[89] la_iena[8]
++ la_iena[90] la_iena[91] la_iena[92] la_iena[93] la_iena[94] la_iena[95] la_iena[96]
++ la_iena[97] la_iena[98] la_iena[99] la_iena[9] la_input[0] la_input[100] la_input[101]
++ la_input[102] la_input[103] la_input[104] la_input[105] la_input[106] la_input[107]
++ la_input[108] la_input[109] la_input[10] la_input[110] la_input[111] la_input[112]
++ la_input[113] la_input[114] la_input[115] la_input[116] la_input[117] la_input[118]
++ la_input[119] la_input[11] la_input[120] la_input[121] la_input[122] la_input[123]
++ la_input[124] la_input[125] la_input[126] la_input[127] la_input[12] la_input[13]
++ la_input[14] la_input[15] la_input[16] la_input[17] la_input[18] la_input[19] la_input[1]
++ la_input[20] la_input[21] la_input[22] la_input[23] la_input[24] la_input[25] la_input[26]
++ la_input[27] la_input[28] la_input[29] la_input[2] la_input[30] la_input[31] la_input[32]
++ la_input[33] la_input[34] la_input[35] la_input[36] la_input[37] la_input[38] la_input[39]
++ la_input[3] la_input[40] la_input[41] la_input[42] la_input[43] la_input[44] la_input[45]
++ la_input[46] la_input[47] la_input[48] la_input[49] la_input[4] la_input[50] la_input[51]
++ la_input[52] la_input[53] la_input[54] la_input[55] la_input[56] la_input[57] la_input[58]
++ la_input[59] la_input[5] la_input[60] la_input[61] la_input[62] la_input[63] la_input[64]
++ la_input[65] la_input[66] la_input[67] la_input[68] la_input[69] la_input[6] la_input[70]
++ la_input[71] la_input[72] la_input[73] la_input[74] la_input[75] la_input[76] la_input[77]
++ la_input[78] la_input[79] la_input[7] la_input[80] la_input[81] la_input[82] la_input[83]
++ la_input[84] la_input[85] la_input[86] la_input[87] la_input[88] la_input[89] la_input[8]
++ la_input[90] la_input[91] la_input[92] la_input[93] la_input[94] la_input[95] la_input[96]
++ la_input[97] la_input[98] la_input[99] la_input[9] la_oenb[0] la_oenb[100] la_oenb[101]
++ la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108]
++ la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114]
++ la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120]
++ la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127]
++ la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18]
++ la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24]
++ la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30]
++ la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37]
++ la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43]
++ la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4]
++ la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56]
++ la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62]
++ la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69]
++ la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75]
++ la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81]
++ la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88]
++ la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94]
++ la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] la_output[0]
++ la_output[100] la_output[101] la_output[102] la_output[103] la_output[104] la_output[105]
++ la_output[106] la_output[107] la_output[108] la_output[109] la_output[10] la_output[110]
++ la_output[111] la_output[112] la_output[113] la_output[114] la_output[115] la_output[116]
++ la_output[117] la_output[118] la_output[119] la_output[11] la_output[120] la_output[121]
++ la_output[122] la_output[123] la_output[124] la_output[125] la_output[126] la_output[127]
++ la_output[12] la_output[13] la_output[14] la_output[15] la_output[16] la_output[17]
++ la_output[18] la_output[19] la_output[1] la_output[20] la_output[21] la_output[22]
++ la_output[23] la_output[24] la_output[25] la_output[26] la_output[27] la_output[28]
++ la_output[29] la_output[2] la_output[30] la_output[31] la_output[32] la_output[33]
++ la_output[34] la_output[35] la_output[36] la_output[37] la_output[38] la_output[39]
++ la_output[3] la_output[40] la_output[41] la_output[42] la_output[43] la_output[44]
++ la_output[45] la_output[46] la_output[47] la_output[48] la_output[49] la_output[4]
++ la_output[50] la_output[51] la_output[52] la_output[53] la_output[54] la_output[55]
++ la_output[56] la_output[57] la_output[58] la_output[59] la_output[5] la_output[60]
++ la_output[61] la_output[62] la_output[63] la_output[64] la_output[65] la_output[66]
++ la_output[67] la_output[68] la_output[69] la_output[6] la_output[70] la_output[71]
++ la_output[72] la_output[73] la_output[74] la_output[75] la_output[76] la_output[77]
++ la_output[78] la_output[79] la_output[7] la_output[80] la_output[81] la_output[82]
++ la_output[83] la_output[84] la_output[85] la_output[86] la_output[87] la_output[88]
++ la_output[89] la_output[8] la_output[90] la_output[91] la_output[92] la_output[93]
++ la_output[94] la_output[95] la_output[96] la_output[97] la_output[98] la_output[99]
++ la_output[9] mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13] mask_rev[14]
++ mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1] mask_rev[20]
++ mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26] mask_rev[27]
++ mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3] mask_rev[4]
++ mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] mgmt_addr[0] mgmt_addr[1]
++ mgmt_addr[2] mgmt_addr[3] mgmt_addr[4] mgmt_addr[5] mgmt_addr[6] mgmt_addr[7] mgmt_addr_ro[0]
++ mgmt_addr_ro[1] mgmt_addr_ro[2] mgmt_addr_ro[3] mgmt_addr_ro[4] mgmt_addr_ro[5]
++ mgmt_addr_ro[6] mgmt_addr_ro[7] mgmt_ena[0] mgmt_ena[1] mgmt_ena_ro mgmt_in_data[0]
++ mgmt_in_data[10] mgmt_in_data[11] mgmt_in_data[12] mgmt_in_data[13] mgmt_in_data[14]
++ mgmt_in_data[15] mgmt_in_data[16] mgmt_in_data[17] mgmt_in_data[18] mgmt_in_data[19]
++ mgmt_in_data[1] mgmt_in_data[20] mgmt_in_data[21] mgmt_in_data[22] mgmt_in_data[23]
++ mgmt_in_data[24] mgmt_in_data[25] mgmt_in_data[26] mgmt_in_data[27] mgmt_in_data[28]
++ mgmt_in_data[29] mgmt_in_data[2] mgmt_in_data[30] mgmt_in_data[31] mgmt_in_data[32]
++ mgmt_in_data[33] mgmt_in_data[34] mgmt_in_data[35] mgmt_in_data[36] mgmt_in_data[37]
++ mgmt_in_data[3] mgmt_in_data[4] mgmt_in_data[5] mgmt_in_data[6] mgmt_in_data[7]
++ mgmt_in_data[8] mgmt_in_data[9] mgmt_out_data[0] mgmt_out_data[10] mgmt_out_data[11]
++ mgmt_out_data[12] mgmt_out_data[13] mgmt_out_data[14] mgmt_out_data[15] mgmt_out_data[16]
++ mgmt_out_data[17] mgmt_out_data[18] mgmt_out_data[19] mgmt_out_data[1] mgmt_out_data[20]
++ mgmt_out_data[21] mgmt_out_data[22] mgmt_out_data[23] mgmt_out_data[24] mgmt_out_data[25]
++ mgmt_out_data[26] mgmt_out_data[27] mgmt_out_data[28] mgmt_out_data[29] mgmt_out_data[2]
++ mgmt_out_data[30] mgmt_out_data[31] mgmt_out_data[32] mgmt_out_data[33] mgmt_out_data[34]
++ mgmt_out_data[35] mgmt_out_data[36] mgmt_out_data[37] mgmt_out_data[3] mgmt_out_data[4]
++ mgmt_out_data[5] mgmt_out_data[6] mgmt_out_data[7] mgmt_out_data[8] mgmt_out_data[9]
++ mgmt_rdata[0] mgmt_rdata[10] mgmt_rdata[11] mgmt_rdata[12] mgmt_rdata[13] mgmt_rdata[14]
++ mgmt_rdata[15] mgmt_rdata[16] mgmt_rdata[17] mgmt_rdata[18] mgmt_rdata[19] mgmt_rdata[1]
++ mgmt_rdata[20] mgmt_rdata[21] mgmt_rdata[22] mgmt_rdata[23] mgmt_rdata[24] mgmt_rdata[25]
++ mgmt_rdata[26] mgmt_rdata[27] mgmt_rdata[28] mgmt_rdata[29] mgmt_rdata[2] mgmt_rdata[30]
++ mgmt_rdata[31] mgmt_rdata[32] mgmt_rdata[33] mgmt_rdata[34] mgmt_rdata[35] mgmt_rdata[36]
++ mgmt_rdata[37] mgmt_rdata[38] mgmt_rdata[39] mgmt_rdata[3] mgmt_rdata[40] mgmt_rdata[41]
++ mgmt_rdata[42] mgmt_rdata[43] mgmt_rdata[44] mgmt_rdata[45] mgmt_rdata[46] mgmt_rdata[47]
++ mgmt_rdata[48] mgmt_rdata[49] mgmt_rdata[4] mgmt_rdata[50] mgmt_rdata[51] mgmt_rdata[52]
++ mgmt_rdata[53] mgmt_rdata[54] mgmt_rdata[55] mgmt_rdata[56] mgmt_rdata[57] mgmt_rdata[58]
++ mgmt_rdata[59] mgmt_rdata[5] mgmt_rdata[60] mgmt_rdata[61] mgmt_rdata[62] mgmt_rdata[63]
++ mgmt_rdata[6] mgmt_rdata[7] mgmt_rdata[8] mgmt_rdata[9] mgmt_rdata_ro[0] mgmt_rdata_ro[10]
++ mgmt_rdata_ro[11] mgmt_rdata_ro[12] mgmt_rdata_ro[13] mgmt_rdata_ro[14] mgmt_rdata_ro[15]
++ mgmt_rdata_ro[16] mgmt_rdata_ro[17] mgmt_rdata_ro[18] mgmt_rdata_ro[19] mgmt_rdata_ro[1]
++ mgmt_rdata_ro[20] mgmt_rdata_ro[21] mgmt_rdata_ro[22] mgmt_rdata_ro[23] mgmt_rdata_ro[24]
++ mgmt_rdata_ro[25] mgmt_rdata_ro[26] mgmt_rdata_ro[27] mgmt_rdata_ro[28] mgmt_rdata_ro[29]
++ mgmt_rdata_ro[2] mgmt_rdata_ro[30] mgmt_rdata_ro[31] mgmt_rdata_ro[3] mgmt_rdata_ro[4]
++ mgmt_rdata_ro[5] mgmt_rdata_ro[6] mgmt_rdata_ro[7] mgmt_rdata_ro[8] mgmt_rdata_ro[9]
++ mgmt_wdata[0] mgmt_wdata[10] mgmt_wdata[11] mgmt_wdata[12] mgmt_wdata[13] mgmt_wdata[14]
++ mgmt_wdata[15] mgmt_wdata[16] mgmt_wdata[17] mgmt_wdata[18] mgmt_wdata[19] mgmt_wdata[1]
++ mgmt_wdata[20] mgmt_wdata[21] mgmt_wdata[22] mgmt_wdata[23] mgmt_wdata[24] mgmt_wdata[25]
++ mgmt_wdata[26] mgmt_wdata[27] mgmt_wdata[28] mgmt_wdata[29] mgmt_wdata[2] mgmt_wdata[30]
++ mgmt_wdata[31] mgmt_wdata[3] mgmt_wdata[4] mgmt_wdata[5] mgmt_wdata[6] mgmt_wdata[7]
++ mgmt_wdata[8] mgmt_wdata[9] mgmt_wen[0] mgmt_wen[1] mgmt_wen_mask[0] mgmt_wen_mask[1]
++ mgmt_wen_mask[2] mgmt_wen_mask[3] mgmt_wen_mask[4] mgmt_wen_mask[5] mgmt_wen_mask[6]
++ mgmt_wen_mask[7] mprj2_vcc_pwrgood mprj2_vdd_pwrgood mprj_ack_i mprj_adr_o[0] mprj_adr_o[10]
++ mprj_adr_o[11] mprj_adr_o[12] mprj_adr_o[13] mprj_adr_o[14] mprj_adr_o[15] mprj_adr_o[16]
++ mprj_adr_o[17] mprj_adr_o[18] mprj_adr_o[19] mprj_adr_o[1] mprj_adr_o[20] mprj_adr_o[21]
++ mprj_adr_o[22] mprj_adr_o[23] mprj_adr_o[24] mprj_adr_o[25] mprj_adr_o[26] mprj_adr_o[27]
++ mprj_adr_o[28] mprj_adr_o[29] mprj_adr_o[2] mprj_adr_o[30] mprj_adr_o[31] mprj_adr_o[3]
++ mprj_adr_o[4] mprj_adr_o[5] mprj_adr_o[6] mprj_adr_o[7] mprj_adr_o[8] mprj_adr_o[9]
++ mprj_cyc_o mprj_dat_i[0] mprj_dat_i[10] mprj_dat_i[11] mprj_dat_i[12] mprj_dat_i[13]
++ mprj_dat_i[14] mprj_dat_i[15] mprj_dat_i[16] mprj_dat_i[17] mprj_dat_i[18] mprj_dat_i[19]
++ mprj_dat_i[1] mprj_dat_i[20] mprj_dat_i[21] mprj_dat_i[22] mprj_dat_i[23] mprj_dat_i[24]
++ mprj_dat_i[25] mprj_dat_i[26] mprj_dat_i[27] mprj_dat_i[28] mprj_dat_i[29] mprj_dat_i[2]
++ mprj_dat_i[30] mprj_dat_i[31] mprj_dat_i[3] mprj_dat_i[4] mprj_dat_i[5] mprj_dat_i[6]
++ mprj_dat_i[7] mprj_dat_i[8] mprj_dat_i[9] mprj_dat_o[0] mprj_dat_o[10] mprj_dat_o[11]
++ mprj_dat_o[12] mprj_dat_o[13] mprj_dat_o[14] mprj_dat_o[15] mprj_dat_o[16] mprj_dat_o[17]
++ mprj_dat_o[18] mprj_dat_o[19] mprj_dat_o[1] mprj_dat_o[20] mprj_dat_o[21] mprj_dat_o[22]
++ mprj_dat_o[23] mprj_dat_o[24] mprj_dat_o[25] mprj_dat_o[26] mprj_dat_o[27] mprj_dat_o[28]
++ mprj_dat_o[29] mprj_dat_o[2] mprj_dat_o[30] mprj_dat_o[31] mprj_dat_o[3] mprj_dat_o[4]
++ mprj_dat_o[5] mprj_dat_o[6] mprj_dat_o[7] mprj_dat_o[8] mprj_dat_o[9] mprj_io_loader_clock
++ mprj_io_loader_data_1 mprj_io_loader_data_2 mprj_io_loader_resetn mprj_sel_o[0]
++ mprj_sel_o[1] mprj_sel_o[2] mprj_sel_o[3] mprj_stb_o mprj_vcc_pwrgood mprj_vdd_pwrgood
++ mprj_we_o porb pwr_ctrl_out[0] pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3] resetb
++ sdo_out sdo_outenb user_clk user_irq[0] user_irq[1] user_irq[2] user_irq_ena[0]
++ user_irq_ena[1] user_irq_ena[2] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for user_id_textblock abstract view
+.subckt user_id_textblock VSUBS
+.ends
+
+* Black-box entry subcircuit for simple_por abstract view
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+.ends
+
+* Black-box entry subcircuit for user_id_programming abstract view
+.subckt user_id_programming mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13]
++ mask_rev[14] mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1]
++ mask_rev[20] mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26]
++ mask_rev[27] mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3]
++ mask_rev[4] mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for open_source abstract view
+.subckt open_source VSUBS
+.ends
+
+* Black-box entry subcircuit for mgmt_protect abstract view
+.subckt mgmt_protect caravel_clk caravel_clk2 caravel_rstn la_data_in_core[0] la_data_in_core[100]
++ la_data_in_core[101] la_data_in_core[102] la_data_in_core[103] la_data_in_core[104]
++ la_data_in_core[105] la_data_in_core[106] la_data_in_core[107] la_data_in_core[108]
++ la_data_in_core[109] la_data_in_core[10] la_data_in_core[110] la_data_in_core[111]
++ la_data_in_core[112] la_data_in_core[113] la_data_in_core[114] la_data_in_core[115]
++ la_data_in_core[116] la_data_in_core[117] la_data_in_core[118] la_data_in_core[119]
++ la_data_in_core[11] la_data_in_core[120] la_data_in_core[121] la_data_in_core[122]
++ la_data_in_core[123] la_data_in_core[124] la_data_in_core[125] la_data_in_core[126]
++ la_data_in_core[127] la_data_in_core[12] la_data_in_core[13] la_data_in_core[14]
++ la_data_in_core[15] la_data_in_core[16] la_data_in_core[17] la_data_in_core[18]
++ la_data_in_core[19] la_data_in_core[1] la_data_in_core[20] la_data_in_core[21] la_data_in_core[22]
++ la_data_in_core[23] la_data_in_core[24] la_data_in_core[25] la_data_in_core[26]
++ la_data_in_core[27] la_data_in_core[28] la_data_in_core[29] la_data_in_core[2] la_data_in_core[30]
++ la_data_in_core[31] la_data_in_core[32] la_data_in_core[33] la_data_in_core[34]
++ la_data_in_core[35] la_data_in_core[36] la_data_in_core[37] la_data_in_core[38]
++ la_data_in_core[39] la_data_in_core[3] la_data_in_core[40] la_data_in_core[41] la_data_in_core[42]
++ la_data_in_core[43] la_data_in_core[44] la_data_in_core[45] la_data_in_core[46]
++ la_data_in_core[47] la_data_in_core[48] la_data_in_core[49] la_data_in_core[4] la_data_in_core[50]
++ la_data_in_core[51] la_data_in_core[52] la_data_in_core[53] la_data_in_core[54]
++ la_data_in_core[55] la_data_in_core[56] la_data_in_core[57] la_data_in_core[58]
++ la_data_in_core[59] la_data_in_core[5] la_data_in_core[60] la_data_in_core[61] la_data_in_core[62]
++ la_data_in_core[63] la_data_in_core[64] la_data_in_core[65] la_data_in_core[66]
++ la_data_in_core[67] la_data_in_core[68] la_data_in_core[69] la_data_in_core[6] la_data_in_core[70]
++ la_data_in_core[71] la_data_in_core[72] la_data_in_core[73] la_data_in_core[74]
++ la_data_in_core[75] la_data_in_core[76] la_data_in_core[77] la_data_in_core[78]
++ la_data_in_core[79] la_data_in_core[7] la_data_in_core[80] la_data_in_core[81] la_data_in_core[82]
++ la_data_in_core[83] la_data_in_core[84] la_data_in_core[85] la_data_in_core[86]
++ la_data_in_core[87] la_data_in_core[88] la_data_in_core[89] la_data_in_core[8] la_data_in_core[90]
++ la_data_in_core[91] la_data_in_core[92] la_data_in_core[93] la_data_in_core[94]
++ la_data_in_core[95] la_data_in_core[96] la_data_in_core[97] la_data_in_core[98]
++ la_data_in_core[99] la_data_in_core[9] la_data_in_mprj[0] la_data_in_mprj[100] la_data_in_mprj[101]
++ la_data_in_mprj[102] la_data_in_mprj[103] la_data_in_mprj[104] la_data_in_mprj[105]
++ la_data_in_mprj[106] la_data_in_mprj[107] la_data_in_mprj[108] la_data_in_mprj[109]
++ la_data_in_mprj[10] la_data_in_mprj[110] la_data_in_mprj[111] la_data_in_mprj[112]
++ la_data_in_mprj[113] la_data_in_mprj[114] la_data_in_mprj[115] la_data_in_mprj[116]
++ la_data_in_mprj[117] la_data_in_mprj[118] la_data_in_mprj[119] la_data_in_mprj[11]
++ la_data_in_mprj[120] la_data_in_mprj[121] la_data_in_mprj[122] la_data_in_mprj[123]
++ la_data_in_mprj[124] la_data_in_mprj[125] la_data_in_mprj[126] la_data_in_mprj[127]
++ la_data_in_mprj[12] la_data_in_mprj[13] la_data_in_mprj[14] la_data_in_mprj[15]
++ la_data_in_mprj[16] la_data_in_mprj[17] la_data_in_mprj[18] la_data_in_mprj[19]
++ la_data_in_mprj[1] la_data_in_mprj[20] la_data_in_mprj[21] la_data_in_mprj[22] la_data_in_mprj[23]
++ la_data_in_mprj[24] la_data_in_mprj[25] la_data_in_mprj[26] la_data_in_mprj[27]
++ la_data_in_mprj[28] la_data_in_mprj[29] la_data_in_mprj[2] la_data_in_mprj[30] la_data_in_mprj[31]
++ la_data_in_mprj[32] la_data_in_mprj[33] la_data_in_mprj[34] la_data_in_mprj[35]
++ la_data_in_mprj[36] la_data_in_mprj[37] la_data_in_mprj[38] la_data_in_mprj[39]
++ la_data_in_mprj[3] la_data_in_mprj[40] la_data_in_mprj[41] la_data_in_mprj[42] la_data_in_mprj[43]
++ la_data_in_mprj[44] la_data_in_mprj[45] la_data_in_mprj[46] la_data_in_mprj[47]
++ la_data_in_mprj[48] la_data_in_mprj[49] la_data_in_mprj[4] la_data_in_mprj[50] la_data_in_mprj[51]
++ la_data_in_mprj[52] la_data_in_mprj[53] la_data_in_mprj[54] la_data_in_mprj[55]
++ la_data_in_mprj[56] la_data_in_mprj[57] la_data_in_mprj[58] la_data_in_mprj[59]
++ la_data_in_mprj[5] la_data_in_mprj[60] la_data_in_mprj[61] la_data_in_mprj[62] la_data_in_mprj[63]
++ la_data_in_mprj[64] la_data_in_mprj[65] la_data_in_mprj[66] la_data_in_mprj[67]
++ la_data_in_mprj[68] la_data_in_mprj[69] la_data_in_mprj[6] la_data_in_mprj[70] la_data_in_mprj[71]
++ la_data_in_mprj[72] la_data_in_mprj[73] la_data_in_mprj[74] la_data_in_mprj[75]
++ la_data_in_mprj[76] la_data_in_mprj[77] la_data_in_mprj[78] la_data_in_mprj[79]
++ la_data_in_mprj[7] la_data_in_mprj[80] la_data_in_mprj[81] la_data_in_mprj[82] la_data_in_mprj[83]
++ la_data_in_mprj[84] la_data_in_mprj[85] la_data_in_mprj[86] la_data_in_mprj[87]
++ la_data_in_mprj[88] la_data_in_mprj[89] la_data_in_mprj[8] la_data_in_mprj[90] la_data_in_mprj[91]
++ la_data_in_mprj[92] la_data_in_mprj[93] la_data_in_mprj[94] la_data_in_mprj[95]
++ la_data_in_mprj[96] la_data_in_mprj[97] la_data_in_mprj[98] la_data_in_mprj[99]
++ la_data_in_mprj[9] la_data_out_core[0] la_data_out_core[100] la_data_out_core[101]
++ la_data_out_core[102] la_data_out_core[103] la_data_out_core[104] la_data_out_core[105]
++ la_data_out_core[106] la_data_out_core[107] la_data_out_core[108] la_data_out_core[109]
++ la_data_out_core[10] la_data_out_core[110] la_data_out_core[111] la_data_out_core[112]
++ la_data_out_core[113] la_data_out_core[114] la_data_out_core[115] la_data_out_core[116]
++ la_data_out_core[117] la_data_out_core[118] la_data_out_core[119] la_data_out_core[11]
++ la_data_out_core[120] la_data_out_core[121] la_data_out_core[122] la_data_out_core[123]
++ la_data_out_core[124] la_data_out_core[125] la_data_out_core[126] la_data_out_core[127]
++ la_data_out_core[12] la_data_out_core[13] la_data_out_core[14] la_data_out_core[15]
++ la_data_out_core[16] la_data_out_core[17] la_data_out_core[18] la_data_out_core[19]
++ la_data_out_core[1] la_data_out_core[20] la_data_out_core[21] la_data_out_core[22]
++ la_data_out_core[23] la_data_out_core[24] la_data_out_core[25] la_data_out_core[26]
++ la_data_out_core[27] la_data_out_core[28] la_data_out_core[29] la_data_out_core[2]
++ la_data_out_core[30] la_data_out_core[31] la_data_out_core[32] la_data_out_core[33]
++ la_data_out_core[34] la_data_out_core[35] la_data_out_core[36] la_data_out_core[37]
++ la_data_out_core[38] la_data_out_core[39] la_data_out_core[3] la_data_out_core[40]
++ la_data_out_core[41] la_data_out_core[42] la_data_out_core[43] la_data_out_core[44]
++ la_data_out_core[45] la_data_out_core[46] la_data_out_core[47] la_data_out_core[48]
++ la_data_out_core[49] la_data_out_core[4] la_data_out_core[50] la_data_out_core[51]
++ la_data_out_core[52] la_data_out_core[53] la_data_out_core[54] la_data_out_core[55]
++ la_data_out_core[56] la_data_out_core[57] la_data_out_core[58] la_data_out_core[59]
++ la_data_out_core[5] la_data_out_core[60] la_data_out_core[61] la_data_out_core[62]
++ la_data_out_core[63] la_data_out_core[64] la_data_out_core[65] la_data_out_core[66]
++ la_data_out_core[67] la_data_out_core[68] la_data_out_core[69] la_data_out_core[6]
++ la_data_out_core[70] la_data_out_core[71] la_data_out_core[72] la_data_out_core[73]
++ la_data_out_core[74] la_data_out_core[75] la_data_out_core[76] la_data_out_core[77]
++ la_data_out_core[78] la_data_out_core[79] la_data_out_core[7] la_data_out_core[80]
++ la_data_out_core[81] la_data_out_core[82] la_data_out_core[83] la_data_out_core[84]
++ la_data_out_core[85] la_data_out_core[86] la_data_out_core[87] la_data_out_core[88]
++ la_data_out_core[89] la_data_out_core[8] la_data_out_core[90] la_data_out_core[91]
++ la_data_out_core[92] la_data_out_core[93] la_data_out_core[94] la_data_out_core[95]
++ la_data_out_core[96] la_data_out_core[97] la_data_out_core[98] la_data_out_core[99]
++ la_data_out_core[9] la_data_out_mprj[0] la_data_out_mprj[100] la_data_out_mprj[101]
++ la_data_out_mprj[102] la_data_out_mprj[103] la_data_out_mprj[104] la_data_out_mprj[105]
++ la_data_out_mprj[106] la_data_out_mprj[107] la_data_out_mprj[108] la_data_out_mprj[109]
++ la_data_out_mprj[10] la_data_out_mprj[110] la_data_out_mprj[111] la_data_out_mprj[112]
++ la_data_out_mprj[113] la_data_out_mprj[114] la_data_out_mprj[115] la_data_out_mprj[116]
++ la_data_out_mprj[117] la_data_out_mprj[118] la_data_out_mprj[119] la_data_out_mprj[11]
++ la_data_out_mprj[120] la_data_out_mprj[121] la_data_out_mprj[122] la_data_out_mprj[123]
++ la_data_out_mprj[124] la_data_out_mprj[125] la_data_out_mprj[126] la_data_out_mprj[127]
++ la_data_out_mprj[12] la_data_out_mprj[13] la_data_out_mprj[14] la_data_out_mprj[15]
++ la_data_out_mprj[16] la_data_out_mprj[17] la_data_out_mprj[18] la_data_out_mprj[19]
++ la_data_out_mprj[1] la_data_out_mprj[20] la_data_out_mprj[21] la_data_out_mprj[22]
++ la_data_out_mprj[23] la_data_out_mprj[24] la_data_out_mprj[25] la_data_out_mprj[26]
++ la_data_out_mprj[27] la_data_out_mprj[28] la_data_out_mprj[29] la_data_out_mprj[2]
++ la_data_out_mprj[30] la_data_out_mprj[31] la_data_out_mprj[32] la_data_out_mprj[33]
++ la_data_out_mprj[34] la_data_out_mprj[35] la_data_out_mprj[36] la_data_out_mprj[37]
++ la_data_out_mprj[38] la_data_out_mprj[39] la_data_out_mprj[3] la_data_out_mprj[40]
++ la_data_out_mprj[41] la_data_out_mprj[42] la_data_out_mprj[43] la_data_out_mprj[44]
++ la_data_out_mprj[45] la_data_out_mprj[46] la_data_out_mprj[47] la_data_out_mprj[48]
++ la_data_out_mprj[49] la_data_out_mprj[4] la_data_out_mprj[50] la_data_out_mprj[51]
++ la_data_out_mprj[52] la_data_out_mprj[53] la_data_out_mprj[54] la_data_out_mprj[55]
++ la_data_out_mprj[56] la_data_out_mprj[57] la_data_out_mprj[58] la_data_out_mprj[59]
++ la_data_out_mprj[5] la_data_out_mprj[60] la_data_out_mprj[61] la_data_out_mprj[62]
++ la_data_out_mprj[63] la_data_out_mprj[64] la_data_out_mprj[65] la_data_out_mprj[66]
++ la_data_out_mprj[67] la_data_out_mprj[68] la_data_out_mprj[69] la_data_out_mprj[6]
++ la_data_out_mprj[70] la_data_out_mprj[71] la_data_out_mprj[72] la_data_out_mprj[73]
++ la_data_out_mprj[74] la_data_out_mprj[75] la_data_out_mprj[76] la_data_out_mprj[77]
++ la_data_out_mprj[78] la_data_out_mprj[79] la_data_out_mprj[7] la_data_out_mprj[80]
++ la_data_out_mprj[81] la_data_out_mprj[82] la_data_out_mprj[83] la_data_out_mprj[84]
++ la_data_out_mprj[85] la_data_out_mprj[86] la_data_out_mprj[87] la_data_out_mprj[88]
++ la_data_out_mprj[89] la_data_out_mprj[8] la_data_out_mprj[90] la_data_out_mprj[91]
++ la_data_out_mprj[92] la_data_out_mprj[93] la_data_out_mprj[94] la_data_out_mprj[95]
++ la_data_out_mprj[96] la_data_out_mprj[97] la_data_out_mprj[98] la_data_out_mprj[99]
++ la_data_out_mprj[9] la_iena_mprj[0] la_iena_mprj[100] la_iena_mprj[101] la_iena_mprj[102]
++ la_iena_mprj[103] la_iena_mprj[104] la_iena_mprj[105] la_iena_mprj[106] la_iena_mprj[107]
++ la_iena_mprj[108] la_iena_mprj[109] la_iena_mprj[10] la_iena_mprj[110] la_iena_mprj[111]
++ la_iena_mprj[112] la_iena_mprj[113] la_iena_mprj[114] la_iena_mprj[115] la_iena_mprj[116]
++ la_iena_mprj[117] la_iena_mprj[118] la_iena_mprj[119] la_iena_mprj[11] la_iena_mprj[120]
++ la_iena_mprj[121] la_iena_mprj[122] la_iena_mprj[123] la_iena_mprj[124] la_iena_mprj[125]
++ la_iena_mprj[126] la_iena_mprj[127] la_iena_mprj[12] la_iena_mprj[13] la_iena_mprj[14]
++ la_iena_mprj[15] la_iena_mprj[16] la_iena_mprj[17] la_iena_mprj[18] la_iena_mprj[19]
++ la_iena_mprj[1] la_iena_mprj[20] la_iena_mprj[21] la_iena_mprj[22] la_iena_mprj[23]
++ la_iena_mprj[24] la_iena_mprj[25] la_iena_mprj[26] la_iena_mprj[27] la_iena_mprj[28]
++ la_iena_mprj[29] la_iena_mprj[2] la_iena_mprj[30] la_iena_mprj[31] la_iena_mprj[32]
++ la_iena_mprj[33] la_iena_mprj[34] la_iena_mprj[35] la_iena_mprj[36] la_iena_mprj[37]
++ la_iena_mprj[38] la_iena_mprj[39] la_iena_mprj[3] la_iena_mprj[40] la_iena_mprj[41]
++ la_iena_mprj[42] la_iena_mprj[43] la_iena_mprj[44] la_iena_mprj[45] la_iena_mprj[46]
++ la_iena_mprj[47] la_iena_mprj[48] la_iena_mprj[49] la_iena_mprj[4] la_iena_mprj[50]
++ la_iena_mprj[51] la_iena_mprj[52] la_iena_mprj[53] la_iena_mprj[54] la_iena_mprj[55]
++ la_iena_mprj[56] la_iena_mprj[57] la_iena_mprj[58] la_iena_mprj[59] la_iena_mprj[5]
++ la_iena_mprj[60] la_iena_mprj[61] la_iena_mprj[62] la_iena_mprj[63] la_iena_mprj[64]
++ la_iena_mprj[65] la_iena_mprj[66] la_iena_mprj[67] la_iena_mprj[68] la_iena_mprj[69]
++ la_iena_mprj[6] la_iena_mprj[70] la_iena_mprj[71] la_iena_mprj[72] la_iena_mprj[73]
++ la_iena_mprj[74] la_iena_mprj[75] la_iena_mprj[76] la_iena_mprj[77] la_iena_mprj[78]
++ la_iena_mprj[79] la_iena_mprj[7] la_iena_mprj[80] la_iena_mprj[81] la_iena_mprj[82]
++ la_iena_mprj[83] la_iena_mprj[84] la_iena_mprj[85] la_iena_mprj[86] la_iena_mprj[87]
++ la_iena_mprj[88] la_iena_mprj[89] la_iena_mprj[8] la_iena_mprj[90] la_iena_mprj[91]
++ la_iena_mprj[92] la_iena_mprj[93] la_iena_mprj[94] la_iena_mprj[95] la_iena_mprj[96]
++ la_iena_mprj[97] la_iena_mprj[98] la_iena_mprj[99] la_iena_mprj[9] la_oenb_core[0]
++ la_oenb_core[100] la_oenb_core[101] la_oenb_core[102] la_oenb_core[103] la_oenb_core[104]
++ la_oenb_core[105] la_oenb_core[106] la_oenb_core[107] la_oenb_core[108] la_oenb_core[109]
++ la_oenb_core[10] la_oenb_core[110] la_oenb_core[111] la_oenb_core[112] la_oenb_core[113]
++ la_oenb_core[114] la_oenb_core[115] la_oenb_core[116] la_oenb_core[117] la_oenb_core[118]
++ la_oenb_core[119] la_oenb_core[11] la_oenb_core[120] la_oenb_core[121] la_oenb_core[122]
++ la_oenb_core[123] la_oenb_core[124] la_oenb_core[125] la_oenb_core[126] la_oenb_core[127]
++ la_oenb_core[12] la_oenb_core[13] la_oenb_core[14] la_oenb_core[15] la_oenb_core[16]
++ la_oenb_core[17] la_oenb_core[18] la_oenb_core[19] la_oenb_core[1] la_oenb_core[20]
++ la_oenb_core[21] la_oenb_core[22] la_oenb_core[23] la_oenb_core[24] la_oenb_core[25]
++ la_oenb_core[26] la_oenb_core[27] la_oenb_core[28] la_oenb_core[29] la_oenb_core[2]
++ la_oenb_core[30] la_oenb_core[31] la_oenb_core[32] la_oenb_core[33] la_oenb_core[34]
++ la_oenb_core[35] la_oenb_core[36] la_oenb_core[37] la_oenb_core[38] la_oenb_core[39]
++ la_oenb_core[3] la_oenb_core[40] la_oenb_core[41] la_oenb_core[42] la_oenb_core[43]
++ la_oenb_core[44] la_oenb_core[45] la_oenb_core[46] la_oenb_core[47] la_oenb_core[48]
++ la_oenb_core[49] la_oenb_core[4] la_oenb_core[50] la_oenb_core[51] la_oenb_core[52]
++ la_oenb_core[53] la_oenb_core[54] la_oenb_core[55] la_oenb_core[56] la_oenb_core[57]
++ la_oenb_core[58] la_oenb_core[59] la_oenb_core[5] la_oenb_core[60] la_oenb_core[61]
++ la_oenb_core[62] la_oenb_core[63] la_oenb_core[64] la_oenb_core[65] la_oenb_core[66]
++ la_oenb_core[67] la_oenb_core[68] la_oenb_core[69] la_oenb_core[6] la_oenb_core[70]
++ la_oenb_core[71] la_oenb_core[72] la_oenb_core[73] la_oenb_core[74] la_oenb_core[75]
++ la_oenb_core[76] la_oenb_core[77] la_oenb_core[78] la_oenb_core[79] la_oenb_core[7]
++ la_oenb_core[80] la_oenb_core[81] la_oenb_core[82] la_oenb_core[83] la_oenb_core[84]
++ la_oenb_core[85] la_oenb_core[86] la_oenb_core[87] la_oenb_core[88] la_oenb_core[89]
++ la_oenb_core[8] la_oenb_core[90] la_oenb_core[91] la_oenb_core[92] la_oenb_core[93]
++ la_oenb_core[94] la_oenb_core[95] la_oenb_core[96] la_oenb_core[97] la_oenb_core[98]
++ la_oenb_core[99] la_oenb_core[9] la_oenb_mprj[0] la_oenb_mprj[100] la_oenb_mprj[101]
++ la_oenb_mprj[102] la_oenb_mprj[103] la_oenb_mprj[104] la_oenb_mprj[105] la_oenb_mprj[106]
++ la_oenb_mprj[107] la_oenb_mprj[108] la_oenb_mprj[109] la_oenb_mprj[10] la_oenb_mprj[110]
++ la_oenb_mprj[111] la_oenb_mprj[112] la_oenb_mprj[113] la_oenb_mprj[114] la_oenb_mprj[115]
++ la_oenb_mprj[116] la_oenb_mprj[117] la_oenb_mprj[118] la_oenb_mprj[119] la_oenb_mprj[11]
++ la_oenb_mprj[120] la_oenb_mprj[121] la_oenb_mprj[122] la_oenb_mprj[123] la_oenb_mprj[124]
++ la_oenb_mprj[125] la_oenb_mprj[126] la_oenb_mprj[127] la_oenb_mprj[12] la_oenb_mprj[13]
++ la_oenb_mprj[14] la_oenb_mprj[15] la_oenb_mprj[16] la_oenb_mprj[17] la_oenb_mprj[18]
++ la_oenb_mprj[19] la_oenb_mprj[1] la_oenb_mprj[20] la_oenb_mprj[21] la_oenb_mprj[22]
++ la_oenb_mprj[23] la_oenb_mprj[24] la_oenb_mprj[25] la_oenb_mprj[26] la_oenb_mprj[27]
++ la_oenb_mprj[28] la_oenb_mprj[29] la_oenb_mprj[2] la_oenb_mprj[30] la_oenb_mprj[31]
++ la_oenb_mprj[32] la_oenb_mprj[33] la_oenb_mprj[34] la_oenb_mprj[35] la_oenb_mprj[36]
++ la_oenb_mprj[37] la_oenb_mprj[38] la_oenb_mprj[39] la_oenb_mprj[3] la_oenb_mprj[40]
++ la_oenb_mprj[41] la_oenb_mprj[42] la_oenb_mprj[43] la_oenb_mprj[44] la_oenb_mprj[45]
++ la_oenb_mprj[46] la_oenb_mprj[47] la_oenb_mprj[48] la_oenb_mprj[49] la_oenb_mprj[4]
++ la_oenb_mprj[50] la_oenb_mprj[51] la_oenb_mprj[52] la_oenb_mprj[53] la_oenb_mprj[54]
++ la_oenb_mprj[55] la_oenb_mprj[56] la_oenb_mprj[57] la_oenb_mprj[58] la_oenb_mprj[59]
++ la_oenb_mprj[5] la_oenb_mprj[60] la_oenb_mprj[61] la_oenb_mprj[62] la_oenb_mprj[63]
++ la_oenb_mprj[64] la_oenb_mprj[65] la_oenb_mprj[66] la_oenb_mprj[67] la_oenb_mprj[68]
++ la_oenb_mprj[69] la_oenb_mprj[6] la_oenb_mprj[70] la_oenb_mprj[71] la_oenb_mprj[72]
++ la_oenb_mprj[73] la_oenb_mprj[74] la_oenb_mprj[75] la_oenb_mprj[76] la_oenb_mprj[77]
++ la_oenb_mprj[78] la_oenb_mprj[79] la_oenb_mprj[7] la_oenb_mprj[80] la_oenb_mprj[81]
++ la_oenb_mprj[82] la_oenb_mprj[83] la_oenb_mprj[84] la_oenb_mprj[85] la_oenb_mprj[86]
++ la_oenb_mprj[87] la_oenb_mprj[88] la_oenb_mprj[89] la_oenb_mprj[8] la_oenb_mprj[90]
++ la_oenb_mprj[91] la_oenb_mprj[92] la_oenb_mprj[93] la_oenb_mprj[94] la_oenb_mprj[95]
++ la_oenb_mprj[96] la_oenb_mprj[97] la_oenb_mprj[98] la_oenb_mprj[99] la_oenb_mprj[9]
++ mprj_adr_o_core[0] mprj_adr_o_core[10] mprj_adr_o_core[11] mprj_adr_o_core[12] mprj_adr_o_core[13]
++ mprj_adr_o_core[14] mprj_adr_o_core[15] mprj_adr_o_core[16] mprj_adr_o_core[17]
++ mprj_adr_o_core[18] mprj_adr_o_core[19] mprj_adr_o_core[1] mprj_adr_o_core[20] mprj_adr_o_core[21]
++ mprj_adr_o_core[22] mprj_adr_o_core[23] mprj_adr_o_core[24] mprj_adr_o_core[25]
++ mprj_adr_o_core[26] mprj_adr_o_core[27] mprj_adr_o_core[28] mprj_adr_o_core[29]
++ mprj_adr_o_core[2] mprj_adr_o_core[30] mprj_adr_o_core[31] mprj_adr_o_core[3] mprj_adr_o_core[4]
++ mprj_adr_o_core[5] mprj_adr_o_core[6] mprj_adr_o_core[7] mprj_adr_o_core[8] mprj_adr_o_core[9]
++ mprj_adr_o_user[0] mprj_adr_o_user[10] mprj_adr_o_user[11] mprj_adr_o_user[12] mprj_adr_o_user[13]
++ mprj_adr_o_user[14] mprj_adr_o_user[15] mprj_adr_o_user[16] mprj_adr_o_user[17]
++ mprj_adr_o_user[18] mprj_adr_o_user[19] mprj_adr_o_user[1] mprj_adr_o_user[20] mprj_adr_o_user[21]
++ mprj_adr_o_user[22] mprj_adr_o_user[23] mprj_adr_o_user[24] mprj_adr_o_user[25]
++ mprj_adr_o_user[26] mprj_adr_o_user[27] mprj_adr_o_user[28] mprj_adr_o_user[29]
++ mprj_adr_o_user[2] mprj_adr_o_user[30] mprj_adr_o_user[31] mprj_adr_o_user[3] mprj_adr_o_user[4]
++ mprj_adr_o_user[5] mprj_adr_o_user[6] mprj_adr_o_user[7] mprj_adr_o_user[8] mprj_adr_o_user[9]
++ mprj_cyc_o_core mprj_cyc_o_user mprj_dat_o_core[0] mprj_dat_o_core[10] mprj_dat_o_core[11]
++ mprj_dat_o_core[12] mprj_dat_o_core[13] mprj_dat_o_core[14] mprj_dat_o_core[15]
++ mprj_dat_o_core[16] mprj_dat_o_core[17] mprj_dat_o_core[18] mprj_dat_o_core[19]
++ mprj_dat_o_core[1] mprj_dat_o_core[20] mprj_dat_o_core[21] mprj_dat_o_core[22] mprj_dat_o_core[23]
++ mprj_dat_o_core[24] mprj_dat_o_core[25] mprj_dat_o_core[26] mprj_dat_o_core[27]
++ mprj_dat_o_core[28] mprj_dat_o_core[29] mprj_dat_o_core[2] mprj_dat_o_core[30] mprj_dat_o_core[31]
++ mprj_dat_o_core[3] mprj_dat_o_core[4] mprj_dat_o_core[5] mprj_dat_o_core[6] mprj_dat_o_core[7]
++ mprj_dat_o_core[8] mprj_dat_o_core[9] mprj_dat_o_user[0] mprj_dat_o_user[10] mprj_dat_o_user[11]
++ mprj_dat_o_user[12] mprj_dat_o_user[13] mprj_dat_o_user[14] mprj_dat_o_user[15]
++ mprj_dat_o_user[16] mprj_dat_o_user[17] mprj_dat_o_user[18] mprj_dat_o_user[19]
++ mprj_dat_o_user[1] mprj_dat_o_user[20] mprj_dat_o_user[21] mprj_dat_o_user[22] mprj_dat_o_user[23]
++ mprj_dat_o_user[24] mprj_dat_o_user[25] mprj_dat_o_user[26] mprj_dat_o_user[27]
++ mprj_dat_o_user[28] mprj_dat_o_user[29] mprj_dat_o_user[2] mprj_dat_o_user[30] mprj_dat_o_user[31]
++ mprj_dat_o_user[3] mprj_dat_o_user[4] mprj_dat_o_user[5] mprj_dat_o_user[6] mprj_dat_o_user[7]
++ mprj_dat_o_user[8] mprj_dat_o_user[9] mprj_sel_o_core[0] mprj_sel_o_core[1] mprj_sel_o_core[2]
++ mprj_sel_o_core[3] mprj_sel_o_user[0] mprj_sel_o_user[1] mprj_sel_o_user[2] mprj_sel_o_user[3]
++ mprj_stb_o_core mprj_stb_o_user mprj_we_o_core mprj_we_o_user user1_vcc_powergood
++ user1_vdd_powergood user2_vcc_powergood user2_vdd_powergood user_clock user_clock2
++ user_irq[0] user_irq[1] user_irq[2] user_irq_core[0] user_irq_core[1] user_irq_core[2]
++ user_irq_ena[0] user_irq_ena[1] user_irq_ena[2] user_reset vccd vssd vccd1 vssd1
++ vccd2 vssd2 vdda1 vssa1 vdda2 vssa2
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped abstract view
+.subckt sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped A X VPWR VGND LVPWR LVGND
+.ends
+
+* Black-box entry subcircuit for user_project_wrapper abstract view
+.subckt user_project_wrapper analog_io[0] analog_io[10] analog_io[11] analog_io[12]
++ analog_io[13] analog_io[14] analog_io[15] analog_io[16] analog_io[17] analog_io[18]
++ analog_io[19] analog_io[1] analog_io[20] analog_io[21] analog_io[22] analog_io[23]
++ analog_io[24] analog_io[25] analog_io[26] analog_io[27] analog_io[28] analog_io[2]
++ analog_io[3] analog_io[4] analog_io[5] analog_io[6] analog_io[7] analog_io[8] analog_io[9]
++ io_in[0] io_out[0] io_in[10] io_out[10] io_in[11] io_out[11] io_in[12] io_out[12]
++ io_in[13] io_out[13] io_in[14] io_out[14] io_in[15] io_out[15] io_in[16] io_out[16]
++ io_in[17] io_out[17] io_in[18] io_out[18] io_in[19] io_out[19] io_in[1] io_out[1]
++ io_in[20] io_out[20] io_in[21] io_out[21] io_in[22] io_out[22] io_in[23] io_out[23]
++ io_in[24] io_out[24] io_in[25] io_out[25] io_in[26] io_out[26] io_in[27] io_out[27]
++ io_in[28] io_out[28] io_in[29] io_out[29] io_in[2] io_out[2] io_in[30] io_out[30]
++ io_in[31] io_out[31] io_in[32] io_out[32] io_in[33] io_out[33] io_in[34] io_out[34]
++ io_in[35] io_out[35] io_in[36] io_out[36] io_in[37] io_out[37] io_in[3] io_out[3]
++ io_in[4] io_out[4] io_in[5] io_out[5] io_in[6] io_out[6] io_in[7] io_out[7] io_in[8]
++ io_out[8] io_in[9] io_out[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
++ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
++ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[27] io_oeb[28]
++ io_oeb[29] io_oeb[2] io_oeb[30] io_oeb[31] io_oeb[32] io_oeb[33] io_oeb[34] io_oeb[35]
++ io_oeb[36] io_oeb[37] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
++ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
++ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
++ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
++ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
++ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
++ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
++ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
++ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
++ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
++ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
++ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
++ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
++ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
++ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
++ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
++ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
++ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
++ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
++ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
++ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
++ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
++ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
++ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
++ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
++ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
++ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
++ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
++ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
++ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
++ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
++ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
++ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
++ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
++ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
++ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
++ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
++ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
++ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
++ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
++ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
++ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
++ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
++ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
++ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
++ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
++ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
++ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
++ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
++ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
++ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
++ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
++ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
++ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
++ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
++ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
++ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
++ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
++ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
++ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
++ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
++ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
++ user_clock2 user_irq[0] user_irq[1] user_irq[2] wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i vccd1 vssd1 vccd2 vssd2 vdda1 vssa1 vdda2 vssa2
+.ends
+
+* Black-box entry subcircuit for copyright_block abstract view
+.subckt copyright_block VSUBS
+.ends
+
+* Black-box entry subcircuit for storage abstract view
+.subckt storage mgmt_addr[0] mgmt_addr[1] mgmt_addr[2] mgmt_addr[3] mgmt_addr[4] mgmt_addr[5]
++ mgmt_addr[6] mgmt_addr[7] mgmt_addr_ro[0] mgmt_addr_ro[1] mgmt_addr_ro[2] mgmt_addr_ro[3]
++ mgmt_addr_ro[4] mgmt_addr_ro[5] mgmt_addr_ro[6] mgmt_addr_ro[7] mgmt_clk mgmt_ena[0]
++ mgmt_ena[1] mgmt_ena_ro mgmt_rdata[0] mgmt_rdata[10] mgmt_rdata[11] mgmt_rdata[12]
++ mgmt_rdata[13] mgmt_rdata[14] mgmt_rdata[15] mgmt_rdata[16] mgmt_rdata[17] mgmt_rdata[18]
++ mgmt_rdata[19] mgmt_rdata[1] mgmt_rdata[20] mgmt_rdata[21] mgmt_rdata[22] mgmt_rdata[23]
++ mgmt_rdata[24] mgmt_rdata[25] mgmt_rdata[26] mgmt_rdata[27] mgmt_rdata[28] mgmt_rdata[29]
++ mgmt_rdata[2] mgmt_rdata[30] mgmt_rdata[31] mgmt_rdata[32] mgmt_rdata[33] mgmt_rdata[34]
++ mgmt_rdata[35] mgmt_rdata[36] mgmt_rdata[37] mgmt_rdata[38] mgmt_rdata[39] mgmt_rdata[3]
++ mgmt_rdata[40] mgmt_rdata[41] mgmt_rdata[42] mgmt_rdata[43] mgmt_rdata[44] mgmt_rdata[45]
++ mgmt_rdata[46] mgmt_rdata[47] mgmt_rdata[48] mgmt_rdata[49] mgmt_rdata[4] mgmt_rdata[50]
++ mgmt_rdata[51] mgmt_rdata[52] mgmt_rdata[53] mgmt_rdata[54] mgmt_rdata[55] mgmt_rdata[56]
++ mgmt_rdata[57] mgmt_rdata[58] mgmt_rdata[59] mgmt_rdata[5] mgmt_rdata[60] mgmt_rdata[61]
++ mgmt_rdata[62] mgmt_rdata[63] mgmt_rdata[6] mgmt_rdata[7] mgmt_rdata[8] mgmt_rdata[9]
++ mgmt_rdata_ro[0] mgmt_rdata_ro[10] mgmt_rdata_ro[11] mgmt_rdata_ro[12] mgmt_rdata_ro[13]
++ mgmt_rdata_ro[14] mgmt_rdata_ro[15] mgmt_rdata_ro[16] mgmt_rdata_ro[17] mgmt_rdata_ro[18]
++ mgmt_rdata_ro[19] mgmt_rdata_ro[1] mgmt_rdata_ro[20] mgmt_rdata_ro[21] mgmt_rdata_ro[22]
++ mgmt_rdata_ro[23] mgmt_rdata_ro[24] mgmt_rdata_ro[25] mgmt_rdata_ro[26] mgmt_rdata_ro[27]
++ mgmt_rdata_ro[28] mgmt_rdata_ro[29] mgmt_rdata_ro[2] mgmt_rdata_ro[30] mgmt_rdata_ro[31]
++ mgmt_rdata_ro[3] mgmt_rdata_ro[4] mgmt_rdata_ro[5] mgmt_rdata_ro[6] mgmt_rdata_ro[7]
++ mgmt_rdata_ro[8] mgmt_rdata_ro[9] mgmt_wdata[0] mgmt_wdata[10] mgmt_wdata[11] mgmt_wdata[12]
++ mgmt_wdata[13] mgmt_wdata[14] mgmt_wdata[15] mgmt_wdata[16] mgmt_wdata[17] mgmt_wdata[18]
++ mgmt_wdata[19] mgmt_wdata[1] mgmt_wdata[20] mgmt_wdata[21] mgmt_wdata[22] mgmt_wdata[23]
++ mgmt_wdata[24] mgmt_wdata[25] mgmt_wdata[26] mgmt_wdata[27] mgmt_wdata[28] mgmt_wdata[29]
++ mgmt_wdata[2] mgmt_wdata[30] mgmt_wdata[31] mgmt_wdata[3] mgmt_wdata[4] mgmt_wdata[5]
++ mgmt_wdata[6] mgmt_wdata[7] mgmt_wdata[8] mgmt_wdata[9] mgmt_wen[0] mgmt_wen[1]
++ mgmt_wen_mask[0] mgmt_wen_mask[1] mgmt_wen_mask[2] mgmt_wen_mask[3] mgmt_wen_mask[4]
++ mgmt_wen_mask[5] mgmt_wen_mask[6] mgmt_wen_mask[7] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for caravel_power_routing abstract view
+.subckt caravel_power_routing VSUBS vccd1_core vssd_core vdda1_core vssd2_core vssio_core
++ vssa2_core vddio_core vccd2_core vdda2_core vssd1_core vccd_core vssa1_core
+.ends
+
+.subckt caravel clock flash_clk flash_csb flash_io0 flash_io1 gpio mprj_io[0] mprj_io[10]
++ mprj_io[11] mprj_io[12] mprj_io[13] mprj_io[14] mprj_io[15] mprj_io[16] mprj_io[17]
++ mprj_io[18] mprj_io[19] mprj_io[1] mprj_io[20] mprj_io[21] mprj_io[22] mprj_io[23]
++ mprj_io[24] mprj_io[25] mprj_io[26] mprj_io[27] mprj_io[28] mprj_io[29] mprj_io[2]
++ mprj_io[30] mprj_io[31] mprj_io[32] mprj_io[33] mprj_io[34] mprj_io[35] mprj_io[36]
++ mprj_io[37] mprj_io[3] mprj_io[4] mprj_io[5] mprj_io[6] mprj_io[7] mprj_io[8] mprj_io[9]
++ resetb vccd vccd1 vccd2 vdda vdda1 vdda1_2 vdda2 vddio vddio_2 vssa vssa1 vssa1_2
++ vssa2 vssd vssd1 vssd2 vssio vssio_2 pwr_ctrl_out[0] pwr_ctrl_out[1] pwr_ctrl_out[2]
++ pwr_ctrl_out[3]
+Xgpio_control_in_1\[16\] soc/mgmt_in_data[18] gpio_control_in_1\[16\]/one soc/mgmt_in_data[18]
++ gpio_control_in_1\[16\]/one padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18]
++ padframe/mprj_io_analog_sel[18] padframe/mprj_io_dm[54] padframe/mprj_io_dm[55]
++ padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18] padframe/mprj_io_ib_mode_sel[18]
++ padframe/mprj_io_in[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_out[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18] gpio_control_in_1\[16\]/resetn
++ gpio_control_in_1\[16\]/resetn_out gpio_control_in_1\[16\]/serial_clock gpio_control_in_1\[16\]/serial_clock_out
++ gpio_control_in_1\[16\]/serial_data_in gpio_control_in_1\[16\]/serial_data_out mprj/io_in[18]
++ mprj/io_oeb[18] mprj/io_out[18] gpio_control_in_1\[16\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[0\] soc/mgmt_in_data[19] gpio_control_in_2\[0\]/one soc/mgmt_in_data[19]
++ gpio_control_in_2\[0\]/one padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19]
++ padframe/mprj_io_analog_sel[19] padframe/mprj_io_dm[57] padframe/mprj_io_dm[58]
++ padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19] padframe/mprj_io_ib_mode_sel[19]
++ padframe/mprj_io_in[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_out[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19] soc/mprj_io_loader_resetn
++ gpio_control_in_2\[1\]/resetn soc/mprj_io_loader_clock gpio_control_in_2\[1\]/serial_clock
++ gpio_control_in_2\[0\]/serial_data_in gpio_control_in_2\[0\]/serial_data_out mprj/io_in[19]
++ mprj/io_oeb[19] mprj/io_out[19] gpio_control_in_2\[0\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[6\] soc/mgmt_in_data[8] gpio_control_in_1\[6\]/one soc/mgmt_in_data[8]
++ gpio_control_in_1\[6\]/one padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8]
++ padframe/mprj_io_analog_sel[8] padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26]
++ padframe/mprj_io_holdover[8] padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_in[8]
++ padframe/mprj_io_inp_dis[8] padframe/mprj_io_out[8] padframe/mprj_io_oeb[8] padframe/mprj_io_slow_sel[8]
++ padframe/mprj_io_vtrip_sel[8] gpio_control_in_2\[8\]/resetn gpio_control_in_2\[9\]/resetn
++ gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[6\]/serial_data_in
++ gpio_control_in_1\[7\]/serial_data_in mprj/io_in[8] mprj/io_oeb[8] mprj/io_out[8]
++ gpio_control_in_1\[6\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xpadframe clock soc/clock por/por_l flash_clk soc/flash_clk soc/flash_clk_ieb soc/flash_clk_oeb
++ flash_csb soc/flash_csb soc/flash_csb_ieb soc/flash_csb_oeb flash_io0 soc/flash_io0_di
++ soc/flash_io0_do soc/flash_io0_ieb soc/flash_io0_oeb flash_io1 soc/flash_io1_di
++ soc/flash_io1_do soc/flash_io1_ieb soc/flash_io1_oeb gpio soc/gpio_in_pad soc/gpio_inenb_pad
++ soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad vccd
++ vdda vddio vddio_2 vssa vssd vssio vssio_2 mprj_io[0] padframe/mprj_io_analog_en[0]
++ padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0] padframe/mprj_io_dm[0]
++ padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0] padframe/mprj_io_ib_mode_sel[0]
++ padframe/mprj_io_inp_dis[0] padframe/mprj_io_oeb[0] padframe/mprj_io_out[0] padframe/mprj_io_slow_sel[0]
++ padframe/mprj_io_vtrip_sel[0] padframe/mprj_io_in[0] mprj/analog_io[3] mprj_io[10]
++ padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10] padframe/mprj_io_analog_sel[10]
++ padframe/mprj_io_dm[30] padframe/mprj_io_dm[31] padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10]
++ padframe/mprj_io_ib_mode_sel[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_out[10] padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10]
++ padframe/mprj_io_in[10] mprj/analog_io[4] mprj_io[11] padframe/mprj_io_analog_en[11]
++ padframe/mprj_io_analog_pol[11] padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33]
++ padframe/mprj_io_dm[34] padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11] padframe/mprj_io_ib_mode_sel[11]
++ padframe/mprj_io_inp_dis[11] padframe/mprj_io_oeb[11] padframe/mprj_io_out[11] padframe/mprj_io_slow_sel[11]
++ padframe/mprj_io_vtrip_sel[11] padframe/mprj_io_in[11] mprj/analog_io[5] mprj_io[12]
++ padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12] padframe/mprj_io_analog_sel[12]
++ padframe/mprj_io_dm[36] padframe/mprj_io_dm[37] padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12]
++ padframe/mprj_io_ib_mode_sel[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_out[12] padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12]
++ padframe/mprj_io_in[12] mprj/analog_io[6] mprj_io[13] padframe/mprj_io_analog_en[13]
++ padframe/mprj_io_analog_pol[13] padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39]
++ padframe/mprj_io_dm[40] padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13] padframe/mprj_io_ib_mode_sel[13]
++ padframe/mprj_io_inp_dis[13] padframe/mprj_io_oeb[13] padframe/mprj_io_out[13] padframe/mprj_io_slow_sel[13]
++ padframe/mprj_io_vtrip_sel[13] padframe/mprj_io_in[13] mprj/analog_io[7] mprj_io[14]
++ padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14]
++ padframe/mprj_io_dm[42] padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14]
++ padframe/mprj_io_in[14] mprj/analog_io[8] mprj_io[15] padframe/mprj_io_analog_en[15]
++ padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15] padframe/mprj_io_dm[45]
++ padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15] padframe/mprj_io_ib_mode_sel[15]
++ padframe/mprj_io_inp_dis[15] padframe/mprj_io_oeb[15] padframe/mprj_io_out[15] padframe/mprj_io_slow_sel[15]
++ padframe/mprj_io_vtrip_sel[15] padframe/mprj_io_in[15] mprj/analog_io[9] mprj_io[16]
++ padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16]
++ padframe/mprj_io_dm[48] padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16]
++ padframe/mprj_io_in[16] mprj/analog_io[10] mprj_io[17] padframe/mprj_io_analog_en[17]
++ padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17] padframe/mprj_io_dm[51]
++ padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17] padframe/mprj_io_ib_mode_sel[17]
++ padframe/mprj_io_inp_dis[17] padframe/mprj_io_oeb[17] padframe/mprj_io_out[17] padframe/mprj_io_slow_sel[17]
++ padframe/mprj_io_vtrip_sel[17] padframe/mprj_io_in[17] mprj/analog_io[11] mprj_io[18]
++ padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18]
++ padframe/mprj_io_dm[54] padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18]
++ padframe/mprj_io_in[18] mprj_io[1] padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1]
++ padframe/mprj_io_analog_sel[1] padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5]
++ padframe/mprj_io_holdover[1] padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_oeb[1] padframe/mprj_io_out[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ padframe/mprj_io_in[1] mprj_io[2] padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2]
++ padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8]
++ padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_inp_dis[2]
++ padframe/mprj_io_oeb[2] padframe/mprj_io_out[2] padframe/mprj_io_slow_sel[2] padframe/mprj_io_vtrip_sel[2]
++ padframe/mprj_io_in[2] mprj_io[3] padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3]
++ padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[10] padframe/mprj_io_dm[11] padframe/mprj_io_dm[9]
++ padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_inp_dis[3]
++ padframe/mprj_io_oeb[3] padframe/mprj_io_out[3] padframe/mprj_io_slow_sel[3] padframe/mprj_io_vtrip_sel[3]
++ padframe/mprj_io_in[3] mprj_io[4] padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4]
++ padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14]
++ padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_inp_dis[4]
++ padframe/mprj_io_oeb[4] padframe/mprj_io_out[4] padframe/mprj_io_slow_sel[4] padframe/mprj_io_vtrip_sel[4]
++ padframe/mprj_io_in[4] mprj_io[5] padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5]
++ padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17]
++ padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_inp_dis[5]
++ padframe/mprj_io_oeb[5] padframe/mprj_io_out[5] padframe/mprj_io_slow_sel[5] padframe/mprj_io_vtrip_sel[5]
++ padframe/mprj_io_in[5] mprj_io[6] padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6]
++ padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20]
++ padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_inp_dis[6]
++ padframe/mprj_io_oeb[6] padframe/mprj_io_out[6] padframe/mprj_io_slow_sel[6] padframe/mprj_io_vtrip_sel[6]
++ padframe/mprj_io_in[6] mprj/analog_io[0] mprj_io[7] padframe/mprj_io_analog_en[7]
++ padframe/mprj_io_analog_pol[7] padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21]
++ padframe/mprj_io_dm[22] padframe/mprj_io_dm[23] padframe/mprj_io_holdover[7] padframe/mprj_io_ib_mode_sel[7]
++ padframe/mprj_io_inp_dis[7] padframe/mprj_io_oeb[7] padframe/mprj_io_out[7] padframe/mprj_io_slow_sel[7]
++ padframe/mprj_io_vtrip_sel[7] padframe/mprj_io_in[7] mprj/analog_io[1] mprj_io[8]
++ padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8]
++ padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_inp_dis[8] padframe/mprj_io_oeb[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ padframe/mprj_io_in[8] mprj/analog_io[2] mprj_io[9] padframe/mprj_io_analog_en[9]
++ padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9] padframe/mprj_io_dm[27]
++ padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] padframe/mprj_io_holdover[9] padframe/mprj_io_ib_mode_sel[9]
++ padframe/mprj_io_inp_dis[9] padframe/mprj_io_oeb[9] padframe/mprj_io_out[9] padframe/mprj_io_slow_sel[9]
++ padframe/mprj_io_vtrip_sel[9] padframe/mprj_io_in[9] mprj/analog_io[12] mprj_io[19]
++ padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19]
++ padframe/mprj_io_dm[57] padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19]
++ padframe/mprj_io_in[19] mprj/analog_io[22] mprj_io[29] padframe/mprj_io_analog_en[29]
++ padframe/mprj_io_analog_pol[29] padframe/mprj_io_analog_sel[29] padframe/mprj_io_dm[87]
++ padframe/mprj_io_dm[88] padframe/mprj_io_dm[89] padframe/mprj_io_holdover[29] padframe/mprj_io_ib_mode_sel[29]
++ padframe/mprj_io_inp_dis[29] padframe/mprj_io_oeb[29] padframe/mprj_io_out[29] padframe/mprj_io_slow_sel[29]
++ padframe/mprj_io_vtrip_sel[29] padframe/mprj_io_in[29] mprj/analog_io[23] mprj_io[30]
++ padframe/mprj_io_analog_en[30] padframe/mprj_io_analog_pol[30] padframe/mprj_io_analog_sel[30]
++ padframe/mprj_io_dm[90] padframe/mprj_io_dm[91] padframe/mprj_io_dm[92] padframe/mprj_io_holdover[30]
++ padframe/mprj_io_ib_mode_sel[30] padframe/mprj_io_inp_dis[30] padframe/mprj_io_oeb[30]
++ padframe/mprj_io_out[30] padframe/mprj_io_slow_sel[30] padframe/mprj_io_vtrip_sel[30]
++ padframe/mprj_io_in[30] mprj/analog_io[24] mprj_io[31] padframe/mprj_io_analog_en[31]
++ padframe/mprj_io_analog_pol[31] padframe/mprj_io_analog_sel[31] padframe/mprj_io_dm[93]
++ padframe/mprj_io_dm[94] padframe/mprj_io_dm[95] padframe/mprj_io_holdover[31] padframe/mprj_io_ib_mode_sel[31]
++ padframe/mprj_io_inp_dis[31] padframe/mprj_io_oeb[31] padframe/mprj_io_out[31] padframe/mprj_io_slow_sel[31]
++ padframe/mprj_io_vtrip_sel[31] padframe/mprj_io_in[31] mprj/analog_io[25] mprj_io[32]
++ padframe/mprj_io_analog_en[32] padframe/mprj_io_analog_pol[32] padframe/mprj_io_analog_sel[32]
++ padframe/mprj_io_dm[96] padframe/mprj_io_dm[97] padframe/mprj_io_dm[98] padframe/mprj_io_holdover[32]
++ padframe/mprj_io_ib_mode_sel[32] padframe/mprj_io_inp_dis[32] padframe/mprj_io_oeb[32]
++ padframe/mprj_io_out[32] padframe/mprj_io_slow_sel[32] padframe/mprj_io_vtrip_sel[32]
++ padframe/mprj_io_in[32] mprj/analog_io[26] mprj_io[33] padframe/mprj_io_analog_en[33]
++ padframe/mprj_io_analog_pol[33] padframe/mprj_io_analog_sel[33] padframe/mprj_io_dm[100]
++ padframe/mprj_io_dm[101] padframe/mprj_io_dm[99] padframe/mprj_io_holdover[33] padframe/mprj_io_ib_mode_sel[33]
++ padframe/mprj_io_inp_dis[33] padframe/mprj_io_oeb[33] padframe/mprj_io_out[33] padframe/mprj_io_slow_sel[33]
++ padframe/mprj_io_vtrip_sel[33] padframe/mprj_io_in[33] mprj/analog_io[27] mprj_io[34]
++ padframe/mprj_io_analog_en[34] padframe/mprj_io_analog_pol[34] padframe/mprj_io_analog_sel[34]
++ padframe/mprj_io_dm[102] padframe/mprj_io_dm[103] padframe/mprj_io_dm[104] padframe/mprj_io_holdover[34]
++ padframe/mprj_io_ib_mode_sel[34] padframe/mprj_io_inp_dis[34] padframe/mprj_io_oeb[34]
++ padframe/mprj_io_out[34] padframe/mprj_io_slow_sel[34] padframe/mprj_io_vtrip_sel[34]
++ padframe/mprj_io_in[34] mprj/analog_io[28] mprj_io[35] padframe/mprj_io_analog_en[35]
++ padframe/mprj_io_analog_pol[35] padframe/mprj_io_analog_sel[35] padframe/mprj_io_dm[105]
++ padframe/mprj_io_dm[106] padframe/mprj_io_dm[107] padframe/mprj_io_holdover[35]
++ padframe/mprj_io_ib_mode_sel[35] padframe/mprj_io_inp_dis[35] padframe/mprj_io_oeb[35]
++ padframe/mprj_io_out[35] padframe/mprj_io_slow_sel[35] padframe/mprj_io_vtrip_sel[35]
++ padframe/mprj_io_in[35] mprj_io[36] padframe/mprj_io_analog_en[36] padframe/mprj_io_analog_pol[36]
++ padframe/mprj_io_analog_sel[36] padframe/mprj_io_dm[108] padframe/mprj_io_dm[109]
++ padframe/mprj_io_dm[110] padframe/mprj_io_holdover[36] padframe/mprj_io_ib_mode_sel[36]
++ padframe/mprj_io_inp_dis[36] padframe/mprj_io_oeb[36] padframe/mprj_io_out[36] padframe/mprj_io_slow_sel[36]
++ padframe/mprj_io_vtrip_sel[36] padframe/mprj_io_in[36] mprj_io[37] padframe/mprj_io_analog_en[37]
++ padframe/mprj_io_analog_pol[37] padframe/mprj_io_analog_sel[37] padframe/mprj_io_dm[111]
++ padframe/mprj_io_dm[112] padframe/mprj_io_dm[113] padframe/mprj_io_holdover[37]
++ padframe/mprj_io_ib_mode_sel[37] padframe/mprj_io_inp_dis[37] padframe/mprj_io_oeb[37]
++ padframe/mprj_io_out[37] padframe/mprj_io_slow_sel[37] padframe/mprj_io_vtrip_sel[37]
++ padframe/mprj_io_in[37] mprj/analog_io[13] mprj_io[20] padframe/mprj_io_analog_en[20]
++ padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20] padframe/mprj_io_dm[60]
++ padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20] padframe/mprj_io_ib_mode_sel[20]
++ padframe/mprj_io_inp_dis[20] padframe/mprj_io_oeb[20] padframe/mprj_io_out[20] padframe/mprj_io_slow_sel[20]
++ padframe/mprj_io_vtrip_sel[20] padframe/mprj_io_in[20] mprj/analog_io[14] mprj_io[21]
++ padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21]
++ padframe/mprj_io_dm[63] padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21]
++ padframe/mprj_io_in[21] mprj/analog_io[15] mprj_io[22] padframe/mprj_io_analog_en[22]
++ padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22] padframe/mprj_io_dm[66]
++ padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22] padframe/mprj_io_ib_mode_sel[22]
++ padframe/mprj_io_inp_dis[22] padframe/mprj_io_oeb[22] padframe/mprj_io_out[22] padframe/mprj_io_slow_sel[22]
++ padframe/mprj_io_vtrip_sel[22] padframe/mprj_io_in[22] mprj/analog_io[16] mprj_io[23]
++ padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23]
++ padframe/mprj_io_dm[69] padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23]
++ padframe/mprj_io_in[23] mprj/analog_io[17] mprj_io[24] padframe/mprj_io_analog_en[24]
++ padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24] padframe/mprj_io_dm[72]
++ padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24] padframe/mprj_io_ib_mode_sel[24]
++ padframe/mprj_io_inp_dis[24] padframe/mprj_io_oeb[24] padframe/mprj_io_out[24] padframe/mprj_io_slow_sel[24]
++ padframe/mprj_io_vtrip_sel[24] padframe/mprj_io_in[24] mprj/analog_io[18] mprj_io[25]
++ padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25]
++ padframe/mprj_io_dm[75] padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25]
++ padframe/mprj_io_ib_mode_sel[25] padframe/mprj_io_inp_dis[25] padframe/mprj_io_oeb[25]
++ padframe/mprj_io_out[25] padframe/mprj_io_slow_sel[25] padframe/mprj_io_vtrip_sel[25]
++ padframe/mprj_io_in[25] mprj/analog_io[19] mprj_io[26] padframe/mprj_io_analog_en[26]
++ padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26] padframe/mprj_io_dm[78]
++ padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26] padframe/mprj_io_ib_mode_sel[26]
++ padframe/mprj_io_inp_dis[26] padframe/mprj_io_oeb[26] padframe/mprj_io_out[26] padframe/mprj_io_slow_sel[26]
++ padframe/mprj_io_vtrip_sel[26] padframe/mprj_io_in[26] mprj/analog_io[20] mprj_io[27]
++ padframe/mprj_io_analog_en[27] padframe/mprj_io_analog_pol[27] padframe/mprj_io_analog_sel[27]
++ padframe/mprj_io_dm[81] padframe/mprj_io_dm[82] padframe/mprj_io_dm[83] padframe/mprj_io_holdover[27]
++ padframe/mprj_io_ib_mode_sel[27] padframe/mprj_io_inp_dis[27] padframe/mprj_io_oeb[27]
++ padframe/mprj_io_out[27] padframe/mprj_io_slow_sel[27] padframe/mprj_io_vtrip_sel[27]
++ padframe/mprj_io_in[27] mprj/analog_io[21] mprj_io[28] padframe/mprj_io_analog_en[28]
++ padframe/mprj_io_analog_pol[28] padframe/mprj_io_analog_sel[28] padframe/mprj_io_dm[84]
++ padframe/mprj_io_dm[85] padframe/mprj_io_dm[86] padframe/mprj_io_holdover[28] padframe/mprj_io_ib_mode_sel[28]
++ padframe/mprj_io_inp_dis[28] padframe/mprj_io_oeb[28] padframe/mprj_io_out[28] padframe/mprj_io_slow_sel[28]
++ padframe/mprj_io_vtrip_sel[28] padframe/mprj_io_in[28] por/porb_h resetb rstb_level/A
++ padframe/vdda padframe/vssa vssd_core vccd1 vdda1 vdda1_2 vssa1 vssa1_2 vccd1_core
++ vdda1_core vssa1_core vssd1_core vssd1 vccd2 vdda2 vssa2 vccd_core vccd2_core vdda2_core
++ vddio_core vssa2_core vssd2_core vssd2 vssio_core chip_io
+Xgpio_control_in_2\[14\] soc/mgmt_in_data[33] gpio_control_in_2\[14\]/one soc/mgmt_in_data[33]
++ gpio_control_in_2\[14\]/one padframe/mprj_io_analog_en[33] padframe/mprj_io_analog_pol[33]
++ padframe/mprj_io_analog_sel[33] padframe/mprj_io_dm[99] padframe/mprj_io_dm[100]
++ padframe/mprj_io_dm[101] padframe/mprj_io_holdover[33] padframe/mprj_io_ib_mode_sel[33]
++ padframe/mprj_io_in[33] padframe/mprj_io_inp_dis[33] padframe/mprj_io_out[33] padframe/mprj_io_oeb[33]
++ padframe/mprj_io_slow_sel[33] padframe/mprj_io_vtrip_sel[33] gpio_control_in_2\[14\]/resetn
++ gpio_control_in_2\[15\]/resetn gpio_control_in_2\[14\]/serial_clock gpio_control_in_2\[15\]/serial_clock
++ gpio_control_in_2\[14\]/serial_data_in gpio_control_in_2\[13\]/serial_data_in mprj/io_in[33]
++ mprj/io_oeb[33] mprj/io_out[33] gpio_control_in_2\[14\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_bidir_2\[0\] soc/mgmt_in_data[36] soc/flash_io2_oeb soc/mgmt_out_data[36]
++ gpio_control_bidir_2\[0\]/one padframe/mprj_io_analog_en[36] padframe/mprj_io_analog_pol[36]
++ padframe/mprj_io_analog_sel[36] padframe/mprj_io_dm[108] padframe/mprj_io_dm[109]
++ padframe/mprj_io_dm[110] padframe/mprj_io_holdover[36] padframe/mprj_io_ib_mode_sel[36]
++ padframe/mprj_io_in[36] padframe/mprj_io_inp_dis[36] padframe/mprj_io_out[36] padframe/mprj_io_oeb[36]
++ padframe/mprj_io_slow_sel[36] padframe/mprj_io_vtrip_sel[36] gpio_control_in_1\[15\]/resetn
++ gpio_control_in_1\[16\]/resetn gpio_control_in_1\[15\]/serial_clock gpio_control_in_1\[16\]/serial_clock
++ gpio_control_bidir_2\[0\]/serial_data_in gpio_control_in_2\[16\]/serial_data_in
++ mprj/io_in[36] mprj/io_oeb[36] mprj/io_out[36] gpio_control_bidir_2\[0\]/zero vccd_core
++ vssd_core vccd1_core vssd1_core gpio_control_block
+Xsoc soc/clock soc/core_clk soc/core_rstn soc/flash_clk soc/flash_clk_ieb soc/flash_clk_oeb
++ soc/flash_csb soc/flash_csb_ieb soc/flash_csb_oeb soc/flash_io0_di soc/flash_io0_do
++ soc/flash_io0_ieb soc/flash_io0_oeb soc/flash_io1_di soc/flash_io1_do soc/flash_io1_ieb
++ soc/flash_io1_oeb soc/flash_io2_oeb soc/flash_io3_oeb soc/gpio_in_pad soc/gpio_inenb_pad
++ soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad soc/jtag_out
++ soc/jtag_outenb soc/la_iena[0] soc/la_iena[100] soc/la_iena[101] soc/la_iena[102]
++ soc/la_iena[103] soc/la_iena[104] soc/la_iena[105] soc/la_iena[106] soc/la_iena[107]
++ soc/la_iena[108] soc/la_iena[109] soc/la_iena[10] soc/la_iena[110] soc/la_iena[111]
++ soc/la_iena[112] soc/la_iena[113] soc/la_iena[114] soc/la_iena[115] soc/la_iena[116]
++ soc/la_iena[117] soc/la_iena[118] soc/la_iena[119] soc/la_iena[11] soc/la_iena[120]
++ soc/la_iena[121] soc/la_iena[122] soc/la_iena[123] soc/la_iena[124] soc/la_iena[125]
++ soc/la_iena[126] soc/la_iena[127] soc/la_iena[12] soc/la_iena[13] soc/la_iena[14]
++ soc/la_iena[15] soc/la_iena[16] soc/la_iena[17] soc/la_iena[18] soc/la_iena[19]
++ soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22] soc/la_iena[23] soc/la_iena[24]
++ soc/la_iena[25] soc/la_iena[26] soc/la_iena[27] soc/la_iena[28] soc/la_iena[29]
++ soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32] soc/la_iena[33] soc/la_iena[34]
++ soc/la_iena[35] soc/la_iena[36] soc/la_iena[37] soc/la_iena[38] soc/la_iena[39]
++ soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42] soc/la_iena[43] soc/la_iena[44]
++ soc/la_iena[45] soc/la_iena[46] soc/la_iena[47] soc/la_iena[48] soc/la_iena[49]
++ soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52] soc/la_iena[53] soc/la_iena[54]
++ soc/la_iena[55] soc/la_iena[56] soc/la_iena[57] soc/la_iena[58] soc/la_iena[59]
++ soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62] soc/la_iena[63] soc/la_iena[64]
++ soc/la_iena[65] soc/la_iena[66] soc/la_iena[67] soc/la_iena[68] soc/la_iena[69]
++ soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72] soc/la_iena[73] soc/la_iena[74]
++ soc/la_iena[75] soc/la_iena[76] soc/la_iena[77] soc/la_iena[78] soc/la_iena[79]
++ soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82] soc/la_iena[83] soc/la_iena[84]
++ soc/la_iena[85] soc/la_iena[86] soc/la_iena[87] soc/la_iena[88] soc/la_iena[89]
++ soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92] soc/la_iena[93] soc/la_iena[94]
++ soc/la_iena[95] soc/la_iena[96] soc/la_iena[97] soc/la_iena[98] soc/la_iena[99]
++ soc/la_iena[9] soc/la_input[0] soc/la_input[100] soc/la_input[101] soc/la_input[102]
++ soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106] soc/la_input[107]
++ soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110] soc/la_input[111]
++ soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115] soc/la_input[116]
++ soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11] soc/la_input[120]
++ soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124] soc/la_input[125]
++ soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13] soc/la_input[14]
++ soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18] soc/la_input[19]
++ soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22] soc/la_input[23]
++ soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27] soc/la_input[28]
++ soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31] soc/la_input[32]
++ soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36] soc/la_input[37]
++ soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40] soc/la_input[41]
++ soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45] soc/la_input[46]
++ soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4] soc/la_input[50]
++ soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54] soc/la_input[55]
++ soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59] soc/la_input[5]
++ soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63] soc/la_input[64]
++ soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68] soc/la_input[69]
++ soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72] soc/la_input[73]
++ soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77] soc/la_input[78]
++ soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81] soc/la_input[82]
++ soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86] soc/la_input[87]
++ soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90] soc/la_input[91]
++ soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95] soc/la_input[96]
++ soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9] soc/la_oenb[0]
++ soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102] soc/la_oenb[103] soc/la_oenb[104]
++ soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107] soc/la_oenb[108] soc/la_oenb[109]
++ soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111] soc/la_oenb[112] soc/la_oenb[113]
++ soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116] soc/la_oenb[117] soc/la_oenb[118]
++ soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120] soc/la_oenb[121] soc/la_oenb[122]
++ soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125] soc/la_oenb[126] soc/la_oenb[127]
++ soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14] soc/la_oenb[15] soc/la_oenb[16]
++ soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19] soc/la_oenb[1] soc/la_oenb[20] soc/la_oenb[21]
++ soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24] soc/la_oenb[25] soc/la_oenb[26]
++ soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29] soc/la_oenb[2] soc/la_oenb[30] soc/la_oenb[31]
++ soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34] soc/la_oenb[35] soc/la_oenb[36]
++ soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39] soc/la_oenb[3] soc/la_oenb[40] soc/la_oenb[41]
++ soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44] soc/la_oenb[45] soc/la_oenb[46]
++ soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49] soc/la_oenb[4] soc/la_oenb[50] soc/la_oenb[51]
++ soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54] soc/la_oenb[55] soc/la_oenb[56]
++ soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59] soc/la_oenb[5] soc/la_oenb[60] soc/la_oenb[61]
++ soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64] soc/la_oenb[65] soc/la_oenb[66]
++ soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69] soc/la_oenb[6] soc/la_oenb[70] soc/la_oenb[71]
++ soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74] soc/la_oenb[75] soc/la_oenb[76]
++ soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79] soc/la_oenb[7] soc/la_oenb[80] soc/la_oenb[81]
++ soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84] soc/la_oenb[85] soc/la_oenb[86]
++ soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89] soc/la_oenb[8] soc/la_oenb[90] soc/la_oenb[91]
++ soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94] soc/la_oenb[95] soc/la_oenb[96]
++ soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99] soc/la_oenb[9] soc/la_output[0]
++ soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103] soc/la_output[104]
++ soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108] soc/la_output[109]
++ soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112] soc/la_output[113]
++ soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117] soc/la_output[118]
++ soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121] soc/la_output[122]
++ soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126] soc/la_output[127]
++ soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15] soc/la_output[16]
++ soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1] soc/la_output[20]
++ soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24] soc/la_output[25]
++ soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29] soc/la_output[2]
++ soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33] soc/la_output[34]
++ soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38] soc/la_output[39]
++ soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42] soc/la_output[43]
++ soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47] soc/la_output[48]
++ soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51] soc/la_output[52]
++ soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56] soc/la_output[57]
++ soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60] soc/la_output[61]
++ soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65] soc/la_output[66]
++ soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6] soc/la_output[70]
++ soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74] soc/la_output[75]
++ soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79] soc/la_output[7]
++ soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83] soc/la_output[84]
++ soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88] soc/la_output[89]
++ soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92] soc/la_output[93]
++ soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97] soc/la_output[98]
++ soc/la_output[99] soc/la_output[9] soc/mask_rev[0] soc/mask_rev[10] soc/mask_rev[11]
++ soc/mask_rev[12] soc/mask_rev[13] soc/mask_rev[14] soc/mask_rev[15] soc/mask_rev[16]
++ soc/mask_rev[17] soc/mask_rev[18] soc/mask_rev[19] soc/mask_rev[1] soc/mask_rev[20]
++ soc/mask_rev[21] soc/mask_rev[22] soc/mask_rev[23] soc/mask_rev[24] soc/mask_rev[25]
++ soc/mask_rev[26] soc/mask_rev[27] soc/mask_rev[28] soc/mask_rev[29] soc/mask_rev[2]
++ soc/mask_rev[30] soc/mask_rev[31] soc/mask_rev[3] soc/mask_rev[4] soc/mask_rev[5]
++ soc/mask_rev[6] soc/mask_rev[7] soc/mask_rev[8] soc/mask_rev[9] soc/mgmt_addr[0]
++ soc/mgmt_addr[1] soc/mgmt_addr[2] soc/mgmt_addr[3] soc/mgmt_addr[4] soc/mgmt_addr[5]
++ soc/mgmt_addr[6] soc/mgmt_addr[7] soc/mgmt_addr_ro[0] soc/mgmt_addr_ro[1] soc/mgmt_addr_ro[2]
++ soc/mgmt_addr_ro[3] soc/mgmt_addr_ro[4] soc/mgmt_addr_ro[5] soc/mgmt_addr_ro[6]
++ soc/mgmt_addr_ro[7] soc/mgmt_ena[0] soc/mgmt_ena[1] soc/mgmt_ena_ro soc/mgmt_in_data[0]
++ soc/mgmt_in_data[10] soc/mgmt_in_data[11] soc/mgmt_in_data[12] soc/mgmt_in_data[13]
++ soc/mgmt_in_data[14] soc/mgmt_in_data[15] soc/mgmt_in_data[16] soc/mgmt_in_data[17]
++ soc/mgmt_in_data[18] soc/mgmt_in_data[19] soc/mgmt_in_data[1] soc/mgmt_in_data[20]
++ soc/mgmt_in_data[21] soc/mgmt_in_data[22] soc/mgmt_in_data[23] soc/mgmt_in_data[24]
++ soc/mgmt_in_data[25] soc/mgmt_in_data[26] soc/mgmt_in_data[27] soc/mgmt_in_data[28]
++ soc/mgmt_in_data[29] soc/mgmt_in_data[2] soc/mgmt_in_data[30] soc/mgmt_in_data[31]
++ soc/mgmt_in_data[32] soc/mgmt_in_data[33] soc/mgmt_in_data[34] soc/mgmt_in_data[35]
++ soc/mgmt_in_data[36] soc/mgmt_in_data[37] soc/mgmt_in_data[3] soc/mgmt_in_data[4]
++ soc/mgmt_in_data[5] soc/mgmt_in_data[6] soc/mgmt_in_data[7] soc/mgmt_in_data[8]
++ soc/mgmt_in_data[9] soc/mgmt_out_data[0] soc/mgmt_in_data[10] soc/mgmt_in_data[11]
++ soc/mgmt_in_data[12] soc/mgmt_in_data[13] soc/mgmt_in_data[14] soc/mgmt_in_data[15]
++ soc/mgmt_in_data[16] soc/mgmt_in_data[17] soc/mgmt_in_data[18] soc/mgmt_in_data[19]
++ soc/mgmt_out_data[1] soc/mgmt_in_data[20] soc/mgmt_in_data[21] soc/mgmt_in_data[22]
++ soc/mgmt_in_data[23] soc/mgmt_in_data[24] soc/mgmt_in_data[25] soc/mgmt_in_data[26]
++ soc/mgmt_in_data[27] soc/mgmt_in_data[28] soc/mgmt_in_data[29] soc/mgmt_in_data[2]
++ soc/mgmt_in_data[30] soc/mgmt_in_data[31] soc/mgmt_in_data[32] soc/mgmt_in_data[33]
++ soc/mgmt_in_data[34] soc/mgmt_in_data[35] soc/mgmt_out_data[36] soc/mgmt_out_data[37]
++ soc/mgmt_in_data[3] soc/mgmt_in_data[4] soc/mgmt_in_data[5] soc/mgmt_in_data[6]
++ soc/mgmt_in_data[7] soc/mgmt_in_data[8] soc/mgmt_in_data[9] soc/mgmt_rdata[0] soc/mgmt_rdata[10]
++ soc/mgmt_rdata[11] soc/mgmt_rdata[12] soc/mgmt_rdata[13] soc/mgmt_rdata[14] soc/mgmt_rdata[15]
++ soc/mgmt_rdata[16] soc/mgmt_rdata[17] soc/mgmt_rdata[18] soc/mgmt_rdata[19] soc/mgmt_rdata[1]
++ soc/mgmt_rdata[20] soc/mgmt_rdata[21] soc/mgmt_rdata[22] soc/mgmt_rdata[23] soc/mgmt_rdata[24]
++ soc/mgmt_rdata[25] soc/mgmt_rdata[26] soc/mgmt_rdata[27] soc/mgmt_rdata[28] soc/mgmt_rdata[29]
++ soc/mgmt_rdata[2] soc/mgmt_rdata[30] soc/mgmt_rdata[31] soc/mgmt_rdata[32] soc/mgmt_rdata[33]
++ soc/mgmt_rdata[34] soc/mgmt_rdata[35] soc/mgmt_rdata[36] soc/mgmt_rdata[37] soc/mgmt_rdata[38]
++ soc/mgmt_rdata[39] soc/mgmt_rdata[3] soc/mgmt_rdata[40] soc/mgmt_rdata[41] soc/mgmt_rdata[42]
++ soc/mgmt_rdata[43] soc/mgmt_rdata[44] soc/mgmt_rdata[45] soc/mgmt_rdata[46] soc/mgmt_rdata[47]
++ soc/mgmt_rdata[48] soc/mgmt_rdata[49] soc/mgmt_rdata[4] soc/mgmt_rdata[50] soc/mgmt_rdata[51]
++ soc/mgmt_rdata[52] soc/mgmt_rdata[53] soc/mgmt_rdata[54] soc/mgmt_rdata[55] soc/mgmt_rdata[56]
++ soc/mgmt_rdata[57] soc/mgmt_rdata[58] soc/mgmt_rdata[59] soc/mgmt_rdata[5] soc/mgmt_rdata[60]
++ soc/mgmt_rdata[61] soc/mgmt_rdata[62] soc/mgmt_rdata[63] soc/mgmt_rdata[6] soc/mgmt_rdata[7]
++ soc/mgmt_rdata[8] soc/mgmt_rdata[9] soc/mgmt_rdata_ro[0] soc/mgmt_rdata_ro[10] soc/mgmt_rdata_ro[11]
++ soc/mgmt_rdata_ro[12] soc/mgmt_rdata_ro[13] soc/mgmt_rdata_ro[14] soc/mgmt_rdata_ro[15]
++ soc/mgmt_rdata_ro[16] soc/mgmt_rdata_ro[17] soc/mgmt_rdata_ro[18] soc/mgmt_rdata_ro[19]
++ soc/mgmt_rdata_ro[1] soc/mgmt_rdata_ro[20] soc/mgmt_rdata_ro[21] soc/mgmt_rdata_ro[22]
++ soc/mgmt_rdata_ro[23] soc/mgmt_rdata_ro[24] soc/mgmt_rdata_ro[25] soc/mgmt_rdata_ro[26]
++ soc/mgmt_rdata_ro[27] soc/mgmt_rdata_ro[28] soc/mgmt_rdata_ro[29] soc/mgmt_rdata_ro[2]
++ soc/mgmt_rdata_ro[30] soc/mgmt_rdata_ro[31] soc/mgmt_rdata_ro[3] soc/mgmt_rdata_ro[4]
++ soc/mgmt_rdata_ro[5] soc/mgmt_rdata_ro[6] soc/mgmt_rdata_ro[7] soc/mgmt_rdata_ro[8]
++ soc/mgmt_rdata_ro[9] soc/mgmt_wdata[0] soc/mgmt_wdata[10] soc/mgmt_wdata[11] soc/mgmt_wdata[12]
++ soc/mgmt_wdata[13] soc/mgmt_wdata[14] soc/mgmt_wdata[15] soc/mgmt_wdata[16] soc/mgmt_wdata[17]
++ soc/mgmt_wdata[18] soc/mgmt_wdata[19] soc/mgmt_wdata[1] soc/mgmt_wdata[20] soc/mgmt_wdata[21]
++ soc/mgmt_wdata[22] soc/mgmt_wdata[23] soc/mgmt_wdata[24] soc/mgmt_wdata[25] soc/mgmt_wdata[26]
++ soc/mgmt_wdata[27] soc/mgmt_wdata[28] soc/mgmt_wdata[29] soc/mgmt_wdata[2] soc/mgmt_wdata[30]
++ soc/mgmt_wdata[31] soc/mgmt_wdata[3] soc/mgmt_wdata[4] soc/mgmt_wdata[5] soc/mgmt_wdata[6]
++ soc/mgmt_wdata[7] soc/mgmt_wdata[8] soc/mgmt_wdata[9] soc/mgmt_wen[0] soc/mgmt_wen[1]
++ soc/mgmt_wen_mask[0] soc/mgmt_wen_mask[1] soc/mgmt_wen_mask[2] soc/mgmt_wen_mask[3]
++ soc/mgmt_wen_mask[4] soc/mgmt_wen_mask[5] soc/mgmt_wen_mask[6] soc/mgmt_wen_mask[7]
++ soc/mprj2_vcc_pwrgood soc/mprj2_vdd_pwrgood soc/mprj_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10]
++ soc/mprj_adr_o[11] soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15]
++ soc/mprj_adr_o[16] soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1]
++ soc/mprj_adr_o[20] soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24]
++ soc/mprj_adr_o[25] soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29]
++ soc/mprj_adr_o[2] soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4]
++ soc/mprj_adr_o[5] soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9]
++ soc/mprj_cyc_o soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12]
++ soc/mprj_dat_i[13] soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17]
++ soc/mprj_dat_i[18] soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21]
++ soc/mprj_dat_i[22] soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26]
++ soc/mprj_dat_i[27] soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30]
++ soc/mprj_dat_i[31] soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6]
++ soc/mprj_dat_i[7] soc/mprj_dat_i[8] soc/mprj_dat_i[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ soc/mprj_io_loader_clock soc/mprj_io_loader_data_1 soc/mprj_io_loader_data_2 soc/mprj_io_loader_resetn
++ soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] soc/mprj_stb_o
++ soc/mprj_vcc_pwrgood soc/mprj_vdd_pwrgood soc/mprj_we_o soc/porb pwr_ctrl_out[0]
++ pwr_ctrl_out[1] pwr_ctrl_out[2] pwr_ctrl_out[3] soc/resetb soc/sdo_out soc/sdo_outenb
++ soc/user_clk soc/user_irq[0] soc/user_irq[1] soc/user_irq[2] soc/user_irq_ena[0]
++ soc/user_irq_ena[1] soc/user_irq_ena[2] vccd_core vssd_core mgmt_core
+Xgpio_control_in_1\[14\] soc/mgmt_in_data[16] gpio_control_in_1\[14\]/one soc/mgmt_in_data[16]
++ gpio_control_in_1\[14\]/one padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16]
++ padframe/mprj_io_analog_sel[16] padframe/mprj_io_dm[48] padframe/mprj_io_dm[49]
++ padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16] padframe/mprj_io_ib_mode_sel[16]
++ padframe/mprj_io_in[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_out[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16] gpio_control_in_2\[16\]/resetn
++ gpio_control_in_1\[15\]/resetn gpio_control_in_2\[16\]/serial_clock gpio_control_in_1\[15\]/serial_clock
++ gpio_control_in_1\[14\]/serial_data_in gpio_control_in_1\[15\]/serial_data_in mprj/io_in[16]
++ mprj/io_oeb[16] mprj/io_out[16] gpio_control_in_1\[14\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[9\] soc/mgmt_in_data[28] gpio_control_in_2\[9\]/one soc/mgmt_in_data[28]
++ gpio_control_in_2\[9\]/one padframe/mprj_io_analog_en[28] padframe/mprj_io_analog_pol[28]
++ padframe/mprj_io_analog_sel[28] padframe/mprj_io_dm[84] padframe/mprj_io_dm[85]
++ padframe/mprj_io_dm[86] padframe/mprj_io_holdover[28] padframe/mprj_io_ib_mode_sel[28]
++ padframe/mprj_io_in[28] padframe/mprj_io_inp_dis[28] padframe/mprj_io_out[28] padframe/mprj_io_oeb[28]
++ padframe/mprj_io_slow_sel[28] padframe/mprj_io_vtrip_sel[28] gpio_control_in_2\[9\]/resetn
++ gpio_control_in_1\[8\]/resetn gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[8\]/serial_clock
++ gpio_control_in_2\[9\]/serial_data_in gpio_control_in_2\[8\]/serial_data_in mprj/io_in[28]
++ mprj/io_oeb[28] mprj/io_out[28] gpio_control_in_2\[9\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xuser_id_textblock_0 VSUBS user_id_textblock
+Xgpio_control_in_1\[4\] soc/mgmt_in_data[6] gpio_control_in_1\[4\]/one soc/mgmt_in_data[6]
++ gpio_control_in_1\[4\]/one padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6]
++ padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20]
++ padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_in[6]
++ padframe/mprj_io_inp_dis[6] padframe/mprj_io_out[6] padframe/mprj_io_oeb[6] padframe/mprj_io_slow_sel[6]
++ padframe/mprj_io_vtrip_sel[6] gpio_control_in_2\[6\]/resetn gpio_control_in_2\[7\]/resetn
++ gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[7\]/serial_clock gpio_control_in_1\[4\]/serial_data_in
++ gpio_control_in_1\[5\]/serial_data_in mprj/io_in[6] mprj/io_oeb[6] mprj/io_out[6]
++ gpio_control_in_1\[4\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xpor vddio_core vccd_core vssio_core por/porb_h por/por_l soc/porb simple_por
+Xgpio_control_in_2\[12\] soc/mgmt_in_data[31] gpio_control_in_2\[12\]/one soc/mgmt_in_data[31]
++ gpio_control_in_2\[12\]/one padframe/mprj_io_analog_en[31] padframe/mprj_io_analog_pol[31]
++ padframe/mprj_io_analog_sel[31] padframe/mprj_io_dm[93] padframe/mprj_io_dm[94]
++ padframe/mprj_io_dm[95] padframe/mprj_io_holdover[31] padframe/mprj_io_ib_mode_sel[31]
++ padframe/mprj_io_in[31] padframe/mprj_io_inp_dis[31] padframe/mprj_io_out[31] padframe/mprj_io_oeb[31]
++ padframe/mprj_io_slow_sel[31] padframe/mprj_io_vtrip_sel[31] gpio_control_in_2\[12\]/resetn
++ gpio_control_in_2\[13\]/resetn gpio_control_in_2\[12\]/serial_clock gpio_control_in_2\[13\]/serial_clock
++ gpio_control_in_2\[12\]/serial_data_in gpio_control_in_2\[11\]/serial_data_in mprj/io_in[31]
++ mprj/io_oeb[31] mprj/io_out[31] gpio_control_in_2\[12\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[12\] soc/mgmt_in_data[14] gpio_control_in_1\[12\]/one soc/mgmt_in_data[14]
++ gpio_control_in_1\[12\]/one padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14]
++ padframe/mprj_io_analog_sel[14] padframe/mprj_io_dm[42] padframe/mprj_io_dm[43]
++ padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14] padframe/mprj_io_ib_mode_sel[14]
++ padframe/mprj_io_in[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_out[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14] gpio_control_in_2\[14\]/resetn
++ gpio_control_in_2\[15\]/resetn gpio_control_in_2\[14\]/serial_clock gpio_control_in_2\[15\]/serial_clock
++ gpio_control_in_1\[12\]/serial_data_in gpio_control_in_1\[13\]/serial_data_in mprj/io_in[14]
++ mprj/io_oeb[14] mprj/io_out[14] gpio_control_in_1\[12\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[7\] soc/mgmt_in_data[26] gpio_control_in_2\[7\]/one soc/mgmt_in_data[26]
++ gpio_control_in_2\[7\]/one padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26]
++ padframe/mprj_io_analog_sel[26] padframe/mprj_io_dm[78] padframe/mprj_io_dm[79]
++ padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26] padframe/mprj_io_ib_mode_sel[26]
++ padframe/mprj_io_in[26] padframe/mprj_io_inp_dis[26] padframe/mprj_io_out[26] padframe/mprj_io_oeb[26]
++ padframe/mprj_io_slow_sel[26] padframe/mprj_io_vtrip_sel[26] gpio_control_in_2\[7\]/resetn
++ gpio_control_in_2\[8\]/resetn gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[8\]/serial_clock
++ gpio_control_in_2\[7\]/serial_data_in gpio_control_in_2\[6\]/serial_data_in mprj/io_in[26]
++ mprj/io_oeb[26] mprj/io_out[26] gpio_control_in_2\[7\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[2\] soc/mgmt_in_data[4] gpio_control_in_1\[2\]/one soc/mgmt_in_data[4]
++ gpio_control_in_1\[2\]/one padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4]
++ padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14]
++ padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_in[4]
++ padframe/mprj_io_inp_dis[4] padframe/mprj_io_out[4] padframe/mprj_io_oeb[4] padframe/mprj_io_slow_sel[4]
++ padframe/mprj_io_vtrip_sel[4] gpio_control_in_2\[4\]/resetn gpio_control_in_2\[5\]/resetn
++ gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock gpio_control_in_1\[2\]/serial_data_in
++ gpio_control_in_1\[3\]/serial_data_in mprj/io_in[4] mprj/io_oeb[4] mprj/io_out[4]
++ gpio_control_in_1\[2\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[10\] soc/mgmt_in_data[29] gpio_control_in_2\[10\]/one soc/mgmt_in_data[29]
++ gpio_control_in_2\[10\]/one padframe/mprj_io_analog_en[29] padframe/mprj_io_analog_pol[29]
++ padframe/mprj_io_analog_sel[29] padframe/mprj_io_dm[87] padframe/mprj_io_dm[88]
++ padframe/mprj_io_dm[89] padframe/mprj_io_holdover[29] padframe/mprj_io_ib_mode_sel[29]
++ padframe/mprj_io_in[29] padframe/mprj_io_inp_dis[29] padframe/mprj_io_out[29] padframe/mprj_io_oeb[29]
++ padframe/mprj_io_slow_sel[29] padframe/mprj_io_vtrip_sel[29] gpio_control_in_1\[8\]/resetn
++ gpio_control_in_1\[9\]/resetn gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[9\]/serial_clock
++ gpio_control_in_2\[10\]/serial_data_in gpio_control_in_2\[9\]/serial_data_in mprj/io_in[29]
++ mprj/io_oeb[29] mprj/io_out[29] gpio_control_in_2\[10\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[5\] soc/mgmt_in_data[24] gpio_control_in_2\[5\]/one soc/mgmt_in_data[24]
++ gpio_control_in_2\[5\]/one padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24]
++ padframe/mprj_io_analog_sel[24] padframe/mprj_io_dm[72] padframe/mprj_io_dm[73]
++ padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24] padframe/mprj_io_ib_mode_sel[24]
++ padframe/mprj_io_in[24] padframe/mprj_io_inp_dis[24] padframe/mprj_io_out[24] padframe/mprj_io_oeb[24]
++ padframe/mprj_io_slow_sel[24] padframe/mprj_io_vtrip_sel[24] gpio_control_in_2\[5\]/resetn
++ gpio_control_in_2\[6\]/resetn gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[6\]/serial_clock
++ gpio_control_in_2\[5\]/serial_data_in gpio_control_in_2\[4\]/serial_data_in mprj/io_in[24]
++ mprj/io_oeb[24] mprj/io_out[24] gpio_control_in_2\[5\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[10\] soc/mgmt_in_data[12] gpio_control_in_1\[10\]/one soc/mgmt_in_data[12]
++ gpio_control_in_1\[10\]/one padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12]
++ padframe/mprj_io_analog_sel[12] padframe/mprj_io_dm[36] padframe/mprj_io_dm[37]
++ padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12] padframe/mprj_io_ib_mode_sel[12]
++ padframe/mprj_io_in[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_out[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12] gpio_control_in_2\[12\]/resetn
++ gpio_control_in_2\[13\]/resetn gpio_control_in_2\[12\]/serial_clock gpio_control_in_2\[13\]/serial_clock
++ gpio_control_in_1\[9\]/serial_data_out gpio_control_in_1\[11\]/serial_data_in mprj/io_in[12]
++ mprj/io_oeb[12] mprj/io_out[12] gpio_control_in_1\[10\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[0\] soc/mgmt_in_data[2] gpio_control_in_1\[0\]/one soc/mgmt_in_data[2]
++ gpio_control_in_1\[0\]/one padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2]
++ padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8]
++ padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_in[2]
++ padframe/mprj_io_inp_dis[2] padframe/mprj_io_out[2] padframe/mprj_io_oeb[2] padframe/mprj_io_slow_sel[2]
++ padframe/mprj_io_vtrip_sel[2] gpio_control_in_2\[2\]/resetn gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock gpio_control_in_1\[0\]/serial_data_in
++ gpio_control_in_1\[1\]/serial_data_in mprj/io_in[2] mprj/io_oeb[2] mprj/io_out[2]
++ gpio_control_in_1\[0\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xuser_id_value soc/mask_rev[0] soc/mask_rev[10] soc/mask_rev[11] soc/mask_rev[12]
++ soc/mask_rev[13] soc/mask_rev[14] soc/mask_rev[15] soc/mask_rev[16] soc/mask_rev[17]
++ soc/mask_rev[18] soc/mask_rev[19] soc/mask_rev[1] soc/mask_rev[20] soc/mask_rev[21]
++ soc/mask_rev[22] soc/mask_rev[23] soc/mask_rev[24] soc/mask_rev[25] soc/mask_rev[26]
++ soc/mask_rev[27] soc/mask_rev[28] soc/mask_rev[29] soc/mask_rev[2] soc/mask_rev[30]
++ soc/mask_rev[31] soc/mask_rev[3] soc/mask_rev[4] soc/mask_rev[5] soc/mask_rev[6]
++ soc/mask_rev[7] soc/mask_rev[8] soc/mask_rev[9] vccd_core vssd_core user_id_programming
+Xgpio_control_in_2\[3\] soc/mgmt_in_data[22] gpio_control_in_2\[3\]/one soc/mgmt_in_data[22]
++ gpio_control_in_2\[3\]/one padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22]
++ padframe/mprj_io_analog_sel[22] padframe/mprj_io_dm[66] padframe/mprj_io_dm[67]
++ padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22] padframe/mprj_io_ib_mode_sel[22]
++ padframe/mprj_io_in[22] padframe/mprj_io_inp_dis[22] padframe/mprj_io_out[22] padframe/mprj_io_oeb[22]
++ padframe/mprj_io_slow_sel[22] padframe/mprj_io_vtrip_sel[22] gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[4\]/resetn gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock
++ gpio_control_in_2\[3\]/serial_data_in gpio_control_in_2\[2\]/serial_data_in mprj/io_in[22]
++ mprj/io_oeb[22] mprj/io_out[22] gpio_control_in_2\[3\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_bidir_1\[0\] soc/mgmt_in_data[0] soc/jtag_outenb soc/jtag_out gpio_control_bidir_1\[0\]/one
++ padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0]
++ padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0]
++ padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_in[0] padframe/mprj_io_inp_dis[0]
++ padframe/mprj_io_out[0] padframe/mprj_io_oeb[0] padframe/mprj_io_slow_sel[0] padframe/mprj_io_vtrip_sel[0]
++ soc/mprj_io_loader_resetn gpio_control_in_2\[1\]/resetn soc/mprj_io_loader_clock
++ gpio_control_in_2\[1\]/serial_clock soc/mprj_io_loader_data_1 gpio_control_bidir_1\[1\]/serial_data_in
++ mprj/io_in[0] mprj/io_oeb[0] mprj/io_out[0] gpio_control_bidir_1\[0\]/zero vccd_core
++ vssd_core vccd1_core vssd1_core gpio_control_block
+Xopen_source_0 VSUBS open_source
+Xgpio_control_in_1\[9\] soc/mgmt_in_data[11] gpio_control_in_1\[9\]/one soc/mgmt_in_data[11]
++ gpio_control_in_1\[9\]/one padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11]
++ padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33] padframe/mprj_io_dm[34]
++ padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11] padframe/mprj_io_ib_mode_sel[11]
++ padframe/mprj_io_in[11] padframe/mprj_io_inp_dis[11] padframe/mprj_io_out[11] padframe/mprj_io_oeb[11]
++ padframe/mprj_io_slow_sel[11] padframe/mprj_io_vtrip_sel[11] gpio_control_in_1\[9\]/resetn
++ gpio_control_in_2\[12\]/resetn gpio_control_in_1\[9\]/serial_clock gpio_control_in_2\[12\]/serial_clock
++ gpio_control_in_1\[9\]/serial_data_in gpio_control_in_1\[9\]/serial_data_out mprj/io_in[11]
++ mprj/io_oeb[11] mprj/io_out[11] gpio_control_in_1\[9\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[1\] soc/mgmt_in_data[20] gpio_control_in_2\[1\]/one soc/mgmt_in_data[20]
++ gpio_control_in_2\[1\]/one padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20]
++ padframe/mprj_io_analog_sel[20] padframe/mprj_io_dm[60] padframe/mprj_io_dm[61]
++ padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20] padframe/mprj_io_ib_mode_sel[20]
++ padframe/mprj_io_in[20] padframe/mprj_io_inp_dis[20] padframe/mprj_io_out[20] padframe/mprj_io_oeb[20]
++ padframe/mprj_io_slow_sel[20] padframe/mprj_io_vtrip_sel[20] gpio_control_in_2\[1\]/resetn
++ gpio_control_in_2\[2\]/resetn gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[2\]/serial_clock
++ gpio_control_in_2\[1\]/serial_data_in gpio_control_in_2\[0\]/serial_data_in mprj/io_in[20]
++ mprj/io_oeb[20] mprj/io_out[20] gpio_control_in_2\[1\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[7\] soc/mgmt_in_data[9] gpio_control_in_1\[7\]/one soc/mgmt_in_data[9]
++ gpio_control_in_1\[7\]/one padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9]
++ padframe/mprj_io_analog_sel[9] padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29]
++ padframe/mprj_io_holdover[9] padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_in[9]
++ padframe/mprj_io_inp_dis[9] padframe/mprj_io_out[9] padframe/mprj_io_oeb[9] padframe/mprj_io_slow_sel[9]
++ padframe/mprj_io_vtrip_sel[9] gpio_control_in_2\[9\]/resetn gpio_control_in_1\[8\]/resetn
++ gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[7\]/serial_data_in
++ gpio_control_in_1\[8\]/serial_data_in mprj/io_in[9] mprj/io_oeb[9] mprj/io_out[9]
++ gpio_control_in_1\[7\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xmgmt_buffers soc/core_clk soc/user_clk soc/core_rstn mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ mprj/la_data_out[0] mprj/la_data_out[100] mprj/la_data_out[101] mprj/la_data_out[102]
++ mprj/la_data_out[103] mprj/la_data_out[104] mprj/la_data_out[105] mprj/la_data_out[106]
++ mprj/la_data_out[107] mprj/la_data_out[108] mprj/la_data_out[109] mprj/la_data_out[10]
++ mprj/la_data_out[110] mprj/la_data_out[111] mprj/la_data_out[112] mprj/la_data_out[113]
++ mprj/la_data_out[114] mprj/la_data_out[115] mprj/la_data_out[116] mprj/la_data_out[117]
++ mprj/la_data_out[118] mprj/la_data_out[119] mprj/la_data_out[11] mprj/la_data_out[120]
++ mprj/la_data_out[121] mprj/la_data_out[122] mprj/la_data_out[123] mprj/la_data_out[124]
++ mprj/la_data_out[125] mprj/la_data_out[126] mprj/la_data_out[127] mprj/la_data_out[12]
++ mprj/la_data_out[13] mprj/la_data_out[14] mprj/la_data_out[15] mprj/la_data_out[16]
++ mprj/la_data_out[17] mprj/la_data_out[18] mprj/la_data_out[19] mprj/la_data_out[1]
++ mprj/la_data_out[20] mprj/la_data_out[21] mprj/la_data_out[22] mprj/la_data_out[23]
++ mprj/la_data_out[24] mprj/la_data_out[25] mprj/la_data_out[26] mprj/la_data_out[27]
++ mprj/la_data_out[28] mprj/la_data_out[29] mprj/la_data_out[2] mprj/la_data_out[30]
++ mprj/la_data_out[31] mprj/la_data_out[32] mprj/la_data_out[33] mprj/la_data_out[34]
++ mprj/la_data_out[35] mprj/la_data_out[36] mprj/la_data_out[37] mprj/la_data_out[38]
++ mprj/la_data_out[39] mprj/la_data_out[3] mprj/la_data_out[40] mprj/la_data_out[41]
++ mprj/la_data_out[42] mprj/la_data_out[43] mprj/la_data_out[44] mprj/la_data_out[45]
++ mprj/la_data_out[46] mprj/la_data_out[47] mprj/la_data_out[48] mprj/la_data_out[49]
++ mprj/la_data_out[4] mprj/la_data_out[50] mprj/la_data_out[51] mprj/la_data_out[52]
++ mprj/la_data_out[53] mprj/la_data_out[54] mprj/la_data_out[55] mprj/la_data_out[56]
++ mprj/la_data_out[57] mprj/la_data_out[58] mprj/la_data_out[59] mprj/la_data_out[5]
++ mprj/la_data_out[60] mprj/la_data_out[61] mprj/la_data_out[62] mprj/la_data_out[63]
++ mprj/la_data_out[64] mprj/la_data_out[65] mprj/la_data_out[66] mprj/la_data_out[67]
++ mprj/la_data_out[68] mprj/la_data_out[69] mprj/la_data_out[6] mprj/la_data_out[70]
++ mprj/la_data_out[71] mprj/la_data_out[72] mprj/la_data_out[73] mprj/la_data_out[74]
++ mprj/la_data_out[75] mprj/la_data_out[76] mprj/la_data_out[77] mprj/la_data_out[78]
++ mprj/la_data_out[79] mprj/la_data_out[7] mprj/la_data_out[80] mprj/la_data_out[81]
++ mprj/la_data_out[82] mprj/la_data_out[83] mprj/la_data_out[84] mprj/la_data_out[85]
++ mprj/la_data_out[86] mprj/la_data_out[87] mprj/la_data_out[88] mprj/la_data_out[89]
++ mprj/la_data_out[8] mprj/la_data_out[90] mprj/la_data_out[91] mprj/la_data_out[92]
++ mprj/la_data_out[93] mprj/la_data_out[94] mprj/la_data_out[95] mprj/la_data_out[96]
++ mprj/la_data_out[97] mprj/la_data_out[98] mprj/la_data_out[99] mprj/la_data_out[9]
++ soc/la_output[0] soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103]
++ soc/la_output[104] soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108]
++ soc/la_output[109] soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112]
++ soc/la_output[113] soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117]
++ soc/la_output[118] soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121]
++ soc/la_output[122] soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126]
++ soc/la_output[127] soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15]
++ soc/la_output[16] soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1]
++ soc/la_output[20] soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24]
++ soc/la_output[25] soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29]
++ soc/la_output[2] soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33]
++ soc/la_output[34] soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38]
++ soc/la_output[39] soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42]
++ soc/la_output[43] soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47]
++ soc/la_output[48] soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51]
++ soc/la_output[52] soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56]
++ soc/la_output[57] soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60]
++ soc/la_output[61] soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65]
++ soc/la_output[66] soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6]
++ soc/la_output[70] soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74]
++ soc/la_output[75] soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79]
++ soc/la_output[7] soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83]
++ soc/la_output[84] soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88]
++ soc/la_output[89] soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92]
++ soc/la_output[93] soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97]
++ soc/la_output[98] soc/la_output[99] soc/la_output[9] soc/la_iena[0] soc/la_iena[100]
++ soc/la_iena[101] soc/la_iena[102] soc/la_iena[103] soc/la_iena[104] soc/la_iena[105]
++ soc/la_iena[106] soc/la_iena[107] soc/la_iena[108] soc/la_iena[109] soc/la_iena[10]
++ soc/la_iena[110] soc/la_iena[111] soc/la_iena[112] soc/la_iena[113] soc/la_iena[114]
++ soc/la_iena[115] soc/la_iena[116] soc/la_iena[117] soc/la_iena[118] soc/la_iena[119]
++ soc/la_iena[11] soc/la_iena[120] soc/la_iena[121] soc/la_iena[122] soc/la_iena[123]
++ soc/la_iena[124] soc/la_iena[125] soc/la_iena[126] soc/la_iena[127] soc/la_iena[12]
++ soc/la_iena[13] soc/la_iena[14] soc/la_iena[15] soc/la_iena[16] soc/la_iena[17]
++ soc/la_iena[18] soc/la_iena[19] soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22]
++ soc/la_iena[23] soc/la_iena[24] soc/la_iena[25] soc/la_iena[26] soc/la_iena[27]
++ soc/la_iena[28] soc/la_iena[29] soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32]
++ soc/la_iena[33] soc/la_iena[34] soc/la_iena[35] soc/la_iena[36] soc/la_iena[37]
++ soc/la_iena[38] soc/la_iena[39] soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42]
++ soc/la_iena[43] soc/la_iena[44] soc/la_iena[45] soc/la_iena[46] soc/la_iena[47]
++ soc/la_iena[48] soc/la_iena[49] soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52]
++ soc/la_iena[53] soc/la_iena[54] soc/la_iena[55] soc/la_iena[56] soc/la_iena[57]
++ soc/la_iena[58] soc/la_iena[59] soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62]
++ soc/la_iena[63] soc/la_iena[64] soc/la_iena[65] soc/la_iena[66] soc/la_iena[67]
++ soc/la_iena[68] soc/la_iena[69] soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72]
++ soc/la_iena[73] soc/la_iena[74] soc/la_iena[75] soc/la_iena[76] soc/la_iena[77]
++ soc/la_iena[78] soc/la_iena[79] soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82]
++ soc/la_iena[83] soc/la_iena[84] soc/la_iena[85] soc/la_iena[86] soc/la_iena[87]
++ soc/la_iena[88] soc/la_iena[89] soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92]
++ soc/la_iena[93] soc/la_iena[94] soc/la_iena[95] soc/la_iena[96] soc/la_iena[97]
++ soc/la_iena[98] soc/la_iena[99] soc/la_iena[9] mprj/la_oenb[0] mprj/la_oenb[100]
++ mprj/la_oenb[101] mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105]
++ mprj/la_oenb[106] mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10]
++ mprj/la_oenb[110] mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114]
++ mprj/la_oenb[115] mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119]
++ mprj/la_oenb[11] mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123]
++ mprj/la_oenb[124] mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12]
++ mprj/la_oenb[13] mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17]
++ mprj/la_oenb[18] mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21]
++ mprj/la_oenb[22] mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26]
++ mprj/la_oenb[27] mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30]
++ mprj/la_oenb[31] mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35]
++ mprj/la_oenb[36] mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3]
++ mprj/la_oenb[40] mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44]
++ mprj/la_oenb[45] mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49]
++ mprj/la_oenb[4] mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53]
++ mprj/la_oenb[54] mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58]
++ mprj/la_oenb[59] mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62]
++ mprj/la_oenb[63] mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67]
++ mprj/la_oenb[68] mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71]
++ mprj/la_oenb[72] mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76]
++ mprj/la_oenb[77] mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80]
++ mprj/la_oenb[81] mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85]
++ mprj/la_oenb[86] mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8]
++ mprj/la_oenb[90] mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94]
++ mprj/la_oenb[95] mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99]
++ mprj/la_oenb[9] soc/la_oenb[0] soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102]
++ soc/la_oenb[103] soc/la_oenb[104] soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107]
++ soc/la_oenb[108] soc/la_oenb[109] soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111]
++ soc/la_oenb[112] soc/la_oenb[113] soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116]
++ soc/la_oenb[117] soc/la_oenb[118] soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120]
++ soc/la_oenb[121] soc/la_oenb[122] soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125]
++ soc/la_oenb[126] soc/la_oenb[127] soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14]
++ soc/la_oenb[15] soc/la_oenb[16] soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19]
++ soc/la_oenb[1] soc/la_oenb[20] soc/la_oenb[21] soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24]
++ soc/la_oenb[25] soc/la_oenb[26] soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29]
++ soc/la_oenb[2] soc/la_oenb[30] soc/la_oenb[31] soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34]
++ soc/la_oenb[35] soc/la_oenb[36] soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39]
++ soc/la_oenb[3] soc/la_oenb[40] soc/la_oenb[41] soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44]
++ soc/la_oenb[45] soc/la_oenb[46] soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49]
++ soc/la_oenb[4] soc/la_oenb[50] soc/la_oenb[51] soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54]
++ soc/la_oenb[55] soc/la_oenb[56] soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59]
++ soc/la_oenb[5] soc/la_oenb[60] soc/la_oenb[61] soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64]
++ soc/la_oenb[65] soc/la_oenb[66] soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69]
++ soc/la_oenb[6] soc/la_oenb[70] soc/la_oenb[71] soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74]
++ soc/la_oenb[75] soc/la_oenb[76] soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79]
++ soc/la_oenb[7] soc/la_oenb[80] soc/la_oenb[81] soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84]
++ soc/la_oenb[85] soc/la_oenb[86] soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89]
++ soc/la_oenb[8] soc/la_oenb[90] soc/la_oenb[91] soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94]
++ soc/la_oenb[95] soc/la_oenb[96] soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99]
++ soc/la_oenb[9] soc/mprj_adr_o[0] soc/mprj_adr_o[10] soc/mprj_adr_o[11] soc/mprj_adr_o[12]
++ soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15] soc/mprj_adr_o[16] soc/mprj_adr_o[17]
++ soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1] soc/mprj_adr_o[20] soc/mprj_adr_o[21]
++ soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24] soc/mprj_adr_o[25] soc/mprj_adr_o[26]
++ soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29] soc/mprj_adr_o[2] soc/mprj_adr_o[30]
++ soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4] soc/mprj_adr_o[5] soc/mprj_adr_o[6]
++ soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9] mprj/wbs_adr_i[0] mprj/wbs_adr_i[10]
++ mprj/wbs_adr_i[11] mprj/wbs_adr_i[12] mprj/wbs_adr_i[13] mprj/wbs_adr_i[14] mprj/wbs_adr_i[15]
++ mprj/wbs_adr_i[16] mprj/wbs_adr_i[17] mprj/wbs_adr_i[18] mprj/wbs_adr_i[19] mprj/wbs_adr_i[1]
++ mprj/wbs_adr_i[20] mprj/wbs_adr_i[21] mprj/wbs_adr_i[22] mprj/wbs_adr_i[23] mprj/wbs_adr_i[24]
++ mprj/wbs_adr_i[25] mprj/wbs_adr_i[26] mprj/wbs_adr_i[27] mprj/wbs_adr_i[28] mprj/wbs_adr_i[29]
++ mprj/wbs_adr_i[2] mprj/wbs_adr_i[30] mprj/wbs_adr_i[31] mprj/wbs_adr_i[3] mprj/wbs_adr_i[4]
++ mprj/wbs_adr_i[5] mprj/wbs_adr_i[6] mprj/wbs_adr_i[7] mprj/wbs_adr_i[8] mprj/wbs_adr_i[9]
++ soc/mprj_cyc_o mprj/wbs_cyc_i soc/mprj_dat_o[0] soc/mprj_dat_o[10] soc/mprj_dat_o[11]
++ soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15] soc/mprj_dat_o[16]
++ soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1] soc/mprj_dat_o[20]
++ soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24] soc/mprj_dat_o[25]
++ soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29] soc/mprj_dat_o[2]
++ soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4] soc/mprj_dat_o[5]
++ soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9] mprj/wbs_dat_i[0]
++ mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13] mprj/wbs_dat_i[14]
++ mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18] mprj/wbs_dat_i[19]
++ mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22] mprj/wbs_dat_i[23]
++ mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27] mprj/wbs_dat_i[28]
++ mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31] mprj/wbs_dat_i[3]
++ mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7] mprj/wbs_dat_i[8]
++ mprj/wbs_dat_i[9] soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3]
++ mprj/wbs_sel_i[0] mprj/wbs_sel_i[1] mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] soc/mprj_stb_o
++ mprj/wbs_stb_i soc/mprj_we_o mprj/wbs_we_i soc/mprj_vcc_pwrgood soc/mprj_vdd_pwrgood
++ soc/mprj2_vcc_pwrgood soc/mprj2_vdd_pwrgood mprj/wb_clk_i mprj/user_clock2 soc/user_irq[0]
++ soc/user_irq[1] soc/user_irq[2] mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2]
++ soc/user_irq_ena[0] soc/user_irq_ena[1] soc/user_irq_ena[2] mprj/wb_rst_i vccd_core
++ vssd_core vccd1_core vssd1_core vccd2_core vssd2_core vdda1_core vssa1_core vdda2_core
++ vssa2_core mgmt_protect
+Xrstb_level rstb_level/A soc/resetb vddio_core vssio_core vccd_core vssd_core sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Xgpio_control_in_2\[15\] soc/mgmt_in_data[34] gpio_control_in_2\[15\]/one soc/mgmt_in_data[34]
++ gpio_control_in_2\[15\]/one padframe/mprj_io_analog_en[34] padframe/mprj_io_analog_pol[34]
++ padframe/mprj_io_analog_sel[34] padframe/mprj_io_dm[102] padframe/mprj_io_dm[103]
++ padframe/mprj_io_dm[104] padframe/mprj_io_holdover[34] padframe/mprj_io_ib_mode_sel[34]
++ padframe/mprj_io_in[34] padframe/mprj_io_inp_dis[34] padframe/mprj_io_out[34] padframe/mprj_io_oeb[34]
++ padframe/mprj_io_slow_sel[34] padframe/mprj_io_vtrip_sel[34] gpio_control_in_2\[15\]/resetn
++ gpio_control_in_2\[16\]/resetn gpio_control_in_2\[15\]/serial_clock gpio_control_in_2\[16\]/serial_clock
++ gpio_control_in_2\[15\]/serial_data_in gpio_control_in_2\[14\]/serial_data_in mprj/io_in[34]
++ mprj/io_oeb[34] mprj/io_out[34] gpio_control_in_2\[15\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_bidir_2\[1\] soc/mgmt_in_data[37] soc/flash_io3_oeb soc/mgmt_out_data[37]
++ gpio_control_bidir_2\[1\]/one padframe/mprj_io_analog_en[37] padframe/mprj_io_analog_pol[37]
++ padframe/mprj_io_analog_sel[37] padframe/mprj_io_dm[111] padframe/mprj_io_dm[112]
++ padframe/mprj_io_dm[113] padframe/mprj_io_holdover[37] padframe/mprj_io_ib_mode_sel[37]
++ padframe/mprj_io_in[37] padframe/mprj_io_inp_dis[37] padframe/mprj_io_out[37] padframe/mprj_io_oeb[37]
++ padframe/mprj_io_slow_sel[37] padframe/mprj_io_vtrip_sel[37] gpio_control_in_1\[16\]/resetn
++ gpio_control_in_1\[16\]/resetn_out gpio_control_in_1\[16\]/serial_clock gpio_control_in_1\[16\]/serial_clock_out
++ soc/mprj_io_loader_data_2 gpio_control_bidir_2\[0\]/serial_data_in mprj/io_in[37]
++ mprj/io_oeb[37] mprj/io_out[37] gpio_control_bidir_2\[1\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[15\] soc/mgmt_in_data[17] gpio_control_in_1\[15\]/one soc/mgmt_in_data[17]
++ gpio_control_in_1\[15\]/one padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17]
++ padframe/mprj_io_analog_sel[17] padframe/mprj_io_dm[51] padframe/mprj_io_dm[52]
++ padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17] padframe/mprj_io_ib_mode_sel[17]
++ padframe/mprj_io_in[17] padframe/mprj_io_inp_dis[17] padframe/mprj_io_out[17] padframe/mprj_io_oeb[17]
++ padframe/mprj_io_slow_sel[17] padframe/mprj_io_vtrip_sel[17] gpio_control_in_1\[15\]/resetn
++ gpio_control_in_1\[16\]/resetn gpio_control_in_1\[15\]/serial_clock gpio_control_in_1\[16\]/serial_clock
++ gpio_control_in_1\[15\]/serial_data_in gpio_control_in_1\[16\]/serial_data_in mprj/io_in[17]
++ mprj/io_oeb[17] mprj/io_out[17] gpio_control_in_1\[15\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[5\] soc/mgmt_in_data[7] gpio_control_in_1\[5\]/one soc/mgmt_in_data[7]
++ gpio_control_in_1\[5\]/one padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7]
++ padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23]
++ padframe/mprj_io_holdover[7] padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_in[7]
++ padframe/mprj_io_inp_dis[7] padframe/mprj_io_out[7] padframe/mprj_io_oeb[7] padframe/mprj_io_slow_sel[7]
++ padframe/mprj_io_vtrip_sel[7] gpio_control_in_2\[7\]/resetn gpio_control_in_2\[8\]/resetn
++ gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[8\]/serial_clock gpio_control_in_1\[5\]/serial_data_in
++ gpio_control_in_1\[6\]/serial_data_in mprj/io_in[7] mprj/io_oeb[7] mprj/io_out[7]
++ gpio_control_in_1\[5\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[13\] soc/mgmt_in_data[32] gpio_control_in_2\[13\]/one soc/mgmt_in_data[32]
++ gpio_control_in_2\[13\]/one padframe/mprj_io_analog_en[32] padframe/mprj_io_analog_pol[32]
++ padframe/mprj_io_analog_sel[32] padframe/mprj_io_dm[96] padframe/mprj_io_dm[97]
++ padframe/mprj_io_dm[98] padframe/mprj_io_holdover[32] padframe/mprj_io_ib_mode_sel[32]
++ padframe/mprj_io_in[32] padframe/mprj_io_inp_dis[32] padframe/mprj_io_out[32] padframe/mprj_io_oeb[32]
++ padframe/mprj_io_slow_sel[32] padframe/mprj_io_vtrip_sel[32] gpio_control_in_2\[13\]/resetn
++ gpio_control_in_2\[14\]/resetn gpio_control_in_2\[13\]/serial_clock gpio_control_in_2\[14\]/serial_clock
++ gpio_control_in_2\[13\]/serial_data_in gpio_control_in_2\[12\]/serial_data_in mprj/io_in[32]
++ mprj/io_oeb[32] mprj/io_out[32] gpio_control_in_2\[13\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[8\] soc/mgmt_in_data[27] gpio_control_in_2\[8\]/one soc/mgmt_in_data[27]
++ gpio_control_in_2\[8\]/one padframe/mprj_io_analog_en[27] padframe/mprj_io_analog_pol[27]
++ padframe/mprj_io_analog_sel[27] padframe/mprj_io_dm[81] padframe/mprj_io_dm[82]
++ padframe/mprj_io_dm[83] padframe/mprj_io_holdover[27] padframe/mprj_io_ib_mode_sel[27]
++ padframe/mprj_io_in[27] padframe/mprj_io_inp_dis[27] padframe/mprj_io_out[27] padframe/mprj_io_oeb[27]
++ padframe/mprj_io_slow_sel[27] padframe/mprj_io_vtrip_sel[27] gpio_control_in_2\[8\]/resetn
++ gpio_control_in_2\[9\]/resetn gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[9\]/serial_clock
++ gpio_control_in_2\[8\]/serial_data_in gpio_control_in_2\[7\]/serial_data_in mprj/io_in[27]
++ mprj/io_oeb[27] mprj/io_out[27] gpio_control_in_2\[8\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[13\] soc/mgmt_in_data[15] gpio_control_in_1\[13\]/one soc/mgmt_in_data[15]
++ gpio_control_in_1\[13\]/one padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15]
++ padframe/mprj_io_analog_sel[15] padframe/mprj_io_dm[45] padframe/mprj_io_dm[46]
++ padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15] padframe/mprj_io_ib_mode_sel[15]
++ padframe/mprj_io_in[15] padframe/mprj_io_inp_dis[15] padframe/mprj_io_out[15] padframe/mprj_io_oeb[15]
++ padframe/mprj_io_slow_sel[15] padframe/mprj_io_vtrip_sel[15] gpio_control_in_2\[15\]/resetn
++ gpio_control_in_2\[16\]/resetn gpio_control_in_2\[15\]/serial_clock gpio_control_in_2\[16\]/serial_clock
++ gpio_control_in_1\[13\]/serial_data_in gpio_control_in_1\[14\]/serial_data_in mprj/io_in[15]
++ mprj/io_oeb[15] mprj/io_out[15] gpio_control_in_1\[13\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[3\] soc/mgmt_in_data[5] gpio_control_in_1\[3\]/one soc/mgmt_in_data[5]
++ gpio_control_in_1\[3\]/one padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5]
++ padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17]
++ padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_in[5]
++ padframe/mprj_io_inp_dis[5] padframe/mprj_io_out[5] padframe/mprj_io_oeb[5] padframe/mprj_io_slow_sel[5]
++ padframe/mprj_io_vtrip_sel[5] gpio_control_in_2\[5\]/resetn gpio_control_in_2\[6\]/resetn
++ gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[6\]/serial_clock gpio_control_in_1\[3\]/serial_data_in
++ gpio_control_in_1\[4\]/serial_data_in mprj/io_in[5] mprj/io_oeb[5] mprj/io_out[5]
++ gpio_control_in_1\[3\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[11\] soc/mgmt_in_data[30] gpio_control_in_2\[11\]/one soc/mgmt_in_data[30]
++ gpio_control_in_2\[11\]/one padframe/mprj_io_analog_en[30] padframe/mprj_io_analog_pol[30]
++ padframe/mprj_io_analog_sel[30] padframe/mprj_io_dm[90] padframe/mprj_io_dm[91]
++ padframe/mprj_io_dm[92] padframe/mprj_io_holdover[30] padframe/mprj_io_ib_mode_sel[30]
++ padframe/mprj_io_in[30] padframe/mprj_io_inp_dis[30] padframe/mprj_io_out[30] padframe/mprj_io_oeb[30]
++ padframe/mprj_io_slow_sel[30] padframe/mprj_io_vtrip_sel[30] gpio_control_in_1\[9\]/resetn
++ gpio_control_in_2\[12\]/resetn gpio_control_in_1\[9\]/serial_clock gpio_control_in_2\[12\]/serial_clock
++ gpio_control_in_2\[11\]/serial_data_in gpio_control_in_2\[10\]/serial_data_in mprj/io_in[30]
++ mprj/io_oeb[30] mprj/io_out[30] gpio_control_in_2\[11\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_2\[6\] soc/mgmt_in_data[25] gpio_control_in_2\[6\]/one soc/mgmt_in_data[25]
++ gpio_control_in_2\[6\]/one padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25]
++ padframe/mprj_io_analog_sel[25] padframe/mprj_io_dm[75] padframe/mprj_io_dm[76]
++ padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25] padframe/mprj_io_ib_mode_sel[25]
++ padframe/mprj_io_in[25] padframe/mprj_io_inp_dis[25] padframe/mprj_io_out[25] padframe/mprj_io_oeb[25]
++ padframe/mprj_io_slow_sel[25] padframe/mprj_io_vtrip_sel[25] gpio_control_in_2\[6\]/resetn
++ gpio_control_in_2\[7\]/resetn gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[7\]/serial_clock
++ gpio_control_in_2\[6\]/serial_data_in gpio_control_in_2\[5\]/serial_data_in mprj/io_in[25]
++ mprj/io_oeb[25] mprj/io_out[25] gpio_control_in_2\[6\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[11\] soc/mgmt_in_data[13] gpio_control_in_1\[11\]/one soc/mgmt_in_data[13]
++ gpio_control_in_1\[11\]/one padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13]
++ padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39] padframe/mprj_io_dm[40]
++ padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13] padframe/mprj_io_ib_mode_sel[13]
++ padframe/mprj_io_in[13] padframe/mprj_io_inp_dis[13] padframe/mprj_io_out[13] padframe/mprj_io_oeb[13]
++ padframe/mprj_io_slow_sel[13] padframe/mprj_io_vtrip_sel[13] gpio_control_in_2\[13\]/resetn
++ gpio_control_in_2\[14\]/resetn gpio_control_in_2\[13\]/serial_clock gpio_control_in_2\[14\]/serial_clock
++ gpio_control_in_1\[11\]/serial_data_in gpio_control_in_1\[12\]/serial_data_in mprj/io_in[13]
++ mprj/io_oeb[13] mprj/io_out[13] gpio_control_in_1\[11\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_in_1\[1\] soc/mgmt_in_data[3] gpio_control_in_1\[1\]/one soc/mgmt_in_data[3]
++ gpio_control_in_1\[1\]/one padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3]
++ padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[9] padframe/mprj_io_dm[10] padframe/mprj_io_dm[11]
++ padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_in[3]
++ padframe/mprj_io_inp_dis[3] padframe/mprj_io_out[3] padframe/mprj_io_oeb[3] padframe/mprj_io_slow_sel[3]
++ padframe/mprj_io_vtrip_sel[3] gpio_control_in_2\[3\]/resetn gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock gpio_control_in_1\[1\]/serial_data_in
++ gpio_control_in_1\[2\]/serial_data_in mprj/io_in[3] mprj/io_oeb[3] mprj/io_out[3]
++ gpio_control_in_1\[1\]/zero vccd_core vssd_core vccd1_core vssd1_core gpio_control_block
+Xmprj mprj/analog_io[0] mprj/analog_io[10] mprj/analog_io[11] mprj/analog_io[12] mprj/analog_io[13]
++ mprj/analog_io[14] mprj/analog_io[15] mprj/analog_io[16] mprj/analog_io[17] mprj/analog_io[18]
++ mprj/analog_io[19] mprj/analog_io[1] mprj/analog_io[20] mprj/analog_io[21] mprj/analog_io[22]
++ mprj/analog_io[23] mprj/analog_io[24] mprj/analog_io[25] mprj/analog_io[26] mprj/analog_io[27]
++ mprj/analog_io[28] mprj/analog_io[2] mprj/analog_io[3] mprj/analog_io[4] mprj/analog_io[5]
++ mprj/analog_io[6] mprj/analog_io[7] mprj/analog_io[8] mprj/analog_io[9] mprj/io_in[0]
++ mprj/io_out[0] mprj/io_in[10] mprj/io_out[10] mprj/io_in[11] mprj/io_out[11] mprj/io_in[12]
++ mprj/io_out[12] mprj/io_in[13] mprj/io_out[13] mprj/io_in[14] mprj/io_out[14] mprj/io_in[15]
++ mprj/io_out[15] mprj/io_in[16] mprj/io_out[16] mprj/io_in[17] mprj/io_out[17] mprj/io_in[18]
++ mprj/io_out[18] mprj/io_in[19] mprj/io_out[19] mprj/io_in[1] mprj/io_out[1] mprj/io_in[20]
++ mprj/io_out[20] mprj/io_in[21] mprj/io_out[21] mprj/io_in[22] mprj/io_out[22] mprj/io_in[23]
++ mprj/io_out[23] mprj/io_in[24] mprj/io_out[24] mprj/io_in[25] mprj/io_out[25] mprj/io_in[26]
++ mprj/io_out[26] mprj/io_in[27] mprj/io_out[27] mprj/io_in[28] mprj/io_out[28] mprj/io_in[29]
++ mprj/io_out[29] mprj/io_in[2] mprj/io_out[2] mprj/io_in[30] mprj/io_out[30] mprj/io_in[31]
++ mprj/io_out[31] mprj/io_in[32] mprj/io_out[32] mprj/io_in[33] mprj/io_out[33] mprj/io_in[34]
++ mprj/io_out[34] mprj/io_in[35] mprj/io_out[35] mprj/io_in[36] mprj/io_out[36] mprj/io_in[37]
++ mprj/io_out[37] mprj/io_in[3] mprj/io_out[3] mprj/io_in[4] mprj/io_out[4] mprj/io_in[5]
++ mprj/io_out[5] mprj/io_in[6] mprj/io_out[6] mprj/io_in[7] mprj/io_out[7] mprj/io_in[8]
++ mprj/io_out[8] mprj/io_in[9] mprj/io_out[9] mprj/io_oeb[0] mprj/io_oeb[10] mprj/io_oeb[11]
++ mprj/io_oeb[12] mprj/io_oeb[13] mprj/io_oeb[14] mprj/io_oeb[15] mprj/io_oeb[16]
++ mprj/io_oeb[17] mprj/io_oeb[18] mprj/io_oeb[19] mprj/io_oeb[1] mprj/io_oeb[20] mprj/io_oeb[21]
++ mprj/io_oeb[22] mprj/io_oeb[23] mprj/io_oeb[24] mprj/io_oeb[25] mprj/io_oeb[26]
++ mprj/io_oeb[27] mprj/io_oeb[28] mprj/io_oeb[29] mprj/io_oeb[2] mprj/io_oeb[30] mprj/io_oeb[31]
++ mprj/io_oeb[32] mprj/io_oeb[33] mprj/io_oeb[34] mprj/io_oeb[35] mprj/io_oeb[36]
++ mprj/io_oeb[37] mprj/io_oeb[3] mprj/io_oeb[4] mprj/io_oeb[5] mprj/io_oeb[6] mprj/io_oeb[7]
++ mprj/io_oeb[8] mprj/io_oeb[9] mprj/la_data_in[0] mprj/la_data_in[100] mprj/la_data_in[101]
++ mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104] mprj/la_data_in[105]
++ mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108] mprj/la_data_in[109]
++ mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111] mprj/la_data_in[112]
++ mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115] mprj/la_data_in[116]
++ mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119] mprj/la_data_in[11]
++ mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122] mprj/la_data_in[123]
++ mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126] mprj/la_data_in[127]
++ mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14] mprj/la_data_in[15]
++ mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18] mprj/la_data_in[19]
++ mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22] mprj/la_data_in[23]
++ mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26] mprj/la_data_in[27]
++ mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30] mprj/la_data_in[31]
++ mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34] mprj/la_data_in[35]
++ mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38] mprj/la_data_in[39]
++ mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42] mprj/la_data_in[43]
++ mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46] mprj/la_data_in[47]
++ mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50] mprj/la_data_in[51]
++ mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54] mprj/la_data_in[55]
++ mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58] mprj/la_data_in[59]
++ mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62] mprj/la_data_in[63]
++ mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66] mprj/la_data_in[67]
++ mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70] mprj/la_data_in[71]
++ mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74] mprj/la_data_in[75]
++ mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78] mprj/la_data_in[79]
++ mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82] mprj/la_data_in[83]
++ mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86] mprj/la_data_in[87]
++ mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90] mprj/la_data_in[91]
++ mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94] mprj/la_data_in[95]
++ mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98] mprj/la_data_in[99]
++ mprj/la_data_in[9] mprj/la_data_out[0] mprj/la_data_out[100] mprj/la_data_out[101]
++ mprj/la_data_out[102] mprj/la_data_out[103] mprj/la_data_out[104] mprj/la_data_out[105]
++ mprj/la_data_out[106] mprj/la_data_out[107] mprj/la_data_out[108] mprj/la_data_out[109]
++ mprj/la_data_out[10] mprj/la_data_out[110] mprj/la_data_out[111] mprj/la_data_out[112]
++ mprj/la_data_out[113] mprj/la_data_out[114] mprj/la_data_out[115] mprj/la_data_out[116]
++ mprj/la_data_out[117] mprj/la_data_out[118] mprj/la_data_out[119] mprj/la_data_out[11]
++ mprj/la_data_out[120] mprj/la_data_out[121] mprj/la_data_out[122] mprj/la_data_out[123]
++ mprj/la_data_out[124] mprj/la_data_out[125] mprj/la_data_out[126] mprj/la_data_out[127]
++ mprj/la_data_out[12] mprj/la_data_out[13] mprj/la_data_out[14] mprj/la_data_out[15]
++ mprj/la_data_out[16] mprj/la_data_out[17] mprj/la_data_out[18] mprj/la_data_out[19]
++ mprj/la_data_out[1] mprj/la_data_out[20] mprj/la_data_out[21] mprj/la_data_out[22]
++ mprj/la_data_out[23] mprj/la_data_out[24] mprj/la_data_out[25] mprj/la_data_out[26]
++ mprj/la_data_out[27] mprj/la_data_out[28] mprj/la_data_out[29] mprj/la_data_out[2]
++ mprj/la_data_out[30] mprj/la_data_out[31] mprj/la_data_out[32] mprj/la_data_out[33]
++ mprj/la_data_out[34] mprj/la_data_out[35] mprj/la_data_out[36] mprj/la_data_out[37]
++ mprj/la_data_out[38] mprj/la_data_out[39] mprj/la_data_out[3] mprj/la_data_out[40]
++ mprj/la_data_out[41] mprj/la_data_out[42] mprj/la_data_out[43] mprj/la_data_out[44]
++ mprj/la_data_out[45] mprj/la_data_out[46] mprj/la_data_out[47] mprj/la_data_out[48]
++ mprj/la_data_out[49] mprj/la_data_out[4] mprj/la_data_out[50] mprj/la_data_out[51]
++ mprj/la_data_out[52] mprj/la_data_out[53] mprj/la_data_out[54] mprj/la_data_out[55]
++ mprj/la_data_out[56] mprj/la_data_out[57] mprj/la_data_out[58] mprj/la_data_out[59]
++ mprj/la_data_out[5] mprj/la_data_out[60] mprj/la_data_out[61] mprj/la_data_out[62]
++ mprj/la_data_out[63] mprj/la_data_out[64] mprj/la_data_out[65] mprj/la_data_out[66]
++ mprj/la_data_out[67] mprj/la_data_out[68] mprj/la_data_out[69] mprj/la_data_out[6]
++ mprj/la_data_out[70] mprj/la_data_out[71] mprj/la_data_out[72] mprj/la_data_out[73]
++ mprj/la_data_out[74] mprj/la_data_out[75] mprj/la_data_out[76] mprj/la_data_out[77]
++ mprj/la_data_out[78] mprj/la_data_out[79] mprj/la_data_out[7] mprj/la_data_out[80]
++ mprj/la_data_out[81] mprj/la_data_out[82] mprj/la_data_out[83] mprj/la_data_out[84]
++ mprj/la_data_out[85] mprj/la_data_out[86] mprj/la_data_out[87] mprj/la_data_out[88]
++ mprj/la_data_out[89] mprj/la_data_out[8] mprj/la_data_out[90] mprj/la_data_out[91]
++ mprj/la_data_out[92] mprj/la_data_out[93] mprj/la_data_out[94] mprj/la_data_out[95]
++ mprj/la_data_out[96] mprj/la_data_out[97] mprj/la_data_out[98] mprj/la_data_out[99]
++ mprj/la_data_out[9] mprj/la_oenb[0] mprj/la_oenb[100] mprj/la_oenb[101] mprj/la_oenb[102]
++ mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105] mprj/la_oenb[106] mprj/la_oenb[107]
++ mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10] mprj/la_oenb[110] mprj/la_oenb[111]
++ mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114] mprj/la_oenb[115] mprj/la_oenb[116]
++ mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119] mprj/la_oenb[11] mprj/la_oenb[120]
++ mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123] mprj/la_oenb[124] mprj/la_oenb[125]
++ mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12] mprj/la_oenb[13] mprj/la_oenb[14]
++ mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17] mprj/la_oenb[18] mprj/la_oenb[19]
++ mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21] mprj/la_oenb[22] mprj/la_oenb[23]
++ mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26] mprj/la_oenb[27] mprj/la_oenb[28]
++ mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30] mprj/la_oenb[31] mprj/la_oenb[32]
++ mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35] mprj/la_oenb[36] mprj/la_oenb[37]
++ mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3] mprj/la_oenb[40] mprj/la_oenb[41]
++ mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44] mprj/la_oenb[45] mprj/la_oenb[46]
++ mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49] mprj/la_oenb[4] mprj/la_oenb[50]
++ mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53] mprj/la_oenb[54] mprj/la_oenb[55]
++ mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58] mprj/la_oenb[59] mprj/la_oenb[5]
++ mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62] mprj/la_oenb[63] mprj/la_oenb[64]
++ mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67] mprj/la_oenb[68] mprj/la_oenb[69]
++ mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71] mprj/la_oenb[72] mprj/la_oenb[73]
++ mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76] mprj/la_oenb[77] mprj/la_oenb[78]
++ mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80] mprj/la_oenb[81] mprj/la_oenb[82]
++ mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85] mprj/la_oenb[86] mprj/la_oenb[87]
++ mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8] mprj/la_oenb[90] mprj/la_oenb[91]
++ mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94] mprj/la_oenb[95] mprj/la_oenb[96]
++ mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99] mprj/la_oenb[9] mprj/user_clock2
++ mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2] mprj/wb_clk_i mprj/wb_rst_i soc/mprj_ack_i
++ mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11] mprj/wbs_adr_i[12] mprj/wbs_adr_i[13]
++ mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16] mprj/wbs_adr_i[17] mprj/wbs_adr_i[18]
++ mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20] mprj/wbs_adr_i[21] mprj/wbs_adr_i[22]
++ mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25] mprj/wbs_adr_i[26] mprj/wbs_adr_i[27]
++ mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2] mprj/wbs_adr_i[30] mprj/wbs_adr_i[31]
++ mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5] mprj/wbs_adr_i[6] mprj/wbs_adr_i[7]
++ mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] mprj/wbs_cyc_i mprj/wbs_dat_i[0] mprj/wbs_dat_i[10]
++ mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13] mprj/wbs_dat_i[14] mprj/wbs_dat_i[15]
++ mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18] mprj/wbs_dat_i[19] mprj/wbs_dat_i[1]
++ mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22] mprj/wbs_dat_i[23] mprj/wbs_dat_i[24]
++ mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27] mprj/wbs_dat_i[28] mprj/wbs_dat_i[29]
++ mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31] mprj/wbs_dat_i[3] mprj/wbs_dat_i[4]
++ mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7] mprj/wbs_dat_i[8] mprj/wbs_dat_i[9]
++ soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12] soc/mprj_dat_i[13]
++ soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17] soc/mprj_dat_i[18]
++ soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21] soc/mprj_dat_i[22]
++ soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26] soc/mprj_dat_i[27]
++ soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30] soc/mprj_dat_i[31]
++ soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6] soc/mprj_dat_i[7]
++ soc/mprj_dat_i[8] soc/mprj_dat_i[9] mprj/wbs_sel_i[0] mprj/wbs_sel_i[1] mprj/wbs_sel_i[2]
++ mprj/wbs_sel_i[3] mprj/wbs_stb_i mprj/wbs_we_i vccd1_core vssd1_core vccd2_core
++ vssd2_core vdda1_core vssa1_core vdda2_core vssa2_core user_project_wrapper
+Xgpio_control_in_2\[4\] soc/mgmt_in_data[23] gpio_control_in_2\[4\]/one soc/mgmt_in_data[23]
++ gpio_control_in_2\[4\]/one padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23]
++ padframe/mprj_io_analog_sel[23] padframe/mprj_io_dm[69] padframe/mprj_io_dm[70]
++ padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23] padframe/mprj_io_ib_mode_sel[23]
++ padframe/mprj_io_in[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_out[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23] gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[5\]/resetn gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock
++ gpio_control_in_2\[4\]/serial_data_in gpio_control_in_2\[3\]/serial_data_in mprj/io_in[23]
++ mprj/io_oeb[23] mprj/io_out[23] gpio_control_in_2\[4\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xgpio_control_bidir_1\[1\] soc/mgmt_in_data[1] soc/sdo_outenb soc/sdo_out gpio_control_bidir_1\[1\]/one
++ padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1] padframe/mprj_io_analog_sel[1]
++ padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5] padframe/mprj_io_holdover[1]
++ padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_in[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_out[1] padframe/mprj_io_oeb[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ gpio_control_in_2\[1\]/resetn gpio_control_in_2\[2\]/resetn gpio_control_in_2\[1\]/serial_clock
++ gpio_control_in_2\[2\]/serial_clock gpio_control_bidir_1\[1\]/serial_data_in gpio_control_in_1\[0\]/serial_data_in
++ mprj/io_in[1] mprj/io_oeb[1] mprj/io_out[1] gpio_control_bidir_1\[1\]/zero vccd_core
++ vssd_core vccd1_core vssd1_core gpio_control_block
+Xcopyright_block_0 VSUBS copyright_block
+Xgpio_control_in_2\[2\] soc/mgmt_in_data[21] gpio_control_in_2\[2\]/one soc/mgmt_in_data[21]
++ gpio_control_in_2\[2\]/one padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21]
++ padframe/mprj_io_analog_sel[21] padframe/mprj_io_dm[63] padframe/mprj_io_dm[64]
++ padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21] padframe/mprj_io_ib_mode_sel[21]
++ padframe/mprj_io_in[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_out[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21] gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[3\]/resetn gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock
++ gpio_control_in_2\[2\]/serial_data_in gpio_control_in_2\[1\]/serial_data_in mprj/io_in[21]
++ mprj/io_oeb[21] mprj/io_out[21] gpio_control_in_2\[2\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xstorage soc/mgmt_addr[0] soc/mgmt_addr[1] soc/mgmt_addr[2] soc/mgmt_addr[3] soc/mgmt_addr[4]
++ soc/mgmt_addr[5] soc/mgmt_addr[6] soc/mgmt_addr[7] soc/mgmt_addr_ro[0] soc/mgmt_addr_ro[1]
++ soc/mgmt_addr_ro[2] soc/mgmt_addr_ro[3] soc/mgmt_addr_ro[4] soc/mgmt_addr_ro[5]
++ soc/mgmt_addr_ro[6] soc/mgmt_addr_ro[7] soc/core_clk soc/mgmt_ena[0] soc/mgmt_ena[1]
++ soc/mgmt_ena_ro soc/mgmt_rdata[0] soc/mgmt_rdata[10] soc/mgmt_rdata[11] soc/mgmt_rdata[12]
++ soc/mgmt_rdata[13] soc/mgmt_rdata[14] soc/mgmt_rdata[15] soc/mgmt_rdata[16] soc/mgmt_rdata[17]
++ soc/mgmt_rdata[18] soc/mgmt_rdata[19] soc/mgmt_rdata[1] soc/mgmt_rdata[20] soc/mgmt_rdata[21]
++ soc/mgmt_rdata[22] soc/mgmt_rdata[23] soc/mgmt_rdata[24] soc/mgmt_rdata[25] soc/mgmt_rdata[26]
++ soc/mgmt_rdata[27] soc/mgmt_rdata[28] soc/mgmt_rdata[29] soc/mgmt_rdata[2] soc/mgmt_rdata[30]
++ soc/mgmt_rdata[31] soc/mgmt_rdata[32] soc/mgmt_rdata[33] soc/mgmt_rdata[34] soc/mgmt_rdata[35]
++ soc/mgmt_rdata[36] soc/mgmt_rdata[37] soc/mgmt_rdata[38] soc/mgmt_rdata[39] soc/mgmt_rdata[3]
++ soc/mgmt_rdata[40] soc/mgmt_rdata[41] soc/mgmt_rdata[42] soc/mgmt_rdata[43] soc/mgmt_rdata[44]
++ soc/mgmt_rdata[45] soc/mgmt_rdata[46] soc/mgmt_rdata[47] soc/mgmt_rdata[48] soc/mgmt_rdata[49]
++ soc/mgmt_rdata[4] soc/mgmt_rdata[50] soc/mgmt_rdata[51] soc/mgmt_rdata[52] soc/mgmt_rdata[53]
++ soc/mgmt_rdata[54] soc/mgmt_rdata[55] soc/mgmt_rdata[56] soc/mgmt_rdata[57] soc/mgmt_rdata[58]
++ soc/mgmt_rdata[59] soc/mgmt_rdata[5] soc/mgmt_rdata[60] soc/mgmt_rdata[61] soc/mgmt_rdata[62]
++ soc/mgmt_rdata[63] soc/mgmt_rdata[6] soc/mgmt_rdata[7] soc/mgmt_rdata[8] soc/mgmt_rdata[9]
++ soc/mgmt_rdata_ro[0] soc/mgmt_rdata_ro[10] soc/mgmt_rdata_ro[11] soc/mgmt_rdata_ro[12]
++ soc/mgmt_rdata_ro[13] soc/mgmt_rdata_ro[14] soc/mgmt_rdata_ro[15] soc/mgmt_rdata_ro[16]
++ soc/mgmt_rdata_ro[17] soc/mgmt_rdata_ro[18] soc/mgmt_rdata_ro[19] soc/mgmt_rdata_ro[1]
++ soc/mgmt_rdata_ro[20] soc/mgmt_rdata_ro[21] soc/mgmt_rdata_ro[22] soc/mgmt_rdata_ro[23]
++ soc/mgmt_rdata_ro[24] soc/mgmt_rdata_ro[25] soc/mgmt_rdata_ro[26] soc/mgmt_rdata_ro[27]
++ soc/mgmt_rdata_ro[28] soc/mgmt_rdata_ro[29] soc/mgmt_rdata_ro[2] soc/mgmt_rdata_ro[30]
++ soc/mgmt_rdata_ro[31] soc/mgmt_rdata_ro[3] soc/mgmt_rdata_ro[4] soc/mgmt_rdata_ro[5]
++ soc/mgmt_rdata_ro[6] soc/mgmt_rdata_ro[7] soc/mgmt_rdata_ro[8] soc/mgmt_rdata_ro[9]
++ soc/mgmt_wdata[0] soc/mgmt_wdata[10] soc/mgmt_wdata[11] soc/mgmt_wdata[12] soc/mgmt_wdata[13]
++ soc/mgmt_wdata[14] soc/mgmt_wdata[15] soc/mgmt_wdata[16] soc/mgmt_wdata[17] soc/mgmt_wdata[18]
++ soc/mgmt_wdata[19] soc/mgmt_wdata[1] soc/mgmt_wdata[20] soc/mgmt_wdata[21] soc/mgmt_wdata[22]
++ soc/mgmt_wdata[23] soc/mgmt_wdata[24] soc/mgmt_wdata[25] soc/mgmt_wdata[26] soc/mgmt_wdata[27]
++ soc/mgmt_wdata[28] soc/mgmt_wdata[29] soc/mgmt_wdata[2] soc/mgmt_wdata[30] soc/mgmt_wdata[31]
++ soc/mgmt_wdata[3] soc/mgmt_wdata[4] soc/mgmt_wdata[5] soc/mgmt_wdata[6] soc/mgmt_wdata[7]
++ soc/mgmt_wdata[8] soc/mgmt_wdata[9] soc/mgmt_wen[0] soc/mgmt_wen[1] soc/mgmt_wen_mask[0]
++ soc/mgmt_wen_mask[1] soc/mgmt_wen_mask[2] soc/mgmt_wen_mask[3] soc/mgmt_wen_mask[4]
++ soc/mgmt_wen_mask[5] soc/mgmt_wen_mask[6] soc/mgmt_wen_mask[7] vccd_core vssd_core
++ storage
+Xgpio_control_in_1\[8\] soc/mgmt_in_data[10] gpio_control_in_1\[8\]/one soc/mgmt_in_data[10]
++ gpio_control_in_1\[8\]/one padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10]
++ padframe/mprj_io_analog_sel[10] padframe/mprj_io_dm[30] padframe/mprj_io_dm[31]
++ padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10] padframe/mprj_io_ib_mode_sel[10]
++ padframe/mprj_io_in[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_out[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10] gpio_control_in_1\[8\]/resetn
++ gpio_control_in_1\[9\]/resetn gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[9\]/serial_clock
++ gpio_control_in_1\[8\]/serial_data_in gpio_control_in_1\[9\]/serial_data_in mprj/io_in[10]
++ mprj/io_oeb[10] mprj/io_out[10] gpio_control_in_1\[8\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+Xcaravel_power_routing_0 VSUBS vccd1_core vssd_core vdda1_core vssd2_core vssio_core
++ vssa2_core vddio_core vccd2_core vdda2_core vssd1_core vccd_core vssa1_core caravel_power_routing
+Xgpio_control_in_2\[16\] soc/mgmt_in_data[35] gpio_control_in_2\[16\]/one soc/mgmt_in_data[35]
++ gpio_control_in_2\[16\]/one padframe/mprj_io_analog_en[35] padframe/mprj_io_analog_pol[35]
++ padframe/mprj_io_analog_sel[35] padframe/mprj_io_dm[105] padframe/mprj_io_dm[106]
++ padframe/mprj_io_dm[107] padframe/mprj_io_holdover[35] padframe/mprj_io_ib_mode_sel[35]
++ padframe/mprj_io_in[35] padframe/mprj_io_inp_dis[35] padframe/mprj_io_out[35] padframe/mprj_io_oeb[35]
++ padframe/mprj_io_slow_sel[35] padframe/mprj_io_vtrip_sel[35] gpio_control_in_2\[16\]/resetn
++ gpio_control_in_1\[15\]/resetn gpio_control_in_2\[16\]/serial_clock gpio_control_in_1\[15\]/serial_clock
++ gpio_control_in_2\[16\]/serial_data_in gpio_control_in_2\[15\]/serial_data_in mprj/io_in[35]
++ mprj/io_oeb[35] mprj/io_out[35] gpio_control_in_2\[16\]/zero vccd_core vssd_core
++ vccd1_core vssd1_core gpio_control_block
+.ends
+
diff --git a/caravel/spi/lvs/run_lvs.sh b/caravel/spi/lvs/run_lvs.sh
new file mode 100644
index 0000000..25c27a1
--- /dev/null
+++ b/caravel/spi/lvs/run_lvs.sh
@@ -0,0 +1,20 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+NETGEN_SETUP=$PDK_ROOT/sky130A/libs.tech/netgen/sky130A_setup.tcl
+
+netgen -batch lvs "$1 $3" "$2 $3" ${NETGEN_SETUP} $2_comp.out -json | tee $2_comp_lvs.log
diff --git a/caravel/utils/MAGIC.txt b/caravel/utils/MAGIC.txt
new file mode 100644
index 0000000..78b4d56
--- /dev/null
+++ b/caravel/utils/MAGIC.txt
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+####
+
+1) You must set the PDK_ROOT variable
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export PDKPATH=$PDK_ROOT/sky130A ;
+
+2) Useful misc utils
+
+
+
+load caravel -dereference
+drc style drc(full)
+drc why
+drc find 10 ; findbox zoom
diff --git a/caravel/utils/README.txt b/caravel/utils/README.txt
new file mode 100644
index 0000000..78b4d56
--- /dev/null
+++ b/caravel/utils/README.txt
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+####
+
+1) You must set the PDK_ROOT variable
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export PDKPATH=$PDK_ROOT/sky130A ;
+
+2) Useful misc utils
+
+
+
+load caravel -dereference
+drc style drc(full)
+drc why
+drc find 10 ; findbox zoom
diff --git a/caravel/utils/addmpwseal.tcl b/caravel/utils/addmpwseal.tcl
new file mode 100644
index 0000000..b562f93
--- /dev/null
+++ b/caravel/utils/addmpwseal.tcl
@@ -0,0 +1,25 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly true
+gds rescale false
+gds read ../gds/sram_1rw1r_32_256_8_sky130_lp1.gds
+load ./caravel.mag
+select top cell
+move origin -7.165um -7.120um
+box position 0 0
+getcell advSeal_6um_gen
+gds write caravel.mpw.gds
diff --git a/caravel/utils/apply_caravel.sh b/caravel/utils/apply_caravel.sh
new file mode 100755
index 0000000..1a922cf
--- /dev/null
+++ b/caravel/utils/apply_caravel.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To use: sh apply_caravel.sh <target_project_path> <template_caravel_path>
+
+target_project=$1
+original_caravel=$2
+
+find $original_caravel/def/* -type f ! -name "user_project_wrapper.def" ! -name "user_proj_example.def" -exec cp {} $target_project/def \;
+find $original_caravel/lef/* -type f ! -name "user_project_wrapper.lef" ! -name "user_proj_example.lef" -exec cp {} $target_project/lef \;
+find $original_caravel/gds/* -type f ! -name "user_project_wrapper.gds.gz" ! -name "user_proj_example.gds.gz" ! -name "user_project_wrapper.gds" ! -name "user_proj_example.gds" -exec cp {} $target_project/gds \;
+find $original_caravel/mag/* -type f ! -name "user_project_wrapper.mag" ! -name "user_proj_example.mag" -exec cp {} $target_project/mag \;
+cp $original_caravel/mag/.magicrc $target_project/mag/
+mkdir -p $target_project/mag/hexdigits/
+mv $target_project/mag/alpha_*.mag $target_project/mag/hexdigits/
+cp $original_caravel/maglef/* $target_project/maglef
+cp -r $original_caravel/ngspice/digital_pll $target_project/ngspice/digital_pll
+cp -r $original_caravel/ngspice/simple_por $target_project/ngspice/simple_por
+cp -r $original_caravel/scripts $target_project/scripts
+find $original_caravel/spi/lvs/* -type f ! -name "user_project_wrapper.spice" ! -name "user_proj_example.spice" -exec cp {} $target_project/spi/lvs/ \;
+cp -r $original_caravel/utils $target_project/utils
+find $original_caravel/verilog/rtl/* -type f ! -name "user_project_wrapper.v" ! -name "user_proj_example.v" -exec cp {} $target_project/verilog/rtl/ \;
+find $original_caravel/verilog/gl/* -type f ! -name "user_project_wrapper.v" ! -name "user_proj_example.v" -exec cp {} $target_project/verilog/gl/ \;
+cp $original_caravel/verilog/stubs/*.v $target_project/verilog/stubs/
+cp -r $original_caravel/verilog/dv/caravel $target_project/verilog/dv/caravel
+cp -r $original_caravel/verilog/dv/wb_utests $target_project/verilog/dv/wb_utests
+cp $original_caravel/verilog/dv/dummy_slave.v $target_project/verilog/dv/dummy_slave.v
+
+echo "You'll have to manually copy the openlane/user_project_wrapper configs based on your preference."
+echo "You'll have to manually copy the openlane/Makefile based on your preference."
+echo "You'll have to manually copy the Makefile based on your preference."
\ No newline at end of file
diff --git a/caravel/utils/core_scripts/README.md b/caravel/utils/core_scripts/README.md
new file mode 100644
index 0000000..b14c1db
--- /dev/null
+++ b/caravel/utils/core_scripts/README.md
@@ -0,0 +1,20 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+# What is this?
+
+Core scripts are doing the actual work, scripts under ../scripts are the ones that should be used.
\ No newline at end of file
diff --git a/caravel/utils/core_scripts/magic-drc.sh b/caravel/utils/core_scripts/magic-drc.sh
new file mode 100644
index 0000000..5f5068d
--- /dev/null
+++ b/caravel/utils/core_scripts/magic-drc.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./magic-drc.sh <target_path> <design_name> <pdk-root> <target-type> <pdk-name> <output_path>
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export TARGET_TYPE=$4
+export PDK=$5
+export OUT_DIR=$6
+export TCL_CALL_PATH=${7:-$(pwd)}
+
+echo "Running Magic..."
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/sky130A.magicrc
+
+magic \
+ -noconsole \
+ -dnull \
+ -rcfile $MAGIC_MAGICRC \
+ $TCL_CALL_PATH/magic-drc.tcl \
+ </dev/null \
+ |& tee $OUT_DIR/magic_drc.log
+
+TEST=$OUT_DIR/$DESIGN_NAME.magic.drc
+
+crashSignal=$(find $TEST)
+if ! [[ $crashSignal ]]; then echo "DRC Check FAILED"; exit -1; fi
+
+
+Test_Magic_violations=$(grep "COUNT: " $TEST -s | tail -1 | sed -r 's/[^0-9]*//g')
+if ! [[ $Test_Magic_violations ]]; then Test_Magic_violations=-1; fi
+if [ $Test_Magic_violations -ne -1 ]; then Test_Magic_violations=$(((Test_Magic_violations+3)/4)); fi
+
+echo "Test # of DRC Violations:"
+echo $Test_Magic_violations
+
+if [ 0 -ne $Test_Magic_violations ]; then echo "DRC Check FAILED"; exit -1; fi
+
+echo "DRC Check Passed"
+exit 0
diff --git a/caravel/utils/core_scripts/magic-drc.tcl b/caravel/utils/core_scripts/magic-drc.tcl
new file mode 100755
index 0000000..6768d3c
--- /dev/null
+++ b/caravel/utils/core_scripts/magic-drc.tcl
@@ -0,0 +1,74 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+if { $::env(TARGET_TYPE) == "gds"} {
+ gds read $::env(TARGET_DIR)/$::env(DESIGN_NAME).gds
+} else {
+ if { $::env(TARGET_TYPE) == "mag" } {
+ load $::env(TARGET_DIR)/$::env(DESIGN_NAME).mag
+ } else {
+ def read $::env(TARGET_DIR)/$::env(DESIGN_NAME).def
+ }
+}
+
+set fout [open $::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_NAME)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $cell_name\n"
+flush stdout
+load $cell_name
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+
+
+set count 0
+puts $fout "$cell_name"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE ($::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors($::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save $::env(OUT_DIR)/$::env(DESIGN_NAME).magic.drc.mag
+puts stdout "\[INFO\]: Saved"
+
+exit 0
diff --git a/caravel/utils/core_scripts/magic-ext.sh b/caravel/utils/core_scripts/magic-ext.sh
new file mode 100644
index 0000000..68bfc39
--- /dev/null
+++ b/caravel/utils/core_scripts/magic-ext.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./magic-ext.sh <target_path> <design_name> <pdk-root> <target-type> <pdk-name> <output_path>
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export TARGET_TYPE=$4
+export PDK=$5
+export OUT_DIR=$6
+export TCL_CALL_PATH=${7:-$(pwd)}
+
+echo "Running Magic..."
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/sky130A.magicrc
+
+magic \
+ -noconsole \
+ -dnull \
+ -rcfile $MAGIC_MAGICRC \
+ $TCL_CALL_PATH/magic-ext.tcl \
+ </dev/null \
+ |& tee $OUT_DIR/magic_ext.log
diff --git a/caravel/utils/core_scripts/magic-ext.tcl b/caravel/utils/core_scripts/magic-ext.tcl
new file mode 100644
index 0000000..5a05dcb
--- /dev/null
+++ b/caravel/utils/core_scripts/magic-ext.tcl
@@ -0,0 +1,44 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+puts "Performing Spice Extractions..."
+
+if { ![file isdirectory $::env(OUT_DIR)] } {
+ exec mkdir $::env(OUT_DIR)/
+}
+
+
+if { $::env(TARGET_TYPE) == "gds"} {
+ gds read $::env(TARGET_DIR)/$::env(DESIGN_NAME).gds
+} else {
+ if { $::env(TARGET_TYPE) == "mag" } {
+ load $::env(TARGET_DIR)/$::env(DESIGN_NAME).mag
+ } else {
+ def read $::env(TARGET_DIR)/$::env(DESIGN_NAME).def
+ }
+}
+
+load $::env(DESIGN_NAME) -dereference
+cd $::env(OUT_DIR)/
+extract do local
+# extract warn all
+extract
+ext2spice lvs
+ext2spice $::env(DESIGN_NAME).ext
+feedback save $::env(OUT_DIR)/magic_extraction_feedback.txt
+
+puts "Done!"
\ No newline at end of file
diff --git a/caravel/utils/draw_boundary.sh b/caravel/utils/draw_boundary.sh
new file mode 100644
index 0000000..582be75
--- /dev/null
+++ b/caravel/utils/draw_boundary.sh
@@ -0,0 +1,45 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+: ${1?"Usage: $0 file.mag llx lly urx ury"}
+: ${2?"Usage: $0 file.mag llx lly urx ury"}
+: ${3?"Usage: $0 file.mag llx lly urx ury"}
+: ${4?"Usage: $0 file.mag llx lly urx ury"}
+: ${5?"Usage: $0 file.mag llx lly urx ury"}
+: ${PDK_ROOT?"You need to export PDK_ROOT"}
+
+
+export PDK=sky130A
+
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc
+
+MAGTYPE=mag magic -rcfile $MAGIC_MAGICRC -dnull -noconsole $1 <<EOF
+echo $MAGTYPE
+## Draw Top Boundary
+box 0um $5um $4um 3520.5um
+paint comment
+## Draw Bottom Boundary
+box 0um -0.5um $4um 0um
+paint comment
+## Draw Left Boundary
+box -0.5um -0.5um 0um 3520.5um
+paint comment
+## Draw Right Boundary
+box $4um -0.5um 2920.5um 3520.5um
+paint comment
+## Save mag file
+save
+EOF
+ls $1
diff --git a/caravel/utils/drc-def-sky130A.sh b/caravel/utils/drc-def-sky130A.sh
new file mode 100644
index 0000000..671b14a
--- /dev/null
+++ b/caravel/utils/drc-def-sky130A.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./drc-def-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+bash ./core_scripts/magic-drc.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "def" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/caravel/utils/drc-gds-sky130A.sh b/caravel/utils/drc-gds-sky130A.sh
new file mode 100644
index 0000000..4c1d6d8
--- /dev/null
+++ b/caravel/utils/drc-gds-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./drc-gds-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-drc.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "gds" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/caravel/utils/drc-mag-sky130A.sh b/caravel/utils/drc-mag-sky130A.sh
new file mode 100644
index 0000000..2bbecd3
--- /dev/null
+++ b/caravel/utils/drc-mag-sky130A.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./drc-mag-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+bash ./core_scripts/magic-drc.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "mag" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/caravel/utils/erase_box.sh b/caravel/utils/erase_box.sh
new file mode 100644
index 0000000..7636e42
--- /dev/null
+++ b/caravel/utils/erase_box.sh
@@ -0,0 +1,42 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+: ${1?"Usage: $0 file.gds llx lly urx ury"}
+: ${2?"Usage: $0 file.gds llx lly urx ury"}
+: ${3?"Usage: $0 file.gds llx lly urx ury"}
+: ${4?"Usage: $0 file.gds llx lly urx ury"}
+: ${5?"Usage: $0 file.gds llx lly urx ury"}
+: ${PDK_ROOT?"You need to export PDK_ROOT"}
+
+
+export PDK=sky130A
+
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc
+
+MAGTYPE=mag magic -rcfile $MAGIC_MAGICRC -dnull -noconsole <<EOF
+echo $MAGTYPE
+tech unlock *
+gds read $1
+box $2um $3um $4um $5um
+erase
+select area
+delete
+#### REVISE THIS:
+select top cell
+erase labels
+####
+gds write ${1%.*}_erased.gds
+EOF
+ls ${1%.*}_erased.gds
diff --git a/caravel/utils/examples/README.md b/caravel/utils/examples/README.md
new file mode 100644
index 0000000..10f7a37
--- /dev/null
+++ b/caravel/utils/examples/README.md
@@ -0,0 +1,19 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+This folder contains miscelleneous useful scripts
+THIS IS STILL WORK IN PROGRESSS - SUGGESTIONS ARE WELCOME THROUGH ISSUES
diff --git a/caravel/utils/examples/addmpwseal.tcl b/caravel/utils/examples/addmpwseal.tcl
new file mode 100644
index 0000000..79e4b9e
--- /dev/null
+++ b/caravel/utils/examples/addmpwseal.tcl
@@ -0,0 +1,26 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly true
+gds read ../gds/sram_1rw1r_32_256_8_sky130_lp1.gds
+load openram_tc_1kb.mag
+select top cell
+move origin -1015um -1272.5um
+box position 0 0
+getcell advSeal_6um_gen
+save
+gds write ../gds/openram_tc_1kb.gds
+
diff --git a/caravel/utils/examples/create-project.sh b/caravel/utils/examples/create-project.sh
new file mode 100755
index 0000000..5b5b69c
--- /dev/null
+++ b/caravel/utils/examples/create-project.sh
@@ -0,0 +1,38 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+cat <<'EOT' > .gitignore
+.DS_Store
+*.vcd
+*.raw
+*.vvp
+a.out
+EOT
+mkdir scripts ; echo "This folder contains miscelleneous useful scripts" > scripts/README.md
+mkdir def ; echo "This folder contains *.def files related to this project" > def/README.md
+mkdir gds ; echo "This folder contains *.gds files related to this project" > gds/README.md
+mkdir verilog ; echo "This folder contains *.v files related to this project" > verilog/README.md
+mkdir mag ; echo "This folder contains *.mag files related to this project" > mag/README.md
+mkdir lef ; echo "This folder contains *.lef files related to this project" > lef/README.md
+mkdir macros ; echo "This folder contains subcell & macro files related to this project" > macros/README.md
+mkdir doc ; echo "This folder contains documents related to this project" > doc/README.md
+mkdir ngspice ; echo "This folder contains ngspice related files related to this project" > ngspice/README.md
+mkdir openlane ; echo "This folder contains openlane related files related to this project" > openlane/README.md
+mkdir pkg ; echo "This folder contains packaging-related files related to this project" > pkg/README.md
+mkdir test ; echo "This folder contains test-related files related to this project" > test/README.md
+mkdir xspice ; echo "This folder contains xspice files related to this project" > xspice/README.md
+mkdir spi ; echo "This folder contains *.spi files related to this project" > spi/README.md
+mkdir qflow ; echo "This folder contains qflow-related files related to this project" > qflow/README.md
diff --git a/caravel/utils/examples/dot.magicrc b/caravel/utils/examples/dot.magicrc
new file mode 100644
index 0000000..42f2fb2
--- /dev/null
+++ b/caravel/utils/examples/dot.magicrc
@@ -0,0 +1,65 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+
+# default pdk
+# set SW_PDK_ROOT "/ef/tech/SW.2"
+set PDK "sky130A"
+set SCL_VARIANT "sky130_fd_sc_hd"
+set IO_VARIANT "sky130_fd_io"
+set PDKPATH "$::env(SW_PDK_ROOT)/$PDK"
+
+# loading technology
+tech load "$PDKPATH/libs.tech/magic/current/$PDK.tech"
+
+# load device generator
+source "$PDKPATH/libs.tech/magic/current/$PDK.tcl"
+
+
+# load bind keys (optional)
+source "$PDKPATH/libs.tech/magic/current/$PDK-BindKeys"
+
+# set units to lambda grid
+snap lambda
+
+# add path to reference cells
+set MAGPATH "$PDKPATH/libs.ref/$SCL_VARIANT/mag/*.mag"
+
+
+addpath "$PDKPATH/libs.ref/sky130_fd_pr_base/mag"
+addpath "$PDKPATH/libs.ref/$IO_VARIANT/mag"
+addpath "$PDKPATH/libs.ref/$SCL_VARIANT/mag"
+
+# addpath ${MAGPATH}/s8fmlt
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/caravel/utils/examples/drc-mag.sh b/caravel/utils/examples/drc-mag.sh
new file mode 100644
index 0000000..7229f45
--- /dev/null
+++ b/caravel/utils/examples/drc-mag.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=mag ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1
+cellname delete \(UNNAMED\)
+writeall force
+select top cell
+expand
+drc on
+drc euclidean on
+drc check
+drc catchup
+drc listall
+drc listall why
+drc count total
+drc count
+quit -noprompt
+EOF
diff --git a/caravel/utils/examples/drc-maglef.sh b/caravel/utils/examples/drc-maglef.sh
new file mode 100644
index 0000000..42f622f
--- /dev/null
+++ b/caravel/utils/examples/drc-maglef.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=maglef ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1
+cellname delete \(UNNAMED\)
+writeall force
+select top cell
+expand
+drc on
+drc euclidean on
+drc check
+drc catchup
+drc listall
+drc listall why
+drc count total
+drc count
+quit -noprompt
+EOF
diff --git a/caravel/utils/examples/drc.sh b/caravel/utils/examples/drc.sh
new file mode 100755
index 0000000..7229f45
--- /dev/null
+++ b/caravel/utils/examples/drc.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=mag ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1
+cellname delete \(UNNAMED\)
+writeall force
+select top cell
+expand
+drc on
+drc euclidean on
+drc check
+drc catchup
+drc listall
+drc listall why
+drc count total
+drc count
+quit -noprompt
+EOF
diff --git a/caravel/utils/examples/edit.tcl b/caravel/utils/examples/edit.tcl
new file mode 100644
index 0000000..f1766ad
--- /dev/null
+++ b/caravel/utils/examples/edit.tcl
@@ -0,0 +1,26 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+puts "Small delay..."
+set macro_mags "digital_pll.mag lvlshiftdown.mag striVe2_soc.mag striVe_clkrst.mag striVe_spi.mag"
+
+gds readonly yes
+gds rescale no
+gds read ../gds/sram_1rw1r_32_256_8_sky130.gds
+lef read ../lef/sram.abs.lef
+foreach ff $macro_mags { drc off; load $ff -dereference; after 1000; select top cell; property LEFview TRUE }
+load striVe2 -dereference
+select top cell
diff --git a/caravel/utils/examples/ext-gds.sh b/caravel/utils/examples/ext-gds.sh
new file mode 100644
index 0000000..c3efd7e
--- /dev/null
+++ b/caravel/utils/examples/ext-gds.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=maglef ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1.mag
+save $1.mag
+writeall force
+select top cell
+extract style ngspice(si)
+extract
+ext2spice hierarchy on
+ext2spice format ngspice
+ext2spice cthresh infinite
+ext2spice rthresh infinite
+ext2spice renumber offS
+ext2spice scale off
+ext2spice blackbox on
+ext2spice subcircuit top auto
+ext2spice global off
+ext2spice $1.ext
+quit -noprompt
+EOF
diff --git a/caravel/utils/examples/ext-mag.sh b/caravel/utils/examples/ext-mag.sh
new file mode 100644
index 0000000..a62a831
--- /dev/null
+++ b/caravel/utils/examples/ext-mag.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=mag ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+load $1.mag
+save $1.mag
+writeall force
+select top cell
+extract style ngspice(si)
+extract
+ext2spice hierarchy on
+ext2spice format ngspice
+ext2spice cthresh infinite
+ext2spice rthresh infinite
+ext2spice renumber offS
+ext2spice scale off
+ext2spice blackbox on
+ext2spice subcircuit top auto
+ext2spice global off
+ext2spice $1.ext
+quit -noprompt
+EOF
diff --git a/caravel/utils/examples/ext.sh b/caravel/utils/examples/ext.sh
new file mode 100644
index 0000000..b414e8b
--- /dev/null
+++ b/caravel/utils/examples/ext.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export MAGTYPE=maglef ;
+export BASE=/home/mk/zooz/ ;
+export PDKPATH=$BASE/pdks/ef-skywater-s8/EFS8A ;
+
+magic -dnull -noconsole -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc <<EOF
+gds polygon subcell true
+gds warning default
+gds read $1.gds
+load $1.mag
+save $1.mag
+writeall force
+select top cell
+extract style ngspice(si)
+extract
+ext2spice hierarchy on
+ext2spice format ngspice
+ext2spice cthresh infinite
+ext2spice rthresh infinite
+ext2spice renumber off
+ext2spice scale off
+ext2spice blackbox on
+ext2spice subcircuit top auto
+ext2spice global off
+ext2spice $1.ext
+quit -noprompt
+EOF
diff --git a/caravel/utils/examples/extract.tcl b/caravel/utils/examples/extract.tcl
new file mode 100644
index 0000000..a38c9cb
--- /dev/null
+++ b/caravel/utils/examples/extract.tcl
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+lef read $::env(PDKPATH)/libs.ref/techLEF/scs8hd/scs8hd_tech.lef
+set macro_mags "openram_tc_core.mag"
+
+# lef read ../lef/sram_1rw1r_32_256_8_sky130_lp1.lef
+
+foreach ff $macro_mags { drc off; after 500; load $ff -dereference; select top cell; property LEFview TRUE }
+
+load openram_tc_1kb -dereference
+
+select top cell
+extract do local
+extract
+ext2spice lvs
+ext2spice openram_tc_1kb.ext
+feedback save extract.tcl.log
+exit
diff --git a/caravel/utils/examples/lvs.sh b/caravel/utils/examples/lvs.sh
new file mode 100755
index 0000000..3a5043e
--- /dev/null
+++ b/caravel/utils/examples/lvs.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+/ef/apps/bin/netgen -noconsole << EOF
+readnet spice $1.spice
+readnet spice $1.sp
+lvs {$1.spice sram_2_16_sky130} {sram_2_16_sky130.sp sram_2_16_sky130} setup.tcl sram_2_16_sky130.lvs.report
+quit
+EOF
diff --git a/caravel/utils/examples/mag2gds.tcl b/caravel/utils/examples/mag2gds.tcl
new file mode 100644
index 0000000..8d7057d
--- /dev/null
+++ b/caravel/utils/examples/mag2gds.tcl
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# assumes an /ef tree or at least a symlink
+drc off
+gds readonly true
+gds rescale false
+set ::env(MAGTYPE) mag
+
+# gds read <hard macros read as-is.gds>
+gds read ../gds/sram_1rw1r_32_256_8_sky130_lp1.gds
+
+load sram_1rw1r_32_256_8_sky130 -dereference
+load openram_tc_core -dereference
+load openram_tc_1kb -dereference
+
+select top cell
+
+cif *hier write disable
+
+gds write openram_tc_1kb.gds
diff --git a/caravel/utils/examples/magic_drc.tcl b/caravel/utils/examples/magic_drc.tcl
new file mode 100755
index 0000000..554a4c6
--- /dev/null
+++ b/caravel/utils/examples/magic_drc.tcl
@@ -0,0 +1,71 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+set ::env(DESIGN_NAME) openram_tc_1kb
+drc off
+lef read ../lef/sram_1rw1r_32_256_8_sky130_lp1.lef
+load sram_1rw1r_32_256_8_sky130 -dereference
+load openram_tc_core -dereference
+load openram_tc_1kb -dereference
+
+drc style drc(full)
+drc euclidean on
+
+set fout [open drc.log w]
+set oscale [cif scale out]
+set cell_name $::env(DESIGN_NAME)
+magic::suspendall
+puts stdout "\[INFO\]: Loading $cell_name\n"
+flush stdout
+load $cell_name
+select top cell
+drc check
+set drcresult [drc listall why]
+
+
+set count 0
+puts $fout "$cell_name"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+ puts $fout $errtype
+ puts $fout "----------------------------------------"
+ foreach coord $coordlist {
+ set bllx [expr {$oscale * [lindex $coord 0]}]
+ set blly [expr {$oscale * [lindex $coord 1]}]
+ set burx [expr {$oscale * [lindex $coord 2]}]
+ set bury [expr {$oscale * [lindex $coord 3]}]
+ set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+ puts $fout "$coords"
+ set count [expr {$count + 1} ]
+ }
+ puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE ($::env(DESIGN_NAME).drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors($::env(DESIGN_NAME).drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save $::env(DESIGN_NAME).drc.mag
+puts stdout "\[INFO\]: Saved"
+
+exit 0
diff --git a/caravel/utils/examples/pfg.sh b/caravel/utils/examples/pfg.sh
new file mode 100755
index 0000000..9d8def1
--- /dev/null
+++ b/caravel/utils/examples/pfg.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDKPATH=/home/mk/zooz/pdks/ef-skywater-s8/EFS8A
+export MAGTYPE=mag
+
+padring \
+-L $PDKPATH/libs.ref/lef/s8iom0s8/s8iom0s8.lef \
+-L $PDKPATH/libs.ref/lef/s8iom0s8/power_pads_lib.lef \
+--def padframe.def padframe.cfg
+
+magic -rcfile $PDKPATH/libs.tech/magic/current/EFS8A.magicrc -noc -dnull <<EOF
+def read padframe.def
+save padframe
+select top cell
+lef write padframe.lef
+gds write padframe.gds
+exit
+EOF
+
+
+
+
+
diff --git a/caravel/utils/examples/run_openram_tc_1kb.sh b/caravel/utils/examples/run_openram_tc_1kb.sh
new file mode 100755
index 0000000..408ce96
--- /dev/null
+++ b/caravel/utils/examples/run_openram_tc_1kb.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# Run netgen on striVe (top level)
+#
+
+NETGEN_SETUP=$PDK_ROOT/EFS8A/libs.tech/netgen/EFS8A_setup.tcl
+
+netgen -batch lvs "../spi/openram_tc_1kb.spice openram_tc_1kb" "../verilog/gl/openram_tc_1kb.synthesis.v openram_tc_1kb" ${NETGEN_SETUP} openram_tc_1kb_comp.out -json | tee openram_tc_1kb_comp_lvs.log
diff --git a/caravel/utils/examples/setup.tcl b/caravel/utils/examples/setup.tcl
new file mode 100644
index 0000000..193dd2f
--- /dev/null
+++ b/caravel/utils/examples/setup.tcl
@@ -0,0 +1,27 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# We must flatten these because the ports are disconnected
+flatten class {-circuit1 dummy_cell_6t}
+flatten class {-circuit1 dummy_cell_1rw_1r}
+flatten class {-circuit1 dummy_cell_1w_1r}
+flatten class {-circuit1 bitcell_array_0}
+flatten class {-circuit1 pbitcell_0}
+flatten class {-circuit1 pbitcell_1}
+property {-circuit1 nshort} remove as ad ps pd
+property {-circuit1 pshort} remove as ad ps pd
+property {-circuit2 nshort} remove as ad ps pd
+property {-circuit2 pshort} remove as ad ps pd
+permute transistors
diff --git a/caravel/utils/examples/wrap.tcl b/caravel/utils/examples/wrap.tcl
new file mode 100644
index 0000000..fc2c87e
--- /dev/null
+++ b/caravel/utils/examples/wrap.tcl
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly yes
+gds rescale no
+
+gds read ../macros/sram/riscv-sky130/sram_1rw1r_32_256_8_sky130.gds
+load sram_1rw1r_32_256_8_sky130
+
+select top cell
+property LEFview "TRUE"
+
+save pk_sram_1rw1r_32_256_8_sky130.mag
+
+# exec sed -i -E "/^.*GDS_END.*$/d" sram_1rw1r_32_256_8_sky130_original.mag
diff --git a/caravel/utils/examples/wrap2.tcl b/caravel/utils/examples/wrap2.tcl
new file mode 100644
index 0000000..db1db3c
--- /dev/null
+++ b/caravel/utils/examples/wrap2.tcl
@@ -0,0 +1,36 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+drc off
+gds readonly yes
+gds rescale no
+
+lef read ../lef/sram.abs.con.lef
+load sram_1rw1r_32_256_8_sky130
+
+select top cell
+expand
+property LEFview ""
+property LEFsymmetry ""
+property LEFclass ""
+
+box position 5um 5um
+getcell pk_sram_1rw1r_32_256_8_sky130
+
+save sram_1rw1r_32_256_8_sky130.mag
+
+gds write output.gds
+
+save
diff --git a/caravel/utils/examples/xor.drc b/caravel/utils/examples/xor.drc
new file mode 100644
index 0000000..14896ee
--- /dev/null
+++ b/caravel/utils/examples/xor.drc
@@ -0,0 +1,42 @@
+# A general XOR script
+# (https://www.klayout.de/forum/discussion/100/xor-vs-diff-tool)
+# This script uses KLayout's DRC language to implement a generic
+# XOR between two layouts. The name of the layouts is given
+# in $a and $b.
+
+# For layout-to-layout XOR with multiple cores, run this script with
+# ./klayout -r xor.drc -rd thr=NUM_CORES -rd top_cell=TOP_CELL_NAME -rd a=a.gds -rd b=b.gds -rd ol=xor.gds -zz
+# (replace NUM_CORES by the desired number of cores to utilize
+
+# enable timing output
+verbose
+
+# set up input a
+a = source($a, $top_cell)
+
+# set up input b
+b = source($b, $top_cell)
+
+$o && report("XOR #{$a} vs. #{$b}", $o)
+$ol && target($ol, $co || "XOR")
+
+$thr && threads($thr) || threads(2)
+
+# collect all common layers
+layers = {}
+[ a.layout, b.layout ].each do |ly|
+ ly.layer_indices.each do |li|
+ i = ly.get_info(li)
+ layers[i.to_s] = i
+ end
+end
+
+# perform the XOR's
+layers.keys.sort.each do |l|
+ i = layers[l]
+ info("--- Running XOR for #{l} ---")
+ x = a.input(l) ^ b.input(l)
+ info("XOR differences: #{x.data.size}")
+ $o && x.output(l, "XOR results for layer #{l}")
+ $ol && x.output(i.layer, i.datatype, i.name)
+end
diff --git a/caravel/utils/examples/xor.sh b/caravel/utils/examples/xor.sh
new file mode 100755
index 0000000..6911062
--- /dev/null
+++ b/caravel/utils/examples/xor.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+: ${1?"Usage: $0 file1.gds file2.gds <top_level_module_name>"}
+: ${2?"Usage: $0 file1.gds file2.gds <top_level_module_name>"}
+: ${3?"Usage: $0 file1.gds file2.gds <top_level_module_name>"}
+
+klayout -r $(dirname $0)/xor.drc -rd top_cell=$3 -rd a=$1 -rd b=$2 -rd thr=$(nproc) -rd ol=xor.gds -zz
diff --git a/caravel/utils/export_pin_labels.sh b/caravel/utils/export_pin_labels.sh
new file mode 100755
index 0000000..c31de09
--- /dev/null
+++ b/caravel/utils/export_pin_labels.sh
@@ -0,0 +1,51 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+: ${1?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${2?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${3?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${4?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${5?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${6?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${7?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${8?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${9?"Usage: $0 file.mag llx_top lly_top urx_top ury_top llx_bottom lly_bottom urx_bottom ury_bottom"}
+: ${PDK_ROOT?"You need to export PDK_ROOT"}
+
+export PDK=sky130A
+
+export MAGIC_MAGICRC=$PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc
+ls $1
+echo $1
+MAGTYPE=mag magic -rcfile $MAGIC_MAGICRC -dnull -noconsole $1 <<EOF
+echo $MAGTYPE
+select top cell
+select area label
+setlabel font FreeSans
+setlabel size 0.7um
+setlabel justify c
+### Rotate Top Labels
+box $2um $3um $4um $5um
+select area
+setlabel size 1.2um
+setlabel rotate 180
+### Rotate Bottom Labels
+box $6um $7um $8um $9um
+select area
+setlabel rotate 90
+###
+save
+EOF
+ls $1
diff --git a/caravel/utils/ext-def-sky130A.sh b/caravel/utils/ext-def-sky130A.sh
new file mode 100644
index 0000000..51ec955
--- /dev/null
+++ b/caravel/utils/ext-def-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./ext-def-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-ext.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "def" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/caravel/utils/ext-gds-sky130A.sh b/caravel/utils/ext-gds-sky130A.sh
new file mode 100644
index 0000000..35071b8
--- /dev/null
+++ b/caravel/utils/ext-gds-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./ext-gds-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-ext.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "gds" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/caravel/utils/ext-mag-sky130A.sh b/caravel/utils/ext-mag-sky130A.sh
new file mode 100644
index 0000000..b57ec31
--- /dev/null
+++ b/caravel/utils/ext-mag-sky130A.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# To call: ./ext-mag-sky130A.sh <target_path> <design_name> <pdk-root> [<output_path> default is <target_path>/results/]
+
+export TARGET_DIR=$1
+export DESIGN_NAME=$2
+export PDK_ROOT=$3
+export OUT_DIR=${4:-$TARGET_DIR/results/}
+export TCL_CALL_PATH=$(pwd)/core_scripts
+
+if ! [[ -d "$OUT_DIR" ]]
+then
+ mkdir $OUT_DIR
+fi
+
+bash ./core_scripts/magic-ext.sh $TARGET_DIR $DESIGN_NAME $PDK_ROOT "mag" "sky130A" $OUT_DIR $TCL_CALL_PATH
diff --git a/caravel/utils/gds2mag-mag.local.sh b/caravel/utils/gds2mag-mag.local.sh
new file mode 100755
index 0000000..110358b
--- /dev/null
+++ b/caravel/utils/gds2mag-mag.local.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+
+$MAGIC -dnull -noconsole << EOF
+#------------------------------------------------------
+drc off
+#---------------------------------gds polygon subcell true
+gds warning default
+gds readonly true
+gds rescale false
+#---------------------------------tech unlock *
+gds read $1
+load ${1%.gds}
+#---------------------------------readspice ${1%.gds}.sp
+cellname delete "(UNNAMED)"
+save ${1%.gds}.mag
+quit -noprompt
+EOF
diff --git a/caravel/utils/gds2mag-mag.sh b/caravel/utils/gds2mag-mag.sh
new file mode 100755
index 0000000..d53b156
--- /dev/null
+++ b/caravel/utils/gds2mag-mag.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOF
+#------------------------------------------------------
+drc off
+#---------------------------------gds polygon subcell true
+gds warning default
+gds readonly true
+gds rescale false
+#---------------------------------tech unlock *
+gds read $1
+load ${1%.gds}
+#---------------------------------readspice ${1%.gds}.sp
+cellname delete "(UNNAMED)"
+save ${1%.gds}.mag
+quit -noprompt
+EOF
diff --git a/caravel/utils/lef2maglef.sh b/caravel/utils/lef2maglef.sh
new file mode 100755
index 0000000..455c4a6
--- /dev/null
+++ b/caravel/utils/lef2maglef.sh
@@ -0,0 +1,60 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/caravel/utils/mag2maglef-mag.sh b/caravel/utils/mag2maglef-mag.sh
new file mode 100755
index 0000000..2934887
--- /dev/null
+++ b/caravel/utils/mag2maglef-mag.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=mag ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole <<EOF
+drc off
+load $1.mag
+select top cell
+expand
+lef write $1.lef -hide
+quit -noprompt
+EOF
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/caravel/utils/mag2maglef-maglef.localrc.sh b/caravel/utils/mag2maglef-maglef.localrc.sh
new file mode 100755
index 0000000..f167252
--- /dev/null
+++ b/caravel/utils/mag2maglef-maglef.localrc.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=maglef ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+$MAGIC -dnull -noconsole <<EOF
+drc off
+load $1.mag
+select top cell
+expand
+lef write $1.lef -hide
+quit -noprompt
+EOF
+
+$MAGIC -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/caravel/utils/mag2maglef-maglef.sh b/caravel/utils/mag2maglef-maglef.sh
new file mode 100755
index 0000000..e70fbd3
--- /dev/null
+++ b/caravel/utils/mag2maglef-maglef.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+
+export PDK_ROOT=~/foss/pdks/open_pdks/sky130;
+export MAGTYPE=maglef ;
+export PDKPATH=$PDK_ROOT/sky130A ;
+export MAGIC=magic
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole <<EOF
+drc off
+load $1.mag
+select top cell
+expand
+lef write $1.lef
+quit -noprompt
+EOF
+
+$MAGIC -rcfile $PDKPATH/libs.tech/magic/current/sky130A.magicrc -dnull -noconsole << EOX
+drc off
+lef read $1.lef
+load $1
+save $1.lef.mag
+#writeall force $1.lef.mag
+
+ # copy GDS properties from the MAG view into the MAGLEF view
+ set gds_properties [list]
+ set fp [open $1.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ foreach line \$mag_lines {
+ if { [string first "string GDS_" \$line] != -1 } {
+ lappend gds_properties \$line
+ }
+ }
+ close \$fp
+ set fp [open $1.lef.mag r]
+ set mag_lines [split [read \$fp] "\n"]
+ set new_mag_lines [list]
+ foreach line \$mag_lines {
+ if { [string first "<< end >>" \$line] != -1 } {
+ lappend new_mag_lines [join \$gds_properties "\n"]
+ }
+ lappend new_mag_lines \$line
+ }
+ close \$fp
+ set fp [open $1.lef.mag w]
+ puts \$fp [join \$new_mag_lines "\n"]
+ close \$fp
+
+
+quit
+EOX
+
+mv -f $1.lef.mag ../maglef/$1.mag
+rm -f $1.lef
diff --git a/caravel/utils/magicDrc b/caravel/utils/magicDrc
new file mode 100755
index 0000000..fa6f783
--- /dev/null
+++ b/caravel/utils/magicDrc
@@ -0,0 +1,888 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2015, 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (C) 2015, 2020 efabless Corporation. All Rights Reserved.
+# filter out most options, so magic Natively sees/handles *only* -T <file>.
+# for-bash\
+ declare -a C ; declare -a N ; export _CE= _NE= _M0= ;\
+ for i in "$@" ; do _M0="$_M0${_M0:+ }\"${i//\"/\\\"}\""; done ;\
+ while getopts "NFT:S:l:P:" o; do \
+ : echo got "optchar $o, with optarg $OPTARG" ;\
+ case "$o" in S) \
+ C+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ case "$o" in P) \
+ C+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ case "$o" in F|N) \
+ C+=(-${o}) ;\
+ continue ; esac ;\
+ case "$o" in l) \
+ C+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ case "$o" in T) \
+ N+=(-${o} "$OPTARG") ;\
+ continue ; esac ;\
+ done ;\
+ shift $((OPTIND-1)) ;\
+ for i in "${C[@]}" ; do _CE="$_CE${_CE:+ }\"${i//\"/\\\"}\""; done ;\
+ for i in "${N[@]}" ; do _NE="$_NE${_NE:+ }\"${i//\"/\\\"}\""; done ;\
+ exec magic -dnull -noconsole "${N[@]}" <"$0"
+# for-magic:
+# magicDrc: run magic-DRC in batch on a .mag file, tabulate/pareto the error counts.
+#
+# magicDrc [-T <techfilePath>] [-S <drcStyleName>] [-P <N> ] [-l FILE_NAME] <magFileName>
+# -T name specific techfile (def .tech extension), passed to magic itself only, overrides tech implied by magFileName
+# -S if given, changes from techfile's default drc style (perhaps "drc(fast)") to named style, for example: -S "drc(full)"
+# -l if given, enumerates EVERY individual error bbox to the FILE_NAME
+# -N if given, do Not use -dereference option of load for topcell (not available in older magics)
+# -F flatten top cell in-memory only, not saved (experimental)
+# -P do crude drc performance measurement. At top-cell, do 'drc find' <N> times and report time per call.
+# Stdout will log a pareto of error type by count regardless.
+#
+# <magFileName>: names a .mag file, the toplevel of the hier. to DRC/pareto
+#
+# Normal magic init. files are STILL sourced: ~/.magicrc and either $CWD/.magicrc or $CWD/magic_setup.
+# (This would NOT happen if -rcfile magic cmd-line option were used).
+#
+# WARNING: Before 8.1.70, *.mag on cmd-line that was only found in cell search path set by .magicrc inits,
+# would FAIL to determine the default tech-file.
+#
+# rb@ef 2015-06-30 author
+# rb 2020-03-11 embed some library functions, to standalone from efabless-opengalaxy env, test via magic-8.2.194
+#
+# magic itself outputs following usage message though -rcfile doesn't appear to work (in some versions):
+# Usage: magic [-g gPort] [-d devType] [-m monType] [-i tabletPort] [-D] [-F objFile saveFile]
+# [-T technology] [-rcfile startupFile | -norcfile][-noconsole] [-nowindow] [-wrapper] [file]
+#
+set Prog "magicDrc"
+
+set argv [eval "list $env(_M0)"] ;# orig. mix of native plus custom args, for logging all args to script
+
+proc usage {args} {
+ if {[llength $args] > 0} {
+ puts "ERROR: ${::Prog}: [join $args]"
+ }
+ puts {usage: [ -T <techfilePath> ] [-S <drcStyleName>] [-N] [-l FILE_NAME] <magFileName>}
+ puts " -T name specific techfile, passed to magic itself only, overrides tech implied by magFileName"
+ puts " -S if given, changes from techfile's default drc style (perhaps \"drc(fast)\") to named style, for example: -S \"drc(full)\""
+ puts " -l if given, enumerates EVERY individual error bbox to the FILE_NAME"
+ puts " -N if given, do not use -dereference option of load for topcell (not available in older magics)"
+ puts " Stdout will log a pareto of error type by count regardless."
+ puts ""
+ puts " Recommend to run in dir with a ./.magicrc (or ./magic_setup) to configure magic's"
+ puts " cell search path, thru addpath statements, to locate all cells."
+}
+
+# optionally hardcode library proc-s (part of site-wide extensions - always available - in context of efabless/open-galaxy)
+# This is to make the script more standalone from efabless environment; but these capabilities should be native to magic.
+
+if {[info command scratchWritable] == {}} {
+ puts "${::Prog}: hardcoding library proc-s..."
+# Replacement for 'cellname list exists CELLNAME', to fix ambiguity for cell "0".
+# For cell "0" test for membership in 'cellname list allcells'.
+#
+# Instead of returning 0 for (non-existent) and cellname for exists,
+# returns regular 0/1 instead for non-existent/exists.
+#
+# Therefore NOT direct replacement for uses of 'cellname list exists CELL'.
+# Requires code changes.
+proc cellnameExists {cell} {
+ expr {$cell ne "0" && [cellname list exists $cell] eq $cell ||
+ $cell eq "0" && [lsearch -exact [cellname list allcells] $cell] > -1}
+}
+
+#
+# scratchWritable [-cleanup] [cellname1 ...] --
+#
+# Turn readonly cells writable in-memory, via redirect to scratch dir.
+# No cellname args: default is to process just all non-writable cells.
+# Explicit cellname arguments: ARE scatchified EVEN if ALREADY writable.
+# Limitation: Explicit named cell created in-mem, never saved, won't scratchify.
+# If just -cleanup: default is to only do cleanup: don't scratchify
+# any cells.
+#
+# -cleanup: Last scratch-dir, if any, and contents are deleted first.
+# No restoring old filepath of cells, save after cleanup will fail.
+#
+# Caller strongly recommended to first do: 'select top cell; expand'
+# to force whole hier. of a topcell to be loaded from disk into memory.
+#
+# This proc does not force expand cells. Before expanded, cells cannot be
+# checked whether writable, and cannot have filepath changed.
+#
+# For batch DRC, for 'drc listall count', every cell in-memory must
+# appear writable. This is the work-around (caller to 1st ensure
+# hier. is loaded): Reset filepath of readonly cells to a scratch dir,
+# make a dummy/empty .mag in scratch dir for each cell. Change cell's
+# writeable flag.
+#
+# Skipped cells:
+# In all cases, cells are skipped if
+# 'cellname filepath' matches ::scratchWritableDir (already scratchified),
+# This proc does NOT try and force expand; it presumes caller forced an expand
+# thus cells are skipped if:
+# 'cellname filepath' is "default" (can mean not expanded yet, or created never saved),
+# 'cellname filepath' is <CELLNAME>.mag, indicates failed expand (unbound).
+# Note: when filepath gives "default" or <CELLNAME>.mag, the writeable check not meaningful.
+#
+# How to scratchify all in-memory cells (still subject to internal skipping):
+# scratchWritable {*}[cellname list allcells]
+#
+# TODO: use a combo of filepath & flags likely can detect created in-mem,
+# and could redirect those too scratch dir if named explicitly.
+#
+# Side-effects:
+# Runs zero or one subprocess, '/bin/mktemp -d' to make a scratch dir.
+# Redirects where newly modified cells would be saved, if they ever are saved.
+# Make's a scratch dir that needs to be cleaned-up.
+# Leaves empty *.mag files in that scratch dir.
+#
+# Uses/requires proc cellnameExists.
+#
+# Same scratch-dir is reused if called multiple times, until next -cleanup.
+#
+# return value: list of cells not processed (skipped) for reasons cited above.
+# Non-existent cells are also skipped but not included in the return list.
+#
+if {![info exists ::scratchWritableDir]} {set ::scratchWritableDir {}}
+if {![info exists ::scratchWritableVerb]} {set ::scratchWritableVerb 0}
+proc scratchWritable {args} {
+ # parse -cleanup option
+ set clean [expr {[lindex $args 0] eq {-cleanup}}]
+ if {$clean} {
+ set args [lrange $args 1 end]
+ }
+
+ # If explicit cells given: don't limit to processing just readOnly cells.
+ set onlyReadonly [expr {$args == {}}]
+
+ # only if no -cleanup, does empty cell list imply all cells
+ set allcell [cellname list allcells]
+ if {!$clean && $args == {}} {
+ set args $allcell
+ }
+
+ # do cleanup
+ if {$clean} {
+ if {$::scratchWritableDir != {} && [file isdir $::scratchWritableDir]} {
+ set files [glob -dir $::scratchWritableDir -- {*.ext} {*.mag}]
+ lappend files $::scratchWritableDir
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: running, file delete $files"
+ }
+ eval {file delete} $files
+ set ::scratchWritableDir {}
+ }
+ }
+
+ # Filter out non-existent or unbound cells.
+ # Optionally filter already writable cells.
+ #
+ # Unbounds result from placements of cells that now don't exist:
+ # fail to expand. This proc does not try and force expand; it
+ # presumes a forced expand was already done by caller (if caller
+ # wished).
+ #
+ # Referenced/used cells are initially unexpanded, not yet even located
+ # located in the search path, 'cellname filepath' returns "default".
+ # If expand fails (not found in search path), then 'cellname filepath'
+ # returns <CELLNAME>.mag, if expand worked, the directory containing
+ # the cell.
+ #
+ # If cell was 'cellname create' made, but never saved also "default".
+ # Such a cell is writable. So filter "default" and <CELLNAME>.mag.
+ set skipped {}
+ set ercell1 {}
+ set docells {}
+ foreach cell $args {
+ # filter (without recording as skipped) non-existent cells.
+ if {![cellnameExists $cell]} { continue }
+
+ # filepath = "default": unexpanded (not loaded from disk),
+ # or created in-mem and never saved (is writable already
+ # though flags won't say so): skip both.
+ # TODO: use a combo of filepath & flags likely can detect created in-mem,
+ # and might be able to redirect them too to scratch dir if named explicitly.
+ set tmppath [cellname list filepath $cell]
+ if {$tmppath eq "default"} {
+ lappend skipped $cell
+ continue
+ }
+
+ # flags not meaningful, until expanded or expand attempted.
+ # After expand attempt (filepath != "default"), and flags
+ # can now be used to determine cell unbound: not available.
+ set flags [cellname list flags $cell]
+ if {[lsearch -exact $flags available] < 0} {
+ lappend ercell1 $cell
+ continue
+ }
+
+ if {$onlyReadonly &&
+ [cellname list writeable $cell] eq "writeable"} {
+ lappend skipped $cell
+ continue
+ }
+ lappend docells $cell
+ }
+
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: skipped cells: $skipped"
+ }
+
+ # don't make a scratch dir if no work to do
+ if {$docells == {}} {
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: scratch-directed 0 cells"
+ }
+ return $skipped
+ }
+
+ # make a scratch dir if needed
+ if {$::scratchWritableDir == {}} {
+ if {[catch {set dir [string trimright [exec /bin/mktemp -d]]} msg]} {
+ error "ERROR: scratchWritable, '/bin/mktemp -d' failed, $msg"
+ }
+ if {![file isdir $dir] || ![file writable $dir]} {
+ error "ERROR: scratchWritable, mktemp gave $dir, not a writable dir"
+ }
+ set ::scratchWritableDir $dir
+ }
+
+ set ercell2 {}
+ set okcell {}
+ set madef 0
+ foreach cell $docells {
+ # Relocate if needed: filepath doesn't already point to the scratch dir).
+ # 'cellname list filepath <cellNm>' -> appears to omit .mag extension,
+ # but disk-file needs the .mag in the path.
+ set trgr [file join $::scratchWritableDir "$cell"] ;# expected "lookup" path
+ set trgw [file join $::scratchWritableDir "$cell.mag"] ;# true "write" disk path
+ set src [cellname list filepath $cell]
+ if {[cellname list filepath $cell] ne $trgr && [cellname list filepath $cell] ne $trgw} {
+
+ # make empty .mag for the cell
+ if {[catch {set outmag [open $trgw w]} msg]} {
+ lappend ercell2 $cell
+ continue
+ }
+ incr madef
+ close $outmag
+
+ # relocate cell to new file
+ cellname list filepath $cell $::scratchWritableDir
+ }
+
+ # make cell writable
+ cellname list writeable $cell true
+ lappend okcell $cell
+ }
+
+ if {$::scratchWritableVerb} {
+ puts "scratchWritable: scratch-directed $madef cells"
+ }
+ if {$ercell1 != {} || $ercell2 != {}} {
+ set pre "ERROR: scratchWritable, "
+ set msg {}
+ if {$ercell1 != {}} {
+ lappend msg "$pre unbound cell(s): $ercell1"
+ }
+ if {$ercell2 != {}} {
+ lappend msg "$pre failed to make .mag for cell(s): $ercell2"
+ }
+ error [join $msg "\n"]
+ }
+ set skipped
+} ;# end proc scratchWritable
+}
+
+# without top-level proc around bulk of script, intermediate error statements don't abort script.
+proc main {argv} {
+
+# process name-value pair options, if any
+set nbrErr 0
+set ndx 0
+set max [llength $argv]
+set extTechOpt {} ;# -T ...
+set enumFilel {} ;# -l ... enum output file
+set variant {} ;# -S ... non-default drc style
+set flatten 0
+set perfN 0 ;# -P <N> do crude DRC perf. test
+set noderef 0 ;# -N disable dereference option of: 'load ... -dereference'
+
+while {$ndx < $max && [string match "-*" [lindex $argv $ndx]]} {
+ set opt [lindex $argv $ndx]
+ incr ndx
+ switch -exact -- $opt {
+ -T {
+ if {$ndx == $max} {
+ usage "missing tech-file argument for -T option"
+ exit 1
+ }
+ set extTechOpt [lindex $argv $ndx]
+ incr ndx
+ }
+ -S {
+ if {$ndx == $max} {
+ usage "missing drcStyle argument for -S option"
+ exit 1
+ }
+ set variant [lindex $argv $ndx]
+ incr ndx
+ }
+ -P {
+ if {$ndx == $max} {
+ usage "missing count argument for -P option"
+ exit 1
+ }
+ set perfN [lindex $argv $ndx]
+ incr ndx
+ }
+ -F {
+ set flatten 1
+ }
+ -N {
+ set noderef 1
+ }
+ -l {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -l option"
+ exit 1
+ }
+ set enumFilel [lindex $argv $ndx]
+ incr ndx
+ if {[catch {set enumOut [open $enumFilel w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFilel' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFilel"
+ }
+ default {
+ usage "unknown option: $opt"
+ exit 1
+ }
+ }
+}
+
+if {$ndx == $max} {
+ usage "missing magFileName argument, the topcell"
+ exit 1
+}
+
+# get cmd-line topcell, minus dir-path; and minus extension IFF ext is .mag
+set topc [file tail [lindex $argv $ndx]] ; incr ndx
+if {[file extension $topc] eq ".mag"} {
+ set topc [file rootname $topc]
+}
+set topcStr $topc
+
+# abort if user supplies extra args.
+if {$ndx != $max} {
+ usage "extra/unspported arg past magFileName, '[lindex $argv $ndx]'"
+ exit 1
+}
+
+# load the techfile
+if {$extTechOpt != ""} {
+ if {![file readable $extTechOpt]} {
+ error "ERROR: ${::Prog}: tech-file \"$extTechOpt\" is not readable."
+ }
+
+ tech load $extTechOpt
+
+ # Verify the cmd-line -T option (if any) is still the current 'tech filename'. If we didn't
+ # explicitly 'tech load' ourselves, the .magicrc or magic.setup might 'tech load' something else.
+ # The 'file join [pwd] ...' makes relative path absolute, but without resolving
+ # all symlinks (which 'file normalize' would do).
+ set techf2 [file join [pwd] [tech filename]]
+ set techf1 [file join [pwd] $extTechOpt]
+ if {$techf1 != $techf2} {
+ error "ERROR: ${::Prog}: failed tech-load \"$techf1\" (tech-filename=\"$techf2\" not a match)"
+ }
+}
+
+# if mag-cell were passed natively on magic cmd-line, this is too late:
+if {$noderef} {
+ load $topc
+} else {
+ load $topc -dereference
+}
+
+# error checks: ensure (1st) cmd-line cellname now in-memory, and is now the current cell
+
+set topcells [cellname list top]
+# filter (UNNAMED)
+set topcells [lsearch -exact -not -all -inline $topcells "(UNNAMED)"]
+# puts "cellname-list-top is: $topcells"
+
+# could use [cellname list flags $topc] and ensure non-null result (list with available),
+# but if it fails (cell not found), it generates unwanted stdout.
+if {[lsearch -exact [cellname list allcells] $topc] < 0} {
+ error "ERROR: ${::Prog}: cmd-line topcell \"$topc\" not in magic's list of allcells."
+}
+
+if {[lsearch -exact $topcells $topc] < 0} {
+ puts "WARNING: ${::Prog}: cmd-line topcell \"$topc\" not in magic's list of topcells: $topcells"
+}
+
+# crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+# WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+set topcw [cellname list window]
+if {$topcw ne $topc} {
+ error "ERROR: ${::Prog}: cmd-line topcell, $topc, is not the current cell, 'cellname list window'=$topcw"
+}
+
+# for topcell, filepath==default doesn't change by expand,
+# indicates unknown cell created in-memory by magic's startup sequence.
+if {[cellnameExists $topc] &&
+ [cellname list filepath $topc] eq "default"} {
+ puts "Search path for cells is \"[path search]\""
+ error "ERROR: ${::Prog}: cmd-line topcell, $topc, auto-created in-memory: not found in cell search path"
+}
+
+if {$flatten} {
+ # delete (UNNAMED) if any.
+ set trg "(UNNAMED)"
+ if {[cellnameExists $trg]} {cellname delete $trg}
+
+ # rename top cell to (UNNAMED)
+ cellname rename $topc $trg
+
+ # now Edit Cell contents are original top cell, but under name (UNNAMED)
+ # flatten Edit-Cell into original top cell name
+ puts "${::Prog}: flattening..."
+ flatten $topc
+
+ # load and edit new version of top cell. This is from in-memory, just making it current-cell.
+ # (So with or without -dereference is expected would have discernable effect by now;
+ # and since it's flattened there are no subcell instances either).
+ if {$noderef} {
+ load $topc
+ } else {
+ load $topc -dereference
+ }
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ error "ERROR: ${::Prog}: assertion failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ }
+
+ # should not be necessary:
+ select top cell
+ edit
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ error "ERROR: ${::Prog}: assertion-2 failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ }
+}
+
+# todo: Need a check for non-existent topcell (though magic reported not-found and auto-created it).
+# todo: We should locate fullpath to topcell on disk to record this in the log.
+#
+# WARNING, magic junkCell, or magic junkDir/junkCell (passing paths to cells that don't exist),
+# generate startup error messages (could not open cell), but magic creates the new cell in memory.
+# No simple way to detect this after the fact. Can walk the cell search path to verify it's on disk.
+# For the non-existent cell, magic also discards the dirpath from the cmd-line arg.
+# If it did exist at that path, magic opens it successfully, despite that dir not in search path.
+# A proper check for implicit create of non-existent cell should account for this effect too.
+
+# write a line with timestamp and all arguments to stdout (log)
+# (magic renames the TCL clock command)
+set clockp clock
+if {[info command $clockp] == {} && [info command orig_clock] != {}} {
+ set clockp orig_clock
+}
+set nowSec [$clockp seconds]
+set timestamp [$clockp format $nowSec -format "%Y-%m-%d.%T.%Z"]
+# Show quoted logged argv here so it's machine readable for replay purposes.
+puts "${::Prog}: timestamp: $timestamp, arguments: $::env(_M0)"
+
+puts "${::Prog}: running drc on topcell: $topcStr"
+puts "${::Prog}: tech-name: [tech name] -version: [tech version] -filename: [tech filename] -lambda [tech lambda]"
+
+# log the cell search path for this run. Emulates format output by plain "path" (but which prints more than one the cell search path).
+puts "Search path for cells is \"[path search]\""
+
+set res {}
+if {$variant != {}} {
+ if {[catch {set res [drc list style $variant]} msg]} {
+ puts "ERROR: ${::Prog}: but CONTINUING, 'drc style $variant' threw error, $msg"
+ }
+} else {
+ if {[catch {set res [drc list style]} msg]} {
+ puts "ERROR: ${::Prog}: but CONTINUING, 'drc list style' threw error, $msg"
+ }
+}
+if {$res != {}} {
+ puts "drc style reports:\n$res"
+}
+
+# just Manhattan is default, turn on euclidean, and log new mode
+drc euclidean on
+drc euclidean
+
+# 1st "select top cell": without it drc-list-count is blank, and error count reduced.
+# May be unnecessary in some cases.
+# WARNING: if topcell locked by another process, default box is NOT set to full top cell without this (as of 8.1.70 or earlier)
+select top cell
+# expand cell cells: scratchify step requires this up front else can't force all cells writable.
+expand
+
+# The expand triggered load of all subcells. Till then allcells may be incomplete.
+set allcells [cellname list allcells]
+# filter (UNNAMED)
+set allcells [lsearch -exact -not -all -inline $allcells "(UNNAMED)"]
+set nbrAllCells [llength $allcells]
+# puts "DEBUG: cellname-list-allcells are: $allcells"
+
+# TODO: do explicit separate unbound check here (don't rely on scratchWritable for this)
+
+# make allcells writable. Can error out:
+# if are unbounds, or couldn't make scratch dir or .mag files.
+set scratch [expr {!$flatten}]
+if {$scratch && [catch {scratchWritable} msg]} {
+ puts stderr "ERROR: ${::Prog}: aborting at scratchWritable due error(s):"
+ error $msg
+}
+
+# Erase all preexisting *.drtcl first. Else when cell transitions from
+# dirty in previous run (leaving *.drtcl), to clean, the old *.drtcl
+# remains.
+# TODO: only delete *.drtcl of cells in 'cellname list allcells'?
+# TODO: move this up, before scratchWritable?
+set files [glob -nocomplain -types {f} -- ./*.drtcl]
+if {$files != {}} {
+ # TODO: detect/report failure details better here?
+ puts "${::Prog}: deleting preexisting *.drtcl"
+ set msg {}
+ set delfail [catch {eval {file delete} $files} msg]
+ set files [glob -nocomplain -types {f} -- ./*.drtcl]
+ if {$delfail || $files != {}} {
+ puts "ERROR: ${::Prog}: failed to clean old ./*.drtcl files. $msg"
+ incr nbrErr
+ }
+}
+
+edit ;# Fails if topcell not writable, should not be not needed post scratchWritable
+
+set outScale [cif scale out]
+
+# "select top cell" and box [view bbox] should be equivalent in
+# placing a box around whole cell extent.
+# The box cmd ALSO prints lambda and micron user-friendly box data,
+# but it prints microns with not enough resolution,
+# (and no option to disable that flawed print out).
+#
+# todo: emulate box output in full, except for higher resolution,
+# here we only scale/print the overall bbox in microns.
+# select top cell ;# paranoid, reset the box to data extents post-expand
+# set bbox [view bbox]
+# set bbs {}
+# foreach oord $bbox {
+# lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+# }
+# puts "outScale: $outScale, view-bbox: $bbox"
+# puts "Root cell box2: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+
+# shouldn't need:
+# drc on
+
+# Want to use 'drc list count' to tell us which cells have errors, so we can
+# run 'drc listall why' on just those cells to enumerate details (which reruns
+# drc again unfortunately).
+
+# For accurate DRC (as of 8.1.70), specifically 'drc list count', need:
+# all-writable cells, then run: 'drc check' & 'drc catchup'.
+# Now we have all writable cells.
+set timeRepeat 1
+if {$perfN > 0} {
+ set timeRepeat $perfN
+}
+set timeres [time {
+ set drcCheckTime1 [time {drc check}]
+ set drcCheckTime2 [time {drc catchup}] } $timeRepeat]
+
+if {$perfN > 0} {
+ puts "perf: ${perfN}X 'drc check','drc catchup': $timeres"
+ puts "perf: last 'drc check' time: $drcCheckTime1"
+ puts "perf: last 'drc catchup' time: $drcCheckTime2"
+ drc statistics
+ drc rulestats
+}
+
+# todo: this 2nd select was in GDS version, test if needed in mag version:
+# 2nd select top cell needed else error count may be reduced (why? bbox does not change due to DRC)
+select top cell
+set outScale [cif scale out]
+set bbox [view bbox]
+set bbs {}
+foreach oord $bbox {
+ lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+}
+puts "outScale(ostyle=[cif list ostyle]): $outScale, view-bbox: $bbox"
+puts "Root cell box: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+# print several native bbox representations:
+box
+
+# listall vs list appear same as of 8.1.70 or earlier.
+# warning: celllist order is not stable, not repeatable; run to run on same data.
+# puts "DEBUG: (drc listall count total) is $drcListCountTot"
+set celllist [drc listall count]
+set celllist [lsearch -not -all -inline -index 0 -exact $celllist "(UNNAMED)"]
+# puts "DEBUG: (drc listall count) is [drc listall count]"
+set drcListCountTot [drc list count total]
+set nbrErrCells [llength $celllist]
+
+# TODO: major problem: 'drc listall why' repeated an every cell, will do subcells
+# multiple times, as many times as their depth in the hier.
+
+# canonicalize order of celllist, move topc to last (if present whatsoever).
+# force our own artificial entry for topc (zero errors) if not present (was clean)
+# puts "DEBUG: celllist before: $celllist"
+set topcPair [lsearch -inline -index 0 -exact $celllist $topc]
+set celllist [lsearch -not -all -inline -index 0 -exact $celllist $topc]
+set celllist [lsort -index 0 -dictionary $celllist]
+if {$topcPair == {}} {
+ # puts "DEBUG: $topc clean, forcing celllist entry for it"
+ set topcPair [list $topc 0]
+}
+lappend celllist $topcPair
+# puts "DEBUG: celllist after: $celllist"
+# puts "DEBUG: adjusted celllist(drc list count) is $celllist"
+
+# loop over celllist
+set doFeedback 1 ;# TODO: add cmd-line option to control this
+
+# collect 'dry listall why' for the cells in 'cell list count' with non-zero errors
+# If 'drc listall why' does report zero (shouldn't since we're only processing cells
+# with non-zero counts), it unavoidably writes to console a No drc errors found message.
+# We don't want such polluting our list of per-cell pareto's, so don't risk running
+# drc why in-line, in-between per-cell paretos.
+array set cell2why [list $topc {}] ;# default at least empty topcell why list
+foreach pair $celllist {
+ if {[lindex $pair 1] < 1} {continue} ;# only happens for topcell if topcell clean
+ set acell [lindex $pair 0]
+
+ # TODO: magic needs a useful error checkable load command.
+ # The 'load' writes errors to console/stdout, but never throws an error,
+ # nor gives a useful return value. i.e. These catch never catch.
+ if {$noderef} {
+ if {[catch {set res [load $acell]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $acell' threw error, $msg"
+ exit 1
+ }
+ } else {
+ if {[catch {set res [load $acell -dereference]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $acell -dereference' threw error, $msg"
+ exit 1
+ }
+ }
+ select top cell ;# paranoid, that without it, drc's are reduced
+
+ # optionally do crude DRC perf. analysis here. Only for top-cell, only if -P <N> option given.
+ set timeRepeat 1
+ if {$perfN > 0 && $topc eq $acell} {
+ set timeRepeat $perfN
+ }
+ set timeres [time {set cell2why($acell) [drc listall why]} $timeRepeat]
+ if {$perfN > 0 && $topc eq $acell} {
+ puts "perf: ${::Prog}: for '$acell', ${perfN}X 'drc listall why': $timeres"
+ }
+}
+
+# done with all magic-specifics here. Shouldn't need scratch dir any longer.
+# If this prints something (generally does), don't want it after the pareto table.
+
+# clean/remove the tmp scratch dir and contents
+# TODO: all fatal errors need to call a cleanup proc that includes this before abort
+if {$scratch && [catch {scratchWritable -cleanup} msg]} {
+ puts "ERROR: ${::Prog}: 'scratchWritable -cleanup' threw error, $msg"
+ incr nbrErr
+}
+
+set gtotal 0
+set gcells 0
+foreach pair $celllist {
+ puts ""
+ set acell [lindex $pair 0]
+ if {![info exists cell2why($acell)]} {
+ puts "ERROR: ${::Prog}: cell: $acell, assertion failed, no drc-why list for 'drc list count' pair: $pair"
+ # exit 1
+ continue
+ }
+ set whys $cell2why($acell)
+
+ # enumerate errors under box, plain "drc why" only reports unique types, no quantities
+ # as-yet-undocumented "drc listall why" gives: {errStr1 {errBox1 ...} errStr2 {errBox1 ...} ... }
+ set pareto {}
+ set total 0
+ set enumTotal 0
+ set types 0
+ set typeDup 0
+ set dups 0
+
+ set fbOut {}
+ # file path for feedback, keep in CWD
+ if {$doFeedback && $fbOut == {}} {
+ set fbOut "./$acell.drtcl"
+ if {![file writable $fbOut] &&
+ ([file exists $fbOut] || ![file writable [file dir $fbOut]])} {
+ puts stderr "ERROR: ${::Prog}: feedback output not writable, $fbOut"
+ incr nbrErr
+ set fbOut {}
+ } elseif {[catch {set outfb [open $fbOut w]} msg]} {
+ puts stderr "ERROR: ${::Prog}: failed to truncate previous feedback output, $fbOut : $msg"
+ incr nbrErr
+ set fbOut {}
+ }
+ }
+ foreach {str boxes} $whys {
+ # sort errors
+ set boxes [lsort -dictionary $boxes]
+
+ # for our pareto, gather data
+ set this [llength $boxes]
+ incr total $this
+ incr types
+ lappend pareto [list $this $str]
+
+ # for enumOut, emulate formatting of $CAD_ROOT/magic/tcl/drc.tcl, which is
+ # not tk pure: fails with complaint about winfo
+ # note: we walk these errors also in order to count/report stats on duplicates, even if not outputing enumerations
+ if {[info exists enumOut]} {
+ if {$types == 1} {
+ puts $enumOut "[join $pair]\n----------------------------------------"
+ }
+ puts $enumOut "${str}\n----------------------------------------"
+ }
+ set lastq {}
+ set thisDup 0
+ foreach quad $boxes {
+ set quadUM {}
+ foreach coord $quad {
+ set valum [expr {$coord * $outScale}]
+ set valumf [format "%.3f" $valum]
+ lappend quadUM "${valumf}um"
+ }
+ set dup [expr {$quad == $lastq}]
+ incr thisDup $dup
+ set line $quadUM
+ if {[info exists enumOut]} {
+ if {$dup} {
+ puts $enumOut "[join $line] #dup"
+ } else {
+ puts $enumOut [join $line]
+ }
+ }
+ if {$fbOut != {}} {
+ set line [join $quadUM]
+ regsub -all -- "(\[\[\"\$\\\\])" $str {\\\1} strdq
+ puts $outfb "[concat box $line]" nonewline
+ puts $outfb " ; feedback add \"$strdq\" medium" nonewline
+ if {$dup} {
+ puts $outfb " ;#dup"
+ } else {
+ puts $outfb ""
+ }
+ }
+
+ incr enumTotal
+ set lastq $quad
+ }
+ if {$thisDup} {
+ incr typeDup
+ incr dups $thisDup
+ }
+ if {[info exists enumOut]} {
+ puts $enumOut "----------------------------------------\n"
+ }
+ }
+
+ if {$fbOut != {}} {
+ close $outfb
+ set outfb {}
+ }
+
+ set pareto [lsort -integer -decreasing -index 0 $pareto]
+ if {$total > 0} {
+ puts "--- #err|description, table for cell: $acell"
+ }
+ foreach pair $pareto {
+ puts "[format {%8d} [lindex $pair 0]] [lindex $pair 1]"
+ }
+ if {$typeDup} {
+ puts "[format {%8d} $dups] total duplicate error(s) among $typeDup error type(s), cell: $acell"
+ }
+ puts "[format {%8d} $total] total error(s) among $types error type(s), cell: $acell"
+ # add to grand-totals
+ incr gcells
+ incr gtotal $total
+
+ # always compare the total from the enum to the pareto as error check
+ if {$total != $enumTotal} {
+ puts "ERROR: ${::Prog}: cell: $acell, assertion failed, pareto vs enum count mismatch: $total != $enumTotal"
+ incr nbrErr
+ }
+}
+
+# TODO: in the summary echo also techfile-full-path and drc-style name?
+# grand totals
+puts "[format {%8d} $nbrErrCells] of $nbrAllCells cell(s) report error(s)"
+puts "[format {%8d} $gtotal] grand-total error(s) across $gcells cell(s)"
+
+# wish to compare the drc-list-count-total to the pareto total.
+# Per te 2014-08-27 : it is not an error.
+# if {$total != $drcListCountTot} {
+# puts "info: ${::Prog}: drc-list-count-total vs drc-listall-why mismatch {drc list count total} gave $drcListCountTot, but {drc listall why} gave $total"
+# }
+
+if {[info exists enumOut]} {
+ close $enumOut
+}
+
+# set celllist4 [drc list count]
+# puts "DEBUG: drc list count0: $celllist0"
+# puts "DEBUG: drc list count1: $celllist1"
+# puts "DEBUG: drc list count2: $celllist2"
+# puts "DEBUG: drc list count3: $celllist3"
+# puts "DEBUG: native (drc list count) is $celllistn"
+# puts "DEBUG: drc list count4: $celllist4"
+
+# todo: implement super-pareto, ranked table of SUM of all DRC errs/counts from ALL cells.
+# (It still would not reflect as-if-flat hierarchical expansion due to repetition of instances).
+
+set nbrErr
+}
+
+# non-zero exit-status on errors, either if thrown by main, or counted and returned by main
+set nbrErr 0
+if {[catch {set nbrErr [main $argv]} msg]} {
+ puts stderr $msg
+ set nbrErr 1
+} elseif {$nbrErr > 0} {
+ puts "ERROR: ${::Prog}: script terminated with errors reported above."
+}
+exit $nbrErr
+
+# for emacs syntax-mode:
+# Local Variables:
+# mode:tcl
+# End:
diff --git a/caravel/utils/magicGdrc b/caravel/utils/magicGdrc
new file mode 100755
index 0000000..88280ee
--- /dev/null
+++ b/caravel/utils/magicGdrc
@@ -0,0 +1,911 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2014, 2015, 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (C) 2014, 2015, 2020 efabless Corporation. All Rights Reserved.
+# send a very-first -T FILE to magic's startup, hide all other args from magic-startup
+# for-bash\
+ export _M0= ;\
+ for i in "$@" ; do _M0="$_M0${_M0:+ }\"${i//\"/\\\"}\""; done ;\
+ case "$1" in -T) tch="$2"; shift; shift; _MARGS="$*" exec magic -dnull -noconsole -T "$tch" <"$0" ;; esac
+# hide next line from magic(tclsh):\
+_MARGS="$*" exec magic -dnull -noconsole <"$0"
+#
+# magicDRC: run magic-DRC in batch on a GDS file, tabulate/pareto the error counts.
+#
+# rb@ef 2014-08-28 author
+# rb 2020-02-19 embed some library functions, to standalone from efabless-opengalaxy env, test via magic-8.2.188
+#
+# todo: support "-" as GDS file arg, to mean GDS from stdin
+#
+
+set ::Prog "magicGdrc"
+set argv [eval "list $env(_M0)"] ;# orig. mix of native plus custom args, for logging all args to script
+# set argv [split $env(_MARGS)] ;# (currently unused)
+
+proc usage {args} {
+ if {[llength $args] > 0} {
+ puts "ERROR: ${::Prog}: [join $args]"
+ }
+ puts {usage: [ -T techfilePath ] [-S <drcStyleName>] [-I <cifIStyleName>] [-km FILE_NAME] [-l FILE_NAME] [-L FILE_NAME] gdsFileName [topCellName]}
+ puts " -T if given, must be very first"
+ puts " -S if given, changes from techfile's default/1st drc style (perhaps \"drc(fast)\") to named style, for example: -S \"drc(full)\""
+ puts " -I if given, changes from techfile's default/1st cifinput style (perhaps \"vendorimport\" or \"import(exact)\") to named style, for example: -I \"import(magic)\""
+ puts " -path-sub do 'gds path subcell yes' (default:no). Make unique subcell for each path: cut #tiles cost of angles."
+ puts " -poly-sub do 'gds polygon subcell yes' (default:no). Make unique subcell for each polygon: cut #tiles cost of angles."
+# gds polygon subcell [yes|no]
+ puts " -pps Short hand, equivalent to giving both: -path-sub -poly-sub"
+ puts ""
+ puts " Error tabulation: By default (slowest, most detail): Report table of counts-by-errorString for all cells."
+ puts " Stdout logs a pareto of error-type by count unless disabled for some/all cells by below; topcell last."
+ puts " -tt Table of counts-by-errorString for ONLY topcell; and just lumped total error count per subcell."
+ puts " -tc Just lumped error counts per cell including topcell (fastest, least detail)."
+ puts " Cells NOT tabulating count-by-errorString can't appear in other output error files: feedback(*.drtcl), -l, -km."
+ puts " For lumped error counts, overlapped error shapes from unique error-types are merged further reducing count."
+ puts ""
+ puts " cell-type +-- (default) --+-- option -tt --+-- option -tc"
+ puts " subcell | count-by-errorString | lumped-error-count | lumped-error-count"
+ puts " topcell | count-by-errorString | count-by-errorString | lumped-error-count"
+ puts ""
+ puts " -km if given, write to FILE_NAME EVERY individual error bbox (MICRONS) in klayout Marker database(XML) format (suggest *.lyrdb)"
+ puts " -l if given, enumerates EVERY individual error bbox (MICRONS) to FILE_NAME, emulates $::CAD_ROOT/magic/tcl/drc.tcl"
+ puts " -L same as -l above, but outputs bbox-es in LAMBDA coordinates, not microns"
+ puts " -nf Do NOT write *.drtcl per-cell feedback files. Can be source-ed in magic and step thru: feedback find."
+ puts ""
+ puts " NOTES: Without explicit tech-file option: the ./.magicrc or ./magic_setup and ~/.magicrc may load a default tech-file."
+ puts " Therefore the tech-file used CAN depend on whether your CWD is ~/design/<CURRENT_DESIGN>/mag when running this script."
+ puts " Since no *.mag are loaded by this script: the cell search path defined by any init files has no impact."
+ puts " Since about 8.3.68, magic may generate error-type \"See error definition in the subcell\". There typically are"
+ puts " redundancies of errors across the hierarchy anyway (but with tech-file err-strings), this seems another form."
+ puts ""
+ puts "example, just list all styles: by causing an error which provokes usage report:"
+ puts " magicGdrc -T /ef/tech/XFAB/EFXH035B/libs.tech/magic/current/EFXH035B.tech"
+ puts "example, same but run in a ~/design/*/mag/ dir, so techfile set by ./.magicrc (else magic's builtin minimum.tech):"
+ puts " magicGdrc"
+ puts "example, run GDS drc, explicit: tech, cif-istyle, drc-style:"
+ puts " magicGdrc -T /ef/tech/SW/EFS8A/libs.tech/magic/current/EFS8A.tech -I vendorimport -S 'drc(full)' /tmp/mytop.gds mytopcell"
+ puts "example, run GDS drc, default tech & styles, write klayout marker database, no per-cell *.drtcl feedback files:"
+ puts " magicGdrc -km /tmp/mytop.lyrdb -nf /tmp/mytop.gds mytopcell"
+ puts "example, same but make subcells for paths & polygons"
+ puts " magicGdrc -km /tmp/mytop.lyrdb -nf -pps /tmp/mytop.gds mytopcell"
+ puts "example, run GDS drc, no feedback (*.drtcl), only lumped/merged err-count for all cells"
+ puts " magicGdrc -tc /tmp/mytop.gds mytopcell"
+ puts "example, run GDS drc, no feedback (*.drtcl), lumped/merged err-count for subcells, detail errors for topcell"
+ puts " magicGdrc -nf -tt /tmp/mytop.gds mytopcell"
+ puts ""
+
+ reportTechFile
+ reportAllStyles
+ puts ""
+
+ if {[llength $args] > 0} {
+ puts "ERROR: ${::Prog}: [join $args]"
+ }
+}
+proc gdsChk {file} {
+ foreach suffix {"" ".gds" ".gds2" ".strm"} {
+ if {[file readable "${file}${suffix}"]} {return 1}
+ }
+ puts "ERROR: ${::Prog}: Cannot open (as-is or with .gds, .gds2, or .strm) to read GDS-II stream from: $file"
+ exit 1
+}
+
+proc reportTechFile {} {
+ puts "${::Prog}: tech-name: [tech name] -version: [tech version] -filename: [tech filename] -lambda [tech lambda]"
+}
+
+# query currently loaded tech-file for styles the user might need for -I -S options
+# Suggest a bad tech-file if none are found or errors thrown.
+# Used after finding error in -I -S options, and probably should add it to the usage.
+proc reportAllStyles {} {
+ set errs {}
+ if {[catch {set allstyle [cif listall istyle]} msg]} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? failed to 'cif listall istyle', $msg"
+ } elseif {$allstyle == {}} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? no cifinput styles found by 'cif listall istyle'"
+ } else {
+ puts "info: ${::Prog}: cifinput styles available: $allstyle"
+ }
+ if {[catch {set allstyle [drc listall style]} msg]} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? failed to 'drc listall style', $msg"
+ } elseif {$allstyle == {}} {
+ lappend errs "ERROR: ${::Prog}: bad tech-file? no drc styles found by 'drc listall style'"
+ } else {
+ puts "info: ${::Prog}: drc styles available: $allstyle"
+ }
+ if {$errs != {}} {
+
+ }
+ return [llength $errs]
+}
+
+# optionally hardcode library proc-s (part of site-wide extensions - always available - in context of efabless/open-galaxy)
+# This is to make the script more standalone from efabless environment; but these capabilities should be native to magic.
+
+if {[info command unbounds] == {}} {
+ puts "${::Prog}: hardcoding library proc-s..."
+# Replacement for 'cellname list exists CELLNAME', to fix ambiguity for cell "0".
+# For cell "0" test for membership in 'cellname list allcells'.
+#
+# Instead of returning 0 for (non-existent) and cellname for exists,
+# returns regular 0/1 instead for non-existent/exists.
+#
+# Therefore NOT direct replacement for uses of 'cellname list exists CELL'.
+# Requires code changes.
+proc cellnameExists {cell} {
+ expr {$cell ne "0" && [cellname list exists $cell] eq $cell ||
+ $cell eq "0" && [lsearch -exact [cellname list allcells] $cell] > -1}
+}
+
+# Walk allcells to get/return list of cellNames that are unbound.
+# Only use this after: 'select top cell; expand' to expand whole hierarchy.
+#
+# foreach CELL in 'cellname list allcells':
+# if flags says available : it's Bound, goto next cell.
+# if filepath is "default", try to expand the cell.
+# if still "default"**: cell made by "cellname create", never saved, goto next.
+# if filepath is CELL.mag, check for "available" flags, if none: Unbound.
+# else cell is bound.
+# **: should never get there
+proc unbounds {} {
+ set allcells [cellname list allcells]
+ # filter (UNNAMED)
+ set allcells [lsearch -exact -not -all -inline $allcells "(UNNAMED)"]
+ # set nbrAllCells [llength $allcells]
+ set ercell {}
+ foreach cell $allcells {
+ # filter (without recording as skipped) non-existent cells.
+ if {![cellnameExists $cell]} { continue }
+
+ # filepath = "default": unexpanded (not loaded from disk),
+ # or created in-mem and never saved (is writable already
+ # though flags won't say so): skip both.
+ # TODO: use a combo of filepath & flags likely can detect created in-mem
+ set tmppath [cellname list filepath $cell]
+ if {$tmppath eq "default"} {
+ lappend skipped $cell
+ continue
+ }
+
+ # flags not meaningful, until expanded or expand attempted.
+ # After expand attempt (filepath != "default"), and flags
+ # can now be used to determine cell unbound: not available.
+ set flags [cellname list flags $cell]
+ if {[lsearch -exact $flags available] < 0} {
+ lappend ercell $cell
+ continue
+ }
+ }
+ set ercell ;# return list of unbound cells, if any
+}
+}
+
+# without top-level proc around bulk of script, intermediate error statements don't abort script.
+proc main {argv} {
+
+set mlen [llength $argv]
+
+# process name-value pair options, if any
+set nbrErr 0
+set ndx 0
+set max [llength $argv]
+set extTechOpt {} ;# -T ... but not used here
+set enumFilel {} ;# -l ... enum output file
+set enumFileL {} ;# -L ... enum output file
+set enumFileKm {} ;# -km ... enum output file
+set variant {} ;# -S ... non-default drc style
+set istyle {} ;# -I ... non-default cifinput style
+set doFeedback 1 ;# -nf sets to 0: Do not write *.drtcl per-cell feedback files.
+set pathSub 0 ;# -path-sub ... do 'gds path subcell yes'
+set polySub 0 ;# -poly-sub ... do 'gds polygon subcell yes'
+set subcellTab 1 ;# -tt, -tc both turn OFF subcell count-by-error report
+set topcellTab 1 ;# -tc turns OFF topcell count-by-error report
+set flatten 0
+while {$ndx < $max && [string match "-*" [lindex $argv $ndx]]} {
+ set opt [lindex $argv $ndx]
+ incr ndx
+ switch -exact -- $opt {
+ -T {
+ if {$ndx != 1} {
+ usage "-T option must very 1st (here was #$ndx)"
+ exit 1
+ }
+ if {$ndx == $max} {
+ usage "missing tech-file argument for -T option"
+ exit 1
+ }
+ set extTechOpt [lindex $argv $ndx] ;# unused
+ incr ndx
+ }
+ -S {
+ if {$ndx == $max} {
+ usage "missing drcStyle argument for -S option"
+ exit 1
+ }
+ set variant [lindex $argv $ndx]
+ incr ndx
+ }
+ -I {
+ if {$ndx == $max} {
+ usage "missing cifinput-style argument for -I option"
+ exit 1
+ }
+ set istyle [lindex $argv $ndx]
+ incr ndx
+ }
+ -F { set flatten 1}
+ -nf { set doFeedback 0 }
+ -path-sub { set pathSub 1}
+ -poly-sub { set polySub 1}
+ -pps { set pathSub 1; set polySub 1}
+ -tt { set subcellTab 0 ; set topcellTab 1}
+ -tc { set subcellTab 0 ; set topcellTab 0 }
+ -km {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -km option"
+ exit 1
+ }
+ set enumFileKm [lindex $argv $ndx]
+ incr ndx
+ }
+ -l {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -l option"
+ exit 1
+ }
+ set enumFilel [lindex $argv $ndx]
+ incr ndx
+ if {[catch {set enumOut [open $enumFilel w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFilel' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFilel"
+ }
+ -L {
+ if {$ndx == $max} {
+ usage "missing outputFile argument for -L option"
+ exit 1
+ }
+ set enumFileL [lindex $argv $ndx]
+ incr ndx
+ if {[catch {set enumOutL [open $enumFileL w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFileL' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFileL"
+ }
+ default {
+ usage "unknown option: $opt"
+ exit 1
+ }
+ }
+}
+
+if {$ndx == $max} {
+ usage {Insufficient number of arguments, need gdsFileName [topCellName]}
+ exit 1
+}
+
+set gdsf [lindex $argv $ndx] ; incr ndx
+set topc {}
+set topcStr "(AUTO)"
+if {$ndx < $max} {
+ set topc [lindex $argv $ndx] ; incr ndx
+ set topcStr $topc
+}
+# error if extra options (not understood, something is wrong):
+if {$ndx < $max} {
+ error "ERROR: ${::Prog}: after gdsFile=\"$gdsf\", topcell=\"$topc\" found unsupported extra arguments: [lrange $argv $ndx end]"
+}
+# ndx no longer used for argv position from here
+
+gdsChk $gdsf
+
+# warning on combo of -tc & -km. If -km ok, open its output file.
+if {$enumFileKm ne {}} {
+ if {! $topcellTab} {
+ puts "WARNING: ${::Prog}: with -tc cannot (-km) write klayout-marker-db"
+ } else {
+ if {[catch {set enumOutKm [open $enumFileKm w]} msg]} {
+ error "ERROR: ${::Prog}: failed to open-for-write '$enumFileKm' threw error, $msg"
+ }
+ puts "${::Prog}: enumerating each error bbox to: $enumFileKm"
+ }
+}
+
+# write a line with timestamp and all arguments to stdout (log)
+# (magic renames the TCL clock command)
+set clockp clock
+if {[info command $clockp] == {} && [info command orig_clock] != {}} {
+ set clockp orig_clock
+}
+set nowSec [$clockp seconds]
+set timestamp [$clockp format $nowSec -format "%Y-%m-%d.%T.%Z"]
+# TODO: quote logged argv here as needed so it's machine readable for replay purposes.
+puts "${::Prog}: timestamp: $timestamp, arguments: $argv"
+
+# just Manhattan is default, turn on euclidean, and log new mode
+drc euclidean on
+drc euclidean
+
+# 8.1.83 this worked:
+# drc off; gds drccheck no; gds read ... ; load topcell; select top cell; expand; drc check; drc update; drc listall count
+# By 8.2.64, that fails, the 'drc listall count' reports errors only in the top-cell, no subcells.
+# 8.1.83 & 8.2.193 this works (gds drccheck defaults to on anyway):
+# drc off; gds drccheck yes; gds read ... ; load topcell; select top cell; expand; drc check; drc update; drc listall count
+#
+# But are we properly avoiding redundant drc runs?
+#
+# turn off background checker. We'll invoke checks explicitly.
+drc off
+gds drccheck yes
+puts "drc status (whether background checking enabled) is: [drc status]"
+puts "gds drccheck (whether gds-read marks new cells as need-drc) is: [gds drccheck]"
+
+# set user's drc style; set user's cifinput istyle
+# These are back-to-back without intervening status messages.
+# If both wrong their errors are back-to-back.
+set res {}
+set res [drc list style]
+if {$variant != {}} {
+ set allstyle [drc listall style]
+ set ndx [lsearch -exact $allstyle $variant]
+ if {$ndx < 0} {
+ puts "ERROR: ${::Prog}: drc style '$variant' not one of those available: $allstyle"
+ incr nbrErr
+ } else {
+ set res [drc list style $variant]
+ }
+}
+set res2 [cif list istyle]
+if {$istyle != {}} {
+ set allstyle [cif listall istyle]
+ set ndx [lsearch -exact $allstyle $istyle]
+ if {$ndx < 0} {
+ puts "ERROR: ${::Prog}: istyle '$istyle' not one of those available: $allstyle"
+ incr nbrErr
+ } else {
+ set res2 [cif istyle $istyle]
+ }
+}
+if {$res != {}} {
+ puts "drc style reports:\n$res"
+}
+if {$res2 != {}} {
+ puts "cif istyle reports:\n$res2"
+}
+
+# gds {path,polygon} subcell yes
+if {$pathSub != 0} { gds path subcells yes }
+puts "gds path subcells: [gds path subcells]"
+if {$polySub != 0} { gds polygon subcells yes }
+puts "gds polygon subcells: [gds polygon subcells]"
+
+# todo: this catch never happens. Need nicer error check of 'gds read' somehow. Can check for zero-sized file?
+# if use /dev/null for example, it prints its own error message, but no throw, no useful return value.
+puts "doing: gds read $gdsf ..."
+if {[catch {set res [gds read $gdsf]} msg]} {
+ puts "ERROR: ${::Prog}: 'gds read $gdsf' threw error, $msg"
+ incr nbrErr
+}
+# nothing useful:
+# puts "gds-read res: $res"
+
+set topcells [cellname list top]
+set allcells [cellname list allcells]
+# puts "cellname-list-top from GDS is: $topcells"
+# puts "cellname-list-allcells from GDS are: $allcells"
+# filter (UNNAMED)
+set topcells [lsearch -exact -not -all -inline $topcells "(UNNAMED)"]
+set allcells [lsearch -exact -not -all -inline $allcells "(UNNAMED)"]
+set nbrAllCells [llength $allcells]
+
+if {$topcells == {}} {
+ puts "ERROR: ${::Prog}: GDS-read did not report any useful cell name(s) found."
+ incr nbrErr
+}
+
+if {$nbrErr > 0} {
+ return $nbrErr ;# outside of main, we print termination with errors message
+}
+
+if {$topc == {}} {
+ # try and infer topcell from cellname-list-top.
+ # presume its list of cells not placed anywhere else.
+ # todo: test with "library" GDS having more than one topcell
+ # here we just take the last entry
+ set topc [lindex $topcells end]
+ set topcStr $topc
+ puts "WARNING: auto-picked top-cell \"$topc\"; the topcells inferred from GDS are: $topcells"
+} else {
+ # verify input topc argument exists in GDS read result
+ set ndx [lsearch -exact $allcells $topc]
+ if {$ndx < 0} {
+ puts "ERROR: ${::Prog}: top-cell name: $topc, not found in GDS"
+ puts "info: top cells inferred from GDS are: $topcells"
+ puts "info: all cells inferred from GDS are: $allcells"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+}
+
+puts "${::Prog}: running drc on -gds: $gdsf -topcell: $topcStr"
+reportTechFile
+
+# todo: need to error check load command somehow (no useful return value).
+# it can fail with error message (in log) like:
+# File dne.mag couldn't be found
+# Creating new cell
+if {[catch {set res [load $topc]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $topc' threw error (maybe cellName not found in GDS?), $msg"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+}
+# nothing useful:
+# puts "load $topc res: $res"
+
+if {$flatten} {
+ # delete (UNNAMED) if any.
+ set trg "(UNNAMED)"
+ if {[cellnameExists $trg]} {cellname delete $trg}
+
+ # rename top cell to (UNNAMED)
+ cellname rename $topc $trg
+
+ # now Edit Cell contents are original top cell, but under name (UNNAMED)
+ # flatten Edit-Cell into original top cell name
+ puts "${::Prog}: flattening..."
+ flatten $topc
+
+ # load and edit new version of top cell
+ load $topc
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ puts "ERROR: ${::Prog}: assertion failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+
+ # should not be necessary:
+ select top cell
+ edit
+
+ # crude way even in batch to determine the "current" cell; perhaps not yet the "Edit" cell
+ # WARNING, if topcell locked elsewhere or not writable, it can't become the "Edit" cell.
+ set topcw [cellname list window]
+ if {$topcw ne $topc} {
+ puts "ERROR: ${::Prog}: assertion-2 failed, post-flatten, $topc, is not the current cell, 'cellname list window'=$topcw"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+}
+
+# Erase all preexisting *.drtcl first. Else when cell transitions from
+# dirty in previous run (leaving *.drtcl), to clean, the old *.drtcl
+# remains.
+# TODO: only delete *.drtcl of cells in 'cellname list allcells'?
+if {$doFeedback} {
+ set files [glob -nocomplain -types {f} -- ./*.drtcl]
+ if {$flatten} {
+ # only delete topcell's .drtcl in flatten mode, if there is one
+ set files [lsearch -all -inline -exact $files ./$topc.drtcl]
+ }
+ if {$files != {}} {
+ # TODO: detect/report failure details better here?
+ puts "${::Prog}: deleting preexisting *.drtcl"
+ set msg {}
+ set delfail [catch {eval {file delete} $files} msg]
+ set files [glob -nocomplain -types {f} -- ./*.drtcl]
+ if {$delfail || $files != {}} {
+ puts "ERROR: ${::Prog}: failed to clean old ./*.drtcl files. $msg"
+ incr nbrErr
+ }
+ }
+}
+
+# 1st "select top cell": without it drc-list-count is blank, and error count reduced.
+select top cell
+
+set bbox0 [view bbox]
+set outScale [cif scale out]
+
+# set bbox1 [view bbox]
+
+# "select top cell" and box [view bbox] should be equivalent in
+# placing a box around whole cell extent.
+# The box cmd ALSO prints lambda and micron user-friendly box data,
+# but it prints microns with not enough resolution,
+# (and no option to disable that flawed print out).
+#
+# todo: emulate box output in full, except for higher resolution,
+# here we only scale/print the overall bbox in microns.
+set bbs {}
+foreach oord $bbox0 {
+ lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+}
+puts "info: outScale: [format "%.6f" $outScale], view-bbox: $bbox0"
+puts "info: Root cell box: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+
+drc check
+drc catchup
+drc statistics
+drc rulestats
+# puts "doing plain: drc count"
+drc count
+
+# 2nd select top cell needed else error count may be reduced (why? bbox does not change due to DRC)
+select top cell
+
+set celllist [drc listall count]
+set drcListCountTot [drc list count total]
+# puts stdout "(drc listall count) is << " nonewline; puts stdout [list $celllist] nonewline; puts " >>"
+# puts stdout "(drc list count) is << " nonewline; puts stdout [list [drc list count]] nonewline; puts " >>"
+# puts stdout "(drc list count total) is << " nonewline; puts stdout [list $drcListCountTot] nonewline; puts " >>"
+# puts stdout "(drc listall count total) is << " nonewline; puts stdout [list [drc listall count total]] nonewline; puts " >>"
+# puts stdout "(drc list why) is << " nonewline; puts stdout [list [drc list why]] nonewline; puts " >>"
+# puts stdout "(drc listall why) is << " nonewline; puts stdout [list [drc listall why]] nonewline; puts " >>"
+
+set bbox2 [view bbox]
+if {$bbox2 != $bbox0} {
+ set bbs {}
+ foreach oord $bbox2 {
+ lappend bbs [format "%.3f" [expr {$outScale * $oord}]]
+ }
+ puts "info: outScale: [format "%.6f" $outScale], view-bbox: $bbox2"
+ puts "info: Root cell box2: ([lindex $bbs 0] [lindex $bbs 1]), ([lindex $bbs 2] [lindex $bbs 3])"
+}
+
+
+# canonicalize order of celllist, move topc to last (if present whatsoever).
+# force our own artificial entry for topc (zero errors) if not present (was clean)
+# puts "celllist before: $celllist"
+set nbrErrCells [llength $celllist]
+set topcPair [lsearch -inline -index 0 -exact $celllist $topc]
+set celllist [lsearch -not -all -inline -index 0 -exact $celllist $topc]
+set celllist [lsort -index 0 -dictionary $celllist]
+if {$topcPair == {}} {
+ # puts "info: ${::Prog}: $topc clean, forcing celllist entry for it"
+ set topcPair [list $topc 0]
+}
+lappend celllist $topcPair
+# puts stdout "adjusted celllist(drc list count) is << " nonewline; puts stdout $celllist nonewline; puts " >>"
+
+array set kmErr2catNm {}
+array set kmErr2catDesc {}
+array set kmCell2item {}
+if {$celllist != {} && [info exists enumOutKm]} {
+ # Header example of .lyrdb klayout Marker format
+ # <?xml version="1.0" encoding="utf-8"?>
+ # <report-database>
+ # <description>Diff of 'x.gds, Cell RINGO' vs. 'x.gds[1], Cell INV2'</description>
+ # <original-file/>
+ # <generator/>
+ # <top-cell>RINGO</top-cell>
+ # <tags>
+ # <tag>
+ # <name>red</name>
+ # <description>Red flag</description>
+ # </tag>
+ # ...
+ # </tags>
+
+ puts $enumOutKm {<?xml version="1.0" encoding="utf-8"?><report-database>}
+ puts $enumOutKm "<description>$topc DRC timestamp: $timestamp, arguments: $argv</description>"
+ puts $enumOutKm {<original-file/><generator/>}
+ puts $enumOutKm "<top-cell>$topc</top-cell>"
+ puts $enumOutKm {<tags/>}
+ puts $enumOutKm {<cells>}
+
+ # multiple <cells>...</cells> sections do accumulate, but cells and categories need
+ # to be defined before use in an item (specific error), and we know cell names here,
+ # so declare all cells to klayout here.
+ #
+ # Cell-specific header of klayout marker file
+ # <cell>
+ # <name>CELLNAME1</name>
+ # <variant>1</variant> (don't need)
+ # </cell>
+ #
+ foreach pair $celllist {
+ set acell [lindex $pair 0]
+
+ # for -tt, no subcell error-detail: don't write subcells in <cells>...</cells> section.
+ if {$acell ne $topc && ! $subcellTab} { continue }
+
+ puts $enumOutKm " <cell><name>$acell</name></cell>"
+ set kmCell2item($acell) {}
+ }
+ puts $enumOutKm {</cells>}
+}
+
+# loop over celllist
+set gtotal 0
+set gcells 0
+set lumpedHeader 0
+foreach pair $celllist {
+ set acell [lindex $pair 0]
+ set acount [lindex $pair 1]
+
+ if {$acell ne $topc && ! $subcellTab} {
+ if {! $lumpedHeader} {
+ puts "--- #err|cell, lumped total counts"
+ set lumpedHeader 1
+ }
+ puts "[format {%8d} $acount] $acell"
+ incr gcells
+ incr gtotal $acount
+ continue
+ }
+ if {$acell eq $topc && ! $topcellTab} {
+ if {! $lumpedHeader} {
+ puts "--- #err|cell, lumped total counts"
+ set lumpedHeader 1
+ }
+ puts "[format {%8d} $acount] $acell"
+ incr gcells
+ incr gtotal $acount
+ continue
+ }
+ puts ""
+
+ # todo: need useful error check of load command
+ if {[catch {set res [load $acell]} msg]} {
+ puts "ERROR: ${::Prog}: 'load $acell' threw error, $msg"
+ return [incr nbrErr] ;# outside of main, we print termination with errors message
+ }
+
+ # instead use quiet version for per-cell selects
+ select top cell
+
+ set drcListCountTot [drc listall count total]
+
+ # enumerate errors under box, plain "drc why" only reports unique types, no quantities
+ # as-yet-undocumented "drc listall why" will give: {errStr1 {errBox1 ...} errStr2 {errBox1 ...} ... }
+ set pareto {}
+ set total 0
+ set enumTotal 0
+ set types 0
+ set typeDup 0
+ set dups 0
+
+ set fbOut {}
+ if {$acount != 0} {
+ # file path for feedback, keep in CWD
+ if {$doFeedback && $fbOut == {}} {
+ set fbOut "./$acell.drtcl"
+ if {![file writable $fbOut] &&
+ ([file exists $fbOut] || ![file writable [file dir $fbOut]])} {
+ puts stderr "ERROR: ${::Prog}: feedback output not writable, $fbOut"
+ incr nbrErr
+ set fbOut {}
+ } elseif {[catch {set outfb [open $fbOut w]} msg]} {
+ puts stderr "ERROR: ${::Prog}: failed to truncate previous feedback output, $fbOut : $msg"
+ incr nbrErr
+ set fbOut {}
+ }
+ }
+
+ foreach {str boxes} [drc listall why] {
+ # sort errors
+ set boxes [lsort -dictionary $boxes]
+ # for our pareto, gather data
+ set this [llength $boxes]
+ incr total $this
+ incr types
+ lappend pareto [list $this $str]
+
+ # for enumOut, emulate formatting of $CAD_ROOT/magic/tcl/drc.tcl, which is
+ # not tk pure: fails with complaint about winfo
+ # note: we walk these errors also in order to count/report stats on duplicates, even if not outputing enumerations
+ if {[info exists enumOut]} {
+ if {$types == 1} {
+ puts $enumOut "[join $pair]\n----------------------------------------"
+ }
+ puts $enumOut "${str}\n----------------------------------------"
+ }
+ if {[info exists enumOutL]} {
+ if {$types == 1} {
+ puts $enumOutL "[join $pair]\n----------------------------------------"
+ }
+ puts $enumOutL "${str}\n----------------------------------------"
+ }
+ if {[info exists enumOutKm]} {
+ # category names must be declared all together up front before use in items
+ # so we only store their names (error strings) and error detail (items)
+ # to dump after all cells and errors are processed.
+ # TODO: Only quote catName in item if embeds dot, instead of full-time
+ # TODO: test klayout handles literal (non-entity) single-quote in double-quoted name
+ set strKmNm $str
+ set strKmDesc $str
+ regsub -all -- {&} $strKmDesc {\&} strKmDesc ;# perhaps not needed; just in case
+ regsub -all -- {<} $strKmDesc {\<} strKmDesc ;# description does not have such bug, so use correct entity
+ regsub -all -- {>} $strKmDesc {\>} strKmDesc ;# perhaps not needed; just in case
+ regsub -all -- {&} $strKmNm {-and-} strKmNm ;# perhaps not needed; just in case
+ regsub -all -- {>} $strKmNm {-gt-} strKmNm ;# perhaps not needed; just in case
+ regsub -all -- {<} $strKmNm {-lt-} strKmNm ;# catName klayout bug: info win truncates at '<' as < entity
+ regsub -all -- "\"" $strKmNm {'} strKmNm ;# we dqoute each catNm in item, so change embedded double to single
+ set kmErr2catNm($str) $strKmNm
+ set kmErr2catDesc($str) $strKmDesc
+ #
+ # example klayout Marker format, header of one item (one error instance)
+ # <item>
+ # <tags/> (don't need?)
+ # <image/> (don't need?)
+ # <category>'DRC-MSG-STR'</category> (cat1.cat2 path delimit by dot: names with dot need single|double quotes)
+ # <cell>RINGO:1</cell> (don't need :N variant suffix)
+ # <visited>false</visited> (optional? start with false?)
+ # <multiplicity>1</multiplicity> (not boolean, if error "represents" more that are NOT enumerated)
+ # <values> ... </values>
+ # </item>
+
+ set itemStr "<item><category>\"$strKmNm\"</category><cell>$acell</cell><values>"
+ }
+ set lastq {}
+ set thisDup 0
+ foreach quad $boxes {
+ set quadUM {}
+ set kmBoxUM {}
+ foreach coord $quad {
+ set valum [expr {$coord * $outScale}]
+ set valumf [format "%.3f" $valum]
+ lappend quadUM "${valumf}um"
+ lappend kmBoxUM ${valumf}
+ }
+ set dup [expr {$quad == $lastq}]
+ incr thisDup $dup
+ set line $quadUM
+ if {[info exists enumOut]} {
+ if {$dup} {
+ puts $enumOut "[join $line] #dup"
+ } else {
+ puts $enumOut [join $line]
+ }
+ }
+ if {[info exists enumOutL]} {
+ if {$dup} {
+ puts $enumOutL "$quad #dup"
+ } else {
+ puts $enumOutL $quad
+ }
+ }
+ if {[info exists enumOutKm]} {
+ # <value>text: 'item: polygon'</value> (text is optional? Repeat the box coordinates here in um?)
+ # <value>polygon: (1.4,1.8;-1.4,1.8;-1.4,3.8;1.4,3.8)</value>
+ # <value>box: (1.4,1.8;-1.4,3.8)</value>
+ # </values>
+ set kmItem $itemStr
+ append kmItem " <value>box: ([lindex $kmBoxUM 0],[lindex $kmBoxUM 1];[lindex $kmBoxUM 2],[lindex $kmBoxUM 3])</value>"
+ if {$dup} {
+ append kmItem " <value>text: 'dup'</value>"
+ }
+ append kmItem " </values></item>"
+ lappend kmCell2item($acell) $kmItem
+ }
+ if {$fbOut != {}} {
+ set line [join $quadUM]
+ regsub -all -- "(\[\[\"\$\\\\])" $str {\\\1} strdq
+ puts $outfb "[concat box $line]" nonewline
+ puts $outfb " ; feedback add \"$strdq\" medium" nonewline
+ if {$dup} {
+ puts $outfb " ;#dup"
+ } else {
+ puts $outfb ""
+ }
+ }
+
+ incr enumTotal
+ set lastq $quad
+ }
+ if {$thisDup} {
+ incr typeDup
+ incr dups $thisDup
+ }
+ if {[info exists enumOut]} {
+ puts $enumOut "----------------------------------------\n"
+ }
+ if {[info exists enumOutL]} {
+ puts $enumOutL "----------------------------------------\n"
+ }
+ }
+ }
+
+ if {$fbOut != {}} {
+ close $outfb
+ set outfb {}
+ }
+
+ set pareto [lsort -integer -decreasing -index 0 $pareto]
+ if {$total > 0} {
+ puts "--- #err|description, table for cell: $acell"
+ }
+ foreach pair $pareto {
+ puts "[format {%8d} [lindex $pair 0]] [lindex $pair 1]"
+ }
+ if {$typeDup} {
+ puts "[format {%8d} $dups] total duplicate error(s) among $typeDup error type(s), cell: $acell"
+ }
+ puts "[format {%8d} $total] total error(s) among $types error type(s), cell: $acell"
+ # add to grand-totals
+ incr gcells
+ incr gtotal $total
+
+ # always compare the total from the enum to the pareto as error check
+ if {$total != $enumTotal} {
+ puts "ERROR: ${::Prog}: cell: $acell, internal error, pareto vs enum count mismatch: $total != $enumTotal"
+ incr nbrErr
+ }
+ # wish to compare the drc-list-count-total to the pareto total.
+ # Per te 2014-08-27 : it is not an error.
+ if {$total != $drcListCountTot} {
+ # puts "info: ${::Prog}: cell: $acell, drc-list-count-total vs drc-listall-why mismatch {drc list count total} gave $drcListCountTot, but {drc listall why} gave $total"
+ }
+}
+
+# grand totals
+puts "[format {%8d} $nbrErrCells] of $nbrAllCells cell(s) report error(s)"
+puts "[format {%8d} $gtotal] grand-total error(s) across $gcells cell(s)"
+
+if {[info exists enumOut]} {
+ close $enumOut
+}
+if {[info exists enumOutL]} {
+ close $enumOutL
+}
+if {[info exists enumOutKm]} {
+ # declare all category names and descriptions, note '<' in name vs description are represented differently
+ #
+ # <categories><category><name>layerN width -lt- 1.0um</name>
+ # <description>layerN width < 1.0um</description></category>
+ # <category> ... </category></categories>
+ #
+ puts $enumOutKm "<categories>"
+ foreach errStr [array names kmErr2catNm] {
+ set nm $kmErr2catNm($errStr)
+ set desc $kmErr2catDesc($errStr)
+ puts $enumOutKm " <category><name>$nm</name><description>$desc</description></category>"
+ }
+ puts $enumOutKm "</categories>"
+
+ # dump all items (after all cells and all categories have been defined up front)
+ puts $enumOutKm "<items>"
+ foreach {acell items} [array get kmCell2item] {
+ foreach item $items {
+ puts $enumOutKm $item
+ }
+ }
+ puts $enumOutKm "</items>"
+
+ # footer example .lyrdb klayout Marker file
+ # </report-database>
+ puts $enumOutKm {</report-database>}
+ close $enumOutKm
+}
+# todo: implement super-pareto, ranked table of SUM of all DRC errs/counts from ALL cells.
+# (It still would not reflect as-if-flat hierarchical expansion due to repetition of instances).
+
+set nbrErr ;# return value
+} ;# end main
+
+# non-zero exit-status on errors, either if thrown by main, or counted and returned by main
+set nbrErr 0
+if {[catch {set nbrErr [main $argv]} msg]} {
+ puts stderr $msg
+ set nbrErr 1
+} elseif {$nbrErr > 0} {
+ puts "ERROR: ${::Prog}: script terminated with errors reported above."
+}
+exit $nbrErr
+
+# for emacs syntax-mode:
+# Local Variables:
+# mode:tcl
+# End:
diff --git a/caravel/utils/parse_klayout_xor_log.py b/caravel/utils/parse_klayout_xor_log.py
new file mode 100644
index 0000000..d93fb2c
--- /dev/null
+++ b/caravel/utils/parse_klayout_xor_log.py
@@ -0,0 +1,43 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import re
+
+parser = argparse.ArgumentParser(
+ description='extracts the total xor differnces from an xor log')
+
+parser.add_argument('--log_file', '-l',required=True,
+ help='log file')
+
+parser.add_argument('--output', '-o', required=True,
+ help='output file to store results')
+
+args = parser.parse_args()
+log_file_name = args.log_file
+out_file_name = args.output
+
+string = "XOR differences:"
+pattern = re.compile(r'\s*%s\s*([\d+]+)' % string)
+tot_cnt = 0
+with open(log_file_name, "r") as f:
+ for line in f:
+ m = pattern.match(line)
+ if m:
+ tot_cnt += int(m.group(1))
+
+outFileOpener = open(out_file_name, "w")
+outFileOpener.write("Total XOR differences = "+ str(tot_cnt))
+outFileOpener.close()
diff --git a/caravel/utils/rename_pins.sh b/caravel/utils/rename_pins.sh
new file mode 100755
index 0000000..165b4b3
--- /dev/null
+++ b/caravel/utils/rename_pins.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#!/bin/bash
+
+# : ${1?"Usage: $0 file.def pin_name new_name"}
+# : ${2?"Usage: $0 file.def pin_name new_name"}
+# : ${3?"Usage: $0 file.def pin_name new_name"}
+
+IFS=', ' read -r -a pin_name <<< $2
+IFS=', ' read -r -a new_name <<< $3
+
+for i in "${!pin_name[@]}"; do
+ sed -i "s/${pin_name[i]}/${new_name[i]}/g" $1
+done
diff --git a/caravel/utils/scrotLayout.py b/caravel/utils/scrotLayout.py
new file mode 100644
index 0000000..6eb282e
--- /dev/null
+++ b/caravel/utils/scrotLayout.py
@@ -0,0 +1,59 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+import pya
+import re
+import os
+
+WIDTH = 2048
+HEIGHT = 2048
+
+app = pya.Application.instance()
+win = app.main_window()
+
+# Load technology file
+print('[INFO] Reading tech file: ' + str(tech_file))
+tech = pya.Technology()
+tech.load(tech_file)
+
+layoutOptions = tech.load_layout_options
+
+# Load def file in the main window
+print('[INFO] Reading Layout file: ' + str(input_layout))
+cell_view = win.load_layout(input_layout, layoutOptions, 0)
+layout_view = cell_view.view()
+
+layout_view.load_layer_props(os.path.splitext(tech_file)[0]+'.lyp')
+
+layout_view.max_hier()
+# layout_view.clear_layers()
+
+# Hide layers with these purposes
+hidden_purposes = [0, 4, 5]
+
+li = layout_view.begin_layers()
+while not li.at_end():
+ lp = li.current()
+ if lp.source_datatype in hidden_purposes:
+ new_lp = lp.dup()
+ new_lp.visible = False
+ layout_view.set_layer_properties(li, new_lp)
+
+ li.next()
+
+print("[INFO] Writing out PNG screenshot '{0}'".format(input_layout+".png"))
+layout_view.save_image(input_layout+".png", WIDTH, HEIGHT)
+print("Done")
+app.exit(0)
diff --git a/caravel/utils/scrotLayout.sh b/caravel/utils/scrotLayout.sh
new file mode 100644
index 0000000..3b81a3f
--- /dev/null
+++ b/caravel/utils/scrotLayout.sh
@@ -0,0 +1,32 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set -e
+
+: ${1?"Usage: $0 tech_file input"}
+: ${2?"Usage: $0 tech_file input"}
+
+echo "Using Techfile: $1"
+echo "Using layout file: $2"
+
+# The -a here is necessary to handle race conditions.
+# This limits the max number of possible jobs to 100.
+xvfb-run -a klayout -z \
+ -rd input_layout=$2 \
+ -rd tech_file=$1 \
+ -rm $(dirname $0)/scrotLayout.py
+
+exit 0
diff --git a/caravel/utils/xor.drc b/caravel/utils/xor.drc
new file mode 100644
index 0000000..6caee91
--- /dev/null
+++ b/caravel/utils/xor.drc
@@ -0,0 +1,42 @@
+# A general XOR script
+# (https://www.klayout.de/forum/discussion/100/xor-vs-diff-tool)
+# This script uses KLayout's DRC language to implement a generic
+# XOR between two layouts. The name of the layouts is given
+# in $a and $b.
+
+# For layout-to-layout XOR with multiple cores, run this script with
+# ./klayout -r xor.drc -rd thr=NUM_CORES -rd top_cell=TOP_CELL_NAME -rd a=a.gds -rd b=b.gds -rd ol=xor.gds -zz
+# (replace NUM_CORES by the desired number of cores to utilize
+
+# enable timing output
+verbose
+
+# set up input a
+a = source($a, $top_cell)
+
+# set up input b
+b = source($b, $top_cell)
+
+$o && $ext != "gds" && report("XOR #{$a} vs. #{$b}", $o)
+$ol && $ext == "gds" && target($ol, $co || "XOR")
+
+$thr && threads($thr) || threads(2)
+
+# collect all common layers
+layers = {}
+[ a.layout, b.layout ].each do |ly|
+ ly.layer_indices.each do |li|
+ i = ly.get_info(li)
+ layers[i.to_s] = i
+ end
+end
+
+# perform the XOR's
+layers.keys.sort.each do |l|
+ i = layers[l]
+ info("--- Running XOR for #{l} ---")
+ x = a.input(l) ^ b.input(l)
+ info("XOR differences: #{x.data.size}")
+ $o && $ext != "gds" && x.output(l, "XOR results for layer #{l} #{i.name}")
+ $ol && $ext == "gds" && x.output(i.layer, i.datatype, i.name)
+end
diff --git a/caravel/utils/xor.sh b/caravel/utils/xor.sh
new file mode 100644
index 0000000..44800d6
--- /dev/null
+++ b/caravel/utils/xor.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+: ${1?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${2?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${3?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+: ${4?"Usage: $0 file1.gds file2.gds <top_level_module_name> output.gds|markers.xml"}
+
+
+echo "First Layout: $1"
+echo "Second Layout: $2"
+echo "Design Name: $3"
+echo "Output GDS will be: $4"
+
+xvfb-run -a klayout -r $(dirname $0)/xor.drc \
+ -rd top_cell=$3 \
+ -rd a=$1 \
+ -rd b=$2 \
+ -rd thr=$(nproc) \
+ -rd ol=$4 \
+ -rd o=$4 \
+ -rd ext=${4##*.} \
+ -zz
diff --git a/caravel/verilog/dv/README.md b/caravel/verilog/dv/README.md
new file mode 100644
index 0000000..49cd280
--- /dev/null
+++ b/caravel/verilog/dv/README.md
@@ -0,0 +1,30 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+# DV Tests
+
+Organized into two subdirectories:
+ * caravel: contains tests for both the mangement SoC and an example user project.
+ * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
+
+<pre>
+├── caravel
+│ ├── mgmt_soc
+│ ├── user_proj_example
+└── wb_utests
+</pre>
+
diff --git a/caravel/verilog/dv/caravel/defs.h b/caravel/verilog/dv/caravel/defs.h
new file mode 100644
index 0000000..a9d27ec
--- /dev/null
+++ b/caravel/verilog/dv/caravel/defs.h
@@ -0,0 +1,216 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_oenb (*(volatile uint32_t*)0x25000010)
+#define reg_la1_oenb (*(volatile uint32_t*)0x25000014)
+#define reg_la2_oenb (*(volatile uint32_t*)0x25000018)
+#define reg_la3_oenb (*(volatile uint32_t*)0x2500001c)
+
+#define reg_la0_iena (*(volatile uint32_t*)0x25000020)
+#define reg_la1_iena (*(volatile uint32_t*)0x25000024)
+#define reg_la2_iena (*(volatile uint32_t*)0x25000028)
+#define reg_la3_iena (*(volatile uint32_t*)0x2500002c)
+
+#define reg_la_sample (*(volatile uint32_t*)0x25000030)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_irq (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datal (*(volatile uint32_t*)0x2600000c)
+#define reg_mprj_datah (*(volatile uint32_t*)0x26000010)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000038)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x2600003c)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000048)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x2600004c)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000058)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x2600005c)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000068)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x2600006c)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000078)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x2600007c)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000088)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x2600008c)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x2600009c)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x260000a0)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b4)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b8)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0 0x00000001
+#define FLASH_BITBANG_IO1 0x00000002
+#define FLASH_BITBANG_CLK 0x00000010
+#define FLASH_BITBANG_CSB 0x00000020
+#define FLASH_BITBANG_OEB0 0x00000100
+#define FLASH_BITBANG_OEB1 0x00000200
+#define FLASH_ENABLE 0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE 0x01
+#define TIMER_ONESHOT 0x02
+#define TIMER_UPCOUNT 0x04
+#define TIMER_CHAIN 0x08
+#define TIMER_IRQ_ENABLE 0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK 0x00ff
+#define SPI_MASTER_MLB 0x0100
+#define SPI_MASTER_INV_CSB 0x0200
+#define SPI_MASTER_INV_CLK 0x0400
+#define SPI_MASTER_MODE_1 0x0800
+#define SPI_MASTER_STREAM 0x1000
+#define SPI_MASTER_ENABLE 0x2000
+#define SPI_MASTER_IRQ_ENABLE 0x4000
+#define SPI_HOUSEKEEPING_CONN 0x8000
+
+// System Area (0x2F00_0000)
+#define reg_power_good (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE 0x0001
+#define OUTPUT_DISABLE 0x0002
+#define HOLD_OVERRIDE 0x0004
+#define INPUT_DISABLE 0x0008
+#define MODE_SELECT 0x0010
+#define ANALOG_ENABLE 0x0020
+#define ANALOG_SELECT 0x0040
+#define ANALOG_POLARITY 0x0080
+#define SLOW_SLEW_MODE 0x0100
+#define TRIPPOINT_SEL 0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
+#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801
+#define GPIO_MODE_MGMT_STD_ANALOG 0x000b
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT 0x1808
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800
+#define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802
+#define GPIO_MODE_USER_STD_ANALOG 0x000a
+
+// --------------------------------------------------------
+#endif
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/Makefile
new file mode 100644
index 0000000..7706531
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/Makefile
@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_mgmt gpio mem uart perf hkspi sysctrl mprj_ctrl pass_thru timer timer2 pll storage qspi caravan irq user_pass_thru
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ ( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile
new file mode 100644
index 0000000..285e337
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = caravan
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/README b/caravel/verilog/dv/caravel/mgmt_soc/caravan/README
new file mode 100644
index 0000000..a39b365
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/README
@@ -0,0 +1,27 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravan
+basic testbench
+------------------------------------------------
+
+This testbench exercises the basic use of the Caravan analog project
+harness, which is equivalent to the Caravel chip with 11 GPIOs
+removed from the top of the padframe and replaced with straight-through
+connections to pads.
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
new file mode 100644
index 0000000..feca129
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Caravan GPIO Test
+ *
+ * This is mainly a test of the digital I/O surrounding the analog
+ * pinouts on the caravan chip to make sure that they are connected
+ * properly after the middle GPIO pads and serial loader blocks are
+ * clipped out from the caravel design.
+ *
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* GPIO 14 to 24 have been replaced by analog and should be set */
+ /* to mode output to keep the input from floating. */
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0x0a000000;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xaa000000;
+
+ while (1) {
+ int x = (reg_mprj_datal & 0x3f80) >> 7;
+ reg_mprj_datal = (x+1) << 25;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
new file mode 100644
index 0000000..1b32be2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
@@ -0,0 +1,214 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+
+module caravan_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("caravan.vcd");
+ $dumpvars(0, caravan_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [6:0] checkbits_hi; // Upper 7 valid GPIO bits
+ wire [7:0] checkbits_lo; // Lower 6 valid GPIO bits (read)
+
+ reg [7:0] setbits_lo; // Lower 6 valid GPIO bits (write)
+
+ assign mprj_io[13:7] = setbits_lo;
+ assign checkbits_lo = mprj_io[13:7];
+ assign checkbits_hi = mprj_io[31:25];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ setbits_lo <= {7{1'bz}};
+ wait(checkbits_hi == 7'h50);
+ repeat (500) @(posedge clock);
+ setbits_lo <= 7'h30;
+ wait(checkbits_hi == 7'h05);
+ repeat (500) @(posedge clock);
+ setbits_lo <= 7'h0f;
+ wait(checkbits_hi == 7'h55);
+ repeat (1000) @(posedge clock);
+ setbits_lo <= 7'h00;
+ repeat (1300) @(posedge clock);
+ setbits_lo <= 7'h01;
+ repeat (1300) @(posedge clock);
+ setbits_lo <= 7'h03;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 7'h50); // 1st pull test
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Started");
+ `else
+ $display("Monitor: Test GPIO (RTL) Started");
+ `endif
+ wait(checkbits_lo == 7'h30); // (1st pull test result)
+ $display("Monitor: Check 1 seen");
+ wait(checkbits_hi == 7'h05); // 2nd pull test
+ $display("Monitor: Check 2 seen");
+ wait(checkbits_lo == 7'h0F); // (2nd pull test result)
+ $display("Monitor: Check 3 seen");
+ wait(checkbits_hi == 7'h55); // loopback test
+ $display("Monitor: Check 4 seen");
+ wait(checkbits_lo == 7'h00); // 1st value set
+ $display("Monitor: Check 5 seen");
+ wait(checkbits_hi == 7'h01); // 1st loopback read
+ $display("Monitor: Check 6 seen");
+ wait(checkbits_lo == 7'h01); // 2nd value set
+ $display("Monitor: Check 7 seen");
+ wait(checkbits_hi == 7'h02); // 2nd loopback read
+ $display("Monitor: Check 8 seen");
+ wait(checkbits_lo == 7'h03); // 3rd value set
+ $display("Monitor: Check 9 seen");
+ wait(checkbits_hi == 7'h04); // 3rd loopback read
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(mprj_io) begin
+ #1 $display("GPIO state = %b (%d - %d)", mprj_io,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("caravan.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile
new file mode 100644
index 0000000..7346f4e
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/README b/caravel/verilog/dv/caravel/mgmt_soc/gpio/README
new file mode 100644
index 0000000..baadc1f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/README
@@ -0,0 +1,44 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+gpio testbench
+------------------------------------------------
+
+This testbench exercises the fundamental use of the Caravel
+management SoC to drive the I/O in the user area as general
+purpose I/O on startup.
+
+On startup, all GPIO are configured as input to the management
+region (so as to be high impedence to the external world) and
+decoupled from the user project area.
+
+To configure any GPIO as output, the appropriate memory-mapped
+location for the I/O must be properly configured. Since the
+I/O configuration is stored in two places, in the SoC, but
+also locally at each I/O pad, the "transfer" bit must be
+applied, which initiates a transfer of the configuration data
+around the padframe.
+
+The testbench takes 16 pins from the user area and checks
+functionality by applying input values on 8 of these pins from
+the testbench verilog, detecting them in the C program, then
+copying the values to the other 8 pins, and detecting those
+values in the testbench verilog.
+
+If any of that does not work, then the testbench will fail.
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
new file mode 100644
index 0000000..73dd397
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -0,0 +1,115 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * GPIO Test
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0x0b000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xab000000;
+
+ while (1){
+ int x = (reg_mprj_datal & 0xff0000) >> 16;
+ reg_mprj_datal = (x+1) << 24;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
new file mode 100644
index 0000000..a6bd94d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -0,0 +1,196 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("gpio.vcd");
+ $dumpvars(0, gpio_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ checkbits_lo <= {8{1'bz}};
+ wait(checkbits_hi == 8'hA0);
+ checkbits_lo <= 8'hF0;
+ wait(checkbits_hi == 8'h0B);
+ checkbits_lo <= 8'h0F;
+ wait(checkbits_hi == 8'hAB);
+ checkbits_lo <= 8'h0;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h1;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h3;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 8'hA0);
+ wait(checkbits[7:0] == 8'hF0);
+ wait(checkbits_hi == 8'h0B);
+ wait(checkbits[7:0] == 8'h0F);
+ wait(checkbits_hi == 8'hAB);
+ wait(checkbits[7:0] == 8'h00);
+ wait(checkbits_hi == 8'h01);
+ wait(checkbits[7:0] == 8'h01);
+ wait(checkbits_hi == 8'h02);
+ wait(checkbits[7:0] == 8'h03);
+ wait(checkbits_hi == 8'h04);
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("gpio.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile
new file mode 100644
index 0000000..a4ae097
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio_mgmt
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README
new file mode 100644
index 0000000..c8dcd45
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README
@@ -0,0 +1,27 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+gpio_mgmt testbench
+------------------------------------------------
+
+This testbench is the simplest "wake-up call" for the development
+board. It toggles the single "gpio" pin under exclusive control
+of the management SoC; first a few times quickly (so it can be
+seen in simulation) then continuously at a slow pulse rate, so it
+will blink the LED on the prototype board.
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c
new file mode 100644
index 0000000..3a3265c
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Management SoC GPIO Pin Test
+ * Tests writing to the GPIO pin.
+ */
+
+void main()
+{
+ int i;
+
+ reg_gpio_data = 0;
+ reg_gpio_ena = 0;
+ reg_gpio_pu = 0;
+ reg_gpio_pd = 0;
+
+ for (i = 0; i < 10; i++) {
+ /* Fast blink for simulation */
+ reg_gpio_data = 1;
+ reg_gpio_data = 0;
+ }
+
+ while (1) {
+ /* Slow blink for demonstration board */
+ for (i = 0; i < 30000; i++) {
+ reg_gpio_data = 1;
+ }
+ for (i = 0; i < 30000; i++) {
+ reg_gpio_data = 0;
+ }
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v
new file mode 100644
index 0000000..b181dc3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v
@@ -0,0 +1,200 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_mgmt_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("gpio_mgmt.vcd");
+ $dumpvars(0, gpio_mgmt_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mgmt GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mgmt GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Monitor
+ initial begin
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ `ifdef GL
+ $display("Monitor: Test Mgmt GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test Mgmt GPIO (RTL) Passed");
+ `endif
+ #2000;
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("Mgmt GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("gpio_mgmt.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
new file mode 100644
index 0000000..2eae1ec
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = hkspi
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
new file mode 100644
index 0000000..3bfac32
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed, to show that the
+ // processor is interrupted only when the reset is applied
+ // through the SPI.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test message
+ print("\n");
+ print(" ____ _ ____ ____\n");
+ print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
+ print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+ print(" | __/| | (_| (_) |__) | (_) | |___\n");
+ print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
+
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
new file mode 100644
index 0000000..b895381
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -0,0 +1,431 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ StriVe housekeeping SPI testbench.
+*/
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module hkspi_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("hkspi.vcd");
+ $dumpvars(0, hkspi_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ // Delay, then bring chip out of reset
+ #1000;
+ RSTB <= 1'b1;
+ #2000;
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+
+ // Toggle external reset
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 7 = external reset)
+ write_byte(8'h01); // Data = 0x01 (apply external reset)
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 7 = external reset)
+ write_byte(8'h00); // Data = 0x00 (release external reset)
+ end_csb();
+
+ // Read all registers (0 to 18)
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h00); // Address (register 3 = product ID)
+ read_byte(tbdata);
+
+ $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
+ if(tbdata !== 8'h56) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
+ if(tbdata !== 8'h02) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
+ if(tbdata !== 8'hef) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
+ if(tbdata !== 8'h03) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
+ if(tbdata !== 8'h12) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("hkspi.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile
new file mode 100644
index 0000000..4520f98
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile
@@ -0,0 +1,82 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+PDK_PATH = $(PDK_ROOT)/sky130A
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = irq
+
+all: ${PATTERN:=.vcd}
+
+ex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+%.elf: %.c sections.lds start.S check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ start.S $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/README b/caravel/verilog/dv/caravel/mgmt_soc/irq/README
new file mode 100644
index 0000000..99d3cf9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/README
@@ -0,0 +1,32 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+irq testbench
+------------------------------------------------
+
+This testbench demonstrates how to use the interrupts on the
+picoRV32. It uses the internal picoRV32 counter to set up an
+interval timer. At each timer expiration, an interrupt is
+generated, and the assembler code in start.S runs and captures
+data from a routine emulating a Digilent PMOD MIC-3 microphone
+module. Data are accumulated in a ring buffer reserved in the
+top of memory. The main loop of the program queries the
+current ring buffer position, reads the data there, and
+displays the value on the GPIO (upper 16 of the lower 32 GPIO
+channels).
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S b/caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S
new file mode 100644
index 0000000..e3d1e2d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S
@@ -0,0 +1,116 @@
+/*
+ * SPDX-FileCopyrightText: 2015 Clifford Wolf
+ * PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+#define regnum_q0 0
+#define regnum_q1 1
+#define regnum_q2 2
+#define regnum_q3 3
+
+#define regnum_x0 0
+#define regnum_x1 1
+#define regnum_x2 2
+#define regnum_x3 3
+#define regnum_x4 4
+#define regnum_x5 5
+#define regnum_x6 6
+#define regnum_x7 7
+#define regnum_x8 8
+#define regnum_x9 9
+#define regnum_x10 10
+#define regnum_x11 11
+#define regnum_x12 12
+#define regnum_x13 13
+#define regnum_x14 14
+#define regnum_x15 15
+#define regnum_x16 16
+#define regnum_x17 17
+#define regnum_x18 18
+#define regnum_x19 19
+#define regnum_x20 20
+#define regnum_x21 21
+#define regnum_x22 22
+#define regnum_x23 23
+#define regnum_x24 24
+#define regnum_x25 25
+#define regnum_x26 26
+#define regnum_x27 27
+#define regnum_x28 28
+#define regnum_x29 29
+#define regnum_x30 30
+#define regnum_x31 31
+
+#define regnum_zero 0
+#define regnum_ra 1
+#define regnum_sp 2
+#define regnum_gp 3
+#define regnum_tp 4
+#define regnum_t0 5
+#define regnum_t1 6
+#define regnum_t2 7
+#define regnum_s0 8
+#define regnum_s1 9
+#define regnum_a0 10
+#define regnum_a1 11
+#define regnum_a2 12
+#define regnum_a3 13
+#define regnum_a4 14
+#define regnum_a5 15
+#define regnum_a6 16
+#define regnum_a7 17
+#define regnum_s2 18
+#define regnum_s3 19
+#define regnum_s4 20
+#define regnum_s5 21
+#define regnum_s6 22
+#define regnum_s7 23
+#define regnum_s8 24
+#define regnum_s9 25
+#define regnum_s10 26
+#define regnum_s11 27
+#define regnum_t3 28
+#define regnum_t4 29
+#define regnum_t5 30
+#define regnum_t6 31
+
+// x8 is s0 and also fp
+#define regnum_fp 8
+
+#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
+.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
+
+#define picorv32_getq_insn(_rd, _qs) \
+r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_setq_insn(_qd, _rs) \
+r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
+
+#define picorv32_retirq_insn() \
+r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
+
+#define picorv32_maskirq_insn(_rd, _rs) \
+r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_waitirq_insn(_rd) \
+r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_timer_insn(_rd, _rs) \
+r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c
new file mode 100755
index 0000000..61dfcdd
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// -------------------------------------------------------------------------
+// Test IRQ callback
+// -------------------------------------------------------------------------
+
+uint16_t flag;
+
+void irq_callback()
+{
+ /* If this routine is called, then the test passes the 1st stage */
+ reg_mprj_datah = 0xa; // Signal end of test 1st stage
+ reg_mprj_datal = 0x20000;
+ flag = 1;
+ return;
+}
+
+void main()
+{
+ uint16_t data;
+ int i;
+
+ // Configure GPIO upper bits to assert the test code
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply the GPIO configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datah = 0x5; // Signal start of test
+ reg_mprj_datal = 0;
+ flag = 0;
+
+ // Loop, waiting for the interrupt to change reg_mprj_datah
+
+ while (flag == 0) {
+ reg_mprj_datal = 0x10000;
+ }
+ reg_mprj_datal = 0x40000;
+ reg_mprj_datah = 0xc; // Signal end of test
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v
new file mode 100755
index 0000000..0e03d6d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v
@@ -0,0 +1,172 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * Caravel - A full example SoC using PicoRV32 in SkyWater sky130
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2021 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module irq_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("irq.vcd");
+ $dumpvars(0, irq_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (12) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test IRQ (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test IRQ (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [3:0] status;
+ wire [3:0] checkbits;
+
+ assign checkbits = mprj_io[19:16];
+ assign status = mprj_io[35:32];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Monitor
+ initial begin
+ wait(status == 4'h5);
+ `ifdef GL
+ $display("Monitor: Test IRQ (GL) Started");
+ `else
+ $display("Monitor: Test IRQ (RTL) Started");
+ `endif
+ wait(status == 4'ha);
+ wait(status == 4'hc);
+ `ifdef GL
+ $display("Monitor: Test IRQ (GL) Passed");
+ `else
+ $display("Monitor: Test IRQ (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits, status) begin
+ #1 $display("GPIO state = %b (%b)", checkbits, status);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("irq.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds b/caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds
new file mode 100755
index 0000000..c328222
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds
@@ -0,0 +1,83 @@
+/*
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+*/
+
+/*
+ *-------------------------------------------------------------------------
+ * Note: This is like the default sections.lds file for Caravel, but moves
+ * the start of SRAM used by the compiler to address 0x80 to make room for
+ * memory used by the firmware routines defined in the local start.S file.
+ *-------------------------------------------------------------------------
+ */
+
+MEMORY {
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
+ RAM(xrw) : ORIGIN = 0x00000080, LENGTH = 0x0380 /* 256 words (1 KB) */
+}
+
+SECTIONS {
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.srodata) /* .srodata sections (constants, strings, etc.) */
+ *(.srodata*) /* .srodata*sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ _etext = .; /* define a global symbol at end of code */
+ _sidata = _etext; /* This is used by the startup to initialize data */
+ } >FLASH
+
+ /* Initialized data section */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ _ram_start = .;
+ . = ALIGN(4);
+ *(.data)
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ *(.bss)
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+
+ /* Define the start of the heap */
+ .heap :
+ {
+ . = ALIGN(4);
+ _heap_start = .;
+ } >RAM
+}
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/start.S b/caravel/verilog/dv/caravel/mgmt_soc/irq/start.S
new file mode 100755
index 0000000..7c1c8a5
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/start.S
@@ -0,0 +1,195 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*-----------------------------------------------*/
+/* Start code that enables and handles an IRQ */
+/*-----------------------------------------------*/
+
+#undef ENABLE_FASTIRQ
+
+#include "custom_ops.S"
+
+.section .text
+.global irq
+
+reset_vec:
+ j start
+
+/* Interrupt handler @ 0x10000004 */
+/* Requires defining a routine called irq_callback in the C code */
+
+.balign 4
+irq_vec:
+ sw gp, 0*4+0x10(zero)
+ sw t0, 1*4+0x10(zero)
+ sw t1, 2*4+0x10(zero)
+ sw t2, 3*4+0x10(zero)
+ sw t4, 4*4+0x10(zero)
+ sw t5, 5*4+0x10(zero)
+
+ call irq_callback
+
+ lw gp, 0*4+0x10(zero)
+ lw t0, 1*4+0x10(zero)
+ lw t1, 2*4+0x10(zero)
+ lw t2, 3*4+0x10(zero)
+ lw t4, 4*4+0x10(zero)
+ lw t5, 5*4+0x10(zero)
+
+ picorv32_retirq_insn()
+
+irq_regs:
+ .fill 32,8
+
+
+/* Main program */
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# Write these instructions to memory location zero and following:
+# lui t4, 0x10000 = 10000eb7
+# addi t4, t4, 4 = 0e91
+# jalr t4, 0 = 000e80e7
+#
+# These three instructions jump to 0x10000004, which is the location
+# of the interrupt handler. For a fast interrupt handler, the whole
+# handler should be moved into SRAM.
+
+li t4, 0x10000eb7
+sw t4, 0(zero)
+li t4, 0x80e70e91
+sw t4, 4(zero)
+li t4, 0x000e
+sw t4, 8(zero)
+
+# Enable the timer IRQ only
+li t4, 0xfff0
+picorv32_maskirq_insn(t4, t4)
+
+# Set the picorv32 32-bit counter/timer to trigger one interrupt.
+
+li t4, 0x1200
+picorv32_timer_insn(t4, t4)
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li t0, 0x02000000
+
+# Set CS high, IO0 is output
+li t1, 0x120
+sh t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+beqz a1, flashio_worker_L3
+li t5, 8
+lbu t2, 0(a0)
+flashio_worker_L2:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+lbu t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or t2, t2, t4
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L2
+sb t2, 0(a0)
+addi a0, a0, 1
+addi a1, a1, -1
+j flashio_worker_L1
+flashio_worker_L3:
+
+# Back to MEMIO mode
+li t1, 0x80
+sb t1, 3(t0)
+
+ret
+flashio_worker_end:
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile
new file mode 100644
index 0000000..7ea6ed8
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mem
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c
new file mode 100644
index 0000000..a3b6fcc
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Memory Test
+ It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[10];
+unsigned short shorts[10];
+unsigned char bytes[10];
+
+void main()
+{
+ int i;
+
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Test Word R/W
+ for (i=0; i<10; i++)
+ ints[i] = i*5000 + 10000;
+
+ for (i=0; i<10; i++)
+ if ((i*5000+10000) != ints[i])
+ reg_mprj_datal = 0xAB400000;
+
+ reg_mprj_datal = 0xAB410000;
+
+ // Test Half Word R/W
+ reg_mprj_datal = 0xA0200000;
+ for (i=0; i<10; i++)
+ shorts[i] = i*500 + 100;
+
+ for(i=0; i<10; i++)
+ if((i*500+100) != shorts[i])
+ reg_mprj_datal = 0xAB200000;
+
+ reg_mprj_datal = 0xAB210000;
+
+ // Test byte R/W
+ reg_mprj_datal = 0xA0100000;
+ for(i=0; i<10; i++)
+ bytes[i] = i*5 + 10;
+
+ for(i=0; i<10; i++)
+ if((i*5+10) != bytes[i])
+ reg_mprj_datal = 0xAB100000;
+
+ reg_mprj_datal = 0xAB110000;
+}
\ No newline at end of file
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
new file mode 100644
index 0000000..4aa244a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -0,0 +1,203 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mem_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mem.vcd");
+ $dumpvars(0, mem_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test MEM (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test MEM (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
+ $display("Mem Test (word rw) started");
+ end
+ else if(checkbits == 16'hAB40) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB41) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA020) begin
+ $display("Mem Test (short rw) started");
+ end
+ else if(checkbits == 16'hAB20) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB21) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA010) begin
+ $display("Mem Test (byte rw) started");
+ end
+ else if(checkbits == 16'hAB10) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB11) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] passed");
+ `endif
+ $finish;
+ end
+
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VSS = 1'b0;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mem.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
new file mode 100644
index 0000000..a27ef40
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
new file mode 100644
index 0000000..1d7a140
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -0,0 +1,108 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * User Project IO Control Test
+ */
+
+void main()
+{
+ /* All GPIO pins are configured to be output */
+ /* The lower 28 bits are connected to the user */
+ /* project to output the counter result, and the */
+ /* upper 4 bits are connected to the management */
+ /* SoC to apply values that can be flagged by the */
+ /* testbench for specific benchmark tests. */
+
+ /* GPIOs 31 to 16 are connected to the management SoC */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* GPIOs 27 to 0 are connected to the user area */
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0;
+
+ // start test
+ reg_mprj_datal = 0x50000000;
+
+ // Write to IO Control
+ reg_mprj_io_0 = 0x004F;
+ if (reg_mprj_io_0 != 0x004F)
+ reg_mprj_datal = 0x60000000;
+ else
+ reg_mprj_datal = 0x70000000;
+
+ // Write to IO Control
+ reg_mprj_io_1 = 0x005F;
+ if (reg_mprj_io_1 != 0x005F)
+ reg_mprj_datal = 0x80000000;
+ else
+ reg_mprj_datal = 0x90000000;
+
+ // Write to IO Control
+ reg_mprj_io_2 = 0x006F;
+ if (reg_mprj_io_2 != 0x006F)
+ reg_mprj_datal = 0xA0000000;
+ else
+ reg_mprj_datal = 0xb0000000;
+
+ // Write to IO Control (NOTE: Only 13 bits are valid)
+ reg_mprj_io_3 = 0xF0F5;
+ if (reg_mprj_io_3 != 0x10F5)
+ reg_mprj_datal = 0xc0000000;
+ else
+ reg_mprj_datal = 0xd0000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..6ddfca3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,176 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mprj_ctrl_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] user_io;
+ wire SDO;
+
+ wire [3:0] checkbits;
+
+ assign checkbits = user_io[31:28];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_ctrl.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test User Project (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test User Project (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 4'h5) begin
+ $display("User Project control Test started");
+ end else if(checkbits == 4'h6) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: IO control R/W failed (check 6)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'h7) begin
+ $display("Monitor: IO control R/W passed (check 7)");
+ end else if(checkbits == 4'h8) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 8)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'h9) begin
+ $display("Monitor: power control R/W passed (check 9)");
+ end else if(checkbits == 4'ha) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 10)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'hb) begin
+ $display("Monitor: power control R/W passed (check 11)");
+ end else if(checkbits == 4'hc) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 12)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'hd) begin
+
+ $display("Monitor: power control R/W passed (check 13)");
+ `ifdef GL
+ $display("Monitor: User Project control (GL) test passed.");
+ `else
+ $display("Monitor: User Project control (RTL) test passed.");
+ `endif
+ $finish;
+ end
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(gpio) begin
+ #1 $display("GPIO state = %b ", gpio);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign user_io[3] = 1'b1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (user_io),
+ .flash_csb (flash_csb),
+ .flash_clk (flash_clk),
+ .flash_io0 (flash_io0),
+ .flash_io1 (flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mprj_ctrl.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
new file mode 100644
index 0000000..59ee63c
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pass_thru
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c
new file mode 100644
index 0000000..33a981d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed. to show that the
+ // processor is halted while the SPI is accessing the
+ // flash SPI in pass-through mode.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test in progress
+ reg_mprj_datal = 0xa5000000;
+
+ // Test message
+ print("Test message\n");
+
+ // End test
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
new file mode 100644
index 0000000..4ab65de
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -0,0 +1,351 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ * StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module pass_thru_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("pass_thru.vcd");
+ $dumpvars(0, pass_thru_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ #2000;
+
+ RSTB <= 1'b1;
+
+ // Wait on start of program execution
+ wait(checkbits == 16'hA000);
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ // Now write a command directly to the SPI flash.
+ start_csb();
+ write_byte(8'hc4); // Pass-thru mode
+ write_byte(8'h03); // Command 03 (read values w/3-byte address
+ write_byte(8'h00); // Address is next three bytes (0x000000)
+ write_byte(8'h00);
+ write_byte(8'h00);
+
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ // Wait for processor to restart
+ wait(checkbits == 16'hA000);
+
+ // Read product ID register again
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("pass_thru.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile
new file mode 100644
index 0000000..e96935a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = perf
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c
new file mode 100644
index 0000000..5a17ba2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Performance Test
+ It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[50];
+unsigned short shorts[50];
+unsigned char bytes[50];
+
+int main()
+{
+ int i;
+ int sum = 0;
+
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0;
+
+ // start test
+ reg_mprj_datal = 0xA0000000;
+
+ for (i=0; i<100; i++)
+ sum += (sum + i);
+
+ reg_mprj_datal = 0xAB000000;
+
+ return sum;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
new file mode 100644
index 0000000..25798ec
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -0,0 +1,159 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module perf_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ reg [31:0] kcycles;
+
+ initial begin
+ $dumpfile("perf.vcd");
+ $dumpvars(0, perf_tb);
+
+ kcycles = 0;
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ kcycles <= kcycles + 1;
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Performance (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Performance (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ //#1 $display("GPIO state = %X ", gpio);
+ if(checkbits == 16'hA000) begin
+ kcycles = 0;
+ $display("Performance Test started");
+ end
+ else if(checkbits == 16'hAB00) begin
+ //$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
+ `ifdef GL
+ $display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
+ `else
+ $display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("perf.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile
new file mode 100644
index 0000000..965ce0a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -0,0 +1,79 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pll
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c
new file mode 100644
index 0000000..81a1fc6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c
@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * PLL Test (self-switching)
+ * - Enables SPI master
+ * - Uses SPI master to internally access the housekeeping SPI
+ * - Switches PLL bypass
+ * - Changes PLL divider
+ *
+ * Tesbench mostly copied from sysctrl
+ */
+void main()
+{
+ int i;
+
+ reg_mprj_datal = 0;
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Enable SPI master
+ // SPI master configuration bits:
+ // bits 7-0: Clock prescaler value (default 2)
+ // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
+ // bit 9: CSB sense (0 = inverted, 1 = noninverted)
+ // bit 10: SCK sense (0 = noninverted, 1 = inverted)
+ // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
+ // bit 12: stream (1 = CSB ends transmission)
+ // bit 13: enable (1 = enabled)
+ // bit 14: IRQ enable (1 = enabled)
+ // bit 15: Connect to housekeeping SPI (1 = connected)
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Apply stream read (0x40 + 0x03) and read back one byte
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x08; // Write 0x18 (start address)
+ reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x11; // Write 0x11 (start address)
+ reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x09; // Write 0x09 (start address)
+ reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass)
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ // Write checkpoint
+ reg_mprj_datal = 0xA0410000;
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x12; // Write 0x12 (start address)
+ reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04)
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ // Write checkpoint
+ reg_mprj_datal = 0xA0420000;
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x80; // Write 0x80 (write mode)
+ reg_spimaster_data = 0x11; // Write 0x11 (start address)
+ reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+
+ reg_spimaster_config = 0x2102; // Release housekeeping SPI
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
new file mode 100644
index 0000000..5c037b0
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -0,0 +1,158 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module pll_tb;
+ reg clock;
+ reg power1;
+ reg power2;
+ reg RSTB;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("pll.vcd");
+ $dumpvars(0, pll_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test PLL (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+
+ $display("Monitor: Test PLL (RTL) Started");
+
+ wait(checkbits == 16'hA041);
+ // $display(" SPI value = 0x%x (should be 0x04)", spivalue);
+ // if(spivalue !== 32'h04) begin
+ // $display("Monitor: Test PLL (RTL) Failed");
+ // $finish;
+ // end
+ wait(checkbits == 16'hA042);
+ // $display(" SPI value = 0x%x (should be 0x56)", spivalue);
+ // if(spivalue !== 32'h56) begin
+ // $display("Monitor: Test PLL (RTL) Failed");
+ // $finish;
+ // end
+
+ wait(checkbits == 16'hA090);
+
+ $display("Monitor: Test PLL (RTL) Passed");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("pll.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile
new file mode 100644
index 0000000..d94dd33
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = qspi
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/README b/caravel/verilog/dv/caravel/mgmt_soc/qspi/README
new file mode 100644
index 0000000..4b3644a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/README
@@ -0,0 +1,28 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+qspi testbench
+------------------------------------------------
+
+This testbench is mainly a copy of the gpio testbench and uses the
+same checks for pass/fail status. The difference is that the startup
+C code puts the SPI flash into QSPI/DDR/CRM modes for fastest access
+and enables the GPIO channels 36 and 37 to work as the flash IO2 and
+IO3 channels. If the channel and spimemio setup works correctly,
+then the testbench simulation will pass.
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c
new file mode 100644
index 0000000..597e45f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c
@@ -0,0 +1,132 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * GPIO Test
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set SPI flash latency to 8 for use with the spiflash.v
+ * module (note that spiflash.v does not have configuration
+ * registers emulated, so the external flash cannot be
+ * changed from its default of 8).
+ */
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Now the flash SPI controller can be put in qspi/ddr/crm mode */
+ /* First run DSPI + CRM */
+ reg_spictrl = 0x80580000; // DSPI + CRM
+
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Now run QSPI + CRM */
+ reg_spictrl = 0x80380000; // QSPI + CRM
+
+ reg_mprj_datal = 0x0b000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Now run QSPI + DDR + CRM */
+ reg_spictrl = 0x80780000; // QSPI + DDR + CRM
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xab000000;
+
+ while (1){
+ int x = (reg_mprj_datal & 0xff0000) >> 16;
+ reg_mprj_datal = (x+1) << 24;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
new file mode 100644
index 0000000..d8683b9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
@@ -0,0 +1,205 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module qspi_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("qspi.vcd");
+ $dumpvars(0, qspi_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [35:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ checkbits_lo <= {8{1'bz}};
+ wait(checkbits_hi == 8'hA0);
+ checkbits_lo <= 8'hF0;
+ wait(checkbits_hi == 8'h0B);
+ checkbits_lo <= 8'h0F;
+ wait(checkbits_hi == 8'hAB);
+ checkbits_lo <= 8'h0;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h1;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h3;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 8'hA0);
+ `ifdef GL
+ $display("Monitor: Test QSPI (GL) Started");
+ `else
+ $display("Monitor: Test QSPI (RTL) Started");
+ `endif
+ wait(checkbits[7:0] == 8'hF0);
+ wait(checkbits_hi == 8'h0B);
+ wait(checkbits[7:0] == 8'h0F);
+ wait(checkbits_hi == 8'hAB);
+ wait(checkbits[7:0] == 8'h00);
+ wait(checkbits_hi == 8'h01);
+ wait(checkbits[7:0] == 8'h01);
+ wait(checkbits_hi == 8'h02);
+ wait(checkbits[7:0] == 8'h03);
+ wait(checkbits_hi == 8'h04);
+ `ifdef GL
+ $display("Monitor: Test QSPI (GL) Passed");
+ `else
+ $display("Monitor: Test QSPI (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+ // flash_io2 = mgmt_gpio_io[36] (inout)
+ // flash_io3 = mgmt_gpio_io[37] (inout)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io ({flash_io3, flash_io2, mprj_io}),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("qspi.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(flash_io2),
+ .io3(flash_io3)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile
new file mode 100644
index 0000000..d0657a3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = storage
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c
new file mode 100644
index 0000000..55fdd98
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c
@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Storage area Test
+ It uses GPIO to flag the success or failure of the test
+*/
+
+void main()
+{
+ int i;
+ volatile uint32_t* ram_addr;
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Test Management R/W block0
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ *ram_addr = i*5000 + 10000;
+ }
+
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ if ((i*5000+10000) != *ram_addr)
+ reg_mprj_datal = 0xAB400000;
+ }
+
+ reg_mprj_datal = 0xAB410000;
+
+ // Test Management R/W block1
+ reg_mprj_datal = 0xA0200000;
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block1 + i;
+ *ram_addr = i*5000 + 10000;
+ }
+
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block1 + i;
+ if ((i*5000+10000) != *ram_addr)
+ reg_mprj_datal = 0xAB200000;
+ }
+
+ reg_mprj_datal = 0xAB210000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
new file mode 100644
index 0000000..0adee87
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -0,0 +1,190 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module storage_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("storage.vcd");
+ $dumpvars(0, storage_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Storage (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Storage (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
+ `ifdef GL
+ $display("Mem Test storage MGMT block0 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+ `endif
+ end
+ else if(checkbits == 16'hAB40) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB41) begin
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA020) begin
+ `ifdef GL
+ $display("Mem Test storage MGMT block1 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+ `endif
+ end
+ else if(checkbits == 16'hAB20) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB21) begin
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] passed");
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VSS = 1'b0;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("storage.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
new file mode 100644
index 0000000..0566b44
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = sysctrl
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
new file mode 100644
index 0000000..0f5d56d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
@@ -0,0 +1,165 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * System Control Test
+ * - Enables SPI master
+ * - Uses SPI master to internally access the housekeeping SPI
+ * - Reads default value of SPI-Controlled registers
+ * - Flags failure/success using mprj_io
+ */
+void main()
+{
+ int i;
+ uint32_t value;
+
+ reg_mprj_datal = 0;
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Configure next 8 bits for writing the SPI value read on GPIO
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Enable SPI master
+ // SPI master configuration bits:
+ // bits 7-0: Clock prescaler value (default 2)
+ // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
+ // bit 9: CSB sense (0 = inverted, 1 = noninverted)
+ // bit 10: SCK sense (0 = noninverted, 1 = inverted)
+ // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
+ // bit 12: stream (1 = CSB ends transmission)
+ // bit 13: enable (1 = enabled)
+ // bit 14: IRQ enable (1 = enabled)
+ // bit 15: Connect to housekeeping SPI (1 = connected)
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Apply stream read (0x40 + 0x03) and read back one byte
+
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x40; // Write 0x40 (read mode)
+ reg_spimaster_data = 0x01; // Write 0x01 (start address)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0410000 | (value << 8); // Mfgr ID (high)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0420000 | (value << 8); // Mfgr ID (low)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0430000 | (value << 8); // Prod ID
+
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x40; // Write 0x40 (read mode)
+ reg_spimaster_data = 0x08; // Write 0x08 (start address)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0440000 | (value << 8); // PLL enable
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0450000 | (value << 8); // PLL bypass
+
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0xb002; // Apply stream mode
+ reg_spimaster_data = 0x40; // Write 0x40 (read mode)
+ reg_spimaster_data = 0x0d; // Write 0x0d (start address)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0460000 | (value << 8); // PLL trim (2 high bits)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0470000 | (value << 8); // PLL trim (2nd byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0480000 | (value << 8); // PLL trim (3rd byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0490000 | (value << 8); // PLL trim (low byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA04a0000 | (value << 8); // PLL select (3 lowest bits)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA04b0000 | (value << 8); // PLL divider (5 lowest bits)
+
+ reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x2102; // Release housekeeping SPI
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
new file mode 100644
index 0000000..295c029
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -0,0 +1,224 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module sysctrl_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("sysctrl.vcd");
+ $dumpvars(0, sysctrl_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Sysctrl (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+ `ifdef GL
+ $display("Monitor: Test Sysctrl (GL) Started");
+ `else
+ $display("Monitor: Test Sysctrl (RTL) Started");
+ `endif
+ wait(checkbits == 16'hA041);
+ $display(" SPI value = 0x%x (should be 0x04)", spivalue);
+ if(spivalue !== 32'h04) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA042);
+ $display(" SPI value = 0x%x (should be 0x56)", spivalue);
+ if(spivalue !== 32'h56) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA043);
+ $display(" SPI value = 0x%x (should be 0x10)", spivalue);
+ if(spivalue !== 32'h10) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA044);
+ $display(" SPI value = 0x%x (should be 0x02)", spivalue);
+ if(spivalue !== 32'h02) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA045);
+ $display(" SPI value = 0x%x (should be 0x01)", spivalue);
+ if(spivalue !== 32'h01) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA046);
+ $display(" SPI value = 0x%x (should be 0xff)", spivalue);
+ if(spivalue !== 32'hff) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA047);
+ $display(" SPI value = 0x%x (should be 0xef)", spivalue);
+ if(spivalue !== 32'hef) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA048);
+ $display(" SPI value = 0x%x (should be 0xff)", spivalue);
+ if(spivalue !== 32'hff) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA049);
+ $display(" SPI value = 0x%x (should be 0x03)", spivalue);
+ if(spivalue !== 32'h03) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA04a);
+ $display(" SPI value = 0x%x (should be 0x12)", spivalue);
+ if(spivalue !== 32'h12) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA04b);
+ $display(" SPI value = 0x%x (should be 0x04)", spivalue);
+ if(spivalue !== 32'h04) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA090);
+ `ifdef GL
+ $display("Monitor: Test Sysctrl (GL) Passed");
+ `else
+ $display("Monitor: Test Sysctrl (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("sysctrl.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile
new file mode 100644
index 0000000..aa978e5
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = timer
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c
new file mode 100644
index 0000000..e01ed7f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Timer Test
+ */
+
+void main()
+{
+ int i;
+ uint32_t value;
+
+ /* Initialize output data vector to zero */
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datal = 0x00000000;
+
+ /* Apply all 38 bits to management standard output. */
+
+ /* The lower 32 will be used to output the count value */
+ /* from the timer. The top 5 bits will be used to mark */
+ /* specific checkpoints for the testbench simulation. */
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Present start marker (see testbench verilog) */
+ reg_mprj_datah = 0x0a;
+
+ /* Configure timer for a single-shot countdown */
+ reg_timer0_value = 0xdcba9876;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = chain (1 = enabled, 0 = disabled) */
+ /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer0_config = 3; /* Enabled, one-shot, down count */
+
+ for (i = 0; i < 8; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_timer0_config = 0; /* Disabled */
+
+ reg_mprj_datah = 0x01; /* Check value in testbench */
+
+ reg_timer0_value = 0x00000011;
+ reg_timer0_config = 7; /* Enabled, one-shot, count up */
+
+ for (i = 0; i < 3; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x02; /* Check value in testbench */
+
+ reg_timer0_data = 0x00000101; // Set value (will be reset)
+ reg_timer0_config = 2; /* Disabled, one-shot, count up */
+ reg_timer0_config = 5; /* Enabled, continuous, count down */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x03; /* Check value in testbench */
+
+ reg_timer0_data = 0x00000145; // Force new value
+
+ reg_mprj_datah = 0x04; /* Check value in testbench */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ /* Present end marker (see testbench verilog) */
+ reg_mprj_datah = 0x05;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
new file mode 100644
index 0000000..3865bf3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -0,0 +1,201 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer_tb;
+
+ reg RSTB;
+ reg clock;
+ reg power1, power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("timer.vcd");
+ $dumpvars(0, timer_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (50) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [5:0] checkbits;
+ wire [31:0] countbits;
+
+ assign checkbits = mprj_io[37:32];
+ assign countbits = mprj_io[31:0];
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ // Monitor
+ initial begin
+ wait(checkbits == 6'h0a);
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Started");
+ `else
+ $display("Monitor: Test Timer (RTL) Started");
+ `endif
+ /* Add checks here */
+ wait(checkbits == 6'h01);
+ $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+ if(countbits !== 32'hdcba7cfb) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h02);
+ $display(" countbits = 0x%x (should be 0x19)", countbits);
+ if(countbits !== 32'h19) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h03);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== ((32'h0f) | (3'b100))) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h04);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== ((32'h0f) | (3'b100))) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h05);
+ $display(" countbits = %x (should be 0x12bc)", countbits);
+ if(countbits !== 32'h12bc) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Passed");
+ `else
+ $display("Monitor: Test Timer (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("Timer state = %b (%d)", countbits, countbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("timer.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile
new file mode 100644
index 0000000..206be56
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = timer2
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
new file mode 100644
index 0000000..6d598ac
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Timer2 Test --- This runs the same testbench as the
+ * other timer, on the 2nd counter/timer module instance.
+ */
+
+void main()
+{
+ int i;
+ uint32_t value;
+
+ /* Initialize output data vector to zero */
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datal = 0x00000000;
+
+ /* Apply all 38 bits to management standard output. */
+
+ /* The lower 32 will be used to output the count value */
+ /* from the timer. The top 5 bits will be used to mark */
+ /* specific checkpoints for the testbench simulation. */
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Present start marker (see testbench verilog) */
+ reg_mprj_datah = 0x0a;
+
+ /* Configure timer for a single-shot countdown */
+ reg_timer1_value = 0xdcba9876;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer1_config = 3; /* Enabled, one-shot, down count */
+
+ for (i = 0; i < 8; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_timer1_config = 0; /* Disabled */
+
+ reg_mprj_datah = 0x01; /* Check value in testbench */
+
+ reg_timer1_value = 0x00000011;
+ reg_timer1_config = 7; /* Enabled, one-shot, count up */
+
+ for (i = 0; i < 3; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x02; /* Check value in testbench */
+
+ reg_timer1_data = 0x00000101; // Set value (will be reset)
+ reg_timer1_config = 2; /* Disabled, one-shot, count up */
+ reg_timer1_config = 5; /* Enabled, continuous, count down */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x03; /* Check value in testbench */
+
+ reg_timer1_data = 0x00000145; // Force new value
+
+ reg_mprj_datah = 0x04; /* Check value in testbench */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x05; /* Check value in testbench */
+
+ /* Now, set up chained 64 bit timer. Check count-up */
+ /* value and count-down value crossing the 32-bit */
+ /* boundary. */
+
+ /* First disable both counters, and set the "chained" */
+ /* property so that enable/disable will be synchronized */
+
+ reg_timer1_config = 8; /* Disabled, chained */
+ reg_timer0_config = 8; /* Disabled, chained */
+
+ /* Configure timer for a chained single-shot countdown. */
+ /* Count start = 0x0000000100001000, end = 0x0 */
+
+ reg_timer1_value = 0x00000055;
+ reg_timer0_value = 0x00001000;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = chain (1 = enabled, 0 = disabled) */
+ /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer1_config = 11; /* Enabled, one-shot, down count, chained */
+ reg_timer0_config = 11; /* Enabled, one-shot, down count, chained */
+
+ for (i = 0; i < 1; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x06; /* Check value in testbench */
+
+ // Skip to the end. . .
+ reg_timer1_data = 0x00000000;
+ reg_timer0_data = 0x00000200;
+
+ for (i = 0; i < 4; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x07; /* Check value in testbench */
+
+ reg_timer1_config = 14; /* Disabled, one-shot, up count, chained */
+ reg_timer0_config = 14; /* Disabled, one-shot, up count, chained */
+
+ reg_timer1_value = 0x00000002;
+ reg_timer0_value = 0x00000000;
+
+ reg_timer1_config = 15; /* Enabled, one-shot, up count, chained */
+ reg_timer0_config = 15; /* Enabled, one-shot, up count, chained */
+
+ for (i = 0; i < 1; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x08; /* Check value in testbench */
+
+ // Skip to the end. . .
+ /* Count 0x00000001ffffff00 to 0x0000000200000000 and stop */
+
+ reg_timer1_data = 0x00000001; // Set value (will be reset)
+ reg_timer0_data = 0xffffff00; // Set value (will be reset)
+
+ for (i = 0; i < 4; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put timer1 count value on GPIO
+ }
+
+ /* Present end marker (see testbench verilog) */
+ reg_mprj_datah = 0x10;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
new file mode 100644
index 0000000..a53e216
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -0,0 +1,229 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer2_tb;
+
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("timer2.vcd");
+ $dumpvars(0, timer2_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (60) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Timer2 (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Timer2 (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [5:0] checkbits;
+ wire [31:0] countbits;
+
+ assign checkbits = mprj_io[37:32];
+ assign countbits = mprj_io[31:0];
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ // Monitor
+ initial begin
+ wait(checkbits == 6'h0a);
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Started");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Started");
+ `endif
+ /* Add checks here */
+ wait(checkbits == 6'h01);
+ $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+ if(countbits !== 32'hdcba7cfb) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h02);
+ $display(" countbits = 0x%x (should be 0x19)", countbits);
+ if(countbits !== 32'h19) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h03);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== 32'h0f) begin
+ $display("Monitor: Test Timer (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h04);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== 32'h0f) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h05);
+ $display(" countbits = %x (should be 0x12bc)", countbits);
+ if(countbits !== 32'h12bc) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h06);
+ $display(" countbits = %x (should be 0x005d)", countbits);
+ if(countbits !== 32'h005d) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h07);
+ $display(" countbits = %x (should be 0x0008)", countbits);
+ if(countbits !== 32'h0008) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h08);
+ $display(" countbits = %x (should be 0x0259)", countbits);
+ if(countbits !== 32'h0259) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h10);
+ $display(" countbits = %x (should be 0x000a)", countbits);
+ if(countbits !== 32'h000a) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Passed");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("Timer state = %b (%d)", countbits, countbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("timer2.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile
new file mode 100644
index 0000000..e8bd40a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = uart
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c
new file mode 100644
index 0000000..13cee0f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c
@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+void main()
+{
+ int j;
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set clock to 64 kbaud and enable the UART. It is important to do this
+ // before applying the configuration, or else the Tx line initializes as
+ // zero, which indicates the start of a byte to the receiver.
+
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Now, apply the configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // This should appear at the output, received by the testbench UART.
+ // (Makes simulation time long.)
+ print("Monitor: Test UART (RTL) passed\n");
+
+ // Allow transmission to complete before signalling that the program
+ // has ended.
+ for (j = 0; j < 20; j++);
+ reg_mprj_datal = 0xab000000;
+}
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
new file mode 100644
index 0000000..d8bbd35
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -0,0 +1,150 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module uart_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+ wire uart_tx;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("uart.vcd");
+ $dumpvars(0, uart_tb);
+
+ $display("Wait for UART o/p");
+ repeat (150) begin
+ repeat (10000) @(posedge clock);
+ // Diagnostic. . . interrupts output pattern.
+ end
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA000) begin
+ $display("UART Test started");
+ end
+ else if(checkbits == 16'hAB00) begin
+ `ifdef GL
+ $display("UART Test (GL) passed");
+ `else
+ $display("UART Test (RTL) passed");
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("uart.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile
new file mode 100644
index 0000000..074b999
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = user_pass_thru
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README
new file mode 100644
index 0000000..e4072d6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README
@@ -0,0 +1,14 @@
+------------------------------------
+user_pass_thru test bench
+------------------------------------
+
+This test bench exercises the pass-thru mode to the GPIO pins
+that are reserved for use by a user project for connecting to
+an SPI flash. The pass-thru mode allows the SPI flash to be
+programmed using the housekeeping SPI.
+
+The testbench is essentially the same as the pass_thru test
+bench, but using the pins specified for the secondary SPI
+flash. Note that the testbench does not define a controller
+on the user side to access the SPI flash (which would be a
+useful thing to add to the testbench).
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c
new file mode 100644
index 0000000..011102c
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed. to show that the
+ // processor is halted while the SPI is accessing the
+ // flash SPI in pass-through mode.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Management needs to apply output on these pads to access the user area SPI flash
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test in progress
+ reg_mprj_datal = 0xa5000000;
+
+ // Test message
+ print("Test message\n");
+
+ // End test
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v
new file mode 100644
index 0000000..6407813
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v
@@ -0,0 +1,399 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ * StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module user_pass_thru_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire user_csb;
+ wire user_clk;
+ wire user_io0;
+ wire user_io1;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("user_pass_thru.vcd");
+ $dumpvars(0, user_pass_thru_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ #2000;
+
+ RSTB <= 1'b1;
+
+ // Wait on start of program execution
+ wait(checkbits == 16'hA000);
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ // The SPI flash may need to be reset.
+ start_csb();
+ write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+ write_byte(8'hff); // SPI flash command ff
+ end_csb();
+
+ start_csb();
+ write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+ write_byte(8'hab); // SPI flash command ab
+ end_csb();
+
+ start_csb();
+ write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+ write_byte(8'h03); // Command 03 (read values w/3-byte address)
+ write_byte(8'h00); // Address is next three bytes (0x000000)
+ write_byte(8'h00);
+ write_byte(8'h00);
+
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ // Reset processor
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 11 = reset)
+ write_byte(8'h01); // Data (value 1 = apply reset)
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 11 = reset)
+ write_byte(8'h00); // Data (value 1 = apply reset)
+ end_csb();
+
+ // Wait for processor to restart
+ wait(checkbits == 16'hA000);
+
+ // Read product ID register again
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x10)", tbdata);
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ assign user_csb = mprj_io[8];
+ assign user_clk = mprj_io[9];
+ assign user_io0 = mprj_io[10];
+ assign mprj_io[11] = user_io1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("user_pass_thru.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Use the same flash; this is just to put known data in memory that can be
+ // checked by reading it back through a pass-through command.
+ spiflash #(
+ .FILENAME("user_pass_thru.hex")
+ ) secondary (
+ .csb(user_csb),
+ .clk(user_clk),
+ .io0(user_io0),
+ .io1(user_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/sections.lds b/caravel/verilog/dv/caravel/sections.lds
new file mode 100644
index 0000000..2d8c048
--- /dev/null
+++ b/caravel/verilog/dv/caravel/sections.lds
@@ -0,0 +1,75 @@
+/*
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+*/
+
+MEMORY {
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x0400 /* 256 words (1 KB) */
+}
+
+SECTIONS {
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.srodata) /* .srodata sections (constants, strings, etc.) */
+ *(.srodata*) /* .srodata*sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ _etext = .; /* define a global symbol at end of code */
+ _sidata = _etext; /* This is used by the startup to initialize data */
+ } >FLASH
+
+ /* Initialized data section */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ _ram_start = .;
+ . = ALIGN(4);
+ *(.data)
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ *(.bss)
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+
+ /* Define the start of the heap */
+ .heap :
+ {
+ . = ALIGN(4);
+ _heap_start = .;
+ } >RAM
+}
diff --git a/caravel/verilog/dv/caravel/spiflash.v b/caravel/verilog/dv/caravel/spiflash.v
new file mode 100644
index 0000000..6aa29ba
--- /dev/null
+++ b/caravel/verilog/dv/caravel/spiflash.v
@@ -0,0 +1,447 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+// AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+// Cypress S25FL064L http://www.cypress.com/file/316661/download
+// Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+ parameter FILENAME = "firmware.hex"
+)(
+ input csb,
+ input clk,
+ inout io0, // MOSI
+ inout io1, // MISO
+ inout io2,
+ inout io3
+);
+ localparam verbose = 0;
+ localparam integer latency = 8;
+
+ reg [7:0] buffer;
+ reg [3:0] reset_count = 0;
+ reg [3:0] reset_monitor = 0;
+ integer bitcount = 0;
+ integer bytecount = 0;
+ integer dummycount = 0;
+
+ reg [7:0] spi_cmd;
+ reg [7:0] xip_cmd = 0;
+ reg [23:0] spi_addr;
+
+ reg [7:0] spi_in;
+ reg [7:0] spi_out;
+ reg spi_io_vld;
+
+ reg powered_up = 0;
+
+ localparam [3:0] mode_spi = 1;
+ localparam [3:0] mode_dspi_rd = 2;
+ localparam [3:0] mode_dspi_wr = 3;
+ localparam [3:0] mode_qspi_rd = 4;
+ localparam [3:0] mode_qspi_wr = 5;
+ localparam [3:0] mode_qspi_ddr_rd = 6;
+ localparam [3:0] mode_qspi_ddr_wr = 7;
+
+ reg [3:0] mode = 0;
+ reg [3:0] next_mode = 0;
+
+ reg io0_oe = 0;
+ reg io1_oe = 0;
+ reg io2_oe = 0;
+ reg io3_oe = 0;
+
+ reg io0_dout = 0;
+ reg io1_dout = 0;
+ reg io2_dout = 0;
+ reg io3_dout = 0;
+
+ assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+ assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+ assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+ assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+ wire io0_delayed;
+ wire io1_delayed;
+ wire io2_delayed;
+ wire io3_delayed;
+
+ assign #1 io0_delayed = io0;
+ assign #1 io1_delayed = io1;
+ assign #1 io2_delayed = io2;
+ assign #1 io3_delayed = io3;
+
+ // 16 MB (128Mb) Flash
+ reg [7:0] memory [0:16*1024*1024-1];
+
+ initial begin
+ $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+ memory[1048576], memory[1048577], memory[1048578],
+ memory[1048579], memory[1048580]);
+ $display("Reading %s", FILENAME);
+ $readmemh(FILENAME, memory);
+ $display("%s loaded into memory", FILENAME);
+ $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+ memory[1048576], memory[1048577], memory[1048578],
+ memory[1048579], memory[1048580]);
+ end
+
+ task spi_action;
+ begin
+ spi_in = buffer;
+
+ if (bytecount == 1) begin
+ spi_cmd = buffer;
+
+ if (spi_cmd == 8'h ab)
+ powered_up = 1;
+
+ if (spi_cmd == 8'h b9)
+ powered_up = 0;
+
+ if (spi_cmd == 8'h ff)
+ xip_cmd = 0;
+ end
+
+ if (powered_up && spi_cmd == 'h 03) begin
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount >= 4) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h bb) begin
+ if (bytecount == 1)
+ mode = mode_dspi_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_dspi_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h eb) begin
+ if (bytecount == 1)
+ mode = mode_qspi_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_qspi_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h ed) begin
+ if (bytecount == 1)
+ next_mode = mode_qspi_ddr_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_qspi_ddr_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ spi_out = buffer;
+ spi_io_vld = 1;
+
+ if (verbose) begin
+ if (bytecount == 1)
+ $write("<SPI-START>");
+ $write("<SPI:%02x:%02x>", spi_in, spi_out);
+ end
+
+ end
+ endtask
+
+ task ddr_rd_edge;
+ begin
+ buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ endtask
+
+ task ddr_wr_edge;
+ begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+
+ buffer = {buffer, 4'h 0};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ endtask
+
+ always @(csb) begin
+ if (csb) begin
+ if (verbose) begin
+ $display("");
+ $fflush;
+ end
+ buffer = 0;
+ bitcount = 0;
+ bytecount = 0;
+ mode = mode_spi;
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+
+ // Handle MBR. If in XIP continuous mode, the following
+ // 8 clock cycles are normally not expected to be a command.
+ // If followed by CSB high, however, if the address bits
+ // are consistent with io0 == 1 for 8 clk cycles, then an
+ // MBR has been issued and the system must exit XIP
+ // continuous mode.
+ if (xip_cmd == 8'hbb || xip_cmd == 8'heb
+ || xip_cmd == 8'hed) begin
+ if (reset_count == 4'h8 && reset_monitor == 4'h8) begin
+ xip_cmd = 8'h00;
+ spi_cmd = 8'h03;
+ end
+ end
+ end else
+ if (xip_cmd) begin
+ buffer = xip_cmd;
+ bitcount = 0;
+ bytecount = 1;
+ spi_action;
+ end
+ end
+
+ always @(posedge clk or posedge csb) begin
+ if (csb == 1'b1) begin
+ reset_count = 0;
+ reset_monitor = 0;
+ end else begin
+ if (reset_count < 4'h9) begin
+ reset_count = reset_count + 1;
+ if (io0_delayed == 1'b1) begin
+ reset_monitor = reset_monitor + 1;
+ end
+ end
+ end
+ end
+
+ always @(csb, clk) begin
+ spi_io_vld = 0;
+ if (!csb && !clk) begin
+ if (dummycount > 0) begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end else
+ case (mode)
+ mode_spi: begin
+ io0_oe = 0;
+ io1_oe = 1;
+ io2_oe = 0;
+ io3_oe = 0;
+ io1_dout = buffer[7];
+ end
+ mode_dspi_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_dspi_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 0;
+ io3_oe = 0;
+ io0_dout = buffer[6];
+ io1_dout = buffer[7];
+ end
+ mode_qspi_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_qspi_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+ end
+ mode_qspi_ddr_rd: begin
+ ddr_rd_edge;
+ end
+ mode_qspi_ddr_wr: begin
+ ddr_wr_edge;
+ end
+ endcase
+ if (next_mode) begin
+ case (next_mode)
+ mode_qspi_ddr_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_qspi_ddr_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+ end
+ endcase
+ mode = next_mode;
+ next_mode = 0;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!csb) begin
+ if (dummycount > 0) begin
+ dummycount = dummycount - 1;
+ end else
+ case (mode)
+ mode_spi: begin
+ buffer = {buffer, io0};
+ bitcount = bitcount + 1;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_dspi_rd, mode_dspi_wr: begin
+ buffer = {buffer, io1, io0};
+ bitcount = bitcount + 2;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_qspi_rd, mode_qspi_wr: begin
+ buffer = {buffer, io3, io2, io1, io0};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_qspi_ddr_rd: begin
+ ddr_rd_edge;
+ end
+ mode_qspi_ddr_wr: begin
+ ddr_wr_edge;
+ end
+ endcase
+ end
+ end
+endmodule
diff --git a/caravel/verilog/dv/caravel/start.s b/caravel/verilog/dv/caravel/start.s
new file mode 100644
index 0000000..287cba2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/start.s
@@ -0,0 +1,174 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li t0, 0x28000000
+
+# Set CS high, IO0 is output
+li t1, 0x120
+sh t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li t5, 32
+# Load t2 from address a0 (4 bytes)
+lw t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+lbu t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw t2, 0(a0)
+addi a0, a0, 4
+lw t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li t1, 0x80
+sb t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+
diff --git a/caravel/verilog/dv/caravel/stub.c b/caravel/verilog/dv/caravel/stub.c
new file mode 100644
index 0000000..575cfc3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/stub.c
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
\ No newline at end of file
diff --git a/caravel/verilog/dv/caravel/tbuart.v b/caravel/verilog/dv/caravel/tbuart.v
new file mode 100644
index 0000000..bac9480
--- /dev/null
+++ b/caravel/verilog/dv/caravel/tbuart.v
@@ -0,0 +1,93 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud */
+/* and accepting ASCII characters for display. */
+
+/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */
+/* should be possible on a testing system to interface to the UART */
+/* pins on a Raspberry Pi, also running at 3.3V. */
+
+module tbuart (
+ input ser_rx
+);
+ reg [3:0] recv_state;
+ reg [2:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+ reg [8*50-1:0] recv_buf_data; // 50 characters. Increase as needed for tests.
+
+ reg clk;
+
+ initial begin
+ clk <= 1'b0;
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ recv_buf_data <= 0;
+ end
+
+ // NOTE: Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+ // bit ~= 64 kbaud. Not tuned to any particular UART. Most run at
+ // 9600 baud default and will bounce up to higher baud rates when
+ // passed specific command words.
+
+ always #1500 clk <= (clk === 1'b0);
+
+ always @(posedge clk) begin
+ recv_divcnt <= recv_divcnt + 1;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > 3'd3) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > 3'd3) begin
+ // 0x0a = '\n'
+ if (recv_pattern == 8'h0a) begin
+ $display("output: %s", recv_buf_data);
+ end else begin
+ recv_buf_data <= {recv_buf_data, recv_pattern};
+ end
+ recv_state <= 0;
+ end
+ end
+ default: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+
+endmodule
diff --git a/caravel/verilog/dv/dummy_slave.v b/caravel/verilog/dv/dummy_slave.v
new file mode 100644
index 0000000..be068fc
--- /dev/null
+++ b/caravel/verilog/dv/dummy_slave.v
@@ -0,0 +1,49 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+module dummy_slave(
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input wb_stb_i,
+ input wb_cyc_i,
+ input wb_we_i,
+ input [3:0] wb_sel_i,
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+
+ output reg [31:0] wb_dat_o,
+ output reg wb_ack_o
+);
+ reg [31:0] store;
+
+ wire valid = wb_cyc_i & wb_stb_i;
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i == 1'b 1) begin
+ wb_ack_o <= 1'b 0;
+ end else begin
+ if (wb_we_i == 1'b 1) begin
+ if (wb_sel_i[0]) store[7:0] <= wb_dat_i[7:0];
+ if (wb_sel_i[1]) store[15:8] <= wb_dat_i[15:8];
+ if (wb_sel_i[2]) store[23:16] <= wb_dat_i[23:16];
+ if (wb_sel_i[3]) store[31:24] <= wb_dat_i[31:24];
+ end
+ wb_dat_o <= store;
+ wb_ack_o <= valid & !wb_ack_o;
+ end
+ end
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/Makefile b/caravel/verilog/dv/wb_utests/Makefile
new file mode 100644
index 0000000..cd86cb8
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_wb intercon_wb la_wb mem_wb mprj_ctrl spi_sysctrl_wb spimemio_wb uart_wb storage_wb mgmt_protect chip_io
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/chip_io/Makefile b/caravel/verilog/dv/wb_utests/chip_io/Makefile
new file mode 100644
index 0000000..4bd731a
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/Makefile
@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = chip_io
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+ifeq ($(SIM),SPLIT_BUS)
+ iverilog -Ttyp -DFUNCTIONAL -DSPLIT_BUS -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+ifeq ($(SIM),GL)
+ iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v b/caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v
new file mode 100644
index 0000000..62a1cb2
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v
@@ -0,0 +1,4218 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module chip_io(vddio, vssio, vccd, vssd, vdda, vssa, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1, porb_h, por, resetb_core_h, clock_core, gpio_out_core, gpio_in_core, gpio_mode0_core, gpio_mode1_core, gpio_outenb_core, gpio_inenb_core, flash_csb_core, flash_clk_core, flash_csb_oeb_core, flash_clk_oeb_core, flash_io0_oeb_core, flash_io1_oeb_core, flash_csb_ieb_core, flash_clk_ieb_core, flash_io0_ieb_core, flash_io1_ieb_core, flash_io0_do_core, flash_io1_do_core, flash_io0_di_core, flash_io1_di_core, \mprj_io[0] , \mprj_io[1] , \mprj_io[2] , \mprj_io[3] , \mprj_io[4] , \mprj_io[5] , \mprj_io[6] , \mprj_io[7] , \mprj_io[8] , \mprj_io[9] , \mprj_io[10] , \mprj_io[11] , \mprj_io[12] , \mprj_io[13] , \mprj_io[14] , \mprj_io[15] , \mprj_io[16] , \mprj_io[17] , \mprj_io[18] , \mprj_io[19] , \mprj_io[20] , \mprj_io[21] , \mprj_io[22] , \mprj_io[23] , \mprj_io[24] , \mprj_io[25] , \mprj_io[26] , \mprj_io[27] , \mprj_io[28] , \mprj_io[29] , \mprj_io[30] , \mprj_io[31] , \mprj_io[32] , \mprj_io[33] , \mprj_io[34] , \mprj_io[35] , \mprj_io[36] , \mprj_io[37] , \mprj_io_out[0] , \mprj_io_out[1] , \mprj_io_out[2] , \mprj_io_out[3] , \mprj_io_out[4] , \mprj_io_out[5] , \mprj_io_out[6] , \mprj_io_out[7] , \mprj_io_out[8] , \mprj_io_out[9] , \mprj_io_out[10] , \mprj_io_out[11] , \mprj_io_out[12] , \mprj_io_out[13] , \mprj_io_out[14] , \mprj_io_out[15] , \mprj_io_out[16] , \mprj_io_out[17] , \mprj_io_out[18] , \mprj_io_out[19] , \mprj_io_out[20] , \mprj_io_out[21] , \mprj_io_out[22] , \mprj_io_out[23] , \mprj_io_out[24] , \mprj_io_out[25] , \mprj_io_out[26] , \mprj_io_out[27] , \mprj_io_out[28] , \mprj_io_out[29] , \mprj_io_out[30] , \mprj_io_out[31] , \mprj_io_out[32] , \mprj_io_out[33] , \mprj_io_out[34] , \mprj_io_out[35] , \mprj_io_out[36] , \mprj_io_out[37] , \mprj_io_oeb[0] , \mprj_io_oeb[1] , \mprj_io_oeb[2] , \mprj_io_oeb[3] , \mprj_io_oeb[4] , \mprj_io_oeb[5] , \mprj_io_oeb[6] , \mprj_io_oeb[7] , \mprj_io_oeb[8] , \mprj_io_oeb[9] , \mprj_io_oeb[10] , \mprj_io_oeb[11] , \mprj_io_oeb[12] , \mprj_io_oeb[13] , \mprj_io_oeb[14] , \mprj_io_oeb[15] , \mprj_io_oeb[16] , \mprj_io_oeb[17] , \mprj_io_oeb[18] , \mprj_io_oeb[19] , \mprj_io_oeb[20] , \mprj_io_oeb[21] , \mprj_io_oeb[22] , \mprj_io_oeb[23] , \mprj_io_oeb[24] , \mprj_io_oeb[25] , \mprj_io_oeb[26] , \mprj_io_oeb[27] , \mprj_io_oeb[28] , \mprj_io_oeb[29] , \mprj_io_oeb[30] , \mprj_io_oeb[31] , \mprj_io_oeb[32] , \mprj_io_oeb[33] , \mprj_io_oeb[34] , \mprj_io_oeb[35] , \mprj_io_oeb[36] , \mprj_io_oeb[37] , \mprj_io_hldh_n[0] , \mprj_io_hldh_n[1] , \mprj_io_hldh_n[2] , \mprj_io_hldh_n[3] , \mprj_io_hldh_n[4] , \mprj_io_hldh_n[5] , \mprj_io_hldh_n[6] , \mprj_io_hldh_n[7] , \mprj_io_hldh_n[8] , \mprj_io_hldh_n[9] , \mprj_io_hldh_n[10] , \mprj_io_hldh_n[11] , \mprj_io_hldh_n[12] , \mprj_io_hldh_n[13] , \mprj_io_hldh_n[14] , \mprj_io_hldh_n[15] , \mprj_io_hldh_n[16] , \mprj_io_hldh_n[17] , \mprj_io_hldh_n[18] , \mprj_io_hldh_n[19] , \mprj_io_hldh_n[20] , \mprj_io_hldh_n[21] , \mprj_io_hldh_n[22] , \mprj_io_hldh_n[23] , \mprj_io_hldh_n[24] , \mprj_io_hldh_n[25] , \mprj_io_hldh_n[26] , \mprj_io_hldh_n[27] , \mprj_io_hldh_n[28] , \mprj_io_hldh_n[29] , \mprj_io_hldh_n[30] , \mprj_io_hldh_n[31] , \mprj_io_hldh_n[32] , \mprj_io_hldh_n[33] , \mprj_io_hldh_n[34] , \mprj_io_hldh_n[35] , \mprj_io_hldh_n[36] , \mprj_io_hldh_n[37] , \mprj_io_enh[0] , \mprj_io_enh[1] , \mprj_io_enh[2] , \mprj_io_enh[3] , \mprj_io_enh[4] , \mprj_io_enh[5] , \mprj_io_enh[6] , \mprj_io_enh[7] , \mprj_io_enh[8] , \mprj_io_enh[9] , \mprj_io_enh[10] , \mprj_io_enh[11] , \mprj_io_enh[12] , \mprj_io_enh[13] , \mprj_io_enh[14] , \mprj_io_enh[15] , \mprj_io_enh[16] , \mprj_io_enh[17] , \mprj_io_enh[18] , \mprj_io_enh[19] , \mprj_io_enh[20] , \mprj_io_enh[21] , \mprj_io_enh[22] , \mprj_io_enh[23] , \mprj_io_enh[24] , \mprj_io_enh[25] , \mprj_io_enh[26] , \mprj_io_enh[27] , \mprj_io_enh[28] , \mprj_io_enh[29] , \mprj_io_enh[30] , \mprj_io_enh[31] , \mprj_io_enh[32] , \mprj_io_enh[33] , \mprj_io_enh[34] , \mprj_io_enh[35] , \mprj_io_enh[36] , \mprj_io_enh[37] , \mprj_io_inp_dis[0] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[37] , \mprj_io_ib_mode_sel[0] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[37] , \mprj_io_vtrip_sel[0] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[37] , \mprj_io_slow_sel[0] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[37] , \mprj_io_holdover[0] , \mprj_io_holdover[1] , \mprj_io_holdover[2] , \mprj_io_holdover[3] , \mprj_io_holdover[4] , \mprj_io_holdover[5] , \mprj_io_holdover[6] , \mprj_io_holdover[7] , \mprj_io_holdover[8] , \mprj_io_holdover[9] , \mprj_io_holdover[10] , \mprj_io_holdover[11] , \mprj_io_holdover[12] , \mprj_io_holdover[13] , \mprj_io_holdover[14] , \mprj_io_holdover[15] , \mprj_io_holdover[16] , \mprj_io_holdover[17] , \mprj_io_holdover[18] , \mprj_io_holdover[19] , \mprj_io_holdover[20] , \mprj_io_holdover[21] , \mprj_io_holdover[22] , \mprj_io_holdover[23] , \mprj_io_holdover[24] , \mprj_io_holdover[25] , \mprj_io_holdover[26] , \mprj_io_holdover[27] , \mprj_io_holdover[28] , \mprj_io_holdover[29] , \mprj_io_holdover[30] , \mprj_io_holdover[31] , \mprj_io_holdover[32] , \mprj_io_holdover[33] , \mprj_io_holdover[34] , \mprj_io_holdover[35] , \mprj_io_holdover[36] , \mprj_io_holdover[37] , \mprj_io_analog_en[0] , \mprj_io_analog_en[1] , \mprj_io_analog_en[2] , \mprj_io_analog_en[3] , \mprj_io_analog_en[4] , \mprj_io_analog_en[5] , \mprj_io_analog_en[6] , \mprj_io_analog_en[7] , \mprj_io_analog_en[8] , \mprj_io_analog_en[9] , \mprj_io_analog_en[10] , \mprj_io_analog_en[11] , \mprj_io_analog_en[12] , \mprj_io_analog_en[13] , \mprj_io_analog_en[14] , \mprj_io_analog_en[15] , \mprj_io_analog_en[16] , \mprj_io_analog_en[17] , \mprj_io_analog_en[18] , \mprj_io_analog_en[19] , \mprj_io_analog_en[20] , \mprj_io_analog_en[21] , \mprj_io_analog_en[22] , \mprj_io_analog_en[23] , \mprj_io_analog_en[24] , \mprj_io_analog_en[25] , \mprj_io_analog_en[26] , \mprj_io_analog_en[27] , \mprj_io_analog_en[28] , \mprj_io_analog_en[29] , \mprj_io_analog_en[30] , \mprj_io_analog_en[31] , \mprj_io_analog_en[32] , \mprj_io_analog_en[33] , \mprj_io_analog_en[34] , \mprj_io_analog_en[35] , \mprj_io_analog_en[36] , \mprj_io_analog_en[37] , \mprj_io_analog_sel[0] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[37] , \mprj_io_analog_pol[0] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[37] , \mprj_io_dm[0] , \mprj_io_dm[1] , \mprj_io_dm[2] , \mprj_io_dm[3] , \mprj_io_dm[4] , \mprj_io_dm[5] , \mprj_io_dm[6] , \mprj_io_dm[7] , \mprj_io_dm[8] , \mprj_io_dm[9] , \mprj_io_dm[10] , \mprj_io_dm[11] , \mprj_io_dm[12] , \mprj_io_dm[13] , \mprj_io_dm[14] , \mprj_io_dm[15] , \mprj_io_dm[16] , \mprj_io_dm[17] , \mprj_io_dm[18] , \mprj_io_dm[19] , \mprj_io_dm[20] , \mprj_io_dm[21] , \mprj_io_dm[22] , \mprj_io_dm[23] , \mprj_io_dm[24] , \mprj_io_dm[25] , \mprj_io_dm[26] , \mprj_io_dm[27] , \mprj_io_dm[28] , \mprj_io_dm[29] , \mprj_io_dm[30] , \mprj_io_dm[31] , \mprj_io_dm[32] , \mprj_io_dm[33] , \mprj_io_dm[34] , \mprj_io_dm[35] , \mprj_io_dm[36] , \mprj_io_dm[37] , \mprj_io_dm[38] , \mprj_io_dm[39] , \mprj_io_dm[40] , \mprj_io_dm[41] , \mprj_io_dm[42] , \mprj_io_dm[43] , \mprj_io_dm[44] , \mprj_io_dm[45] , \mprj_io_dm[46] , \mprj_io_dm[47] , \mprj_io_dm[48] , \mprj_io_dm[49] , \mprj_io_dm[50] , \mprj_io_dm[51] , \mprj_io_dm[52] , \mprj_io_dm[53] , \mprj_io_dm[54] , \mprj_io_dm[55] , \mprj_io_dm[56] , \mprj_io_dm[57] , \mprj_io_dm[58] , \mprj_io_dm[59] , \mprj_io_dm[60] , \mprj_io_dm[61] , \mprj_io_dm[62] , \mprj_io_dm[63] , \mprj_io_dm[64] , \mprj_io_dm[65] , \mprj_io_dm[66] , \mprj_io_dm[67] , \mprj_io_dm[68] , \mprj_io_dm[69] , \mprj_io_dm[70] , \mprj_io_dm[71] , \mprj_io_dm[72] , \mprj_io_dm[73] , \mprj_io_dm[74] , \mprj_io_dm[75] , \mprj_io_dm[76] , \mprj_io_dm[77] , \mprj_io_dm[78] , \mprj_io_dm[79] , \mprj_io_dm[80] , \mprj_io_dm[81] , \mprj_io_dm[82] , \mprj_io_dm[83] , \mprj_io_dm[84] , \mprj_io_dm[85] , \mprj_io_dm[86] , \mprj_io_dm[87] , \mprj_io_dm[88] , \mprj_io_dm[89] , \mprj_io_dm[90] , \mprj_io_dm[91] , \mprj_io_dm[92] , \mprj_io_dm[93] , \mprj_io_dm[94] , \mprj_io_dm[95] , \mprj_io_dm[96] , \mprj_io_dm[97] , \mprj_io_dm[98] , \mprj_io_dm[99] , \mprj_io_dm[100] , \mprj_io_dm[101] , \mprj_io_dm[102] , \mprj_io_dm[103] , \mprj_io_dm[104] , \mprj_io_dm[105] , \mprj_io_dm[106] , \mprj_io_dm[107] , \mprj_io_dm[108] , \mprj_io_dm[109] , \mprj_io_dm[110] , \mprj_io_dm[111] , \mprj_io_dm[112] , \mprj_io_dm[113] , \mprj_io_in[0] , \mprj_io_in[1] , \mprj_io_in[2] , \mprj_io_in[3] , \mprj_io_in[4] , \mprj_io_in[5] , \mprj_io_in[6] , \mprj_io_in[7] , \mprj_io_in[8] , \mprj_io_in[9] , \mprj_io_in[10] , \mprj_io_in[11] , \mprj_io_in[12] , \mprj_io_in[13] , \mprj_io_in[14] , \mprj_io_in[15] , \mprj_io_in[16] , \mprj_io_in[17] , \mprj_io_in[18] , \mprj_io_in[19] , \mprj_io_in[20] , \mprj_io_in[21] , \mprj_io_in[22] , \mprj_io_in[23] , \mprj_io_in[24] , \mprj_io_in[25] , \mprj_io_in[26] , \mprj_io_in[27] , \mprj_io_in[28] , \mprj_io_in[29] , \mprj_io_in[30] , \mprj_io_in[31] , \mprj_io_in[32] , \mprj_io_in[33] , \mprj_io_in[34] , \mprj_io_in[35] , \mprj_io_in[36] , \mprj_io_in[37] , \mprj_analog_io[0] , \mprj_analog_io[1] , \mprj_analog_io[2] , \mprj_analog_io[3] , \mprj_analog_io[4] , \mprj_analog_io[5] , \mprj_analog_io[6] , \mprj_analog_io[7] , \mprj_analog_io[8] , \mprj_analog_io[9] , \mprj_analog_io[10] , \mprj_analog_io[11] , \mprj_analog_io[12] , \mprj_analog_io[13] , \mprj_analog_io[14] , \mprj_analog_io[15] , \mprj_analog_io[16] , \mprj_analog_io[17] , \mprj_analog_io[18] , \mprj_analog_io[19] , \mprj_analog_io[20] , \mprj_analog_io[21] , \mprj_analog_io[22] , \mprj_analog_io[23] , \mprj_analog_io[24] , \mprj_analog_io[25] , \mprj_analog_io[26] , \mprj_analog_io[27] , \mprj_analog_io[28] , \mprj_analog_io[29] , \mprj_analog_io[30] );
+ wire analog_a;
+ wire analog_b;
+ input clock;
+ output clock_core;
+ wire \dm_all[0] ;
+ wire \dm_all[1] ;
+ wire \dm_all[2] ;
+ output flash_clk;
+ input flash_clk_core;
+ input flash_clk_ieb_core;
+ input flash_clk_oeb_core;
+ output flash_csb;
+ input flash_csb_core;
+ input flash_csb_ieb_core;
+ input flash_csb_oeb_core;
+ inout flash_io0;
+ output flash_io0_di_core;
+ input flash_io0_do_core;
+ input flash_io0_ieb_core;
+ wire \flash_io0_mode[0] ;
+ wire \flash_io0_mode[1] ;
+ wire \flash_io0_mode[2] ;
+ input flash_io0_oeb_core;
+ inout flash_io1;
+ output flash_io1_di_core;
+ input flash_io1_do_core;
+ input flash_io1_ieb_core;
+ wire \flash_io1_mode[0] ;
+ wire \flash_io1_mode[1] ;
+ wire \flash_io1_mode[2] ;
+ input flash_io1_oeb_core;
+ inout gpio;
+ output gpio_in_core;
+ input gpio_inenb_core;
+ input gpio_mode0_core;
+ input gpio_mode1_core;
+ input gpio_out_core;
+ input gpio_outenb_core;
+ wire loop_clock;
+ wire loop_flash_clk;
+ wire loop_flash_csb;
+ wire loop_flash_io0;
+ wire loop_flash_io1;
+ wire loop_gpio;
+ inout \mprj_analog_io[0] ;
+ inout \mprj_analog_io[10] ;
+ inout \mprj_analog_io[11] ;
+ inout \mprj_analog_io[12] ;
+ inout \mprj_analog_io[13] ;
+ inout \mprj_analog_io[14] ;
+ inout \mprj_analog_io[15] ;
+ inout \mprj_analog_io[16] ;
+ inout \mprj_analog_io[17] ;
+ inout \mprj_analog_io[18] ;
+ inout \mprj_analog_io[19] ;
+ inout \mprj_analog_io[1] ;
+ inout \mprj_analog_io[20] ;
+ inout \mprj_analog_io[21] ;
+ inout \mprj_analog_io[22] ;
+ inout \mprj_analog_io[23] ;
+ inout \mprj_analog_io[24] ;
+ inout \mprj_analog_io[25] ;
+ inout \mprj_analog_io[26] ;
+ inout \mprj_analog_io[27] ;
+ inout \mprj_analog_io[28] ;
+ inout \mprj_analog_io[29] ;
+ inout \mprj_analog_io[2] ;
+ inout \mprj_analog_io[30] ;
+ inout \mprj_analog_io[3] ;
+ inout \mprj_analog_io[4] ;
+ inout \mprj_analog_io[5] ;
+ inout \mprj_analog_io[6] ;
+ inout \mprj_analog_io[7] ;
+ inout \mprj_analog_io[8] ;
+ inout \mprj_analog_io[9] ;
+ inout \mprj_io[0] ;
+ inout \mprj_io[10] ;
+ inout \mprj_io[11] ;
+ inout \mprj_io[12] ;
+ inout \mprj_io[13] ;
+ inout \mprj_io[14] ;
+ inout \mprj_io[15] ;
+ inout \mprj_io[16] ;
+ inout \mprj_io[17] ;
+ inout \mprj_io[18] ;
+ inout \mprj_io[19] ;
+ inout \mprj_io[1] ;
+ inout \mprj_io[20] ;
+ inout \mprj_io[21] ;
+ inout \mprj_io[22] ;
+ inout \mprj_io[23] ;
+ inout \mprj_io[24] ;
+ inout \mprj_io[25] ;
+ inout \mprj_io[26] ;
+ inout \mprj_io[27] ;
+ inout \mprj_io[28] ;
+ inout \mprj_io[29] ;
+ inout \mprj_io[2] ;
+ inout \mprj_io[30] ;
+ inout \mprj_io[31] ;
+ inout \mprj_io[32] ;
+ inout \mprj_io[33] ;
+ inout \mprj_io[34] ;
+ inout \mprj_io[35] ;
+ inout \mprj_io[36] ;
+ inout \mprj_io[37] ;
+ inout \mprj_io[3] ;
+ inout \mprj_io[4] ;
+ inout \mprj_io[5] ;
+ inout \mprj_io[6] ;
+ inout \mprj_io[7] ;
+ inout \mprj_io[8] ;
+ inout \mprj_io[9] ;
+ input \mprj_io_analog_en[0] ;
+ input \mprj_io_analog_en[10] ;
+ input \mprj_io_analog_en[11] ;
+ input \mprj_io_analog_en[12] ;
+ input \mprj_io_analog_en[13] ;
+ input \mprj_io_analog_en[14] ;
+ input \mprj_io_analog_en[15] ;
+ input \mprj_io_analog_en[16] ;
+ input \mprj_io_analog_en[17] ;
+ input \mprj_io_analog_en[18] ;
+ input \mprj_io_analog_en[19] ;
+ input \mprj_io_analog_en[1] ;
+ input \mprj_io_analog_en[20] ;
+ input \mprj_io_analog_en[21] ;
+ input \mprj_io_analog_en[22] ;
+ input \mprj_io_analog_en[23] ;
+ input \mprj_io_analog_en[24] ;
+ input \mprj_io_analog_en[25] ;
+ input \mprj_io_analog_en[26] ;
+ input \mprj_io_analog_en[27] ;
+ input \mprj_io_analog_en[28] ;
+ input \mprj_io_analog_en[29] ;
+ input \mprj_io_analog_en[2] ;
+ input \mprj_io_analog_en[30] ;
+ input \mprj_io_analog_en[31] ;
+ input \mprj_io_analog_en[32] ;
+ input \mprj_io_analog_en[33] ;
+ input \mprj_io_analog_en[34] ;
+ input \mprj_io_analog_en[35] ;
+ input \mprj_io_analog_en[36] ;
+ input \mprj_io_analog_en[37] ;
+ input \mprj_io_analog_en[3] ;
+ input \mprj_io_analog_en[4] ;
+ input \mprj_io_analog_en[5] ;
+ input \mprj_io_analog_en[6] ;
+ input \mprj_io_analog_en[7] ;
+ input \mprj_io_analog_en[8] ;
+ input \mprj_io_analog_en[9] ;
+ input \mprj_io_analog_pol[0] ;
+ input \mprj_io_analog_pol[10] ;
+ input \mprj_io_analog_pol[11] ;
+ input \mprj_io_analog_pol[12] ;
+ input \mprj_io_analog_pol[13] ;
+ input \mprj_io_analog_pol[14] ;
+ input \mprj_io_analog_pol[15] ;
+ input \mprj_io_analog_pol[16] ;
+ input \mprj_io_analog_pol[17] ;
+ input \mprj_io_analog_pol[18] ;
+ input \mprj_io_analog_pol[19] ;
+ input \mprj_io_analog_pol[1] ;
+ input \mprj_io_analog_pol[20] ;
+ input \mprj_io_analog_pol[21] ;
+ input \mprj_io_analog_pol[22] ;
+ input \mprj_io_analog_pol[23] ;
+ input \mprj_io_analog_pol[24] ;
+ input \mprj_io_analog_pol[25] ;
+ input \mprj_io_analog_pol[26] ;
+ input \mprj_io_analog_pol[27] ;
+ input \mprj_io_analog_pol[28] ;
+ input \mprj_io_analog_pol[29] ;
+ input \mprj_io_analog_pol[2] ;
+ input \mprj_io_analog_pol[30] ;
+ input \mprj_io_analog_pol[31] ;
+ input \mprj_io_analog_pol[32] ;
+ input \mprj_io_analog_pol[33] ;
+ input \mprj_io_analog_pol[34] ;
+ input \mprj_io_analog_pol[35] ;
+ input \mprj_io_analog_pol[36] ;
+ input \mprj_io_analog_pol[37] ;
+ input \mprj_io_analog_pol[3] ;
+ input \mprj_io_analog_pol[4] ;
+ input \mprj_io_analog_pol[5] ;
+ input \mprj_io_analog_pol[6] ;
+ input \mprj_io_analog_pol[7] ;
+ input \mprj_io_analog_pol[8] ;
+ input \mprj_io_analog_pol[9] ;
+ input \mprj_io_analog_sel[0] ;
+ input \mprj_io_analog_sel[10] ;
+ input \mprj_io_analog_sel[11] ;
+ input \mprj_io_analog_sel[12] ;
+ input \mprj_io_analog_sel[13] ;
+ input \mprj_io_analog_sel[14] ;
+ input \mprj_io_analog_sel[15] ;
+ input \mprj_io_analog_sel[16] ;
+ input \mprj_io_analog_sel[17] ;
+ input \mprj_io_analog_sel[18] ;
+ input \mprj_io_analog_sel[19] ;
+ input \mprj_io_analog_sel[1] ;
+ input \mprj_io_analog_sel[20] ;
+ input \mprj_io_analog_sel[21] ;
+ input \mprj_io_analog_sel[22] ;
+ input \mprj_io_analog_sel[23] ;
+ input \mprj_io_analog_sel[24] ;
+ input \mprj_io_analog_sel[25] ;
+ input \mprj_io_analog_sel[26] ;
+ input \mprj_io_analog_sel[27] ;
+ input \mprj_io_analog_sel[28] ;
+ input \mprj_io_analog_sel[29] ;
+ input \mprj_io_analog_sel[2] ;
+ input \mprj_io_analog_sel[30] ;
+ input \mprj_io_analog_sel[31] ;
+ input \mprj_io_analog_sel[32] ;
+ input \mprj_io_analog_sel[33] ;
+ input \mprj_io_analog_sel[34] ;
+ input \mprj_io_analog_sel[35] ;
+ input \mprj_io_analog_sel[36] ;
+ input \mprj_io_analog_sel[37] ;
+ input \mprj_io_analog_sel[3] ;
+ input \mprj_io_analog_sel[4] ;
+ input \mprj_io_analog_sel[5] ;
+ input \mprj_io_analog_sel[6] ;
+ input \mprj_io_analog_sel[7] ;
+ input \mprj_io_analog_sel[8] ;
+ input \mprj_io_analog_sel[9] ;
+ input \mprj_io_dm[0] ;
+ input \mprj_io_dm[100] ;
+ input \mprj_io_dm[101] ;
+ input \mprj_io_dm[102] ;
+ input \mprj_io_dm[103] ;
+ input \mprj_io_dm[104] ;
+ input \mprj_io_dm[105] ;
+ input \mprj_io_dm[106] ;
+ input \mprj_io_dm[107] ;
+ input \mprj_io_dm[108] ;
+ input \mprj_io_dm[109] ;
+ input \mprj_io_dm[10] ;
+ input \mprj_io_dm[110] ;
+ input \mprj_io_dm[111] ;
+ input \mprj_io_dm[112] ;
+ input \mprj_io_dm[113] ;
+ input \mprj_io_dm[11] ;
+ input \mprj_io_dm[12] ;
+ input \mprj_io_dm[13] ;
+ input \mprj_io_dm[14] ;
+ input \mprj_io_dm[15] ;
+ input \mprj_io_dm[16] ;
+ input \mprj_io_dm[17] ;
+ input \mprj_io_dm[18] ;
+ input \mprj_io_dm[19] ;
+ input \mprj_io_dm[1] ;
+ input \mprj_io_dm[20] ;
+ input \mprj_io_dm[21] ;
+ input \mprj_io_dm[22] ;
+ input \mprj_io_dm[23] ;
+ input \mprj_io_dm[24] ;
+ input \mprj_io_dm[25] ;
+ input \mprj_io_dm[26] ;
+ input \mprj_io_dm[27] ;
+ input \mprj_io_dm[28] ;
+ input \mprj_io_dm[29] ;
+ input \mprj_io_dm[2] ;
+ input \mprj_io_dm[30] ;
+ input \mprj_io_dm[31] ;
+ input \mprj_io_dm[32] ;
+ input \mprj_io_dm[33] ;
+ input \mprj_io_dm[34] ;
+ input \mprj_io_dm[35] ;
+ input \mprj_io_dm[36] ;
+ input \mprj_io_dm[37] ;
+ input \mprj_io_dm[38] ;
+ input \mprj_io_dm[39] ;
+ input \mprj_io_dm[3] ;
+ input \mprj_io_dm[40] ;
+ input \mprj_io_dm[41] ;
+ input \mprj_io_dm[42] ;
+ input \mprj_io_dm[43] ;
+ input \mprj_io_dm[44] ;
+ input \mprj_io_dm[45] ;
+ input \mprj_io_dm[46] ;
+ input \mprj_io_dm[47] ;
+ input \mprj_io_dm[48] ;
+ input \mprj_io_dm[49] ;
+ input \mprj_io_dm[4] ;
+ input \mprj_io_dm[50] ;
+ input \mprj_io_dm[51] ;
+ input \mprj_io_dm[52] ;
+ input \mprj_io_dm[53] ;
+ input \mprj_io_dm[54] ;
+ input \mprj_io_dm[55] ;
+ input \mprj_io_dm[56] ;
+ input \mprj_io_dm[57] ;
+ input \mprj_io_dm[58] ;
+ input \mprj_io_dm[59] ;
+ input \mprj_io_dm[5] ;
+ input \mprj_io_dm[60] ;
+ input \mprj_io_dm[61] ;
+ input \mprj_io_dm[62] ;
+ input \mprj_io_dm[63] ;
+ input \mprj_io_dm[64] ;
+ input \mprj_io_dm[65] ;
+ input \mprj_io_dm[66] ;
+ input \mprj_io_dm[67] ;
+ input \mprj_io_dm[68] ;
+ input \mprj_io_dm[69] ;
+ input \mprj_io_dm[6] ;
+ input \mprj_io_dm[70] ;
+ input \mprj_io_dm[71] ;
+ input \mprj_io_dm[72] ;
+ input \mprj_io_dm[73] ;
+ input \mprj_io_dm[74] ;
+ input \mprj_io_dm[75] ;
+ input \mprj_io_dm[76] ;
+ input \mprj_io_dm[77] ;
+ input \mprj_io_dm[78] ;
+ input \mprj_io_dm[79] ;
+ input \mprj_io_dm[7] ;
+ input \mprj_io_dm[80] ;
+ input \mprj_io_dm[81] ;
+ input \mprj_io_dm[82] ;
+ input \mprj_io_dm[83] ;
+ input \mprj_io_dm[84] ;
+ input \mprj_io_dm[85] ;
+ input \mprj_io_dm[86] ;
+ input \mprj_io_dm[87] ;
+ input \mprj_io_dm[88] ;
+ input \mprj_io_dm[89] ;
+ input \mprj_io_dm[8] ;
+ input \mprj_io_dm[90] ;
+ input \mprj_io_dm[91] ;
+ input \mprj_io_dm[92] ;
+ input \mprj_io_dm[93] ;
+ input \mprj_io_dm[94] ;
+ input \mprj_io_dm[95] ;
+ input \mprj_io_dm[96] ;
+ input \mprj_io_dm[97] ;
+ input \mprj_io_dm[98] ;
+ input \mprj_io_dm[99] ;
+ input \mprj_io_dm[9] ;
+ input \mprj_io_enh[0] ;
+ input \mprj_io_enh[10] ;
+ input \mprj_io_enh[11] ;
+ input \mprj_io_enh[12] ;
+ input \mprj_io_enh[13] ;
+ input \mprj_io_enh[14] ;
+ input \mprj_io_enh[15] ;
+ input \mprj_io_enh[16] ;
+ input \mprj_io_enh[17] ;
+ input \mprj_io_enh[18] ;
+ input \mprj_io_enh[19] ;
+ input \mprj_io_enh[1] ;
+ input \mprj_io_enh[20] ;
+ input \mprj_io_enh[21] ;
+ input \mprj_io_enh[22] ;
+ input \mprj_io_enh[23] ;
+ input \mprj_io_enh[24] ;
+ input \mprj_io_enh[25] ;
+ input \mprj_io_enh[26] ;
+ input \mprj_io_enh[27] ;
+ input \mprj_io_enh[28] ;
+ input \mprj_io_enh[29] ;
+ input \mprj_io_enh[2] ;
+ input \mprj_io_enh[30] ;
+ input \mprj_io_enh[31] ;
+ input \mprj_io_enh[32] ;
+ input \mprj_io_enh[33] ;
+ input \mprj_io_enh[34] ;
+ input \mprj_io_enh[35] ;
+ input \mprj_io_enh[36] ;
+ input \mprj_io_enh[37] ;
+ input \mprj_io_enh[3] ;
+ input \mprj_io_enh[4] ;
+ input \mprj_io_enh[5] ;
+ input \mprj_io_enh[6] ;
+ input \mprj_io_enh[7] ;
+ input \mprj_io_enh[8] ;
+ input \mprj_io_enh[9] ;
+ input \mprj_io_hldh_n[0] ;
+ input \mprj_io_hldh_n[10] ;
+ input \mprj_io_hldh_n[11] ;
+ input \mprj_io_hldh_n[12] ;
+ input \mprj_io_hldh_n[13] ;
+ input \mprj_io_hldh_n[14] ;
+ input \mprj_io_hldh_n[15] ;
+ input \mprj_io_hldh_n[16] ;
+ input \mprj_io_hldh_n[17] ;
+ input \mprj_io_hldh_n[18] ;
+ input \mprj_io_hldh_n[19] ;
+ input \mprj_io_hldh_n[1] ;
+ input \mprj_io_hldh_n[20] ;
+ input \mprj_io_hldh_n[21] ;
+ input \mprj_io_hldh_n[22] ;
+ input \mprj_io_hldh_n[23] ;
+ input \mprj_io_hldh_n[24] ;
+ input \mprj_io_hldh_n[25] ;
+ input \mprj_io_hldh_n[26] ;
+ input \mprj_io_hldh_n[27] ;
+ input \mprj_io_hldh_n[28] ;
+ input \mprj_io_hldh_n[29] ;
+ input \mprj_io_hldh_n[2] ;
+ input \mprj_io_hldh_n[30] ;
+ input \mprj_io_hldh_n[31] ;
+ input \mprj_io_hldh_n[32] ;
+ input \mprj_io_hldh_n[33] ;
+ input \mprj_io_hldh_n[34] ;
+ input \mprj_io_hldh_n[35] ;
+ input \mprj_io_hldh_n[36] ;
+ input \mprj_io_hldh_n[37] ;
+ input \mprj_io_hldh_n[3] ;
+ input \mprj_io_hldh_n[4] ;
+ input \mprj_io_hldh_n[5] ;
+ input \mprj_io_hldh_n[6] ;
+ input \mprj_io_hldh_n[7] ;
+ input \mprj_io_hldh_n[8] ;
+ input \mprj_io_hldh_n[9] ;
+ input \mprj_io_holdover[0] ;
+ input \mprj_io_holdover[10] ;
+ input \mprj_io_holdover[11] ;
+ input \mprj_io_holdover[12] ;
+ input \mprj_io_holdover[13] ;
+ input \mprj_io_holdover[14] ;
+ input \mprj_io_holdover[15] ;
+ input \mprj_io_holdover[16] ;
+ input \mprj_io_holdover[17] ;
+ input \mprj_io_holdover[18] ;
+ input \mprj_io_holdover[19] ;
+ input \mprj_io_holdover[1] ;
+ input \mprj_io_holdover[20] ;
+ input \mprj_io_holdover[21] ;
+ input \mprj_io_holdover[22] ;
+ input \mprj_io_holdover[23] ;
+ input \mprj_io_holdover[24] ;
+ input \mprj_io_holdover[25] ;
+ input \mprj_io_holdover[26] ;
+ input \mprj_io_holdover[27] ;
+ input \mprj_io_holdover[28] ;
+ input \mprj_io_holdover[29] ;
+ input \mprj_io_holdover[2] ;
+ input \mprj_io_holdover[30] ;
+ input \mprj_io_holdover[31] ;
+ input \mprj_io_holdover[32] ;
+ input \mprj_io_holdover[33] ;
+ input \mprj_io_holdover[34] ;
+ input \mprj_io_holdover[35] ;
+ input \mprj_io_holdover[36] ;
+ input \mprj_io_holdover[37] ;
+ input \mprj_io_holdover[3] ;
+ input \mprj_io_holdover[4] ;
+ input \mprj_io_holdover[5] ;
+ input \mprj_io_holdover[6] ;
+ input \mprj_io_holdover[7] ;
+ input \mprj_io_holdover[8] ;
+ input \mprj_io_holdover[9] ;
+ input \mprj_io_ib_mode_sel[0] ;
+ input \mprj_io_ib_mode_sel[10] ;
+ input \mprj_io_ib_mode_sel[11] ;
+ input \mprj_io_ib_mode_sel[12] ;
+ input \mprj_io_ib_mode_sel[13] ;
+ input \mprj_io_ib_mode_sel[14] ;
+ input \mprj_io_ib_mode_sel[15] ;
+ input \mprj_io_ib_mode_sel[16] ;
+ input \mprj_io_ib_mode_sel[17] ;
+ input \mprj_io_ib_mode_sel[18] ;
+ input \mprj_io_ib_mode_sel[19] ;
+ input \mprj_io_ib_mode_sel[1] ;
+ input \mprj_io_ib_mode_sel[20] ;
+ input \mprj_io_ib_mode_sel[21] ;
+ input \mprj_io_ib_mode_sel[22] ;
+ input \mprj_io_ib_mode_sel[23] ;
+ input \mprj_io_ib_mode_sel[24] ;
+ input \mprj_io_ib_mode_sel[25] ;
+ input \mprj_io_ib_mode_sel[26] ;
+ input \mprj_io_ib_mode_sel[27] ;
+ input \mprj_io_ib_mode_sel[28] ;
+ input \mprj_io_ib_mode_sel[29] ;
+ input \mprj_io_ib_mode_sel[2] ;
+ input \mprj_io_ib_mode_sel[30] ;
+ input \mprj_io_ib_mode_sel[31] ;
+ input \mprj_io_ib_mode_sel[32] ;
+ input \mprj_io_ib_mode_sel[33] ;
+ input \mprj_io_ib_mode_sel[34] ;
+ input \mprj_io_ib_mode_sel[35] ;
+ input \mprj_io_ib_mode_sel[36] ;
+ input \mprj_io_ib_mode_sel[37] ;
+ input \mprj_io_ib_mode_sel[3] ;
+ input \mprj_io_ib_mode_sel[4] ;
+ input \mprj_io_ib_mode_sel[5] ;
+ input \mprj_io_ib_mode_sel[6] ;
+ input \mprj_io_ib_mode_sel[7] ;
+ input \mprj_io_ib_mode_sel[8] ;
+ input \mprj_io_ib_mode_sel[9] ;
+ output \mprj_io_in[0] ;
+ output \mprj_io_in[10] ;
+ output \mprj_io_in[11] ;
+ output \mprj_io_in[12] ;
+ output \mprj_io_in[13] ;
+ output \mprj_io_in[14] ;
+ output \mprj_io_in[15] ;
+ output \mprj_io_in[16] ;
+ output \mprj_io_in[17] ;
+ output \mprj_io_in[18] ;
+ output \mprj_io_in[19] ;
+ output \mprj_io_in[1] ;
+ output \mprj_io_in[20] ;
+ output \mprj_io_in[21] ;
+ output \mprj_io_in[22] ;
+ output \mprj_io_in[23] ;
+ output \mprj_io_in[24] ;
+ output \mprj_io_in[25] ;
+ output \mprj_io_in[26] ;
+ output \mprj_io_in[27] ;
+ output \mprj_io_in[28] ;
+ output \mprj_io_in[29] ;
+ output \mprj_io_in[2] ;
+ output \mprj_io_in[30] ;
+ output \mprj_io_in[31] ;
+ output \mprj_io_in[32] ;
+ output \mprj_io_in[33] ;
+ output \mprj_io_in[34] ;
+ output \mprj_io_in[35] ;
+ output \mprj_io_in[36] ;
+ output \mprj_io_in[37] ;
+ output \mprj_io_in[3] ;
+ output \mprj_io_in[4] ;
+ output \mprj_io_in[5] ;
+ output \mprj_io_in[6] ;
+ output \mprj_io_in[7] ;
+ output \mprj_io_in[8] ;
+ output \mprj_io_in[9] ;
+ input \mprj_io_inp_dis[0] ;
+ input \mprj_io_inp_dis[10] ;
+ input \mprj_io_inp_dis[11] ;
+ input \mprj_io_inp_dis[12] ;
+ input \mprj_io_inp_dis[13] ;
+ input \mprj_io_inp_dis[14] ;
+ input \mprj_io_inp_dis[15] ;
+ input \mprj_io_inp_dis[16] ;
+ input \mprj_io_inp_dis[17] ;
+ input \mprj_io_inp_dis[18] ;
+ input \mprj_io_inp_dis[19] ;
+ input \mprj_io_inp_dis[1] ;
+ input \mprj_io_inp_dis[20] ;
+ input \mprj_io_inp_dis[21] ;
+ input \mprj_io_inp_dis[22] ;
+ input \mprj_io_inp_dis[23] ;
+ input \mprj_io_inp_dis[24] ;
+ input \mprj_io_inp_dis[25] ;
+ input \mprj_io_inp_dis[26] ;
+ input \mprj_io_inp_dis[27] ;
+ input \mprj_io_inp_dis[28] ;
+ input \mprj_io_inp_dis[29] ;
+ input \mprj_io_inp_dis[2] ;
+ input \mprj_io_inp_dis[30] ;
+ input \mprj_io_inp_dis[31] ;
+ input \mprj_io_inp_dis[32] ;
+ input \mprj_io_inp_dis[33] ;
+ input \mprj_io_inp_dis[34] ;
+ input \mprj_io_inp_dis[35] ;
+ input \mprj_io_inp_dis[36] ;
+ input \mprj_io_inp_dis[37] ;
+ input \mprj_io_inp_dis[3] ;
+ input \mprj_io_inp_dis[4] ;
+ input \mprj_io_inp_dis[5] ;
+ input \mprj_io_inp_dis[6] ;
+ input \mprj_io_inp_dis[7] ;
+ input \mprj_io_inp_dis[8] ;
+ input \mprj_io_inp_dis[9] ;
+ input \mprj_io_oeb[0] ;
+ input \mprj_io_oeb[10] ;
+ input \mprj_io_oeb[11] ;
+ input \mprj_io_oeb[12] ;
+ input \mprj_io_oeb[13] ;
+ input \mprj_io_oeb[14] ;
+ input \mprj_io_oeb[15] ;
+ input \mprj_io_oeb[16] ;
+ input \mprj_io_oeb[17] ;
+ input \mprj_io_oeb[18] ;
+ input \mprj_io_oeb[19] ;
+ input \mprj_io_oeb[1] ;
+ input \mprj_io_oeb[20] ;
+ input \mprj_io_oeb[21] ;
+ input \mprj_io_oeb[22] ;
+ input \mprj_io_oeb[23] ;
+ input \mprj_io_oeb[24] ;
+ input \mprj_io_oeb[25] ;
+ input \mprj_io_oeb[26] ;
+ input \mprj_io_oeb[27] ;
+ input \mprj_io_oeb[28] ;
+ input \mprj_io_oeb[29] ;
+ input \mprj_io_oeb[2] ;
+ input \mprj_io_oeb[30] ;
+ input \mprj_io_oeb[31] ;
+ input \mprj_io_oeb[32] ;
+ input \mprj_io_oeb[33] ;
+ input \mprj_io_oeb[34] ;
+ input \mprj_io_oeb[35] ;
+ input \mprj_io_oeb[36] ;
+ input \mprj_io_oeb[37] ;
+ input \mprj_io_oeb[3] ;
+ input \mprj_io_oeb[4] ;
+ input \mprj_io_oeb[5] ;
+ input \mprj_io_oeb[6] ;
+ input \mprj_io_oeb[7] ;
+ input \mprj_io_oeb[8] ;
+ input \mprj_io_oeb[9] ;
+ input \mprj_io_out[0] ;
+ input \mprj_io_out[10] ;
+ input \mprj_io_out[11] ;
+ input \mprj_io_out[12] ;
+ input \mprj_io_out[13] ;
+ input \mprj_io_out[14] ;
+ input \mprj_io_out[15] ;
+ input \mprj_io_out[16] ;
+ input \mprj_io_out[17] ;
+ input \mprj_io_out[18] ;
+ input \mprj_io_out[19] ;
+ input \mprj_io_out[1] ;
+ input \mprj_io_out[20] ;
+ input \mprj_io_out[21] ;
+ input \mprj_io_out[22] ;
+ input \mprj_io_out[23] ;
+ input \mprj_io_out[24] ;
+ input \mprj_io_out[25] ;
+ input \mprj_io_out[26] ;
+ input \mprj_io_out[27] ;
+ input \mprj_io_out[28] ;
+ input \mprj_io_out[29] ;
+ input \mprj_io_out[2] ;
+ input \mprj_io_out[30] ;
+ input \mprj_io_out[31] ;
+ input \mprj_io_out[32] ;
+ input \mprj_io_out[33] ;
+ input \mprj_io_out[34] ;
+ input \mprj_io_out[35] ;
+ input \mprj_io_out[36] ;
+ input \mprj_io_out[37] ;
+ input \mprj_io_out[3] ;
+ input \mprj_io_out[4] ;
+ input \mprj_io_out[5] ;
+ input \mprj_io_out[6] ;
+ input \mprj_io_out[7] ;
+ input \mprj_io_out[8] ;
+ input \mprj_io_out[9] ;
+ input \mprj_io_slow_sel[0] ;
+ input \mprj_io_slow_sel[10] ;
+ input \mprj_io_slow_sel[11] ;
+ input \mprj_io_slow_sel[12] ;
+ input \mprj_io_slow_sel[13] ;
+ input \mprj_io_slow_sel[14] ;
+ input \mprj_io_slow_sel[15] ;
+ input \mprj_io_slow_sel[16] ;
+ input \mprj_io_slow_sel[17] ;
+ input \mprj_io_slow_sel[18] ;
+ input \mprj_io_slow_sel[19] ;
+ input \mprj_io_slow_sel[1] ;
+ input \mprj_io_slow_sel[20] ;
+ input \mprj_io_slow_sel[21] ;
+ input \mprj_io_slow_sel[22] ;
+ input \mprj_io_slow_sel[23] ;
+ input \mprj_io_slow_sel[24] ;
+ input \mprj_io_slow_sel[25] ;
+ input \mprj_io_slow_sel[26] ;
+ input \mprj_io_slow_sel[27] ;
+ input \mprj_io_slow_sel[28] ;
+ input \mprj_io_slow_sel[29] ;
+ input \mprj_io_slow_sel[2] ;
+ input \mprj_io_slow_sel[30] ;
+ input \mprj_io_slow_sel[31] ;
+ input \mprj_io_slow_sel[32] ;
+ input \mprj_io_slow_sel[33] ;
+ input \mprj_io_slow_sel[34] ;
+ input \mprj_io_slow_sel[35] ;
+ input \mprj_io_slow_sel[36] ;
+ input \mprj_io_slow_sel[37] ;
+ input \mprj_io_slow_sel[3] ;
+ input \mprj_io_slow_sel[4] ;
+ input \mprj_io_slow_sel[5] ;
+ input \mprj_io_slow_sel[6] ;
+ input \mprj_io_slow_sel[7] ;
+ input \mprj_io_slow_sel[8] ;
+ input \mprj_io_slow_sel[9] ;
+ input \mprj_io_vtrip_sel[0] ;
+ input \mprj_io_vtrip_sel[10] ;
+ input \mprj_io_vtrip_sel[11] ;
+ input \mprj_io_vtrip_sel[12] ;
+ input \mprj_io_vtrip_sel[13] ;
+ input \mprj_io_vtrip_sel[14] ;
+ input \mprj_io_vtrip_sel[15] ;
+ input \mprj_io_vtrip_sel[16] ;
+ input \mprj_io_vtrip_sel[17] ;
+ input \mprj_io_vtrip_sel[18] ;
+ input \mprj_io_vtrip_sel[19] ;
+ input \mprj_io_vtrip_sel[1] ;
+ input \mprj_io_vtrip_sel[20] ;
+ input \mprj_io_vtrip_sel[21] ;
+ input \mprj_io_vtrip_sel[22] ;
+ input \mprj_io_vtrip_sel[23] ;
+ input \mprj_io_vtrip_sel[24] ;
+ input \mprj_io_vtrip_sel[25] ;
+ input \mprj_io_vtrip_sel[26] ;
+ input \mprj_io_vtrip_sel[27] ;
+ input \mprj_io_vtrip_sel[28] ;
+ input \mprj_io_vtrip_sel[29] ;
+ input \mprj_io_vtrip_sel[2] ;
+ input \mprj_io_vtrip_sel[30] ;
+ input \mprj_io_vtrip_sel[31] ;
+ input \mprj_io_vtrip_sel[32] ;
+ input \mprj_io_vtrip_sel[33] ;
+ input \mprj_io_vtrip_sel[34] ;
+ input \mprj_io_vtrip_sel[35] ;
+ input \mprj_io_vtrip_sel[36] ;
+ input \mprj_io_vtrip_sel[37] ;
+ input \mprj_io_vtrip_sel[3] ;
+ input \mprj_io_vtrip_sel[4] ;
+ input \mprj_io_vtrip_sel[5] ;
+ input \mprj_io_vtrip_sel[6] ;
+ input \mprj_io_vtrip_sel[7] ;
+ input \mprj_io_vtrip_sel[8] ;
+ input \mprj_io_vtrip_sel[9] ;
+ wire \mprj_pads.analog_a ;
+ wire \mprj_pads.analog_b ;
+ wire \mprj_pads.analog_en[0] ;
+ wire \mprj_pads.analog_en[10] ;
+ wire \mprj_pads.analog_en[11] ;
+ wire \mprj_pads.analog_en[12] ;
+ wire \mprj_pads.analog_en[13] ;
+ wire \mprj_pads.analog_en[14] ;
+ wire \mprj_pads.analog_en[15] ;
+ wire \mprj_pads.analog_en[16] ;
+ wire \mprj_pads.analog_en[17] ;
+ wire \mprj_pads.analog_en[18] ;
+ wire \mprj_pads.analog_en[19] ;
+ wire \mprj_pads.analog_en[1] ;
+ wire \mprj_pads.analog_en[20] ;
+ wire \mprj_pads.analog_en[21] ;
+ wire \mprj_pads.analog_en[22] ;
+ wire \mprj_pads.analog_en[23] ;
+ wire \mprj_pads.analog_en[24] ;
+ wire \mprj_pads.analog_en[25] ;
+ wire \mprj_pads.analog_en[26] ;
+ wire \mprj_pads.analog_en[27] ;
+ wire \mprj_pads.analog_en[28] ;
+ wire \mprj_pads.analog_en[29] ;
+ wire \mprj_pads.analog_en[2] ;
+ wire \mprj_pads.analog_en[30] ;
+ wire \mprj_pads.analog_en[31] ;
+ wire \mprj_pads.analog_en[32] ;
+ wire \mprj_pads.analog_en[33] ;
+ wire \mprj_pads.analog_en[34] ;
+ wire \mprj_pads.analog_en[35] ;
+ wire \mprj_pads.analog_en[36] ;
+ wire \mprj_pads.analog_en[37] ;
+ wire \mprj_pads.analog_en[3] ;
+ wire \mprj_pads.analog_en[4] ;
+ wire \mprj_pads.analog_en[5] ;
+ wire \mprj_pads.analog_en[6] ;
+ wire \mprj_pads.analog_en[7] ;
+ wire \mprj_pads.analog_en[8] ;
+ wire \mprj_pads.analog_en[9] ;
+ wire \mprj_pads.analog_io[0] ;
+ wire \mprj_pads.analog_io[10] ;
+ wire \mprj_pads.analog_io[11] ;
+ wire \mprj_pads.analog_io[12] ;
+ wire \mprj_pads.analog_io[13] ;
+ wire \mprj_pads.analog_io[14] ;
+ wire \mprj_pads.analog_io[15] ;
+ wire \mprj_pads.analog_io[16] ;
+ wire \mprj_pads.analog_io[17] ;
+ wire \mprj_pads.analog_io[18] ;
+ wire \mprj_pads.analog_io[19] ;
+ wire \mprj_pads.analog_io[1] ;
+ wire \mprj_pads.analog_io[20] ;
+ wire \mprj_pads.analog_io[21] ;
+ wire \mprj_pads.analog_io[22] ;
+ wire \mprj_pads.analog_io[23] ;
+ wire \mprj_pads.analog_io[24] ;
+ wire \mprj_pads.analog_io[25] ;
+ wire \mprj_pads.analog_io[26] ;
+ wire \mprj_pads.analog_io[27] ;
+ wire \mprj_pads.analog_io[28] ;
+ wire \mprj_pads.analog_io[29] ;
+ wire \mprj_pads.analog_io[2] ;
+ wire \mprj_pads.analog_io[30] ;
+ wire \mprj_pads.analog_io[3] ;
+ wire \mprj_pads.analog_io[4] ;
+ wire \mprj_pads.analog_io[5] ;
+ wire \mprj_pads.analog_io[6] ;
+ wire \mprj_pads.analog_io[7] ;
+ wire \mprj_pads.analog_io[8] ;
+ wire \mprj_pads.analog_io[9] ;
+ wire \mprj_pads.analog_pol[0] ;
+ wire \mprj_pads.analog_pol[10] ;
+ wire \mprj_pads.analog_pol[11] ;
+ wire \mprj_pads.analog_pol[12] ;
+ wire \mprj_pads.analog_pol[13] ;
+ wire \mprj_pads.analog_pol[14] ;
+ wire \mprj_pads.analog_pol[15] ;
+ wire \mprj_pads.analog_pol[16] ;
+ wire \mprj_pads.analog_pol[17] ;
+ wire \mprj_pads.analog_pol[18] ;
+ wire \mprj_pads.analog_pol[19] ;
+ wire \mprj_pads.analog_pol[1] ;
+ wire \mprj_pads.analog_pol[20] ;
+ wire \mprj_pads.analog_pol[21] ;
+ wire \mprj_pads.analog_pol[22] ;
+ wire \mprj_pads.analog_pol[23] ;
+ wire \mprj_pads.analog_pol[24] ;
+ wire \mprj_pads.analog_pol[25] ;
+ wire \mprj_pads.analog_pol[26] ;
+ wire \mprj_pads.analog_pol[27] ;
+ wire \mprj_pads.analog_pol[28] ;
+ wire \mprj_pads.analog_pol[29] ;
+ wire \mprj_pads.analog_pol[2] ;
+ wire \mprj_pads.analog_pol[30] ;
+ wire \mprj_pads.analog_pol[31] ;
+ wire \mprj_pads.analog_pol[32] ;
+ wire \mprj_pads.analog_pol[33] ;
+ wire \mprj_pads.analog_pol[34] ;
+ wire \mprj_pads.analog_pol[35] ;
+ wire \mprj_pads.analog_pol[36] ;
+ wire \mprj_pads.analog_pol[37] ;
+ wire \mprj_pads.analog_pol[3] ;
+ wire \mprj_pads.analog_pol[4] ;
+ wire \mprj_pads.analog_pol[5] ;
+ wire \mprj_pads.analog_pol[6] ;
+ wire \mprj_pads.analog_pol[7] ;
+ wire \mprj_pads.analog_pol[8] ;
+ wire \mprj_pads.analog_pol[9] ;
+ wire \mprj_pads.analog_sel[0] ;
+ wire \mprj_pads.analog_sel[10] ;
+ wire \mprj_pads.analog_sel[11] ;
+ wire \mprj_pads.analog_sel[12] ;
+ wire \mprj_pads.analog_sel[13] ;
+ wire \mprj_pads.analog_sel[14] ;
+ wire \mprj_pads.analog_sel[15] ;
+ wire \mprj_pads.analog_sel[16] ;
+ wire \mprj_pads.analog_sel[17] ;
+ wire \mprj_pads.analog_sel[18] ;
+ wire \mprj_pads.analog_sel[19] ;
+ wire \mprj_pads.analog_sel[1] ;
+ wire \mprj_pads.analog_sel[20] ;
+ wire \mprj_pads.analog_sel[21] ;
+ wire \mprj_pads.analog_sel[22] ;
+ wire \mprj_pads.analog_sel[23] ;
+ wire \mprj_pads.analog_sel[24] ;
+ wire \mprj_pads.analog_sel[25] ;
+ wire \mprj_pads.analog_sel[26] ;
+ wire \mprj_pads.analog_sel[27] ;
+ wire \mprj_pads.analog_sel[28] ;
+ wire \mprj_pads.analog_sel[29] ;
+ wire \mprj_pads.analog_sel[2] ;
+ wire \mprj_pads.analog_sel[30] ;
+ wire \mprj_pads.analog_sel[31] ;
+ wire \mprj_pads.analog_sel[32] ;
+ wire \mprj_pads.analog_sel[33] ;
+ wire \mprj_pads.analog_sel[34] ;
+ wire \mprj_pads.analog_sel[35] ;
+ wire \mprj_pads.analog_sel[36] ;
+ wire \mprj_pads.analog_sel[37] ;
+ wire \mprj_pads.analog_sel[3] ;
+ wire \mprj_pads.analog_sel[4] ;
+ wire \mprj_pads.analog_sel[5] ;
+ wire \mprj_pads.analog_sel[6] ;
+ wire \mprj_pads.analog_sel[7] ;
+ wire \mprj_pads.analog_sel[8] ;
+ wire \mprj_pads.analog_sel[9] ;
+ wire \mprj_pads.dm[0] ;
+ wire \mprj_pads.dm[100] ;
+ wire \mprj_pads.dm[101] ;
+ wire \mprj_pads.dm[102] ;
+ wire \mprj_pads.dm[103] ;
+ wire \mprj_pads.dm[104] ;
+ wire \mprj_pads.dm[105] ;
+ wire \mprj_pads.dm[106] ;
+ wire \mprj_pads.dm[107] ;
+ wire \mprj_pads.dm[108] ;
+ wire \mprj_pads.dm[109] ;
+ wire \mprj_pads.dm[10] ;
+ wire \mprj_pads.dm[110] ;
+ wire \mprj_pads.dm[111] ;
+ wire \mprj_pads.dm[112] ;
+ wire \mprj_pads.dm[113] ;
+ wire \mprj_pads.dm[11] ;
+ wire \mprj_pads.dm[12] ;
+ wire \mprj_pads.dm[13] ;
+ wire \mprj_pads.dm[14] ;
+ wire \mprj_pads.dm[15] ;
+ wire \mprj_pads.dm[16] ;
+ wire \mprj_pads.dm[17] ;
+ wire \mprj_pads.dm[18] ;
+ wire \mprj_pads.dm[19] ;
+ wire \mprj_pads.dm[1] ;
+ wire \mprj_pads.dm[20] ;
+ wire \mprj_pads.dm[21] ;
+ wire \mprj_pads.dm[22] ;
+ wire \mprj_pads.dm[23] ;
+ wire \mprj_pads.dm[24] ;
+ wire \mprj_pads.dm[25] ;
+ wire \mprj_pads.dm[26] ;
+ wire \mprj_pads.dm[27] ;
+ wire \mprj_pads.dm[28] ;
+ wire \mprj_pads.dm[29] ;
+ wire \mprj_pads.dm[2] ;
+ wire \mprj_pads.dm[30] ;
+ wire \mprj_pads.dm[31] ;
+ wire \mprj_pads.dm[32] ;
+ wire \mprj_pads.dm[33] ;
+ wire \mprj_pads.dm[34] ;
+ wire \mprj_pads.dm[35] ;
+ wire \mprj_pads.dm[36] ;
+ wire \mprj_pads.dm[37] ;
+ wire \mprj_pads.dm[38] ;
+ wire \mprj_pads.dm[39] ;
+ wire \mprj_pads.dm[3] ;
+ wire \mprj_pads.dm[40] ;
+ wire \mprj_pads.dm[41] ;
+ wire \mprj_pads.dm[42] ;
+ wire \mprj_pads.dm[43] ;
+ wire \mprj_pads.dm[44] ;
+ wire \mprj_pads.dm[45] ;
+ wire \mprj_pads.dm[46] ;
+ wire \mprj_pads.dm[47] ;
+ wire \mprj_pads.dm[48] ;
+ wire \mprj_pads.dm[49] ;
+ wire \mprj_pads.dm[4] ;
+ wire \mprj_pads.dm[50] ;
+ wire \mprj_pads.dm[51] ;
+ wire \mprj_pads.dm[52] ;
+ wire \mprj_pads.dm[53] ;
+ wire \mprj_pads.dm[54] ;
+ wire \mprj_pads.dm[55] ;
+ wire \mprj_pads.dm[56] ;
+ wire \mprj_pads.dm[57] ;
+ wire \mprj_pads.dm[58] ;
+ wire \mprj_pads.dm[59] ;
+ wire \mprj_pads.dm[5] ;
+ wire \mprj_pads.dm[60] ;
+ wire \mprj_pads.dm[61] ;
+ wire \mprj_pads.dm[62] ;
+ wire \mprj_pads.dm[63] ;
+ wire \mprj_pads.dm[64] ;
+ wire \mprj_pads.dm[65] ;
+ wire \mprj_pads.dm[66] ;
+ wire \mprj_pads.dm[67] ;
+ wire \mprj_pads.dm[68] ;
+ wire \mprj_pads.dm[69] ;
+ wire \mprj_pads.dm[6] ;
+ wire \mprj_pads.dm[70] ;
+ wire \mprj_pads.dm[71] ;
+ wire \mprj_pads.dm[72] ;
+ wire \mprj_pads.dm[73] ;
+ wire \mprj_pads.dm[74] ;
+ wire \mprj_pads.dm[75] ;
+ wire \mprj_pads.dm[76] ;
+ wire \mprj_pads.dm[77] ;
+ wire \mprj_pads.dm[78] ;
+ wire \mprj_pads.dm[79] ;
+ wire \mprj_pads.dm[7] ;
+ wire \mprj_pads.dm[80] ;
+ wire \mprj_pads.dm[81] ;
+ wire \mprj_pads.dm[82] ;
+ wire \mprj_pads.dm[83] ;
+ wire \mprj_pads.dm[84] ;
+ wire \mprj_pads.dm[85] ;
+ wire \mprj_pads.dm[86] ;
+ wire \mprj_pads.dm[87] ;
+ wire \mprj_pads.dm[88] ;
+ wire \mprj_pads.dm[89] ;
+ wire \mprj_pads.dm[8] ;
+ wire \mprj_pads.dm[90] ;
+ wire \mprj_pads.dm[91] ;
+ wire \mprj_pads.dm[92] ;
+ wire \mprj_pads.dm[93] ;
+ wire \mprj_pads.dm[94] ;
+ wire \mprj_pads.dm[95] ;
+ wire \mprj_pads.dm[96] ;
+ wire \mprj_pads.dm[97] ;
+ wire \mprj_pads.dm[98] ;
+ wire \mprj_pads.dm[99] ;
+ wire \mprj_pads.dm[9] ;
+ wire \mprj_pads.enh[0] ;
+ wire \mprj_pads.enh[10] ;
+ wire \mprj_pads.enh[11] ;
+ wire \mprj_pads.enh[12] ;
+ wire \mprj_pads.enh[13] ;
+ wire \mprj_pads.enh[14] ;
+ wire \mprj_pads.enh[15] ;
+ wire \mprj_pads.enh[16] ;
+ wire \mprj_pads.enh[17] ;
+ wire \mprj_pads.enh[18] ;
+ wire \mprj_pads.enh[19] ;
+ wire \mprj_pads.enh[1] ;
+ wire \mprj_pads.enh[20] ;
+ wire \mprj_pads.enh[21] ;
+ wire \mprj_pads.enh[22] ;
+ wire \mprj_pads.enh[23] ;
+ wire \mprj_pads.enh[24] ;
+ wire \mprj_pads.enh[25] ;
+ wire \mprj_pads.enh[26] ;
+ wire \mprj_pads.enh[27] ;
+ wire \mprj_pads.enh[28] ;
+ wire \mprj_pads.enh[29] ;
+ wire \mprj_pads.enh[2] ;
+ wire \mprj_pads.enh[30] ;
+ wire \mprj_pads.enh[31] ;
+ wire \mprj_pads.enh[32] ;
+ wire \mprj_pads.enh[33] ;
+ wire \mprj_pads.enh[34] ;
+ wire \mprj_pads.enh[35] ;
+ wire \mprj_pads.enh[36] ;
+ wire \mprj_pads.enh[37] ;
+ wire \mprj_pads.enh[3] ;
+ wire \mprj_pads.enh[4] ;
+ wire \mprj_pads.enh[5] ;
+ wire \mprj_pads.enh[6] ;
+ wire \mprj_pads.enh[7] ;
+ wire \mprj_pads.enh[8] ;
+ wire \mprj_pads.enh[9] ;
+ wire \mprj_pads.hldh_n[0] ;
+ wire \mprj_pads.hldh_n[10] ;
+ wire \mprj_pads.hldh_n[11] ;
+ wire \mprj_pads.hldh_n[12] ;
+ wire \mprj_pads.hldh_n[13] ;
+ wire \mprj_pads.hldh_n[14] ;
+ wire \mprj_pads.hldh_n[15] ;
+ wire \mprj_pads.hldh_n[16] ;
+ wire \mprj_pads.hldh_n[17] ;
+ wire \mprj_pads.hldh_n[18] ;
+ wire \mprj_pads.hldh_n[19] ;
+ wire \mprj_pads.hldh_n[1] ;
+ wire \mprj_pads.hldh_n[20] ;
+ wire \mprj_pads.hldh_n[21] ;
+ wire \mprj_pads.hldh_n[22] ;
+ wire \mprj_pads.hldh_n[23] ;
+ wire \mprj_pads.hldh_n[24] ;
+ wire \mprj_pads.hldh_n[25] ;
+ wire \mprj_pads.hldh_n[26] ;
+ wire \mprj_pads.hldh_n[27] ;
+ wire \mprj_pads.hldh_n[28] ;
+ wire \mprj_pads.hldh_n[29] ;
+ wire \mprj_pads.hldh_n[2] ;
+ wire \mprj_pads.hldh_n[30] ;
+ wire \mprj_pads.hldh_n[31] ;
+ wire \mprj_pads.hldh_n[32] ;
+ wire \mprj_pads.hldh_n[33] ;
+ wire \mprj_pads.hldh_n[34] ;
+ wire \mprj_pads.hldh_n[35] ;
+ wire \mprj_pads.hldh_n[36] ;
+ wire \mprj_pads.hldh_n[37] ;
+ wire \mprj_pads.hldh_n[3] ;
+ wire \mprj_pads.hldh_n[4] ;
+ wire \mprj_pads.hldh_n[5] ;
+ wire \mprj_pads.hldh_n[6] ;
+ wire \mprj_pads.hldh_n[7] ;
+ wire \mprj_pads.hldh_n[8] ;
+ wire \mprj_pads.hldh_n[9] ;
+ wire \mprj_pads.holdover[0] ;
+ wire \mprj_pads.holdover[10] ;
+ wire \mprj_pads.holdover[11] ;
+ wire \mprj_pads.holdover[12] ;
+ wire \mprj_pads.holdover[13] ;
+ wire \mprj_pads.holdover[14] ;
+ wire \mprj_pads.holdover[15] ;
+ wire \mprj_pads.holdover[16] ;
+ wire \mprj_pads.holdover[17] ;
+ wire \mprj_pads.holdover[18] ;
+ wire \mprj_pads.holdover[19] ;
+ wire \mprj_pads.holdover[1] ;
+ wire \mprj_pads.holdover[20] ;
+ wire \mprj_pads.holdover[21] ;
+ wire \mprj_pads.holdover[22] ;
+ wire \mprj_pads.holdover[23] ;
+ wire \mprj_pads.holdover[24] ;
+ wire \mprj_pads.holdover[25] ;
+ wire \mprj_pads.holdover[26] ;
+ wire \mprj_pads.holdover[27] ;
+ wire \mprj_pads.holdover[28] ;
+ wire \mprj_pads.holdover[29] ;
+ wire \mprj_pads.holdover[2] ;
+ wire \mprj_pads.holdover[30] ;
+ wire \mprj_pads.holdover[31] ;
+ wire \mprj_pads.holdover[32] ;
+ wire \mprj_pads.holdover[33] ;
+ wire \mprj_pads.holdover[34] ;
+ wire \mprj_pads.holdover[35] ;
+ wire \mprj_pads.holdover[36] ;
+ wire \mprj_pads.holdover[37] ;
+ wire \mprj_pads.holdover[3] ;
+ wire \mprj_pads.holdover[4] ;
+ wire \mprj_pads.holdover[5] ;
+ wire \mprj_pads.holdover[6] ;
+ wire \mprj_pads.holdover[7] ;
+ wire \mprj_pads.holdover[8] ;
+ wire \mprj_pads.holdover[9] ;
+ wire \mprj_pads.ib_mode_sel[0] ;
+ wire \mprj_pads.ib_mode_sel[10] ;
+ wire \mprj_pads.ib_mode_sel[11] ;
+ wire \mprj_pads.ib_mode_sel[12] ;
+ wire \mprj_pads.ib_mode_sel[13] ;
+ wire \mprj_pads.ib_mode_sel[14] ;
+ wire \mprj_pads.ib_mode_sel[15] ;
+ wire \mprj_pads.ib_mode_sel[16] ;
+ wire \mprj_pads.ib_mode_sel[17] ;
+ wire \mprj_pads.ib_mode_sel[18] ;
+ wire \mprj_pads.ib_mode_sel[19] ;
+ wire \mprj_pads.ib_mode_sel[1] ;
+ wire \mprj_pads.ib_mode_sel[20] ;
+ wire \mprj_pads.ib_mode_sel[21] ;
+ wire \mprj_pads.ib_mode_sel[22] ;
+ wire \mprj_pads.ib_mode_sel[23] ;
+ wire \mprj_pads.ib_mode_sel[24] ;
+ wire \mprj_pads.ib_mode_sel[25] ;
+ wire \mprj_pads.ib_mode_sel[26] ;
+ wire \mprj_pads.ib_mode_sel[27] ;
+ wire \mprj_pads.ib_mode_sel[28] ;
+ wire \mprj_pads.ib_mode_sel[29] ;
+ wire \mprj_pads.ib_mode_sel[2] ;
+ wire \mprj_pads.ib_mode_sel[30] ;
+ wire \mprj_pads.ib_mode_sel[31] ;
+ wire \mprj_pads.ib_mode_sel[32] ;
+ wire \mprj_pads.ib_mode_sel[33] ;
+ wire \mprj_pads.ib_mode_sel[34] ;
+ wire \mprj_pads.ib_mode_sel[35] ;
+ wire \mprj_pads.ib_mode_sel[36] ;
+ wire \mprj_pads.ib_mode_sel[37] ;
+ wire \mprj_pads.ib_mode_sel[3] ;
+ wire \mprj_pads.ib_mode_sel[4] ;
+ wire \mprj_pads.ib_mode_sel[5] ;
+ wire \mprj_pads.ib_mode_sel[6] ;
+ wire \mprj_pads.ib_mode_sel[7] ;
+ wire \mprj_pads.ib_mode_sel[8] ;
+ wire \mprj_pads.ib_mode_sel[9] ;
+ wire \mprj_pads.inp_dis[0] ;
+ wire \mprj_pads.inp_dis[10] ;
+ wire \mprj_pads.inp_dis[11] ;
+ wire \mprj_pads.inp_dis[12] ;
+ wire \mprj_pads.inp_dis[13] ;
+ wire \mprj_pads.inp_dis[14] ;
+ wire \mprj_pads.inp_dis[15] ;
+ wire \mprj_pads.inp_dis[16] ;
+ wire \mprj_pads.inp_dis[17] ;
+ wire \mprj_pads.inp_dis[18] ;
+ wire \mprj_pads.inp_dis[19] ;
+ wire \mprj_pads.inp_dis[1] ;
+ wire \mprj_pads.inp_dis[20] ;
+ wire \mprj_pads.inp_dis[21] ;
+ wire \mprj_pads.inp_dis[22] ;
+ wire \mprj_pads.inp_dis[23] ;
+ wire \mprj_pads.inp_dis[24] ;
+ wire \mprj_pads.inp_dis[25] ;
+ wire \mprj_pads.inp_dis[26] ;
+ wire \mprj_pads.inp_dis[27] ;
+ wire \mprj_pads.inp_dis[28] ;
+ wire \mprj_pads.inp_dis[29] ;
+ wire \mprj_pads.inp_dis[2] ;
+ wire \mprj_pads.inp_dis[30] ;
+ wire \mprj_pads.inp_dis[31] ;
+ wire \mprj_pads.inp_dis[32] ;
+ wire \mprj_pads.inp_dis[33] ;
+ wire \mprj_pads.inp_dis[34] ;
+ wire \mprj_pads.inp_dis[35] ;
+ wire \mprj_pads.inp_dis[36] ;
+ wire \mprj_pads.inp_dis[37] ;
+ wire \mprj_pads.inp_dis[3] ;
+ wire \mprj_pads.inp_dis[4] ;
+ wire \mprj_pads.inp_dis[5] ;
+ wire \mprj_pads.inp_dis[6] ;
+ wire \mprj_pads.inp_dis[7] ;
+ wire \mprj_pads.inp_dis[8] ;
+ wire \mprj_pads.inp_dis[9] ;
+ wire \mprj_pads.io[0] ;
+ wire \mprj_pads.io[10] ;
+ wire \mprj_pads.io[11] ;
+ wire \mprj_pads.io[12] ;
+ wire \mprj_pads.io[13] ;
+ wire \mprj_pads.io[14] ;
+ wire \mprj_pads.io[15] ;
+ wire \mprj_pads.io[16] ;
+ wire \mprj_pads.io[17] ;
+ wire \mprj_pads.io[18] ;
+ wire \mprj_pads.io[19] ;
+ wire \mprj_pads.io[1] ;
+ wire \mprj_pads.io[20] ;
+ wire \mprj_pads.io[21] ;
+ wire \mprj_pads.io[22] ;
+ wire \mprj_pads.io[23] ;
+ wire \mprj_pads.io[24] ;
+ wire \mprj_pads.io[25] ;
+ wire \mprj_pads.io[26] ;
+ wire \mprj_pads.io[27] ;
+ wire \mprj_pads.io[28] ;
+ wire \mprj_pads.io[29] ;
+ wire \mprj_pads.io[2] ;
+ wire \mprj_pads.io[30] ;
+ wire \mprj_pads.io[31] ;
+ wire \mprj_pads.io[32] ;
+ wire \mprj_pads.io[33] ;
+ wire \mprj_pads.io[34] ;
+ wire \mprj_pads.io[35] ;
+ wire \mprj_pads.io[36] ;
+ wire \mprj_pads.io[37] ;
+ wire \mprj_pads.io[3] ;
+ wire \mprj_pads.io[4] ;
+ wire \mprj_pads.io[5] ;
+ wire \mprj_pads.io[6] ;
+ wire \mprj_pads.io[7] ;
+ wire \mprj_pads.io[8] ;
+ wire \mprj_pads.io[9] ;
+ wire \mprj_pads.io_in[0] ;
+ wire \mprj_pads.io_in[10] ;
+ wire \mprj_pads.io_in[11] ;
+ wire \mprj_pads.io_in[12] ;
+ wire \mprj_pads.io_in[13] ;
+ wire \mprj_pads.io_in[14] ;
+ wire \mprj_pads.io_in[15] ;
+ wire \mprj_pads.io_in[16] ;
+ wire \mprj_pads.io_in[17] ;
+ wire \mprj_pads.io_in[18] ;
+ wire \mprj_pads.io_in[19] ;
+ wire \mprj_pads.io_in[1] ;
+ wire \mprj_pads.io_in[20] ;
+ wire \mprj_pads.io_in[21] ;
+ wire \mprj_pads.io_in[22] ;
+ wire \mprj_pads.io_in[23] ;
+ wire \mprj_pads.io_in[24] ;
+ wire \mprj_pads.io_in[25] ;
+ wire \mprj_pads.io_in[26] ;
+ wire \mprj_pads.io_in[27] ;
+ wire \mprj_pads.io_in[28] ;
+ wire \mprj_pads.io_in[29] ;
+ wire \mprj_pads.io_in[2] ;
+ wire \mprj_pads.io_in[30] ;
+ wire \mprj_pads.io_in[31] ;
+ wire \mprj_pads.io_in[32] ;
+ wire \mprj_pads.io_in[33] ;
+ wire \mprj_pads.io_in[34] ;
+ wire \mprj_pads.io_in[35] ;
+ wire \mprj_pads.io_in[36] ;
+ wire \mprj_pads.io_in[37] ;
+ wire \mprj_pads.io_in[3] ;
+ wire \mprj_pads.io_in[4] ;
+ wire \mprj_pads.io_in[5] ;
+ wire \mprj_pads.io_in[6] ;
+ wire \mprj_pads.io_in[7] ;
+ wire \mprj_pads.io_in[8] ;
+ wire \mprj_pads.io_in[9] ;
+ wire \mprj_pads.io_out[0] ;
+ wire \mprj_pads.io_out[10] ;
+ wire \mprj_pads.io_out[11] ;
+ wire \mprj_pads.io_out[12] ;
+ wire \mprj_pads.io_out[13] ;
+ wire \mprj_pads.io_out[14] ;
+ wire \mprj_pads.io_out[15] ;
+ wire \mprj_pads.io_out[16] ;
+ wire \mprj_pads.io_out[17] ;
+ wire \mprj_pads.io_out[18] ;
+ wire \mprj_pads.io_out[19] ;
+ wire \mprj_pads.io_out[1] ;
+ wire \mprj_pads.io_out[20] ;
+ wire \mprj_pads.io_out[21] ;
+ wire \mprj_pads.io_out[22] ;
+ wire \mprj_pads.io_out[23] ;
+ wire \mprj_pads.io_out[24] ;
+ wire \mprj_pads.io_out[25] ;
+ wire \mprj_pads.io_out[26] ;
+ wire \mprj_pads.io_out[27] ;
+ wire \mprj_pads.io_out[28] ;
+ wire \mprj_pads.io_out[29] ;
+ wire \mprj_pads.io_out[2] ;
+ wire \mprj_pads.io_out[30] ;
+ wire \mprj_pads.io_out[31] ;
+ wire \mprj_pads.io_out[32] ;
+ wire \mprj_pads.io_out[33] ;
+ wire \mprj_pads.io_out[34] ;
+ wire \mprj_pads.io_out[35] ;
+ wire \mprj_pads.io_out[36] ;
+ wire \mprj_pads.io_out[37] ;
+ wire \mprj_pads.io_out[3] ;
+ wire \mprj_pads.io_out[4] ;
+ wire \mprj_pads.io_out[5] ;
+ wire \mprj_pads.io_out[6] ;
+ wire \mprj_pads.io_out[7] ;
+ wire \mprj_pads.io_out[8] ;
+ wire \mprj_pads.io_out[9] ;
+ wire \mprj_pads.loop1_io[0] ;
+ wire \mprj_pads.loop1_io[10] ;
+ wire \mprj_pads.loop1_io[11] ;
+ wire \mprj_pads.loop1_io[12] ;
+ wire \mprj_pads.loop1_io[13] ;
+ wire \mprj_pads.loop1_io[14] ;
+ wire \mprj_pads.loop1_io[15] ;
+ wire \mprj_pads.loop1_io[16] ;
+ wire \mprj_pads.loop1_io[17] ;
+ wire \mprj_pads.loop1_io[18] ;
+ wire \mprj_pads.loop1_io[19] ;
+ wire \mprj_pads.loop1_io[1] ;
+ wire \mprj_pads.loop1_io[20] ;
+ wire \mprj_pads.loop1_io[21] ;
+ wire \mprj_pads.loop1_io[22] ;
+ wire \mprj_pads.loop1_io[23] ;
+ wire \mprj_pads.loop1_io[24] ;
+ wire \mprj_pads.loop1_io[25] ;
+ wire \mprj_pads.loop1_io[26] ;
+ wire \mprj_pads.loop1_io[27] ;
+ wire \mprj_pads.loop1_io[28] ;
+ wire \mprj_pads.loop1_io[29] ;
+ wire \mprj_pads.loop1_io[2] ;
+ wire \mprj_pads.loop1_io[30] ;
+ wire \mprj_pads.loop1_io[31] ;
+ wire \mprj_pads.loop1_io[32] ;
+ wire \mprj_pads.loop1_io[33] ;
+ wire \mprj_pads.loop1_io[34] ;
+ wire \mprj_pads.loop1_io[35] ;
+ wire \mprj_pads.loop1_io[36] ;
+ wire \mprj_pads.loop1_io[37] ;
+ wire \mprj_pads.loop1_io[3] ;
+ wire \mprj_pads.loop1_io[4] ;
+ wire \mprj_pads.loop1_io[5] ;
+ wire \mprj_pads.loop1_io[6] ;
+ wire \mprj_pads.loop1_io[7] ;
+ wire \mprj_pads.loop1_io[8] ;
+ wire \mprj_pads.loop1_io[9] ;
+ wire \mprj_pads.no_connect[0] ;
+ wire \mprj_pads.no_connect[1] ;
+ wire \mprj_pads.no_connect[2] ;
+ wire \mprj_pads.no_connect[3] ;
+ wire \mprj_pads.no_connect[4] ;
+ wire \mprj_pads.no_connect[5] ;
+ wire \mprj_pads.no_connect[6] ;
+ wire \mprj_pads.oeb[0] ;
+ wire \mprj_pads.oeb[10] ;
+ wire \mprj_pads.oeb[11] ;
+ wire \mprj_pads.oeb[12] ;
+ wire \mprj_pads.oeb[13] ;
+ wire \mprj_pads.oeb[14] ;
+ wire \mprj_pads.oeb[15] ;
+ wire \mprj_pads.oeb[16] ;
+ wire \mprj_pads.oeb[17] ;
+ wire \mprj_pads.oeb[18] ;
+ wire \mprj_pads.oeb[19] ;
+ wire \mprj_pads.oeb[1] ;
+ wire \mprj_pads.oeb[20] ;
+ wire \mprj_pads.oeb[21] ;
+ wire \mprj_pads.oeb[22] ;
+ wire \mprj_pads.oeb[23] ;
+ wire \mprj_pads.oeb[24] ;
+ wire \mprj_pads.oeb[25] ;
+ wire \mprj_pads.oeb[26] ;
+ wire \mprj_pads.oeb[27] ;
+ wire \mprj_pads.oeb[28] ;
+ wire \mprj_pads.oeb[29] ;
+ wire \mprj_pads.oeb[2] ;
+ wire \mprj_pads.oeb[30] ;
+ wire \mprj_pads.oeb[31] ;
+ wire \mprj_pads.oeb[32] ;
+ wire \mprj_pads.oeb[33] ;
+ wire \mprj_pads.oeb[34] ;
+ wire \mprj_pads.oeb[35] ;
+ wire \mprj_pads.oeb[36] ;
+ wire \mprj_pads.oeb[37] ;
+ wire \mprj_pads.oeb[3] ;
+ wire \mprj_pads.oeb[4] ;
+ wire \mprj_pads.oeb[5] ;
+ wire \mprj_pads.oeb[6] ;
+ wire \mprj_pads.oeb[7] ;
+ wire \mprj_pads.oeb[8] ;
+ wire \mprj_pads.oeb[9] ;
+ wire \mprj_pads.porb_h ;
+ wire \mprj_pads.slow_sel[0] ;
+ wire \mprj_pads.slow_sel[10] ;
+ wire \mprj_pads.slow_sel[11] ;
+ wire \mprj_pads.slow_sel[12] ;
+ wire \mprj_pads.slow_sel[13] ;
+ wire \mprj_pads.slow_sel[14] ;
+ wire \mprj_pads.slow_sel[15] ;
+ wire \mprj_pads.slow_sel[16] ;
+ wire \mprj_pads.slow_sel[17] ;
+ wire \mprj_pads.slow_sel[18] ;
+ wire \mprj_pads.slow_sel[19] ;
+ wire \mprj_pads.slow_sel[1] ;
+ wire \mprj_pads.slow_sel[20] ;
+ wire \mprj_pads.slow_sel[21] ;
+ wire \mprj_pads.slow_sel[22] ;
+ wire \mprj_pads.slow_sel[23] ;
+ wire \mprj_pads.slow_sel[24] ;
+ wire \mprj_pads.slow_sel[25] ;
+ wire \mprj_pads.slow_sel[26] ;
+ wire \mprj_pads.slow_sel[27] ;
+ wire \mprj_pads.slow_sel[28] ;
+ wire \mprj_pads.slow_sel[29] ;
+ wire \mprj_pads.slow_sel[2] ;
+ wire \mprj_pads.slow_sel[30] ;
+ wire \mprj_pads.slow_sel[31] ;
+ wire \mprj_pads.slow_sel[32] ;
+ wire \mprj_pads.slow_sel[33] ;
+ wire \mprj_pads.slow_sel[34] ;
+ wire \mprj_pads.slow_sel[35] ;
+ wire \mprj_pads.slow_sel[36] ;
+ wire \mprj_pads.slow_sel[37] ;
+ wire \mprj_pads.slow_sel[3] ;
+ wire \mprj_pads.slow_sel[4] ;
+ wire \mprj_pads.slow_sel[5] ;
+ wire \mprj_pads.slow_sel[6] ;
+ wire \mprj_pads.slow_sel[7] ;
+ wire \mprj_pads.slow_sel[8] ;
+ wire \mprj_pads.slow_sel[9] ;
+ wire \mprj_pads.vccd ;
+ wire \mprj_pads.vccd1 ;
+ wire \mprj_pads.vccd2 ;
+ wire \mprj_pads.vdda ;
+ wire \mprj_pads.vdda1 ;
+ wire \mprj_pads.vdda2 ;
+ wire \mprj_pads.vddio ;
+ wire \mprj_pads.vddio_q ;
+ wire \mprj_pads.vssa ;
+ wire \mprj_pads.vssa1 ;
+ wire \mprj_pads.vssa2 ;
+ wire \mprj_pads.vssd ;
+ wire \mprj_pads.vssd1 ;
+ wire \mprj_pads.vssd2 ;
+ wire \mprj_pads.vssio ;
+ wire \mprj_pads.vssio_q ;
+ wire \mprj_pads.vtrip_sel[0] ;
+ wire \mprj_pads.vtrip_sel[10] ;
+ wire \mprj_pads.vtrip_sel[11] ;
+ wire \mprj_pads.vtrip_sel[12] ;
+ wire \mprj_pads.vtrip_sel[13] ;
+ wire \mprj_pads.vtrip_sel[14] ;
+ wire \mprj_pads.vtrip_sel[15] ;
+ wire \mprj_pads.vtrip_sel[16] ;
+ wire \mprj_pads.vtrip_sel[17] ;
+ wire \mprj_pads.vtrip_sel[18] ;
+ wire \mprj_pads.vtrip_sel[19] ;
+ wire \mprj_pads.vtrip_sel[1] ;
+ wire \mprj_pads.vtrip_sel[20] ;
+ wire \mprj_pads.vtrip_sel[21] ;
+ wire \mprj_pads.vtrip_sel[22] ;
+ wire \mprj_pads.vtrip_sel[23] ;
+ wire \mprj_pads.vtrip_sel[24] ;
+ wire \mprj_pads.vtrip_sel[25] ;
+ wire \mprj_pads.vtrip_sel[26] ;
+ wire \mprj_pads.vtrip_sel[27] ;
+ wire \mprj_pads.vtrip_sel[28] ;
+ wire \mprj_pads.vtrip_sel[29] ;
+ wire \mprj_pads.vtrip_sel[2] ;
+ wire \mprj_pads.vtrip_sel[30] ;
+ wire \mprj_pads.vtrip_sel[31] ;
+ wire \mprj_pads.vtrip_sel[32] ;
+ wire \mprj_pads.vtrip_sel[33] ;
+ wire \mprj_pads.vtrip_sel[34] ;
+ wire \mprj_pads.vtrip_sel[35] ;
+ wire \mprj_pads.vtrip_sel[36] ;
+ wire \mprj_pads.vtrip_sel[37] ;
+ wire \mprj_pads.vtrip_sel[3] ;
+ wire \mprj_pads.vtrip_sel[4] ;
+ wire \mprj_pads.vtrip_sel[5] ;
+ wire \mprj_pads.vtrip_sel[6] ;
+ wire \mprj_pads.vtrip_sel[7] ;
+ wire \mprj_pads.vtrip_sel[8] ;
+ wire \mprj_pads.vtrip_sel[9] ;
+ input por;
+ input porb_h;
+ input resetb;
+ output resetb_core_h;
+ inout vccd;
+ inout vccd1;
+ inout vccd2;
+ inout vdda;
+ inout vdda1;
+ inout vdda2;
+ inout vddio;
+ wire vddio_q;
+ inout vssa;
+ inout vssa1;
+ inout vssa2;
+ inout vssd;
+ inout vssd1;
+ inout vssd2;
+ inout vssio;
+ wire vssio_q;
+ wire xresloop;
+ sky130_ef_io__gpiov2_pad_wrapped clock_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vssd, vssd, vccd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_clock),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(clock_core),
+ .INP_DIS(por),
+ .IN_H(),
+ .OE_N(vccd),
+ .OUT(vssd),
+ .PAD(clock),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_clock),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_clk_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_clk),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(flash_clk_ieb_core),
+ .IN_H(),
+ .OE_N(flash_clk_oeb_core),
+ .OUT(flash_clk_core),
+ .PAD(flash_clk),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_clk),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_csb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_csb),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(flash_csb_ieb_core),
+ .IN_H(),
+ .OE_N(flash_csb_oeb_core),
+ .OUT(flash_csb_core),
+ .PAD(flash_csb),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_csb),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io0_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io0),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io0_di_core),
+ .INP_DIS(flash_io0_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io0_oeb_core),
+ .OUT(flash_io0_do_core),
+ .PAD(flash_io0),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io0),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io1_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io1),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io1_di_core),
+ .INP_DIS(flash_io1_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io1_oeb_core),
+ .OUT(flash_io1_do_core),
+ .PAD(flash_io1),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io1),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped gpio_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ gpio_mode1_core, gpio_mode1_core, gpio_mode0_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_gpio),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(gpio_in_core),
+ .INP_DIS(gpio_inenb_core),
+ .IN_H(),
+ .OE_N(gpio_outenb_core),
+ .OUT(gpio_out_core),
+ .PAD(gpio),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_gpio),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclmap_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[0] ),
+ .ANALOG_POL(\mprj_io_analog_pol[0] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[0] ),
+ .DM({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .ENABLE_H(\mprj_io_enh[0] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[0] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[0] ),
+ .HLD_OVR(\mprj_io_holdover[0] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[0] ),
+ .IN(\mprj_pads.io_in[0] ),
+ .INP_DIS(\mprj_io_inp_dis[0] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[0] ),
+ .OUT(\mprj_io_out[0] ),
+ .PAD(\mprj_io[0] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[0] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[0] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[0] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[10] ),
+ .ANALOG_POL(\mprj_io_analog_pol[10] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[10] ),
+ .DM({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] }),
+ .ENABLE_H(\mprj_io_enh[10] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[10] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[10] ),
+ .HLD_OVR(\mprj_io_holdover[10] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[10] ),
+ .IN(\mprj_pads.io_in[10] ),
+ .INP_DIS(\mprj_io_inp_dis[10] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[10] ),
+ .OUT(\mprj_io_out[10] ),
+ .PAD(\mprj_io[10] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[3] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[10] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[10] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[10] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[11] ),
+ .ANALOG_POL(\mprj_io_analog_pol[11] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[11] ),
+ .DM({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] }),
+ .ENABLE_H(\mprj_io_enh[11] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[11] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[11] ),
+ .HLD_OVR(\mprj_io_holdover[11] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[11] ),
+ .IN(\mprj_pads.io_in[11] ),
+ .INP_DIS(\mprj_io_inp_dis[11] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[11] ),
+ .OUT(\mprj_io_out[11] ),
+ .PAD(\mprj_io[11] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[4] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[11] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[11] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[11] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[12] ),
+ .ANALOG_POL(\mprj_io_analog_pol[12] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[12] ),
+ .DM({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] }),
+ .ENABLE_H(\mprj_io_enh[12] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[12] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[12] ),
+ .HLD_OVR(\mprj_io_holdover[12] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[12] ),
+ .IN(\mprj_pads.io_in[12] ),
+ .INP_DIS(\mprj_io_inp_dis[12] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[12] ),
+ .OUT(\mprj_io_out[12] ),
+ .PAD(\mprj_io[12] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[5] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[12] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[12] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[12] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[13] ),
+ .ANALOG_POL(\mprj_io_analog_pol[13] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[13] ),
+ .DM({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] }),
+ .ENABLE_H(\mprj_io_enh[13] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[13] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[13] ),
+ .HLD_OVR(\mprj_io_holdover[13] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[13] ),
+ .IN(\mprj_pads.io_in[13] ),
+ .INP_DIS(\mprj_io_inp_dis[13] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[13] ),
+ .OUT(\mprj_io_out[13] ),
+ .PAD(\mprj_io[13] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[6] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[13] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[13] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[13] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[14] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[14] ),
+ .ANALOG_POL(\mprj_io_analog_pol[14] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[14] ),
+ .DM({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] }),
+ .ENABLE_H(\mprj_io_enh[14] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[14] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[14] ),
+ .HLD_OVR(\mprj_io_holdover[14] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[14] ),
+ .IN(\mprj_pads.io_in[14] ),
+ .INP_DIS(\mprj_io_inp_dis[14] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[14] ),
+ .OUT(\mprj_io_out[14] ),
+ .PAD(\mprj_io[14] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[7] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[14] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[14] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[14] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[15] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[15] ),
+ .ANALOG_POL(\mprj_io_analog_pol[15] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[15] ),
+ .DM({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] }),
+ .ENABLE_H(\mprj_io_enh[15] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[15] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[15] ),
+ .HLD_OVR(\mprj_io_holdover[15] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[15] ),
+ .IN(\mprj_pads.io_in[15] ),
+ .INP_DIS(\mprj_io_inp_dis[15] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[15] ),
+ .OUT(\mprj_io_out[15] ),
+ .PAD(\mprj_io[15] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[8] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[15] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[15] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[15] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[16] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[16] ),
+ .ANALOG_POL(\mprj_io_analog_pol[16] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[16] ),
+ .DM({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] }),
+ .ENABLE_H(\mprj_io_enh[16] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[16] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[16] ),
+ .HLD_OVR(\mprj_io_holdover[16] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[16] ),
+ .IN(\mprj_pads.io_in[16] ),
+ .INP_DIS(\mprj_io_inp_dis[16] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[16] ),
+ .OUT(\mprj_io_out[16] ),
+ .PAD(\mprj_io[16] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[9] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[16] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[16] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[16] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[17] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[17] ),
+ .ANALOG_POL(\mprj_io_analog_pol[17] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[17] ),
+ .DM({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] }),
+ .ENABLE_H(\mprj_io_enh[17] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[17] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[17] ),
+ .HLD_OVR(\mprj_io_holdover[17] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[17] ),
+ .IN(\mprj_pads.io_in[17] ),
+ .INP_DIS(\mprj_io_inp_dis[17] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[17] ),
+ .OUT(\mprj_io_out[17] ),
+ .PAD(\mprj_io[17] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[10] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[17] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[17] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[17] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[1] ),
+ .ANALOG_POL(\mprj_io_analog_pol[1] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[1] ),
+ .DM({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] }),
+ .ENABLE_H(\mprj_io_enh[1] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[1] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[1] ),
+ .HLD_OVR(\mprj_io_holdover[1] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[1] ),
+ .IN(\mprj_pads.io_in[1] ),
+ .INP_DIS(\mprj_io_inp_dis[1] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[1] ),
+ .OUT(\mprj_io_out[1] ),
+ .PAD(\mprj_io[1] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[1] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[1] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[1] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[2] ),
+ .ANALOG_POL(\mprj_io_analog_pol[2] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[2] ),
+ .DM({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] }),
+ .ENABLE_H(\mprj_io_enh[2] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[2] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[2] ),
+ .HLD_OVR(\mprj_io_holdover[2] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[2] ),
+ .IN(\mprj_pads.io_in[2] ),
+ .INP_DIS(\mprj_io_inp_dis[2] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[2] ),
+ .OUT(\mprj_io_out[2] ),
+ .PAD(\mprj_io[2] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[2] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[2] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[2] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[2] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[3] ),
+ .ANALOG_POL(\mprj_io_analog_pol[3] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[3] ),
+ .DM({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] }),
+ .ENABLE_H(\mprj_io_enh[3] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[3] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[3] ),
+ .HLD_OVR(\mprj_io_holdover[3] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[3] ),
+ .IN(\mprj_pads.io_in[3] ),
+ .INP_DIS(\mprj_io_inp_dis[3] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[3] ),
+ .OUT(\mprj_io_out[3] ),
+ .PAD(\mprj_io[3] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[3] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[3] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[3] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[3] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[4] ),
+ .ANALOG_POL(\mprj_io_analog_pol[4] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[4] ),
+ .DM({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] }),
+ .ENABLE_H(\mprj_io_enh[4] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[4] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[4] ),
+ .HLD_OVR(\mprj_io_holdover[4] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[4] ),
+ .IN(\mprj_pads.io_in[4] ),
+ .INP_DIS(\mprj_io_inp_dis[4] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[4] ),
+ .OUT(\mprj_io_out[4] ),
+ .PAD(\mprj_io[4] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[4] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[4] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[4] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[4] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[5] ),
+ .ANALOG_POL(\mprj_io_analog_pol[5] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[5] ),
+ .DM({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] }),
+ .ENABLE_H(\mprj_io_enh[5] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[5] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[5] ),
+ .HLD_OVR(\mprj_io_holdover[5] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[5] ),
+ .IN(\mprj_pads.io_in[5] ),
+ .INP_DIS(\mprj_io_inp_dis[5] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[5] ),
+ .OUT(\mprj_io_out[5] ),
+ .PAD(\mprj_io[5] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[5] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[5] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[5] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[5] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[6] ),
+ .ANALOG_POL(\mprj_io_analog_pol[6] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[6] ),
+ .DM({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] }),
+ .ENABLE_H(\mprj_io_enh[6] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[6] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[6] ),
+ .HLD_OVR(\mprj_io_holdover[6] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[6] ),
+ .IN(\mprj_pads.io_in[6] ),
+ .INP_DIS(\mprj_io_inp_dis[6] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[6] ),
+ .OUT(\mprj_io_out[6] ),
+ .PAD(\mprj_io[6] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[6] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[6] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[6] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[6] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[7] ),
+ .ANALOG_POL(\mprj_io_analog_pol[7] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[7] ),
+ .DM({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] }),
+ .ENABLE_H(\mprj_io_enh[7] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[7] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[7] ),
+ .HLD_OVR(\mprj_io_holdover[7] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[7] ),
+ .IN(\mprj_pads.io_in[7] ),
+ .INP_DIS(\mprj_io_inp_dis[7] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[7] ),
+ .OUT(\mprj_io_out[7] ),
+ .PAD(\mprj_io[7] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[7] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[7] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[7] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[8] ),
+ .ANALOG_POL(\mprj_io_analog_pol[8] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[8] ),
+ .DM({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] }),
+ .ENABLE_H(\mprj_io_enh[8] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[8] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[8] ),
+ .HLD_OVR(\mprj_io_holdover[8] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[8] ),
+ .IN(\mprj_pads.io_in[8] ),
+ .INP_DIS(\mprj_io_inp_dis[8] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[8] ),
+ .OUT(\mprj_io_out[8] ),
+ .PAD(\mprj_io[8] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[8] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[8] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[8] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[9] ),
+ .ANALOG_POL(\mprj_io_analog_pol[9] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[9] ),
+ .DM({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] }),
+ .ENABLE_H(\mprj_io_enh[9] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[9] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[9] ),
+ .HLD_OVR(\mprj_io_holdover[9] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[9] ),
+ .IN(\mprj_pads.io_in[9] ),
+ .INP_DIS(\mprj_io_inp_dis[9] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[9] ),
+ .OUT(\mprj_io_out[9] ),
+ .PAD(\mprj_io[9] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[2] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[9] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[9] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[9] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[18] ),
+ .ANALOG_POL(\mprj_io_analog_pol[18] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[18] ),
+ .DM({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] }),
+ .ENABLE_H(\mprj_io_enh[18] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[18] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[18] ),
+ .HLD_OVR(\mprj_io_holdover[18] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[18] ),
+ .IN(\mprj_pads.io_in[18] ),
+ .INP_DIS(\mprj_io_inp_dis[18] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[18] ),
+ .OUT(\mprj_io_out[18] ),
+ .PAD(\mprj_io[18] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[11] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[18] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[18] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[18] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[28] ),
+ .ANALOG_POL(\mprj_io_analog_pol[28] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[28] ),
+ .DM({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] }),
+ .ENABLE_H(\mprj_io_enh[28] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[28] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[28] ),
+ .HLD_OVR(\mprj_io_holdover[28] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[28] ),
+ .IN(\mprj_pads.io_in[28] ),
+ .INP_DIS(\mprj_io_inp_dis[28] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[28] ),
+ .OUT(\mprj_io_out[28] ),
+ .PAD(\mprj_io[28] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[21] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[28] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[28] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[28] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[29] ),
+ .ANALOG_POL(\mprj_io_analog_pol[29] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[29] ),
+ .DM({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] }),
+ .ENABLE_H(\mprj_io_enh[29] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[29] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[29] ),
+ .HLD_OVR(\mprj_io_holdover[29] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[29] ),
+ .IN(\mprj_pads.io_in[29] ),
+ .INP_DIS(\mprj_io_inp_dis[29] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[29] ),
+ .OUT(\mprj_io_out[29] ),
+ .PAD(\mprj_io[29] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[22] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[29] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[29] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[29] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[30] ),
+ .ANALOG_POL(\mprj_io_analog_pol[30] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[30] ),
+ .DM({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] }),
+ .ENABLE_H(\mprj_io_enh[30] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[30] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[30] ),
+ .HLD_OVR(\mprj_io_holdover[30] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[30] ),
+ .IN(\mprj_pads.io_in[30] ),
+ .INP_DIS(\mprj_io_inp_dis[30] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[30] ),
+ .OUT(\mprj_io_out[30] ),
+ .PAD(\mprj_io[30] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[23] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[30] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[30] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[30] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[31] ),
+ .ANALOG_POL(\mprj_io_analog_pol[31] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[31] ),
+ .DM({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] }),
+ .ENABLE_H(\mprj_io_enh[31] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[31] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[31] ),
+ .HLD_OVR(\mprj_io_holdover[31] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[31] ),
+ .IN(\mprj_pads.io_in[31] ),
+ .INP_DIS(\mprj_io_inp_dis[31] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[31] ),
+ .OUT(\mprj_io_out[31] ),
+ .PAD(\mprj_io[31] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[24] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[31] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[31] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[31] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[14] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[32] ),
+ .ANALOG_POL(\mprj_io_analog_pol[32] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[32] ),
+ .DM({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] }),
+ .ENABLE_H(\mprj_io_enh[32] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[32] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[32] ),
+ .HLD_OVR(\mprj_io_holdover[32] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[32] ),
+ .IN(\mprj_pads.io_in[32] ),
+ .INP_DIS(\mprj_io_inp_dis[32] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[32] ),
+ .OUT(\mprj_io_out[32] ),
+ .PAD(\mprj_io[32] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[25] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[32] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[32] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[32] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[15] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[33] ),
+ .ANALOG_POL(\mprj_io_analog_pol[33] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[33] ),
+ .DM({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] }),
+ .ENABLE_H(\mprj_io_enh[33] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[33] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[33] ),
+ .HLD_OVR(\mprj_io_holdover[33] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[33] ),
+ .IN(\mprj_pads.io_in[33] ),
+ .INP_DIS(\mprj_io_inp_dis[33] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[33] ),
+ .OUT(\mprj_io_out[33] ),
+ .PAD(\mprj_io[33] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[26] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[33] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[33] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[33] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[16] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[34] ),
+ .ANALOG_POL(\mprj_io_analog_pol[34] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[34] ),
+ .DM({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] }),
+ .ENABLE_H(\mprj_io_enh[34] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[34] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[34] ),
+ .HLD_OVR(\mprj_io_holdover[34] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[34] ),
+ .IN(\mprj_pads.io_in[34] ),
+ .INP_DIS(\mprj_io_inp_dis[34] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[34] ),
+ .OUT(\mprj_io_out[34] ),
+ .PAD(\mprj_io[34] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[27] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[34] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[34] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[34] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[17] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[35] ),
+ .ANALOG_POL(\mprj_io_analog_pol[35] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[35] ),
+ .DM({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] }),
+ .ENABLE_H(\mprj_io_enh[35] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[35] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[35] ),
+ .HLD_OVR(\mprj_io_holdover[35] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[35] ),
+ .IN(\mprj_pads.io_in[35] ),
+ .INP_DIS(\mprj_io_inp_dis[35] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[35] ),
+ .OUT(\mprj_io_out[35] ),
+ .PAD(\mprj_io[35] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[28] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[35] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[35] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[35] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[18] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[36] ),
+ .ANALOG_POL(\mprj_io_analog_pol[36] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[36] ),
+ .DM({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] }),
+ .ENABLE_H(\mprj_io_enh[36] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[36] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[36] ),
+ .HLD_OVR(\mprj_io_holdover[36] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[36] ),
+ .IN(\mprj_pads.io_in[36] ),
+ .INP_DIS(\mprj_io_inp_dis[36] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[36] ),
+ .OUT(\mprj_io_out[36] ),
+ .PAD(\mprj_io[36] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[29] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[36] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[36] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[36] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[19] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[37] ),
+ .ANALOG_POL(\mprj_io_analog_pol[37] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[37] ),
+ .DM({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] }),
+ .ENABLE_H(\mprj_io_enh[37] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[37] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[37] ),
+ .HLD_OVR(\mprj_io_holdover[37] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[37] ),
+ .IN(\mprj_pads.io_in[37] ),
+ .INP_DIS(\mprj_io_inp_dis[37] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[37] ),
+ .OUT(\mprj_io_out[37] ),
+ .PAD(\mprj_io[37] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[30] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[37] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[37] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[37] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[19] ),
+ .ANALOG_POL(\mprj_io_analog_pol[19] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[19] ),
+ .DM({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] }),
+ .ENABLE_H(\mprj_io_enh[19] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[19] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[19] ),
+ .HLD_OVR(\mprj_io_holdover[19] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[19] ),
+ .IN(\mprj_pads.io_in[19] ),
+ .INP_DIS(\mprj_io_inp_dis[19] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[19] ),
+ .OUT(\mprj_io_out[19] ),
+ .PAD(\mprj_io[19] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[12] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[19] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[19] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[19] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[20] ),
+ .ANALOG_POL(\mprj_io_analog_pol[20] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[20] ),
+ .DM({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] }),
+ .ENABLE_H(\mprj_io_enh[20] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[20] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[20] ),
+ .HLD_OVR(\mprj_io_holdover[20] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[20] ),
+ .IN(\mprj_pads.io_in[20] ),
+ .INP_DIS(\mprj_io_inp_dis[20] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[20] ),
+ .OUT(\mprj_io_out[20] ),
+ .PAD(\mprj_io[20] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[13] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[20] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[20] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[20] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[21] ),
+ .ANALOG_POL(\mprj_io_analog_pol[21] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[21] ),
+ .DM({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] }),
+ .ENABLE_H(\mprj_io_enh[21] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[21] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[21] ),
+ .HLD_OVR(\mprj_io_holdover[21] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[21] ),
+ .IN(\mprj_pads.io_in[21] ),
+ .INP_DIS(\mprj_io_inp_dis[21] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[21] ),
+ .OUT(\mprj_io_out[21] ),
+ .PAD(\mprj_io[21] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[14] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[21] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[21] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[21] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[22] ),
+ .ANALOG_POL(\mprj_io_analog_pol[22] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[22] ),
+ .DM({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] }),
+ .ENABLE_H(\mprj_io_enh[22] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[22] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[22] ),
+ .HLD_OVR(\mprj_io_holdover[22] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[22] ),
+ .IN(\mprj_pads.io_in[22] ),
+ .INP_DIS(\mprj_io_inp_dis[22] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[22] ),
+ .OUT(\mprj_io_out[22] ),
+ .PAD(\mprj_io[22] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[15] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[22] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[22] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[22] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[23] ),
+ .ANALOG_POL(\mprj_io_analog_pol[23] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[23] ),
+ .DM({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] }),
+ .ENABLE_H(\mprj_io_enh[23] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[23] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[23] ),
+ .HLD_OVR(\mprj_io_holdover[23] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[23] ),
+ .IN(\mprj_pads.io_in[23] ),
+ .INP_DIS(\mprj_io_inp_dis[23] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[23] ),
+ .OUT(\mprj_io_out[23] ),
+ .PAD(\mprj_io[23] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[16] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[23] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[23] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[23] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[24] ),
+ .ANALOG_POL(\mprj_io_analog_pol[24] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[24] ),
+ .DM({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] }),
+ .ENABLE_H(\mprj_io_enh[24] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[24] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[24] ),
+ .HLD_OVR(\mprj_io_holdover[24] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[24] ),
+ .IN(\mprj_pads.io_in[24] ),
+ .INP_DIS(\mprj_io_inp_dis[24] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[24] ),
+ .OUT(\mprj_io_out[24] ),
+ .PAD(\mprj_io[24] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[17] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[24] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[24] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[24] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[25] ),
+ .ANALOG_POL(\mprj_io_analog_pol[25] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[25] ),
+ .DM({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] }),
+ .ENABLE_H(\mprj_io_enh[25] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[25] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[25] ),
+ .HLD_OVR(\mprj_io_holdover[25] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[25] ),
+ .IN(\mprj_pads.io_in[25] ),
+ .INP_DIS(\mprj_io_inp_dis[25] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[25] ),
+ .OUT(\mprj_io_out[25] ),
+ .PAD(\mprj_io[25] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[18] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[25] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[25] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[25] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[26] ),
+ .ANALOG_POL(\mprj_io_analog_pol[26] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[26] ),
+ .DM({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] }),
+ .ENABLE_H(\mprj_io_enh[26] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[26] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[26] ),
+ .HLD_OVR(\mprj_io_holdover[26] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[26] ),
+ .IN(\mprj_pads.io_in[26] ),
+ .INP_DIS(\mprj_io_inp_dis[26] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[26] ),
+ .OUT(\mprj_io_out[26] ),
+ .PAD(\mprj_io[26] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[19] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[26] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[26] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[26] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[27] ),
+ .ANALOG_POL(\mprj_io_analog_pol[27] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[27] ),
+ .DM({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] }),
+ .ENABLE_H(\mprj_io_enh[27] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[27] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[27] ),
+ .HLD_OVR(\mprj_io_holdover[27] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[27] ),
+ .IN(\mprj_pads.io_in[27] ),
+ .INP_DIS(\mprj_io_inp_dis[27] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[27] ),
+ .OUT(\mprj_io_out[27] ),
+ .PAD(\mprj_io[27] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[20] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[27] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[27] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[27] )
+ );
+ sky130_fd_io__top_xres4v2 resetb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DISABLE_PULLUP_H(vssio),
+ .ENABLE_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .EN_VDDIO_SIG_H(vssio),
+ .FILT_IN_H(vssio),
+ .INP_SEL_H(vssio),
+ .PAD(resetb),
+ .PAD_A_ESD_H(xresloop),
+ .PULLUP_H(vssio),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(),
+ .TIE_WEAK_HI_H(xresloop),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .XRES_H_N(resetb_core_h)
+ );
+ sky130_ef_io__corner_pad user1_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclmap_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad user2_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclmap_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ assign \mprj_pads.slow_sel[19] = \mprj_io_slow_sel[19] ;
+ assign \mprj_pads.slow_sel[18] = \mprj_io_slow_sel[18] ;
+ assign \mprj_pads.slow_sel[17] = \mprj_io_slow_sel[17] ;
+ assign \mprj_pads.slow_sel[16] = \mprj_io_slow_sel[16] ;
+ assign \mprj_pads.slow_sel[15] = \mprj_io_slow_sel[15] ;
+ assign \mprj_pads.slow_sel[14] = \mprj_io_slow_sel[14] ;
+ assign \mprj_pads.slow_sel[13] = \mprj_io_slow_sel[13] ;
+ assign \mprj_pads.slow_sel[12] = \mprj_io_slow_sel[12] ;
+ assign \mprj_pads.slow_sel[11] = \mprj_io_slow_sel[11] ;
+ assign \mprj_pads.slow_sel[10] = \mprj_io_slow_sel[10] ;
+ assign \mprj_pads.slow_sel[9] = \mprj_io_slow_sel[9] ;
+ assign \mprj_pads.slow_sel[8] = \mprj_io_slow_sel[8] ;
+ assign \mprj_pads.slow_sel[7] = \mprj_io_slow_sel[7] ;
+ assign \mprj_pads.slow_sel[6] = \mprj_io_slow_sel[6] ;
+ assign \mprj_pads.slow_sel[5] = \mprj_io_slow_sel[5] ;
+ assign \mprj_pads.slow_sel[4] = \mprj_io_slow_sel[4] ;
+ assign \mprj_pads.slow_sel[3] = \mprj_io_slow_sel[3] ;
+ assign \mprj_pads.slow_sel[2] = \mprj_io_slow_sel[2] ;
+ assign \mprj_pads.slow_sel[1] = \mprj_io_slow_sel[1] ;
+ assign \mprj_pads.slow_sel[0] = \mprj_io_slow_sel[0] ;
+ assign \mprj_pads.enh[37] = \mprj_io_enh[37] ;
+ assign \mprj_pads.enh[36] = \mprj_io_enh[36] ;
+ assign \mprj_pads.enh[35] = \mprj_io_enh[35] ;
+ assign \mprj_pads.enh[34] = \mprj_io_enh[34] ;
+ assign \mprj_pads.enh[33] = \mprj_io_enh[33] ;
+ assign \mprj_pads.enh[32] = \mprj_io_enh[32] ;
+ assign \mprj_pads.enh[31] = \mprj_io_enh[31] ;
+ assign \mprj_pads.enh[30] = \mprj_io_enh[30] ;
+ assign \mprj_pads.enh[29] = \mprj_io_enh[29] ;
+ assign \mprj_pads.enh[28] = \mprj_io_enh[28] ;
+ assign \mprj_pads.enh[27] = \mprj_io_enh[27] ;
+ assign \mprj_pads.enh[26] = \mprj_io_enh[26] ;
+ assign \mprj_pads.enh[25] = \mprj_io_enh[25] ;
+ assign \mprj_pads.enh[24] = \mprj_io_enh[24] ;
+ assign \mprj_pads.enh[23] = \mprj_io_enh[23] ;
+ assign \mprj_pads.enh[22] = \mprj_io_enh[22] ;
+ assign \mprj_pads.enh[21] = \mprj_io_enh[21] ;
+ assign \mprj_pads.enh[20] = \mprj_io_enh[20] ;
+ assign \mprj_pads.enh[19] = \mprj_io_enh[19] ;
+ assign \mprj_pads.enh[18] = \mprj_io_enh[18] ;
+ assign \mprj_pads.enh[17] = \mprj_io_enh[17] ;
+ assign \mprj_pads.enh[16] = \mprj_io_enh[16] ;
+ assign \mprj_pads.enh[15] = \mprj_io_enh[15] ;
+ assign \mprj_pads.enh[14] = \mprj_io_enh[14] ;
+ assign \mprj_pads.enh[13] = \mprj_io_enh[13] ;
+ assign \mprj_pads.enh[12] = \mprj_io_enh[12] ;
+ assign \mprj_pads.enh[11] = \mprj_io_enh[11] ;
+ assign \mprj_pads.enh[10] = \mprj_io_enh[10] ;
+ assign \mprj_pads.enh[9] = \mprj_io_enh[9] ;
+ assign \mprj_pads.enh[8] = \mprj_io_enh[8] ;
+ assign \mprj_pads.enh[7] = \mprj_io_enh[7] ;
+ assign \mprj_pads.enh[6] = \mprj_io_enh[6] ;
+ assign \mprj_pads.enh[5] = \mprj_io_enh[5] ;
+ assign \mprj_pads.enh[4] = \mprj_io_enh[4] ;
+ assign \mprj_pads.enh[3] = \mprj_io_enh[3] ;
+ assign \mprj_pads.enh[2] = \mprj_io_enh[2] ;
+ assign \mprj_pads.enh[1] = \mprj_io_enh[1] ;
+ assign \mprj_pads.enh[0] = \mprj_io_enh[0] ;
+ assign \mprj_pads.hldh_n[37] = \mprj_io_hldh_n[37] ;
+ assign \mprj_pads.hldh_n[36] = \mprj_io_hldh_n[36] ;
+ assign \mprj_pads.hldh_n[35] = \mprj_io_hldh_n[35] ;
+ assign \mprj_pads.hldh_n[34] = \mprj_io_hldh_n[34] ;
+ assign \mprj_pads.hldh_n[33] = \mprj_io_hldh_n[33] ;
+ assign \mprj_pads.hldh_n[32] = \mprj_io_hldh_n[32] ;
+ assign \mprj_pads.hldh_n[31] = \mprj_io_hldh_n[31] ;
+ assign \mprj_pads.hldh_n[30] = \mprj_io_hldh_n[30] ;
+ assign \mprj_pads.hldh_n[29] = \mprj_io_hldh_n[29] ;
+ assign \mprj_pads.hldh_n[28] = \mprj_io_hldh_n[28] ;
+ assign \mprj_pads.hldh_n[27] = \mprj_io_hldh_n[27] ;
+ assign \mprj_pads.hldh_n[26] = \mprj_io_hldh_n[26] ;
+ assign \mprj_pads.hldh_n[25] = \mprj_io_hldh_n[25] ;
+ assign \mprj_pads.hldh_n[24] = \mprj_io_hldh_n[24] ;
+ assign \mprj_pads.hldh_n[23] = \mprj_io_hldh_n[23] ;
+ assign \mprj_pads.hldh_n[22] = \mprj_io_hldh_n[22] ;
+ assign \mprj_pads.hldh_n[21] = \mprj_io_hldh_n[21] ;
+ assign \mprj_pads.hldh_n[20] = \mprj_io_hldh_n[20] ;
+ assign \mprj_pads.hldh_n[19] = \mprj_io_hldh_n[19] ;
+ assign \mprj_pads.hldh_n[18] = \mprj_io_hldh_n[18] ;
+ assign \mprj_pads.hldh_n[17] = \mprj_io_hldh_n[17] ;
+ assign \mprj_pads.hldh_n[16] = \mprj_io_hldh_n[16] ;
+ assign \mprj_pads.hldh_n[15] = \mprj_io_hldh_n[15] ;
+ assign \mprj_pads.hldh_n[14] = \mprj_io_hldh_n[14] ;
+ assign \mprj_pads.hldh_n[13] = \mprj_io_hldh_n[13] ;
+ assign \mprj_pads.hldh_n[12] = \mprj_io_hldh_n[12] ;
+ assign \mprj_pads.hldh_n[11] = \mprj_io_hldh_n[11] ;
+ assign \mprj_pads.hldh_n[10] = \mprj_io_hldh_n[10] ;
+ assign \mprj_pads.hldh_n[9] = \mprj_io_hldh_n[9] ;
+ assign \mprj_pads.hldh_n[8] = \mprj_io_hldh_n[8] ;
+ assign \mprj_pads.hldh_n[7] = \mprj_io_hldh_n[7] ;
+ assign \mprj_pads.hldh_n[6] = \mprj_io_hldh_n[6] ;
+ assign \mprj_pads.hldh_n[5] = \mprj_io_hldh_n[5] ;
+ assign \mprj_pads.hldh_n[4] = \mprj_io_hldh_n[4] ;
+ assign \mprj_pads.hldh_n[3] = \mprj_io_hldh_n[3] ;
+ assign \mprj_pads.hldh_n[2] = \mprj_io_hldh_n[2] ;
+ assign \mprj_pads.hldh_n[1] = \mprj_io_hldh_n[1] ;
+ assign \mprj_pads.hldh_n[0] = \mprj_io_hldh_n[0] ;
+ assign \mprj_pads.io[37] = \mprj_io[37] ;
+ assign \mprj_pads.io[36] = \mprj_io[36] ;
+ assign \mprj_pads.io[35] = \mprj_io[35] ;
+ assign \mprj_pads.io[34] = \mprj_io[34] ;
+ assign \mprj_pads.io[33] = \mprj_io[33] ;
+ assign \mprj_pads.io[32] = \mprj_io[32] ;
+ assign \mprj_pads.io[31] = \mprj_io[31] ;
+ assign \mprj_pads.io[30] = \mprj_io[30] ;
+ assign \mprj_pads.io[29] = \mprj_io[29] ;
+ assign \mprj_pads.io[28] = \mprj_io[28] ;
+ assign \mprj_pads.io[27] = \mprj_io[27] ;
+ assign \mprj_pads.io[26] = \mprj_io[26] ;
+ assign \mprj_pads.io[25] = \mprj_io[25] ;
+ assign \mprj_pads.io[24] = \mprj_io[24] ;
+ assign \mprj_pads.io[23] = \mprj_io[23] ;
+ assign \mprj_pads.io[22] = \mprj_io[22] ;
+ assign \mprj_pads.io[21] = \mprj_io[21] ;
+ assign \mprj_pads.io[20] = \mprj_io[20] ;
+ assign \mprj_pads.io[19] = \mprj_io[19] ;
+ assign \mprj_pads.io[18] = \mprj_io[18] ;
+ assign \mprj_pads.io[17] = \mprj_io[17] ;
+ assign \mprj_pads.io[16] = \mprj_io[16] ;
+ assign \mprj_pads.io[15] = \mprj_io[15] ;
+ assign \mprj_pads.io[14] = \mprj_io[14] ;
+ assign \mprj_pads.io[13] = \mprj_io[13] ;
+ assign \mprj_pads.io[12] = \mprj_io[12] ;
+ assign \mprj_pads.io[11] = \mprj_io[11] ;
+ assign \mprj_pads.io[10] = \mprj_io[10] ;
+ assign \mprj_pads.io[9] = \mprj_io[9] ;
+ assign \mprj_pads.io[8] = \mprj_io[8] ;
+ assign \mprj_pads.io[7] = \mprj_io[7] ;
+ assign \mprj_pads.io[6] = \mprj_io[6] ;
+ assign \mprj_pads.io[5] = \mprj_io[5] ;
+ assign \mprj_pads.io[4] = \mprj_io[4] ;
+ assign \mprj_pads.io[3] = \mprj_io[3] ;
+ assign \mprj_pads.io[2] = \mprj_io[2] ;
+ assign \mprj_pads.io[1] = \mprj_io[1] ;
+ assign \mprj_pads.io[0] = \mprj_io[0] ;
+ assign \mprj_pads.analog_io[30] = \mprj_analog_io[30] ;
+ assign \mprj_pads.analog_io[29] = \mprj_analog_io[29] ;
+ assign \mprj_pads.analog_io[28] = \mprj_analog_io[28] ;
+ assign \mprj_pads.analog_io[27] = \mprj_analog_io[27] ;
+ assign \mprj_pads.analog_io[26] = \mprj_analog_io[26] ;
+ assign \mprj_pads.analog_io[25] = \mprj_analog_io[25] ;
+ assign \mprj_pads.analog_io[24] = \mprj_analog_io[24] ;
+ assign \mprj_pads.analog_io[23] = \mprj_analog_io[23] ;
+ assign \mprj_pads.analog_io[22] = \mprj_analog_io[22] ;
+ assign \mprj_pads.analog_io[21] = \mprj_analog_io[21] ;
+ assign \mprj_pads.analog_io[20] = \mprj_analog_io[20] ;
+ assign \mprj_pads.analog_io[19] = \mprj_analog_io[19] ;
+ assign \mprj_pads.analog_io[18] = \mprj_analog_io[18] ;
+ assign \mprj_pads.analog_io[17] = \mprj_analog_io[17] ;
+ assign \mprj_pads.analog_io[16] = \mprj_analog_io[16] ;
+ assign \mprj_pads.analog_io[15] = \mprj_analog_io[15] ;
+ assign \mprj_pads.analog_io[14] = \mprj_analog_io[14] ;
+ assign \mprj_pads.analog_io[13] = \mprj_analog_io[13] ;
+ assign \mprj_pads.analog_io[12] = \mprj_analog_io[12] ;
+ assign \mprj_pads.analog_io[11] = \mprj_analog_io[11] ;
+ assign \mprj_pads.analog_io[10] = \mprj_analog_io[10] ;
+ assign \mprj_pads.analog_io[9] = \mprj_analog_io[9] ;
+ assign \mprj_pads.analog_io[8] = \mprj_analog_io[8] ;
+ assign \mprj_pads.analog_io[7] = \mprj_analog_io[7] ;
+ assign \mprj_pads.analog_io[6] = \mprj_analog_io[6] ;
+ assign \mprj_pads.analog_io[5] = \mprj_analog_io[5] ;
+ assign \mprj_pads.analog_io[4] = \mprj_analog_io[4] ;
+ assign \mprj_pads.analog_io[3] = \mprj_analog_io[3] ;
+ assign \mprj_pads.analog_io[2] = \mprj_analog_io[2] ;
+ assign \mprj_pads.analog_io[1] = \mprj_analog_io[1] ;
+ assign \mprj_pads.analog_io[0] = \mprj_analog_io[0] ;
+ assign \flash_io1_mode[2] = flash_io1_ieb_core;
+ assign \flash_io1_mode[1] = flash_io1_ieb_core;
+ assign \flash_io1_mode[0] = flash_io1_oeb_core;
+ assign \dm_all[2] = gpio_mode1_core;
+ assign \dm_all[1] = gpio_mode1_core;
+ assign \dm_all[0] = gpio_mode0_core;
+ assign \mprj_pads.analog_sel[37] = \mprj_io_analog_sel[37] ;
+ assign \mprj_pads.analog_sel[36] = \mprj_io_analog_sel[36] ;
+ assign \mprj_pads.analog_sel[35] = \mprj_io_analog_sel[35] ;
+ assign \mprj_pads.analog_sel[34] = \mprj_io_analog_sel[34] ;
+ assign \mprj_pads.analog_sel[33] = \mprj_io_analog_sel[33] ;
+ assign \mprj_pads.analog_sel[32] = \mprj_io_analog_sel[32] ;
+ assign \mprj_pads.analog_sel[31] = \mprj_io_analog_sel[31] ;
+ assign \mprj_pads.analog_sel[30] = \mprj_io_analog_sel[30] ;
+ assign \mprj_pads.analog_sel[29] = \mprj_io_analog_sel[29] ;
+ assign \mprj_pads.analog_sel[28] = \mprj_io_analog_sel[28] ;
+ assign \mprj_pads.analog_sel[27] = \mprj_io_analog_sel[27] ;
+ assign \mprj_pads.analog_sel[26] = \mprj_io_analog_sel[26] ;
+ assign \mprj_pads.analog_sel[25] = \mprj_io_analog_sel[25] ;
+ assign \mprj_pads.analog_sel[24] = \mprj_io_analog_sel[24] ;
+ assign \mprj_pads.analog_sel[23] = \mprj_io_analog_sel[23] ;
+ assign \mprj_pads.analog_sel[22] = \mprj_io_analog_sel[22] ;
+ assign \mprj_pads.analog_sel[21] = \mprj_io_analog_sel[21] ;
+ assign \mprj_pads.analog_sel[20] = \mprj_io_analog_sel[20] ;
+ assign \mprj_pads.analog_sel[19] = \mprj_io_analog_sel[19] ;
+ assign \mprj_pads.analog_sel[18] = \mprj_io_analog_sel[18] ;
+ assign \mprj_pads.analog_sel[17] = \mprj_io_analog_sel[17] ;
+ assign \mprj_pads.analog_sel[16] = \mprj_io_analog_sel[16] ;
+ assign \mprj_pads.analog_sel[15] = \mprj_io_analog_sel[15] ;
+ assign \mprj_pads.analog_sel[14] = \mprj_io_analog_sel[14] ;
+ assign \mprj_pads.analog_sel[13] = \mprj_io_analog_sel[13] ;
+ assign \mprj_pads.analog_sel[12] = \mprj_io_analog_sel[12] ;
+ assign \mprj_pads.analog_sel[11] = \mprj_io_analog_sel[11] ;
+ assign \mprj_pads.analog_sel[10] = \mprj_io_analog_sel[10] ;
+ assign \mprj_pads.analog_sel[9] = \mprj_io_analog_sel[9] ;
+ assign \mprj_pads.analog_sel[8] = \mprj_io_analog_sel[8] ;
+ assign \mprj_pads.analog_sel[7] = \mprj_io_analog_sel[7] ;
+ assign \mprj_pads.analog_sel[6] = \mprj_io_analog_sel[6] ;
+ assign \mprj_pads.analog_sel[5] = \mprj_io_analog_sel[5] ;
+ assign \mprj_pads.analog_sel[4] = \mprj_io_analog_sel[4] ;
+ assign \mprj_pads.analog_sel[3] = \mprj_io_analog_sel[3] ;
+ assign \mprj_pads.analog_sel[2] = \mprj_io_analog_sel[2] ;
+ assign \mprj_pads.analog_sel[1] = \mprj_io_analog_sel[1] ;
+ assign \mprj_pads.analog_sel[0] = \mprj_io_analog_sel[0] ;
+ assign \mprj_pads.vtrip_sel[37] = \mprj_io_vtrip_sel[37] ;
+ assign \mprj_pads.vtrip_sel[36] = \mprj_io_vtrip_sel[36] ;
+ assign \mprj_pads.vtrip_sel[35] = \mprj_io_vtrip_sel[35] ;
+ assign \mprj_pads.vtrip_sel[34] = \mprj_io_vtrip_sel[34] ;
+ assign \mprj_pads.vtrip_sel[33] = \mprj_io_vtrip_sel[33] ;
+ assign \mprj_pads.vtrip_sel[32] = \mprj_io_vtrip_sel[32] ;
+ assign \mprj_pads.vtrip_sel[31] = \mprj_io_vtrip_sel[31] ;
+ assign \mprj_pads.vtrip_sel[30] = \mprj_io_vtrip_sel[30] ;
+ assign \mprj_pads.vtrip_sel[29] = \mprj_io_vtrip_sel[29] ;
+ assign \mprj_pads.vtrip_sel[28] = \mprj_io_vtrip_sel[28] ;
+ assign \mprj_pads.vtrip_sel[27] = \mprj_io_vtrip_sel[27] ;
+ assign \mprj_pads.vtrip_sel[26] = \mprj_io_vtrip_sel[26] ;
+ assign \mprj_pads.vtrip_sel[25] = \mprj_io_vtrip_sel[25] ;
+ assign \mprj_pads.vtrip_sel[24] = \mprj_io_vtrip_sel[24] ;
+ assign \mprj_pads.vtrip_sel[23] = \mprj_io_vtrip_sel[23] ;
+ assign \mprj_pads.vtrip_sel[22] = \mprj_io_vtrip_sel[22] ;
+ assign \mprj_pads.vtrip_sel[21] = \mprj_io_vtrip_sel[21] ;
+ assign \mprj_pads.vtrip_sel[20] = \mprj_io_vtrip_sel[20] ;
+ assign \mprj_pads.vtrip_sel[19] = \mprj_io_vtrip_sel[19] ;
+ assign \mprj_pads.vtrip_sel[18] = \mprj_io_vtrip_sel[18] ;
+ assign \mprj_pads.vtrip_sel[17] = \mprj_io_vtrip_sel[17] ;
+ assign \mprj_pads.vtrip_sel[16] = \mprj_io_vtrip_sel[16] ;
+ assign \mprj_pads.vtrip_sel[15] = \mprj_io_vtrip_sel[15] ;
+ assign \mprj_pads.vtrip_sel[14] = \mprj_io_vtrip_sel[14] ;
+ assign \mprj_pads.vtrip_sel[13] = \mprj_io_vtrip_sel[13] ;
+ assign \mprj_pads.vtrip_sel[12] = \mprj_io_vtrip_sel[12] ;
+ assign \mprj_pads.vtrip_sel[11] = \mprj_io_vtrip_sel[11] ;
+ assign \mprj_pads.vtrip_sel[10] = \mprj_io_vtrip_sel[10] ;
+ assign \mprj_pads.vtrip_sel[9] = \mprj_io_vtrip_sel[9] ;
+ assign \mprj_pads.vtrip_sel[8] = \mprj_io_vtrip_sel[8] ;
+ assign \mprj_pads.vtrip_sel[7] = \mprj_io_vtrip_sel[7] ;
+ assign \mprj_pads.vtrip_sel[6] = \mprj_io_vtrip_sel[6] ;
+ assign \mprj_pads.vtrip_sel[5] = \mprj_io_vtrip_sel[5] ;
+ assign \mprj_pads.vtrip_sel[4] = \mprj_io_vtrip_sel[4] ;
+ assign \mprj_pads.vtrip_sel[3] = \mprj_io_vtrip_sel[3] ;
+ assign \mprj_pads.vtrip_sel[2] = \mprj_io_vtrip_sel[2] ;
+ assign \mprj_pads.vtrip_sel[1] = \mprj_io_vtrip_sel[1] ;
+ assign \mprj_pads.vtrip_sel[0] = \mprj_io_vtrip_sel[0] ;
+ assign \mprj_pads.analog_pol[37] = \mprj_io_analog_pol[37] ;
+ assign \mprj_pads.analog_pol[36] = \mprj_io_analog_pol[36] ;
+ assign \mprj_pads.analog_pol[35] = \mprj_io_analog_pol[35] ;
+ assign \mprj_pads.analog_pol[34] = \mprj_io_analog_pol[34] ;
+ assign \mprj_pads.analog_pol[33] = \mprj_io_analog_pol[33] ;
+ assign \mprj_pads.analog_pol[32] = \mprj_io_analog_pol[32] ;
+ assign \mprj_pads.analog_pol[31] = \mprj_io_analog_pol[31] ;
+ assign \mprj_pads.analog_pol[30] = \mprj_io_analog_pol[30] ;
+ assign \mprj_pads.analog_pol[29] = \mprj_io_analog_pol[29] ;
+ assign \mprj_pads.analog_pol[28] = \mprj_io_analog_pol[28] ;
+ assign \mprj_pads.analog_pol[27] = \mprj_io_analog_pol[27] ;
+ assign \mprj_pads.analog_pol[26] = \mprj_io_analog_pol[26] ;
+ assign \mprj_pads.analog_pol[25] = \mprj_io_analog_pol[25] ;
+ assign \mprj_pads.analog_pol[24] = \mprj_io_analog_pol[24] ;
+ assign \mprj_pads.analog_pol[23] = \mprj_io_analog_pol[23] ;
+ assign \mprj_pads.analog_pol[22] = \mprj_io_analog_pol[22] ;
+ assign \mprj_pads.analog_pol[21] = \mprj_io_analog_pol[21] ;
+ assign \mprj_pads.analog_pol[20] = \mprj_io_analog_pol[20] ;
+ assign \mprj_pads.analog_pol[19] = \mprj_io_analog_pol[19] ;
+ assign \mprj_pads.analog_pol[18] = \mprj_io_analog_pol[18] ;
+ assign \mprj_pads.analog_pol[17] = \mprj_io_analog_pol[17] ;
+ assign \mprj_pads.analog_pol[16] = \mprj_io_analog_pol[16] ;
+ assign \mprj_pads.analog_pol[15] = \mprj_io_analog_pol[15] ;
+ assign \mprj_pads.analog_pol[14] = \mprj_io_analog_pol[14] ;
+ assign \mprj_pads.analog_pol[13] = \mprj_io_analog_pol[13] ;
+ assign \mprj_pads.analog_pol[12] = \mprj_io_analog_pol[12] ;
+ assign \mprj_pads.analog_pol[11] = \mprj_io_analog_pol[11] ;
+ assign \mprj_pads.analog_pol[10] = \mprj_io_analog_pol[10] ;
+ assign \mprj_pads.analog_pol[9] = \mprj_io_analog_pol[9] ;
+ assign \mprj_pads.analog_pol[8] = \mprj_io_analog_pol[8] ;
+ assign \mprj_pads.analog_pol[7] = \mprj_io_analog_pol[7] ;
+ assign \mprj_pads.analog_pol[6] = \mprj_io_analog_pol[6] ;
+ assign \mprj_pads.analog_pol[5] = \mprj_io_analog_pol[5] ;
+ assign \mprj_pads.analog_pol[4] = \mprj_io_analog_pol[4] ;
+ assign \mprj_pads.analog_pol[3] = \mprj_io_analog_pol[3] ;
+ assign \mprj_pads.analog_pol[2] = \mprj_io_analog_pol[2] ;
+ assign \mprj_pads.analog_pol[1] = \mprj_io_analog_pol[1] ;
+ assign \mprj_pads.analog_pol[0] = \mprj_io_analog_pol[0] ;
+ assign \mprj_pads.oeb[37] = \mprj_io_oeb[37] ;
+ assign \mprj_pads.oeb[36] = \mprj_io_oeb[36] ;
+ assign \mprj_pads.oeb[35] = \mprj_io_oeb[35] ;
+ assign \mprj_pads.oeb[34] = \mprj_io_oeb[34] ;
+ assign \mprj_pads.oeb[33] = \mprj_io_oeb[33] ;
+ assign \mprj_pads.oeb[32] = \mprj_io_oeb[32] ;
+ assign \mprj_pads.oeb[31] = \mprj_io_oeb[31] ;
+ assign \mprj_pads.oeb[30] = \mprj_io_oeb[30] ;
+ assign \mprj_pads.oeb[29] = \mprj_io_oeb[29] ;
+ assign \mprj_pads.oeb[28] = \mprj_io_oeb[28] ;
+ assign \mprj_pads.oeb[27] = \mprj_io_oeb[27] ;
+ assign \mprj_pads.oeb[26] = \mprj_io_oeb[26] ;
+ assign \mprj_pads.oeb[25] = \mprj_io_oeb[25] ;
+ assign \mprj_pads.oeb[24] = \mprj_io_oeb[24] ;
+ assign \mprj_pads.oeb[23] = \mprj_io_oeb[23] ;
+ assign \mprj_pads.oeb[22] = \mprj_io_oeb[22] ;
+ assign \mprj_pads.oeb[21] = \mprj_io_oeb[21] ;
+ assign \mprj_pads.oeb[20] = \mprj_io_oeb[20] ;
+ assign \mprj_pads.oeb[19] = \mprj_io_oeb[19] ;
+ assign \mprj_pads.oeb[18] = \mprj_io_oeb[18] ;
+ assign \mprj_pads.oeb[17] = \mprj_io_oeb[17] ;
+ assign \mprj_pads.oeb[16] = \mprj_io_oeb[16] ;
+ assign \mprj_pads.oeb[15] = \mprj_io_oeb[15] ;
+ assign \mprj_pads.oeb[14] = \mprj_io_oeb[14] ;
+ assign \mprj_pads.oeb[13] = \mprj_io_oeb[13] ;
+ assign \mprj_pads.oeb[12] = \mprj_io_oeb[12] ;
+ assign \mprj_pads.oeb[11] = \mprj_io_oeb[11] ;
+ assign \mprj_pads.oeb[10] = \mprj_io_oeb[10] ;
+ assign \mprj_pads.oeb[9] = \mprj_io_oeb[9] ;
+ assign \mprj_pads.oeb[8] = \mprj_io_oeb[8] ;
+ assign \mprj_pads.oeb[7] = \mprj_io_oeb[7] ;
+ assign \mprj_pads.oeb[6] = \mprj_io_oeb[6] ;
+ assign \mprj_pads.oeb[5] = \mprj_io_oeb[5] ;
+ assign \mprj_pads.oeb[4] = \mprj_io_oeb[4] ;
+ assign \mprj_pads.oeb[3] = \mprj_io_oeb[3] ;
+ assign \mprj_pads.oeb[2] = \mprj_io_oeb[2] ;
+ assign \mprj_pads.oeb[1] = \mprj_io_oeb[1] ;
+ assign \mprj_pads.oeb[0] = \mprj_io_oeb[0] ;
+ assign \mprj_pads.analog_en[37] = \mprj_io_analog_en[37] ;
+ assign \mprj_pads.analog_en[36] = \mprj_io_analog_en[36] ;
+ assign \mprj_pads.analog_en[35] = \mprj_io_analog_en[35] ;
+ assign \mprj_pads.analog_en[34] = \mprj_io_analog_en[34] ;
+ assign \mprj_pads.analog_en[33] = \mprj_io_analog_en[33] ;
+ assign \mprj_pads.analog_en[32] = \mprj_io_analog_en[32] ;
+ assign \mprj_pads.analog_en[31] = \mprj_io_analog_en[31] ;
+ assign \mprj_pads.analog_en[30] = \mprj_io_analog_en[30] ;
+ assign \mprj_pads.analog_en[29] = \mprj_io_analog_en[29] ;
+ assign \mprj_pads.analog_en[28] = \mprj_io_analog_en[28] ;
+ assign \mprj_pads.analog_en[27] = \mprj_io_analog_en[27] ;
+ assign \mprj_pads.analog_en[26] = \mprj_io_analog_en[26] ;
+ assign \mprj_pads.analog_en[25] = \mprj_io_analog_en[25] ;
+ assign \mprj_pads.analog_en[24] = \mprj_io_analog_en[24] ;
+ assign \mprj_pads.analog_en[23] = \mprj_io_analog_en[23] ;
+ assign \mprj_pads.analog_en[22] = \mprj_io_analog_en[22] ;
+ assign \mprj_pads.analog_en[21] = \mprj_io_analog_en[21] ;
+ assign \mprj_pads.analog_en[20] = \mprj_io_analog_en[20] ;
+ assign \mprj_pads.analog_en[19] = \mprj_io_analog_en[19] ;
+ assign \mprj_pads.analog_en[18] = \mprj_io_analog_en[18] ;
+ assign \mprj_pads.analog_en[17] = \mprj_io_analog_en[17] ;
+ assign \mprj_pads.analog_en[16] = \mprj_io_analog_en[16] ;
+ assign \mprj_pads.analog_en[15] = \mprj_io_analog_en[15] ;
+ assign \mprj_pads.analog_en[14] = \mprj_io_analog_en[14] ;
+ assign \mprj_pads.analog_en[13] = \mprj_io_analog_en[13] ;
+ assign \mprj_pads.analog_en[12] = \mprj_io_analog_en[12] ;
+ assign \mprj_pads.analog_en[11] = \mprj_io_analog_en[11] ;
+ assign \mprj_pads.analog_en[10] = \mprj_io_analog_en[10] ;
+ assign \mprj_pads.analog_en[9] = \mprj_io_analog_en[9] ;
+ assign \mprj_pads.analog_en[8] = \mprj_io_analog_en[8] ;
+ assign \mprj_pads.analog_en[7] = \mprj_io_analog_en[7] ;
+ assign \mprj_pads.analog_en[6] = \mprj_io_analog_en[6] ;
+ assign \mprj_pads.analog_en[5] = \mprj_io_analog_en[5] ;
+ assign \mprj_pads.analog_en[4] = \mprj_io_analog_en[4] ;
+ assign \mprj_pads.analog_en[3] = \mprj_io_analog_en[3] ;
+ assign \mprj_pads.analog_en[2] = \mprj_io_analog_en[2] ;
+ assign \mprj_pads.analog_en[1] = \mprj_io_analog_en[1] ;
+ assign \mprj_pads.analog_en[0] = \mprj_io_analog_en[0] ;
+ assign \mprj_pads.dm[113] = \mprj_io_dm[113] ;
+ assign \mprj_pads.dm[112] = \mprj_io_dm[112] ;
+ assign \mprj_pads.dm[111] = \mprj_io_dm[111] ;
+ assign \mprj_pads.dm[110] = \mprj_io_dm[110] ;
+ assign \mprj_pads.dm[109] = \mprj_io_dm[109] ;
+ assign \mprj_pads.dm[108] = \mprj_io_dm[108] ;
+ assign \mprj_pads.dm[107] = \mprj_io_dm[107] ;
+ assign \mprj_pads.dm[106] = \mprj_io_dm[106] ;
+ assign \mprj_pads.dm[105] = \mprj_io_dm[105] ;
+ assign \mprj_pads.dm[104] = \mprj_io_dm[104] ;
+ assign \mprj_pads.dm[103] = \mprj_io_dm[103] ;
+ assign \mprj_pads.dm[102] = \mprj_io_dm[102] ;
+ assign \mprj_pads.dm[101] = \mprj_io_dm[101] ;
+ assign \mprj_pads.dm[100] = \mprj_io_dm[100] ;
+ assign \mprj_pads.dm[99] = \mprj_io_dm[99] ;
+ assign \mprj_pads.dm[98] = \mprj_io_dm[98] ;
+ assign \mprj_pads.dm[97] = \mprj_io_dm[97] ;
+ assign \mprj_pads.dm[96] = \mprj_io_dm[96] ;
+ assign \mprj_pads.dm[95] = \mprj_io_dm[95] ;
+ assign \mprj_pads.dm[94] = \mprj_io_dm[94] ;
+ assign \mprj_pads.dm[93] = \mprj_io_dm[93] ;
+ assign \mprj_pads.dm[92] = \mprj_io_dm[92] ;
+ assign \mprj_pads.dm[91] = \mprj_io_dm[91] ;
+ assign \mprj_pads.dm[90] = \mprj_io_dm[90] ;
+ assign \mprj_pads.dm[89] = \mprj_io_dm[89] ;
+ assign \mprj_pads.dm[88] = \mprj_io_dm[88] ;
+ assign \mprj_pads.dm[87] = \mprj_io_dm[87] ;
+ assign \mprj_pads.dm[86] = \mprj_io_dm[86] ;
+ assign \mprj_pads.dm[85] = \mprj_io_dm[85] ;
+ assign \mprj_pads.dm[84] = \mprj_io_dm[84] ;
+ assign \mprj_pads.dm[83] = \mprj_io_dm[83] ;
+ assign \mprj_pads.dm[82] = \mprj_io_dm[82] ;
+ assign \mprj_pads.dm[81] = \mprj_io_dm[81] ;
+ assign \mprj_pads.dm[80] = \mprj_io_dm[80] ;
+ assign \mprj_pads.dm[79] = \mprj_io_dm[79] ;
+ assign \mprj_pads.dm[78] = \mprj_io_dm[78] ;
+ assign \mprj_pads.dm[77] = \mprj_io_dm[77] ;
+ assign \mprj_pads.dm[76] = \mprj_io_dm[76] ;
+ assign \mprj_pads.dm[75] = \mprj_io_dm[75] ;
+ assign \mprj_pads.dm[74] = \mprj_io_dm[74] ;
+ assign \mprj_pads.dm[73] = \mprj_io_dm[73] ;
+ assign \mprj_pads.dm[72] = \mprj_io_dm[72] ;
+ assign \mprj_pads.dm[71] = \mprj_io_dm[71] ;
+ assign \mprj_pads.dm[70] = \mprj_io_dm[70] ;
+ assign \mprj_pads.dm[69] = \mprj_io_dm[69] ;
+ assign \mprj_pads.dm[68] = \mprj_io_dm[68] ;
+ assign \mprj_pads.dm[67] = \mprj_io_dm[67] ;
+ assign \mprj_pads.dm[66] = \mprj_io_dm[66] ;
+ assign \mprj_pads.dm[65] = \mprj_io_dm[65] ;
+ assign \mprj_pads.dm[64] = \mprj_io_dm[64] ;
+ assign \mprj_pads.dm[63] = \mprj_io_dm[63] ;
+ assign \mprj_pads.dm[62] = \mprj_io_dm[62] ;
+ assign \mprj_pads.dm[61] = \mprj_io_dm[61] ;
+ assign \mprj_pads.dm[60] = \mprj_io_dm[60] ;
+ assign \mprj_pads.dm[59] = \mprj_io_dm[59] ;
+ assign \mprj_pads.dm[58] = \mprj_io_dm[58] ;
+ assign \mprj_pads.dm[57] = \mprj_io_dm[57] ;
+ assign \mprj_pads.dm[56] = \mprj_io_dm[56] ;
+ assign \mprj_pads.dm[55] = \mprj_io_dm[55] ;
+ assign \mprj_pads.dm[54] = \mprj_io_dm[54] ;
+ assign \mprj_pads.dm[53] = \mprj_io_dm[53] ;
+ assign \mprj_pads.dm[52] = \mprj_io_dm[52] ;
+ assign \mprj_pads.dm[51] = \mprj_io_dm[51] ;
+ assign \mprj_pads.dm[50] = \mprj_io_dm[50] ;
+ assign \mprj_pads.dm[49] = \mprj_io_dm[49] ;
+ assign \mprj_pads.dm[48] = \mprj_io_dm[48] ;
+ assign \mprj_pads.dm[47] = \mprj_io_dm[47] ;
+ assign \mprj_pads.dm[46] = \mprj_io_dm[46] ;
+ assign \mprj_pads.dm[45] = \mprj_io_dm[45] ;
+ assign \mprj_pads.dm[44] = \mprj_io_dm[44] ;
+ assign \mprj_pads.dm[43] = \mprj_io_dm[43] ;
+ assign \mprj_pads.dm[42] = \mprj_io_dm[42] ;
+ assign \mprj_pads.dm[41] = \mprj_io_dm[41] ;
+ assign \mprj_pads.dm[40] = \mprj_io_dm[40] ;
+ assign \mprj_pads.dm[39] = \mprj_io_dm[39] ;
+ assign \mprj_pads.dm[38] = \mprj_io_dm[38] ;
+ assign \mprj_pads.dm[37] = \mprj_io_dm[37] ;
+ assign \mprj_pads.dm[36] = \mprj_io_dm[36] ;
+ assign \mprj_pads.dm[35] = \mprj_io_dm[35] ;
+ assign \mprj_pads.dm[34] = \mprj_io_dm[34] ;
+ assign \mprj_pads.dm[33] = \mprj_io_dm[33] ;
+ assign \mprj_pads.dm[32] = \mprj_io_dm[32] ;
+ assign \mprj_pads.dm[31] = \mprj_io_dm[31] ;
+ assign \mprj_pads.dm[30] = \mprj_io_dm[30] ;
+ assign \mprj_pads.dm[29] = \mprj_io_dm[29] ;
+ assign \mprj_pads.dm[28] = \mprj_io_dm[28] ;
+ assign \mprj_pads.dm[27] = \mprj_io_dm[27] ;
+ assign \mprj_pads.dm[26] = \mprj_io_dm[26] ;
+ assign \mprj_pads.dm[25] = \mprj_io_dm[25] ;
+ assign \mprj_pads.dm[24] = \mprj_io_dm[24] ;
+ assign \mprj_pads.dm[23] = \mprj_io_dm[23] ;
+ assign \mprj_pads.dm[22] = \mprj_io_dm[22] ;
+ assign \mprj_pads.dm[21] = \mprj_io_dm[21] ;
+ assign \mprj_pads.dm[20] = \mprj_io_dm[20] ;
+ assign \mprj_pads.dm[19] = \mprj_io_dm[19] ;
+ assign \mprj_pads.dm[18] = \mprj_io_dm[18] ;
+ assign \mprj_pads.dm[17] = \mprj_io_dm[17] ;
+ assign \mprj_pads.dm[16] = \mprj_io_dm[16] ;
+ assign \mprj_pads.dm[15] = \mprj_io_dm[15] ;
+ assign \mprj_pads.dm[14] = \mprj_io_dm[14] ;
+ assign \mprj_pads.dm[13] = \mprj_io_dm[13] ;
+ assign \mprj_pads.dm[12] = \mprj_io_dm[12] ;
+ assign \mprj_pads.dm[11] = \mprj_io_dm[11] ;
+ assign \mprj_pads.dm[10] = \mprj_io_dm[10] ;
+ assign \mprj_pads.dm[9] = \mprj_io_dm[9] ;
+ assign \mprj_pads.dm[8] = \mprj_io_dm[8] ;
+ assign \mprj_pads.dm[7] = \mprj_io_dm[7] ;
+ assign \mprj_pads.dm[6] = \mprj_io_dm[6] ;
+ assign \mprj_pads.dm[5] = \mprj_io_dm[5] ;
+ assign \mprj_pads.dm[4] = \mprj_io_dm[4] ;
+ assign \mprj_pads.dm[3] = \mprj_io_dm[3] ;
+ assign \mprj_pads.dm[2] = \mprj_io_dm[2] ;
+ assign \mprj_pads.dm[1] = \mprj_io_dm[1] ;
+ assign \mprj_pads.dm[0] = \mprj_io_dm[0] ;
+ assign \mprj_pads.inp_dis[37] = \mprj_io_inp_dis[37] ;
+ assign \mprj_pads.inp_dis[36] = \mprj_io_inp_dis[36] ;
+ assign \mprj_pads.inp_dis[35] = \mprj_io_inp_dis[35] ;
+ assign \mprj_pads.inp_dis[34] = \mprj_io_inp_dis[34] ;
+ assign \mprj_pads.inp_dis[33] = \mprj_io_inp_dis[33] ;
+ assign \mprj_pads.inp_dis[32] = \mprj_io_inp_dis[32] ;
+ assign \mprj_pads.inp_dis[31] = \mprj_io_inp_dis[31] ;
+ assign \mprj_pads.inp_dis[30] = \mprj_io_inp_dis[30] ;
+ assign \mprj_pads.inp_dis[29] = \mprj_io_inp_dis[29] ;
+ assign \mprj_pads.inp_dis[28] = \mprj_io_inp_dis[28] ;
+ assign \mprj_pads.inp_dis[27] = \mprj_io_inp_dis[27] ;
+ assign \mprj_pads.inp_dis[26] = \mprj_io_inp_dis[26] ;
+ assign \mprj_pads.inp_dis[25] = \mprj_io_inp_dis[25] ;
+ assign \mprj_pads.inp_dis[24] = \mprj_io_inp_dis[24] ;
+ assign \mprj_pads.inp_dis[23] = \mprj_io_inp_dis[23] ;
+ assign \mprj_pads.inp_dis[22] = \mprj_io_inp_dis[22] ;
+ assign \mprj_pads.inp_dis[21] = \mprj_io_inp_dis[21] ;
+ assign \mprj_pads.inp_dis[20] = \mprj_io_inp_dis[20] ;
+ assign \mprj_pads.inp_dis[19] = \mprj_io_inp_dis[19] ;
+ assign \mprj_pads.inp_dis[18] = \mprj_io_inp_dis[18] ;
+ assign \mprj_pads.inp_dis[17] = \mprj_io_inp_dis[17] ;
+ assign \mprj_pads.inp_dis[16] = \mprj_io_inp_dis[16] ;
+ assign \mprj_pads.inp_dis[15] = \mprj_io_inp_dis[15] ;
+ assign \mprj_pads.inp_dis[14] = \mprj_io_inp_dis[14] ;
+ assign \mprj_pads.inp_dis[13] = \mprj_io_inp_dis[13] ;
+ assign \mprj_pads.inp_dis[12] = \mprj_io_inp_dis[12] ;
+ assign \mprj_pads.inp_dis[11] = \mprj_io_inp_dis[11] ;
+ assign \mprj_pads.inp_dis[10] = \mprj_io_inp_dis[10] ;
+ assign \mprj_pads.inp_dis[9] = \mprj_io_inp_dis[9] ;
+ assign \mprj_pads.inp_dis[8] = \mprj_io_inp_dis[8] ;
+ assign \mprj_pads.inp_dis[7] = \mprj_io_inp_dis[7] ;
+ assign \mprj_pads.inp_dis[6] = \mprj_io_inp_dis[6] ;
+ assign \mprj_pads.inp_dis[5] = \mprj_io_inp_dis[5] ;
+ assign \mprj_pads.inp_dis[4] = \mprj_io_inp_dis[4] ;
+ assign \mprj_pads.inp_dis[3] = \mprj_io_inp_dis[3] ;
+ assign \mprj_pads.inp_dis[2] = \mprj_io_inp_dis[2] ;
+ assign \mprj_pads.inp_dis[1] = \mprj_io_inp_dis[1] ;
+ assign \mprj_pads.inp_dis[0] = \mprj_io_inp_dis[0] ;
+ assign \mprj_pads.io_out[37] = \mprj_io_out[37] ;
+ assign \mprj_pads.io_out[36] = \mprj_io_out[36] ;
+ assign \mprj_pads.io_out[35] = \mprj_io_out[35] ;
+ assign \mprj_pads.io_out[34] = \mprj_io_out[34] ;
+ assign \mprj_pads.io_out[33] = \mprj_io_out[33] ;
+ assign \mprj_pads.io_out[32] = \mprj_io_out[32] ;
+ assign \mprj_pads.io_out[31] = \mprj_io_out[31] ;
+ assign \mprj_pads.io_out[30] = \mprj_io_out[30] ;
+ assign \mprj_pads.io_out[29] = \mprj_io_out[29] ;
+ assign \mprj_pads.io_out[28] = \mprj_io_out[28] ;
+ assign \mprj_pads.io_out[27] = \mprj_io_out[27] ;
+ assign \mprj_pads.io_out[26] = \mprj_io_out[26] ;
+ assign \mprj_pads.io_out[25] = \mprj_io_out[25] ;
+ assign \mprj_pads.io_out[24] = \mprj_io_out[24] ;
+ assign \mprj_pads.io_out[23] = \mprj_io_out[23] ;
+ assign \mprj_pads.io_out[22] = \mprj_io_out[22] ;
+ assign \mprj_pads.io_out[21] = \mprj_io_out[21] ;
+ assign \mprj_pads.io_out[20] = \mprj_io_out[20] ;
+ assign \mprj_pads.io_out[19] = \mprj_io_out[19] ;
+ assign \mprj_pads.io_out[18] = \mprj_io_out[18] ;
+ assign \mprj_pads.io_out[17] = \mprj_io_out[17] ;
+ assign \mprj_pads.io_out[16] = \mprj_io_out[16] ;
+ assign \mprj_pads.io_out[15] = \mprj_io_out[15] ;
+ assign \mprj_pads.io_out[14] = \mprj_io_out[14] ;
+ assign \mprj_pads.io_out[13] = \mprj_io_out[13] ;
+ assign \mprj_pads.io_out[12] = \mprj_io_out[12] ;
+ assign \mprj_pads.io_out[11] = \mprj_io_out[11] ;
+ assign \mprj_pads.io_out[10] = \mprj_io_out[10] ;
+ assign \mprj_pads.io_out[9] = \mprj_io_out[9] ;
+ assign \mprj_pads.io_out[8] = \mprj_io_out[8] ;
+ assign \mprj_pads.io_out[7] = \mprj_io_out[7] ;
+ assign \mprj_pads.io_out[6] = \mprj_io_out[6] ;
+ assign \mprj_pads.io_out[5] = \mprj_io_out[5] ;
+ assign \mprj_pads.io_out[4] = \mprj_io_out[4] ;
+ assign \mprj_pads.io_out[3] = \mprj_io_out[3] ;
+ assign \mprj_pads.io_out[2] = \mprj_io_out[2] ;
+ assign \mprj_pads.io_out[1] = \mprj_io_out[1] ;
+ assign \mprj_pads.io_out[0] = \mprj_io_out[0] ;
+ assign \mprj_pads.holdover[37] = \mprj_io_holdover[37] ;
+ assign \mprj_pads.holdover[36] = \mprj_io_holdover[36] ;
+ assign \mprj_pads.holdover[35] = \mprj_io_holdover[35] ;
+ assign \mprj_pads.holdover[34] = \mprj_io_holdover[34] ;
+ assign \mprj_pads.holdover[33] = \mprj_io_holdover[33] ;
+ assign \mprj_pads.holdover[32] = \mprj_io_holdover[32] ;
+ assign \mprj_pads.holdover[31] = \mprj_io_holdover[31] ;
+ assign \mprj_pads.holdover[30] = \mprj_io_holdover[30] ;
+ assign \mprj_pads.holdover[29] = \mprj_io_holdover[29] ;
+ assign \mprj_pads.holdover[28] = \mprj_io_holdover[28] ;
+ assign \mprj_pads.holdover[27] = \mprj_io_holdover[27] ;
+ assign \mprj_pads.holdover[26] = \mprj_io_holdover[26] ;
+ assign \mprj_pads.holdover[25] = \mprj_io_holdover[25] ;
+ assign \mprj_pads.holdover[24] = \mprj_io_holdover[24] ;
+ assign \mprj_pads.holdover[23] = \mprj_io_holdover[23] ;
+ assign \mprj_pads.holdover[22] = \mprj_io_holdover[22] ;
+ assign \mprj_pads.holdover[21] = \mprj_io_holdover[21] ;
+ assign \mprj_pads.holdover[20] = \mprj_io_holdover[20] ;
+ assign \mprj_pads.holdover[19] = \mprj_io_holdover[19] ;
+ assign \mprj_pads.holdover[18] = \mprj_io_holdover[18] ;
+ assign \mprj_pads.holdover[17] = \mprj_io_holdover[17] ;
+ assign \mprj_pads.holdover[16] = \mprj_io_holdover[16] ;
+ assign \mprj_pads.holdover[15] = \mprj_io_holdover[15] ;
+ assign \mprj_pads.holdover[14] = \mprj_io_holdover[14] ;
+ assign \mprj_pads.holdover[13] = \mprj_io_holdover[13] ;
+ assign \mprj_pads.holdover[12] = \mprj_io_holdover[12] ;
+ assign \mprj_pads.holdover[11] = \mprj_io_holdover[11] ;
+ assign \mprj_pads.holdover[10] = \mprj_io_holdover[10] ;
+ assign \mprj_pads.holdover[9] = \mprj_io_holdover[9] ;
+ assign \mprj_pads.holdover[8] = \mprj_io_holdover[8] ;
+ assign \mprj_pads.holdover[7] = \mprj_io_holdover[7] ;
+ assign \mprj_pads.holdover[6] = \mprj_io_holdover[6] ;
+ assign \mprj_pads.holdover[5] = \mprj_io_holdover[5] ;
+ assign \mprj_pads.holdover[4] = \mprj_io_holdover[4] ;
+ assign \mprj_pads.holdover[3] = \mprj_io_holdover[3] ;
+ assign \mprj_pads.holdover[2] = \mprj_io_holdover[2] ;
+ assign \mprj_pads.holdover[1] = \mprj_io_holdover[1] ;
+ assign \mprj_pads.holdover[0] = \mprj_io_holdover[0] ;
+ assign \mprj_pads.ib_mode_sel[37] = \mprj_io_ib_mode_sel[37] ;
+ assign \mprj_pads.ib_mode_sel[36] = \mprj_io_ib_mode_sel[36] ;
+ assign \mprj_pads.ib_mode_sel[35] = \mprj_io_ib_mode_sel[35] ;
+ assign \mprj_pads.ib_mode_sel[34] = \mprj_io_ib_mode_sel[34] ;
+ assign \mprj_pads.ib_mode_sel[33] = \mprj_io_ib_mode_sel[33] ;
+ assign \mprj_pads.ib_mode_sel[32] = \mprj_io_ib_mode_sel[32] ;
+ assign \mprj_pads.ib_mode_sel[31] = \mprj_io_ib_mode_sel[31] ;
+ assign \mprj_pads.ib_mode_sel[30] = \mprj_io_ib_mode_sel[30] ;
+ assign \mprj_pads.ib_mode_sel[29] = \mprj_io_ib_mode_sel[29] ;
+ assign \mprj_pads.ib_mode_sel[28] = \mprj_io_ib_mode_sel[28] ;
+ assign \mprj_pads.ib_mode_sel[27] = \mprj_io_ib_mode_sel[27] ;
+ assign \mprj_pads.ib_mode_sel[26] = \mprj_io_ib_mode_sel[26] ;
+ assign \mprj_pads.ib_mode_sel[25] = \mprj_io_ib_mode_sel[25] ;
+ assign \mprj_pads.ib_mode_sel[24] = \mprj_io_ib_mode_sel[24] ;
+ assign \mprj_pads.ib_mode_sel[23] = \mprj_io_ib_mode_sel[23] ;
+ assign \mprj_pads.ib_mode_sel[22] = \mprj_io_ib_mode_sel[22] ;
+ assign \mprj_pads.ib_mode_sel[21] = \mprj_io_ib_mode_sel[21] ;
+ assign \mprj_pads.ib_mode_sel[20] = \mprj_io_ib_mode_sel[20] ;
+ assign \mprj_pads.ib_mode_sel[19] = \mprj_io_ib_mode_sel[19] ;
+ assign \mprj_pads.ib_mode_sel[18] = \mprj_io_ib_mode_sel[18] ;
+ assign \mprj_pads.ib_mode_sel[17] = \mprj_io_ib_mode_sel[17] ;
+ assign \mprj_pads.ib_mode_sel[16] = \mprj_io_ib_mode_sel[16] ;
+ assign \mprj_pads.ib_mode_sel[15] = \mprj_io_ib_mode_sel[15] ;
+ assign \mprj_pads.ib_mode_sel[14] = \mprj_io_ib_mode_sel[14] ;
+ assign \mprj_pads.ib_mode_sel[13] = \mprj_io_ib_mode_sel[13] ;
+ assign \mprj_pads.ib_mode_sel[12] = \mprj_io_ib_mode_sel[12] ;
+ assign \mprj_pads.ib_mode_sel[11] = \mprj_io_ib_mode_sel[11] ;
+ assign \mprj_pads.ib_mode_sel[10] = \mprj_io_ib_mode_sel[10] ;
+ assign \mprj_pads.ib_mode_sel[9] = \mprj_io_ib_mode_sel[9] ;
+ assign \mprj_pads.ib_mode_sel[8] = \mprj_io_ib_mode_sel[8] ;
+ assign \mprj_pads.ib_mode_sel[7] = \mprj_io_ib_mode_sel[7] ;
+ assign \mprj_pads.ib_mode_sel[6] = \mprj_io_ib_mode_sel[6] ;
+ assign \mprj_pads.ib_mode_sel[5] = \mprj_io_ib_mode_sel[5] ;
+ assign \mprj_pads.ib_mode_sel[4] = \mprj_io_ib_mode_sel[4] ;
+ assign \mprj_pads.ib_mode_sel[3] = \mprj_io_ib_mode_sel[3] ;
+ assign \mprj_pads.ib_mode_sel[2] = \mprj_io_ib_mode_sel[2] ;
+ assign \mprj_pads.ib_mode_sel[1] = \mprj_io_ib_mode_sel[1] ;
+ assign \mprj_pads.ib_mode_sel[0] = \mprj_io_ib_mode_sel[0] ;
+ assign \mprj_pads.vddio = vddio;
+ assign \mprj_pads.vssio = vssio;
+ assign \mprj_pads.vccd = vccd;
+ assign \mprj_pads.vssd = vssd;
+ assign \mprj_pads.vdda1 = vdda1;
+ assign \mprj_pads.vdda2 = vdda2;
+ assign \mprj_pads.vssa1 = vssa1;
+ assign \mprj_pads.vssa2 = vssa2;
+ assign \mprj_pads.vccd1 = vccd1;
+ assign \mprj_pads.vccd2 = vccd2;
+ assign \mprj_pads.vssd1 = vssd1;
+ assign \mprj_pads.vssd2 = vssd2;
+ assign \mprj_pads.porb_h = porb_h;
+ assign \mprj_pads.slow_sel[36] = \mprj_io_slow_sel[36] ;
+ assign \mprj_pads.slow_sel[23] = \mprj_io_slow_sel[23] ;
+ assign \mprj_pads.slow_sel[28] = \mprj_io_slow_sel[28] ;
+ assign \mprj_pads.slow_sel[37] = \mprj_io_slow_sel[37] ;
+ assign \flash_io0_mode[0] = flash_io0_oeb_core;
+ assign \mprj_pads.slow_sel[24] = \mprj_io_slow_sel[24] ;
+ assign \mprj_pads.slow_sel[21] = \mprj_io_slow_sel[21] ;
+ assign \mprj_pads.slow_sel[31] = \mprj_io_slow_sel[31] ;
+ assign \flash_io0_mode[1] = flash_io0_ieb_core;
+ assign \mprj_pads.slow_sel[22] = \mprj_io_slow_sel[22] ;
+ assign \mprj_pads.slow_sel[27] = \mprj_io_slow_sel[27] ;
+ assign \mprj_pads.slow_sel[32] = \mprj_io_slow_sel[32] ;
+ assign \mprj_pads.slow_sel[30] = \mprj_io_slow_sel[30] ;
+ assign \mprj_pads.slow_sel[26] = \mprj_io_slow_sel[26] ;
+ assign \mprj_pads.slow_sel[29] = \mprj_io_slow_sel[29] ;
+ assign \mprj_pads.slow_sel[35] = \mprj_io_slow_sel[35] ;
+ assign \mprj_pads.slow_sel[25] = \mprj_io_slow_sel[25] ;
+ assign \mprj_pads.slow_sel[20] = \mprj_io_slow_sel[20] ;
+ assign \mprj_pads.slow_sel[34] = \mprj_io_slow_sel[34] ;
+ assign \flash_io0_mode[2] = flash_io0_ieb_core;
+ assign \mprj_pads.slow_sel[33] = \mprj_io_slow_sel[33] ;
+ assign vssio_q = \mprj_pads.vssio_q ;
+ assign vddio_q = \mprj_pads.vddio_q ;
+ assign analog_b = \mprj_pads.analog_b ;
+ assign analog_a = \mprj_pads.analog_a ;
+ assign { \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0] } =
+ { \mprj_pads.io_in[37] , \mprj_pads.io_in[36] , \mprj_pads.io_in[35] , \mprj_pads.io_in[34] , \mprj_pads.io_in[33] , \mprj_pads.io_in[32] , \mprj_pads.io_in[31] , \mprj_pads.io_in[30] , \mprj_pads.io_in[29] , \mprj_pads.io_in[28] , \mprj_pads.io_in[27] , \mprj_pads.io_in[26] , \mprj_pads.io_in[25] , \mprj_pads.io_in[24] , \mprj_pads.io_in[23] , \mprj_pads.io_in[22] , \mprj_pads.io_in[21] , \mprj_pads.io_in[20] , \mprj_pads.io_in[19] , \mprj_pads.io_in[18] , \mprj_pads.io_in[17] , \mprj_pads.io_in[16] , \mprj_pads.io_in[15] , \mprj_pads.io_in[14] , \mprj_pads.io_in[13] , \mprj_pads.io_in[12] , \mprj_pads.io_in[11] , \mprj_pads.io_in[10] , \mprj_pads.io_in[9] , \mprj_pads.io_in[8] , \mprj_pads.io_in[7] , \mprj_pads.io_in[6] , \mprj_pads.io_in[5] , \mprj_pads.io_in[4] , \mprj_pads.io_in[3] , \mprj_pads.io_in[2] , \mprj_pads.io_in[1] , \mprj_pads.io_in[0] };
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v b/caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v
new file mode 100644
index 0000000..400c5ab
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v
@@ -0,0 +1,377 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
+
+`include "defines.v"
+
+`ifdef GL
+ `include "gl/chip_io.v"
+`else
+ `ifdef SPLIT_BUS
+ `include "ports.v"
+ `include "chip_io_split.v"
+ `else
+ `include "pads.v"
+ `include "mprj_io.v"
+ `include "chip_io.v"
+ `endif
+`endif
+
+module chip_io_tb;
+
+ wire clock_core;
+ reg clock;
+
+ wire rstb_h;
+ reg RSTB;
+
+ reg porb_h;
+ wire por_l;
+
+ wire gpio;
+ reg gpio_out_core;
+ reg gpio_inenb_core;
+ reg gpio_outenb_core;
+
+ wire flash_csb;
+ reg flash_csb_core;
+ reg flash_csb_ieb_core;
+ reg flash_csb_oeb_core;
+
+ wire flash_clk;
+ reg flash_clk_core;
+ reg flash_clk_ieb_core;
+ reg flash_clk_oeb_core;
+
+ wire flash_io0;
+ wire flash_io0_di_core;
+ reg flash_io0_do_core;
+ reg flash_io0_ieb_core;
+ reg flash_io0_oeb_core;
+
+ wire flash_io1;
+ wire flash_io1_di_core;
+ reg flash_io1_do_core;
+ reg flash_io1_ieb_core;
+ reg flash_io1_oeb_core;
+
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+
+ wire [`MPRJ_IO_PADS-1:0] mprj_io;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ reg [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-10:0] mprj_analog_io;
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ porb_h = 0;
+ flash_csb_core = 0;
+ flash_csb_ieb_core = 1;
+ flash_csb_oeb_core = 0;
+ flash_clk_ieb_core = 1;
+ flash_clk_oeb_core = 0;
+ mprj_io_ib_mode_sel = {38{1'b0}};
+ mprj_io_vtrip_sel = {38{1'b0}};
+ mprj_io_slow_sel = {38{1'b0}};
+ mprj_io_holdover = {38{1'b0}};
+ mprj_io_analog_en = {38{1'b0}};
+ mprj_io_analog_sel = {38{1'b0}};
+ mprj_io_analog_pol = {38{1'b0}};
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ reg power1, power2;
+
+ initial begin
+ RSTB <= 1'b0;
+ porb_h <= 1'b0;
+ #500;
+ porb_h <= 1'b1;
+ #500;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ initial begin
+ $dumpfile("chip_io.vcd");
+ $dumpvars(0, chip_io_tb);
+ #(`SIM_TIME);
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Management Protect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [2:0] dm_all;
+ reg gpio_bit;
+
+ assign gpio = gpio_bit;
+ assign gpio_mode0_core = dm_all[0];
+ assign gpio_mode1_core = dm_all[1];
+
+ reg flash_io0_bit;
+ reg flash_io1_bit;
+
+ assign flash_io0 = flash_io0_bit;
+ assign flash_io1 = flash_io1_bit;
+
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_bits;
+
+ assign mprj_io = mprj_io_bits;
+
+ initial begin
+ wait(RSTB == 1'b1); // wait for reset
+ #25;
+ // Clock & Reset Pads
+ if (clock !== clock_core) begin
+ $display("Error: Clock Pad Test Failed."); $finish;
+ end
+ if (RSTB !== rstb_h) begin
+ $display("Error: Reset Pad Test Failed."); $finish;
+ end
+
+ // Management GPIO Pad
+ gpio_bit = 1'b1;
+ gpio_out_core = 1'b0;
+ gpio_inenb_core = 1'b0;
+ gpio_outenb_core = 1'b1;
+ dm_all = 3'b001; // input-only
+ #25;
+ if (gpio_in_core !== gpio) begin
+ $display("Error: GPIO Pad Input Test Failed."); $finish;
+ end
+
+ gpio_bit = 1'bz;
+ gpio_out_core = 1'b1;
+ gpio_inenb_core = 1'b1;
+ gpio_outenb_core = 1'b0;
+ dm_all = 3'b110; // output-only
+ #25;
+ if (gpio_out_core !== gpio) begin
+ $display("Error: GPIO Pad Output Test Failed."); $finish;
+ end
+
+ // Flash Output Pads
+ flash_csb_core = 1'b1; // CSB Pad
+ #25;
+ if (flash_csb !== flash_csb_core) begin
+ $display("Error: Flash CSB Pad Test Failed."); $finish;
+ end
+
+ flash_clk_core = 1'b1; // CLK Pad
+ #25;
+ if (flash_clk !== flash_clk_core) begin
+ $display("Error: Flash CLK Pad Test Failed."); $finish;
+ end
+
+ // Flash Inout Pads
+ flash_io0_bit = 1'b1;
+ flash_io0_ieb_core = 1'b0; // Input
+ flash_io0_oeb_core = 1'b1;
+ #25;
+ if (flash_io0_di_core !== flash_io0_bit) begin
+ $display("Error: Flash io0 Pad Input Test Failed."); $finish;
+ end
+
+ flash_io0_bit = 1'bz;
+ flash_io0_do_core = 1'b1;
+ flash_io0_ieb_core = 1'b1;
+ flash_io0_oeb_core = 1'b0; // Output
+ #25
+ if (flash_io0 !== flash_io0_do_core) begin
+ $display("Error: Flash io0 Pad Output Test Failed."); $finish;
+ end
+
+ // User Project Pads - All Outputs
+ mprj_io_bits = {38{1'bz}};
+ mprj_io_out = {6'b10101, 32'hF0F0};
+ mprj_io_oeb = {38{1'b0}};
+ mprj_io_inp_dis = {38{1'b1}};
+ mprj_io_dm = {38*3{3'b110}};
+
+ #25;
+ if (mprj_io !== mprj_io_out) begin
+ $display("Error: User Project Pads Output Test Failed."); $finish;
+ end
+
+ // User Project Pads - All Inputs
+ mprj_io_bits = {6'b01010, 32'hFF0F};
+ mprj_io_out = {38{1'b0}};
+ mprj_io_oeb = {38{1'b1}};
+ mprj_io_inp_dis = {38{1'b0}};
+ mprj_io_dm = {38*3{3'b001}};
+
+ #25;
+ if (mprj_io_in !== mprj_io_bits) begin
+ $display("Error: User Project Pads Input Test Failed."); $finish;
+ end
+
+ // User Project Pads - All Bidirectional
+ mprj_io_bits = {6'b01010, 32'hF00F}; // drive input signal
+ mprj_io_out = {38{1'bz}};
+ mprj_io_oeb = {38{1'b1}};
+ mprj_io_inp_dis = {38{1'b0}};
+ mprj_io_dm = {38{3'b110}};
+
+ #25;
+ if (mprj_io_in !== mprj_io_bits) begin
+ $display("Error: User Project Pads Bidirectional Test Failed."); $finish;
+ end
+
+ mprj_io_bits = {38{1'bz}};
+ mprj_io_out = {6'b01110, 32'h0FF0}; // drive output signal
+ mprj_io_oeb = {38{1'b0}};
+ mprj_io_inp_dis = {38{1'b0}};
+ mprj_io_dm = {38{3'b110}};
+
+ #25;
+ if (mprj_io !== mprj_io_out) begin
+ $display("Error: User Project Pads Output Test Failed."); $finish;
+ end
+ $display("Success");
+ $display("Monitor: Chip IO Test Passed.");
+ #2000;
+ $finish;
+ end
+
+ assign por_l = ~porb_h;
+
+ chip_io uut (
+ // Package Pins
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+
+ .gpio(gpio),
+ .clock(clock),
+ .resetb(RSTB),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_core),
+ .flash_clk_core(flash_clk_core),
+ .flash_csb_oeb_core(flash_csb_oeb_core),
+ .flash_clk_oeb_core(flash_clk_oeb_core),
+ .flash_io0_oeb_core(flash_io0_oeb_core),
+ .flash_io1_oeb_core(flash_io1_oeb_core),
+ .flash_csb_ieb_core(flash_csb_ieb_core),
+ .flash_clk_ieb_core(flash_clk_ieb_core),
+ .flash_io0_ieb_core(flash_io0_ieb_core),
+ .flash_io1_ieb_core(flash_io1_ieb_core),
+ .flash_io0_do_core(flash_io0_do_core),
+ .flash_io1_do_core(flash_io1_do_core),
+ .flash_io0_di_core(flash_io0_di_core),
+ .flash_io1_di_core(flash_io1_di_core),
+ `ifdef SPLIT_BUS
+ `MPRJ_IO,
+ `MPRJ_IO_IN,
+ `MPRJ_IO_OUT,
+ `MPRJ_IO_OEB,
+ `MPRJ_IO_INP_DIS,
+ `MPRJ_IO_IB_MODE_SEL,
+ `MPRJ_IO_VTRIP_SEL,
+ `MPRJ_IO_SLOW_SEL,
+ `MPRJ_IO_HOLDOVER,
+ `MPRJ_IO_ANALOG_EN,
+ `MPRJ_IO_ANALOG_SEL,
+ `MPRJ_IO_ANALOG_POL,
+ `MPRJ_IO_DM,
+ `MPRJ_IO_ANALOG
+ `else
+ .mprj_io(mprj_io),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(mprj_analog_io)
+`endif
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/chip_io/ports.v b/caravel/verilog/dv/wb_utests/chip_io/ports.v
new file mode 100644
index 0000000..6516802
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/ports.v
@@ -0,0 +1,727 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`define MPRJ_IO \
+.\mprj_io[0] (mprj_io[0]),\
+.\mprj_io[1] (mprj_io[1]),\
+.\mprj_io[2] (mprj_io[2]),\
+.\mprj_io[3] (mprj_io[3]),\
+.\mprj_io[4] (mprj_io[4]),\
+.\mprj_io[5] (mprj_io[5]),\
+.\mprj_io[6] (mprj_io[6]),\
+.\mprj_io[7] (mprj_io[7]),\
+.\mprj_io[8] (mprj_io[8]),\
+.\mprj_io[9] (mprj_io[9]),\
+.\mprj_io[10] (mprj_io[10]),\
+.\mprj_io[11] (mprj_io[11]),\
+.\mprj_io[12] (mprj_io[12]),\
+.\mprj_io[13] (mprj_io[13]),\
+.\mprj_io[14] (mprj_io[14]),\
+.\mprj_io[15] (mprj_io[15]),\
+.\mprj_io[16] (mprj_io[16]),\
+.\mprj_io[17] (mprj_io[17]),\
+.\mprj_io[18] (mprj_io[18]),\
+.\mprj_io[19] (mprj_io[19]),\
+.\mprj_io[20] (mprj_io[20]),\
+.\mprj_io[21] (mprj_io[21]),\
+.\mprj_io[22] (mprj_io[22]),\
+.\mprj_io[23] (mprj_io[23]),\
+.\mprj_io[24] (mprj_io[24]),\
+.\mprj_io[25] (mprj_io[25]),\
+.\mprj_io[26] (mprj_io[26]),\
+.\mprj_io[27] (mprj_io[27]),\
+.\mprj_io[28] (mprj_io[28]),\
+.\mprj_io[29] (mprj_io[29]),\
+.\mprj_io[30] (mprj_io[30]),\
+.\mprj_io[31] (mprj_io[31]),\
+.\mprj_io[32] (mprj_io[32]),\
+.\mprj_io[33] (mprj_io[33]),\
+.\mprj_io[34] (mprj_io[34]),\
+.\mprj_io[35] (mprj_io[35]),\
+.\mprj_io[36] (mprj_io[36]),\
+.\mprj_io[37] (mprj_io[37])
+
+`define MPRJ_IO_IN \
+.\mprj_io_in[0] (mprj_io_in[0]),\
+.\mprj_io_in[1] (mprj_io_in[1]),\
+.\mprj_io_in[2] (mprj_io_in[2]),\
+.\mprj_io_in[3] (mprj_io_in[3]),\
+.\mprj_io_in[4] (mprj_io_in[4]),\
+.\mprj_io_in[5] (mprj_io_in[5]),\
+.\mprj_io_in[6] (mprj_io_in[6]),\
+.\mprj_io_in[7] (mprj_io_in[7]),\
+.\mprj_io_in[8] (mprj_io_in[8]),\
+.\mprj_io_in[9] (mprj_io_in[9]),\
+.\mprj_io_in[10] (mprj_io_in[10]),\
+.\mprj_io_in[11] (mprj_io_in[11]),\
+.\mprj_io_in[12] (mprj_io_in[12]),\
+.\mprj_io_in[13] (mprj_io_in[13]),\
+.\mprj_io_in[14] (mprj_io_in[14]),\
+.\mprj_io_in[15] (mprj_io_in[15]),\
+.\mprj_io_in[16] (mprj_io_in[16]),\
+.\mprj_io_in[17] (mprj_io_in[17]),\
+.\mprj_io_in[18] (mprj_io_in[18]),\
+.\mprj_io_in[19] (mprj_io_in[19]),\
+.\mprj_io_in[20] (mprj_io_in[20]),\
+.\mprj_io_in[21] (mprj_io_in[21]),\
+.\mprj_io_in[22] (mprj_io_in[22]),\
+.\mprj_io_in[23] (mprj_io_in[23]),\
+.\mprj_io_in[24] (mprj_io_in[24]),\
+.\mprj_io_in[25] (mprj_io_in[25]),\
+.\mprj_io_in[26] (mprj_io_in[26]),\
+.\mprj_io_in[27] (mprj_io_in[27]),\
+.\mprj_io_in[28] (mprj_io_in[28]),\
+.\mprj_io_in[29] (mprj_io_in[29]),\
+.\mprj_io_in[30] (mprj_io_in[30]),\
+.\mprj_io_in[31] (mprj_io_in[31]),\
+.\mprj_io_in[32] (mprj_io_in[32]),\
+.\mprj_io_in[33] (mprj_io_in[33]),\
+.\mprj_io_in[34] (mprj_io_in[34]),\
+.\mprj_io_in[35] (mprj_io_in[35]),\
+.\mprj_io_in[36] (mprj_io_in[36]),\
+.\mprj_io_in[37] (mprj_io_in[37])
+
+
+`define MPRJ_IO_OUT \
+.\mprj_io_out[0] (mprj_io_out[0]),\
+.\mprj_io_out[1] (mprj_io_out[1]),\
+.\mprj_io_out[2] (mprj_io_out[2]),\
+.\mprj_io_out[3] (mprj_io_out[3]),\
+.\mprj_io_out[4] (mprj_io_out[4]),\
+.\mprj_io_out[5] (mprj_io_out[5]),\
+.\mprj_io_out[6] (mprj_io_out[6]),\
+.\mprj_io_out[7] (mprj_io_out[7]),\
+.\mprj_io_out[8] (mprj_io_out[8]),\
+.\mprj_io_out[9] (mprj_io_out[9]),\
+.\mprj_io_out[10] (mprj_io_out[10]),\
+.\mprj_io_out[11] (mprj_io_out[11]),\
+.\mprj_io_out[12] (mprj_io_out[12]),\
+.\mprj_io_out[13] (mprj_io_out[13]),\
+.\mprj_io_out[14] (mprj_io_out[14]),\
+.\mprj_io_out[15] (mprj_io_out[15]),\
+.\mprj_io_out[16] (mprj_io_out[16]),\
+.\mprj_io_out[17] (mprj_io_out[17]),\
+.\mprj_io_out[18] (mprj_io_out[18]),\
+.\mprj_io_out[19] (mprj_io_out[19]),\
+.\mprj_io_out[20] (mprj_io_out[20]),\
+.\mprj_io_out[21] (mprj_io_out[21]),\
+.\mprj_io_out[22] (mprj_io_out[22]),\
+.\mprj_io_out[23] (mprj_io_out[23]),\
+.\mprj_io_out[24] (mprj_io_out[24]),\
+.\mprj_io_out[25] (mprj_io_out[25]),\
+.\mprj_io_out[26] (mprj_io_out[26]),\
+.\mprj_io_out[27] (mprj_io_out[27]),\
+.\mprj_io_out[28] (mprj_io_out[28]),\
+.\mprj_io_out[29] (mprj_io_out[29]),\
+.\mprj_io_out[30] (mprj_io_out[30]),\
+.\mprj_io_out[31] (mprj_io_out[31]),\
+.\mprj_io_out[32] (mprj_io_out[32]),\
+.\mprj_io_out[33] (mprj_io_out[33]),\
+.\mprj_io_out[34] (mprj_io_out[34]),\
+.\mprj_io_out[35] (mprj_io_out[35]),\
+.\mprj_io_out[36] (mprj_io_out[36]),\
+.\mprj_io_out[37] (mprj_io_out[37])
+
+`define MPRJ_IO_OEB \
+.\mprj_io_oeb[0] (mprj_io_oeb[0]),\
+.\mprj_io_oeb[1] (mprj_io_oeb[1]),\
+.\mprj_io_oeb[2] (mprj_io_oeb[2]),\
+.\mprj_io_oeb[3] (mprj_io_oeb[3]),\
+.\mprj_io_oeb[4] (mprj_io_oeb[4]),\
+.\mprj_io_oeb[5] (mprj_io_oeb[5]),\
+.\mprj_io_oeb[6] (mprj_io_oeb[6]),\
+.\mprj_io_oeb[7] (mprj_io_oeb[7]),\
+.\mprj_io_oeb[8] (mprj_io_oeb[8]),\
+.\mprj_io_oeb[9] (mprj_io_oeb[9]),\
+.\mprj_io_oeb[10] (mprj_io_oeb[10]),\
+.\mprj_io_oeb[11] (mprj_io_oeb[11]),\
+.\mprj_io_oeb[12] (mprj_io_oeb[12]),\
+.\mprj_io_oeb[13] (mprj_io_oeb[13]),\
+.\mprj_io_oeb[14] (mprj_io_oeb[14]),\
+.\mprj_io_oeb[15] (mprj_io_oeb[15]),\
+.\mprj_io_oeb[16] (mprj_io_oeb[16]),\
+.\mprj_io_oeb[17] (mprj_io_oeb[17]),\
+.\mprj_io_oeb[18] (mprj_io_oeb[18]),\
+.\mprj_io_oeb[19] (mprj_io_oeb[19]),\
+.\mprj_io_oeb[20] (mprj_io_oeb[20]),\
+.\mprj_io_oeb[21] (mprj_io_oeb[21]),\
+.\mprj_io_oeb[22] (mprj_io_oeb[22]),\
+.\mprj_io_oeb[23] (mprj_io_oeb[23]),\
+.\mprj_io_oeb[24] (mprj_io_oeb[24]),\
+.\mprj_io_oeb[25] (mprj_io_oeb[25]),\
+.\mprj_io_oeb[26] (mprj_io_oeb[26]),\
+.\mprj_io_oeb[27] (mprj_io_oeb[27]),\
+.\mprj_io_oeb[28] (mprj_io_oeb[28]),\
+.\mprj_io_oeb[29] (mprj_io_oeb[29]),\
+.\mprj_io_oeb[30] (mprj_io_oeb[30]),\
+.\mprj_io_oeb[31] (mprj_io_oeb[31]),\
+.\mprj_io_oeb[32] (mprj_io_oeb[32]),\
+.\mprj_io_oeb[33] (mprj_io_oeb[33]),\
+.\mprj_io_oeb[34] (mprj_io_oeb[34]),\
+.\mprj_io_oeb[35] (mprj_io_oeb[35]),\
+.\mprj_io_oeb[36] (mprj_io_oeb[36]),\
+.\mprj_io_oeb[37] (mprj_io_oeb[37])
+
+`define MPRJ_IO_HLDH_N \
+.\mprj_io_hldh_n[0] (mprj_io_hldh_n[0]),\
+.\mprj_io_hldh_n[1] (mprj_io_hldh_n[1]),\
+.\mprj_io_hldh_n[2] (mprj_io_hldh_n[2]),\
+.\mprj_io_hldh_n[3] (mprj_io_hldh_n[3]),\
+.\mprj_io_hldh_n[4] (mprj_io_hldh_n[4]),\
+.\mprj_io_hldh_n[5] (mprj_io_hldh_n[5]),\
+.\mprj_io_hldh_n[6] (mprj_io_hldh_n[6]),\
+.\mprj_io_hldh_n[7] (mprj_io_hldh_n[7]),\
+.\mprj_io_hldh_n[8] (mprj_io_hldh_n[8]),\
+.\mprj_io_hldh_n[9] (mprj_io_hldh_n[9]),\
+.\mprj_io_hldh_n[10] (mprj_io_hldh_n[10]),\
+.\mprj_io_hldh_n[11] (mprj_io_hldh_n[11]),\
+.\mprj_io_hldh_n[12] (mprj_io_hldh_n[12]),\
+.\mprj_io_hldh_n[13] (mprj_io_hldh_n[13]),\
+.\mprj_io_hldh_n[14] (mprj_io_hldh_n[14]),\
+.\mprj_io_hldh_n[15] (mprj_io_hldh_n[15]),\
+.\mprj_io_hldh_n[16] (mprj_io_hldh_n[16]),\
+.\mprj_io_hldh_n[17] (mprj_io_hldh_n[17]),\
+.\mprj_io_hldh_n[18] (mprj_io_hldh_n[18]),\
+.\mprj_io_hldh_n[19] (mprj_io_hldh_n[19]),\
+.\mprj_io_hldh_n[20] (mprj_io_hldh_n[20]),\
+.\mprj_io_hldh_n[21] (mprj_io_hldh_n[21]),\
+.\mprj_io_hldh_n[22] (mprj_io_hldh_n[22]),\
+.\mprj_io_hldh_n[23] (mprj_io_hldh_n[23]),\
+.\mprj_io_hldh_n[24] (mprj_io_hldh_n[24]),\
+.\mprj_io_hldh_n[25] (mprj_io_hldh_n[25]),\
+.\mprj_io_hldh_n[26] (mprj_io_hldh_n[26]),\
+.\mprj_io_hldh_n[27] (mprj_io_hldh_n[27]),\
+.\mprj_io_hldh_n[28] (mprj_io_hldh_n[28]),\
+.\mprj_io_hldh_n[29] (mprj_io_hldh_n[29]),\
+.\mprj_io_hldh_n[30] (mprj_io_hldh_n[30]),\
+.\mprj_io_hldh_n[31] (mprj_io_hldh_n[31]),\
+.\mprj_io_hldh_n[32] (mprj_io_hldh_n[32]),\
+.\mprj_io_hldh_n[33] (mprj_io_hldh_n[33]),\
+.\mprj_io_hldh_n[34] (mprj_io_hldh_n[34]),\
+.\mprj_io_hldh_n[35] (mprj_io_hldh_n[35]),\
+.\mprj_io_hldh_n[36] (mprj_io_hldh_n[36]),\
+.\mprj_io_hldh_n[37] (mprj_io_hldh_n[37])
+
+`define MPRJ_IO_ENH \
+.\mprj_io_enh[0] (mprj_io_enh[0]),\
+.\mprj_io_enh[1] (mprj_io_enh[1]),\
+.\mprj_io_enh[2] (mprj_io_enh[2]),\
+.\mprj_io_enh[3] (mprj_io_enh[3]),\
+.\mprj_io_enh[4] (mprj_io_enh[4]),\
+.\mprj_io_enh[5] (mprj_io_enh[5]),\
+.\mprj_io_enh[6] (mprj_io_enh[6]),\
+.\mprj_io_enh[7] (mprj_io_enh[7]),\
+.\mprj_io_enh[8] (mprj_io_enh[8]),\
+.\mprj_io_enh[9] (mprj_io_enh[9]),\
+.\mprj_io_enh[10] (mprj_io_enh[10]),\
+.\mprj_io_enh[11] (mprj_io_enh[11]),\
+.\mprj_io_enh[12] (mprj_io_enh[12]),\
+.\mprj_io_enh[13] (mprj_io_enh[13]),\
+.\mprj_io_enh[14] (mprj_io_enh[14]),\
+.\mprj_io_enh[15] (mprj_io_enh[15]),\
+.\mprj_io_enh[16] (mprj_io_enh[16]),\
+.\mprj_io_enh[17] (mprj_io_enh[17]),\
+.\mprj_io_enh[18] (mprj_io_enh[18]),\
+.\mprj_io_enh[19] (mprj_io_enh[19]),\
+.\mprj_io_enh[20] (mprj_io_enh[20]),\
+.\mprj_io_enh[21] (mprj_io_enh[21]),\
+.\mprj_io_enh[22] (mprj_io_enh[22]),\
+.\mprj_io_enh[23] (mprj_io_enh[23]),\
+.\mprj_io_enh[24] (mprj_io_enh[24]),\
+.\mprj_io_enh[25] (mprj_io_enh[25]),\
+.\mprj_io_enh[26] (mprj_io_enh[26]),\
+.\mprj_io_enh[27] (mprj_io_enh[27]),\
+.\mprj_io_enh[28] (mprj_io_enh[28]),\
+.\mprj_io_enh[29] (mprj_io_enh[29]),\
+.\mprj_io_enh[30] (mprj_io_enh[30]),\
+.\mprj_io_enh[31] (mprj_io_enh[31]),\
+.\mprj_io_enh[32] (mprj_io_enh[32]),\
+.\mprj_io_enh[33] (mprj_io_enh[33]),\
+.\mprj_io_enh[34] (mprj_io_enh[34]),\
+.\mprj_io_enh[35] (mprj_io_enh[35]),\
+.\mprj_io_enh[36] (mprj_io_enh[36]),\
+.\mprj_io_enh[37] (mprj_io_enh[37])
+
+`define MPRJ_IO_INP_DIS \
+.\mprj_io_inp_dis[0] (mprj_io_inp_dis[0]),\
+.\mprj_io_inp_dis[1] (mprj_io_inp_dis[1]),\
+.\mprj_io_inp_dis[2] (mprj_io_inp_dis[2]),\
+.\mprj_io_inp_dis[3] (mprj_io_inp_dis[3]),\
+.\mprj_io_inp_dis[4] (mprj_io_inp_dis[4]),\
+.\mprj_io_inp_dis[5] (mprj_io_inp_dis[5]),\
+.\mprj_io_inp_dis[6] (mprj_io_inp_dis[6]),\
+.\mprj_io_inp_dis[7] (mprj_io_inp_dis[7]),\
+.\mprj_io_inp_dis[8] (mprj_io_inp_dis[8]),\
+.\mprj_io_inp_dis[9] (mprj_io_inp_dis[9]),\
+.\mprj_io_inp_dis[10] (mprj_io_inp_dis[10]),\
+.\mprj_io_inp_dis[11] (mprj_io_inp_dis[11]),\
+.\mprj_io_inp_dis[12] (mprj_io_inp_dis[12]),\
+.\mprj_io_inp_dis[13] (mprj_io_inp_dis[13]),\
+.\mprj_io_inp_dis[14] (mprj_io_inp_dis[14]),\
+.\mprj_io_inp_dis[15] (mprj_io_inp_dis[15]),\
+.\mprj_io_inp_dis[16] (mprj_io_inp_dis[16]),\
+.\mprj_io_inp_dis[17] (mprj_io_inp_dis[17]),\
+.\mprj_io_inp_dis[18] (mprj_io_inp_dis[18]),\
+.\mprj_io_inp_dis[19] (mprj_io_inp_dis[19]),\
+.\mprj_io_inp_dis[20] (mprj_io_inp_dis[20]),\
+.\mprj_io_inp_dis[21] (mprj_io_inp_dis[21]),\
+.\mprj_io_inp_dis[22] (mprj_io_inp_dis[22]),\
+.\mprj_io_inp_dis[23] (mprj_io_inp_dis[23]),\
+.\mprj_io_inp_dis[24] (mprj_io_inp_dis[24]),\
+.\mprj_io_inp_dis[25] (mprj_io_inp_dis[25]),\
+.\mprj_io_inp_dis[26] (mprj_io_inp_dis[26]),\
+.\mprj_io_inp_dis[27] (mprj_io_inp_dis[27]),\
+.\mprj_io_inp_dis[28] (mprj_io_inp_dis[28]),\
+.\mprj_io_inp_dis[29] (mprj_io_inp_dis[29]),\
+.\mprj_io_inp_dis[30] (mprj_io_inp_dis[30]),\
+.\mprj_io_inp_dis[31] (mprj_io_inp_dis[31]),\
+.\mprj_io_inp_dis[32] (mprj_io_inp_dis[32]),\
+.\mprj_io_inp_dis[33] (mprj_io_inp_dis[33]),\
+.\mprj_io_inp_dis[34] (mprj_io_inp_dis[34]),\
+.\mprj_io_inp_dis[35] (mprj_io_inp_dis[35]),\
+.\mprj_io_inp_dis[36] (mprj_io_inp_dis[36]),\
+.\mprj_io_inp_dis[37] (mprj_io_inp_dis[37])
+
+`define MPRJ_IO_IB_MODE_SEL \
+.\mprj_io_ib_mode_sel[0] (mprj_io_ib_mode_sel[0]),\
+.\mprj_io_ib_mode_sel[1] (mprj_io_ib_mode_sel[1]),\
+.\mprj_io_ib_mode_sel[2] (mprj_io_ib_mode_sel[2]),\
+.\mprj_io_ib_mode_sel[3] (mprj_io_ib_mode_sel[3]),\
+.\mprj_io_ib_mode_sel[4] (mprj_io_ib_mode_sel[4]),\
+.\mprj_io_ib_mode_sel[5] (mprj_io_ib_mode_sel[5]),\
+.\mprj_io_ib_mode_sel[6] (mprj_io_ib_mode_sel[6]),\
+.\mprj_io_ib_mode_sel[7] (mprj_io_ib_mode_sel[7]),\
+.\mprj_io_ib_mode_sel[8] (mprj_io_ib_mode_sel[8]),\
+.\mprj_io_ib_mode_sel[9] (mprj_io_ib_mode_sel[9]),\
+.\mprj_io_ib_mode_sel[10] (mprj_io_ib_mode_sel[10]),\
+.\mprj_io_ib_mode_sel[11] (mprj_io_ib_mode_sel[11]),\
+.\mprj_io_ib_mode_sel[12] (mprj_io_ib_mode_sel[12]),\
+.\mprj_io_ib_mode_sel[13] (mprj_io_ib_mode_sel[13]),\
+.\mprj_io_ib_mode_sel[14] (mprj_io_ib_mode_sel[14]),\
+.\mprj_io_ib_mode_sel[15] (mprj_io_ib_mode_sel[15]),\
+.\mprj_io_ib_mode_sel[16] (mprj_io_ib_mode_sel[16]),\
+.\mprj_io_ib_mode_sel[17] (mprj_io_ib_mode_sel[17]),\
+.\mprj_io_ib_mode_sel[18] (mprj_io_ib_mode_sel[18]),\
+.\mprj_io_ib_mode_sel[19] (mprj_io_ib_mode_sel[19]),\
+.\mprj_io_ib_mode_sel[20] (mprj_io_ib_mode_sel[20]),\
+.\mprj_io_ib_mode_sel[21] (mprj_io_ib_mode_sel[21]),\
+.\mprj_io_ib_mode_sel[22] (mprj_io_ib_mode_sel[22]),\
+.\mprj_io_ib_mode_sel[23] (mprj_io_ib_mode_sel[23]),\
+.\mprj_io_ib_mode_sel[24] (mprj_io_ib_mode_sel[24]),\
+.\mprj_io_ib_mode_sel[25] (mprj_io_ib_mode_sel[25]),\
+.\mprj_io_ib_mode_sel[26] (mprj_io_ib_mode_sel[26]),\
+.\mprj_io_ib_mode_sel[27] (mprj_io_ib_mode_sel[27]),\
+.\mprj_io_ib_mode_sel[28] (mprj_io_ib_mode_sel[28]),\
+.\mprj_io_ib_mode_sel[29] (mprj_io_ib_mode_sel[29]),\
+.\mprj_io_ib_mode_sel[30] (mprj_io_ib_mode_sel[30]),\
+.\mprj_io_ib_mode_sel[31] (mprj_io_ib_mode_sel[31]),\
+.\mprj_io_ib_mode_sel[32] (mprj_io_ib_mode_sel[32]),\
+.\mprj_io_ib_mode_sel[33] (mprj_io_ib_mode_sel[33]),\
+.\mprj_io_ib_mode_sel[34] (mprj_io_ib_mode_sel[34]),\
+.\mprj_io_ib_mode_sel[35] (mprj_io_ib_mode_sel[35]),\
+.\mprj_io_ib_mode_sel[36] (mprj_io_ib_mode_sel[36]),\
+.\mprj_io_ib_mode_sel[37] (mprj_io_ib_mode_sel[37])
+
+`define MPRJ_IO_VTRIP_SEL \
+.\mprj_io_vtrip_sel[0] (mprj_io_vtrip_sel[0]),\
+.\mprj_io_vtrip_sel[1] (mprj_io_vtrip_sel[1]),\
+.\mprj_io_vtrip_sel[2] (mprj_io_vtrip_sel[2]),\
+.\mprj_io_vtrip_sel[3] (mprj_io_vtrip_sel[3]),\
+.\mprj_io_vtrip_sel[4] (mprj_io_vtrip_sel[4]),\
+.\mprj_io_vtrip_sel[5] (mprj_io_vtrip_sel[5]),\
+.\mprj_io_vtrip_sel[6] (mprj_io_vtrip_sel[6]),\
+.\mprj_io_vtrip_sel[7] (mprj_io_vtrip_sel[7]),\
+.\mprj_io_vtrip_sel[8] (mprj_io_vtrip_sel[8]),\
+.\mprj_io_vtrip_sel[9] (mprj_io_vtrip_sel[9]),\
+.\mprj_io_vtrip_sel[10] (mprj_io_vtrip_sel[10]),\
+.\mprj_io_vtrip_sel[11] (mprj_io_vtrip_sel[11]),\
+.\mprj_io_vtrip_sel[12] (mprj_io_vtrip_sel[12]),\
+.\mprj_io_vtrip_sel[13] (mprj_io_vtrip_sel[13]),\
+.\mprj_io_vtrip_sel[14] (mprj_io_vtrip_sel[14]),\
+.\mprj_io_vtrip_sel[15] (mprj_io_vtrip_sel[15]),\
+.\mprj_io_vtrip_sel[16] (mprj_io_vtrip_sel[16]),\
+.\mprj_io_vtrip_sel[17] (mprj_io_vtrip_sel[17]),\
+.\mprj_io_vtrip_sel[18] (mprj_io_vtrip_sel[18]),\
+.\mprj_io_vtrip_sel[19] (mprj_io_vtrip_sel[19]),\
+.\mprj_io_vtrip_sel[20] (mprj_io_vtrip_sel[20]),\
+.\mprj_io_vtrip_sel[21] (mprj_io_vtrip_sel[21]),\
+.\mprj_io_vtrip_sel[22] (mprj_io_vtrip_sel[22]),\
+.\mprj_io_vtrip_sel[23] (mprj_io_vtrip_sel[23]),\
+.\mprj_io_vtrip_sel[24] (mprj_io_vtrip_sel[24]),\
+.\mprj_io_vtrip_sel[25] (mprj_io_vtrip_sel[25]),\
+.\mprj_io_vtrip_sel[26] (mprj_io_vtrip_sel[26]),\
+.\mprj_io_vtrip_sel[27] (mprj_io_vtrip_sel[27]),\
+.\mprj_io_vtrip_sel[28] (mprj_io_vtrip_sel[28]),\
+.\mprj_io_vtrip_sel[29] (mprj_io_vtrip_sel[29]),\
+.\mprj_io_vtrip_sel[30] (mprj_io_vtrip_sel[30]),\
+.\mprj_io_vtrip_sel[31] (mprj_io_vtrip_sel[31]),\
+.\mprj_io_vtrip_sel[32] (mprj_io_vtrip_sel[32]),\
+.\mprj_io_vtrip_sel[33] (mprj_io_vtrip_sel[33]),\
+.\mprj_io_vtrip_sel[34] (mprj_io_vtrip_sel[34]),\
+.\mprj_io_vtrip_sel[35] (mprj_io_vtrip_sel[35]),\
+.\mprj_io_vtrip_sel[36] (mprj_io_vtrip_sel[36]),\
+.\mprj_io_vtrip_sel[37] (mprj_io_vtrip_sel[37])
+
+
+`define MPRJ_IO_SLOW_SEL \
+.\mprj_io_slow_sel[0] (mprj_io_slow_sel[0]),\
+.\mprj_io_slow_sel[1] (mprj_io_slow_sel[1]),\
+.\mprj_io_slow_sel[2] (mprj_io_slow_sel[2]),\
+.\mprj_io_slow_sel[3] (mprj_io_slow_sel[3]),\
+.\mprj_io_slow_sel[4] (mprj_io_slow_sel[4]),\
+.\mprj_io_slow_sel[5] (mprj_io_slow_sel[5]),\
+.\mprj_io_slow_sel[6] (mprj_io_slow_sel[6]),\
+.\mprj_io_slow_sel[7] (mprj_io_slow_sel[7]),\
+.\mprj_io_slow_sel[8] (mprj_io_slow_sel[8]),\
+.\mprj_io_slow_sel[9] (mprj_io_slow_sel[9]),\
+.\mprj_io_slow_sel[10] (mprj_io_slow_sel[10]),\
+.\mprj_io_slow_sel[11] (mprj_io_slow_sel[11]),\
+.\mprj_io_slow_sel[12] (mprj_io_slow_sel[12]),\
+.\mprj_io_slow_sel[13] (mprj_io_slow_sel[13]),\
+.\mprj_io_slow_sel[14] (mprj_io_slow_sel[14]),\
+.\mprj_io_slow_sel[15] (mprj_io_slow_sel[15]),\
+.\mprj_io_slow_sel[16] (mprj_io_slow_sel[16]),\
+.\mprj_io_slow_sel[17] (mprj_io_slow_sel[17]),\
+.\mprj_io_slow_sel[18] (mprj_io_slow_sel[18]),\
+.\mprj_io_slow_sel[19] (mprj_io_slow_sel[19]),\
+.\mprj_io_slow_sel[20] (mprj_io_slow_sel[20]),\
+.\mprj_io_slow_sel[21] (mprj_io_slow_sel[21]),\
+.\mprj_io_slow_sel[22] (mprj_io_slow_sel[22]),\
+.\mprj_io_slow_sel[23] (mprj_io_slow_sel[23]),\
+.\mprj_io_slow_sel[24] (mprj_io_slow_sel[24]),\
+.\mprj_io_slow_sel[25] (mprj_io_slow_sel[25]),\
+.\mprj_io_slow_sel[26] (mprj_io_slow_sel[26]),\
+.\mprj_io_slow_sel[27] (mprj_io_slow_sel[27]),\
+.\mprj_io_slow_sel[28] (mprj_io_slow_sel[28]),\
+.\mprj_io_slow_sel[29] (mprj_io_slow_sel[29]),\
+.\mprj_io_slow_sel[30] (mprj_io_slow_sel[30]),\
+.\mprj_io_slow_sel[31] (mprj_io_slow_sel[31]),\
+.\mprj_io_slow_sel[32] (mprj_io_slow_sel[32]),\
+.\mprj_io_slow_sel[33] (mprj_io_slow_sel[33]),\
+.\mprj_io_slow_sel[34] (mprj_io_slow_sel[34]),\
+.\mprj_io_slow_sel[35] (mprj_io_slow_sel[35]),\
+.\mprj_io_slow_sel[36] (mprj_io_slow_sel[36]),\
+.\mprj_io_slow_sel[37] (mprj_io_slow_sel[37])
+
+
+`define MPRJ_IO_HOLDOVER \
+.\mprj_io_holdover[0] (mprj_io_holdover[0]),\
+.\mprj_io_holdover[1] (mprj_io_holdover[1]),\
+.\mprj_io_holdover[2] (mprj_io_holdover[2]),\
+.\mprj_io_holdover[3] (mprj_io_holdover[3]),\
+.\mprj_io_holdover[4] (mprj_io_holdover[4]),\
+.\mprj_io_holdover[5] (mprj_io_holdover[5]),\
+.\mprj_io_holdover[6] (mprj_io_holdover[6]),\
+.\mprj_io_holdover[7] (mprj_io_holdover[7]),\
+.\mprj_io_holdover[8] (mprj_io_holdover[8]),\
+.\mprj_io_holdover[9] (mprj_io_holdover[9]),\
+.\mprj_io_holdover[10] (mprj_io_holdover[10]),\
+.\mprj_io_holdover[11] (mprj_io_holdover[11]),\
+.\mprj_io_holdover[12] (mprj_io_holdover[12]),\
+.\mprj_io_holdover[13] (mprj_io_holdover[13]),\
+.\mprj_io_holdover[14] (mprj_io_holdover[14]),\
+.\mprj_io_holdover[15] (mprj_io_holdover[15]),\
+.\mprj_io_holdover[16] (mprj_io_holdover[16]),\
+.\mprj_io_holdover[17] (mprj_io_holdover[17]),\
+.\mprj_io_holdover[18] (mprj_io_holdover[18]),\
+.\mprj_io_holdover[19] (mprj_io_holdover[19]),\
+.\mprj_io_holdover[20] (mprj_io_holdover[20]),\
+.\mprj_io_holdover[21] (mprj_io_holdover[21]),\
+.\mprj_io_holdover[22] (mprj_io_holdover[22]),\
+.\mprj_io_holdover[23] (mprj_io_holdover[23]),\
+.\mprj_io_holdover[24] (mprj_io_holdover[24]),\
+.\mprj_io_holdover[25] (mprj_io_holdover[25]),\
+.\mprj_io_holdover[26] (mprj_io_holdover[26]),\
+.\mprj_io_holdover[27] (mprj_io_holdover[27]),\
+.\mprj_io_holdover[28] (mprj_io_holdover[28]),\
+.\mprj_io_holdover[29] (mprj_io_holdover[29]),\
+.\mprj_io_holdover[30] (mprj_io_holdover[30]),\
+.\mprj_io_holdover[31] (mprj_io_holdover[31]),\
+.\mprj_io_holdover[32] (mprj_io_holdover[32]),\
+.\mprj_io_holdover[33] (mprj_io_holdover[33]),\
+.\mprj_io_holdover[34] (mprj_io_holdover[34]),\
+.\mprj_io_holdover[35] (mprj_io_holdover[35]),\
+.\mprj_io_holdover[36] (mprj_io_holdover[36]),\
+.\mprj_io_holdover[37] (mprj_io_holdover[37])
+
+`define MPRJ_IO_ANALOG_EN \
+.\mprj_io_analog_en[0] (mprj_io_analog_en[0]),\
+.\mprj_io_analog_en[1] (mprj_io_analog_en[1]),\
+.\mprj_io_analog_en[2] (mprj_io_analog_en[2]),\
+.\mprj_io_analog_en[3] (mprj_io_analog_en[3]),\
+.\mprj_io_analog_en[4] (mprj_io_analog_en[4]),\
+.\mprj_io_analog_en[5] (mprj_io_analog_en[5]),\
+.\mprj_io_analog_en[6] (mprj_io_analog_en[6]),\
+.\mprj_io_analog_en[7] (mprj_io_analog_en[7]),\
+.\mprj_io_analog_en[8] (mprj_io_analog_en[8]),\
+.\mprj_io_analog_en[9] (mprj_io_analog_en[9]),\
+.\mprj_io_analog_en[10] (mprj_io_analog_en[10]),\
+.\mprj_io_analog_en[11] (mprj_io_analog_en[11]),\
+.\mprj_io_analog_en[12] (mprj_io_analog_en[12]),\
+.\mprj_io_analog_en[13] (mprj_io_analog_en[13]),\
+.\mprj_io_analog_en[14] (mprj_io_analog_en[14]),\
+.\mprj_io_analog_en[15] (mprj_io_analog_en[15]),\
+.\mprj_io_analog_en[16] (mprj_io_analog_en[16]),\
+.\mprj_io_analog_en[17] (mprj_io_analog_en[17]),\
+.\mprj_io_analog_en[18] (mprj_io_analog_en[18]),\
+.\mprj_io_analog_en[19] (mprj_io_analog_en[19]),\
+.\mprj_io_analog_en[20] (mprj_io_analog_en[20]),\
+.\mprj_io_analog_en[21] (mprj_io_analog_en[21]),\
+.\mprj_io_analog_en[22] (mprj_io_analog_en[22]),\
+.\mprj_io_analog_en[23] (mprj_io_analog_en[23]),\
+.\mprj_io_analog_en[24] (mprj_io_analog_en[24]),\
+.\mprj_io_analog_en[25] (mprj_io_analog_en[25]),\
+.\mprj_io_analog_en[26] (mprj_io_analog_en[26]),\
+.\mprj_io_analog_en[27] (mprj_io_analog_en[27]),\
+.\mprj_io_analog_en[28] (mprj_io_analog_en[28]),\
+.\mprj_io_analog_en[29] (mprj_io_analog_en[29]),\
+.\mprj_io_analog_en[30] (mprj_io_analog_en[30]),\
+.\mprj_io_analog_en[31] (mprj_io_analog_en[31]),\
+.\mprj_io_analog_en[32] (mprj_io_analog_en[32]),\
+.\mprj_io_analog_en[33] (mprj_io_analog_en[33]),\
+.\mprj_io_analog_en[34] (mprj_io_analog_en[34]),\
+.\mprj_io_analog_en[35] (mprj_io_analog_en[35]),\
+.\mprj_io_analog_en[36] (mprj_io_analog_en[36]),\
+.\mprj_io_analog_en[37] (mprj_io_analog_en[37])
+
+`define MPRJ_IO_ANALOG_SEL \
+.\mprj_io_analog_sel[0] (mprj_io_analog_sel[0]),\
+.\mprj_io_analog_sel[1] (mprj_io_analog_sel[1]),\
+.\mprj_io_analog_sel[2] (mprj_io_analog_sel[2]),\
+.\mprj_io_analog_sel[3] (mprj_io_analog_sel[3]),\
+.\mprj_io_analog_sel[4] (mprj_io_analog_sel[4]),\
+.\mprj_io_analog_sel[5] (mprj_io_analog_sel[5]),\
+.\mprj_io_analog_sel[6] (mprj_io_analog_sel[6]),\
+.\mprj_io_analog_sel[7] (mprj_io_analog_sel[7]),\
+.\mprj_io_analog_sel[8] (mprj_io_analog_sel[8]),\
+.\mprj_io_analog_sel[9] (mprj_io_analog_sel[9]),\
+.\mprj_io_analog_sel[10] (mprj_io_analog_sel[10]),\
+.\mprj_io_analog_sel[11] (mprj_io_analog_sel[11]),\
+.\mprj_io_analog_sel[12] (mprj_io_analog_sel[12]),\
+.\mprj_io_analog_sel[13] (mprj_io_analog_sel[13]),\
+.\mprj_io_analog_sel[14] (mprj_io_analog_sel[14]),\
+.\mprj_io_analog_sel[15] (mprj_io_analog_sel[15]),\
+.\mprj_io_analog_sel[16] (mprj_io_analog_sel[16]),\
+.\mprj_io_analog_sel[17] (mprj_io_analog_sel[17]),\
+.\mprj_io_analog_sel[18] (mprj_io_analog_sel[18]),\
+.\mprj_io_analog_sel[19] (mprj_io_analog_sel[19]),\
+.\mprj_io_analog_sel[20] (mprj_io_analog_sel[20]),\
+.\mprj_io_analog_sel[21] (mprj_io_analog_sel[21]),\
+.\mprj_io_analog_sel[22] (mprj_io_analog_sel[22]),\
+.\mprj_io_analog_sel[23] (mprj_io_analog_sel[23]),\
+.\mprj_io_analog_sel[24] (mprj_io_analog_sel[24]),\
+.\mprj_io_analog_sel[25] (mprj_io_analog_sel[25]),\
+.\mprj_io_analog_sel[26] (mprj_io_analog_sel[26]),\
+.\mprj_io_analog_sel[27] (mprj_io_analog_sel[27]),\
+.\mprj_io_analog_sel[28] (mprj_io_analog_sel[28]),\
+.\mprj_io_analog_sel[29] (mprj_io_analog_sel[29]),\
+.\mprj_io_analog_sel[30] (mprj_io_analog_sel[30]),\
+.\mprj_io_analog_sel[31] (mprj_io_analog_sel[31]),\
+.\mprj_io_analog_sel[32] (mprj_io_analog_sel[32]),\
+.\mprj_io_analog_sel[33] (mprj_io_analog_sel[33]),\
+.\mprj_io_analog_sel[34] (mprj_io_analog_sel[34]),\
+.\mprj_io_analog_sel[35] (mprj_io_analog_sel[35]),\
+.\mprj_io_analog_sel[36] (mprj_io_analog_sel[36]),\
+.\mprj_io_analog_sel[37] (mprj_io_analog_sel[37])
+
+
+`define MPRJ_IO_ANALOG_POL \
+.\mprj_io_analog_pol[0] (mprj_io_analog_pol[0]),\
+.\mprj_io_analog_pol[1] (mprj_io_analog_pol[1]),\
+.\mprj_io_analog_pol[2] (mprj_io_analog_pol[2]),\
+.\mprj_io_analog_pol[3] (mprj_io_analog_pol[3]),\
+.\mprj_io_analog_pol[4] (mprj_io_analog_pol[4]),\
+.\mprj_io_analog_pol[5] (mprj_io_analog_pol[5]),\
+.\mprj_io_analog_pol[6] (mprj_io_analog_pol[6]),\
+.\mprj_io_analog_pol[7] (mprj_io_analog_pol[7]),\
+.\mprj_io_analog_pol[8] (mprj_io_analog_pol[8]),\
+.\mprj_io_analog_pol[9] (mprj_io_analog_pol[9]),\
+.\mprj_io_analog_pol[10] (mprj_io_analog_pol[10]),\
+.\mprj_io_analog_pol[11] (mprj_io_analog_pol[11]),\
+.\mprj_io_analog_pol[12] (mprj_io_analog_pol[12]),\
+.\mprj_io_analog_pol[13] (mprj_io_analog_pol[13]),\
+.\mprj_io_analog_pol[14] (mprj_io_analog_pol[14]),\
+.\mprj_io_analog_pol[15] (mprj_io_analog_pol[15]),\
+.\mprj_io_analog_pol[16] (mprj_io_analog_pol[16]),\
+.\mprj_io_analog_pol[17] (mprj_io_analog_pol[17]),\
+.\mprj_io_analog_pol[18] (mprj_io_analog_pol[18]),\
+.\mprj_io_analog_pol[19] (mprj_io_analog_pol[19]),\
+.\mprj_io_analog_pol[20] (mprj_io_analog_pol[20]),\
+.\mprj_io_analog_pol[21] (mprj_io_analog_pol[21]),\
+.\mprj_io_analog_pol[22] (mprj_io_analog_pol[22]),\
+.\mprj_io_analog_pol[23] (mprj_io_analog_pol[23]),\
+.\mprj_io_analog_pol[24] (mprj_io_analog_pol[24]),\
+.\mprj_io_analog_pol[25] (mprj_io_analog_pol[25]),\
+.\mprj_io_analog_pol[26] (mprj_io_analog_pol[26]),\
+.\mprj_io_analog_pol[27] (mprj_io_analog_pol[27]),\
+.\mprj_io_analog_pol[28] (mprj_io_analog_pol[28]),\
+.\mprj_io_analog_pol[29] (mprj_io_analog_pol[29]),\
+.\mprj_io_analog_pol[30] (mprj_io_analog_pol[30]),\
+.\mprj_io_analog_pol[31] (mprj_io_analog_pol[31]),\
+.\mprj_io_analog_pol[32] (mprj_io_analog_pol[32]),\
+.\mprj_io_analog_pol[33] (mprj_io_analog_pol[33]),\
+.\mprj_io_analog_pol[34] (mprj_io_analog_pol[34]),\
+.\mprj_io_analog_pol[35] (mprj_io_analog_pol[35]),\
+.\mprj_io_analog_pol[36] (mprj_io_analog_pol[36]),\
+.\mprj_io_analog_pol[37] (mprj_io_analog_pol[37])
+
+`define MPRJ_IO_DM \
+.\mprj_io_dm[0] (mprj_io_dm[0]),\
+.\mprj_io_dm[1] (mprj_io_dm[1]),\
+.\mprj_io_dm[2] (mprj_io_dm[2]),\
+.\mprj_io_dm[3] (mprj_io_dm[3]),\
+.\mprj_io_dm[4] (mprj_io_dm[4]),\
+.\mprj_io_dm[5] (mprj_io_dm[5]),\
+.\mprj_io_dm[6] (mprj_io_dm[6]),\
+.\mprj_io_dm[7] (mprj_io_dm[7]),\
+.\mprj_io_dm[8] (mprj_io_dm[8]),\
+.\mprj_io_dm[9] (mprj_io_dm[9]),\
+.\mprj_io_dm[10] (mprj_io_dm[10]),\
+.\mprj_io_dm[11] (mprj_io_dm[11]),\
+.\mprj_io_dm[12] (mprj_io_dm[12]),\
+.\mprj_io_dm[13] (mprj_io_dm[13]),\
+.\mprj_io_dm[14] (mprj_io_dm[14]),\
+.\mprj_io_dm[15] (mprj_io_dm[15]),\
+.\mprj_io_dm[16] (mprj_io_dm[16]),\
+.\mprj_io_dm[17] (mprj_io_dm[17]),\
+.\mprj_io_dm[18] (mprj_io_dm[18]),\
+.\mprj_io_dm[19] (mprj_io_dm[19]),\
+.\mprj_io_dm[20] (mprj_io_dm[20]),\
+.\mprj_io_dm[21] (mprj_io_dm[21]),\
+.\mprj_io_dm[22] (mprj_io_dm[22]),\
+.\mprj_io_dm[23] (mprj_io_dm[23]),\
+.\mprj_io_dm[24] (mprj_io_dm[24]),\
+.\mprj_io_dm[25] (mprj_io_dm[25]),\
+.\mprj_io_dm[26] (mprj_io_dm[26]),\
+.\mprj_io_dm[27] (mprj_io_dm[27]),\
+.\mprj_io_dm[28] (mprj_io_dm[28]),\
+.\mprj_io_dm[29] (mprj_io_dm[29]),\
+.\mprj_io_dm[30] (mprj_io_dm[30]),\
+.\mprj_io_dm[31] (mprj_io_dm[31]),\
+.\mprj_io_dm[32] (mprj_io_dm[32]),\
+.\mprj_io_dm[33] (mprj_io_dm[33]),\
+.\mprj_io_dm[34] (mprj_io_dm[34]),\
+.\mprj_io_dm[35] (mprj_io_dm[35]),\
+.\mprj_io_dm[36] (mprj_io_dm[36]),\
+.\mprj_io_dm[37] (mprj_io_dm[37]),\
+.\mprj_io_dm[38] (mprj_io_dm[38]),\
+.\mprj_io_dm[39] (mprj_io_dm[39]),\
+.\mprj_io_dm[40] (mprj_io_dm[40]),\
+.\mprj_io_dm[41] (mprj_io_dm[41]),\
+.\mprj_io_dm[42] (mprj_io_dm[42]),\
+.\mprj_io_dm[43] (mprj_io_dm[43]),\
+.\mprj_io_dm[44] (mprj_io_dm[44]),\
+.\mprj_io_dm[45] (mprj_io_dm[45]),\
+.\mprj_io_dm[46] (mprj_io_dm[46]),\
+.\mprj_io_dm[47] (mprj_io_dm[47]),\
+.\mprj_io_dm[48] (mprj_io_dm[48]),\
+.\mprj_io_dm[49] (mprj_io_dm[49]),\
+.\mprj_io_dm[50] (mprj_io_dm[50]),\
+.\mprj_io_dm[51] (mprj_io_dm[51]),\
+.\mprj_io_dm[52] (mprj_io_dm[52]),\
+.\mprj_io_dm[53] (mprj_io_dm[53]),\
+.\mprj_io_dm[54] (mprj_io_dm[54]),\
+.\mprj_io_dm[55] (mprj_io_dm[55]),\
+.\mprj_io_dm[56] (mprj_io_dm[56]),\
+.\mprj_io_dm[57] (mprj_io_dm[57]),\
+.\mprj_io_dm[58] (mprj_io_dm[58]),\
+.\mprj_io_dm[59] (mprj_io_dm[59]),\
+.\mprj_io_dm[60] (mprj_io_dm[60]),\
+.\mprj_io_dm[61] (mprj_io_dm[61]),\
+.\mprj_io_dm[62] (mprj_io_dm[62]),\
+.\mprj_io_dm[63] (mprj_io_dm[63]),\
+.\mprj_io_dm[64] (mprj_io_dm[64]),\
+.\mprj_io_dm[65] (mprj_io_dm[65]),\
+.\mprj_io_dm[66] (mprj_io_dm[66]),\
+.\mprj_io_dm[67] (mprj_io_dm[67]),\
+.\mprj_io_dm[68] (mprj_io_dm[68]),\
+.\mprj_io_dm[69] (mprj_io_dm[69]),\
+.\mprj_io_dm[70] (mprj_io_dm[70]),\
+.\mprj_io_dm[71] (mprj_io_dm[71]),\
+.\mprj_io_dm[72] (mprj_io_dm[72]),\
+.\mprj_io_dm[73] (mprj_io_dm[73]),\
+.\mprj_io_dm[74] (mprj_io_dm[74]),\
+.\mprj_io_dm[75] (mprj_io_dm[75]),\
+.\mprj_io_dm[76] (mprj_io_dm[76]),\
+.\mprj_io_dm[77] (mprj_io_dm[77]),\
+.\mprj_io_dm[78] (mprj_io_dm[78]),\
+.\mprj_io_dm[79] (mprj_io_dm[79]),\
+.\mprj_io_dm[80] (mprj_io_dm[80]),\
+.\mprj_io_dm[81] (mprj_io_dm[81]),\
+.\mprj_io_dm[82] (mprj_io_dm[82]),\
+.\mprj_io_dm[83] (mprj_io_dm[83]),\
+.\mprj_io_dm[84] (mprj_io_dm[84]),\
+.\mprj_io_dm[85] (mprj_io_dm[85]),\
+.\mprj_io_dm[86] (mprj_io_dm[86]),\
+.\mprj_io_dm[87] (mprj_io_dm[87]),\
+.\mprj_io_dm[88] (mprj_io_dm[88]),\
+.\mprj_io_dm[89] (mprj_io_dm[89]),\
+.\mprj_io_dm[90] (mprj_io_dm[90]),\
+.\mprj_io_dm[91] (mprj_io_dm[91]),\
+.\mprj_io_dm[92] (mprj_io_dm[92]),\
+.\mprj_io_dm[93] (mprj_io_dm[93]),\
+.\mprj_io_dm[94] (mprj_io_dm[94]),\
+.\mprj_io_dm[95] (mprj_io_dm[95]),\
+.\mprj_io_dm[96] (mprj_io_dm[96]),\
+.\mprj_io_dm[97] (mprj_io_dm[97]),\
+.\mprj_io_dm[98] (mprj_io_dm[98]),\
+.\mprj_io_dm[99] (mprj_io_dm[99]),\
+.\mprj_io_dm[100] (mprj_io_dm[100]),\
+.\mprj_io_dm[101] (mprj_io_dm[101]),\
+.\mprj_io_dm[102] (mprj_io_dm[102]),\
+.\mprj_io_dm[103] (mprj_io_dm[103]),\
+.\mprj_io_dm[104] (mprj_io_dm[104]),\
+.\mprj_io_dm[105] (mprj_io_dm[105]),\
+.\mprj_io_dm[106] (mprj_io_dm[106]),\
+.\mprj_io_dm[107] (mprj_io_dm[107]),\
+.\mprj_io_dm[108] (mprj_io_dm[108]),\
+.\mprj_io_dm[109] (mprj_io_dm[109]),\
+.\mprj_io_dm[110] (mprj_io_dm[110]),\
+.\mprj_io_dm[111] (mprj_io_dm[111]),\
+.\mprj_io_dm[112] (mprj_io_dm[112]),\
+.\mprj_io_dm[113] (mprj_io_dm[113])
+
+`define MPRJ_IO_ANALOG \
+.\mprj_analog_io[0] (mprj_analog_io[0]),\
+.\mprj_analog_io[1] (mprj_analog_io[1]),\
+.\mprj_analog_io[2] (mprj_analog_io[2]),\
+.\mprj_analog_io[3] (mprj_analog_io[3]),\
+.\mprj_analog_io[4] (mprj_analog_io[4]),\
+.\mprj_analog_io[5] (mprj_analog_io[5]),\
+.\mprj_analog_io[6] (mprj_analog_io[6]),\
+.\mprj_analog_io[7] (mprj_analog_io[7]),\
+.\mprj_analog_io[8] (mprj_analog_io[8]),\
+.\mprj_analog_io[9] (mprj_analog_io[9]),\
+.\mprj_analog_io[10] (mprj_analog_io[10]),\
+.\mprj_analog_io[11] (mprj_analog_io[11]),\
+.\mprj_analog_io[12] (mprj_analog_io[12]),\
+.\mprj_analog_io[13] (mprj_analog_io[13]),\
+.\mprj_analog_io[14] (mprj_analog_io[14]),\
+.\mprj_analog_io[15] (mprj_analog_io[15]),\
+.\mprj_analog_io[16] (mprj_analog_io[16]),\
+.\mprj_analog_io[17] (mprj_analog_io[17]),\
+.\mprj_analog_io[18] (mprj_analog_io[18]),\
+.\mprj_analog_io[19] (mprj_analog_io[19]),\
+.\mprj_analog_io[20] (mprj_analog_io[20]),\
+.\mprj_analog_io[21] (mprj_analog_io[21]),\
+.\mprj_analog_io[22] (mprj_analog_io[22]),\
+.\mprj_analog_io[23] (mprj_analog_io[23]),\
+.\mprj_analog_io[24] (mprj_analog_io[24]),\
+.\mprj_analog_io[25] (mprj_analog_io[25]),\
+.\mprj_analog_io[26] (mprj_analog_io[26]),\
+.\mprj_analog_io[27] (mprj_analog_io[27]),\
+.\mprj_analog_io[28] (mprj_analog_io[28]),\
+.\mprj_analog_io[29] (mprj_analog_io[29]),\
+.\mprj_analog_io[30] (mprj_analog_io[30])
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/gpio_wb/Makefile b/caravel/verilog/dv/wb_utests/gpio_wb/Makefile
new file mode 100644
index 0000000..a42f609
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/gpio_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = gpio_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/caravel/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
new file mode 100644
index 0000000..ea6c772
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -0,0 +1,199 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "gpio_wb.v"
+
+module gpio_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+ reg gpio_in_pad;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ gpio_in_pad = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("gpio_wb_tb.vcd");
+ $dumpvars(0, gpio_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test GPIO Wishbone Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // GPIO Internal Register Addresses
+ wire [31:0] gpio_adr = uut.BASE_ADR | uut.GPIO_DATA;
+ wire [31:0] gpio_oeb_adr = uut.BASE_ADR | uut.GPIO_ENA;
+ wire [31:0] gpio_pu_adr = uut.BASE_ADR | uut.GPIO_PU;
+ wire [31:0] gpio_pd_adr = uut.BASE_ADR | uut.GPIO_PD;
+
+ reg gpio_data;
+ reg gpio_pu;
+ reg gpio_pd;
+ reg gpio_oeb;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Write to gpio_data reg
+ gpio_in_pad = 1'b1;
+ gpio_data = 1'b1;
+ write(gpio_adr, gpio_data);
+
+ #2;
+ // Read from gpio_data reg
+ read(gpio_adr);
+ if (wb_dat_o !== {30'd0, gpio_data, gpio_in_pad}) begin
+ $display("Monitor: Error reading from gpio reg");
+ $finish;
+ end
+
+ #2;
+ // Write to pull-up reg
+ gpio_pu = 1'b1;
+ write(gpio_pu_adr, gpio_pu);
+
+ #2;
+ // Read from pull-up reg
+ read(gpio_pu_adr);
+ if (wb_dat_o !== {31'd0, gpio_pu}) begin
+ $display("Monitor: Error reading from gpio pull-up reg");
+ $finish;
+ end
+
+ #2;
+ // Write to pull-down reg
+ gpio_pd = 1'b1;
+ write(gpio_pd_adr, gpio_pd);
+
+ #2;
+ // Read from pull-down reg
+ read(gpio_pd_adr);
+ if (wb_dat_o !== {31'd0, gpio_pd}) begin
+ $display("Monitor: Error reading from gpio pull-down reg");
+ $finish;
+ end
+
+ #2;
+ // Write to gpio enable reg
+ gpio_oeb = 1'b1;
+ write(gpio_oeb_adr, gpio_oeb);
+
+ #2;
+ // Read from gpio enable reg
+ read(gpio_oeb_adr);
+ if (wb_dat_o !== {31'd0, gpio_oeb}) begin
+ $display("Monitor: Error reading from gpio output enable reg");
+ $finish;
+ end
+
+ #6;
+ $display("Monitor: GPIO WB Success!");
+ $display("Monitor: GPIO WB Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ gpio_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o),
+ .gpio_in_pad(gpio_in_pad)
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/intercon_wb/Makefile b/caravel/verilog/dv/wb_utests/intercon_wb/Makefile
new file mode 100644
index 0000000..294cf17
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/intercon_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = intercon_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../ -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/caravel/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
new file mode 100644
index 0000000..4f6fd38
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -0,0 +1,204 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "wb_intercon.v"
+`include "dummy_slave.v"
+
+`define AW 32
+`define DW 32
+`define NS 6
+
+`define SLAVE_ADR { \
+ {8'h28, {24{1'b0}} }, \
+ {8'h23, {24{1'b0}} }, \
+ {8'h21, {24{1'b0}} }, \
+ {8'h20, {24{1'b0}} }, \
+ {8'h10, {24{1'b0}} }, \
+ {8'h00, {24{1'b0}} } \
+}\
+
+`define ADR_MASK { \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} }, \
+ {8'hFF, {24{1'b0}} } \
+}\
+
+module intercon_wb_tb;
+
+ localparam SEL = `DW / 8;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ // Master Interface
+ reg wbm_stb_i;
+ reg wbm_cyc_i;
+ reg wbm_we_i;
+ reg [SEL-1:0] wbm_sel_i;
+ reg [`AW-1:0] wbm_adr_i;
+ reg [`DW-1:0] wbm_dat_i;
+
+ wire [`DW-1:0] wbm_dat_o;
+ wire wbm_ack_o;
+
+ // Wishbone Slave Interface
+ wire [`NS-1:0] wbs_stb_i;
+ wire [`NS-1:0] wbs_ack_o;
+ wire [(`NS*`DW)-1:0] wbs_adr_i;
+ wire [(`NS*`AW)-1:0] wbs_dat_i;
+ wire [(`NS*`DW)-1:0] wbs_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wbm_adr_i = 0;
+ wbm_dat_i = 0;
+ wbm_sel_i = 0;
+ wbm_we_i = 0;
+ wbm_cyc_i = 0;
+ wbm_stb_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("intercon_wb_tb.vcd");
+ $dumpvars(0, intercon_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Wishbone Interconnect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [`AW*`NS-1: 0] addr = `SLAVE_ADR;
+ reg [`DW:0] slave_data;
+ reg [`AW:0] slave_addr;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // W/R from all slaves
+ for (i=0; i<`NS; i=i+1) begin
+ slave_addr = addr[i*`AW +: `AW];
+ slave_data = $urandom_range(0, 2**32);
+ write(slave_addr, slave_data);
+ #2;
+ read(slave_addr);
+ if (wbm_dat_o !== slave_data) begin
+ $display("%c[1;31m",27);
+ $display ("Monitor: Reading from slave %0d failed", i);
+ $display("Monitor: Test Wishbone Interconnect failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ end
+ $display("Monitor: Test Wishbone Interconnect Success!");
+ $display("Monitor: Test Wishbone Interconnect Passed!");
+ $finish;
+ end
+
+ task write;
+ input [`AW-1:0] addr;
+ input [`AW-1:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wbm_stb_i = 1;
+ wbm_cyc_i = 1;
+ wbm_sel_i = {SEL{1'b1}};
+ wbm_we_i = 1;
+ wbm_adr_i = addr;
+ wbm_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wbm_ack_o == 1);
+ wait(wbm_ack_o == 0);
+ wbm_cyc_i = 0;
+ wbm_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [`AW-1:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wbm_stb_i = 1;
+ wbm_cyc_i = 1;
+ wbm_adr_i = addr;
+ wbm_we_i = 0;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wbm_ack_o == 1);
+ wait(wbm_ack_o == 0);
+ wbm_cyc_i = 0;
+ wbm_stb_i = 0;
+ $display("Read Cycle Ended.");
+
+ end
+ endtask
+
+ wb_intercon #(
+ .AW(`AW),
+ .DW(`DW),
+ .NS(`NS),
+ .ADR_MASK(`ADR_MASK),
+ .SLAVE_ADR(`SLAVE_ADR)
+ ) uut(
+ // Master Interface
+ .wbm_adr_i(wbm_adr_i),
+ .wbm_stb_i(wbm_stb_i),
+ .wbm_dat_o(wbm_dat_o),
+ .wbm_ack_o(wbm_ack_o),
+
+ // Slave Interface
+ .wbs_stb_o(wbs_stb_i),
+ .wbs_dat_i(wbs_dat_o),
+ .wbs_ack_i(wbs_ack_o)
+ );
+
+ // Instantiate five dummy slaves for testing
+ dummy_slave dummy_slaves [`NS-1:0](
+ .wb_clk_i({`NS{wb_clk_i}}),
+ .wb_rst_i({`NS{wb_rst_i}}),
+ .wb_stb_i(wbs_stb_i),
+ .wb_cyc_i(wbm_cyc_i),
+ .wb_we_i(wbm_we_i),
+ .wb_sel_i(wbm_sel_i),
+ .wb_adr_i(wbm_adr_i),
+ .wb_dat_i(wbm_dat_i),
+ .wb_dat_o(wbs_dat_o),
+ .wb_ack_o(wbs_ack_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/la_wb/Makefile b/caravel/verilog/dv/wb_utests/la_wb/Makefile
new file mode 100644
index 0000000..1b76d6b
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/la_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = la_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/caravel/verilog/dv/wb_utests/la_wb/la_wb_tb.v
new file mode 100644
index 0000000..a1c10ab
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -0,0 +1,271 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+`include "la_wb.v"
+
+module la_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+ wire [127:0] la_data;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("la_wb_tb.vcd");
+ $dumpvars(0, la_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Wishbone LA Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // LA Wishbone Internal Register Addresses
+ wire [31:0] la_data_adr_0 = uut.BASE_ADR | uut.LA_DATA_0;
+ wire [31:0] la_data_adr_1 = uut.BASE_ADR | uut.LA_DATA_1;
+ wire [31:0] la_data_adr_2 = uut.BASE_ADR | uut.LA_DATA_2;
+ wire [31:0] la_data_adr_3 = uut.BASE_ADR | uut.LA_DATA_3;
+
+ wire [31:0] la_iena_adr_0 = uut.BASE_ADR | uut.LA_IENA_0;
+ wire [31:0] la_iena_adr_1 = uut.BASE_ADR | uut.LA_IENA_1;
+ wire [31:0] la_iena_adr_2 = uut.BASE_ADR | uut.LA_IENA_2;
+ wire [31:0] la_iena_adr_3 = uut.BASE_ADR | uut.LA_IENA_3;
+
+ wire [31:0] la_oenb_adr_0 = uut.BASE_ADR | uut.LA_OENB_0;
+ wire [31:0] la_oenb_adr_1 = uut.BASE_ADR | uut.LA_OENB_1;
+ wire [31:0] la_oenb_adr_2 = uut.BASE_ADR | uut.LA_OENB_2;
+ wire [31:0] la_oenb_adr_3 = uut.BASE_ADR | uut.LA_OENB_3;
+
+ reg [31:0] la_data_0;
+ reg [31:0] la_data_1;
+ reg [31:0] la_data_2;
+ reg [31:0] la_data_3;
+
+ reg [31:0] la_iena_0;
+ reg [31:0] la_iena_1;
+ reg [31:0] la_iena_2;
+ reg [31:0] la_iena_3;
+
+ reg [31:0] la_oenb_0;
+ reg [31:0] la_oenb_1;
+ reg [31:0] la_oenb_2;
+ reg [31:0] la_oenb_3;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Write to la input enable registers
+ la_iena_0 = 32'hF0F0_F0F0;
+ la_iena_1 = 32'hA0A0_A0A0;
+ la_iena_2 = 32'hB0B0_B0B0;
+ la_iena_3 = 32'hC0C0_C0C0;
+
+ write(la_iena_adr_0, la_iena_0);
+ write(la_iena_adr_1, la_iena_1);
+ write(la_iena_adr_2, la_iena_2);
+ write(la_iena_adr_3, la_iena_3);
+
+ #2;
+ // Read from la input enable registers
+ read(la_iena_adr_0);
+ if (wb_dat_o !== la_iena_0) begin
+ $display("Monitor: Error reading from la_iena_0 reg");
+ $finish;
+ end
+
+ read(la_iena_adr_1);
+ if (wb_dat_o !== la_iena_1) begin
+ $display("Monitor: Error reading from la_iena_1 reg");
+ $finish;
+ end
+
+ read(la_iena_adr_2);
+ if (wb_dat_o !== la_iena_2) begin
+ $display("Monitor: Error reading from la_iena_2 reg");
+ $finish;
+ end
+
+ read(la_iena_adr_3);
+ if (wb_dat_o !== la_iena_3) begin
+ $display("Monitor: Error reading from la_iena_3 reg");
+ $finish;
+ end
+
+ // Write to la output enable registers
+ la_oenb_0 = 32'hC00C_0CC0;
+ la_oenb_1 = 32'hD00D_0DD0;
+ la_oenb_2 = 32'h0FF0_0FF0;
+ la_oenb_3 = 32'hA00A_A00A;
+
+ write(la_oenb_adr_0, la_oenb_0);
+ write(la_oenb_adr_1, la_oenb_1);
+ write(la_oenb_adr_2, la_oenb_2);
+ write(la_oenb_adr_3, la_oenb_3);
+
+ #2;
+ // Read from la output enable registers
+ read(la_oenb_adr_0);
+ if (wb_dat_o !== la_oenb_0) begin
+ $display("Monitor: Error reading from la_oenb_0 reg");
+ $finish;
+ end
+
+ read(la_oenb_adr_1);
+ if (wb_dat_o !== la_oenb_1) begin
+ $display("Monitor: Error reading from la_oenb_1 reg");
+ $finish;
+ end
+
+ read(la_oenb_adr_2);
+ if (wb_dat_o !== la_oenb_2) begin
+ $display("Monitor: Error reading from la_oenb_2 reg");
+ $finish;
+ end
+
+ read(la_oenb_adr_3);
+ if (wb_dat_o !== la_oenb_3) begin
+ $display("Monitor: Error reading from la_oenb_3 reg");
+ $finish;
+ end
+
+ // Write to la data registers
+ la_data_0 = $urandom_range(0, 2**30);
+ la_data_1 = $urandom_range(0, 2**30);
+ la_data_2 = $urandom_range(0, 2**30);
+ la_data_3 = $urandom_range(0, 2**30);
+
+ write(la_data_adr_0, la_data_0);
+ write(la_data_adr_1, la_data_1);
+ write(la_data_adr_2, la_data_2);
+ write(la_data_adr_3, la_data_3);
+
+ // #2;
+ // Read from la data registers
+ #25;
+ if (la_data[31:0] !== la_data_0) begin
+ $display("Monitor: Error reading from la data_0 reg");
+ $finish;
+ end
+
+ if (la_data[63:32] !== la_data_1) begin
+ $display("Monitor: Error reading from la data_1 reg");
+ $finish;
+ end
+
+ if (la_data[95:64] !== la_data_2) begin
+ $display("Monitor: Error reading from la data_2 reg");
+ $finish;
+ end
+
+ if (la_data[127:96] !== la_data_3) begin
+ $display("Monitor: Error reading from la data_3 reg");
+ $finish;
+ end
+ #6;
+ $display("Monitor: Test LA Wishbone Success!");
+ $display("Monitor: Test LA Wishbone Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ la_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o),
+ .la_data(la_data)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mem_wb/Makefile b/caravel/verilog/dv/wb_utests/mem_wb/Makefile
new file mode 100644
index 0000000..dc0ed9e
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mem_wb/Makefile
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mem_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/caravel/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
new file mode 100644
index 0000000..28f3e0c
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -0,0 +1,190 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "defines.v"
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "gl/DFFRAM.v"
+`else
+ `include "DFFRAMBB.v"
+ `include "DFFRAM.v"
+`endif
+
+`include "mem_wb.v"
+
+module mem_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+ reg [3:0] wb_sel_i;
+ reg wb_we_i;
+ reg wb_cyc_i;
+ reg wb_stb_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+ reg power1;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+
+ wb_stb_i = 0; // master select-signal for the slave
+ wb_we_i = 0; // R = 0 , W = 1
+ wb_cyc_i = 0; // master is transferring
+ wb_adr_i = 0; // input addr 32-bits
+ wb_dat_i = 0; // input data 32-bits
+ wb_sel_i = 0; // where data is available on data_i 4-bits
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ #1;
+ power1 <= 1'b1;
+ end
+
+ wire VPWR;
+ wire VGND;
+ assign VGND = 1'b0;
+ assign VPWR = power1;
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("mem_wb_tb.vcd");
+ $dumpvars(0, mem_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Wishbone Memory Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [31:0] ref_data [255: 0];
+ reg [31: 0] read_data;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Randomly Write to memory array
+ for ( i = 0; i < 1; i = i + 1) begin
+ ref_data[i] = $urandom_range(0, 2**30);
+ write(i, ref_data[i]);
+ #2;
+ end
+
+ #6;
+ for ( i = 0; i < 1; i = i + 1) begin
+ read(i);
+ if (wb_dat_o !== ref_data[i]) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", ref_data[i], wb_dat_o);
+ $display("Monitor: Wishbone Memory Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ #2;
+ end
+ #6;
+ $display("Success!");
+ $display ("Monitor: Test Wishbone Memory Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ mem_wb uut(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_stb_i(wb_stb_i),
+
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mgmt_protect/Makefile b/caravel/verilog/dv/wb_utests/mgmt_protect/Makefile
new file mode 100644
index 0000000..7dd7866
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mgmt_protect/Makefile
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = mgmt_protect
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v b/caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
new file mode 100644
index 0000000..accae33
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
@@ -0,0 +1,263 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+`include "defines.v"
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "gl/mprj_logic_high.v"
+ `include "gl/mprj2_logic_high.v"
+ `include "gl/mgmt_protect.v"
+ `include "gl/mgmt_protect_hv.v"
+`else
+ `include "mprj_logic_high.v"
+ `include "mprj2_logic_high.v"
+ `include "mgmt_protect.v"
+ `include "mgmt_protect_hv.v"
+`endif
+
+module mgmt_protect_tb;
+
+ reg caravel_clk;
+ reg caravel_clk2;
+ reg caravel_rstn;
+
+ reg mprj_cyc_o_core;
+ reg mprj_stb_o_core;
+ reg mprj_we_o_core;
+ reg [31:0] mprj_adr_o_core;
+ reg [31:0] mprj_dat_o_core;
+ reg [3:0] mprj_sel_o_core;
+
+ wire [127:0] la_data_in_mprj;
+ reg [127:0] la_data_out_mprj;
+ reg [127:0] la_oenb_mprj;
+ reg [127:0] la_iena_mprj;
+
+ reg [127:0] la_data_out_core;
+ wire [127:0] la_data_in_core;
+ wire [127:0] la_oenb_core;
+
+ wire user_clock;
+ wire user_clock2;
+ wire user_reset;
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire user1_vcc_powergood;
+ wire user2_vcc_powergood;
+ wire user1_vdd_powergood;
+ wire user2_vdd_powergood;
+
+ always #12.5 caravel_clk <= (caravel_clk === 1'b0);
+ always #12.5 caravel_clk2 <= (caravel_clk2 === 1'b0);
+
+ initial begin
+ caravel_clk = 0;
+ caravel_clk2 = 0;
+ caravel_rstn = 0;
+
+ mprj_cyc_o_core = 0;
+ mprj_stb_o_core = 0;
+ mprj_we_o_core = 0;
+ mprj_adr_o_core = 0;
+ mprj_dat_o_core = 0;
+ mprj_sel_o_core = 0;
+
+ la_data_out_mprj = 0;
+ la_oenb_mprj = 0;
+ la_data_out_core = 0;
+ end
+
+ reg USER_VDD3V3;
+ reg USER_VDD1V8;
+ reg VDD3V3;
+ reg VDD1V8;
+
+ wire VCCD; // Management/Common 1.8V power
+ wire VSSD; // Common digital ground
+
+ wire VCCD1; // User area 1 1.8V power
+ wire VSSD1; // User area 1 digital ground
+ wire VCCD2; // User area 2 1.8V power
+ wire VSSD2; // User area 2 digital ground
+
+ wire VDDA1; // User area 1 3.3V power
+ wire VSSA1; // User area 1 analog ground
+ wire VDDA2; // User area 2 3.3V power
+ wire VSSA2; // User area 2 analog ground
+
+ assign VCCD = VDD1V8;
+ assign VSSD = 1'b0;
+
+ assign VCCD1 = USER_VDD1V8;
+ assign VSSD1 = 1'b0;
+
+ assign VCCD2 = USER_VDD1V8;
+ assign VSSD2 = 1'b0;
+
+ assign VDDA1 = USER_VDD3V3;
+ assign VSSA1 = 1'b0;
+
+ assign VDDA2 = USER_VDD3V3;
+ assign VSSA2 = 1'b0;
+
+ initial begin // Power-up sequence
+ VDD1V8 <= 1'b0;
+ USER_VDD3V3 <= 1'b0;
+ USER_VDD1V8 <= 1'b0;
+ #200;
+ VDD1V8 <= 1'b1;
+ #200;
+ USER_VDD3V3 <= 1'b1;
+ #200;
+ USER_VDD1V8 <= 1'b1;
+ end
+
+ initial begin
+ $dumpfile("mgmt_protect.vcd");
+ $dumpvars(0, mgmt_protect_tb);
+ #(`SIM_TIME);
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Management Protect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ initial begin
+ caravel_rstn = 1'b1;
+ mprj_cyc_o_core = 1'b1;
+ mprj_stb_o_core = 1'b1;
+ mprj_we_o_core = 1'b1;
+ mprj_sel_o_core = 4'b1010;
+ mprj_adr_o_core = 32'hF0F0;
+ mprj_dat_o_core = 32'h0F0F;
+ la_data_out_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
+ la_oenb_mprj = 128'h0000_0000_0000_0000;
+ la_data_out_core = 128'h0F0F_FFFF_F0F0_FFFF;
+ la_iena_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
+
+ wait(user1_vdd_powergood === 1'b1);
+ wait(user2_vdd_powergood === 1'b1);
+ wait(user1_vcc_powergood === 1'b1);
+ wait(user2_vcc_powergood === 1'b1);
+ #25;
+ if (user_reset !== ~caravel_rstn) begin
+ $display("Monitor: Error on user_reset. "); $finish;
+ end
+ if (mprj_cyc_o_user !== mprj_cyc_o_core) begin
+ $display("Monitor: Error on mprj_cyc_o_user. "); $finish;
+ end
+ if (mprj_stb_o_user !== mprj_stb_o_core) begin
+ $display("Monitor: Error on mprj_stb_o_user. "); $finish;
+ end
+ if (mprj_we_o_user !== mprj_we_o_core) begin
+ $display("Monitor: Error on mprj_we_o_user. "); $finish;
+ end
+ if (mprj_sel_o_user !== mprj_sel_o_core) begin
+ $display("Monitor: Error on mprj_sel_o_user. "); $finish;
+ end
+ if (mprj_adr_o_user !== mprj_adr_o_core) begin
+ $display("Monitor: Error on mprj_adr_o_user. "); $finish;
+ end
+ if (la_data_in_core !== la_data_out_mprj) begin
+ $display("%0h", la_data_in_core);
+ $display("Monitor: Error on la_data_in_core. "); $finish;
+ end
+ if (la_oenb_core !== la_oenb_mprj) begin
+ $display("Monitor: Error on la_oenb_core. "); $finish;
+ end
+ if (la_data_in_mprj !== la_data_out_core) begin
+ $display("%0h , %0h", la_data_in_mprj, la_data_out_core);
+ $display("Monitor: Error on la_data_in_mprj. "); $finish;
+ end
+ $display ("Success!");
+ $display ("Monitor: Test Management Protect Passed");
+ $finish;
+ end
+
+ mgmt_protect uut (
+ `ifdef USE_POWER_PINS
+ .vccd(VCCD),
+ .vssd(VSSD),
+ .vccd1(VCCD1),
+ .vssd1(VSSD1),
+ .vccd2(VCCD2),
+ .vssd2(VSSD2),
+ .vdda1(VDDA1),
+ .vssa1(VSSA1),
+ .vdda2(VDDA2),
+ .vssa2(VSSA2),
+ `endif
+
+ .caravel_clk (caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core (mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+
+ .la_data_out_core(la_data_out_core),
+ .la_data_in_core (la_data_in_core),
+ .la_oenb_core(la_oenb_core),
+
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_iena_mprj(la_iena_mprj),
+
+ .user_clock (user_clock),
+ .user_clock2(user_clock2),
+ .user_reset (user_reset),
+
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user (mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+
+ .user1_vcc_powergood(user1_vcc_powergood),
+ .user2_vcc_powergood(user2_vcc_powergood),
+ .user1_vdd_powergood(user1_vdd_powergood),
+ .user2_vdd_powergood(user2_vdd_powergood)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile b/caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile
new file mode 100644
index 0000000..f354018
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..fd9e5a2
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,159 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "defines.v"
+`include "mprj_ctrl.v"
+
+module mprj_ctrl_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ // Mega Project Control Registers
+ wire [31:0] mprj_ctrl = uut.BASE_ADR | uut.IOCONFIG;
+ wire [31:0] pwr_ctrl = uut.BASE_ADR | uut.PWRDATA;
+
+ initial begin
+ $dumpfile("mprj_ctrl_tb.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [31:0] data;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
+ data = $urandom_range(0, 2**(7));
+ write(mprj_ctrl+i*4, data);
+ #2;
+ read(mprj_ctrl+i*4);
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from IO-CTRL Failed.");
+ $finish;
+ end
+ end
+
+ data = $urandom_range(0, 2**(`MPRJ_PWR_PADS-2));
+ write(pwr_ctrl, data);
+ #2;
+ read(pwr_ctrl);
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from POWER-CTRL Failed.");
+ $finish;
+ end
+
+
+ $display("Success!");
+ $display ("Monitor: Test Mega-Project Control Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ mprj_ctrl_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile b/caravel/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile
new file mode 100644
index 0000000..8bf03c7
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = spi_sysctrl_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/caravel/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/caravel/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
new file mode 100644
index 0000000..99cb008
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -0,0 +1,157 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "simple_spi_master.v"
+
+module spi_sysctrl_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ reg [31:0] spi_cfg_data;
+ reg [31:0] spi_data;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ // SPI Control Register Addresses
+ wire [31:0] spi_cfg = uut.BASE_ADR | uut.CONFIG;
+ wire [31:0] spi_data_adr = uut.BASE_ADR | uut.DATA;
+
+ initial begin
+ $dumpfile("spi_sysctrl_wb_tb.vcd");
+ $dumpvars(0, spi_sysctrl_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test SPI System Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #10;
+
+ // Write to SPI_CFG
+ spi_cfg_data = {16'd0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0,
+ 1'b0, 1'b0, 1'b0, 8'd2};
+ write(spi_cfg, spi_cfg_data);
+
+ #2;
+ // Read from SPI_CFG
+ read(spi_cfg);
+ if (wb_dat_o !== spi_cfg_data) begin
+ $display("Error reading spi_cfg reg");
+ $finish;
+ end
+
+ // Read default value of SPI_DATA
+ spi_data = 32'h00FF;
+ read(spi_data_adr);
+ if (wb_dat_o !== spi_data) begin
+ $display("Error reading data register reg");
+ $finish;
+ end
+ $display("Success!");
+ $display ("Monitor: Test SPI-SYSCTRL WB Passed");
+ $finish;
+ end
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Monitor: Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ wb_adr_i = 0;
+ $display("Monitor: Read Cycle Ended.");
+ end
+ endtask
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ wb_adr_i = 0;
+ wait(wb_ack_o == 0);
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ simple_spi_master_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/spimemio_wb/Makefile b/caravel/verilog/dv/wb_utests/spimemio_wb/Makefile
new file mode 100644
index 0000000..d145f04
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/spimemio_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = spimemio_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../ -I ../../ -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/caravel/verilog/dv/wb_utests/spimemio_wb/flash.hex b/caravel/verilog/dv/wb_utests/spimemio_wb/flash.hex
new file mode 100644
index 0000000..23bd76d
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/spimemio_wb/flash.hex
@@ -0,0 +1,6 @@
+@10000000
+a1
+b1
+c1
+d1
+f1
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/caravel/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
new file mode 100644
index 0000000..c474fd0
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -0,0 +1,234 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define FLASH_BASE 32'h 1000_000
+
+`include "spimemio.v"
+// `include "spiflash.v"
+
+module spimemio_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_flash_stb_i;
+ reg wb_cfg_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+
+ wire wb_flash_ack_o;
+ wire wb_cfg_ack_o;
+ wire [31:0] wb_flash_dat_o;
+ wire [31:0] wb_cfg_dat_o;
+
+ wire flash_csb;
+ wire flash_clk;
+
+ wire flash_io0_oeb;
+ wire flash_io1_oeb;
+ wire flash_io2_oeb;
+ wire flash_io3_oeb;
+
+ wire flash_io0_di = 1'b 1;
+ wire flash_io1_di = 1'b 1;
+ wire flash_io2_di = 1'b 1;
+ wire flash_io3_di = 1'b 1;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_flash_stb_i = 0;
+ wb_cfg_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_we_i = 0;
+ wb_sel_i = 0;
+ wb_adr_i = 0;
+ wb_dat_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ spimemio_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_flash_stb_i(wb_flash_stb_i),
+ .wb_cfg_stb_i(wb_cfg_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_we_i(wb_we_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_flash_ack_o(wb_flash_ack_o),
+ .wb_cfg_ack_o(wb_cfg_ack_o),
+ .wb_flash_dat_o(wb_flash_dat_o),
+ .wb_cfg_dat_o(wb_cfg_dat_o),
+
+ .flash_clk(flash_clk),
+ .flash_csb(flash_csb),
+
+ .flash_io0_oeb(flash_io0_oeb),
+ .flash_io1_oeb(flash_io1_oeb),
+ .flash_io2_oeb(flash_io2_oeb),
+ .flash_io3_oeb(flash_io3_oeb),
+
+ .flash_io0_di(flash_io0_di),
+ .flash_io1_di(flash_io1_di),
+ .flash_io2_di(flash_io2_di),
+ .flash_io3_di(flash_io3_di)
+ );
+
+ initial begin
+ $dumpfile("spimemio_wb_tb.vcd");
+ $dumpvars(0, spimemio_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test spimmemio Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ wire [31:0] cfgreg_data;
+ assign cfgreg_data = {
+ 1'b 1,
+ 8'b 0,
+ 3'b 111,
+ 4'b 1010,
+ 4'b 0, // make sure is it tied to zero in the module itself
+ {~flash_io3_oeb, ~flash_io2_oeb, ~flash_io1_oeb, ~flash_io0_oeb},
+ 2'b 0,
+ flash_csb,
+ flash_clk,
+ {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}
+ };
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Read from flash
+ for (i = `FLASH_BASE; i < `FLASH_BASE + 100 ; i = i + 4) begin
+ read(i, 1, 0);
+ if (wb_flash_dat_o !== 32'hFFFF_FFFF) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", 32'hFFFF_FFFF, wb_flash_dat_o);
+ $display("Monitor: Wishbone spimemio Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ #2;
+ end
+
+ #6;
+ // Write to Configuration register
+ write(cfgreg_data, 0);
+ #2;
+ read(0, 0, 1);
+ if (wb_cfg_dat_o !== cfgreg_data) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", cfgreg_data, wb_cfg_dat_o);
+ $display("Monitor: Wishbone spimemio Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ $display("Success!");
+ $display("Monitor: Wishbone spimemio Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] data;
+ input [31:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_cfg_stb_i = 1'b 1;
+ wb_flash_stb_i = 1'b 0;
+ wb_cyc_i = 1'b 1;
+ wb_sel_i = 4'b 1111; // complete word
+ wb_we_i = 1'b 1; // write enable
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ end
+
+ wait_ack();
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ input flash_stb;
+ input cfg_stb;
+ begin
+ wb_flash_stb_i = flash_stb;
+ wb_cfg_stb_i = cfg_stb;
+
+ wb_cyc_i = 1'b 1;
+ wb_adr_i = addr;
+ wb_dat_i = 24;
+ wb_sel_i = 4'b 1111; // complete word
+ wb_we_i = 1'b 0; // read
+ $display("Initiated Read transaction...");
+ wait_ack();
+ end
+ endtask
+
+ task wait_ack;
+ // Wait for an ACK
+ if (wb_cfg_stb_i == 1) begin
+ @(posedge wb_cfg_ack_o) begin
+ #2; // To end the transaction on the falling edge of ack
+ wb_cyc_i = 1'b 0;
+ wb_cfg_stb_i = 1'b 0;
+ $display("Monitor: Received an ACK from slave");
+ end
+ end
+ else begin
+ @(posedge wb_flash_ack_o) begin
+ #2; // To end the transaction on the falling edge of ack
+ wb_cyc_i = 1'b 0;
+ wb_flash_stb_i = 1'b 0;
+ $display("Monitor: Received an ACK from slave");
+ end
+ end
+ endtask
+
+ // spiflash #(
+ // .FILENAME("flash.hex")
+ // ) spiflash (
+ // .csb(flash_csb),
+ // .clk(flash_clk),
+ // .io0(flash_io0),
+ // .io1(flash_io1),
+ // .io2(flash_io2),
+ // .io3(flash_io3)
+ // );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/storage_wb/Makefile b/caravel/verilog/dv/wb_utests/storage_wb/Makefile
new file mode 100644
index 0000000..6b04de9
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/storage_wb/Makefile
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = storage_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/caravel/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
new file mode 100644
index 0000000..71a84df
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -0,0 +1,257 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// `define DBG
+
+`define STORAGE_BASE_ADR 32'h0100_0000
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "defines.v"
+`include "sram_1rw1r_32_256_8_sky130.v"
+
+`ifdef GL
+ `include "gl/storage.v"
+`else
+ `include "storage.v"
+`endif
+
+`include "storage_bridge_wb.v"
+
+module storage_tb;
+
+ localparam [(`RAM_BLOCKS*24)-1:0] STORAGE_RW_ADR = {
+ {24'h 10_0000},
+ {24'h 00_0000}
+ };
+
+ localparam [23:0] STORAGE_RO_ADR = {
+ {24'h 20_0000}
+ };
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+ reg [3:0] wb_sel_i;
+ reg wb_we_i;
+ reg wb_cyc_i;
+ reg [1:0] wb_stb_i;
+ wire [1:0] wb_ack_o;
+ wire [31:0] wb_rw_dat_o;
+
+ // MGMT_AREA RO WB Interface
+ wire [31:0] wb_ro_dat_o;
+
+ wire [`RAM_BLOCKS-1:0] mgmt_ena;
+ wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
+ wire [`RAM_BLOCKS-1:0] mgmt_wen;
+ wire [31:0] mgmt_wdata;
+ wire [7:0] mgmt_addr;
+ wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
+ wire ro_ena;
+ wire [7:0] ro_addr;
+ wire [31:0] ro_rdata;
+ reg power1;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ #1;
+ power1 <= 1'b1;
+ end
+
+ wire VPWR;
+ wire VGND;
+ assign VGND = 1'b0;
+ assign VPWR = power1;
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("storage.vcd");
+ $dumpvars(0, storage_tb);
+ repeat (100) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Storage Area Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ reg [31:0] ref_data [255: 0];
+ reg [(24*`RAM_BLOCKS)-1:0] storage_rw_adr = STORAGE_RW_ADR;
+ reg [23:0] storage_ro_adr = STORAGE_RO_ADR;
+ reg [31:0] block_adr;
+
+ integer i,j;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Test MGMT R/W port and user RO port
+ for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
+ for ( j = 0; j < 100; j = j + 1) begin
+ if (i == 0) begin
+ ref_data[j] = $urandom_range(0, 2**30);
+ end
+ block_adr = (storage_rw_adr[24*i+:24] + (j << 2)) | `STORAGE_BASE_ADR;
+ write(block_adr, ref_data[j]);
+ #2;
+ end
+ end
+
+ for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
+ for ( j = 0; j < 100; j = j + 1) begin
+ block_adr = (storage_rw_adr[24*i+:24] + (j << 2)) | `STORAGE_BASE_ADR;
+ read(block_adr, 0);
+ if (wb_rw_dat_o !== ref_data[j]) begin
+ $display("Got %0h, Expected %0h from addr %0h: ",wb_rw_dat_o,ref_data[j], block_adr);
+ $display("Monitor: MGMT R/W Operation Failed");
+ $finish;
+ end
+
+ if (i == 0) begin
+ block_adr = (storage_ro_adr + (j << 2)) | `STORAGE_BASE_ADR;
+ read(block_adr, 1);
+ if (wb_ro_dat_o !== ref_data[j]) begin
+ $display("Monitor: MGMT RO Operation Failed");
+ $finish;
+ end
+ end
+ #2;
+ end
+ end
+
+ $display("Success");
+ $display ("Monitor: Test Storage Area Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i[0] = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o[0] == 1);
+ wait(wb_ack_o[0] == 0);
+ wb_cyc_i = 0;
+ wb_stb_i[0] = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ input integer interface;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i[interface] = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o[interface] == 1);
+ wait(wb_ack_o[interface] == 0);
+ wb_cyc_i = 0;
+ wb_stb_i[interface] = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ storage_bridge_wb #(
+ .RW_BLOCKS_ADR(STORAGE_RW_ADR),
+ .RO_BLOCKS_ADR(STORAGE_RO_ADR)
+ ) wb_bridge (
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_rw_dat_o(wb_rw_dat_o),
+
+ // MGMT_AREA RO WB Interface
+ .wb_ro_dat_o(wb_ro_dat_o),
+
+ // MGMT Area native memory interface
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // MGMT_AREA RO Interface
+ .mgmt_ena_ro(ro_ena),
+ .mgmt_addr_ro(ro_addr),
+ .mgmt_rdata_ro(ro_rdata)
+ );
+
+ storage uut (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ // Management R/W WB interface
+ .mgmt_clk(wb_clk_i),
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // Management RO interface
+ .mgmt_ena_ro(ro_ena),
+ .mgmt_addr_ro(ro_addr),
+ .mgmt_rdata_ro(ro_rdata)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile b/caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile
new file mode 100644
index 0000000..89aa77b
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = sysctrl_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
new file mode 100644
index 0000000..77140c7
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "sysctrl.v"
+
+module sysctrl_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("sysctrl_wb_tb.vcd");
+ $dumpvars(0, sysctrl_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test System Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // System Control Default Register Addresses
+ wire [31:0] clk_out_adr = uut.BASE_ADR | uut.CLK_OUT;
+ wire [31:0] trap_out_adr = uut.BASE_ADR | uut.TRAP_OUT;
+ wire [31:0] irq_src_adr = uut.BASE_ADR | uut.IRQ_SRC;
+
+ reg clk1_output_dest;
+ reg clk2_output_dest;
+ reg trap_output_dest;
+ reg irq_7_inputsrc;
+ reg irq_8_inputsrc;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ clk1_output_dest = 1'b1;
+ clk2_output_dest = 1'b1;
+ trap_output_dest = 1'b1;
+ irq_7_inputsrc = 1'b1;
+ irq_8_inputsrc = 1'b1;
+
+ // Write to System Control Registers
+ write(clk_out_adr, clk1_output_dest);
+ write(trap_out_adr, trap_output_dest);
+ write(irq_src_adr, irq_7_inputsrc);
+ #2;
+ read(clk_out_adr);
+ if (wb_dat_o !== clk1_output_dest) begin
+ $display("Error reading CLK1 output destination register.");
+ $finish;
+ end
+
+ read(trap_out_adr);
+ if (wb_dat_o !== trap_output_dest) begin
+ $display("Error reading trap output destination register.");
+ $finish;
+ end
+
+ read(irq_src_adr);
+ if (wb_dat_o !== irq_7_inputsrc) begin
+ $display("Error reading IRQ7 input source register.");
+ $finish;
+ end
+
+ $display("Success!");
+ $display ("Monitor: Test System Control Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Monitor: Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Monitor: Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Monitor: Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Monitor: Read Cycle Ended.");
+ end
+ endtask
+
+ sysctrl_wb uut(
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/uart_wb/Makefile b/caravel/verilog/dv/wb_utests/uart_wb/Makefile
new file mode 100644
index 0000000..d1c587f
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/uart_wb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = uart_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I .. -I ../../ -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/caravel/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
new file mode 100644
index 0000000..da48151
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -0,0 +1,169 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "simpleuart.v"
+
+module uart_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_adr_i;
+ reg [31:0] wb_dat_i;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ wire tbuart_rx;
+ wire ser_rx;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_we_i = 0;
+ wb_cyc_i = 0;
+ wb_adr_i = 0;
+ wb_dat_i = 0;
+ wb_sel_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("uart_wb_tb.vcd");
+ $dumpvars(0, uart_wb_tb);
+ repeat (500) begin
+ repeat (10000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display("Monitor: Timeout, Test UART Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ wire [31:0] div_reg_addr = uut.BASE_ADR | uut.CLK_DIV;
+ wire [31:0] div_reg_data = 32'h FFFF_FFFF;
+
+ wire [31:0] dat_reg_addr = uut.BASE_ADR | uut.DATA;
+ wire [31:0] dat_reg_data = 32'h FFFF_FFFF;
+
+ initial begin
+ // Reset Operation
+ wb_rst_i = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ // Write to div register
+ write(div_reg_addr, div_reg_data);
+ #2;
+ read(div_reg_addr);
+ if (wb_dat_o !== div_reg_data) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", div_reg_data, wb_dat_o);
+ $display("Monitor: Wishbone UART Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ #6;
+
+ // Write Operation: writes to data register
+ write(dat_reg_addr, dat_reg_data);
+ #2;
+ read(dat_reg_addr);
+ if (wb_dat_o !== dat_reg_data) begin
+ $display("%c[1;31m",27);
+ $display("Expected %0b, but Got %0b ", dat_reg_data, wb_dat_o);
+ $display("Monitor: Wishbone UART Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+ $display("Success!");
+ $display("Monitor: Wishbone UART Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ #2;
+ wb_we_i = 0;
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ #2;
+ // wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ simpleuart_wb uut (
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o),
+ .ser_tx(tbuart_rx),
+ .ser_rx(ser_rx)
+ );
+
+endmodule
diff --git a/caravel/verilog/gl/DFFRAM.v b/caravel/verilog/gl/DFFRAM.v
new file mode 100644
index 0000000..602189c
--- /dev/null
+++ b/caravel/verilog/gl/DFFRAM.v
@@ -0,0 +1,263366 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+module DFFRAM (CLK,
+ EN,
+ VPWR,
+ VGND,
+ A,
+ Di,
+ Do,
+ WE);
+ input CLK;
+ input EN;
+ input VPWR;
+ input VGND;
+ input [7:0] A;
+ input [31:0] Di;
+ output [31:0] Do;
+ input [3:0] WE;
+
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[0] (.A(A[0]),
+ .X(\BLOCK[0].RAM128.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[1] (.A(A[1]),
+ .X(\BLOCK[0].RAM128.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[2] (.A(A[2]),
+ .X(\BLOCK[0].RAM128.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[3] (.A(A[3]),
+ .X(\BLOCK[0].RAM128.A_buf[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[4] (.A(A[4]),
+ .X(\BLOCK[0].RAM128.A_buf[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[5] (.A(A[5]),
+ .X(\BLOCK[0].RAM128.A_buf[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.ABUF[6] (.A(A[6]),
+ .X(\BLOCK[0].RAM128.A_buf[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.ABUF[0] (.A(\BLOCK[0].RAM128.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.ABUF[1] (.A(\BLOCK[0].RAM128.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.ABUF[2] (.A(\BLOCK[0].RAM128.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.ABUF[3] (.A(\BLOCK[0].RAM128.A_buf[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.ABUF[4] (.A(\BLOCK[0].RAM128.A_buf[4] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[4] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[5] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[6] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[0].FLOATBUF[7] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[10] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[11] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[12] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[13] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[14] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[15] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[8] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[1].FLOATBUF[9] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[16] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[17] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[18] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[19] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[20] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[21] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[22] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[2].FLOATBUF[23] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[24] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[25] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[26] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[27] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[28] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[29] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[30] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.BYTE[3].FLOATBUF[31] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3b_4 \BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[3] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[4] ),
+ .C_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.EN ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3b_4 \BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[4] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[3] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3b_4 \BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[3] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[4] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_4 \BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.AND3 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[4] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[3] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[10] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[10] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[11] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[11] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[12] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[12] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[13] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[13] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[14] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[14] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[15] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[15] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[16] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[16] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[17] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[17] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[18] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[18] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[19] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[19] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[20] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[20] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[21] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[21] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[22] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[22] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[23] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[23] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[24] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[24] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[25] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[25] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[26] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[26] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[27] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[27] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[28] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[28] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[29] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[29] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[30] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[30] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[31] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[31] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[4] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[4] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[5] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[5] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[6] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[6] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[7] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[7] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[8] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[8] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[0].RAM32.DIBUF[9] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[9] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[0] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[10] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[10] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[11] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[11] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[12] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[12] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[13] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[13] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[14] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[14] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[15] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[15] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[16] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[16] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[17] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[17] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[18] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[18] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[19] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[19] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[1] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[20] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[20] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[21] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[21] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[22] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[22] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[23] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[23] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[24] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[24] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[25] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[25] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[26] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[26] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[27] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[27] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[28] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[28] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[29] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[29] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[2] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[30] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[30] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[31] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[31] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[3] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[4] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[5] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[6] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[7] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[8] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[8] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.Do_FF[9] (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do[9] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.FBUFENBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.FBUFENBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.FBUFENBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.FBUFENBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.float_buf_en[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.ABUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.ABUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.ABUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND3 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND4 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND5 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND6 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.AND7 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.ABUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.ABUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.ABUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND3 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND4 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND5 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND6 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.AND7 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[1].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.ABUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.ABUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.ABUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .D_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND3 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND4 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND5 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND6 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.AND7 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.DEC.EN_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[2].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.ABUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.ABUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.ABUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .D_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND3 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND4 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND5 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND6 (.A_N(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.AND7 (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.DEC.EN_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[0].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[3].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.TIE[0] (.LO(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.TIE[1] (.LO(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.TIE[2] (.LO(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \BLOCK[0].RAM128.BLOCK[0].RAM32.TIE[3] (.LO(\BLOCK[0].RAM128.BLOCK[0].RAM32.lo[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[0].RAM32.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WE[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.ABUF[0] (.A(\BLOCK[0].RAM128.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.ABUF[1] (.A(\BLOCK[0].RAM128.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.ABUF[2] (.A(\BLOCK[0].RAM128.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.ABUF[3] (.A(\BLOCK[0].RAM128.A_buf[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.ABUF[4] (.A(\BLOCK[0].RAM128.A_buf[4] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[4] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[5] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[6] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[0].FLOATBUF[7] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[10] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[11] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[12] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[13] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[14] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[15] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[8] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[1].FLOATBUF[9] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[16] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[17] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[18] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[19] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[20] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[21] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[22] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[2].FLOATBUF[23] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[24] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[25] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[26] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[27] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[28] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[29] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[30] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.BYTE[3].FLOATBUF[31] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.lo[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3b_4 \BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[3] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[4] ),
+ .C_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.EN ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3b_4 \BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[4] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[3] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3b_4 \BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[3] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[4] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[2].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_4 \BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.AND3 (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[4] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[3] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[3].RAM8.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[10] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[10] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[11] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[11] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[12] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[12] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[13] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[13] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[14] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[14] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[15] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[15] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[16] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[16] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[17] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[17] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[18] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[18] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[19] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[19] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[20] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[20] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[21] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[21] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[22] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[22] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[23] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[23] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[24] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[24] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[25] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[25] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[26] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[26] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[27] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[27] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[28] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[28] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[29] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[29] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[30] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[30] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[31] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[31] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[4] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[4] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[5] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[5] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[6] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[6] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[7] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[7] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[8] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[8] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \BLOCK[0].RAM128.BLOCK[1].RAM32.DIBUF[9] (.A(\BLOCK[0].RAM128.BLOCK[0].RAM32.Di[9] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[0] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[10] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[10] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[11] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[11] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[12] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[12] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[13] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[13] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[14] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[14] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[15] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[15] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[16] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[16] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[17] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[17] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[18] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[18] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[19] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[19] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[1] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[20] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[20] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[21] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[21] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[22] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[22] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[23] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[23] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[24] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[24] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[25] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[25] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[26] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[26] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[27] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[27] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[28] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[28] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[29] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[29] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[2] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[30] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[30] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[31] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[31] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[3] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[4] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[5] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[6] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[7] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[8] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[8] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.Do_FF[9] (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do[9] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[0].RAM32.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.DEC.EN ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.FBUFENBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.FBUFENBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.FBUFENBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.FBUFENBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.float_buf_en[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.ABUF[0] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.ABUF[1] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.ABUF[2] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND3 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND4 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND5 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND6 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.AND7 (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.DEC.EN_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[3].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[4].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[5].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[6].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WORD[7].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.ABUF[0] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.ABUF[1] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.ABUF[2] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.A_buf[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND0 (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND1 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND2 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[2].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND3 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[3].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND4 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[4].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND5 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[5].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND6 (.A_N(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[6].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.AND7 (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[0] ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[1] ),
+ .C(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.A_buf[2] ),
+ .D(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[7].W.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.ENBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.DEC.EN_buf ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WEBUF[0] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[0] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WEBUF[1] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[1] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WEBUF[2] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[2] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WEBUF[3] (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[0].RAM8.WE[3] ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[17] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[18] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[18] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[19] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[19] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[20] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[20] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[21] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[21] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[22] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[22] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[23] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[23] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[2].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[24] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[24] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[25] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[25] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[26] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[26] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[27] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[27] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[28] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[28] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[29] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[29] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[30] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[30] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[31] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[31] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[3].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.CLKBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.CLK_buf ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.SELBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.SEL ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.SEL ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[0] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[1] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[2] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[3] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[4] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[5] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[6] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[7] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[0].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[8] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[9] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[1].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[1] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[2].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[10] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[2].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[2] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[3].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[11] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[3].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[3] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[4].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[12] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[4].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[4] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[5].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[13] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[5].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[5] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[6].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[14] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[6].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[6] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[7].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[15] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.BIT[7].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.q_wire[7] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlclkp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.CG (.GATE(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .GCLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.GCLK ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.CLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.CGAND (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[0].W.BYTE[1].B.WE ),
+ .X(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.we_wire ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SELINV (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[0].B.SEL ),
+ .Y(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[1].B.SEL_B ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[0].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[16] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[0].OBUF (.A(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[0] ),
+ .TE_B(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.SEL_B ),
+ .Z(\BLOCK[0].RAM128.BLOCK[1].RAM32.Do_pre[16] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[1].FF (.D(\BLOCK[0].RAM128.BLOCK[1].RAM32.Di_buf[17] ),
+ .Q(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.q_wire[1] ),
+ .CLK(\BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.GCLK ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 \BLOCK[0].RAM128.BLOCK[1].RAM32.SLICE[1].RAM8.WORD[1].W.BYTE[2].B.BIT[1].OBU
