commit vco passing prechecks
diff --git a/README.md b/README.md
index d7d53a3..eef6e19 100644
--- a/README.md
+++ b/README.md
@@ -4,15 +4,43 @@
---
-| :exclamation: Important Note |
-|-----------------------------------------|
-## Please fill in your project documentation in this README.md file
+High Speed VCO in Skywater 130nm
+====
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
+
+Peace & Global cooperation
+
+High Speed VCO in Skywater 130nm.
+Project info: https://github.com/powergainer/vco
-:warning: | Use this sample project for analog user projects.
-:---: | :---
----
-
-Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/caravel b/caravel
index 0f16ba8..05a73d7 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 0f16ba8eaae841a6f122fc0d5837005d3312fd2b
+Subproject commit 05a73d70b12b1f0ee9e2043f6b46d43e42031bec
diff --git a/gds/old/user_analog_project_wrapper_-_copy_beforehand.gds b/gds/old/user_analog_project_wrapper_-_copy_beforehand.gds
new file mode 100644
index 0000000..764b362
--- /dev/null
+++ b/gds/old/user_analog_project_wrapper_-_copy_beforehand.gds
Binary files differ
diff --git a/gds/old/user_analog_project_wrapper_-_forced_xor_differences.gds b/gds/old/user_analog_project_wrapper_-_forced_xor_differences.gds
new file mode 100644
index 0000000..b6d2871
--- /dev/null
+++ b/gds/old/user_analog_project_wrapper_-_forced_xor_differences.gds
Binary files differ
diff --git a/gds/old/user_analog_project_wrapper_-_mine.gds b/gds/old/user_analog_project_wrapper_-_mine.gds
new file mode 100644
index 0000000..1e0f2c2
--- /dev/null
+++ b/gds/old/user_analog_project_wrapper_-_mine.gds
Binary files differ
diff --git a/gds/old/user_analog_project_wrapper_-_mine_that_passes_xor_just_consistency_fails.gds b/gds/old/user_analog_project_wrapper_-_mine_that_passes_xor_just_consistency_fails.gds
new file mode 100644
index 0000000..309a86c
--- /dev/null
+++ b/gds/old/user_analog_project_wrapper_-_mine_that_passes_xor_just_consistency_fails.gds
Binary files differ
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 764b362..075e4a6 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 120000
index 0000000..3522dc1
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1 @@
+/usr/local/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc
\ No newline at end of file
diff --git a/mag/3-stage_cs-vco_dp9.ext b/mag/3-stage_cs-vco_dp9.ext
new file mode 100644
index 0000000..ffd31d5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9.ext
@@ -0,0 +1,862 @@
+timestamp 1647616625
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use vco_switch_n_v2 vco_switch_n_v2_0 1 0 -1367 0 -1 -304
+use vco_switch_n_v2 vco_switch_n_v2_1 1 0 -721 0 -1 -304
+use vco_switch_n_v2 vco_switch_n_v2_2 1 0 -78 0 -1 -304
+use vco_switch_n_v2 vco_switch_n_v2_3 1 0 568 0 -1 -304
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -685 0 1 -537
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 -271 0 1 -397
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -891 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B 1 0 -478 0 1 -537
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16A -1 0 -64 0 1 -299
+use sky130_fd_pr__nfet_01v8_MV8TJR XM16B -1 0 143 0 1 -517
+use sky130_fd_pr__nfet_01v8_26QSQN XM16C 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16D_1 -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16 -1 0 -64 0 1 -577
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_26QSQN XM16D_2 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1357 0 1 45
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -397
+use sky130_fd_pr__pfet_01v8_MP1P4U XM1 0 1 -465 -1 0 351
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -437 1 0 101
+use sky130_fd_pr__pfet_01v8_MP0P75 XM3 0 1 -99 -1 0 351
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4 0 -1 -167 1 0 101
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 -271 0 1 899
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5 0 -1 517 1 0 351
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_4XEGTB XM11A 1 0 -64 0 1 791
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11C 1 0 350 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11D_1 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11D_2 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__nfet_01v8_LS30AB XM22_0p42 1 0 886 0 1 107
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 562
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -688 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -894 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B 1 0 -482 0 1 1040
+use vco_switch_p vco_switch_p_0 1 0 -1367 0 -1 2536
+use vco_switch_p vco_switch_p_1 1 0 -721 0 -1 2536
+use sky130_fd_pr__pfet_01v8_KQRM7Z XM11B 1 0 143 0 1 1019
+use sky130_fd_pr__pfet_01v8_4XEGTB XM11 1 0 -64 0 1 1079
+use vco_switch_p vco_switch_p_2 1 0 -78 0 -1 2536
+use vco_switch_p vco_switch_p_3 1 0 568 0 -1 2536
+port "vctrl" 3 -1753 -752 -1553 -552 m1
+port "sel3" 7 -1190 1364 -1158 1396 m1
+port "sel2" 6 -1279 1445 -1247 1477 m1
+port "sel1" 5 -1359 1519 -1327 1551 m1
+port "sel0" 4 -1436 1674 -1404 1706 m1
+port "out" 2 1710 200 1766 228 li
+port "vdd" 0 1633 2181 1833 2381 m1
+port "vss" 1 1893 2441 2093 2641 m1
+node "ng3" 5 1344.6 528 -684 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12786 754 48852 2478 28280 1056 0 0 0 0 0 0
+node "m1_488_n269#" 1 311.685 488 -269 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 270 102 0 0 0 0 0 0 0 0 0 0
+node "ng2" 3 1086.69 313 -691 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9246 590 45116 1734 23046 876 0 0 0 0 0 0
+node "ng1" 2 584.509 112 -696 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9293 590 14380 730 26056 984 0 0 0 0 0 0
+node "ng0" 5 1349.87 -437 -1048 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9008 576 43160 2124 48332 1842 0 0 0 0 0 0
+node "vgp" 4 364.138 -758 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64630 2902 0 0 0 0 0 0 0 0 0 0
+node "m1_n1099_1625#" 16 215.654 -1099 1625 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45201 2284 140128 7146 115778 4430 0 0 0 0 0 0
+node "vctrl" 19 3367.75 -1753 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80203 2894 179744 9136 112866 4206 0 0 0 0 0 0
+node "sel3" 29 1850.7 -1190 1364 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111696 6532 213524 10756 49048 1852 0 0 0 0 0 0
+node "sel2" 26 1786.27 -1279 1445 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111866 6542 169112 8562 39632 1552 0 0 0 0 0 0
+node "sel1" 22 1796.64 -1359 1519 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111832 6540 123672 6290 30152 1236 0 0 0 0 0 0
+node "pg3" 5 294.331 527 1143 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13002 754 50493 2436 45016 1616 0 0 0 0 0 0
+node "pg2" 4 204.309 318 1140 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8254 558 33796 1736 42476 1516 0 0 0 0 0 0
+node "sel0" 17 1955.81 -1436 1674 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108240 6444 64752 3340 0 0 0 0 0 0 0 0
+node "pg0" 5 179.199 -437 1792 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9008 576 44126 2174 65552 2416 0 0 0 0 0 0
+node "pg1" 2 182.15 113 1131 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9293 590 15202 728 45076 1618 0 0 0 0 0 0
+node "li_528_n678#" 55 145.007 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 101 197.891 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9588 632 0 0 0 0 0 0 0 0 0 0 0 0
+node "net8" 44 3574.38 -460 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 95979 4106 0 0 0 0 0 0 0 0 0 0
+node "net6" 207 214.144 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 245.72 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "net4" 264 349.918 -102 132 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24694 1530 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n118_290#" 51 6.86424 -118 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 831 146 0 0 0 0 0 0 0 0 0 0 0 0
+node "net5" 222 768.32 -690 207 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17777 1192 35970 2150 0 0 0 0 0 0 0 0 0 0
+node "net3" 287 278.665 -545 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27234 1670 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1388_346#" 59 0 1388 346 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 238 82 0 0 0 0 0 0 0 0 0 0 0 0
+node "net7" 221 134.496 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20944 1300 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 473 228.571 1710 200 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 57222 3056 0 0 0 0 0 0 0 0 0 0 0 0
+node "net2" 56 0 -517 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 111768 4848 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 150 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14178 902 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 0 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 56.5972 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 32.5685 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 47677 19504.4 1633 2181 m1 0 0 0 0 5615313 15454 0 0 287028 16952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 313276 18700 1096287 27918 39012 1368 394100 8080 0 0 0 0 0 0
+substrate "vss" 0 0 1893 2441 m1 0 0 0 0 0 0 0 0 0 0 267036 15776 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 278324 16644 861968 30636 39012 1368 341000 7018 0 0 0 0 0 0
+cap "ng1" "ng3" 13.7266
+cap "vgp" "m1_n1099_1625#" 29.1549
+cap "ng0" "vctrl" 1475.82
+cap "pg1" "sel3" 103.983
+cap "sel0" "ng0" 5.55985
+cap "vctrl" "vdd" 352.59
+cap "sel0" "vdd" 21.3132
+cap "pg1" "net2" 1.33005
+cap "net4" "net5" 80.6316
+cap "sel2" "pg2" 192.028
+cap "sel2" "ng3" 19.4974
+cap "sel1" "pg1" 83.4672
+cap "net7" "li_1388_346#" 12.97
+cap "ng3" "ng2" 368.531
+cap "net7" "net6" 106.342
+cap "pg1" "sel2" 166.472
+cap "out" "li_1388_346#" 6.26867
+cap "vdd" "pg2" 873.473
+cap "ng3" "vdd" 216.549
+cap "li_1388_346#" "vdd" 17.0301
+cap "sel0" "pg0" 5.55985
+cap "net4" "li_n118_290#" 23.2619
+cap "pg3" "m1_n1099_1625#" 167.763
+cap "vgp" "vctrl" 2.925
+cap "out" "net6" 3.9521
+cap "net2" "net5" 157.498
+cap "net6" "vdd" 126.227
+cap "pg1" "vdd" 503.171
+cap "pg3" "li_523_1149#" 92.738
+cap "sel0" "m1_n1099_1625#" 199.69
+cap "net7" "li_1179_712#" 3.3
+cap "net8" "m1_488_n269#" 15.7628
+cap "ng1" "sel3" 15.8171
+cap "pg0" "pg2" 15.9873
+cap "sel1" "sel3" 1989.41
+cap "out" "li_1179_712#" 46.9389
+cap "vdd" "net4" 146.063
+cap "a_879_204#" "vdd" 11
+cap "vdd" "li_1179_712#" 342.954
+cap "net6" "li_611_133#" 28.2715
+cap "sel1" "ng1" 7.6556
+cap "pg2" "m1_n1099_1625#" 1112.84
+cap "net3" "net4" 30.6658
+cap "sel3" "sel2" 7080.01
+cap "pg1" "pg0" 101.678
+cap "sel3" "ng2" 15.1539
+cap "vdd" "net5" 249.936
+cap "ng1" "sel2" 26.549
+cap "ng1" "ng2" 57.7228
+cap "sel1" "sel2" 6161.54
+cap "sel0" "vctrl" 523.352
+cap "pg1" "m1_n1099_1625#" 478.177
+cap "net4" "li_611_133#" 3.57049
+cap "a_879_204#" "li_611_133#" 11.55
+cap "ng0" "sel3" 17.0393
+cap "net3" "net5" 77.5585
+cap "sel3" "vdd" 2284.39
+cap "a_590_n694#" "ng3" 19.205
+cap "net2" "vdd" 2929.62
+cap "sel2" "ng2" 21.9918
+cap "ng0" "ng1" 113.773
+cap "pg3" "pg2" 301.72
+cap "ng1" "vdd" 4.00763
+cap "sel1" "ng0" 52.4429
+cap "sel1" "vdd" 1041.82
+cap "net3" "net2" 64.4913
+cap "li_611_133#" "net5" 25.3289
+cap "vdd" "li_n118_290#" 47.8032
+cap "a_589_1133#" "vdd" 51.7
+cap "net8" "net5" 159.767
+cap "vctrl" "ng3" 173.123
+cap "net7" "out" 100.159
+cap "ng0" "sel2" 22.2163
+cap "sel2" "vdd" 1653.24
+cap "net7" "vdd" 151.377
+cap "pg1" "pg3" 13.3403
+cap "vgp" "net5" 23
+cap "ng0" "ng2" 11.5226
+cap "vdd" "ng2" 3.89313
+cap "net3" "li_n118_290#" 12.1957
+cap "sel3" "pg0" 299.342
+cap "net2" "pg0" 143.754
+cap "net8" "net2" 27.8642
+cap "vgp" "sel3" 148.083
+cap "vgp" "net2" 35.6134
+cap "net8" "ng1" 0.93361
+cap "out" "vdd" 658.458
+cap "li_1179_n70#" "net6" 0.798387
+cap "ng0" "vdd" 3.89313
+cap "sel1" "pg0" 224.578
+cap "sel3" "m1_n1099_1625#" 2877.8
+cap "ng3" "m1_488_n269#" 0.609756
+cap "net7" "li_611_133#" 5.25334
+cap "sel2" "pg0" 218.342
+cap "net3" "vdd" 254.387
+cap "sel1" "m1_n1099_1625#" 821.237
+cap "a_590_n694#" "li_528_n678#" 25.2972
+cap "pg1" "pg2" 51.6756
+cap "sel2" "m1_n1099_1625#" 1213.1
+cap "vdd" "li_611_133#" 94.682
+cap "a_589_1133#" "li_523_1149#" 25.2972
+cap "net8" "ng0" 135.658
+cap "sel3" "pg3" 250.541
+cap "pg0" "vdd" 1183.63
+cap "net2" "pg3" 5.52
+cap "vgp" "vdd" 382.224
+cap "sel3" "vctrl" 281.048
+cap "sel0" "sel3" 785.479
+cap "net8" "net3" 53.7118
+cap "vdd" "m1_n1099_1625#" 3992.12
+cap "a_589_1133#" "pg3" 19.205
+cap "ng1" "vctrl" 387.107
+cap "sel1" "vctrl" 640.179
+cap "sel0" "sel1" 3544.74
+cap "sel2" "pg3" 9.13793
+cap "vdd" "li_523_1149#" 152.4
+cap "vctrl" "sel2" 311.671
+cap "sel0" "sel2" 1336.43
+cap "ng3" "li_528_n678#" 71.6688
+cap "vctrl" "ng2" 1046.55
+cap "net8" "vgp" 28.224
+cap "sel3" "pg2" 360.385
+cap "net2" "pg2" 0.944882
+cap "sel3" "ng3" 13.6627
+cap "pg3" "vdd" 1652.67
+cap "li_1179_n70#" "net7" 23.8335
+cap "pg0" "m1_n1099_1625#" 1657.78
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/selb" 24.3718
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/vss" 453.266
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_0/selb" 30.9974
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_1/sel" 103.004
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_0/selb" 42.962
+cap "sel2" "vco_switch_n_v2_0/selb" 35.26
+cap "vco_switch_n_v2_0/vss" "XM26/a_n76_n69#" 356.268
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/sel" 6.73021
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/selb" 149.335
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/out" 94.2427
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/out" 18.1424
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_0/sel" 27.295
+cap "sel2" "vco_switch_n_v2_0/sel" 18.8183
+cap "vco_switch_n_v2_0/vdd" "sel2" -67.6471
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/sel" 17.4878
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_0/out" 101.526
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_1/sel" -126.846
+cap "sel2" "vco_switch_n_v2_0/out" 137.717
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/out" 38.8126
+cap "sel2" "vco_switch_n_v2_0/vss" 27.9619
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/vss" 23.9984
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_1/selb" 3.51738
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/selb" 1.09235
+cap "vco_switch_n_v2_0/in" "sel3" 1.875
+cap "sel3" "vco_switch_n_v2_0/selb" 6.00852
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/out" 30.5942
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/selb" 66.5781
+cap "vco_switch_n_v2_0/in" "XM26/a_n76_n69#" 0.734364
+cap "sel3" "vco_switch_n_v2_0/sel" 7.72388
+cap "sel3" "vco_switch_n_v2_0/vdd" 162.947
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/sel" 19.2798
+cap "vco_switch_n_v2_0/vss" "XM16A/a_18_n29#" 14.7271
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/vdd" 26.1045
+cap "sel3" "vco_switch_n_v2_0/vss" 43.405
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/out" 147.165
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/selb" 45.6391
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_1/sel" 13.0806
+cap "vco_switch_n_v2_0/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "vco_switch_n_v2_0/vss" 10.4924
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_1/in" 53.9773
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_0/vss" 61.0551
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_2/out" 8.92483
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_2/out" 21.6825
+cap "XM26/a_n33_n157#" "XM16A/a_18_n29#" 5.80096
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_0/vss" 117.055
+cap "vco_switch_n_v2_1/out" "XM16A/a_18_n29#" 2.62195
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_0/vdd" 109.625
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_2/sel" 93.6304
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_2/sel" 37.1
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/out" 31.2911
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_1/sel" -66.0833
+cap "vco_switch_n_v2_2/sel" "XM16D_1/a_n33_n297#" 4.33268
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/out" 24.3622
+cap "vco_switch_n_v2_2/out" "vco_switch_n_v2_0/vss" 186.481
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_1/selb" 2.20213
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_0/vdd" 315.967
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_1/sel" 4.46782
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_1/in" 61.0788
+cap "vco_switch_n_v2_2/selb" "XM16D_1/a_n33_n297#" 38.3249
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_1/out" 21.6825
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/out" 30.5942
+cap "XM26/a_n76_n69#" "vco_switch_n_v2_0/vss" 14.8829
+cap "vco_switch_n_v2_0/vss" "XM16A/a_18_n29#" 911.399
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_1/in" 29.8724
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/vss" 3.20704
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_1/sel" 18.206
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_2/sel" 156.417
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/XM25/a_n76_n108#" 2.40773
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_0/vss" 51.6091
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_2/out" 146.722
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_0/vss" 143.608
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_1/in" -78.7494
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/vdd" 24.3718
+cap "vco_switch_n_v2_2/out" "XM16D_1/a_n33_n297#" 23.5919
+cap "vco_switch_n_v2_1/selb" "XM16A/a_18_n29#" 8.46918
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_1/in" 0.605381
+cap "XM16D_1/a_n33_n297#" "XM16A/a_18_n29#" 33.0122
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_1/sel" 15.1258
+cap "vco_switch_n_v2_2/out" "vco_switch_n_v2_2/sel" 32.5472
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_1/selb" 10.4577
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_2/sel" -124.488
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_1/sel" 7.77237
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_1/in" 173.574
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_2/out" 33.2831
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_1/selb" 33.0796
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_0/vdd" 24.3718
+cap "vco_switch_n_v2_1/out" "XM16D_1/a_n33_n297#" 8.92483
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_0/vss" 2.44978
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_1/in" 3.51738
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_0/vdd" 14.9311
+cap "vco_switch_n_v2_0/XM25/a_n33_67#" "vco_switch_n_v2_1/selb" 1.09235
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_1/sel" 75.4294
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_1/sel" 187.671
+cap "vco_switch_n_v2_0/out" "XM16A/a_18_n29#" 23.3374
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_1/in" 27.7607
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_2/sel" 164.363
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/vss" 49.619
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/vss" 1079.12
+cap "vco_switch_n_v2_0/vss" "XM16D_1/a_n33_n297#" 35.4191
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_2/selb" 63.3885
+cap "vco_switch_n_v2_2/sel" "vco_switch_n_v2_1/sel" 22.0351
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_0/out" 30.9991
+cap "vco_switch_n_v2_2/out" "XM16A/a_18_n29#" 1.29592
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_2/out" 94.2427
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/XM25/a_n76_n108#" 16.4475
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/XM25/a_n76_n108#" 3.51738
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/sel" 8.51746
+cap "vco_switch_n_v2_2/sel" "vco_switch_n_v2_0/vss" 14.45
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_0/out" 3.704
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_3/selb" 1.09235
+cap "vco_switch_n_v2_0/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "vco_switch_n_v2_1/sel" 0.909091
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_3/sel" 0.909091
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_3/in" 56.6746
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_3/sel" 162.075
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/XM25/a_n76_n108#" 3.51738
+cap "vco_switch_n_v2_2/XM25/a_n76_n108#" "vco_switch_n_v2_3/in" 2.70974
+cap "vco_switch_n_v2_2/vss" "vco_switch_n_v2_3/vdd" -5.68434e-14
+cap "vco_switch_n_v2_3/out" "vco_switch_n_v2_3/vdd" 79.3116
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/XM25/a_n76_n108#" 6.75692
+cap "vco_switch_n_v2_3/vdd" "vco_switch_n_v2_2/out" 14.9311
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_3/vdd" 24.3718
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_3/vdd" 130.659
+cap "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "vco_switch_n_v2_2/vss" 5.42299
+cap "vco_switch_n_v2_3/out" "vco_switch_n_v2_2/vss" 3.61204
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_3/vdd" -118.415
+cap "vco_switch_n_v2_2/vss" "vco_switch_n_v2_2/out" 13.118
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/XM25/a_n33_67#" 1.09235
+cap "vco_switch_n_v2_2/XM25/a_n76_n108#" "vco_switch_n_v2_3/vdd" 2.40773
+cap "vco_switch_n_v2_2/vss" "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 3.20704
+cap "vco_switch_n_v2_3/out" "vco_switch_n_v2_3/in" 72.2544
+cap "vco_switch_n_v2_2/vss" "vco_switch_n_v2_3/in" -7.3
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_3/out" 20.6506
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_2/out" 0.38961
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/out" 31.2911
+cap "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "vco_switch_n_v2_3/sel" 0.909091
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_3/out" 13.4311
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/vss" -6.19138
+cap "vco_switch_n_v2_2/vss" "vco_switch_n_v2_2/XM25/a_n76_n108#" 2.44978
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/out" 13.0236
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 4.44805
+cap "XM1/a_n33_n241#" "XM4/a_15_n96#" 0.38484
+cap "vss" "XM1/a_n33_n241#" 3.58542
+cap "XM16A/a_18_n29#" "XM1/a_n73_n144#" 5.67628
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "XM1/w_n109_n244#" 3.06251
+cap "XM1/a_15_n144#" "XM4/a_15_n96#" -2.19397
+cap "XM26/a_n76_n69#" "sel3" 8.00752
+cap "sel1" "XM1/w_n109_n244#" 11.0635
+cap "XM1/a_15_n144#" "vss" 7.1465
+cap "XM1/a_n73_n144#" "XM1/a_n33_n241#" 16.7192
+cap "XM1/a_15_n144#" "XM1/a_n73_n144#" -45.394
+cap "XM1/a_15_n144#" "XM16A/a_18_n29#" -34.4228
+cap "XM1/a_15_n144#" "XM1/a_n33_n241#" 52.8243
+cap "XM11A/a_n33_55#" "XM1/w_n109_n244#" 0.814714
+cap "XM3/a_n73_n64#" "XM1/a_n73_n144#" -0.249057
+cap "vco_switch_p_0/sel" "XM1/w_n109_n244#" 0.189112
+cap "XM26/a_n76_n69#" "XM1/w_n109_n244#" 370.212
+cap "sel2" "XM1/w_n109_n244#" 23.2979
+cap "XM1/a_n73_n144#" "XM1/w_n109_n244#" -22.6368
+cap "XM26/a_n76_n69#" "vco_switch_p_0/sel" 1.94792
+cap "XM26/a_n76_n69#" "vss" 1.65
+cap "vss" "XM26/a_18_n69#" 1.65
+cap "XM26/a_n76_n69#" "XMDUM16/a_n76_n209#" 0.0019407
+cap "XM4/a_n73_n96#" "XM16A/a_18_n29#" -0.371622
+cap "XM1/a_n33_n241#" "XM1/w_n109_n244#" -5.07346
+cap "XM4/a_n73_n96#" "XM1/a_n33_n241#" 0.0962099
+cap "XM1/a_15_n144#" "XM1/w_n109_n244#" -22.4633
+cap "XM3/a_15_n64#" "XM1/a_15_n144#" -3.63416
+cap "sel3" "XM1/w_n109_n244#" 32.6677
+cap "vss" "XMDUM26/a_n76_n69#" 3.3
+cap "vss" "XMDUM26B/a_n76_n69#" 3.3
+cap "XM16A/a_18_n29#" "vss" 8.25
+cap "XM1/a_n73_n144#" "XM1/a_n33_n241#" 7.5302
+cap "XM1/a_n33_n241#" "XM13/a_n33_142#" 11.8249
+cap "vco_switch_p_1/sel" "XM1/w_n109_n244#" 2.15003
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "XM1/w_n109_n244#" 3.06761
+cap "XM13/a_n33_142#" "XM16D_2/a_18_n209#" 5.38542
+cap "XM13/a_15_n120#" "XM1/w_n109_n244#" 61.4609
+cap "XM16A/a_18_n29#" "XM3/a_15_n64#" 8.37613
+cap "XMDUM16B/a_n76_n209#" "XM1/a_n33_n241#" 17.2928
+cap "XMDUM16B/a_n76_n209#" "XM16D_2/a_18_n209#" 77.752
+cap "XM13/a_n33_142#" "XM24/a_18_n129#" 2.96029
+cap "vss" "XM13/a_n33_142#" 10.6825
+cap "XM1/a_n33_n241#" "XM1/a_15_n144#" 36.4137
+cap "XM1/a_15_n144#" "XM16D_2/a_18_n209#" 0.2489
+cap "XM11D_1/a_n33_235#" "XM1/w_n109_n244#" -192.147
+cap "XMDUM16/a_n76_n209#" "XM1/a_15_n144#" 9.80153
+cap "XM26/a_n76_n69#" "XM1/w_n109_n244#" 70.7604
+cap "XM11C/a_n33_235#" "XM11D_1/a_n33_235#" 19.3062
+cap "XM24/a_n76_n129#" "XM13/a_n33_142#" 9.37965
+cap "XM1/a_n33_n241#" "XM16D_2/a_18_n209#" 24.544
+cap "vss" "XMDUM16B/a_n76_n209#" 120.403
+cap "XM11D_1/a_n33_235#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 0.508562
+cap "XM26/a_n76_n69#" "XM11C/a_n33_235#" 4.41593
+cap "XMDUM16/a_n33_n297#" "XM16A/a_18_n29#" 16.7825
+cap "XM16A/a_n33_n117#" "XM1/a_15_n144#" 2.14552
+cap "vss" "XM1/a_15_n144#" 0.825
+cap "XM16C/a_18_n209#" "XMDUM16B/a_n76_n209#" 35.9202
+cap "XM1/a_n73_n144#" "XM1/w_n109_n244#" 1347.19
+cap "XM13/a_n33_142#" "XM1/w_n109_n244#" 26.0783
+cap "XM13/a_n73_n120#" "XM13/a_n33_142#" 44.2393
+cap "XM1/a_n73_n144#" "XM11C/a_n33_235#" 15.9992
+cap "XM26/a_n76_n69#" "XM11A/a_n33_55#" 31.262
+cap "vss" "XM1/a_n33_n241#" 104.363
+cap "vss" "XM16D_2/a_18_n209#" 85.6259
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "XM11D_1/a_n33_235#" 0.55618
+cap "XM11B/a_n33_115#" "XM1/w_n109_n244#" -4.55551
+cap "XMDUM16B/a_n76_n209#" "XM1/w_n109_n244#" 7.50227
+cap "XMDUM16B/a_n76_n209#" "XM13/a_n73_n120#" 17.7442
+cap "XMDUM16/a_n76_n209#" "vss" 37.4
+cap "XM26/a_n76_n69#" "vco_switch_p_1/sel" 1.48454
+cap "XM1/a_n73_n144#" "XM3/a_15_n64#" 3.22347
+cap "XM11C/a_n33_235#" "XM11B/a_n33_115#" 10.3669
+cap "XM3/a_15_n64#" "XM13/a_n33_142#" 0.192737
+cap "XM1/a_n73_n144#" "XM11A/a_n33_55#" 26.0774
+cap "XM1/a_n73_n144#" "XM16A/a_18_n29#" 1.79808
+cap "XM16C/a_18_n209#" "XM1/a_n33_n241#" 8.83465
+cap "XM16C/a_18_n209#" "XM16D_2/a_18_n209#" 65.0634
+cap "XM16A/a_n76_n29#" "XM16D_2/a_18_n209#" 2.02342
+cap "XM24/a_n76_n129#" "XM1/a_n33_n241#" 1.05413
+cap "XM1/a_15_n144#" "XM1/w_n109_n244#" 46.4692
+cap "vss" "XM24/a_18_n129#" 2.71978
+cap "XMDUM16/a_n76_n209#" "XM16A/a_n76_n29#" 12.5306
+cap "XM16C/a_n33_n297#" "a_590_n694#" 5.75368
+cap "XM16A/a_n33_n117#" "vss" 3.58224
+cap "XM11A/a_n33_55#" "XM11B/a_n33_115#" 3.71694
+cap "XM1/a_n33_n241#" "XM1/w_n109_n244#" 118.806
+cap "XM1/a_n33_n241#" "XM13/a_n73_n120#" 2.28145
+cap "XM13/a_n73_n120#" "XM16D_2/a_18_n209#" 6.87126
+cap "XM16D_2/a_18_n209#" "XM1/w_n109_n244#" 14.2773
+cap "XMDUM16B/a_n76_n209#" "XM16A/a_18_n29#" 77.8241
+cap "XM11C/a_n33_235#" "vco_switch_p_2/sel" 2.26133
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 19.6055
+cap "XM16C/a_18_n209#" "vss" 37.4
+cap "XM3/a_15_n64#" "XM1/a_15_n144#" 43.2961
+cap "vss" "XM16A/a_n76_n29#" 9.77141
+cap "XM24/a_n76_n129#" "vss" 3.66667
+cap "XM16A/a_18_n29#" "XM1/a_15_n144#" 2.86733
+cap "XM16C/a_18_n209#" "XM16A/a_n76_n29#" 3.21316
+cap "XM1/a_n33_n241#" "XM3/a_15_n64#" 64.4646
+cap "XM13/a_15_n120#" "XMDUM16B/a_n76_n209#" 8.65096
+cap "XM1/a_n73_n144#" "XM11D_1/a_n33_235#" 41.8398
+cap "XM3/a_15_n64#" "XM16D_2/a_18_n209#" 6.90148
+cap "vss" "XM13/a_n73_n120#" 10.1912
+cap "XM16C/a_n33_n297#" "XM3/a_15_n64#" 2.59677
+cap "vss" "XM1/w_n109_n244#" 3.71523
+cap "XM1/a_n33_n241#" "XM16A/a_18_n29#" 4.41732
+cap "XM16A/a_18_n29#" "XM16D_2/a_18_n209#" 122.226
+cap "XM16C/a_n33_n297#" "XM16A/a_18_n29#" 16.993
+cap "vco_switch_p_1/sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "XM1/a_n73_n144#" 0.815407
+cap "XM1/a_n73_n144#" "XM26/a_n76_n69#" 1.22185
+cap "XMDUM16B/a_n33_n297#" "XM1/a_n33_n241#" 2.92292
+cap "XMDUM16/a_n76_n209#" "XM16A/a_18_n29#" 60.5534
+cap "XM11B/a_n33_115#" "XM11D_1/a_n33_235#" 4.40674
+cap "XMDUM16/a_n33_n297#" "XM1/a_15_n144#" 1.77976
+cap "XM23/a_n78_n220#" "XM1/w_n109_n244#" 11.5274
+cap "XM13/a_15_n120#" "XM1/a_n33_n241#" 0.212704
+cap "XM26/a_n76_n69#" "XM11B/a_n33_115#" 10.474
+cap "vss" "XM3/a_15_n64#" 25.7281
+cap "vss" "XM16A/a_18_n29#" 66.0926
+cap "XM1/a_n73_n144#" "XM11B/a_n33_115#" -0.549465
+cap "XM3/a_15_n64#" "XM16A/a_n76_n29#" 3.33929
+cap "XM16C/a_18_n209#" "XM16A/a_18_n29#" 96.9346
+cap "XM11C/a_n33_235#" "XM1/w_n109_n244#" -44.3169
+cap "XM16A/a_18_n29#" "XM16A/a_n76_n29#" 9.12566
+cap "XM11D_1/a_n33_235#" "vco_switch_p_2/sel" 1.94792
+cap "XMDUM16B/a_n76_n209#" "XM13/a_n33_142#" 1.52489
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "XM1/w_n109_n244#" 1.33913
+cap "XM3/a_15_n64#" "a_590_n694#" 3.21505
+cap "vss" "XM13/a_15_n120#" 0.846154
+cap "XM16A/a_18_n29#" "a_590_n694#" 16.7825
+cap "XM1/a_n73_n144#" "XM1/a_15_n144#" 5.09259
+cap "ng1" "XM16A/a_18_n29#" -0.293734
+cap "XM3/a_15_n64#" "XM1/w_n109_n244#" -7.40527
+cap "XMDUM16B/a_n33_n297#" "a_590_n694#" 5.75368
+cap "XMDUM16/a_n76_n209#" "XM26/a_n76_n69#" 0.0019407
+cap "XM11A/a_n33_55#" "XM1/w_n109_n244#" 48.6013
+cap "XM11B/a_n33_115#" "vco_switch_p_1/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" 3.05977
+cap "XM1/a_n73_n144#" "vco_switch_p_2/sel" 1.30645
+cap "XM24/a_n76_n129#" "XM21/a_n15_n53#" 1.05413
+cap "XM13/a_n73_n120#" "XM21/a_n15_n53#" 2.28145
+cap "XM13/a_15_n120#" "XM13/a_n73_n120#" 3.40206
+cap "XM13/a_15_n120#" "XM24/a_n76_n129#" 228.678
+cap "XM13/a_n33_142#" "XM21/a_n15_n53#" 6.24162
+cap "XM5/w_n109_n298#" "XM13/a_15_n120#" 335.966
+cap "XM13/a_n33_142#" "XM13/a_15_n120#" 70.6166
+cap "vss" "XM13/a_n73_n120#" 10.1912
+cap "vss" "XM24/a_n76_n129#" 3.66667
+cap "XM24/a_18_n129#" "XM13/a_15_n120#" 291.505
+cap "XM13/a_n33_142#" "XM5/a_n33_395#" 0.192737
+cap "XM24/a_18_n129#" "vss" 2.71978
+cap "XM13/a_n73_n120#" "XM16D_2/a_18_n209#" 6.87126
+cap "XM5/w_n109_n298#" "XM13/a_n73_n120#" 15.2444
+cap "XM24/a_n76_n129#" "XM13/a_n73_n120#" 92.2113
+cap "XM5/w_n109_n298#" "XM24/a_n76_n129#" 6.80625
+cap "XM13/a_n33_142#" "XM13/a_n73_n120#" 113.734
+cap "XM5/w_n109_n298#" "XM13/a_n33_142#" -30.4529
+cap "XM13/a_15_n120#" "XMDUM16B/a_n76_n209#" 8.65096
+cap "XM13/a_n33_142#" "XM24/a_n76_n129#" 16.4928
+cap "XM13/a_15_n120#" "XM21/a_n15_n53#" 0.212704
+cap "XM24/a_18_n129#" "XM13/a_n73_n120#" 31.2366
+cap "XM5/w_n109_n298#" "XM24/a_18_n129#" 160.216
+cap "XM24/a_18_n129#" "XM24/a_n76_n129#" 3.33511
+cap "XM13/a_n33_142#" "XM24/a_18_n129#" 6.02695
+cap "vss" "XM13/a_15_n120#" 0.846154
+cap "XMDUM16B/a_n76_n209#" "XM13/a_n73_n120#" 17.7442
+cap "XM13/a_n33_142#" "XM5/a_n73_n236#" 0.637807
+cap "XM13/a_n33_142#" "XMDUM16B/a_n76_n209#" 1.375
+cap "vco_switch_p_0/vss" "XM11A/a_n33_55#" 49.7301
+cap "vco_switch_p_0/sel" "vco_switch_p_0/vss" 30.3946
+cap "vco_switch_p_0/selb" "XMDUM11/a_n33_235#" 18.5451
+cap "sel3" "XMDUM11/a_n33_235#" 267.409
+cap "XMDUM11/a_n33_235#" "XM25/a_n33_95#" 54.6323
+cap "vco_switch_p_1/selb" "XM11A/a_n33_55#" 26.9504
+cap "sel2" "vco_switch_p_0/selb" 16.58
+cap "vco_switch_p_1/sel" "XM25/a_n33_95#" 106.623
+cap "vco_switch_p_0/selb" "vco_switch_p_1/sel" 145.127
+cap "XM11A/a_n33_55#" "XM25/a_n33_95#" 222.216
+cap "vco_switch_p_0/selb" "XM11A/a_n33_55#" 7.0055
+cap "vco_switch_p_0/sel" "XM25/a_n33_95#" 44.9392
+cap "vco_switch_p_0/sel" "vco_switch_p_0/selb" 17.2205
+cap "vco_switch_p_0/sel" "sel3" 31.4715
+cap "vco_switch_p_1/sel" "XMDUM11/a_n33_235#" -138.486
+cap "sel2" "XMDUM11/a_n33_235#" -157.835
+cap "XMDUM11/a_n33_235#" "XM11A/a_n33_55#" 22.0896
+cap "vco_switch_p_0/sel" "XMDUM11/a_n33_235#" 7.92187
+cap "vco_switch_p_0/vss" "XM25/a_n33_95#" 10.1664
+cap "vco_switch_p_0/vss" "vco_switch_p_0/selb" 7.48
+cap "sel2" "XM11A/a_n33_55#" 137.717
+cap "vco_switch_p_0/sel" "sel2" 316.809
+cap "vco_switch_p_1/sel" "XM11A/a_n33_55#" 87.7161
+cap "vco_switch_p_0/sel" "vco_switch_p_1/sel" 57.1232
+cap "vco_switch_p_1/selb" "XM25/a_n33_95#" 3.51738
+cap "vco_switch_p_1/selb" "vco_switch_p_0/selb" 1.09235
+cap "vco_switch_p_0/sel" "XM11A/a_n33_55#" 32.5749
+cap "vco_switch_p_1/selb" "XMDUM11/a_n33_235#" 0.205607
+cap "vco_switch_p_0/selb" "XM25/a_n33_95#" 6.39406
+cap "vco_switch_p_0/selb" "sel3" 11.8123
+cap "vco_switch_p_3/sel" "XM25/a_n33_95#" 126.654
+cap "vco_switch_p_1/selb" "vco_switch_p_3/sel" 11.8123
+cap "XM11C/a_n33_235#" "vco_switch_p_1/out" 12.1418
+cap "vco_switch_p_1/sel" "XMDUM11/a_n33_235#" -92.8854
+cap "vco_switch_p_1/selb" "XM11/a_n76_n96#" 0.815407
+cap "XMDUM11/a_n33_235#" "XM11D_1/a_n33_235#" -215.551
+cap "vco_switch_p_2/sel" "XM11C/a_n33_235#" 66.6129
+cap "XM11C/a_n33_235#" "XM11C/a_n76_n276#" 0.695876
+cap "XM25/a_n33_95#" "XM11/a_n76_n96#" 0.795643
+cap "vco_switch_p_0/vss" "XM11A/a_n33_55#" 13.118
+cap "vco_switch_p_2/selb" "XMDUM11/a_n33_235#" 20.2248
+cap "XM11A/a_n33_55#" "XM25/a_n33_95#" 34.5663
+cap "vco_switch_p_2/sel" "XM11D_1/a_18_n276#" 1.30645
+cap "XM11A/a_n33_55#" "vco_switch_p_1/selb" 26.9504
+cap "vco_switch_p_3/sel" "XM11C/a_n33_235#" 120.826
+cap "XMDUM11/a_n33_235#" "XM25/a_n33_95#" -127.703
+cap "vco_switch_p_1/selb" "XMDUM11/a_n33_235#" 17.409
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" "vco_switch_p_1/sel" 3.11143
+cap "vco_switch_p_2/sel" "vco_switch_p_1/out" 265.655
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "XMDUM11/a_n33_235#" 2.40773
+cap "vco_switch_p_1/sel" "vco_switch_p_0/sel" 4.78875
+cap "XMDUM11/a_n33_235#" "XM11C/a_n33_235#" 13.5906
+cap "vco_switch_p_2/selb" "XM11D_1/a_n33_235#" 10.0903
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" "vco_switch_p_1/selb" 1.09235
+cap "vco_switch_p_2/sel" "vco_switch_p_3/sel" 52.0786
+cap "vco_switch_p_1/sel" "vco_switch_p_1/selb" 110.605
+cap "vco_switch_p_0/vss" "vco_switch_p_1/sel" 21.4801
+cap "XM11D_1/a_18_n276#" "XMDUM11/a_n33_235#" 8.50219
+cap "vco_switch_p_3/selb" "XMDUM11/a_n33_235#" 0.205607
+cap "XMDUM11/a_n33_235#" "XM11B/a_18_n156#" 6.08829
+cap "vco_switch_p_0/vss" "vco_switch_p_0/sel" 3.20704
+cap "vco_switch_p_1/sel" "XM25/a_n33_95#" 138.329
+cap "vco_switch_p_0/sel" "XM25/a_n33_95#" 0.605381
+cap "vco_switch_p_2/selb" "vco_switch_p_0/vss" 7.48
+cap "vco_switch_p_2/selb" "vco_switch_p_1/selb" 2.20213
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_1/sel" 11.3917
+cap "vco_switch_p_2/selb" "XM25/a_n33_95#" 7.10155
+cap "vco_switch_p_0/vss" "vco_switch_p_1/selb" 7.48
+cap "vco_switch_p_0/vss" "XM25/a_n33_95#" 7.00951
+cap "XMDUM11/a_n33_235#" "vco_switch_p_1/out" 40.8242
+cap "vco_switch_p_1/selb" "XM25/a_n33_95#" 3.66243
+cap "XM11C/a_n33_235#" "XM11D_1/a_n33_235#" 13.9838
+cap "vco_switch_p_1/sel" "vco_switch_p_0/sel" 6.27151
+cap "vco_switch_p_2/sel" "XMDUM11/a_n33_235#" -312.27
+cap "XMDUM11/a_n33_235#" "XM11C/a_n76_n276#" 7.64761
+cap "vco_switch_p_0/vss" "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 2.44978
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "XM25/a_n33_95#" 16.4475
+cap "XM11D_1/a_18_n276#" "XM11D_1/a_n33_235#" 8.71698
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_1/selb" 3.51738
+cap "vco_switch_p_2/selb" "XM11C/a_n33_235#" 21.492
+cap "vco_switch_p_0/vss" "XM11C/a_n33_235#" 49.7301
+cap "vco_switch_p_2/selb" "vco_switch_p_3/selb" 1.09235
+cap "XMDUM11/a_n33_235#" "vco_switch_p_3/sel" 547.249
+cap "XMDUM11/a_n33_235#" "XM11/a_n76_n96#" 10.9741
+cap "XM11C/a_n33_235#" "XM25/a_n33_95#" 240.888
+cap "vco_switch_p_1/sel" "vco_switch_p_1/out" 32.586
+cap "vco_switch_p_3/selb" "XM25/a_n33_95#" 3.51738
+cap "XM11D_1/a_n33_235#" "vco_switch_p_1/out" 4.93372
+cap "XM11A/a_n33_55#" "XMDUM11/a_n33_235#" 17.9901
+cap "vco_switch_p_2/selb" "vco_switch_p_1/out" 54.5484
+cap "vco_switch_p_2/sel" "XM11D_1/a_n33_235#" 29.5171
+cap "vco_switch_p_2/sel" "vco_switch_p_1/sel" 330.23
+cap "vco_switch_p_0/vss" "vco_switch_p_1/out" 63.1957
+cap "vco_switch_p_2/sel" "vco_switch_p_2/selb" 57.9939
+cap "vco_switch_p_1/out" "XM25/a_n33_95#" 258.937
+cap "vco_switch_p_1/sel" "vco_switch_p_3/sel" 31.4715
+cap "vco_switch_p_1/selb" "vco_switch_p_1/out" 21.3624
+cap "vco_switch_p_2/sel" "vco_switch_p_0/vss" 17.6377
+cap "vco_switch_p_2/sel" "vco_switch_p_1/selb" 22.8567
+cap "vco_switch_p_3/selb" "XM11C/a_n33_235#" 26.9504
+cap "vco_switch_p_2/sel" "XM25/a_n33_95#" 165.371
+cap "vco_switch_p_2/selb" "vco_switch_p_3/sel" 18.0352
+cap "vco_switch_p_1/sel" "XM11A/a_n33_55#" 61.9841
+cap "vco_switch_p_0/vss" "vco_switch_p_3/sel" 4.6118
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/selb" 0.205607
+cap "vco_switch_p_3/out" "vco_switch_p_3/in" 72.2544
+cap "vco_switch_p_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "vco_switch_p_3/sel" 4.44805
+cap "vco_switch_p_3/in" "vco_switch_p_2/out" 0.38961
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_3/in" 2.70974
+cap "vco_switch_p_3/in" "vco_switch_p_3/sel" 56.6746
+cap "vco_switch_p_2/vss" "vco_switch_p_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 3.20704
+cap "vco_switch_p_3/out" "vco_switch_p_3/sel" 13.4311
+cap "vco_switch_p_3/sel" "vco_switch_p_2/out" 14.3666
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/in" 109.026
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_3/sel" 6.75692
+cap "vco_switch_p_3/selb" "vco_switch_p_2/out" 26.9504
+cap "vco_switch_p_2/sel" "vco_switch_p_3/sel" 1.09524
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/out" 30.0199
+cap "XM11D_2/a_18_n276#" "vco_switch_p_2/out" 14.9311
+cap "vco_switch_p_3/out" "vco_switch_p_2/vss" 3.61204
+cap "vco_switch_p_2/vss" "vco_switch_p_2/out" 13.118
+cap "vco_switch_p_3/selb" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" 1.09235
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_3/selb" 3.51738
+cap "vco_switch_p_3/selb" "vco_switch_p_3/sel" 136.122
+cap "XM11D_2/a_18_n276#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 2.40773
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/sel" -320.085
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_2/vss" 2.44978
+cap "vco_switch_p_2/vss" "vco_switch_p_3/sel" -6.19138
+merge "XM16C/a_n33_n297#" "vco_switch_n_v2_2/out" -175.458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48438 -276 46440 0 0 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_2/out" "ng2"
+merge "vco_switch_p_0/out" "XM11A/a_n33_55#" -116.482 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44862 -276 0 0 0 0 0 0 0 0 0 0
+merge "XM11A/a_n33_55#" "pg0"
+merge "XM5/a_n33_395#" "XM3/a_15_n64#" -204.668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -150549 -610 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_15_n64#" "li_n118_290#"
+merge "li_n118_290#" "XM6/a_n33_135#"
+merge "XM6/a_n33_135#" "XM4/a_15_n96#"
+merge "XM4/a_15_n96#" "net4"
+merge "XM16D_2/a_n76_n209#" "XM16D_1/a_n76_n209#" -181.6 0 0 0 0 0 0 0 0 -1392 -1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25896 -1270 -16802 -1114 0 0 0 0 0 0 0 0 0 0
+merge "XM16D_1/a_n76_n209#" "XM16C/a_n76_n209#"
+merge "XM16C/a_n76_n209#" "XM16B/a_n76_n89#"
+merge "XM16B/a_n76_n89#" "XM2/a_n73_n103#"
+merge "XM2/a_n73_n103#" "XM16/a_18_n29#"
+merge "XM16/a_18_n29#" "XM16A/a_18_n29#"
+merge "XM16A/a_18_n29#" "net8"
+merge "XM23/a_63_n366#" "XM23/a_n33_310#" -303.424 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13926 -264 0 0 -89150 -1046 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n33_310#" "XM23/a_n129_n366#"
+merge "XM23/a_n129_n366#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "li_1179_712#"
+merge "li_1179_712#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "li_1179_n70#"
+merge "li_1179_n70#" "net7"
+merge "vco_switch_p_3/out" "XM11D_2/a_n33_235#" 218.944 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -952 -264 0 0 7888 -400 12136 -484 -6567 -552 2802 -120 0 0 0 0 0 0
+merge "XM11D_2/a_n33_235#" "XM11D_1/a_n33_235#"
+merge "XM11D_1/a_n33_235#" "pg3"
+merge "pg3" "li_523_1149#"
+merge "li_523_1149#" "a_589_1133#"
+merge "vco_switch_p_3/in" "vco_switch_p_2/in" -393.433 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -153943 -1610 -81974 0 -57429 0 0 0 0 0 0 0
+merge "vco_switch_p_2/in" "vco_switch_p_1/in"
+merge "vco_switch_p_1/in" "vco_switch_p_0/in"
+merge "vco_switch_p_0/in" "XM11/a_n33_55#"
+merge "XM11/a_n33_55#" "XM25/a_n76_n136#"
+merge "XM25/a_n76_n136#" "XM25/a_n33_95#"
+merge "XM25/a_n33_95#" "m1_n1099_1625#"
+merge "m1_n1099_1625#" "XM26/a_n76_n69#"
+merge "XM26/a_n76_n69#" "vgp"
+merge "vco_switch_p_3/vss" "vco_switch_p_2/vss" -5614.99 0 0 0 0 0 0 0 0 0 0 -79174 -5364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11632 -6104 -146841 -16060 9336 -190 -137100 -2966 0 0 0 0 0 0
+merge "vco_switch_p_2/vss" "XMDUM11B/VSUBS"
+merge "XMDUM11B/VSUBS" "XM23/VSUBS"
+merge "XM23/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "XM12/VSUBS"
+merge "XM12/VSUBS" "XM11D_2/VSUBS"
+merge "XM11D_2/VSUBS" "XM11D_1/VSUBS"
+merge "XM11D_1/VSUBS" "XM11C/VSUBS"
+merge "XM11C/VSUBS" "XM5/VSUBS"
+merge "XM5/VSUBS" "XM11/VSUBS"
+merge "XM11/VSUBS" "XM11B/VSUBS"
+merge "XM11B/VSUBS" "vco_switch_p_1/vss"
+merge "vco_switch_p_1/vss" "vco_switch_p_0/vss"
+merge "vco_switch_p_0/vss" "XMDUM25B/VSUBS"
+merge "XMDUM25B/VSUBS" "XMDUM25/VSUBS"
+merge "XMDUM25/VSUBS" "XM25/VSUBS"
+merge "XM25/VSUBS" "XM11A/VSUBS"
+merge "XM11A/VSUBS" "XMDUM11/VSUBS"
+merge "XMDUM11/VSUBS" "XM3/VSUBS"
+merge "XM3/VSUBS" "XM1/VSUBS"
+merge "XM1/VSUBS" "XM22_0p42/VSUBS"
+merge "XM22_0p42/VSUBS" "XM22_0p42/a_n73_n80#"
+merge "XM22_0p42/a_n73_n80#" "XM6/VSUBS"
+merge "XM6/VSUBS" "XM6/a_n73_n175#"
+merge "XM6/a_n73_n175#" "XMDUM16B/VSUBS"
+merge "XMDUM16B/VSUBS" "XMDUM16B/a_n33_n297#"
+merge "XMDUM16B/a_n33_n297#" "XMDUM16B/a_18_n209#"
+merge "XMDUM16B/a_18_n209#" "XMDUM16B/a_n76_n209#"
+merge "XMDUM16B/a_n76_n209#" "XM24/VSUBS"
+merge "XM24/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM16D_2/VSUBS"
+merge "XM16D_2/VSUBS" "XM16D_2/a_18_n209#"
+merge "XM16D_2/a_18_n209#" "XM13/VSUBS"
+merge "XM13/VSUBS" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "XM16D_1/VSUBS"
+merge "XM16D_1/VSUBS" "XM16D_1/a_18_n209#"
+merge "XM16D_1/a_18_n209#" "m1_488_n269#"
+merge "m1_488_n269#" "XM16C/VSUBS"
+merge "XM16C/VSUBS" "XM16C/a_18_n209#"
+merge "XM16C/a_18_n209#" "XM16B/VSUBS"
+merge "XM16B/VSUBS" "XM16B/a_18_n89#"
+merge "XM16B/a_18_n89#" "vco_switch_n_v2_3/vss"
+merge "vco_switch_n_v2_3/vss" "vco_switch_n_v2_2/vss"
+merge "vco_switch_n_v2_2/vss" "XM4/VSUBS"
+merge "XM4/VSUBS" "XM4/a_n73_n96#"
+merge "XM4/a_n73_n96#" "XM2/VSUBS"
+merge "XM2/VSUBS" "XM16/VSUBS"
+merge "XM16/VSUBS" "XM16/a_n76_n29#"
+merge "XM16/a_n76_n29#" "XM16A/VSUBS"
+merge "XM16A/VSUBS" "XM16A/a_n76_n29#"
+merge "XM16A/a_n76_n29#" "XMDUM26B/VSUBS"
+merge "XMDUM26B/VSUBS" "XMDUM26B/a_n33_n157#"
+merge "XMDUM26B/a_n33_n157#" "XMDUM26B/a_18_n69#"
+merge "XMDUM26B/a_18_n69#" "XMDUM26B/a_n76_n69#"
+merge "XMDUM26B/a_n76_n69#" "XMDUM26/VSUBS"
+merge "XMDUM26/VSUBS" "XMDUM26/a_n33_n157#"
+merge "XMDUM26/a_n33_n157#" "XMDUM26/a_18_n69#"
+merge "XMDUM26/a_18_n69#" "XMDUM26/a_n76_n69#"
+merge "XMDUM26/a_n76_n69#" "XMDUM16/VSUBS"
+merge "XMDUM16/VSUBS" "XMDUM16/a_n33_n297#"
+merge "XMDUM16/a_n33_n297#" "XMDUM16/a_18_n209#"
+merge "XMDUM16/a_18_n209#" "XMDUM16/a_n76_n209#"
+merge "XMDUM16/a_n76_n209#" "XM26/VSUBS"
+merge "XM26/VSUBS" "XM26/a_18_n69#"
+merge "XM26/a_18_n69#" "vco_switch_n_v2_1/vss"
+merge "vco_switch_n_v2_1/vss" "vco_switch_n_v2_0/vss"
+merge "vco_switch_n_v2_0/vss" "vss"
+merge "vco_switch_p_0/sel" "vco_switch_n_v2_0/sel" -759.298 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -11852 -3076 0 0 0 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_0/sel" "sel0"
+merge "vco_switch_p_2/sel" "vco_switch_n_v2_2/sel" -642.351 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1966 -4014 610378 -1946 94960 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_2/sel" "sel2"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -100.555 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -79212 -366 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "li_1388_346#"
+merge "li_1388_346#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "XM11B/a_18_n156#" "XM11D_2/a_n76_n276#" 50.2964 0 0 0 0 0 0 0 0 0 0 -20532 -1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5934 -1334 33296 -1072 0 0 0 0 0 0 0 0 0 0
+merge "XM11D_2/a_n76_n276#" "XM11D_1/a_18_n276#"
+merge "XM11D_1/a_18_n276#" "XM11C/a_n76_n276#"
+merge "XM11C/a_n76_n276#" "XM11/a_n76_n96#"
+merge "XM11/a_n76_n96#" "XM11A/a_n76_n96#"
+merge "XM11A/a_n76_n96#" "XM1/a_n73_n144#"
+merge "XM1/a_n73_n144#" "net2"
+merge "XM23/a_18_n220#" "vco_switch_p_3/vdd" -6315.06 0 0 0 0 -2144258 -40352 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 550 -1698 -124954 -11198 142200 0 78100 0 0 0 0 0 0 0
+merge "vco_switch_p_3/vdd" "vco_switch_p_2/vdd"
+merge "vco_switch_p_2/vdd" "XM11B/a_n76_n156#"
+merge "XM11B/a_n76_n156#" "XMDUM11B/a_18_n276#"
+merge "XMDUM11B/a_18_n276#" "XMDUM11B/a_n76_n276#"
+merge "XMDUM11B/a_n76_n276#" "XMDUM11B/a_n33_235#"
+merge "XMDUM11B/a_n33_235#" "XMDUM11B/w_n112_n338#"
+merge "XMDUM11B/w_n112_n338#" "XM23/a_n173_n220#"
+merge "XM23/a_n173_n220#" "XM23/w_n209_n320#"
+merge "XM23/w_n209_n320#" "XM21/a_n72_n22#"
+merge "XM21/a_n72_n22#" "XM21/w_n109_n58#"
+merge "XM21/w_n109_n58#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XM12/w_n109_n340#"
+merge "XM12/w_n109_n340#" "XM11D_2/a_18_n276#"
+merge "XM11D_2/a_18_n276#" "XM11D_2/w_n112_n338#"
+merge "XM11D_2/w_n112_n338#" "XM11D_1/a_n76_n276#"
+merge "XM11D_1/a_n76_n276#" "XM11D_1/w_n112_n338#"
+merge "XM11D_1/w_n112_n338#" "XM11C/a_18_n276#"
+merge "XM11C/a_18_n276#" "XM11C/w_n112_n338#"
+merge "XM11C/w_n112_n338#" "XM5/a_15_n236#"
+merge "XM5/a_15_n236#" "XM5/w_n109_n298#"
+merge "XM5/w_n109_n298#" "XM11/a_18_n96#"
+merge "XM11/a_18_n96#" "XM11/w_n112_n158#"
+merge "XM11/w_n112_n158#" "XM11B/w_n112_n218#"
+merge "XM11B/w_n112_n218#" "vco_switch_p_1/vdd"
+merge "vco_switch_p_1/vdd" "vco_switch_p_0/vdd"
+merge "vco_switch_p_0/vdd" "XMDUM25B/a_18_n136#"
+merge "XMDUM25B/a_18_n136#" "XMDUM25B/a_n76_n136#"
+merge "XMDUM25B/a_n76_n136#" "XMDUM25B/a_n33_95#"
+merge "XMDUM25B/a_n33_95#" "XMDUM25B/w_n112_n198#"
+merge "XMDUM25B/w_n112_n198#" "XMDUM25/a_18_n136#"
+merge "XMDUM25/a_18_n136#" "XMDUM25/a_n76_n136#"
+merge "XMDUM25/a_n76_n136#" "XMDUM25/a_n33_95#"
+merge "XMDUM25/a_n33_95#" "XMDUM25/w_n112_n198#"
+merge "XMDUM25/w_n112_n198#" "XM25/a_18_n136#"
+merge "XM25/a_18_n136#" "XM25/w_n112_n198#"
+merge "XM25/w_n112_n198#" "XM11A/a_18_n96#"
+merge "XM11A/a_18_n96#" "XM11A/w_n112_n158#"
+merge "XM11A/w_n112_n158#" "XMDUM11/a_18_n276#"
+merge "XMDUM11/a_18_n276#" "XMDUM11/a_n76_n276#"
+merge "XMDUM11/a_n76_n276#" "XMDUM11/a_n33_235#"
+merge "XMDUM11/a_n33_235#" "XMDUM11/w_n112_n338#"
+merge "XMDUM11/w_n112_n338#" "XM3/a_n73_n64#"
+merge "XM3/a_n73_n64#" "XM3/w_n109_n164#"
+merge "XM3/w_n109_n164#" "XM1/w_n109_n244#"
+merge "XM1/w_n109_n244#" "vco_switch_n_v2_3/vdd"
+merge "vco_switch_n_v2_3/vdd" "vco_switch_n_v2_2/vdd"
+merge "vco_switch_n_v2_2/vdd" "vco_switch_n_v2_1/vdd"
+merge "vco_switch_n_v2_1/vdd" "vco_switch_n_v2_0/vdd"
+merge "vco_switch_n_v2_0/vdd" "vdd"
+merge "XM5/a_n73_n236#" "XM21/a_n15_n53#" -123.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 216 -124 0 0 -1872 -888 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM21/a_n15_n53#" "a_879_204#"
+merge "a_879_204#" "XM1/a_n33_n241#"
+merge "XM1/a_n33_n241#" "XM22_0p42/a_n33_33#"
+merge "XM22_0p42/a_n33_33#" "XM6/a_15_n175#"
+merge "XM6/a_15_n175#" "li_611_133#"
+merge "li_611_133#" "XM2/a_n33_63#"
+merge "XM2/a_n33_63#" "net5"
+merge "vco_switch_n_v2_3/in" "vco_switch_n_v2_2/in" -1660.88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -965446 -1300 -407636 0 51678 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_2/in" "XM16/a_n33_n117#"
+merge "XM16/a_n33_n117#" "XM26/a_n33_n157#"
+merge "XM26/a_n33_n157#" "vco_switch_n_v2_1/in"
+merge "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/in"
+merge "vco_switch_n_v2_0/in" "vctrl"
+merge "vco_switch_p_3/sel" "vco_switch_n_v2_3/sel" -574.659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14458 -3912 444637 -1774 -147658 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_3/sel" "sel3"
+merge "XM3/a_n33_n161#" "XM1/a_15_n144#" -180.416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 57236 -1156 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_15_n144#" "XM4/a_n33_33#"
+merge "XM4/a_n33_33#" "XM2/a_15_n103#"
+merge "XM2/a_15_n103#" "net3"
+merge "XM21/a_15_n22#" "XM12/a_n33_n337#" -89.3578 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 102 -166 0 0 -14844 -456 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM12/a_n33_n337#" "XM13/a_n33_142#"
+merge "XM13/a_n33_142#" "XM22_0p42/a_15_n80#"
+merge "XM22_0p42/a_15_n80#" "net6"
+merge "XM16B/a_n33_n177#" "vco_switch_n_v2_1/out" -15.5485 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 66678 -278 112646 0 51282 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_1/out" "ng1"
+merge "vco_switch_p_1/sel" "vco_switch_n_v2_1/sel" -753.09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -41776 -3160 0 0 -74824 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_1/sel" "sel1"
+merge "vco_switch_n_v2_3/out" "XM16D_2/a_n33_n297#" -17.3778 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 78048 -900 0 0 8262 -384 -153436 -484 411636 0 75670 0 0 0 0 0 0 0
+merge "XM16D_2/a_n33_n297#" "XM16D_1/a_n33_n297#"
+merge "XM16D_1/a_n33_n297#" "ng3"
+merge "ng3" "li_528_n678#"
+merge "li_528_n678#" "a_590_n694#"
+merge "vco_switch_p_2/out" "XM11C/a_n33_235#" -147.896 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2464 -276 -99428 0 -111643 0 0 0 0 0 0 0
+merge "XM11C/a_n33_235#" "pg2"
+merge "vco_switch_p_1/out" "XM11B/a_n33_115#" -94.1707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2736 -278 0 0 0 0 0 0 0 0 0 0
+merge "XM11B/a_n33_115#" "pg1"
+merge "XM16A/a_n33_n117#" "vco_switch_n_v2_0/out" -214.079 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -15598 -276 0 0 0 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_0/out" "ng0"
diff --git a/mag/3-stage_cs-vco_dp9/.magicrc b/mag/3-stage_cs-vco_dp9/.magicrc
new file mode 120000
index 0000000..3522dc1
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/.magicrc
@@ -0,0 +1 @@
+/usr/local/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc
\ No newline at end of file
diff --git a/mag/3-stage_cs-vco_dp9/.spiceinit b/mag/3-stage_cs-vco_dp9/.spiceinit
new file mode 100755
index 0000000..828ff06
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/.spiceinit
@@ -0,0 +1,10 @@
+* ngspice initialization for sky130
+* assert BSIM compatibility mode with "nf" vs. "W"
+set ngbehavior=hsa
+* "nomodcheck" speeds up loading time
+set ng_nomodcheck
+* ngspice initialization for sky130
+* assert BSIM compatibility mode with "nf" vs. "W"
+set ngbehavior=hsa
+* "nomodcheck" speeds up loading time
+set ng_nomodcheck
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.ext b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.ext
new file mode 100755
index 0000000..234bc4f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.ext
@@ -0,0 +1,862 @@
+timestamp 1647616625
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use vco_switch_n_v2 vco_switch_n_v2_0 1 0 -1367 0 -1 -304
+use vco_switch_n_v2 vco_switch_n_v2_1 1 0 -721 0 -1 -304
+use vco_switch_n_v2 vco_switch_n_v2_2 1 0 -78 0 -1 -304
+use vco_switch_n_v2 vco_switch_n_v2_3 1 0 568 0 -1 -304
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -685 0 1 -537
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 -271 0 1 -397
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B 1 0 -478 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -891 0 1 -537
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16A -1 0 -64 0 1 -299
+use sky130_fd_pr__nfet_01v8_MV8TJR XM16B -1 0 143 0 1 -517
+use sky130_fd_pr__nfet_01v8_26QSQN XM16C 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16D_1 -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16 -1 0 -64 0 1 -577
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_26QSQN XM16D_2 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1357 0 1 45
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -397
+use sky130_fd_pr__pfet_01v8_MP1P4U XM1 0 1 -465 -1 0 351
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -437 1 0 101
+use sky130_fd_pr__pfet_01v8_MP0P75 XM3 0 1 -99 -1 0 351
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4 0 -1 -167 1 0 101
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 -271 0 1 899
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5 0 -1 517 1 0 351
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_4XEGTB XM11A 1 0 -64 0 1 791
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11C 1 0 350 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11D_1 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11D_2 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__nfet_01v8_LS30AB XM22_0p42 1 0 886 0 1 107
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 562
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -688 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B 1 0 -482 0 1 1040
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -894 0 1 1039
+use vco_switch_p vco_switch_p_0 1 0 -1367 0 -1 2536
+use vco_switch_p vco_switch_p_1 1 0 -721 0 -1 2536
+use sky130_fd_pr__pfet_01v8_4XEGTB XM11 1 0 -64 0 1 1079
+use sky130_fd_pr__pfet_01v8_KQRM7Z XM11B 1 0 143 0 1 1019
+use vco_switch_p vco_switch_p_2 1 0 -78 0 -1 2536
+use vco_switch_p vco_switch_p_3 1 0 568 0 -1 2536
+port "vctrl" 3 -1753 -752 -1553 -552 m1
+port "sel3" 7 -1190 1364 -1158 1396 m1
+port "sel2" 6 -1279 1445 -1247 1477 m1
+port "sel1" 5 -1359 1519 -1327 1551 m1
+port "sel0" 4 -1436 1674 -1404 1706 m1
+port "out" 2 1710 200 1766 228 li
+port "vdd" 0 1633 2181 1833 2381 m1
+port "vss" 1 1893 2441 2093 2641 m1
+node "ng3" 5 1344.6 528 -684 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12786 754 48852 2478 28280 1056 0 0 0 0 0 0
+node "m1_488_n269#" 1 311.685 488 -269 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 270 102 0 0 0 0 0 0 0 0 0 0
+node "ng2" 3 1086.69 313 -691 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9246 590 45116 1734 23046 876 0 0 0 0 0 0
+node "ng1" 2 584.509 112 -696 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9293 590 14380 730 26056 984 0 0 0 0 0 0
+node "ng0" 5 1349.87 -437 -1048 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9008 576 43160 2124 48332 1842 0 0 0 0 0 0
+node "vgp" 4 364.138 -758 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64630 2902 0 0 0 0 0 0 0 0 0 0
+node "m1_n1099_1625#" 16 215.654 -1099 1625 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45201 2284 140128 7146 115778 4430 0 0 0 0 0 0
+node "vctrl" 19 3367.75 -1753 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80203 2894 179744 9136 112866 4206 0 0 0 0 0 0
+node "sel3" 29 1850.7 -1190 1364 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111696 6532 213524 10756 49048 1852 0 0 0 0 0 0
+node "sel2" 26 1786.27 -1279 1445 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111866 6542 169112 8562 39632 1552 0 0 0 0 0 0
+node "sel1" 22 1796.64 -1359 1519 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111832 6540 123672 6290 30152 1236 0 0 0 0 0 0
+node "pg3" 5 294.331 527 1143 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13002 754 50493 2436 45016 1616 0 0 0 0 0 0
+node "pg2" 4 204.309 318 1140 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8254 558 33796 1736 42476 1516 0 0 0 0 0 0
+node "sel0" 17 1955.81 -1436 1674 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108240 6444 64752 3340 0 0 0 0 0 0 0 0
+node "pg0" 5 179.199 -437 1792 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9008 576 44126 2174 65552 2416 0 0 0 0 0 0
+node "pg1" 2 182.15 113 1131 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9293 590 15202 728 45076 1618 0 0 0 0 0 0
+node "li_528_n678#" 55 145.007 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 101 197.891 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9588 632 0 0 0 0 0 0 0 0 0 0 0 0
+node "net8" 44 3574.38 -460 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 95979 4106 0 0 0 0 0 0 0 0 0 0
+node "net6" 207 214.144 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 245.72 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "net4" 264 349.918 -102 132 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24694 1530 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n118_290#" 51 6.86424 -118 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 831 146 0 0 0 0 0 0 0 0 0 0 0 0
+node "net5" 222 768.32 -690 207 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17777 1192 35970 2150 0 0 0 0 0 0 0 0 0 0
+node "net3" 287 278.665 -545 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27234 1670 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1388_346#" 59 0 1388 346 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 238 82 0 0 0 0 0 0 0 0 0 0 0 0
+node "net7" 221 134.496 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20944 1300 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 473 228.571 1710 200 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 57222 3056 0 0 0 0 0 0 0 0 0 0 0 0
+node "net2" 56 0 -517 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 111768 4848 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 150 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14178 902 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 0 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 56.5972 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 32.5685 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 47677 19504.4 1633 2181 m1 0 0 0 0 5615313 15454 0 0 287028 16952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 313276 18700 1096287 27918 39012 1368 394100 8080 0 0 0 0 0 0
+substrate "vss" 0 0 1893 2441 m1 0 0 0 0 0 0 0 0 0 0 267036 15776 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 278324 16644 861968 30636 39012 1368 341000 7018 0 0 0 0 0 0
+cap "a_879_204#" "li_611_133#" 11.55
+cap "ng2" "vctrl" 1046.55
+cap "net3" "vdd" 254.387
+cap "net8" "ng0" 135.658
+cap "pg2" "sel3" 360.385
+cap "pg2" "pg0" 15.9873
+cap "pg3" "a_589_1133#" 19.205
+cap "net4" "net5" 80.6316
+cap "pg3" "pg1" 13.3403
+cap "net4" "li_611_133#" 3.57049
+cap "ng1" "ng2" 57.7228
+cap "li_1179_712#" "out" 46.9389
+cap "sel2" "ng0" 22.2163
+cap "li_1179_n70#" "net7" 23.8335
+cap "ng2" "vdd" 3.89313
+cap "sel0" "ng0" 5.55985
+cap "li_1388_346#" "net7" 12.97
+cap "sel3" "pg1" 103.983
+cap "m1_n1099_1625#" "pg2" 1112.84
+cap "pg2" "sel2" 192.028
+cap "pg0" "pg1" 101.678
+cap "li_528_n678#" "ng3" 71.6688
+cap "li_523_1149#" "a_589_1133#" 25.2972
+cap "sel3" "ng3" 13.6627
+cap "li_n118_290#" "vdd" 47.8032
+cap "li_1388_346#" "vdd" 17.0301
+cap "pg3" "sel3" 250.541
+cap "ng0" "vctrl" 1475.82
+cap "m1_n1099_1625#" "pg1" 478.177
+cap "sel2" "pg1" 166.472
+cap "net6" "out" 3.9521
+cap "sel3" "vgp" 148.083
+cap "pg3" "li_523_1149#" 92.738
+cap "a_879_204#" "vdd" 11
+cap "ng1" "ng0" 113.773
+cap "sel2" "ng3" 19.4974
+cap "sel3" "pg0" 299.342
+cap "pg2" "net2" 0.944882
+cap "net8" "vgp" 28.224
+cap "net6" "li_611_133#" 28.2715
+cap "li_1179_712#" "net7" 3.3
+cap "vdd" "ng0" 3.89313
+cap "net4" "vdd" 146.063
+cap "pg3" "m1_n1099_1625#" 167.763
+cap "pg3" "sel2" 9.13793
+cap "net5" "vgp" 23
+cap "net3" "li_n118_290#" 12.1957
+cap "m1_n1099_1625#" "vgp" 29.1549
+cap "pg2" "vdd" 873.473
+cap "sel3" "sel2" 7080.01
+cap "m1_n1099_1625#" "sel3" 2877.8
+cap "sel1" "ng0" 52.4429
+cap "net2" "pg1" 1.33005
+cap "pg0" "sel2" 218.342
+cap "m1_n1099_1625#" "pg0" 1657.78
+cap "li_1179_712#" "vdd" 342.954
+cap "net5" "net8" 159.767
+cap "sel3" "sel0" 785.479
+cap "pg0" "sel0" 5.55985
+cap "ng3" "vctrl" 173.123
+cap "net5" "li_611_133#" 25.3289
+cap "vdd" "a_589_1133#" 51.7
+cap "net4" "net3" 30.6658
+cap "net6" "net7" 106.342
+cap "vdd" "pg1" 503.171
+cap "pg3" "net2" 5.52
+cap "ng1" "ng3" 13.7266
+cap "vgp" "vctrl" 2.925
+cap "m1_n1099_1625#" "sel2" 1213.1
+cap "sel2" "sel0" 1336.43
+cap "m1_n1099_1625#" "sel0" 199.69
+cap "ng3" "vdd" 216.549
+cap "vgp" "net2" 35.6134
+cap "net7" "out" 100.159
+cap "ng2" "ng0" 11.5226
+cap "sel3" "vctrl" 281.048
+cap "sel1" "pg1" 83.4672
+cap "pg3" "vdd" 1652.67
+cap "net6" "vdd" 126.227
+cap "pg0" "net2" 143.754
+cap "vgp" "vdd" 382.224
+cap "li_611_133#" "net7" 5.25334
+cap "ng1" "sel3" 15.8171
+cap "a_590_n694#" "ng3" 19.205
+cap "net8" "net2" 27.8642
+cap "sel3" "vdd" 2284.39
+cap "out" "vdd" 658.458
+cap "net4" "li_n118_290#" 23.2619
+cap "pg0" "vdd" 1183.63
+cap "net5" "net2" 157.498
+cap "sel2" "vctrl" 311.671
+cap "ng1" "net8" 0.93361
+cap "sel0" "vctrl" 523.352
+cap "li_523_1149#" "vdd" 152.4
+cap "a_590_n694#" "li_528_n678#" 25.2972
+cap "net5" "vdd" 249.936
+cap "li_611_133#" "vdd" 94.682
+cap "ng1" "sel2" 26.549
+cap "sel1" "sel3" 1989.41
+cap "sel1" "pg0" 224.578
+cap "sel2" "vdd" 1653.24
+cap "m1_n1099_1625#" "vdd" 3992.12
+cap "ng2" "ng3" 368.531
+cap "sel0" "vdd" 21.3132
+cap "m1_488_n269#" "ng3" 0.609756
+cap "net3" "net8" 53.7118
+cap "sel1" "sel2" 6161.54
+cap "m1_n1099_1625#" "sel1" 821.237
+cap "sel1" "sel0" 3544.74
+cap "net3" "net5" 77.5585
+cap "ng2" "sel3" 15.1539
+cap "ng1" "vctrl" 387.107
+cap "net7" "vdd" 151.377
+cap "vdd" "vctrl" 352.59
+cap "net6" "li_1179_n70#" 0.798387
+cap "vdd" "net2" 2929.62
+cap "m1_488_n269#" "net8" 15.7628
+cap "ng1" "vdd" 4.00763
+cap "pg2" "pg1" 51.6756
+cap "ng2" "sel2" 21.9918
+cap "li_1388_346#" "out" 6.26867
+cap "sel1" "vctrl" 640.179
+cap "sel1" "ng1" 7.6556
+cap "net3" "net2" 64.4913
+cap "pg3" "pg2" 301.72
+cap "sel1" "vdd" 1041.82
+cap "sel3" "ng0" 17.0393
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/out" 147.165
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/out" 18.1424
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_0/selb" 66.5781
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/out" 30.5942
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/in" 26.1045
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_0/in" 453.266
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/selb" 45.6391
+cap "vco_switch_n_v2_0/vss" "sel3" 43.405
+cap "sel3" "vco_switch_n_v2_0/selb" 6.00852
+cap "vco_switch_n_v2_0/vdd" "sel3" 162.947
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/sel" 6.73021
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/vss" 27.295
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/selb" 1.09235
+cap "vco_switch_n_v2_0/in" "XM26/a_n76_n69#" 0.734364
+cap "sel2" "vco_switch_n_v2_0/sel" 18.8183
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_0/selb" 30.9974
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/out" 94.2427
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_0/out" 101.526
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_1/sel" 103.004
+cap "sel2" "vco_switch_n_v2_0/out" 137.717
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_0/selb" 24.3718
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_1/sel" 17.4878
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_0/selb" 42.962
+cap "sel2" "vco_switch_n_v2_0/selb" 35.26
+cap "sel2" "vco_switch_n_v2_0/vss" 27.9619
+cap "vco_switch_n_v2_0/vdd" "sel2" -67.6471
+cap "vco_switch_n_v2_0/vss" "XM26/a_n76_n69#" 356.268
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_1/sel" 38.8126
+cap "vco_switch_n_v2_0/in" "sel3" 1.875
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/in" 19.2798
+cap "vco_switch_n_v2_0/vss" "XM16A/a_18_n29#" 14.7271
+cap "vco_switch_n_v2_0/sel" "sel3" 7.72388
+cap "vco_switch_n_v2_0/in" "vco_switch_n_v2_1/selb" 3.51738
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/selb" 149.335
+cap "vco_switch_n_v2_0/vss" "vco_switch_n_v2_1/sel" 23.9984
+cap "vco_switch_n_v2_0/vdd" "vco_switch_n_v2_1/sel" -126.846
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/vdd" 24.3718
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/out" 24.3622
+cap "vco_switch_n_v2_2/out" "XM16A/a_18_n29#" 1.29592
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/XM25/a_n33_67#" 1.09235
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_0/vdd" 315.967
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_0/vss" 117.055
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_0/vdd" 2.40773
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/vdd" -66.0833
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_0/out" 3.704
+cap "vco_switch_n_v2_2/sel" "XM16D_1/a_n33_n297#" 4.33268
+cap "vco_switch_n_v2_2/selb" "XM16D_1/a_n33_n297#" 38.3249
+cap "vco_switch_n_v2_2/out" "vco_switch_n_v2_0/vss" 186.481
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_1/in" 3.51738
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_0/vdd" 109.625
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_2/out" 21.6825
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_2/selb" 61.0788
+cap "vco_switch_n_v2_0/out" "vco_switch_n_v2_0/vdd" 14.9311
+cap "XM16D_1/a_n33_n297#" "XM16A/a_18_n29#" 33.0122
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_2/sel" 93.6304
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_1/in" 53.9773
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_3/sel" 27.7607
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_1/in" 16.4475
+cap "vco_switch_n_v2_2/out" "vco_switch_n_v2_0/vdd" 94.2427
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/selb" 1.09235
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_1/sel" 75.4294
+cap "XM16D_1/a_n33_n297#" "vco_switch_n_v2_0/vss" 35.4191
+cap "vco_switch_n_v2_1/out" "XM16D_1/a_n33_n297#" 8.92483
+cap "vco_switch_n_v2_1/selb" "XM26/a_n33_n157#" 10.4577
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_2/sel" 156.417
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/vss" 1079.12
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_1/in" 173.574
+cap "XM26/a_n33_n157#" "XM16A/a_18_n29#" 5.80096
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/sel" 0.605381
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_2/selb" 2.20213
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_2/sel" 37.1
+cap "vco_switch_n_v2_2/sel" "vco_switch_n_v2_3/sel" 8.51746
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_3/sel" 0.909091
+cap "vco_switch_n_v2_2/out" "XM16D_1/a_n33_n297#" 23.5919
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/out" 29.8724
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_2/sel" 22.0351
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_0/vss" 51.6091
+cap "vco_switch_n_v2_1/out" "XM26/a_n33_n157#" 21.6825
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_2/out" 146.722
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_1/selb" 3.51738
+cap "vco_switch_n_v2_1/selb" "XM16A/a_18_n29#" 8.46918
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_1/sel" 187.671
+cap "vco_switch_n_v2_2/sel" "vco_switch_n_v2_0/vss" 14.45
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_0/vss" 61.0551
+cap "XM26/a_n33_n157#" "vco_switch_n_v2_0/out" 30.9991
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_2/sel" 164.363
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_2/selb" 63.3885
+cap "vco_switch_n_v2_1/in" "vco_switch_n_v2_0/vdd" -78.7494
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_1/sel" 7.77237
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/vss" 49.619
+cap "XM26/a_n76_n69#" "vco_switch_n_v2_0/vss" 14.8829
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_1/selb" 33.0796
+cap "vco_switch_n_v2_2/out" "XM26/a_n33_n157#" 8.92483
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/out" 31.2911
+cap "vco_switch_n_v2_0/XM25/a_n76_n108#" "vco_switch_n_v2_0/vss" 2.44978
+cap "vco_switch_n_v2_0/vss" "XM16A/a_18_n29#" 911.399
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/vss" 15.1258
+cap "vco_switch_n_v2_1/selb" "vco_switch_n_v2_0/out" 30.5942
+cap "vco_switch_n_v2_1/out" "XM16A/a_18_n29#" 2.62195
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/sel" 4.46782
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_1/sel" 18.206
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_2/out" 33.2831
+cap "vco_switch_n_v2_0/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "vco_switch_n_v2_1/sel" 0.909091
+cap "vco_switch_n_v2_2/selb" "vco_switch_n_v2_0/vdd" 24.3718
+cap "vco_switch_n_v2_2/sel" "vco_switch_n_v2_0/vdd" -124.488
+cap "vco_switch_n_v2_2/sel" "vco_switch_n_v2_2/out" 32.5472
+cap "vco_switch_n_v2_1/sel" "vco_switch_n_v2_0/out" 13.0806
+cap "vco_switch_n_v2_0/out" "XM16A/a_18_n29#" 23.3374
+cap "vco_switch_n_v2_0/sel" "vco_switch_n_v2_0/vss" 3.20704
+cap "vco_switch_n_v2_0/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "vco_switch_n_v2_0/vss" 10.4924
+cap "vco_switch_n_v2_1/out" "vco_switch_n_v2_0/vss" 143.608
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_2/out" 0.38961
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_2/XM25/a_n76_n108#" 2.70974
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/XM25/a_n76_n108#" 6.75692
+cap "vco_switch_n_v2_3/out" "vco_switch_n_v2_2/vss" 3.61204
+cap "vco_switch_n_v2_3/vdd" "vco_switch_n_v2_2/vss" -5.68434e-14
+cap "vco_switch_n_v2_2/XM25/a_n76_n108#" "vco_switch_n_v2_2/vss" 2.44978
+cap "vco_switch_n_v2_2/out" "vco_switch_n_v2_2/vss" 13.118
+cap "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "vco_switch_n_v2_3/sel" 4.44805
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_3/sel" 162.075
+cap "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "vco_switch_n_v2_2/vss" 3.20704
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_3/sel" 56.6746
+cap "vco_switch_n_v2_3/out" "vco_switch_n_v2_3/vdd" 79.3116
+cap "vco_switch_n_v2_2/out" "vco_switch_n_v2_3/vdd" 14.9311
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/vss" -6.19138
+cap "vco_switch_n_v2_2/XM25/a_n76_n108#" "vco_switch_n_v2_3/vdd" 2.40773
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_2/vss" -7.3
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_3/out" 20.6506
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" 0.909091
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_3/vdd" 24.3718
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/XM25/a_n76_n108#" 3.51738
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/out" 31.2911
+cap "vco_switch_n_v2_3/out" "vco_switch_n_v2_3/sel" 13.4311
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_3/out" 72.2544
+cap "vco_switch_n_v2_3/selb" "vco_switch_n_v2_2/XM25/a_n33_67#" 1.09235
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_3/vdd" -118.415
+cap "vco_switch_n_v2_3/sel" "vco_switch_n_v2_2/out" 13.0236
+cap "vco_switch_n_v2_2/vss" "vco_switch_n_v2_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" 5.42299
+cap "vco_switch_n_v2_3/in" "vco_switch_n_v2_3/vdd" 130.659
+cap "XM1/w_n109_n244#" "sel3" 32.6677
+cap "XM26/a_n76_n69#" "vss" 1.65
+cap "XM1/w_n109_n244#" "XM1/a_n73_n144#" -22.6368
+cap "XM1/w_n109_n244#" "sel1" 11.0635
+cap "XM16A/a_18_n29#" "XM1/a_15_n144#" -34.4228
+cap "vco_switch_p_0/sel" "XM1/w_n109_n244#" 0.189112
+cap "XM1/w_n109_n244#" "XM1/a_n33_n241#" -5.07346
+cap "XM1/w_n109_n244#" "XM11A/a_n33_55#" 0.814714
+cap "XM26/a_n76_n69#" "sel3" 8.00752
+cap "XM1/w_n109_n244#" "sel2" 23.2979
+cap "XM26/a_n76_n69#" "vco_switch_p_0/sel" 1.94792
+cap "XM1/w_n109_n244#" "XM1/a_15_n144#" -22.4633
+cap "vss" "XM1/a_n33_n241#" 3.58542
+cap "XM3/a_n73_n64#" "XM1/a_n73_n144#" -0.249057
+cap "vss" "XMDUM26/a_n76_n69#" 3.3
+cap "XM4/a_n73_n96#" "XM1/a_n33_n241#" 0.0962099
+cap "vss" "XM1/a_15_n144#" 7.1465
+cap "XM1/a_n73_n144#" "XM1/a_n33_n241#" 16.7192
+cap "XM16A/a_18_n29#" "vss" 8.25
+cap "XM4/a_15_n96#" "XM1/a_n33_n241#" 0.38484
+cap "XM26/a_n76_n69#" "XMDUM16/a_n76_n209#" 0.0019407
+cap "XM16A/a_18_n29#" "XM4/a_n73_n96#" -0.371622
+cap "vss" "XMDUM26B/a_n76_n69#" 3.3
+cap "XM1/a_15_n144#" "XM1/a_n73_n144#" -45.394
+cap "XM26/a_18_n69#" "vss" 1.65
+cap "XM16A/a_18_n29#" "XM1/a_n73_n144#" 5.67628
+cap "XM1/a_15_n144#" "XM1/a_n33_n241#" 52.8243
+cap "XM26/a_n76_n69#" "XM1/w_n109_n244#" 370.212
+cap "XM4/a_15_n96#" "XM1/a_15_n144#" -2.19397
+cap "XM1/a_15_n144#" "XM3/a_15_n64#" -3.63416
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "XM1/w_n109_n244#" 3.06251
+cap "XM11C/a_n33_235#" "XM1/a_n73_n144#" 15.9992
+cap "XM1/w_n109_n244#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" 3.06761
+cap "XM1/a_15_n144#" "XM16A/a_n33_n117#" 2.14552
+cap "XMDUM16/a_n76_n209#" "XM26/a_n76_n69#" 0.0019407
+cap "XM1/a_n73_n144#" "XM11B/a_n33_115#" -0.549465
+cap "XM13/a_n33_142#" "XMDUM16B/a_n76_n209#" 1.52489
+cap "XM13/a_n33_142#" "XM24/a_18_n129#" 2.96029
+cap "XMDUM16/a_n76_n209#" "vss" 37.4
+cap "XM1/a_n73_n144#" "XM1/w_n109_n244#" 1347.19
+cap "XM16A/a_18_n29#" "XM1/a_n33_n241#" 4.41732
+cap "XM16C/a_18_n209#" "XM1/a_n33_n241#" 8.83465
+cap "XMDUM16/a_n76_n209#" "XM16A/a_n76_n29#" 12.5306
+cap "XM1/w_n109_n244#" "XM3/a_15_n64#" -7.40527
+cap "XM16D_2/a_18_n209#" "XM16A/a_18_n29#" 122.226
+cap "XM1/a_n73_n144#" "XM11A/a_n33_55#" 26.0774
+cap "XM16A/a_18_n29#" "vss" 66.0926
+cap "XM16C/a_18_n209#" "XM16D_2/a_18_n209#" 65.0634
+cap "XM16C/a_18_n209#" "vss" 37.4
+cap "XM13/a_n73_n120#" "XM1/a_n33_n241#" 2.28145
+cap "XM16A/a_18_n29#" "XM16A/a_n76_n29#" 9.12566
+cap "XM16D_2/a_18_n209#" "XM13/a_n73_n120#" 6.87126
+cap "XM16C/a_18_n209#" "XM16A/a_n76_n29#" 3.21316
+cap "XM13/a_n73_n120#" "vss" 10.1912
+cap "XM11C/a_n33_235#" "vco_switch_p_2/sel" 2.26133
+cap "vss" "XM16A/a_n33_n117#" 3.58224
+cap "XM13/a_n33_142#" "XM1/w_n109_n244#" 26.0783
+cap "XM16A/a_18_n29#" "XMDUM16B/a_n76_n209#" 77.8241
+cap "XM16C/a_18_n209#" "XMDUM16B/a_n76_n209#" 35.9202
+cap "XM1/a_15_n144#" "XM1/a_n33_n241#" 36.4137
+cap "XM16A/a_18_n29#" "XMDUM16/a_n33_n297#" 16.7825
+cap "XM16D_2/a_18_n209#" "XM1/a_15_n144#" 0.2489
+cap "XM13/a_n73_n120#" "XMDUM16B/a_n76_n209#" 17.7442
+cap "XM1/a_15_n144#" "vss" 0.825
+cap "XM11C/a_n33_235#" "XM11D_1/a_n33_235#" 19.3062
+cap "XM13/a_n33_142#" "XM24/a_n76_n129#" 9.37965
+cap "XM13/a_15_n120#" "XM1/a_n33_n241#" 0.212704
+cap "XM11D_1/a_n33_235#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 0.508562
+cap "XM11D_1/a_n33_235#" "XM11B/a_n33_115#" 4.40674
+cap "XM1/a_n73_n144#" "XM3/a_15_n64#" 3.22347
+cap "XM16D_2/a_18_n209#" "XM1/a_n33_n241#" 24.544
+cap "XM13/a_15_n120#" "vss" 0.846154
+cap "XM11D_1/a_n33_235#" "XM1/w_n109_n244#" -192.147
+cap "XMDUM16/a_n33_n297#" "XM1/a_15_n144#" 1.77976
+cap "vss" "XM1/a_n33_n241#" 104.363
+cap "XM26/a_n76_n69#" "vco_switch_p_1/sel" 1.48454
+cap "XM16D_2/a_18_n209#" "vss" 85.6259
+cap "XM16D_2/a_18_n209#" "XM16A/a_n76_n29#" 2.02342
+cap "XM13/a_15_n120#" "XMDUM16B/a_n76_n209#" 8.65096
+cap "vss" "XM16A/a_n76_n29#" 9.77141
+cap "XM13/a_n33_142#" "XM3/a_15_n64#" 0.192737
+cap "XMDUM16B/a_n76_n209#" "XM1/a_n33_n241#" 17.2928
+cap "XM16A/a_18_n29#" "ng1" -0.293734
+cap "XM1/w_n109_n244#" "XM1/a_15_n144#" 46.4692
+cap "XM1/a_n73_n144#" "vco_switch_p_2/sel" 1.30645
+cap "XM16D_2/a_18_n209#" "XMDUM16B/a_n76_n209#" 77.752
+cap "XMDUM16B/a_n76_n209#" "vss" 120.403
+cap "vss" "XM24/a_18_n129#" 2.71978
+cap "XM11C/a_n33_235#" "XM26/a_n76_n69#" 4.41593
+cap "XM23/a_n78_n220#" "XM1/w_n109_n244#" 11.5274
+cap "XM11D_1/a_n33_235#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" 0.55618
+cap "XM16A/a_18_n29#" "XM1/a_n73_n144#" 1.79808
+cap "XM1/w_n109_n244#" "XM13/a_15_n120#" 61.4609
+cap "XM26/a_n76_n69#" "XM11B/a_n33_115#" 10.474
+cap "XM1/w_n109_n244#" "XM26/a_n76_n69#" 70.7604
+cap "XM1/w_n109_n244#" "XM1/a_n33_n241#" 118.806
+cap "XM16A/a_18_n29#" "XM3/a_15_n64#" 8.37613
+cap "XM11D_1/a_n33_235#" "XM1/a_n73_n144#" 41.8398
+cap "XM16D_2/a_18_n209#" "XM1/w_n109_n244#" 14.2773
+cap "XM26/a_n76_n69#" "XM11A/a_n33_55#" 31.262
+cap "XM3/a_15_n64#" "XM16C/a_n33_n297#" 2.59677
+cap "XM1/w_n109_n244#" "vss" 3.71523
+cap "XM1/w_n109_n244#" "vco_switch_p_1/sel" 2.15003
+cap "a_590_n694#" "XM3/a_15_n64#" 3.21505
+cap "XM1/w_n109_n244#" "XMDUM16B/a_n76_n209#" 7.50227
+cap "XM1/a_n73_n144#" "XM1/a_15_n144#" 5.09259
+cap "a_590_n694#" "XMDUM16B/a_n33_n297#" 5.75368
+cap "XM1/a_n33_n241#" "XM24/a_n76_n129#" 1.05413
+cap "XM13/a_n33_142#" "XM13/a_n73_n120#" 44.2393
+cap "XM3/a_15_n64#" "XM1/a_15_n144#" 43.2961
+cap "XM11C/a_n33_235#" "XM11B/a_n33_115#" 10.3669
+cap "vss" "XM24/a_n76_n129#" 3.66667
+cap "XM16A/a_18_n29#" "XMDUM16/a_n76_n209#" 60.5534
+cap "XM11C/a_n33_235#" "XM1/w_n109_n244#" -44.3169
+cap "XM11D_1/a_n33_235#" "vco_switch_p_2/sel" 1.94792
+cap "XM1/w_n109_n244#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 1.33913
+cap "XM1/w_n109_n244#" "XM11B/a_n33_115#" -4.55551
+cap "XM16C/a_18_n209#" "XM16A/a_18_n29#" 96.9346
+cap "XM1/a_n73_n144#" "XM1/a_n33_n241#" 7.5302
+cap "XM1/a_n73_n144#" "XM26/a_n76_n69#" 1.22185
+cap "XM1/a_n73_n144#" "vco_switch_p_1/sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 0.815407
+cap "XM11A/a_n33_55#" "XM11B/a_n33_115#" 3.71694
+cap "XM16A/a_18_n29#" "XM16C/a_n33_n297#" 16.993
+cap "XM3/a_15_n64#" "XM1/a_n33_n241#" 64.4646
+cap "XM1/w_n109_n244#" "XM11A/a_n33_55#" 48.6013
+cap "a_590_n694#" "XM16A/a_18_n29#" 16.7825
+cap "XM16D_2/a_18_n209#" "XM3/a_15_n64#" 6.90148
+cap "XM3/a_15_n64#" "vss" 25.7281
+cap "a_590_n694#" "XM16C/a_n33_n297#" 5.75368
+cap "XM13/a_n33_142#" "XM13/a_15_n120#" 19.6055
+cap "XMDUM16/a_n76_n209#" "XM1/a_15_n144#" 9.80153
+cap "XM3/a_15_n64#" "XM16A/a_n76_n29#" 3.33929
+cap "XM13/a_n33_142#" "XM1/a_n33_n241#" 11.8249
+cap "XM1/a_n33_n241#" "XMDUM16B/a_n33_n297#" 2.92292
+cap "vco_switch_p_1/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "XM11B/a_n33_115#" 3.05977
+cap "XM13/a_n33_142#" "XM16D_2/a_18_n209#" 5.38542
+cap "XM16A/a_18_n29#" "XM1/a_15_n144#" 2.86733
+cap "XM13/a_n33_142#" "vss" 10.6825
+cap "XM13/a_n73_n120#" "XM21/a_n15_n53#" 2.28145
+cap "XM13/a_15_n120#" "XM5/w_n109_n298#" 335.966
+cap "XM24/a_18_n129#" "XM24/a_n76_n129#" 3.33511
+cap "XM13/a_15_n120#" "XM21/a_n15_n53#" 0.212704
+cap "XM24/a_n76_n129#" "XM13/a_n33_142#" 16.4928
+cap "vss" "XM24/a_n76_n129#" 3.66667
+cap "XM24/a_n76_n129#" "XM13/a_n73_n120#" 92.2113
+cap "XM24/a_18_n129#" "XM13/a_n33_142#" 6.02695
+cap "XM13/a_n33_142#" "XMDUM16B/a_n76_n209#" 1.375
+cap "vss" "XM24/a_18_n129#" 2.71978
+cap "XM24/a_18_n129#" "XM13/a_n73_n120#" 31.2366
+cap "XM13/a_n73_n120#" "XMDUM16B/a_n76_n209#" 17.7442
+cap "XM13/a_n33_142#" "XM5/a_n73_n236#" 0.637807
+cap "XM24/a_n76_n129#" "XM5/w_n109_n298#" 6.80625
+cap "XM13/a_n73_n120#" "XM13/a_n33_142#" 113.734
+cap "XM24/a_18_n129#" "XM5/w_n109_n298#" 160.216
+cap "XM13/a_15_n120#" "XM24/a_n76_n129#" 228.678
+cap "vss" "XM13/a_n73_n120#" 10.1912
+cap "XM24/a_n76_n129#" "XM21/a_n15_n53#" 1.05413
+cap "XM13/a_15_n120#" "XMDUM16B/a_n76_n209#" 8.65096
+cap "XM5/a_n33_395#" "XM13/a_n33_142#" 0.192737
+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 291.505
+cap "XM16D_2/a_18_n209#" "XM13/a_n73_n120#" 6.87126
+cap "XM13/a_n33_142#" "XM5/w_n109_n298#" -30.4529
+cap "XM13/a_n73_n120#" "XM5/w_n109_n298#" 15.2444
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 70.6166
+cap "XM13/a_15_n120#" "vss" 0.846154
+cap "XM13/a_15_n120#" "XM13/a_n73_n120#" 3.40206
+cap "XM21/a_n15_n53#" "XM13/a_n33_142#" 6.24162
+cap "sel2" "vco_switch_p_0/sel" 316.809
+cap "vco_switch_p_0/selb" "vco_switch_p_1/selb" 1.09235
+cap "XM25/a_n33_95#" "XMDUM11/a_n33_235#" 54.6323
+cap "sel3" "vco_switch_p_0/selb" 11.8123
+cap "XMDUM11/a_n33_235#" "vco_switch_p_1/sel" -138.486
+cap "XM11A/a_n33_55#" "vco_switch_p_1/selb" 26.9504
+cap "XM25/a_n33_95#" "vco_switch_p_0/sel" 44.9392
+cap "vco_switch_p_0/vss" "vco_switch_p_0/sel" 30.3946
+cap "XMDUM11/a_n33_235#" "vco_switch_p_0/selb" 18.5451
+cap "vco_switch_p_0/sel" "vco_switch_p_1/sel" 57.1232
+cap "XM25/a_n33_95#" "vco_switch_p_0/vss" 10.1664
+cap "vco_switch_p_0/sel" "vco_switch_p_0/selb" 17.2205
+cap "sel2" "vco_switch_p_0/selb" 16.58
+cap "XM25/a_n33_95#" "vco_switch_p_1/sel" 106.623
+cap "XMDUM11/a_n33_235#" "XM11A/a_n33_55#" 22.0896
+cap "XMDUM11/a_n33_235#" "vco_switch_p_1/selb" 0.205607
+cap "XM25/a_n33_95#" "vco_switch_p_0/selb" 6.39406
+cap "XM11A/a_n33_55#" "vco_switch_p_0/sel" 32.5749
+cap "sel2" "XM11A/a_n33_55#" 137.717
+cap "vco_switch_p_0/vss" "vco_switch_p_0/selb" 7.48
+cap "sel3" "XMDUM11/a_n33_235#" 267.409
+cap "vco_switch_p_0/selb" "vco_switch_p_1/sel" 145.127
+cap "XM25/a_n33_95#" "XM11A/a_n33_55#" 222.216
+cap "vco_switch_p_0/vss" "XM11A/a_n33_55#" 49.7301
+cap "sel3" "vco_switch_p_0/sel" 31.4715
+cap "XM11A/a_n33_55#" "vco_switch_p_1/sel" 87.7161
+cap "XM25/a_n33_95#" "vco_switch_p_1/selb" 3.51738
+cap "XMDUM11/a_n33_235#" "vco_switch_p_0/sel" 7.92187
+cap "XMDUM11/a_n33_235#" "sel2" -157.835
+cap "XM11A/a_n33_55#" "vco_switch_p_0/selb" 7.0055
+cap "XM11C/a_n33_235#" "XM11D_1/a_n33_235#" 13.9838
+cap "XM25/a_n33_95#" "vco_switch_p_2/selb" 7.10155
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "XMDUM11/a_n33_235#" 2.40773
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_1/selb" 3.51738
+cap "vco_switch_p_2/sel" "vco_switch_p_3/sel" 52.0786
+cap "XM25/a_n33_95#" "vco_switch_p_3/sel" 126.654
+cap "vco_switch_p_1/out" "vco_switch_p_0/vss" 63.1957
+cap "vco_switch_p_1/out" "XM11C/a_n33_235#" 12.1418
+cap "vco_switch_p_1/selb" "XMDUM11/a_n33_235#" 17.409
+cap "vco_switch_p_3/sel" "vco_switch_p_2/selb" 18.0352
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" "vco_switch_p_1/selb" 1.09235
+cap "vco_switch_p_1/out" "vco_switch_p_1/sel" 32.586
+cap "XM11/a_n76_n96#" "XMDUM11/a_n33_235#" 10.9741
+cap "XM25/a_n33_95#" "vco_switch_p_3/selb" 3.51738
+cap "vco_switch_p_3/selb" "vco_switch_p_2/selb" 1.09235
+cap "vco_switch_p_2/sel" "XM11D_1/a_18_n276#" 1.30645
+cap "XM11/a_n76_n96#" "vco_switch_p_1/selb" 0.815407
+cap "vco_switch_p_2/sel" "XM11D_1/a_n33_235#" 29.5171
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_0/vss" 2.44978
+cap "XM11D_1/a_n33_235#" "vco_switch_p_2/selb" 10.0903
+cap "vco_switch_p_1/out" "vco_switch_p_2/sel" 265.655
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_1/sel" 11.3917
+cap "XM11C/a_n33_235#" "XMDUM11/a_n33_235#" 13.5906
+cap "vco_switch_p_1/out" "XM25/a_n33_95#" 258.937
+cap "vco_switch_p_1/sel" "XMDUM11/a_n33_235#" -92.8854
+cap "vco_switch_p_1/out" "vco_switch_p_2/selb" 54.5484
+cap "vco_switch_p_0/vss" "vco_switch_p_1/selb" 7.48
+cap "vco_switch_p_1/sel" "vco_switch_p_1/selb" 110.605
+cap "XM11A/a_n33_55#" "XMDUM11/a_n33_235#" 17.9901
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" "vco_switch_p_1/sel" 3.11143
+cap "XM11A/a_n33_55#" "vco_switch_p_1/selb" 26.9504
+cap "vco_switch_p_1/sel" "vco_switch_p_0/sel" 6.27151
+cap "vco_switch_p_0/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "XM25/a_n33_95#" 16.4475
+cap "XM11D_1/a_n33_235#" "XM11D_1/a_18_n276#" 8.71698
+cap "vco_switch_p_0/vss" "vco_switch_p_0/sel" 3.20704
+cap "vco_switch_p_2/sel" "XMDUM11/a_n33_235#" -312.27
+cap "vco_switch_p_2/sel" "vco_switch_p_1/selb" 22.8567
+cap "vco_switch_p_1/sel" "vco_switch_p_0/sel" 4.78875
+cap "vco_switch_p_0/vss" "XM11C/a_n33_235#" 49.7301
+cap "XM25/a_n33_95#" "XMDUM11/a_n33_235#" -127.703
+cap "vco_switch_p_1/out" "XM11D_1/a_n33_235#" 4.93372
+cap "XMDUM11/a_n33_235#" "vco_switch_p_2/selb" 20.2248
+cap "XM25/a_n33_95#" "vco_switch_p_1/selb" 3.66243
+cap "vco_switch_p_1/sel" "vco_switch_p_0/vss" 21.4801
+cap "vco_switch_p_1/selb" "vco_switch_p_2/selb" 2.20213
+cap "XM25/a_n33_95#" "XM11/a_n76_n96#" 0.795643
+cap "XM11A/a_n33_55#" "vco_switch_p_0/vss" 13.118
+cap "XM11A/a_n33_55#" "vco_switch_p_1/sel" 61.9841
+cap "vco_switch_p_3/sel" "XMDUM11/a_n33_235#" 547.249
+cap "vco_switch_p_3/selb" "XMDUM11/a_n33_235#" 0.205607
+cap "XM11B/a_18_n156#" "XMDUM11/a_n33_235#" 6.08829
+cap "vco_switch_p_3/sel" "vco_switch_p_1/selb" 11.8123
+cap "XM25/a_n33_95#" "vco_switch_p_0/sel" 0.605381
+cap "XMDUM11/a_n33_235#" "XM11C/a_n76_n276#" 7.64761
+cap "vco_switch_p_2/sel" "XM11C/a_n33_235#" 66.6129
+cap "vco_switch_p_2/sel" "vco_switch_p_0/vss" 17.6377
+cap "XMDUM11/a_n33_235#" "XM11D_1/a_18_n276#" 8.50219
+cap "XM25/a_n33_95#" "vco_switch_p_0/vss" 7.00951
+cap "XM11D_1/a_n33_235#" "XMDUM11/a_n33_235#" -215.551
+cap "XM25/a_n33_95#" "XM11C/a_n33_235#" 240.888
+cap "vco_switch_p_2/sel" "vco_switch_p_1/sel" 330.23
+cap "vco_switch_p_0/vss" "vco_switch_p_2/selb" 7.48
+cap "XM11C/a_n33_235#" "vco_switch_p_2/selb" 21.492
+cap "XM25/a_n33_95#" "vco_switch_p_1/sel" 138.329
+cap "XM11A/a_n33_55#" "XM25/a_n33_95#" 34.5663
+cap "vco_switch_p_1/out" "XMDUM11/a_n33_235#" 40.8242
+cap "XM11C/a_n33_235#" "vco_switch_p_3/sel" 120.826
+cap "vco_switch_p_0/vss" "vco_switch_p_3/sel" 4.6118
+cap "vco_switch_p_1/out" "vco_switch_p_1/selb" 21.3624
+cap "XM11C/a_n33_235#" "vco_switch_p_3/selb" 26.9504
+cap "vco_switch_p_1/sel" "vco_switch_p_3/sel" 31.4715
+cap "XM11C/a_n33_235#" "XM11C/a_n76_n276#" 0.695876
+cap "XM25/a_n33_95#" "vco_switch_p_2/sel" 165.371
+cap "vco_switch_p_2/sel" "vco_switch_p_2/selb" 57.9939
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_3/sel" 6.75692
+cap "vco_switch_p_3/selb" "vco_switch_p_3/sel" 136.122
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/sel" -320.085
+cap "vco_switch_p_3/selb" "vco_switch_p_2/out" 26.9504
+cap "vco_switch_p_2/vss" "vco_switch_p_3/out" 3.61204
+cap "vco_switch_p_3/in" "vco_switch_p_3/sel" 56.6746
+cap "XM11D_2/a_18_n276#" "vco_switch_p_2/out" 14.9311
+cap "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "vco_switch_p_3/selb" 3.51738
+cap "vco_switch_p_3/in" "vco_switch_p_2/out" 0.38961
+cap "XM11D_2/a_18_n276#" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 2.40773
+cap "vco_switch_p_2/sel" "vco_switch_p_3/sel" 1.09524
+cap "vco_switch_p_2/vss" "vco_switch_p_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 3.20704
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/selb" 0.205607
+cap "vco_switch_p_3/out" "vco_switch_p_3/sel" 13.4311
+cap "vco_switch_p_3/in" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 2.70974
+cap "vco_switch_p_3/sel" "vco_switch_p_2/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 4.44805
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/in" 109.026
+cap "vco_switch_p_3/selb" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" 1.09235
+cap "vco_switch_p_2/vss" "vco_switch_p_3/sel" -6.19138
+cap "vco_switch_p_2/vss" "vco_switch_p_2/out" 13.118
+cap "XM11D_2/a_18_n276#" "vco_switch_p_3/out" 30.0199
+cap "vco_switch_p_3/in" "vco_switch_p_3/out" 72.2544
+cap "vco_switch_p_2/vss" "vco_switch_p_2/sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 2.44978
+cap "vco_switch_p_2/out" "vco_switch_p_3/sel" 14.3666
+merge "XM16C/a_n33_n297#" "vco_switch_n_v2_2/out" -175.458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48438 -276 46440 0 0 0 0 0 0 0 0 0
+merge "vco_switch_n_v2_2/out" "ng2"
+merge "vco_switch_p_0/out" "XM11A/a_n33_55#" -116.482 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44862 -276 0 0 0 0 0 0 0 0 0 0
+merge "XM11A/a_n33_55#" "pg0"
+merge "XM5/a_n33_395#" "XM3/a_15_n64#" -204.668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -150549 -610 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_15_n64#" "li_n118_290#"
+merge "li_n118_290#" "XM6/a_n33_135#"
+merge "XM6/a_n33_135#" "XM4/a_15_n96#"
+merge "XM4/a_15_n96#" "net4"
+merge "XM16D_2/a_n76_n209#" "XM16D_1/a_n76_n209#" -181.6 0 0 0 0 0 0 0 0 -1392 -1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -25896 -1270 -16802 -1114 0 0 0 0 0 0 0 0 0 0
+merge "XM16D_1/a_n76_n209#" "XM16C/a_n76_n209#"
+merge "XM16C/a_n76_n209#" "XM16B/a_n76_n89#"
+merge "XM16B/a_n76_n89#" "XM2/a_n73_n103#"
+merge "XM2/a_n73_n103#" "XM16/a_18_n29#"
+merge "XM16/a_18_n29#" "XM16A/a_18_n29#"
+merge "XM16A/a_18_n29#" "net8"
+merge "XM23/a_63_n366#" "XM23/a_n33_310#" -303.424 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13926 -264 0 0 -89150 -1046 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n33_310#" "XM23/a_n129_n366#"
+merge "XM23/a_n129_n366#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "li_1179_712#"
+merge "li_1179_712#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "li_1179_n70#"
+merge "li_1179_n70#" "net7"
+merge "vco_switch_p_3/out" "XM11D_2/a_n33_235#" 218.944 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -952 -264 0 0 7888 -400 12136 -484 -6567 -552 2802 -120 0 0 0 0 0 0
+merge "XM11D_2/a_n33_235#" "XM11D_1/a_n33_235#"
+merge "XM11D_1/a_n33_235#" "pg3"
+merge "pg3" "li_523_1149#"
+merge "li_523_1149#" "a_589_1133#"
+merge "vco_switch_p_3/in" "vco_switch_p_2/in" -393.433 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -153943 -1610 -81974 0 -57429 0 0 0 0 0 0 0
+merge "vco_switch_p_2/in" "vco_switch_p_1/in"
+merge "vco_switch_p_1/in" "vco_switch_p_0/in"
+merge "vco_switch_p_0/in" "XM11/a_n33_55#"
+merge "XM11/a_n33_55#" "XM25/a_n76_n136#"
+merge "XM25/a_n76_n136#" "XM25/a_n33_95#"
+merge "XM25/a_n33_95#" "m1_n1099_1625#"
+merge "m1_n1099_1625#" "XM26/a_n76_n69#"
+merge "XM26/a_n76_n69#" "vgp"
+merge "vco_switch_p_3/vss" "vco_switch_p_2/vss" -5614.99 0 0 0 0 0 0 0 0 0 0 -79174 -5364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11632 -6104 -146841 -16060 9336 -190 -137100 -2966 0 0 0 0 0 0
+merge "vco_switch_p_2/vss" "XMDUM11B/VSUBS"
+merge "XMDUM11B/VSUBS" "XM23/VSUBS"
+merge "XM23/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "XM12/VSUBS"
+merge "XM12/VSUBS" "XM11D_2/VSUBS"
+merge "XM11D_2/VSUBS" "XM11D_1/VSUBS"
+merge "XM11D_1/VSUBS" "XM11C/VSUBS"
+merge "XM11C/VSUBS" "XM5/VSUBS"
+merge "XM5/VSUBS" "XM11B/VSUBS"
+merge "XM11B/VSUBS" "XM11/VSUBS"
+merge "XM11/VSUBS" "vco_switch_p_1/vss"
+merge "vco_switch_p_1/vss" "vco_switch_p_0/vss"
+merge "vco_switch_p_0/vss" "XMDUM25/VSUBS"
+merge "XMDUM25/VSUBS" "XMDUM25B/VSUBS"
+merge "XMDUM25B/VSUBS" "XM25/VSUBS"
+merge "XM25/VSUBS" "XM11A/VSUBS"
+merge "XM11A/VSUBS" "XMDUM11/VSUBS"
+merge "XMDUM11/VSUBS" "XM3/VSUBS"
+merge "XM3/VSUBS" "XM1/VSUBS"
+merge "XM1/VSUBS" "XM22_0p42/VSUBS"
+merge "XM22_0p42/VSUBS" "XM22_0p42/a_n73_n80#"
+merge "XM22_0p42/a_n73_n80#" "XM6/VSUBS"
+merge "XM6/VSUBS" "XM6/a_n73_n175#"
+merge "XM6/a_n73_n175#" "XMDUM16B/VSUBS"
+merge "XMDUM16B/VSUBS" "XMDUM16B/a_n33_n297#"
+merge "XMDUM16B/a_n33_n297#" "XMDUM16B/a_18_n209#"
+merge "XMDUM16B/a_18_n209#" "XMDUM16B/a_n76_n209#"
+merge "XMDUM16B/a_n76_n209#" "XM24/VSUBS"
+merge "XM24/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM16D_2/VSUBS"
+merge "XM16D_2/VSUBS" "XM16D_2/a_18_n209#"
+merge "XM16D_2/a_18_n209#" "XM13/VSUBS"
+merge "XM13/VSUBS" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "XM16D_1/VSUBS"
+merge "XM16D_1/VSUBS" "XM16D_1/a_18_n209#"
+merge "XM16D_1/a_18_n209#" "m1_488_n269#"
+merge "m1_488_n269#" "XM16C/VSUBS"
+merge "XM16C/VSUBS" "XM16C/a_18_n209#"
+merge "XM16C/a_18_n209#" "XM16B/VSUBS"
+merge "XM16B/VSUBS" "XM16B/a_18_n89#"
+merge "XM16B/a_18_n89#" "vco_switch_n_v2_3/vss"
+merge "vco_switch_n_v2_3/vss" "vco_switch_n_v2_2/vss"
+merge "vco_switch_n_v2_2/vss" "XM4/VSUBS"
+merge "XM4/VSUBS" "XM4/a_n73_n96#"
+merge "XM4/a_n73_n96#" "XM2/VSUBS"
+merge "XM2/VSUBS" "XM16/VSUBS"
+merge "XM16/VSUBS" "XM16/a_n76_n29#"
+merge "XM16/a_n76_n29#" "XM16A/VSUBS"
+merge "XM16A/VSUBS" "XM16A/a_n76_n29#"
+merge "XM16A/a_n76_n29#" "XMDUM26/VSUBS"
+merge "XMDUM26/VSUBS" "XMDUM26/a_n33_n157#"
+merge "XMDUM26/a_n33_n157#" "XMDUM26/a_18_n69#"
+merge "XMDUM26/a_18_n69#" "XMDUM26/a_n76_n69#"
+merge "XMDUM26/a_n76_n69#" "XMDUM26B/VSUBS"
+merge "XMDUM26B/VSUBS" "XMDUM26B/a_n33_n157#"
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diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.mag b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.mag
new file mode 100755
index 0000000..14e7760
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.mag
@@ -0,0 +1,1361 @@
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+rect -1032 -691 -1027 -635
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+rect 300 -881 366 -876
+rect 161 -978 231 -973
+rect 161 -1038 166 -978
+rect 226 -1038 231 -978
+rect 161 -1043 231 -1038
+rect -93 -1055 -27 -1050
+rect -93 -1111 -88 -1055
+rect -32 -1111 -27 -1055
+rect -93 -1116 -27 -1111
+rect -1095 -1138 -1025 -1133
+rect -1095 -1198 -1090 -1138
+rect -1030 -1198 -1025 -1138
+rect -1095 -1205 -1025 -1198
+rect -349 -1138 -279 -1133
+rect -349 -1198 -344 -1138
+rect -284 -1198 -279 -1138
+rect -349 -1205 -279 -1198
+rect -90 -1213 -30 -1116
+rect 303 -1133 363 -881
+rect 797 -974 857 -794
+rect 943 -820 1034 -815
+rect 943 -876 948 -820
+rect 1004 -876 1034 -820
+rect 943 -881 1034 -876
+rect 797 -979 913 -974
+rect 797 -1039 848 -979
+rect 908 -1039 913 -979
+rect 843 -1044 913 -1039
+rect 554 -1056 620 -1051
+rect 554 -1112 559 -1056
+rect 615 -1112 620 -1056
+rect 554 -1117 620 -1112
+rect 298 -1138 368 -1133
+rect 298 -1198 303 -1138
+rect 363 -1198 368 -1138
+rect 298 -1205 368 -1198
+rect -95 -1218 -25 -1213
+rect -95 -1278 -90 -1218
+rect -30 -1278 -25 -1218
+rect -95 -1283 -25 -1278
+rect 557 -1293 617 -1117
+rect 974 -1133 1034 -881
+rect 1494 -976 1554 -696
+rect 1489 -981 1559 -976
+rect 1489 -1041 1494 -981
+rect 1554 -1041 1559 -981
+rect 1489 -1046 1559 -1041
+rect 941 -1138 1034 -1133
+rect 1176 -1073 1250 -1065
+rect 1176 -1129 1185 -1073
+rect 1241 -1129 1250 -1073
+rect 1176 -1137 1250 -1129
+rect 941 -1198 946 -1138
+rect 1006 -1198 1034 -1138
+rect 941 -1205 1034 -1198
+rect 552 -1298 622 -1293
+rect 552 -1358 557 -1298
+rect 617 -1358 622 -1298
+rect 552 -1363 622 -1358
+rect 1183 -1373 1243 -1137
+rect 1178 -1378 1248 -1373
+rect 1178 -1438 1183 -1378
+rect 1243 -1438 1248 -1378
+rect 1178 -1443 1248 -1438
+rect 1688 -1503 1788 1213
+rect 1949 -712 2049 2029
+rect 1949 -802 1954 -712
+rect 2044 -802 2049 -712
+rect 1949 -807 2049 -802
+rect 1688 -1593 1693 -1503
+rect 1783 -1593 1788 -1503
+rect 1688 -1598 1788 -1593
+use sky130_fd_pr__pfet_01v8_MP1P4U XM1
+timestamp 1647613837
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1647613837
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP0P75 XM3
+timestamp 1647613837
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4
+timestamp 1647613837
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5
+timestamp 1647613837
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1647613837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_4XEGTB XM11A
+timestamp 1647613837
+transform 1 0 -64 0 1 791
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_KQRM7Z XM11B
+timestamp 1647613837
+transform 1 0 143 0 1 1019
+box -112 -218 112 184
+use sky130_fd_pr__pfet_01v8_4XEGTB XM11
+timestamp 1647613837
+transform 1 0 -64 0 1 1079
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11C
+timestamp 1647613837
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11D_1
+timestamp 1647613837
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11D_2
+timestamp 1647613837
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1647613837
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1647613837
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16A
+timestamp 1647613837
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR XM16B
+timestamp 1647613837
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16C
+timestamp 1647613837
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16D_1
+timestamp 1647613837
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16D_2
+timestamp 1647613837
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1647613837
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1647613837
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__nfet_01v8_LS30AB XM22_0p42
+timestamp 1647613837
+transform 1 0 886 0 1 107
+box -73 -111 73 99
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1647613837
+transform 1 0 1453 0 1 562
+box -209 -366 209 376
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1647613837
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1647613837
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1647613837
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1647613837
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1647613837
+transform 1 0 -271 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1647613837
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1647613837
+transform 1 0 -271 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1647613837
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1647613837
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1647613837
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1647613837
+transform 1 0 -478 0 1 -537
+box -76 -157 76 157
+use vco_switch_n_v2 vco_switch_n_v2_0
+timestamp 1647613837
+transform 1 0 -1367 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n_v2 vco_switch_n_v2_1
+timestamp 1647613837
+transform 1 0 -721 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n_v2 vco_switch_n_v2_2
+timestamp 1647613837
+transform 1 0 -78 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n_v2 vco_switch_n_v2_3
+timestamp 1647613837
+transform 1 0 568 0 -1 -304
+box 376 462 987 1215
+use vco_switch_p vco_switch_p_0
+timestamp 1647613837
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use vco_switch_p vco_switch_p_1
+timestamp 1647613837
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use vco_switch_p vco_switch_p_2
+timestamp 1647613837
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use vco_switch_p vco_switch_p_3
+timestamp 1647613837
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+rlabel metal1 -1753 -752 -1553 -552 1 vctrl
+port 3 n
+flabel metal1 1633 2181 1833 2381 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+rlabel metal1 -1436 1674 -1404 1706 1 sel0
+port 4 n
+rlabel metal1 -1359 1519 -1327 1551 1 sel1
+port 5 n
+rlabel metal1 -1279 1445 -1247 1477 1 sel2
+port 6 n
+rlabel metal1 -1190 1364 -1158 1396 1 sel3
+port 7 n
+rlabel metal1 -754 -328 -716 -294 1 vgp
+rlabel via1 -86 858 -40 900 1 pg0
+rlabel via1 120 1148 166 1190 1 pg1
+rlabel via1 328 1146 374 1188 1 pg2
+rlabel via1 582 1146 628 1188 1 pg3
+rlabel via1 -86 -404 -40 -362 1 ng0
+rlabel via1 122 -682 168 -640 1 ng1
+rlabel via1 328 -682 374 -640 1 ng2
+rlabel via1 582 -684 628 -642 1 ng3
+rlabel metal1 276 210 306 236 1 net5
+rlabel locali 74 256 104 282 1 net4
+rlabel locali -242 250 -212 276 1 net3
+rlabel locali 1024 230 1054 256 1 net6
+rlabel metal1 -364 -88 -330 -58 1 net8
+rlabel metal1 -360 428 -326 458 1 net2
+rlabel locali 1710 200 1766 228 1 out
+port 2 n
+rlabel locali 1226 215 1256 241 1 net7
+flabel metal1 1893 2441 2093 2641 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.spice b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.spice
new file mode 100755
index 0000000..4cfb3e3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.spice
@@ -0,0 +1,174 @@
+* NGSPICE file created from 3-stage_cs-vco_dp9.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 vdd vss out vctrl sel0 sel1 sel2 sel3
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_POST-LAYOUT_tb.spice b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_POST-LAYOUT_tb.spice
new file mode 100755
index 0000000..9c47629
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_POST-LAYOUT_tb.spice
@@ -0,0 +1,509 @@
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/3-stage_cs-vco_tb.sch
+**.subckt 3-stage_cs-vco_tb vctrl out buf16_out
+*.iopin vctrl
+*.iopin out
+*.iopin buf16_out
+
+*POST-LAYOUT DUT:
+x1 net1 net2 out vctrl sel0 sel1 sel2 sel3 x3-stage_cs-vco_dp9
+
+
+*Adding SEL CONTROL ports sources:
+Vsel0 sel0 GND 0.0
+Vsel1 sel1 GND 0.0
+Vsel2 sel2 GND 0.0
+Vsel3 sel3 GND 0.0
+
+
+
+
+V2 vdd GND 1.8
+Vmeas_current_vdd vdd net1 0
+Vmeas_current_gnd net2 GND 0
+x2 vdd out GND fdiv2_loadmodel
+x3 out GND GND vdd vdd buf1_out sky130_fd_sc_hd__clkbuf_1
+x4 buf1_out GND GND vdd vdd net4 sky130_fd_sc_hd__clkbuf_2
+x5 net4 GND GND vdd vdd net5 sky130_fd_sc_hd__clkbuf_4
+x6 net5 GND GND vdd vdd net3 sky130_fd_sc_hd__clkbuf_8
+x7 net3 GND GND vdd vdd buf16_out sky130_fd_sc_hd__clkbuf_16
+**** begin user architecture code
+
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+*V1 vctrl GND 0.9
+V1 vctrl GND pwl(0, 0, 1n, 0, 1.1n, 0.9, 2n, 0.9, 2.1n, {vcontrol_par})
+
+*.options savecurrents
+
+*Trying to get the syntax right for probing M26 and M7 current:
+*POST-LAYOUT current probes:
+ *.probe tran all @m.x1.xxm26.x0.msky130_fd_pr__nfet_01v8[id]
+ *.save tran all @m.x1.xxm26.x0.msky130_fd_pr__nfet_01v8[id]
+ *.probe tran all @m.x1.xxm16.x0.msky130_fd_pr__nfet_01v8[id]
+ *.save tran all @m.x1.xxm16.x0.msky130_fd_pr__nfet_01v8[id]
+ *.probe tran all @m.x1.xxm16b.x0.msky130_fd_pr__nfet_01v8[id]
+ *.save tran all @m.x1.xxm16b.x0.msky130_fd_pr__nfet_01v8[id]
+
+
+
+*Instantiate Ring Osc Parasitic Caps:
+*This worked BUT it gave slightly different Fvco numbers, some gmin convergence.
+*Better to put the parasitic caps inside the VCO subcircuit.
+*Cnet10 x1.net10 x1.vss {paracap}
+*Cnet9 x1.net9 x1.vss {0.686*paracap}
+*Cnet8 x1.net8 x1.vss {0.628*paracap}
+
+
+
+
+.control
+
+
+let do_vctrl_sweep = 1
+let do_dimensions_sweep = 0
+let do_2dimensions_sweep = 0
+let do_paracap_sweep = 0
+
+
+.param vcontrol_par = 0.9
+.param paracap = 2.93f
+
+
+
+*-------------------------------
+*DP5 dimensions:
+.param W_delay_pmos = 0.5
+.param W_delay_nmos = 0.36
+.param M21_W = 0.58
+.param M22_W =0.36
+.param L_of_mirrors = 0.18
+.param W_of_mirrors = 2.4
+.param W_of_input_mirror = 1
+*-------------------------------
+
+*-------------------------------
+*DP6 dimensions:
+.param W_delay_pmos = 0.5
+.param W_delay_nmos = 0.36
+*.param M5_and_M6_multiple = 1
+*Strong M5 M6:
+.param M5_and_M6_multiple = 4
+.param L_of_mirrors = 0.18
+*.param W_of_mirrors = 2.4
+.param W_of_mirrors = 19.2
+.param W_of_input_mirror = 1
+*-------------------------------
+
+
+*-------------------------------
+*DP6 with M5/M6 optimization:
+.param W_delay_pmos = 0.5
+.param W_delay_nmos = 0.36
+*.param M5_and_M6_multiple = 1
+*Strong M5 M6:
+.param M5_and_M6_multiple = 4
+.param L_of_mirrors = 0.18
+.param W_of_mirrors = 2.4
+.param W_of_input_mirror = 1
+.param W_m5 = 0.5
+.param W_m6 = 0.36
+*-------------------------------
+
+
+
+*This is to parameterize transient step/stop/start times
+*using variables:
+set t_start = 0
+set t_step = 10p
+let expected_frequency_vec = 1G
+let nperiods_vec = 70
+let t_stop_vec = nperiods_vec / expected_frequency_vec
+set t_stop = $&t_stop_vec
+
+*-----------------------
+*SEE IF THIS DOESN'T BREAK IT:
+*Trying to sync the params with the variables:
+*Just for the measure statements:
+.param t_start_par = 0
+.param t_step_par = 10p
+.param t_stop_par = 100n
+alterparam t_start_par = $t_start
+alterparam t_step_par = $t_step
+alterparam t_stop_par = $t_stop
+reset
+*-----------------------
+
+
+
+
+if do_vctrl_sweep = 1
+ *-------- WHILE LOOP FOR VCTRL SWEEP-----------------
+ let start_vctrl = 0.0
+ let stop_vctrl = 1.81
+ let increment = 0.1
+ let vctrl_next = start_vctrl
+
+ let debug_1 = 1234
+ let debug_2 = 5678
+
+ let iteration = 1
+
+ while vctrl_next le stop_vctrl
+
+ *alter V1 dc = vctrl_next
+ set vctrl_next_var = $&vctrl_next
+ alterparam vcontrol_par = $vctrl_next_var
+ reset
+
+ *This for fast frequencies:
+ *tran 10ps 100ns
+
+ *This for slow frequencies:
+ *tran 1000ps 100000ns
+
+ *This is using the (set) variables:
+ tran $t_step $t_stop $t_start
+
+ *This is to TRY to parameterize the tran
+ *using the global params BUT it doesn't seem
+ *to work if the tran is inside the .control.
+ *tran 't_step_par' 't_stop_par'
+
+
+ let vctrl_next = vctrl_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_vctrl_sweep = 1
+
+
+
+if do_dimensions_sweep = 1
+ *-------- WHILE LOOP FOR DIMENSIONS SWEEP-----------------
+ let start_w = 1
+ let stop_w = 8.1
+ let increment = 1
+ let w_next = start_w
+ *let w_next_extra_for_the_nmos = 0.36
+
+ let iteration = 1
+
+ while w_next le stop_w
+
+ set w_next_var = $&w_next
+
+
+ *----------------------------
+ *Trying to see if wider delay cell devices can charge parasitic caps better
+ *set w_next_var_extra_for_the_nmos = $&w_next_extra_for_the_nmos
+ *alterparam W_delay_pmos = $w_next_var
+ *alterparam W_delay_nmos = $w_next_var_extra_for_the_nmos
+ *Maybe I should increase the Para Cap when I increase the devices...
+ *The RESET is required after the alterparam (manual says)
+ *reset
+ *----------------------------
+
+ *----------------------------
+ *Trying to see if making M5 and M6 stronger helps
+ alterparam M5_and_M6_multiple = $w_next_var
+ reset
+ *----------------------------
+
+ *alterparam W_delay_pmos = 0.42
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam M21_W = 2.88
+ *alterparam M22_W = 1.44
+ *reset
+
+
+ *alterparam M21_W = $w_next_var
+ *alterparam M22_W = {$w_next_var / 2}
+ *reset
+
+
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+ *alterparam M21_W = 0.58
+ *alterparam M22_W = 0.36
+ *reset
+
+
+ *----------------------------------
+ *Trying to extend Vctrl range:
+ *----------------------------------
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam W_of_mirrors = $w_next_var
+ *alterparam W_of_input_mirror = { $w_next_var * 1.01 / 2.4 }
+ *alterparam vcontrol_par = 0.7
+ *reset
+
+ *----------------------------------
+ *Measure M26 current at Vctrl 0.7 in DP5
+
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam W_of_mirrors = 2.4
+ *alterparam W_of_input_mirror = 1.01
+ *alterparam vcontrol_par = 0.7
+ *reset
+ *----------------------------------
+
+ *----------------------------
+ *Trying more current in mirrors to see if that can charge para caps faster
+ *alterparam W_of_mirrors = $w_next_var
+ *reset
+ *----------------------------
+
+
+
+ tran $t_step $t_stop $t_start
+ *tran 't_step_par' 't_stop_par'
+
+ print iteration
+ echo Width_In_This_Iteration = $w_next_var
+
+ let w_next = w_next + increment
+ *let w_next_extra_for_the_nmos = w_next_extra_for_the_nmos + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_dimensions_sweep = 1
+
+
+
+if do_paracap_sweep = 1
+ *-------- WHILE LOOP FOR RING OSC PARASITIC CAPS SWEEP-----------------
+ let start_paracap = 0f
+ let stop_paracap = 3.1f
+ let increment = 1f
+ let paracap_next = start_paracap
+
+ let iteration = 1
+
+ while paracap_next le stop_paracap
+
+ set paracap_next_var = $¶cap_next
+
+ alterparam paracap = $paracap_next_var
+ reset
+
+ tran $t_step $t_stop $t_start
+ *tran 't_step_par' 't_stop_par'
+
+ print iteration
+ echo paracap = $paracap_next_var
+
+ let paracap_next = paracap_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+ end
+
+end
+*-------------- END SWEEP PARA CAP -----------------
+
+
+
+
+if do_2dimensions_sweep = 1
+ *-------- WHILE LOOP FOR 2 DIMENSIONS SWEEP-----------------
+ let start_w_pmos = 0.6
+ let stop_w_pmos = 2.61
+ let increment_w_pmos = 0.2
+ let w_next_pmos = start_w_pmos
+
+ let start_w_nmos = 0.6
+ let stop_w_nmos = 1.61
+ let increment_w_nmos = 0.2
+ let w_next_nmos = start_w_nmos
+
+ let iteration = 1
+
+ set w_next_pmos_var = $&start_w_pmos
+ set w_next_nmos_var = $&start_w_nmos
+
+ while w_next_pmos le stop_w_pmos
+
+
+ while w_next_nmos le stop_w_nmos
+
+ alterparam W_m5 = $w_next_pmos_var
+ alterparam W_m6 = $w_next_nmos_var
+ reset
+
+ tran $t_step $t_stop $t_start
+
+ print iteration
+ echo Width_PMOS_In_This_Iteration = $w_next_pmos_var
+ echo Width_NMOS_In_This_Iteration = $w_next_nmos_var
+
+ let w_next_nmos = w_next_nmos + increment_w_nmos
+ set w_next_nmos_var = $&w_next_nmos
+ let iteration = iteration + 1
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+ end $ end inner nmos while loop
+
+
+ let w_next_pmos = w_next_pmos + increment_w_pmos
+ set w_next_pmos_var = $&w_next_pmos
+
+ let w_next_nmos = start_w_nmos
+ set w_next_nmos_var = $&w_next_nmos
+
+
+ end $ end outer pmos while loop
+
+end $end the IF do_2dimensions_sweep = 1
+*-------- END LOOP FOR 2 DIMENSIONS SWEEP-----------------
+
+
+
+
+.endc
+
+
+
+
+
+*THESE WORK:
+.meas tran Tvco_OUTSIDE_WHILE TRIG v(out) VAL=0.5*1.8 RISE=50 TARG v(out) VAL=0.5*1.8 RISE=51
+*.meas tran Tvco_OUTSIDE_WHILE TRIG v(out) VAL=0.5*1.8 RISE=4 TARG v(out) VAL=0.5*1.8 RISE=5
+.meas tran fvco_OUTSIDE_WHILE PARAM='1/Tvco_OUTSIDE_WHILE'
+.meas tran Supply_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_vdd) FROM=10e-9 TO=40e-9
+.meas tran Ground_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_gnd) FROM=10e-9 TO=40e-9
+.meas tran vctrl_avg_OUTSIDE_WHILE AVG v(vctrl) FROM=10e-9 TO=20e-9
+.meas tran vhigh_OUTSIDE_WHILE MAX v(out) FROM=10e-9 TO=20e-9
+.meas tran vlow_OUTSIDE_WHILE MIN v(out) FROM=10e-9 TO=20e-9
+.meas tran peak_to_peak_OUTSIDE_WHILE PARAM='vhigh_OUTSIDE_WHILE-vlow_OUTSIDE_WHILE'
+
+.meas tran supply_current_rms RMS i(vmeas_current_vdd) FROM='t_start_par' TO='t_stop_par'
+
+*IF NORMAL circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+ *.meas tran m7_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+*IF LVT circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_lvt_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2'
++ TO='t_stop_par'
+ *.meas tran m7_lvt_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2' TO='t_stop_par'
+
+
+
+
+
+**** end user architecture code
+**.ends
+
+
+
+
+
+*POST-LAYOUT DUT EXTRACTED NETLISTS:
+
+
+
+*------------------------------------------------------------------
+*THESE ARE NETLISTS FOR DP9 POST-LAYOUT WITH CONTROL PORTS
+.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.spice
+
+*------------------------------------------------------------------
+
+
+
+
+*------------------------------------------------------------------
+*THESE ARE THE NETLISTS FOR DP7 LAYOUT, GUTFEEL, GUTFEEL_V2/V3.
+*REMEMBER GUTFEEL_V2 IS SAME AS DP9 WITHOUT CONTROL PORTS.
+
+*This is the FULL POST-LAYOUT netlist for DP7:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dp7.spice
+
+*This is DP8 LAYOUT which is like DP7 but with just one 4.8um mirror instead of 2x, to make it less abrupt
+*since it appeared like faster in layout that in Sch.
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dp8.spice
+
+*This is DP_GUTFEEL layout as it looked decent on SCH sim with paracaps (y eso que era a ojillo)
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dpgutfeel.spice
+
+*This is DP_GUTFEEL_v2 layout which is same as GUTFEEL but just 1x 4.8um mirror overall, like DP8 in that sense
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dpgutfeel_v2.spice
+
+*This is DP_GUTFEEL_v3 layout which is same as GUTFEEL and _V2 but just 1x 2.4um mirror overall,
+*like this would be 0.5x the current of GUTFEEL_V2, the goal is to save current.
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dpgutfeel_v3.spice
+
+*------------------------------------------------------------------
+
+
+
+
+*---------------------------------------------------------------------
+*THESE ARE DP5 NETLISTS I USED TO UNDERSTAND FREQUENCY DROP DUE TO PARASITIC CAPS IN RING OSC:
+*These are netlists to debug the cap on which net degrades the speed (net10, net9, net8):
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET10_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET9_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET8_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET10_NET9_NET8_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ALL_TOP_LEVEL_SUBCKT_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ALL_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_DELAY_CELL_TRANS_SUBCKT_CAPS_INSERTED.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_NET10_NET9_NET8_TOP_LEVEL_SUBCKT_CAPS_INSERTED.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_NET10_NET9_NET8_TOP_LEVEL_AND_TRANSISTOR_SUBCKT_CAPS_INSERTED.spice
+
+*This is Layout with LI on delay cells, full extracted layout:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_li/3-stage_cs-vco_dp5_li.spice
+
+*This is Layout with LI on delay cells (v2 is with rotated FETs on delay cells, some more LI, etc), full extracted layout:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_li_v2/3-stage_cs-vco_dp5_li_v2.spice
+*---------------------------------------------------------------------
+
+
+
+
+
+
+* expanding symbol: fdiv2_loadmodel.sym # of pins=3
+** sym_path: /home/darunix/GitSandboxes/VCO/vco/xschem/fdiv2_loadmodel.sym
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/fdiv2_loadmodel.sch
+.subckt fdiv2_loadmodel vdd clk vss
+*.ipin clk
+*.iopin vdd
+*.iopin vss
+XM3 vdd clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 vss clk vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.36 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 vss clk vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 vdd clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p125_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p125_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..04cee54
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p125_POST-LAYOUT_tb.log
@@ -0,0 +1,1563 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.45044e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.74357e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.282756e-06 at= 1.046500e-08
+vlow_outside_while = -3.268921e-06 at= 1.045500e-08
+peak_to_peak_outside_while= 6.55168e-06
+supply_current_rms = 4.93030e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 5.79493e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.79898e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.120739e-06 at= 1.073500e-08
+vlow_outside_while = -2.106574e-06 at= 1.074500e-08
+peak_to_peak_outside_while= 4.22731e-06
+supply_current_rms = 7.19837e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.00159e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.51033e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.305597e-06 at= 1.069500e-08
+vlow_outside_while = -3.291331e-06 at= 1.068500e-08
+peak_to_peak_outside_while= 6.59693e-06
+supply_current_rms = 7.32293e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.96575e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.63321e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.502476e-06 at= 1.001500e-08
+vlow_outside_while = -2.768660e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 6.27114e-06
+supply_current_rms = 5.06429e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.61733e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.52479e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 7.383879e-07 at= 1.045500e-08
+vlow_outside_while = -7.244229e-07 at= 1.044500e-08
+peak_to_peak_outside_while= 1.46281e-06
+supply_current_rms = 5.33981e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.51019e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.76534e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.290746e-06 at= 1.388500e-08
+vlow_outside_while = -1.111609e-06 at= 1.211500e-08
+peak_to_peak_outside_while= 2.40236e-06
+supply_current_rms = 5.48683e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 8.66225e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.03177e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926349e+00 at= 1.416500e-08
+vlow_outside_while = -7.607944e-02 at= 1.936500e-08
+peak_to_peak_outside_while= 2.00243e+00
+supply_current_rms = 9.26284e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 1.219275e-09 targ= 5.727549e-08 trig= 5.605621e-08
+fvco_outside_while = 8.20159e+08
+supply_current_rms_outside_while= 1.52863e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.75645e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927590e+00 at= 1.146500e-08
+vlow_outside_while = -8.358438e-02 at= 1.892500e-08
+peak_to_peak_outside_while= 2.01117e+00
+supply_current_rms = 1.60002e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.550529e-10 targ= 2.903311e-08 trig= 2.847806e-08
+fvco_outside_while = 1.80163e+09
+supply_current_rms_outside_while= 2.21881e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.42489e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928091e+00 at= 1.262500e-08
+vlow_outside_while = -8.416978e-02 at= 1.790500e-08
+peak_to_peak_outside_while= 2.01226e+00
+supply_current_rms = 2.20979e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.723450e-10 targ= 2.031834e-08 trig= 1.994599e-08
+fvco_outside_while = 2.68568e+09
+supply_current_rms_outside_while= 3.23747e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.29682e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928581e+00 at= 1.677500e-08
+vlow_outside_while = -8.323504e-02 at= 1.321500e-08
+peak_to_peak_outside_while= 2.01182e+00
+supply_current_rms = 3.19775e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.213757e-10 targ= 1.782538e-08 trig= 1.750400e-08
+fvco_outside_while = 3.11162e+09
+supply_current_rms_outside_while= 4.01999e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.99814e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928540e+00 at= 1.186500e-08
+vlow_outside_while = -8.228328e-02 at= 1.908500e-08
+peak_to_peak_outside_while= 2.01082e+00
+supply_current_rms = 3.95742e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.067518e-10 targ= 1.709735e-08 trig= 1.679060e-08
+fvco_outside_while = 3.25996e+09
+supply_current_rms_outside_while= 4.41493e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.42932e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928154e+00 at= 1.753500e-08
+vlow_outside_while = -8.162204e-02 at= 1.952500e-08
+peak_to_peak_outside_while= 2.00978e+00
+supply_current_rms = 4.35011e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.999080e-10 targ= 1.675532e-08 trig= 1.645541e-08
+fvco_outside_while = 3.33436e+09
+supply_current_rms_outside_while= 1.22433e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.32445e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928053e+00 at= 1.298500e-08
+vlow_outside_while = -7.868092e-02 at= 1.013500e-08
+peak_to_peak_outside_while= 2.00673e+00
+supply_current_rms = 1.55254e-03 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.961271e-10 targ= 1.656999e-08 trig= 1.627386e-08
+fvco_outside_while = 3.37693e+09
+supply_current_rms_outside_while= 4.86435e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.87383e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928173e+00 at= 1.699500e-08
+vlow_outside_while = -7.988881e-02 at= 1.980500e-08
+peak_to_peak_outside_while= 2.00806e+00
+supply_current_rms = 4.79251e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.941737e-10 targ= 1.644394e-08 trig= 1.614977e-08
+fvco_outside_while = 3.39935e+09
+supply_current_rms_outside_while= 4.93905e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.94981e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928210e+00 at= 1.745500e-08
+vlow_outside_while = -7.907816e-02 at= 1.612500e-08
+peak_to_peak_outside_while= 2.00729e+00
+supply_current_rms = 4.87049e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.920152e-10 targ= 1.634927e-08 trig= 1.605725e-08
+fvco_outside_while = 3.42448e+09
+supply_current_rms_outside_while= 5.00395e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.01123e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928236e+00 at= 1.180500e-08
+vlow_outside_while = -7.838218e-02 at= 1.778500e-08
+peak_to_peak_outside_while= 2.00662e+00
+supply_current_rms = 4.93683e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.906387e-10 targ= 1.627563e-08 trig= 1.598499e-08
+fvco_outside_while = 3.44070e+09
+supply_current_rms_outside_while= 5.05101e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.06348e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928257e+00 at= 1.204500e-08
+vlow_outside_while = -7.784299e-02 at= 1.799500e-08
+peak_to_peak_outside_while= 2.00610e+00
+supply_current_rms = 4.97843e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.896241e-10 targ= 1.621650e-08 trig= 1.592687e-08
+fvco_outside_while = 3.45275e+09
+supply_current_rms_outside_while= 5.08428e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.09589e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928276e+00 at= 1.750500e-08
+vlow_outside_while = -7.738412e-02 at= 1.387500e-08
+peak_to_peak_outside_while= 2.00566e+00
+supply_current_rms = 5.00932e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.74924e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net5 1.77531
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.886767e-10 targ= 1.616772e-08 trig= 1.587905e-08
+fvco_outside_while = 3.46408e+09
+supply_current_rms_outside_while= 5.11942e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.11167e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928300e+00 at= 1.485500e-08
+vlow_outside_while = -7.700404e-02 at= 1.152500e-08
+peak_to_peak_outside_while= 2.00530e+00
+supply_current_rms = 5.04807e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.886767e-10 targ= 1.616772e-08 trig= 1.587905e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.464083085556678e+09 " u=" 3.464083085556678e+09 " id=0
+fvco_outside_while = 3.46408e+09
+supply_current_rms_outside_while= 5.11942e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.11167e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928300e+00 at= 1.485500e-08
+vlow_outside_while = -7.700404e-02 at= 1.152500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.005303996255893e+00 " u=" 2.005303996255893e+00 " id=0
+peak_to_peak_outside_while= 2.00530e+00
+supply_current_rms = 5.04807e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 10.0878
+
+Total CPU time (seconds) = 201.913
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 129.441 MB.
+Maximum ngspice program size = 684.824 MB.
+Current ngspice program size = 666.086 MB.
+
+Shared ngspice pages = 8.977 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.340 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p125_XM22_0p42_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p125_XM22_0p42_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..a14793a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p125_XM22_0p42_POST-LAYOUT_tb.log
@@ -0,0 +1,1563 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.60502e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.21812e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.685082e-06 at= 1.000500e-08
+vlow_outside_while = -2.663742e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 5.34882e-06
+supply_current_rms = 5.02593e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.82300e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.02051e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.234558e-05 at= 1.000500e-08
+vlow_outside_while = -1.231343e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 2.46590e-05
+supply_current_rms = 5.45163e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.90731e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.65320e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.445580e-05 at= 1.000500e-08
+vlow_outside_while = -1.442448e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 2.88803e-05
+supply_current_rms = 5.47040e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.92312e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.59308e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 4.260241e-06 at= 1.000500e-08
+vlow_outside_while = -4.230769e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 8.49101e-06
+supply_current_rms = 5.08798e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.15766e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.99497e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.325977e-06 at= 1.000500e-08
+vlow_outside_while = -8.295543e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.66215e-05
+supply_current_rms = 5.58374e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.80296e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.18746e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 4.022084e-06 at= 1.001500e-08
+vlow_outside_while = -4.019306e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 8.04139e-06
+supply_current_rms = 5.96467e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.67407e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.04816e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926822e+00 at= 1.419500e-08
+vlow_outside_while = -8.685949e-02 at= 1.940500e-08
+peak_to_peak_outside_while= 2.01368e+00
+supply_current_rms = 8.39790e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 1.220333e-09 targ= 5.733917e-08 trig= 5.611884e-08
+fvco_outside_while = 8.19449e+08
+supply_current_rms_outside_while= 1.64451e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.47914e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929086e+00 at= 1.367500e-08
+vlow_outside_while = -8.740907e-02 at= 1.666500e-08
+peak_to_peak_outside_while= 2.01649e+00
+supply_current_rms = 1.71008e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.561425e-10 targ= 2.907698e-08 trig= 2.852084e-08
+fvco_outside_while = 1.79810e+09
+supply_current_rms_outside_while= 2.98916e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.23886e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929854e+00 at= 1.208500e-08
+vlow_outside_while = -8.789232e-02 at= 1.236500e-08
+peak_to_peak_outside_while= 2.01775e+00
+supply_current_rms = 2.85982e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.729117e-10 targ= 2.034901e-08 trig= 1.997610e-08
+fvco_outside_while = 2.68160e+09
+supply_current_rms_outside_while= 3.29776e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.29582e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.930230e+00 at= 1.530500e-08
+vlow_outside_while = -8.686830e-02 at= 1.808500e-08
+peak_to_peak_outside_while= 2.01710e+00
+supply_current_rms = 3.25313e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.216990e-10 targ= 1.785832e-08 trig= 1.753662e-08
+fvco_outside_while = 3.10850e+09
+supply_current_rms_outside_while= 4.02831e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.01324e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.930097e+00 at= 1.574500e-08
+vlow_outside_while = -8.590436e-02 at= 1.815500e-08
+peak_to_peak_outside_while= 2.01600e+00
+supply_current_rms = 3.97393e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.070522e-10 targ= 1.713027e-08 trig= 1.682322e-08
+fvco_outside_while = 3.25678e+09
+supply_current_rms_outside_while= 4.46822e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.45032e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929773e+00 at= 1.879500e-08
+vlow_outside_while = -8.527933e-02 at= 1.710500e-08
+peak_to_peak_outside_while= 2.01505e+00
+supply_current_rms = 4.40441e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.004545e-10 targ= 1.678842e-08 trig= 1.648797e-08
+fvco_outside_while = 3.32829e+09
+supply_current_rms_outside_while= 4.91797e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.90567e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929785e+00 at= 1.150500e-08
+vlow_outside_while = -8.455985e-02 at= 1.195500e-08
+peak_to_peak_outside_while= 2.01434e+00
+supply_current_rms = 4.84125e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.965687e-10 targ= 1.660197e-08 trig= 1.630540e-08
+fvco_outside_while = 3.37190e+09
+supply_current_rms_outside_while= 4.93501e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.89117e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929759e+00 at= 1.316500e-08
+vlow_outside_while = -8.356754e-02 at= 1.479500e-08
+peak_to_peak_outside_while= 2.01333e+00
+supply_current_rms = 4.86269e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.949554e-10 targ= 1.647564e-08 trig= 1.618069e-08
+fvco_outside_while = 3.39034e+09
+supply_current_rms_outside_while= 4.97953e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.97725e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929789e+00 at= 1.159500e-08
+vlow_outside_while = -8.271477e-02 at= 1.026500e-08
+peak_to_peak_outside_while= 2.01250e+00
+supply_current_rms = 4.91212e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.925360e-10 targ= 1.638041e-08 trig= 1.608787e-08
+fvco_outside_while = 3.41838e+09
+supply_current_rms_outside_while= 5.04090e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.04007e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929832e+00 at= 1.299500e-08
+vlow_outside_while = -8.202431e-02 at= 1.957500e-08
+peak_to_peak_outside_while= 2.01186e+00
+supply_current_rms = 4.97294e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.911407e-10 targ= 1.630662e-08 trig= 1.601548e-08
+fvco_outside_while = 3.43476e+09
+supply_current_rms_outside_while= 5.09257e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.08317e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929862e+00 at= 1.672500e-08
+vlow_outside_while = -8.145274e-02 at= 1.715500e-08
+peak_to_peak_outside_while= 2.01132e+00
+supply_current_rms = 5.02101e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.900933e-10 targ= 1.624616e-08 trig= 1.595607e-08
+fvco_outside_while = 3.44717e+09
+supply_current_rms_outside_while= 5.11892e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.13273e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929885e+00 at= 1.985500e-08
+vlow_outside_while = -7.757051e-02 at= 1.999500e-08
+peak_to_peak_outside_while= 2.00746e+00
+supply_current_rms = 5.04892e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.70206e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67848
+vctrl 0
+x1.net8 0.870271
+x1.ng3 9.63187e-09
+x1.net5 1.77531
+x1.ng0 9.63187e-09
+x1.vco_switch_n_v2_0/selb 1.8
+sel0 0
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.870271
+x1.net2 1.76679
+x1.net4 0.698728
+x1.pg3 1.8
+x1.pg0 1.8
+x1.vco_switch_p_0/selb 1.8
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.76416e-11
+vmeas_current_gnd#branch 2.14689e-05
+vmeas_current_vdd#branch 2.14689e-05
+v2#branch -2.1469e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.892783e-10 targ= 1.619846e-08 trig= 1.590918e-08
+fvco_outside_while = 3.45688e+09
+supply_current_rms_outside_while= 5.15036e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.15425e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929891e+00 at= 1.314500e-08
+vlow_outside_while = -8.055922e-02 at= 1.906500e-08
+peak_to_peak_outside_while= 2.01045e+00
+supply_current_rms = 5.07799e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.892783e-10 targ= 1.619846e-08 trig= 1.590918e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.456879064059381e+09 " u=" 3.456879064059381e+09 " id=0
+fvco_outside_while = 3.45688e+09
+supply_current_rms_outside_while= 5.15036e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.15425e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929891e+00 at= 1.314500e-08
+vlow_outside_while = -8.055922e-02 at= 1.906500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.010450557855210e+00 " u=" 2.010450557855210e+00 " id=0
+peak_to_peak_outside_while= 2.01045e+00
+supply_current_rms = 5.07799e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 11.9791
+
+Total CPU time (seconds) = 286.471
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 2314.594 MB.
+Maximum ngspice program size = 684.809 MB.
+Current ngspice program size = 665.219 MB.
+
+Shared ngspice pages = 8.133 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.324 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p25_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p25_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..c934580
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p25_POST-LAYOUT_tb.log
@@ -0,0 +1,1563 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.05613e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.62155e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 7.025800e-07 at= 1.001500e-08
+vlow_outside_while = -4.252659e-07 at= 1.000500e-08
+peak_to_peak_outside_while= 1.12785e-06
+supply_current_rms = 5.68618e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.28402e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.71940e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.841604e-06 at= 1.001500e-08
+vlow_outside_while = -8.843895e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 1.76855e-05
+supply_current_rms = 7.97736e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 5.53439e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.14628e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.629707e-06 at= 1.000500e-08
+vlow_outside_while = -8.597268e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.72270e-05
+supply_current_rms = 7.57548e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 7.51943e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.38729e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.396429e-06 at= 1.001500e-08
+vlow_outside_while = -2.396714e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 4.79314e-06
+supply_current_rms = 8.85055e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.98329e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.10136e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.434116e-06 at= 1.001500e-08
+vlow_outside_while = -2.017900e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 4.45202e-06
+supply_current_rms = 6.06247e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.08605e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.53544e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 9.649351e-06 at= 1.000500e-08
+vlow_outside_while = -9.626865e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.92762e-05
+supply_current_rms = 6.46940e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.29646e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 9.60723e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927910e+00 at= 1.348500e-08
+vlow_outside_while = -8.329762e-02 at= 1.321500e-08
+peak_to_peak_outside_while= 2.01121e+00
+supply_current_rms = 1.03902e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 8.200376e-10 targ= 4.025589e-08 trig= 3.943586e-08
+fvco_outside_while = 1.21946e+09
+supply_current_rms_outside_while= 1.84693e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.90656e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927920e+00 at= 1.531500e-08
+vlow_outside_while = -8.363308e-02 at= 1.984500e-08
+peak_to_peak_outside_while= 2.01155e+00
+supply_current_rms = 2.31236e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 4.144382e-10 targ= 2.247902e-08 trig= 2.206458e-08
+fvco_outside_while = 2.41291e+09
+supply_current_rms_outside_while= 2.85780e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.78834e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928235e+00 at= 1.144500e-08
+vlow_outside_while = -8.431197e-02 at= 1.457500e-08
+peak_to_peak_outside_while= 2.01255e+00
+supply_current_rms = 2.82423e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.117599e-10 targ= 1.746479e-08 trig= 1.715303e-08
+fvco_outside_while = 3.20760e+09
+supply_current_rms_outside_while= 3.86477e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.85405e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928057e+00 at= 1.603500e-08
+vlow_outside_while = -8.287037e-02 at= 1.432500e-08
+peak_to_peak_outside_while= 2.01093e+00
+supply_current_rms = 3.81097e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.938028e-10 targ= 1.656001e-08 trig= 1.626621e-08
+fvco_outside_while = 3.40364e+09
+supply_current_rms_outside_while= 4.35021e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.33586e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927215e+00 at= 1.079500e-08
+vlow_outside_while = -8.202671e-02 at= 1.506500e-08
+peak_to_peak_outside_while= 2.00924e+00
+supply_current_rms = 4.28720e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.850914e-10 targ= 1.606494e-08 trig= 1.577985e-08
+fvco_outside_while = 3.50765e+09
+supply_current_rms_outside_while= 4.74465e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.71483e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926757e+00 at= 1.418500e-08
+vlow_outside_while = -8.110428e-02 at= 1.575500e-08
+peak_to_peak_outside_while= 2.00786e+00
+supply_current_rms = 4.67260e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.790268e-10 targ= 1.577026e-08 trig= 1.549123e-08
+fvco_outside_while = 3.58389e+09
+supply_current_rms_outside_while= 5.22855e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.00152e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926569e+00 at= 1.476500e-08
+vlow_outside_while = -8.041709e-02 at= 1.881500e-08
+peak_to_peak_outside_while= 2.00699e+00
+supply_current_rms = 5.13770e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.760857e-10 targ= 1.587558e-08 trig= 1.559949e-08
+fvco_outside_while = 3.62206e+09
+supply_current_rms_outside_while= 5.14872e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.13950e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926541e+00 at= 1.019500e-08
+vlow_outside_while = -7.954191e-02 at= 1.557500e-08
+peak_to_peak_outside_while= 2.00608e+00
+supply_current_rms = 5.07645e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.734010e-10 targ= 1.576064e-08 trig= 1.548724e-08
+fvco_outside_while = 3.65763e+09
+supply_current_rms_outside_while= 5.23104e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.21809e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926521e+00 at= 1.696500e-08
+vlow_outside_while = -7.892371e-02 at= 1.026500e-08
+peak_to_peak_outside_while= 2.00544e+00
+supply_current_rms = 5.15498e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.718749e-10 targ= 1.567936e-08 trig= 1.540748e-08
+fvco_outside_while = 3.67816e+09
+supply_current_rms_outside_while= 5.28488e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.27383e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926493e+00 at= 1.932500e-08
+vlow_outside_while = -7.846929e-02 at= 1.021500e-08
+peak_to_peak_outside_while= 2.00496e+00
+supply_current_rms = 5.21327e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.707615e-10 targ= 1.561871e-08 trig= 1.534795e-08
+fvco_outside_while = 3.69329e+09
+supply_current_rms_outside_while= 5.33174e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.32317e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926527e+00 at= 1.789500e-08
+vlow_outside_while = -7.812532e-02 at= 1.261500e-08
+peak_to_peak_outside_while= 2.00465e+00
+supply_current_rms = 5.25555e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.699146e-10 targ= 1.557347e-08 trig= 1.530356e-08
+fvco_outside_while = 3.70488e+09
+supply_current_rms_outside_while= 5.37077e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.35532e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926524e+00 at= 1.001500e-08
+vlow_outside_while = -7.601775e-02 at= 1.986500e-08
+peak_to_peak_outside_while= 2.00254e+00
+supply_current_rms = 5.28741e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16221e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net5 1.79999
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.692925e-10 targ= 1.553575e-08 trig= 1.526645e-08
+fvco_outside_while = 3.71343e+09
+supply_current_rms_outside_while= 5.39514e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.38203e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926548e+00 at= 1.914500e-08
+vlow_outside_while = -7.762978e-02 at= 1.416500e-08
+peak_to_peak_outside_while= 2.00418e+00
+supply_current_rms = 5.31855e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.692925e-10 targ= 1.553575e-08 trig= 1.526645e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.713433935801915e+09 " u=" 3.713433935801915e+09 " id=0
+fvco_outside_while = 3.71343e+09
+supply_current_rms_outside_while= 5.39514e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.38203e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926548e+00 at= 1.914500e-08
+vlow_outside_while = -7.762978e-02 at= 1.416500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.004178094097200e+00 " u=" 2.004178094097200e+00 " id=0
+peak_to_peak_outside_while= 2.00418e+00
+supply_current_rms = 5.31855e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 10.2395
+
+Total CPU time (seconds) = 203.646
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 117.641 MB.
+Maximum ngspice program size = 684.824 MB.
+Current ngspice program size = 665.957 MB.
+
+Shared ngspice pages = 8.852 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.340 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p25_XM22_0p42_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p25_XM22_0p42_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..965ec50
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p25_XM22_0p42_POST-LAYOUT_tb.log
@@ -0,0 +1,1563 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.70415e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.84818e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 7.148989e-06 at= 1.000500e-08
+vlow_outside_while = -5.816138e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.29651e-05
+supply_current_rms = 6.47230e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.78173e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.57157e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 9.085991e-06 at= 1.000500e-08
+vlow_outside_while = -9.063840e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.81498e-05
+supply_current_rms = 5.62956e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.71180e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.48885e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.172318e-06 at= 1.001500e-08
+vlow_outside_while = -8.170118e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 1.63424e-05
+supply_current_rms = 5.58966e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.19866e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.82371e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.469881e-06 at= 1.000500e-08
+vlow_outside_while = -6.813848e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.52837e-05
+supply_current_rms = 6.74489e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.44014e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.00485e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 7.805722e-06 at= 1.000500e-08
+vlow_outside_while = -7.770741e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.55765e-05
+supply_current_rms = 5.49509e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.85891e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.94918e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 6.633867e-06 at= 1.001500e-08
+vlow_outside_while = -6.625066e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 1.32589e-05
+supply_current_rms = 6.25657e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.11475e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.06769e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927379e+00 at= 1.687500e-08
+vlow_outside_while = -8.534463e-02 at= 1.323500e-08
+peak_to_peak_outside_while= 2.01272e+00
+supply_current_rms = 9.96616e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 8.209290e-10 targ= 4.030826e-08 trig= 3.948733e-08
+fvco_outside_while = 1.21813e+09
+supply_current_rms_outside_while= 2.02276e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.07230e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929501e+00 at= 1.691500e-08
+vlow_outside_while = -8.768217e-02 at= 1.826500e-08
+peak_to_peak_outside_while= 2.01718e+00
+supply_current_rms = 1.96533e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 4.151597e-10 targ= 2.251247e-08 trig= 2.209731e-08
+fvco_outside_while = 2.40871e+09
+supply_current_rms_outside_while= 3.31520e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.80562e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929863e+00 at= 1.685500e-08
+vlow_outside_while = -8.804678e-02 at= 1.293500e-08
+peak_to_peak_outside_while= 2.01791e+00
+supply_current_rms = 3.22330e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.119562e-10 targ= 1.749754e-08 trig= 1.718558e-08
+fvco_outside_while = 3.20558e+09
+supply_current_rms_outside_while= 3.93646e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.88645e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929611e+00 at= 1.793500e-08
+vlow_outside_while = -8.653253e-02 at= 1.934500e-08
+peak_to_peak_outside_while= 2.01614e+00
+supply_current_rms = 3.87597e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.946199e-10 targ= 1.659260e-08 trig= 1.629798e-08
+fvco_outside_while = 3.39420e+09
+supply_current_rms_outside_while= 4.38070e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.34882e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928594e+00 at= 1.346500e-08
+vlow_outside_while = -8.575226e-02 at= 1.391500e-08
+peak_to_peak_outside_while= 2.01435e+00
+supply_current_rms = 4.32008e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.855879e-10 targ= 1.609632e-08 trig= 1.581073e-08
+fvco_outside_while = 3.50155e+09
+supply_current_rms_outside_while= 4.77643e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.73615e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928031e+00 at= 1.506500e-08
+vlow_outside_while = -8.486167e-02 at= 1.521500e-08
+peak_to_peak_outside_while= 2.01289e+00
+supply_current_rms = 4.70934e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.796125e-10 targ= 1.580156e-08 trig= 1.552194e-08
+fvco_outside_while = 3.57638e+09
+supply_current_rms_outside_while= 5.59124e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.20674e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927921e+00 at= 1.898500e-08
+vlow_outside_while = -8.428722e-02 at= 1.689500e-08
+peak_to_peak_outside_while= 2.01221e+00
+supply_current_rms = 5.46063e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.765754e-10 targ= 1.590718e-08 trig= 1.563060e-08
+fvco_outside_while = 3.61565e+09
+supply_current_rms_outside_while= 5.18959e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.15823e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927776e+00 at= 1.297500e-08
+vlow_outside_while = -8.335480e-02 at= 1.864500e-08
+peak_to_peak_outside_while= 2.01113e+00
+supply_current_rms = 5.11270e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.740459e-10 targ= 1.579233e-08 trig= 1.551828e-08
+fvco_outside_while = 3.64902e+09
+supply_current_rms_outside_while= 5.27101e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.24019e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927745e+00 at= 1.891500e-08
+vlow_outside_while = -8.276111e-02 at= 1.960500e-08
+peak_to_peak_outside_while= 2.01051e+00
+supply_current_rms = 5.19224e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.724261e-10 targ= 1.571084e-08 trig= 1.543842e-08
+fvco_outside_while = 3.67072e+09
+supply_current_rms_outside_while= 5.32739e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.30146e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927752e+00 at= 1.336500e-08
+vlow_outside_while = -8.229432e-02 at= 1.132500e-08
+peak_to_peak_outside_while= 2.01005e+00
+supply_current_rms = 5.25124e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.713094e-10 targ= 1.565023e-08 trig= 1.537892e-08
+fvco_outside_while = 3.68583e+09
+supply_current_rms_outside_while= 5.36775e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.34543e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927757e+00 at= 1.331500e-08
+vlow_outside_while = -8.191015e-02 at= 1.752500e-08
+peak_to_peak_outside_while= 2.00967e+00
+supply_current_rms = 5.29414e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.705062e-10 targ= 1.560360e-08 trig= 1.533309e-08
+fvco_outside_while = 3.69677e+09
+supply_current_rms_outside_while= 5.40656e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.38045e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927765e+00 at= 1.841500e-08
+vlow_outside_while = -8.161881e-02 at= 1.936500e-08
+peak_to_peak_outside_while= 2.00938e+00
+supply_current_rms = 5.32729e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12921e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.67179
+vctrl 0
+x1.net8 0.900366
+x1.ng3 9.63187e-09
+x1.net5 1.79999
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 9.63187e-09
+x1.vco_switch_n_v2_1/selb 1.8
+sel1 0
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.900366
+x1.net2 1.78805
+x1.net4 0.374104
+x1.pg3 1.8
+x1.pg0 1.67179
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.8
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 1.8
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.68327e-11
+vmeas_current_gnd#branch 1.43205e-05
+vmeas_current_vdd#branch 1.43206e-05
+v2#branch -1.43207e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.697952e-10 targ= 1.556739e-08 trig= 1.529759e-08
+fvco_outside_while = 3.70651e+09
+supply_current_rms_outside_while= 5.43564e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.40924e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927775e+00 at= 1.459500e-08
+vlow_outside_while = -8.138054e-02 at= 1.230500e-08
+peak_to_peak_outside_while= 2.00916e+00
+supply_current_rms = 5.35096e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.697952e-10 targ= 1.556739e-08 trig= 1.529759e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.706514527843505e+09 " u=" 3.706514527843505e+09 " id=0
+fvco_outside_while = 3.70651e+09
+supply_current_rms_outside_while= 5.43564e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.40924e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927775e+00 at= 1.459500e-08
+vlow_outside_while = -8.138054e-02 at= 1.230500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.009155417828525e+00 " u=" 2.009155417828525e+00 " id=0
+peak_to_peak_outside_while= 2.00916e+00
+supply_current_rms = 5.35096e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 16.0491
+
+Total CPU time (seconds) = 301.170
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 2873.715 MB.
+Maximum ngspice program size = 684.809 MB.
+Current ngspice program size = 666.141 MB.
+
+Shared ngspice pages = 9.055 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.324 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p5_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p5_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..6d9dbd2
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p5_POST-LAYOUT_tb.log
@@ -0,0 +1,1556 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.60947e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.63628e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.706005e-05 at= 1.000500e-08
+vlow_outside_while = -1.702488e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 3.40849e-05
+supply_current_rms = 6.79133e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.82229e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.40602e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.609131e-06 at= 1.080500e-08
+vlow_outside_while = -1.595182e-06 at= 1.079500e-08
+peak_to_peak_outside_while= 3.20431e-06
+supply_current_rms = 8.32553e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.24922e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.91540e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.118626e-06 at= 1.000500e-08
+vlow_outside_while = -8.090762e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.62094e-05
+supply_current_rms = 5.67121e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.23512e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.17464e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 6.730035e-06 at= 1.000500e-08
+vlow_outside_while = -6.695975e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.34260e-05
+supply_current_rms = 6.63671e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 5.83047e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.45419e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.128271e-06 at= 1.415500e-08
+vlow_outside_while = -1.368199e-06 at= 1.610500e-08
+peak_to_peak_outside_while= 3.49647e-06
+supply_current_rms = 7.60103e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.65028e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.81350e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.748517e-02 at= 1.900500e-08
+vlow_outside_while = -2.084944e-02 at= 1.895500e-08
+peak_to_peak_outside_while= 3.83346e-02
+supply_current_rms = 5.82305e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 1.354233e-09 targ= 6.462338e-08 trig= 6.326915e-08
+fvco_outside_while = 7.38425e+08
+supply_current_rms_outside_while= 1.34545e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.30399e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927146e+00 at= 1.416500e-08
+vlow_outside_while = -8.362875e-02 at= 1.682500e-08
+peak_to_peak_outside_while= 2.01077e+00
+supply_current_rms = 1.49412e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.872459e-10 targ= 3.050018e-08 trig= 2.991294e-08
+fvco_outside_while = 1.70286e+09
+supply_current_rms_outside_while= 2.12892e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.46807e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928147e+00 at= 1.265500e-08
+vlow_outside_while = -8.405245e-02 at= 1.579500e-08
+peak_to_peak_outside_while= 2.01220e+00
+supply_current_rms = 2.12727e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.258389e-10 targ= 1.837478e-08 trig= 1.804894e-08
+fvco_outside_while = 3.06900e+09
+supply_current_rms_outside_while= 3.57584e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.57552e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928475e+00 at= 1.233500e-08
+vlow_outside_while = -8.214268e-02 at= 1.281500e-08
+peak_to_peak_outside_while= 2.01062e+00
+supply_current_rms = 3.51720e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.887761e-10 targ= 1.643940e-08 trig= 1.615062e-08
+fvco_outside_while = 3.46289e+09
+supply_current_rms_outside_while= 4.19105e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.18214e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926775e+00 at= 1.597500e-08
+vlow_outside_while = -8.192387e-02 at= 1.410500e-08
+peak_to_peak_outside_while= 2.00870e+00
+supply_current_rms = 4.12694e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.740220e-10 targ= 1.569002e-08 trig= 1.541600e-08
+fvco_outside_while = 3.64934e+09
+supply_current_rms_outside_while= 4.63495e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.59850e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925458e+00 at= 1.332500e-08
+vlow_outside_while = -8.096259e-02 at= 1.374500e-08
+peak_to_peak_outside_while= 2.00642e+00
+supply_current_rms = 4.56515e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.663303e-10 targ= 1.530226e-08 trig= 1.503593e-08
+fvco_outside_while = 3.75474e+09
+supply_current_rms_outside_while= 4.98062e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.95929e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924214e+00 at= 1.033500e-08
+vlow_outside_while = -8.050078e-02 at= 1.074500e-08
+peak_to_peak_outside_while= 2.00471e+00
+supply_current_rms = 4.90365e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.623422e-10 targ= 1.509825e-08 trig= 1.483591e-08
+fvco_outside_while = 3.81181e+09
+supply_current_rms_outside_while= 5.27745e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.18583e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923504e+00 at= 1.125500e-08
+vlow_outside_while = -8.020317e-02 at= 1.822500e-08
+peak_to_peak_outside_while= 2.00371e+00
+supply_current_rms = 5.20081e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.604047e-10 targ= 1.498579e-08 trig= 1.472538e-08
+fvco_outside_while = 3.84018e+09
+supply_current_rms_outside_while= 6.44351e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.33605e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923081e+00 at= 1.768500e-08
+vlow_outside_while = -7.995231e-02 at= 1.157500e-08
+peak_to_peak_outside_while= 2.00303e+00
+supply_current_rms = 6.43509e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.589721e-10 targ= 1.491261e-08 trig= 1.465364e-08
+fvco_outside_while = 3.86142e+09
+supply_current_rms_outside_while= 5.71231e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.40812e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922975e+00 at= 1.552500e-08
+vlow_outside_while = -7.965946e-02 at= 1.566500e-08
+peak_to_peak_outside_while= 2.00263e+00
+supply_current_rms = 5.59497e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.580028e-10 targ= 1.486042e-08 trig= 1.460241e-08
+fvco_outside_while = 3.87593e+09
+supply_current_rms_outside_while= 5.49885e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.45752e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922986e+00 at= 1.082500e-08
+vlow_outside_while = -7.943543e-02 at= 1.767500e-08
+peak_to_peak_outside_while= 2.00242e+00
+supply_current_rms = 5.42205e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.571648e-10 targ= 1.482167e-08 trig= 1.456450e-08
+fvco_outside_while = 3.88856e+09
+supply_current_rms_outside_while= 5.55624e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.50017e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922954e+00 at= 1.002500e-08
+vlow_outside_while = -7.928569e-02 at= 1.994500e-08
+peak_to_peak_outside_while= 2.00224e+00
+supply_current_rms = 5.47689e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.565745e-10 targ= 1.479164e-08 trig= 1.453507e-08
+fvco_outside_while = 3.89750e+09
+supply_current_rms_outside_while= 5.55996e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.53207e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922928e+00 at= 1.000500e-08
+vlow_outside_while = -7.916963e-02 at= 1.656500e-08
+peak_to_peak_outside_while= 2.00210e+00
+supply_current_rms = 5.47567e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net5 1.8
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.564249e-10 targ= 1.476802e-08 trig= 1.451159e-08
+fvco_outside_while = 3.89978e+09
+supply_current_rms_outside_while= 5.57853e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.54611e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922908e+00 at= 1.101500e-08
+vlow_outside_while = -7.908245e-02 at= 1.679500e-08
+peak_to_peak_outside_while= 2.00199e+00
+supply_current_rms = 5.49700e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.564249e-10 targ= 1.476802e-08 trig= 1.451159e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.899776719884184e+09 " u=" 3.899776719884184e+09 " id=0
+fvco_outside_while = 3.89978e+09
+supply_current_rms_outside_while= 5.57853e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.54611e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922908e+00 at= 1.101500e-08
+vlow_outside_while = -7.908245e-02 at= 1.679500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.001990376958142e+00 " u=" 2.001990376958142e+00 " id=0
+peak_to_peak_outside_while= 2.00199e+00
+supply_current_rms = 5.49700e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 10.518
+
+Total CPU time (seconds) = 202.063
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 117.152 MB.
+Maximum ngspice program size = 684.820 MB.
+Current ngspice program size = 666.195 MB.
+
+Shared ngspice pages = 9.090 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.336 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p5_XM22_0p42_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p5_XM22_0p42_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..d5c673e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x0p5_XM22_0p42_POST-LAYOUT_tb.log
@@ -0,0 +1,1556 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.44520e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.78335e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 5.760322e-06 at= 1.001500e-08
+vlow_outside_while = -5.745752e-06 at= 1.002500e-08
+peak_to_peak_outside_while= 1.15061e-05
+supply_current_rms = 6.75140e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.18212e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.45400e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 5.304070e-06 at= 1.001500e-08
+vlow_outside_while = -5.312619e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 1.06167e-05
+supply_current_rms = 7.86452e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.53894e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.62993e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.147335e-06 at= 1.000500e-08
+vlow_outside_while = -2.546222e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 5.69356e-06
+supply_current_rms = 5.53727e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.29585e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.40052e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.202137e-05 at= 1.000500e-08
+vlow_outside_while = -1.196396e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 2.39853e-05
+supply_current_rms = 8.03314e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.82455e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 7.20352e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.055187e-05 at= 1.000500e-08
+vlow_outside_while = -1.052455e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 2.10764e-05
+supply_current_rms = 6.04304e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.12736e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.70702e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.665290e-02 at= 1.905500e-08
+vlow_outside_while = -2.055050e-02 at= 1.900500e-08
+peak_to_peak_outside_while= 3.72034e-02
+supply_current_rms = 6.06047e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 1.355512e-09 targ= 6.468910e-08 trig= 6.333358e-08
+fvco_outside_while = 7.37729e+08
+supply_current_rms_outside_while= 1.43154e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.64976e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929133e+00 at= 1.265500e-08
+vlow_outside_while = -8.670451e-02 at= 1.964500e-08
+peak_to_peak_outside_while= 2.01584e+00
+supply_current_rms = 1.57495e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.881565e-10 targ= 3.053695e-08 trig= 2.994880e-08
+fvco_outside_while = 1.70023e+09
+supply_current_rms_outside_while= 2.19513e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.17823e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929861e+00 at= 1.795500e-08
+vlow_outside_while = -8.777685e-02 at= 1.816500e-08
+peak_to_peak_outside_while= 2.01764e+00
+supply_current_rms = 2.21937e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.260785e-10 targ= 1.840352e-08 trig= 1.807744e-08
+fvco_outside_while = 3.06675e+09
+supply_current_rms_outside_while= 3.56209e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.57712e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.930199e+00 at= 1.789500e-08
+vlow_outside_while = -8.578716e-02 at= 1.446500e-08
+peak_to_peak_outside_while= 2.01599e+00
+supply_current_rms = 3.50776e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.893118e-10 targ= 1.647110e-08 trig= 1.618179e-08
+fvco_outside_while = 3.45648e+09
+supply_current_rms_outside_while= 4.25893e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.19923e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928056e+00 at= 1.484500e-08
+vlow_outside_while = -8.567244e-02 at= 1.268500e-08
+peak_to_peak_outside_while= 2.01373e+00
+supply_current_rms = 4.19349e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.744849e-10 targ= 1.572040e-08 trig= 1.544592e-08
+fvco_outside_while = 3.64319e+09
+supply_current_rms_outside_while= 4.64216e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.61953e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926341e+00 at= 1.939500e-08
+vlow_outside_while = -8.481796e-02 at= 1.679500e-08
+peak_to_peak_outside_while= 2.01116e+00
+supply_current_rms = 4.57540e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.668066e-10 targ= 1.533218e-08 trig= 1.506537e-08
+fvco_outside_while = 3.74803e+09
+supply_current_rms_outside_while= 4.99621e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.95793e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924872e+00 at= 1.756500e-08
+vlow_outside_while = -8.446532e-02 at= 1.931500e-08
+peak_to_peak_outside_while= 2.00934e+00
+supply_current_rms = 4.92457e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.629654e-10 targ= 1.512811e-08 trig= 1.486514e-08
+fvco_outside_while = 3.80278e+09
+supply_current_rms_outside_while= 5.25609e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.20757e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923949e+00 at= 1.811500e-08
+vlow_outside_while = -8.425554e-02 at= 1.694500e-08
+peak_to_peak_outside_while= 2.00820e+00
+supply_current_rms = 5.18060e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.611173e-10 targ= 1.501543e-08 trig= 1.475431e-08
+fvco_outside_while = 3.82970e+09
+supply_current_rms_outside_while= 5.50795e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.36673e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923526e+00 at= 1.745500e-08
+vlow_outside_while = -8.400000e-02 at= 1.629500e-08
+peak_to_peak_outside_while= 2.00753e+00
+supply_current_rms = 5.42987e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.595432e-10 targ= 1.494198e-08 trig= 1.468244e-08
+fvco_outside_while = 3.85292e+09
+supply_current_rms_outside_while= 6.09228e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.66704e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923494e+00 at= 1.347500e-08
+vlow_outside_while = -8.382245e-02 at= 1.621500e-08
+peak_to_peak_outside_while= 2.00732e+00
+supply_current_rms = 5.91837e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.586580e-10 targ= 1.488975e-08 trig= 1.463110e-08
+fvco_outside_while = 3.86611e+09
+supply_current_rms_outside_while= 5.63674e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.49396e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923446e+00 at= 1.601500e-08
+vlow_outside_while = -8.347040e-02 at= 1.098500e-08
+peak_to_peak_outside_while= 2.00692e+00
+supply_current_rms = 5.55070e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.577190e-10 targ= 1.485091e-08 trig= 1.459320e-08
+fvco_outside_while = 3.88020e+09
+supply_current_rms_outside_while= 5.56363e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.50795e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923358e+00 at= 1.571500e-08
+vlow_outside_while = -8.329946e-02 at= 1.869500e-08
+peak_to_peak_outside_while= 2.00666e+00
+supply_current_rms = 5.48355e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.571009e-10 targ= 1.482085e-08 trig= 1.456374e-08
+fvco_outside_while = 3.88952e+09
+supply_current_rms_outside_while= 5.61064e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.54720e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923292e+00 at= 1.748500e-08
+vlow_outside_while = -8.317787e-02 at= 1.685500e-08
+peak_to_peak_outside_while= 2.00647e+00
+supply_current_rms = 5.53095e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66618
+vctrl 0
+x1.net8 0.938142
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 9.63187e-09
+x1.vco_switch_n_v2_2/selb 1.8
+sel2 0
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.938142
+x1.net2 1.79219
+x1.net4 0.130516
+x1.pg3 1.8
+x1.pg0 1.66618
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66618
+x1.pg2 1.8
+x1.vco_switch_p_2/selb 1.8
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.60237e-11
+vmeas_current_gnd#branch 1.37538e-05
+vmeas_current_vdd#branch 1.37538e-05
+v2#branch -1.37539e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.572479e-10 targ= 1.479746e-08 trig= 1.454021e-08
+fvco_outside_while = 3.88730e+09
+supply_current_rms_outside_while= 5.60015e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.57010e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923247e+00 at= 1.848500e-08
+vlow_outside_while = -8.309296e-02 at= 1.965500e-08
+peak_to_peak_outside_while= 2.00634e+00
+supply_current_rms = 5.51593e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.572479e-10 targ= 1.479746e-08 trig= 1.454021e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.887300726576908e+09 " u=" 3.887300726576908e+09 " id=0
+fvco_outside_while = 3.88730e+09
+supply_current_rms_outside_while= 5.60015e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.57010e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923247e+00 at= 1.848500e-08
+vlow_outside_while = -8.309296e-02 at= 1.965500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.006339773436696e+00 " u=" 2.006339773436696e+00 " id=0
+peak_to_peak_outside_while= 2.00634e+00
+supply_current_rms = 5.51593e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 14.9337
+
+Total CPU time (seconds) = 293.880
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 3433.090 MB.
+Maximum ngspice program size = 684.809 MB.
+Current ngspice program size = 665.770 MB.
+
+Shared ngspice pages = 8.680 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.324 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x1_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x1_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..b22ef7f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x1_POST-LAYOUT_tb.log
@@ -0,0 +1,1556 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.04634e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.44770e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 6.017106e-06 at= 1.194500e-08
+vlow_outside_while = -5.410462e-06 at= 1.099500e-08
+peak_to_peak_outside_while= 1.14276e-05
+supply_current_rms = 6.25872e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.57226e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.51039e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.009703e-06 at= 1.000500e-08
+vlow_outside_while = -2.219146e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 5.22885e-06
+supply_current_rms = 5.36892e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.60060e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.19535e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.954152e-06 at= 1.153500e-08
+vlow_outside_while = -1.677610e-06 at= 1.080500e-08
+peak_to_peak_outside_while= 3.63176e-06
+supply_current_rms = 5.29154e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.35176e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.20154e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.472920e-05 at= 1.001500e-08
+vlow_outside_while = -1.472254e-05 at= 1.000500e-08
+peak_to_peak_outside_while= 2.94517e-05
+supply_current_rms = 5.96312e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.43326e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.00414e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.265351e-06 at= 1.000500e-08
+vlow_outside_while = -2.238907e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 4.50426e-06
+supply_current_rms = 5.35174e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.93489e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.54095e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.834946e+00 at= 1.132500e-08
+vlow_outside_while = -7.450899e-02 at= 1.123500e-08
+peak_to_peak_outside_while= 1.90945e+00
+supply_current_rms = 6.56019e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 1.598954e-09 targ= 6.333837e-08 trig= 6.173942e-08
+fvco_outside_while = 6.25409e+08
+supply_current_rms_outside_while= 1.48989e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.56236e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927695e+00 at= 1.105500e-08
+vlow_outside_while = -8.347376e-02 at= 1.329500e-08
+peak_to_peak_outside_while= 2.01117e+00
+supply_current_rms = 1.60211e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.081865e-10 targ= 2.724422e-08 trig= 2.673603e-08
+fvco_outside_while = 1.96778e+09
+supply_current_rms_outside_while= 2.56493e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.53037e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928334e+00 at= 1.744500e-08
+vlow_outside_while = -7.095087e-02 at= 1.959500e-08
+peak_to_peak_outside_while= 1.99928e+00
+supply_current_rms = 2.52753e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.929823e-10 targ= 1.727859e-08 trig= 1.698560e-08
+fvco_outside_while = 3.41318e+09
+supply_current_rms_outside_while= 4.06648e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.99109e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927557e+00 at= 1.065500e-08
+vlow_outside_while = -8.108597e-02 at= 1.021500e-08
+peak_to_peak_outside_while= 2.00864e+00
+supply_current_rms = 3.95524e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.680603e-10 targ= 1.553938e-08 trig= 1.527132e-08
+fvco_outside_while = 3.73050e+09
+supply_current_rms_outside_while= 4.46878e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.44392e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924316e+00 at= 1.885500e-08
+vlow_outside_while = -8.076857e-02 at= 1.685500e-08
+peak_to_peak_outside_while= 2.00508e+00
+supply_current_rms = 4.39640e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.577627e-10 targ= 1.497831e-08 trig= 1.472055e-08
+fvco_outside_while = 3.87954e+09
+supply_current_rms_outside_while= 4.85098e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.78572e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.921209e+00 at= 1.867500e-08
+vlow_outside_while = -8.080743e-02 at= 1.701500e-08
+peak_to_peak_outside_while= 2.00202e+00
+supply_current_rms = 4.76899e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.531519e-10 targ= 1.472205e-08 trig= 1.446890e-08
+fvco_outside_while = 3.95020e+09
+supply_current_rms_outside_while= 5.08961e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.08642e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.918571e+00 at= 1.885500e-08
+vlow_outside_while = -8.096490e-02 at= 1.368500e-08
+peak_to_peak_outside_while= 1.99954e+00
+supply_current_rms = 5.01370e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.506674e-10 targ= 1.458559e-08 trig= 1.433492e-08
+fvco_outside_while = 3.98935e+09
+supply_current_rms_outside_while= 5.31669e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.30349e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.916730e+00 at= 1.065500e-08
+vlow_outside_while = -8.097731e-02 at= 1.982500e-08
+peak_to_peak_outside_while= 1.99771e+00
+supply_current_rms = 5.23562e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.496224e-10 targ= 1.451017e-08 trig= 1.426055e-08
+fvco_outside_while = 4.00605e+09
+supply_current_rms_outside_while= 5.42816e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.41885e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.915927e+00 at= 1.159500e-08
+vlow_outside_while = -8.090664e-02 at= 1.473500e-08
+peak_to_peak_outside_while= 1.99683e+00
+supply_current_rms = 5.34298e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.488677e-10 targ= 1.446017e-08 trig= 1.421131e-08
+fvco_outside_while = 4.01820e+09
+supply_current_rms_outside_while= 5.49922e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.49055e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.915534e+00 at= 1.553500e-08
+vlow_outside_while = -8.085732e-02 at= 1.866500e-08
+peak_to_peak_outside_while= 1.99639e+00
+supply_current_rms = 5.42046e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.483981e-10 targ= 1.442529e-08 trig= 1.417689e-08
+fvco_outside_while = 4.02580e+09
+supply_current_rms_outside_while= 5.54750e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.53994e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.915297e+00 at= 1.003500e-08
+vlow_outside_while = -8.081654e-02 at= 1.514500e-08
+peak_to_peak_outside_while= 1.99611e+00
+supply_current_rms = 5.46577e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.479967e-10 targ= 1.439880e-08 trig= 1.415080e-08
+fvco_outside_while = 4.03231e+09
+supply_current_rms_outside_while= 5.58209e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.57453e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.915156e+00 at= 1.720500e-08
+vlow_outside_while = -8.077581e-02 at= 1.660500e-08
+peak_to_peak_outside_while= 1.99593e+00
+supply_current_rms = 5.50009e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.477164e-10 targ= 1.437868e-08 trig= 1.413096e-08
+fvco_outside_while = 4.03687e+09
+supply_current_rms_outside_while= 5.60611e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.60169e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.915026e+00 at= 1.049500e-08
+vlow_outside_while = -8.074174e-02 at= 1.633500e-08
+peak_to_peak_outside_while= 1.99577e+00
+supply_current_rms = 5.52413e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net5 1.8
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.471562e-10 targ= 1.436251e-08 trig= 1.411536e-08
+fvco_outside_while = 4.04602e+09
+supply_current_rms_outside_while= 5.63255e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.62655e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.914946e+00 at= 1.889500e-08
+vlow_outside_while = -8.073068e-02 at= 1.458500e-08
+peak_to_peak_outside_while= 1.99568e+00
+supply_current_rms = 5.54831e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.471562e-10 targ= 1.436251e-08 trig= 1.411536e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.046023549291243e+09 " u=" 4.046023549291243e+09 " id=0
+fvco_outside_while = 4.04602e+09
+supply_current_rms_outside_while= 5.63255e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.62655e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.914946e+00 at= 1.889500e-08
+vlow_outside_while = -8.073068e-02 at= 1.458500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 1.995676315181723e+00 " u=" 1.995676315181723e+00 " id=0
+peak_to_peak_outside_while= 1.99568e+00
+supply_current_rms = 5.54831e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 15.161
+
+Total CPU time (seconds) = 281.199
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 4233.176 MB.
+Maximum ngspice program size = 684.824 MB.
+Current ngspice program size = 667.395 MB.
+
+Shared ngspice pages = 10.223 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.340 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x2_XM22_0p42_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x2_XM22_0p42_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..8e257a8
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_with_control_ports_x2_XM22_0p42_POST-LAYOUT_tb.log
@@ -0,0 +1,1563 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.38361e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.86650e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926907e+00 at= 1.034500e-08
+vlow_outside_while = -8.116158e-02 at= 1.016500e-08
+peak_to_peak_outside_while= 2.00807e+00
+supply_current_rms = 5.59574e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.62342e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.49880e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.122765e-05 at= 1.048500e-08
+vlow_outside_while = -1.121234e-05 at= 1.049500e-08
+peak_to_peak_outside_while= 2.24400e-05
+supply_current_rms = 6.58514e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.28524e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.89048e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.200122e-06 at= 1.001500e-08
+vlow_outside_while = -8.197467e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 1.63976e-05
+supply_current_rms = 5.47382e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 5.24008e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.29688e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.438409e-06 at= 1.001500e-08
+vlow_outside_while = -2.432477e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 4.87089e-06
+supply_current_rms = 7.00545e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.72235e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.86317e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.051442e-06 at= 1.001500e-08
+vlow_outside_while = -8.074358e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 1.61258e-05
+supply_current_rms = 6.66147e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 7.62886e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 7.64586e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929096e+00 at= 1.098500e-08
+vlow_outside_while = -8.057387e-02 at= 1.082500e-08
+peak_to_peak_outside_while= 2.00967e+00
+supply_current_rms = 9.64272e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.13201e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.52693e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929116e+00 at= 1.307500e-08
+vlow_outside_while = -7.809854e-02 at= 1.320500e-08
+peak_to_peak_outside_while= 2.00721e+00
+supply_current_rms = 2.04837e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.874020e-10 targ= 2.316262e-08 trig= 2.277522e-08
+fvco_outside_while = 2.58130e+09
+supply_current_rms_outside_while= 2.97628e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.04343e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.930634e+00 at= 1.057500e-08
+vlow_outside_while = -7.665092e-02 at= 1.382500e-08
+peak_to_peak_outside_while= 2.00728e+00
+supply_current_rms = 2.90110e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.716194e-10 targ= 1.646168e-08 trig= 1.619006e-08
+fvco_outside_while = 3.68162e+09
+supply_current_rms_outside_while= 4.31981e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.31471e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926496e+00 at= 1.520500e-08
+vlow_outside_while = -8.394625e-02 at= 1.616500e-08
+peak_to_peak_outside_while= 2.01044e+00
+supply_current_rms = 4.22985e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.537990e-10 targ= 1.497657e-08 trig= 1.472277e-08
+fvco_outside_while = 3.94013e+09
+supply_current_rms_outside_while= 4.64009e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.59466e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.916009e+00 at= 1.505500e-08
+vlow_outside_while = -8.520592e-02 at= 1.748500e-08
+peak_to_peak_outside_while= 2.00122e+00
+supply_current_rms = 4.56287e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.481102e-10 targ= 1.460580e-08 trig= 1.435769e-08
+fvco_outside_while = 4.03047e+09
+supply_current_rms_outside_while= 4.83009e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.83304e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.902348e+00 at= 1.963500e-08
+vlow_outside_while = -8.560364e-02 at= 1.755500e-08
+peak_to_peak_outside_while= 1.98795e+00
+supply_current_rms = 4.75216e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.452788e-10 targ= 1.442304e-08 trig= 1.417776e-08
+fvco_outside_while = 4.07699e+09
+supply_current_rms_outside_while= 5.06048e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.07875e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.886091e+00 at= 1.473500e-08
+vlow_outside_while = -8.573665e-02 at= 1.071500e-08
+peak_to_peak_outside_while= 1.97183e+00
+supply_current_rms = 4.98121e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.439906e-10 targ= 1.432154e-08 trig= 1.407755e-08
+fvco_outside_while = 4.09852e+09
+supply_current_rms_outside_while= 5.25318e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.28107e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.873735e+00 at= 1.609500e-08
+vlow_outside_while = -8.575339e-02 at= 1.722500e-08
+peak_to_peak_outside_while= 1.95949e+00
+supply_current_rms = 5.17242e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.434753e-10 targ= 1.426312e-08 trig= 1.401965e-08
+fvco_outside_while = 4.10719e+09
+supply_current_rms_outside_while= 5.35285e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.37410e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.868167e+00 at= 1.286500e-08
+vlow_outside_while = -8.571639e-02 at= 1.277500e-08
+peak_to_peak_outside_while= 1.95388e+00
+supply_current_rms = 5.27396e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.433372e-10 targ= 1.422480e-08 trig= 1.398147e-08
+fvco_outside_while = 4.10952e+09
+supply_current_rms_outside_while= 5.42015e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.43894e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.865134e+00 at= 1.258500e-08
+vlow_outside_while = -8.570167e-02 at= 1.322500e-08
+peak_to_peak_outside_while= 1.95084e+00
+supply_current_rms = 5.33892e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.429655e-10 targ= 1.419742e-08 trig= 1.395446e-08
+fvco_outside_while = 4.11581e+09
+supply_current_rms_outside_while= 5.47344e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.48572e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.863160e+00 at= 1.304500e-08
+vlow_outside_while = -8.567741e-02 at= 1.708500e-08
+peak_to_peak_outside_while= 1.94884e+00
+supply_current_rms = 5.38944e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.428288e-10 targ= 1.417689e-08 trig= 1.393406e-08
+fvco_outside_while = 4.11813e+09
+supply_current_rms_outside_while= 5.50409e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.51593e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.861770e+00 at= 1.836500e-08
+vlow_outside_while = -8.566965e-02 at= 1.730500e-08
+peak_to_peak_outside_while= 1.94744e+00
+supply_current_rms = 5.42178e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.424671e-10 targ= 1.416083e-08 trig= 1.391836e-08
+fvco_outside_while = 4.12427e+09
+supply_current_rms_outside_while= 5.53132e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.54438e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.860742e+00 at= 1.349500e-08
+vlow_outside_while = -8.565540e-02 at= 1.898500e-08
+peak_to_peak_outside_while= 1.94640e+00
+supply_current_rms = 5.44876e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.424380e-10 targ= 1.414821e-08 trig= 1.390577e-08
+fvco_outside_while = 4.12477e+09
+supply_current_rms_outside_while= 5.54965e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.56177e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.859954e+00 at= 1.469500e-08
+vlow_outside_while = -8.564857e-02 at= 1.945500e-08
+peak_to_peak_outside_while= 1.94560e+00
+supply_current_rms = 5.46738e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.424380e-10 targ= 1.414821e-08 trig= 1.390577e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.124765509710453e+09 " u=" 4.124765509710453e+09 " id=0
+fvco_outside_while = 4.12477e+09
+supply_current_rms_outside_while= 5.54965e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.56177e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.859954e+00 at= 1.469500e-08
+vlow_outside_while = -8.564857e-02 at= 1.945500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 1.945602402679072e+00 " u=" 1.945602402679072e+00 " id=0
+peak_to_peak_outside_while= 1.94560e+00
+supply_current_rms = 5.46738e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 15.5163
+
+Total CPU time (seconds) = 298.935
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 3992.711 MB.
+Maximum ngspice program size = 684.805 MB.
+Current ngspice program size = 665.617 MB.
+
+Shared ngspice pages = 8.531 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.320 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_x1_XM22_0p42_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_x1_XM22_0p42_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..8cd3ce8
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_x1_XM22_0p42_POST-LAYOUT_tb.log
@@ -0,0 +1,1556 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.05096e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.97556e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 9.257659e-06 at= 1.011500e-08
+vlow_outside_while = -9.242708e-06 at= 1.010500e-08
+peak_to_peak_outside_while= 1.85004e-05
+supply_current_rms = 1.11437e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.34844e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.93190e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 4.310862e-06 at= 1.148500e-08
+vlow_outside_while = -4.296573e-06 at= 1.149500e-08
+peak_to_peak_outside_while= 8.60743e-06
+supply_current_rms = 7.80736e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.74836e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.41737e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.780522e-06 at= 1.001500e-08
+vlow_outside_while = -1.775279e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 3.55580e-06
+supply_current_rms = 5.40982e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.02051e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 7.78363e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.121029e-05 at= 1.000500e-08
+vlow_outside_while = -1.118614e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 2.23964e-05
+supply_current_rms = 5.52344e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.43381e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.08902e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 6.177804e-07 at= 1.466500e-08
+vlow_outside_while = -6.040500e-07 at= 1.467500e-08
+peak_to_peak_outside_while= 1.22183e-06
+supply_current_rms = 5.38192e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.39587e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.41191e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.733434e+00 at= 1.133500e-08
+vlow_outside_while = -7.912534e-02 at= 1.125500e-08
+peak_to_peak_outside_while= 1.81256e+00
+supply_current_rms = 6.94973e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 1.599098e-09 targ= 6.338998e-08 trig= 6.179088e-08
+fvco_outside_while = 6.25352e+08
+supply_current_rms_outside_while= 2.20695e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.44746e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929077e+00 at= 1.297500e-08
+vlow_outside_while = -8.747969e-02 at= 1.331500e-08
+peak_to_peak_outside_while= 2.01656e+00
+supply_current_rms = 2.73831e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.087590e-10 targ= 2.726572e-08 trig= 2.675696e-08
+fvco_outside_while = 1.96557e+09
+supply_current_rms_outside_while= 2.49251e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.64062e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.930159e+00 at= 1.440500e-08
+vlow_outside_while = -7.382856e-02 at= 1.401500e-08
+peak_to_peak_outside_while= 2.00399e+00
+supply_current_rms = 2.46458e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.940897e-10 targ= 1.701698e-08 trig= 1.672289e-08
+fvco_outside_while = 3.40032e+09
+supply_current_rms_outside_while= 4.12312e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.01262e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929062e+00 at= 1.860500e-08
+vlow_outside_while = -8.479566e-02 at= 1.875500e-08
+peak_to_peak_outside_while= 2.01386e+00
+supply_current_rms = 4.03797e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.687029e-10 targ= 1.556958e-08 trig= 1.530088e-08
+fvco_outside_while = 3.72158e+09
+supply_current_rms_outside_while= 4.49411e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.45485e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924993e+00 at= 1.378500e-08
+vlow_outside_while = -8.466285e-02 at= 1.930500e-08
+peak_to_peak_outside_while= 2.00966e+00
+supply_current_rms = 4.42583e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.584359e-10 targ= 1.500809e-08 trig= 1.474966e-08
+fvco_outside_while = 3.86943e+09
+supply_current_rms_outside_while= 4.83872e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.81254e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.920795e+00 at= 1.044500e-08
+vlow_outside_while = -8.491764e-02 at= 1.756500e-08
+peak_to_peak_outside_while= 2.00571e+00
+supply_current_rms = 4.76562e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.532518e-10 targ= 1.475130e-08 trig= 1.449805e-08
+fvco_outside_while = 3.94864e+09
+supply_current_rms_outside_while= 5.11135e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.09966e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.916657e+00 at= 1.229500e-08
+vlow_outside_while = -8.511673e-02 at= 1.041500e-08
+peak_to_peak_outside_while= 2.00177e+00
+supply_current_rms = 5.03194e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.515579e-10 targ= 1.461447e-08 trig= 1.436291e-08
+fvco_outside_while = 3.97523e+09
+supply_current_rms_outside_while= 5.30497e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.29268e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.913597e+00 at= 1.946500e-08
+vlow_outside_while = -8.518360e-02 at= 1.383500e-08
+peak_to_peak_outside_while= 1.99878e+00
+supply_current_rms = 5.22354e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.500098e-10 targ= 1.453852e-08 trig= 1.428851e-08
+fvco_outside_while = 3.99984e+09
+supply_current_rms_outside_while= 5.41747e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.40603e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.911785e+00 at= 1.986500e-08
+vlow_outside_while = -8.340232e-02 at= 1.976500e-08
+peak_to_peak_outside_while= 1.99519e+00
+supply_current_rms = 5.33607e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.492970e-10 targ= 1.448940e-08 trig= 1.424010e-08
+fvco_outside_while = 4.01128e+09
+supply_current_rms_outside_while= 5.48679e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.47449e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.911639e+00 at= 1.805500e-08
+vlow_outside_while = -8.504470e-02 at= 1.022500e-08
+peak_to_peak_outside_while= 1.99668e+00
+supply_current_rms = 5.40630e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.488344e-10 targ= 1.445444e-08 trig= 1.420561e-08
+fvco_outside_while = 4.01874e+09
+supply_current_rms_outside_while= 5.53190e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.52535e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.911213e+00 at= 1.527500e-08
+vlow_outside_while = -8.499148e-02 at= 1.517500e-08
+peak_to_peak_outside_while= 1.99620e+00
+supply_current_rms = 5.45435e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.485325e-10 targ= 1.442796e-08 trig= 1.417942e-08
+fvco_outside_while = 4.02362e+09
+supply_current_rms_outside_while= 5.56492e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.56239e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910903e+00 at= 1.723500e-08
+vlow_outside_while = -8.492703e-02 at= 1.713500e-08
+peak_to_peak_outside_while= 1.99583e+00
+supply_current_rms = 5.48659e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.482718e-10 targ= 1.440790e-08 trig= 1.415963e-08
+fvco_outside_while = 4.02784e+09
+supply_current_rms_outside_while= 5.59789e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.59351e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910636e+00 at= 1.944500e-08
+vlow_outside_while = -8.491362e-02 at= 1.264500e-08
+peak_to_peak_outside_while= 1.99555e+00
+supply_current_rms = 5.51502e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.12909e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.66135
+vctrl 0
+x1.net8 0.952127
+x1.ng3 9.63187e-09
+x1.net5 1.8
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 1.8
+sel3 0
+x1.net3 0.952128
+x1.net2 1.7937
+x1.net4 0.102646
+x1.pg3 1.8
+x1.pg0 1.66135
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.66135
+x1.pg2 1.66135
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 1.8
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.52147e-11
+vmeas_current_gnd#branch 1.30191e-05
+vmeas_current_vdd#branch 1.30191e-05
+v2#branch -1.30192e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.478008e-10 targ= 1.439156e-08 trig= 1.414376e-08
+fvco_outside_while = 4.03550e+09
+supply_current_rms_outside_while= 5.62194e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.61251e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910490e+00 at= 1.694500e-08
+vlow_outside_while = -8.489914e-02 at= 1.932500e-08
+peak_to_peak_outside_while= 1.99539e+00
+supply_current_rms = 5.53942e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.478008e-10 targ= 1.439156e-08 trig= 1.414376e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.035499510064193e+09 " u=" 4.035499510064193e+09 " id=0
+fvco_outside_while = 4.03550e+09
+supply_current_rms_outside_while= 5.62194e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.61251e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910490e+00 at= 1.694500e-08
+vlow_outside_while = -8.489914e-02 at= 1.932500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 1.995388736917344e+00 " u=" 1.995388736917344e+00 " id=0
+peak_to_peak_outside_while= 1.99539e+00
+supply_current_rms = 5.53942e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 15.0595
+
+Total CPU time (seconds) = 303.944
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 4552.332 MB.
+Maximum ngspice program size = 684.801 MB.
+Current ngspice program size = 665.574 MB.
+
+Shared ngspice pages = 8.488 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.316 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_x2_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_x2_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..679ec8e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9_x2_POST-LAYOUT_tb.log
@@ -0,0 +1,1563 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.41112e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.26658e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926124e+00 at= 1.087500e-08
+vlow_outside_while = -8.146002e-02 at= 1.072500e-08
+peak_to_peak_outside_while= 2.00758e+00
+supply_current_rms = 5.54515e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.91331e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.58677e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.405164e-06 at= 1.000500e-08
+vlow_outside_while = -3.364600e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 6.76976e-06
+supply_current_rms = 6.73300e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.50853e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.61998e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.365017e-05 at= 1.000500e-08
+vlow_outside_while = -1.361321e-05 at= 1.001500e-08
+peak_to_peak_outside_while= 2.72634e-05
+supply_current_rms = 5.18212e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.44954e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.10402e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.149947e-05 at= 1.050500e-08
+vlow_outside_while = -1.148452e-05 at= 1.051500e-08
+peak_to_peak_outside_while= 2.29840e-05
+supply_current_rms = 6.41630e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.85946e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.42277e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 9.979112e-06 at= 1.176500e-08
+vlow_outside_while = -9.254459e-06 at= 1.115500e-08
+peak_to_peak_outside_while= 1.92336e-05
+supply_current_rms = 1.03380e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.12357e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 7.38040e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927195e+00 at= 1.102500e-08
+vlow_outside_while = -8.209564e-02 at= 1.086500e-08
+peak_to_peak_outside_while= 2.00929e+00
+supply_current_rms = 1.01895e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12460:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12460:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.26686e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.54276e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927504e+00 at= 1.292500e-08
+vlow_outside_while = -7.986223e-02 at= 1.011500e-08
+peak_to_peak_outside_while= 2.00737e+00
+supply_current_rms = 2.78701e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.875399e-10 targ= 2.310807e-08 trig= 2.272053e-08
+fvco_outside_while = 2.58038e+09
+supply_current_rms_outside_while= 2.98478e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.03765e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928845e+00 at= 1.014500e-08
+vlow_outside_while = -7.366888e-02 at= 1.843500e-08
+peak_to_peak_outside_while= 2.00251e+00
+supply_current_rms = 2.90760e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.710748e-10 targ= 1.642394e-08 trig= 1.615286e-08
+fvco_outside_while = 3.68902e+09
+supply_current_rms_outside_while= 4.26644e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.27182e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925582e+00 at= 1.029500e-08
+vlow_outside_while = -8.005204e-02 at= 1.260500e-08
+peak_to_peak_outside_while= 2.00563e+00
+supply_current_rms = 4.17486e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.532283e-10 targ= 1.494354e-08 trig= 1.469031e-08
+fvco_outside_while = 3.94901e+09
+supply_current_rms_outside_while= 4.63559e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.59998e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.918177e+00 at= 1.224500e-08
+vlow_outside_while = -8.106337e-02 at= 1.112500e-08
+peak_to_peak_outside_while= 1.99924e+00
+supply_current_rms = 4.55163e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.474412e-10 targ= 1.457409e-08 trig= 1.432665e-08
+fvco_outside_while = 4.04136e+09
+supply_current_rms_outside_while= 4.85510e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.85989e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910882e+00 at= 1.118500e-08
+vlow_outside_while = -8.149412e-02 at= 1.875500e-08
+peak_to_peak_outside_while= 1.99238e+00
+supply_current_rms = 4.77979e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.448005e-10 targ= 1.439228e-08 trig= 1.414748e-08
+fvco_outside_while = 4.08496e+09
+supply_current_rms_outside_while= 5.10367e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.11429e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.903555e+00 at= 1.103500e-08
+vlow_outside_while = -8.169848e-02 at= 1.926500e-08
+peak_to_peak_outside_while= 1.98525e+00
+supply_current_rms = 5.02605e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.434474e-10 targ= 1.429111e-08 trig= 1.404766e-08
+fvco_outside_while = 4.10766e+09
+supply_current_rms_outside_while= 5.30029e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.32505e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.898660e+00 at= 1.265500e-08
+vlow_outside_while = -8.175048e-02 at= 1.158500e-08
+peak_to_peak_outside_while= 1.98041e+00
+supply_current_rms = 5.21818e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.431595e-10 targ= 1.423302e-08 trig= 1.398986e-08
+fvco_outside_while = 4.11253e+09
+supply_current_rms_outside_while= 5.40731e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.43543e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.896470e+00 at= 1.697500e-08
+vlow_outside_while = -8.173207e-02 at= 1.323500e-08
+peak_to_peak_outside_while= 1.97820e+00
+supply_current_rms = 5.32486e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.430599e-10 targ= 1.419495e-08 trig= 1.395189e-08
+fvco_outside_while = 4.11421e+09
+supply_current_rms_outside_while= 5.47350e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.50000e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.895278e+00 at= 1.353500e-08
+vlow_outside_while = -8.172142e-02 at= 1.659500e-08
+peak_to_peak_outside_while= 1.97700e+00
+supply_current_rms = 5.39058e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.422177e-10 targ= 1.416753e-08 trig= 1.392531e-08
+fvco_outside_while = 4.12852e+09
+supply_current_rms_outside_while= 5.52316e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.53607e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.894516e+00 at= 1.520500e-08
+vlow_outside_while = -8.170435e-02 at= 1.656500e-08
+peak_to_peak_outside_while= 1.97622e+00
+supply_current_rms = 5.43861e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.420747e-10 targ= 1.414711e-08 trig= 1.390504e-08
+fvco_outside_while = 4.13096e+09
+supply_current_rms_outside_while= 5.55415e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.56689e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.893995e+00 at= 1.760500e-08
+vlow_outside_while = -8.168997e-02 at= 1.678500e-08
+peak_to_peak_outside_while= 1.97568e+00
+supply_current_rms = 5.47271e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.419174e-10 targ= 1.413087e-08 trig= 1.388895e-08
+fvco_outside_while = 4.13364e+09
+supply_current_rms_outside_while= 5.57941e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.59083e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.893622e+00 at= 1.734500e-08
+vlow_outside_while = -8.168715e-02 at= 1.410500e-08
+peak_to_peak_outside_while= 1.97531e+00
+supply_current_rms = 5.49807e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.net7 1.8
+x1.net6 1.16209e-06
+net1 1.8
+net2 0
+out 6.80528e-09
+x1.vgp 1.6571
+vctrl 0
+x1.net8 0.966293
+x1.ng3 3.93259e-09
+x1.ng0 3.93259e-09
+x1.vco_switch_n_v2_0/selb 2.69671e-09
+sel0 1.8
+x1.ng1 3.93259e-09
+x1.vco_switch_n_v2_1/selb 2.69671e-09
+sel1 1.8
+x1.ng2 3.93259e-09
+x1.vco_switch_n_v2_2/selb 2.69671e-09
+sel2 1.8
+x1.vco_switch_n_v2_3/selb 2.69671e-09
+sel3 1.8
+x1.net3 0.966293
+x1.net5 1.8
+x1.net2 1.79523
+x1.net4 0.0839479
+x1.pg3 1.6571
+x1.pg0 1.6571
+x1.vco_switch_p_0/selb 2.69671e-09
+x1.pg1 1.6571
+x1.pg2 1.6571
+x1.vco_switch_p_2/selb 2.69671e-09
+x1.vco_switch_p_1/selb 2.69671e-09
+x1.vco_switch_p_3/selb 2.69671e-09
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 1.44058e-11
+vmeas_current_gnd#branch 1.2222e-05
+vmeas_current_vdd#branch 1.2222e-05
+v2#branch -1.22221e-05
+vsel3#branch 0
+vsel2#branch 0
+vsel1#branch 0
+vsel0#branch 0
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.417053e-10 targ= 1.411835e-08 trig= 1.387665e-08
+fvco_outside_while = 4.13727e+09
+supply_current_rms_outside_while= 5.60052e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.62218e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.893334e+00 at= 1.660500e-08
+vlow_outside_while = -8.167676e-02 at= 1.820500e-08
+peak_to_peak_outside_while= 1.97501e+00
+supply_current_rms = 5.51873e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.417053e-10 targ= 1.411835e-08 trig= 1.387665e-08
+Original line no.: 0, new internal line no.: 12460:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.137269400697080e+09 " u=" 4.137269400697080e+09 " id=0
+fvco_outside_while = 4.13727e+09
+supply_current_rms_outside_while= 5.60052e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.62218e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.893334e+00 at= 1.660500e-08
+vlow_outside_while = -8.167676e-02 at= 1.820500e-08
+Original line no.: 0, new internal line no.: 12466:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 1.975011101634743e+00 " u=" 1.975011101634743e+00 " id=0
+peak_to_peak_outside_while= 1.97501e+00
+supply_current_rms = 5.51873e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 11.2864
+
+Total CPU time (seconds) = 204.384
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 127.242 MB.
+Maximum ngspice program size = 684.824 MB.
+Current ngspice program size = 666.176 MB.
+
+Shared ngspice pages = 9.070 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.340 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/FD.ext b/mag/3-stage_cs-vco_dp9/FD.ext
new file mode 100755
index 0000000..3274ab0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD.ext
@@ -0,0 +1,74 @@
+timestamp 1605926473
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+port "Clk_Out" 3 1810 276 1838 304 li
+port "Clk_In" 5 0 262 0 296 li
+port "VDD" 6 0 544 0 640 m1
+port "GND" 4 0 0 0 96 m1
+node "Clk_Out" 749 139.963 1810 276 li 0 0 0 0 0 0 0 0 4176 260 8572 408 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19380 956 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1574_124#" 1489 234.165 1574 124 ndif 0 0 0 0 0 0 0 0 4464 268 8928 412 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15164 992 0 0 25400 1400 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1194_132#" 2371 1029.33 1194 132 ndif 0 0 0 0 0 0 0 0 9744 452 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29996 1976 0 0 30964 1720 28800 1172 0 0 0 0 0 0 0 0 0 0
+node "a_926_148#" 2427 121.717 926 148 ndif 0 0 0 0 0 0 0 0 13920 712 13224 688 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35032 1784 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_664_134#" 1460 222.647 664 134 ndif 0 0 0 0 0 0 0 0 9744 452 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15180 972 0 0 23360 1244 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_380_150#" 2430 146.407 380 150 ndif 0 0 0 0 0 0 0 0 13920 712 13224 688 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35964 1816 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_158_150#" 2138 440.865 158 150 ndif 0 0 0 0 0 0 0 0 4176 260 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28884 1812 0 0 17608 1200 13352 800 75412 2636 0 0 0 0 0 0 0 0
+node "a_286_254#" 1465 672.677 286 254 p 0 0 0 0 0 0 0 0 4176 260 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15180 972 0 0 15912 1020 69776 2604 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 2201 1082.42 0 262 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45108 2828 0 0 9176 740 116764 4416 0 0 0 0 0 0 0 0 0 0
+node "VDD" 22479 1889.86 0 544 m1 0 0 0 0 586328 4700 0 0 29412 2232 43776 2048 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 106432 5812 178944 3920 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 0 0 m1 0 0 0 0 0 0 0 0 21888 1328 28560 2360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90192 5304 179520 3932 0 0 0 0 0 0 0 0 0 0
+cap "a_926_148#" "VDD" 371.371
+cap "a_1574_124#" "a_1194_132#" 440.671
+cap "a_1574_124#" "Clk_In" 10.5585
+cap "a_1194_132#" "VDD" 420.404
+cap "a_926_148#" "a_1194_132#" 322.363
+cap "VDD" "Clk_In" 1925.4
+cap "a_926_148#" "Clk_In" 195.278
+cap "a_1574_124#" "a_286_254#" 118.415
+cap "VDD" "a_664_134#" 322.315
+cap "a_926_148#" "a_664_134#" 122.931
+cap "a_286_254#" "VDD" 668.058
+cap "VDD" "a_158_150#" 949.045
+cap "a_1194_132#" "Clk_In" 170.093
+cap "a_926_148#" "a_286_254#" 206.113
+cap "a_926_148#" "a_158_150#" 122.064
+cap "VDD" "a_380_150#" 387.44
+cap "a_926_148#" "a_380_150#" 39.4599
+cap "a_1194_132#" "a_664_134#" 16.1451
+cap "a_286_254#" "a_1194_132#" 640.962
+cap "a_1574_124#" "Clk_Out" 174.964
+cap "Clk_In" "a_664_134#" 138.527
+cap "a_1194_132#" "a_158_150#" 26.1573
+cap "a_286_254#" "Clk_In" 1167.18
+cap "Clk_In" "a_158_150#" 597.162
+cap "VDD" "Clk_Out" 202.689
+cap "Clk_In" "a_380_150#" 297.407
+cap "a_286_254#" "a_664_134#" 185.693
+cap "a_664_134#" "a_158_150#" 155.998
+cap "a_286_254#" "a_158_150#" 839.048
+cap "a_664_134#" "a_380_150#" 275.441
+cap "a_1194_132#" "Clk_Out" 12.6322
+cap "a_286_254#" "a_380_150#" 200.802
+cap "a_380_150#" "a_158_150#" 287.932
+cap "a_1574_124#" "VDD" 400.16
+cap "a_286_254#" "Clk_Out" 39.8729
+device msubckt sky130_fd_pr__nfet_01v8 1738 124 1739 125 l=30 w=72 "GND" "a_1574_124#" 60 0 "GND" 72 0 "Clk_Out" 72 0
+device msubckt sky130_fd_pr__nfet_01v8 1636 124 1637 125 l=30 w=72 "GND" "a_1194_132#" 60 0 "a_1574_124#" 72 0 "GND" 72 0
+device msubckt sky130_fd_pr__nfet_01v8 1428 150 1429 151 l=30 w=72 "GND" "a_1194_132#" 60 0 "GND" 72 0 "a_286_254#" 72 0
+device msubckt sky130_fd_pr__nfet_01v8 1164 132 1165 133 l=30 w=168 "GND" "a_158_150#" 60 0 "a_926_148#" 168 0 "a_1194_132#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 896 148 897 149 l=30 w=72 "GND" "a_664_134#" 60 0 "GND" 72 0 "a_926_148#" 72 0
+device msubckt sky130_fd_pr__nfet_01v8 634 134 635 135 l=30 w=168 "GND" "Clk_In" 60 0 "a_380_150#" 168 0 "a_664_134#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 350 150 351 151 l=30 w=72 "GND" "a_286_254#" 60 0 "GND" 72 0 "a_380_150#" 72 0
+device msubckt sky130_fd_pr__nfet_01v8 128 150 129 151 l=30 w=72 "GND" "Clk_In" 60 0 "GND" 72 0 "a_158_150#" 72 0
+device msubckt sky130_fd_pr__pfet_01v8 1738 366 1739 367 l=30 w=144 "VDD" "a_1574_124#" 60 0 "VDD" 144 0 "Clk_Out" 144 0
+device msubckt sky130_fd_pr__pfet_01v8 1636 366 1637 367 l=30 w=144 "VDD" "a_1194_132#" 60 0 "a_1574_124#" 144 0 "VDD" 144 0
+device msubckt sky130_fd_pr__pfet_01v8 1428 346 1429 347 l=30 w=144 "VDD" "a_1194_132#" 60 0 "VDD" 144 0 "a_286_254#" 144 0
+device msubckt sky130_fd_pr__pfet_01v8 1164 406 1165 407 l=30 w=84 "VDD" "Clk_In" 60 0 "a_926_148#" 84 0 "a_1194_132#" 84 0
+device msubckt sky130_fd_pr__pfet_01v8 896 344 897 345 l=30 w=144 "VDD" "a_664_134#" 60 0 "VDD" 144 0 "a_926_148#" 144 0
+device msubckt sky130_fd_pr__pfet_01v8 634 408 635 409 l=30 w=84 "VDD" "a_158_150#" 60 0 "a_380_150#" 84 0 "a_664_134#" 84 0
+device msubckt sky130_fd_pr__pfet_01v8 350 346 351 347 l=30 w=144 "VDD" "a_286_254#" 60 0 "VDD" 144 0 "a_380_150#" 144 0
+device msubckt sky130_fd_pr__pfet_01v8 128 346 129 347 l=30 w=144 "VDD" "Clk_In" 60 0 "VDD" 144 0 "a_158_150#" 144 0
diff --git a/mag/3-stage_cs-vco_dp9/FD.mag b/mag/3-stage_cs-vco_dp9/FD.mag
new file mode 100755
index 0000000..c3cf65f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD.mag
@@ -0,0 +1,716 @@
+magic
+tech sky130A
+timestamp 1605926473
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+rect 0 15 16 32
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+rect 332 15 407 32
+rect 424 15 513 32
+rect 530 15 597 32
+rect 614 15 715 32
+rect 732 15 799 32
+rect 816 15 883 32
+rect 900 15 935 32
+<< viali >>
+rect 55 283 74 302
+rect 137 283 156 302
+rect 282 283 301 302
+rect 360 283 379 302
+rect 454 283 473 302
+rect 562 283 581 302
+rect 682 283 701 302
+rect 768 283 787 302
+rect 854 283 873 302
+rect 244 230 261 247
+rect 244 229 261 230
+rect 41 131 58 148
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+rect 407 15 424 32
+rect 513 15 530 32
+rect 597 15 614 32
+rect 715 15 732 32
+rect 799 15 816 32
+rect 883 15 900 32
+<< metal1 >>
+rect 0 302 932 320
+rect 0 283 55 302
+rect 74 283 137 302
+rect 156 283 282 302
+rect 301 283 360 302
+rect 379 283 454 302
+rect 473 283 562 302
+rect 581 283 682 302
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+rect 508 93 541 96
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+rect 508 63 541 66
+rect 0 32 935 48
+rect 0 15 16 32
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+rect 197 15 315 32
+rect 332 15 407 32
+rect 424 15 513 32
+rect 530 15 597 32
+rect 614 15 715 32
+rect 732 15 799 32
+rect 816 15 883 32
+rect 900 15 935 32
+rect 0 0 935 15
+<< via1 >>
+rect 240 247 266 251
+rect 240 229 244 247
+rect 244 229 261 247
+rect 261 229 266 247
+rect 240 225 266 229
+rect 88 149 114 155
+rect 88 132 91 149
+rect 91 132 108 149
+rect 108 132 114 149
+rect 88 129 114 132
+rect 511 88 538 93
+rect 511 71 517 88
+rect 517 71 534 88
+rect 534 71 538 88
+rect 511 66 538 71
+<< metal2 >>
+rect 237 225 240 251
+rect 266 225 269 251
+rect 85 159 118 166
+rect 83 157 118 159
+rect 237 157 269 225
+rect 83 155 540 157
+rect 83 129 88 155
+rect 114 129 540 155
+rect 83 128 540 129
+rect 83 124 118 128
+rect 507 93 540 128
+rect 507 87 511 93
+rect 508 66 511 87
+rect 538 66 541 93
+rect 508 63 541 66
+<< labels >>
+rlabel locali 905 138 919 152 1 Clk_Out
+port 3 n
+rlabel locali 0 131 0 148 3 Clk_In
+port 5 e
+rlabel metal1 0 0 0 48 3 GND
+port 4 e
+rlabel metal1 0 272 0 320 3 VDD
+port 6 e
+<< properties >>
+string LEFsite unithddb1
+string LEFclass CORE
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/FD.spice b/mag/3-stage_cs-vco_dp9/FD.spice
new file mode 100755
index 0000000..9047b72
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD.spice
@@ -0,0 +1,21 @@
+* NGSPICE file created from FD.ext - technology: sky130A
+
+.subckt FD Clk_Out Clk_In VDD GND
+X0 Clk_Out a_1574_124# GND GND sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=5.472e+11p ps=6.64e+06u w=360000u l=150000u
+X1 a_664_134# Clk_In a_380_150# GND sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=3.48e+11p ps=3.56e+06u w=840000u l=150000u
+X2 a_158_150# Clk_In VDD VDD sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=1.0944e+12p ps=1.024e+07u w=720000u l=150000u
+X3 a_926_148# a_664_134# VDD VDD sky130_fd_pr__pfet_01v8 ad=3.306e+11p pd=3.44e+06u as=0p ps=0u w=720000u l=150000u
+X4 a_1194_132# a_158_150# a_926_148# GND sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=3.48e+11p ps=3.56e+06u w=840000u l=150000u
+X5 a_664_134# a_158_150# a_380_150# VDD sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=3.306e+11p ps=3.44e+06u w=420000u l=150000u
+X6 a_380_150# a_286_254# VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=720000u l=150000u
+X7 a_286_254# a_1194_132# VDD VDD sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=0p ps=0u w=720000u l=150000u
+X8 a_926_148# a_664_134# GND GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=360000u l=150000u
+X9 a_1194_132# Clk_In a_926_148# VDD sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=0p ps=0u w=420000u l=150000u
+X10 VDD a_1194_132# a_1574_124# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=2.232e+11p ps=2.06e+06u w=720000u l=150000u
+X11 Clk_Out a_1574_124# VDD VDD sky130_fd_pr__pfet_01v8 ad=2.143e+11p pd=2.04e+06u as=0p ps=0u w=720000u l=150000u
+X12 a_158_150# Clk_In GND GND sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=0p ps=0u w=360000u l=150000u
+X13 a_380_150# a_286_254# GND GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=360000u l=150000u
+X14 a_286_254# a_1194_132# GND GND sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=0p ps=0u w=360000u l=150000u
+X15 GND a_1194_132# a_1574_124# GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.116e+11p ps=1.34e+06u w=360000u l=150000u
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/FD_v2.ext b/mag/3-stage_cs-vco_dp9/FD_v2.ext
new file mode 100755
index 0000000..23c937e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD_v2.ext
@@ -0,0 +1,231 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_0 1 0 177 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_0 1 0 177 0 1 -227
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_1 1 0 377 0 1 -227
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_0 1 0 595 0 -1 -499
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_1 1 0 377 0 1 -422
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_0 1 0 595 0 1 -173
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_2 1 0 879 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_2 1 0 879 0 1 -227
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_1 1 0 1138 0 -1 -499
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_1 1 0 1138 0 1 -173
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_3 1 0 1383 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_3 1 0 1383 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_4 1 0 1614 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_4 1 0 1614 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_5 1 0 1774 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_5 1 0 1774 0 1 -227
+port "Clk_Out" 4 1849 -368 1883 -334 m1
+port "Clk_In" 1 68 -375 92 -329 m1
+port "VDD" 2 68 -49 102 9 m1
+port "GND" 3 96 -688 130 -630 m1
+node "li_1553_n470#" 12 35.4726 1553 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1556_n369#" 12 33.0592 1556 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 70 114.189 1849 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6596 456 4096 292 0 0 0 0 0 0 0 0 0 0
+node "6" 258 562.288 1165 -380 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21794 1418 13308 794 0 0 0 0 0 0 0 0 0 0
+node "5" 194 163.065 906 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18394 1150 0 0 0 0 0 0 0 0 0 0 0 0
+node "4" 125 127.428 622 -380 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11832 764 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 116 700.949 320 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7854 598 53130 2402 0 0 0 0 0 0 0 0 0 0
+node "3" 162 121.242 404 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15368 972 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb" 49 51.3951 204 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 0 0 0 0 0 0 0 0 0 0 0 0
+node "7" 175 415.97 1553 -547 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5848 616 23728 1396 0 0 0 0 0 0 0 0 0 0
+node "li_204_n127#" 72 0 204 -127 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 20148 968 0 0 0 0 0 0 0 0 0 0
+node "a_971_n597#" 128 915.599 971 -597 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6004 310 0 0 3400 336 42780 1952 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 209 1097.67 68 -375 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5092 286 0 0 8794 710 82524 3680 0 0 0 0 0 0 0 0 0 0
+node "a_1687_n501#" 720 0 1687 -501 ndif 0 0 0 0 0 0 0 0 1176 196 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1687_n263#" 2026 0 1687 -263 pdif 0 0 0 0 0 0 0 0 0 0 2016 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 15744 1945.75 68 -49 m1 0 0 0 0 629805 4324 0 0 57800 3468 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80342 4794 105270 3746 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 96 -688 m1 0 0 0 0 0 0 0 0 0 0 61710 3698 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92684 5520 105270 3746 0 0 0 0 0 0 0 0 0 0
+cap "li_204_n127#" "Clk_In" 197.189
+cap "li_204_n127#" "a_971_n597#" 64.8276
+cap "Clk_Out" "7" 97.5628
+cap "Clk_In" "a_971_n597#" 563.519
+cap "VDD" "6" 95.0651
+cap "li_1553_n470#" "7" 186.069
+cap "li_204_n127#" "Clkb" 8.01429
+cap "Clkb" "Clk_In" 68.1857
+cap "Clkb" "a_971_n597#" 22.898
+cap "li_1556_n369#" "6" 79.361
+cap "5" "6" 154.27
+cap "4" "6" 3.16056
+cap "VDD" "Clk_Out" 73.6181
+cap "li_1556_n369#" "Clk_Out" 5.31754
+cap "2" "6" 313.227
+cap "li_1553_n470#" "VDD" 2.81203
+cap "li_204_n127#" "VDD" 882.312
+cap "VDD" "Clk_In" 849.512
+cap "li_1553_n470#" "li_1556_n369#" 15.2687
+cap "VDD" "a_971_n597#" 94.534
+cap "3" "Clk_In" 143.21
+cap "2" "Clk_Out" 24.1201
+cap "5" "Clk_In" 72.7032
+cap "4" "Clk_In" 40.6174
+cap "VDD" "Clkb" 32.155
+cap "5" "a_971_n597#" 12.5172
+cap "3" "Clkb" 35.8436
+cap "VDD" "7" 241.737
+cap "li_204_n127#" "2" 73.4694
+cap "Clkb" "4" 9.71094
+cap "Clk_In" "2" 772.197
+cap "li_1556_n369#" "7" 64.3828
+cap "2" "a_971_n597#" 457.606
+cap "Clkb" "2" 13.6829
+cap "2" "7" 38.6655
+cap "3" "VDD" 136.674
+cap "li_1556_n369#" "VDD" 3.7651
+cap "5" "VDD" 144.699
+cap "Clk_Out" "6" 8.23846
+cap "VDD" "4" 87.618
+cap "3" "5" 16.6953
+cap "3" "4" 130.479
+cap "li_1553_n470#" "6" 33.5915
+cap "5" "4" 29.8951
+cap "VDD" "2" 250.304
+cap "3" "2" 109.908
+cap "a_971_n597#" "6" 12.7317
+cap "li_1556_n369#" "2" 10.2936
+cap "5" "2" 151.309
+cap "4" "2" 113.627
+cap "6" "7" 157.372
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" 2.94263
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 10.378
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 34.9474
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 9.31816
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 8.20812
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 9.52101
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 14.6086
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 63.8225
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" 101.363
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 21.3754
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 100.03
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" 0.215969
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 236.191
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 14.9692
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 188.888
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 18.1003
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 84.3136
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 75.7818
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 76.2931
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 68.6513
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 61.8779
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 4.53321
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" -48.0139
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 27.7803
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" 213.62
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 0.668788
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" 29.3333
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 12.731
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" 36.5315
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 45.2419
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 5.47232
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 11.1681
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 97.9663
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 20.7091
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 15.8854
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 55.1837
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" -29.567
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" 25.3679
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 17.6716
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 102.424
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" 19.6289
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" 42.5694
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 124.772
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 33.4734
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 10.1789
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 8.12678
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 0.770619
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 8.49674
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 56.1379
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" 3.54362
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 0.215969
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 34.9474
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n73_n115#" 5.03919
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 16.2506
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 9.52101
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" 22.0544
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 0.663184
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 46.0273
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" -67.2997
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_5/VSUBS" -136.753 0 0 0 0 0 0 0 0 37968 -336 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8624 -706 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_4/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_15_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_15_n79#" "a_1687_n501#"
+merge "a_1687_n501#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_3/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/VSUBS" "sky130_fd_pr__nfet_01v8_NDE37H_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/VSUBS" "sky130_fd_pr__pfet_01v8_A7DS5R_2/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_2/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_n79#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/VSUBS" "sky130_fd_pr__pfet_01v8_A7DS5R_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/VSUBS" "sky130_fd_pr__pfet_01v8_A7DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" "GND"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_5/w_n109_n86#" -975.658 0 0 0 0 -327834 -7544 0 0 0 0 65088 -576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5760 -568 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_15_n36#" "a_1687_n263#"
+merge "a_1687_n263#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/w_n109_n140#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/w_n109_n140#" "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_2/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/w_n109_n86#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/w_n109_n140#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/w_n109_n140#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "VDD"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" -212.168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1230 -142 0 0 -1736 -388 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "2"
+merge "2" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_37#" -195.578 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10701 -142 0 0 14450 -688 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n73_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "7"
+merge "7" "li_1553_n470#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n73_n78#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n73_n115#" -7.31553 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25483 -558 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n73_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "5"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_n73_n78#" "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_15_n79#" -27.88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3230 -462 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_15_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n73_n115#"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n73_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "3"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 3.92545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17342 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "Clk_Out"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" -152.465 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5781 -284 0 0 25905 -546 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" "li_1556_n369#"
+merge "li_1556_n369#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_37#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_15_n78#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_15_n78#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "6"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n118_22#" -185.194 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3054 -342 0 0 10506 -224 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n118_22#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "Clk_In"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_n33_37#" -319.74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2280 -212 0 0 -2482 -486 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_n33_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_15_n36#" "li_204_n127#"
+merge "li_204_n127#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "Clkb"
+merge "Clkb" "a_971_n597#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_37#" -71.9553 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1230 -142 0 0 -2482 -350 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_37#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_15_n78#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_15_n78#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "4"
diff --git a/mag/3-stage_cs-vco_dp9/FD_v2.mag b/mag/3-stage_cs-vco_dp9/FD_v2.mag
new file mode 100755
index 0000000..017227a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD_v2.mag
@@ -0,0 +1,267 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< nwell >>
+rect 68 -313 1883 34
+<< pwell >>
+rect 68 -697 1883 -313
+<< ndiff >>
+rect 1687 -501 1701 -417
+<< pdiff >>
+rect 1687 -263 1701 -119
+<< psubdiff >>
+rect 68 -676 179 -642
+rect 1772 -676 1883 -642
+<< nsubdiff >>
+rect 127 -37 151 -3
+rect 1800 -37 1827 -3
+<< psubdiffcont >>
+rect 179 -676 1772 -642
+<< nsubdiffcont >>
+rect 151 -37 1800 -3
+<< poly >>
+rect 434 -550 501 -521
+rect 434 -584 450 -550
+rect 484 -584 501 -550
+rect 434 -597 501 -584
+rect 971 -542 1050 -521
+rect 971 -576 986 -542
+rect 1020 -576 1050 -542
+rect 971 -597 1050 -576
+<< polycont >>
+rect 450 -584 484 -550
+rect 986 -576 1020 -542
+<< locali >>
+rect 68 -37 151 -3
+rect 1800 -37 1883 -3
+rect 116 -131 150 -37
+rect 316 -115 350 -37
+rect 818 -131 852 -37
+rect 982 -106 1115 -86
+rect 982 -136 988 -106
+rect 1022 -120 1115 -106
+rect 1022 -136 1028 -120
+rect 1322 -131 1356 -37
+rect 1641 -131 1675 -37
+rect 1713 -131 1747 -37
+rect 204 -403 238 -267
+rect 404 -280 438 -225
+rect 534 -280 568 -202
+rect 404 -314 568 -280
+rect 404 -403 438 -314
+rect 534 -380 568 -314
+rect 622 -335 656 -186
+rect 906 -334 940 -209
+rect 1077 -334 1111 -187
+rect 622 -369 810 -335
+rect 906 -368 1111 -334
+rect 622 -380 656 -369
+rect 906 -403 940 -368
+rect 1077 -397 1111 -368
+rect 1165 -335 1199 -186
+rect 1410 -335 1444 -209
+rect 1801 -334 1835 -209
+rect 1165 -369 1310 -335
+rect 1410 -369 1413 -335
+rect 1481 -369 1541 -335
+rect 1556 -369 1590 -335
+rect 1165 -380 1199 -369
+rect 1243 -470 1277 -369
+rect 1410 -403 1444 -369
+rect 116 -642 150 -503
+rect 316 -642 350 -477
+rect 434 -584 450 -550
+rect 484 -584 500 -550
+rect 818 -642 852 -488
+rect 1481 -433 1515 -369
+rect 1801 -403 1835 -368
+rect 970 -576 986 -542
+rect 1020 -576 1036 -542
+rect 1322 -642 1356 -501
+rect 1481 -510 1515 -467
+rect 1553 -470 1587 -436
+rect 1553 -513 1587 -477
+rect 1641 -642 1675 -486
+rect 1713 -642 1747 -486
+rect 68 -676 179 -642
+rect 1772 -676 1883 -642
+<< viali >>
+rect 151 -37 1800 -3
+rect 204 -127 238 -93
+rect 578 -127 612 -93
+rect 988 -140 1022 -106
+rect 1553 -165 1587 -131
+rect 120 -369 154 -335
+rect 320 -369 354 -335
+rect 1553 -262 1587 -228
+rect 1413 -369 1447 -335
+rect 1717 -369 1751 -335
+rect 1801 -368 1835 -334
+rect 204 -486 238 -452
+rect 450 -584 484 -550
+rect 1243 -504 1277 -470
+rect 1481 -467 1515 -433
+rect 986 -576 1020 -542
+rect 1553 -547 1587 -513
+rect 179 -676 1772 -642
+<< metal1 >>
+rect 68 -3 1883 9
+rect 68 -37 151 -3
+rect 1800 -37 1883 -3
+rect 68 -49 1883 -37
+rect 198 -87 244 -81
+rect 198 -93 624 -87
+rect 198 -127 204 -93
+rect 238 -127 578 -93
+rect 612 -127 624 -93
+rect 198 -133 624 -127
+rect 982 -106 1028 -94
+rect 198 -139 244 -133
+rect 982 -140 988 -106
+rect 1022 -140 1028 -106
+rect 982 -236 1028 -140
+rect 1547 -131 1593 -119
+rect 1547 -165 1553 -131
+rect 1587 -165 1593 -131
+rect 1547 -177 1593 -165
+rect 1553 -216 1587 -177
+rect 113 -282 1028 -236
+rect 1547 -228 1593 -216
+rect 1547 -262 1553 -228
+rect 1587 -262 1593 -228
+rect 1547 -274 1593 -262
+rect 113 -329 159 -282
+rect 68 -335 206 -329
+rect 68 -369 120 -335
+rect 154 -369 206 -335
+rect 68 -375 206 -369
+rect 304 -335 1459 -329
+rect 304 -369 320 -335
+rect 354 -369 1413 -335
+rect 1447 -369 1459 -335
+rect 304 -375 1459 -369
+rect 1553 -335 1587 -274
+rect 1705 -335 1763 -329
+rect 1553 -369 1717 -335
+rect 1751 -369 1763 -335
+rect 113 -544 159 -375
+rect 1475 -433 1521 -421
+rect 192 -452 1026 -446
+rect 192 -486 204 -452
+rect 238 -486 1026 -452
+rect 192 -492 1026 -486
+rect 980 -542 1026 -492
+rect 1231 -470 1287 -458
+rect 1475 -467 1481 -433
+rect 1515 -467 1521 -433
+rect 1475 -470 1521 -467
+rect 1231 -504 1243 -470
+rect 1277 -479 1521 -470
+rect 1277 -504 1515 -479
+rect 1553 -501 1587 -369
+rect 1705 -375 1763 -369
+rect 1795 -334 1841 -322
+rect 1795 -368 1801 -334
+rect 1835 -368 1883 -334
+rect 1795 -380 1841 -368
+rect 1231 -516 1287 -504
+rect 1547 -513 1593 -501
+rect 113 -550 496 -544
+rect 113 -584 450 -550
+rect 484 -584 496 -550
+rect 113 -590 496 -584
+rect 980 -576 986 -542
+rect 1020 -576 1026 -542
+rect 1547 -547 1553 -513
+rect 1587 -547 1593 -513
+rect 1547 -559 1593 -547
+rect 980 -588 1026 -576
+rect 68 -642 1883 -630
+rect 68 -676 179 -642
+rect 1772 -676 1883 -642
+rect 68 -688 1883 -676
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_0
+timestamp 1647613837
+transform 1 0 595 0 -1 -499
+box -118 -141 73 98
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_1
+timestamp 1647613837
+transform 1 0 1138 0 -1 -499
+box -118 -141 73 98
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_0
+timestamp 1647613837
+transform 1 0 177 0 1 -422
+box -73 -115 73 103
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_1
+timestamp 1647613837
+transform 1 0 377 0 1 -422
+box -73 -115 73 103
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_2
+timestamp 1647613837
+transform 1 0 879 0 1 -422
+box -73 -115 73 103
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_3
+timestamp 1647613837
+transform 1 0 1383 0 1 -422
+box -73 -115 73 103
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_4
+timestamp 1647613837
+transform 1 0 1614 0 1 -422
+box -73 -115 73 103
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_5
+timestamp 1647613837
+transform 1 0 1774 0 1 -422
+box -73 -115 73 103
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_0
+timestamp 1647613837
+transform 1 0 177 0 1 -227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_1
+timestamp 1647613837
+transform 1 0 377 0 1 -227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_2
+timestamp 1647613837
+transform 1 0 879 0 1 -227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_3
+timestamp 1647613837
+transform 1 0 1383 0 1 -227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_4
+timestamp 1647613837
+transform 1 0 1614 0 1 -227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_5
+timestamp 1647613837
+transform 1 0 1774 0 1 -227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_0
+timestamp 1647613837
+transform 1 0 595 0 1 -173
+box -109 -140 109 106
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_1
+timestamp 1647613837
+transform 1 0 1138 0 1 -173
+box -109 -140 109 106
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel metal1 1849 -368 1883 -334 1 Clk_Out
+port 4 n
+rlabel metal1 68 -49 102 9 1 VDD
+port 2 n
+rlabel metal1 96 -688 130 -630 1 GND
+port 3 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel locali 470 -312 495 -288 1 3
+rlabel locali 628 -321 653 -297 1 4
+rlabel locali 911 -323 936 -299 1 5
+rlabel locali 1169 -318 1194 -294 1 6
+rlabel locali 1414 -321 1439 -297 1 2
+rlabel metal1 1651 -363 1676 -339 1 7
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/FD_v2.spice b/mag/3-stage_cs-vco_dp9/FD_v2.spice
new file mode 100755
index 0000000..0882535
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD_v2.spice
@@ -0,0 +1,37 @@
+* NGSPICE file created from FD_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n33_75# a_n73_n115# VSUBS
+X0 a_15_n115# a_n33_75# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_n73_n67# a_n73_37# a_15_n67# VSUBS
+X0 a_15_n67# a_n73_37# a_n73_n67# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 li_622_n380# Clk_In li_404_n403# GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 li_1556_n369# li_204_n486# li_906_n403# GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 li_204_n486# VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 li_404_n403# VDD VDD li_320_n369# sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 li_906_n403# VDD VDD li_622_n380# sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 li_320_n369# VDD VDD li_1556_n369# sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD li_1553_n547# sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD li_1553_n547# VDD li_1556_n369# sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 GND li_320_n369# li_404_n403# GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 GND Clk_In li_204_n486# GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 GND li_622_n380# li_906_n403# GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 GND li_1556_n369# li_320_n369# GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 li_1553_n547# li_1556_n369# GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In li_1556_n369# li_906_n403# VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 li_204_n486# li_622_n380# li_404_n403# VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 GND li_1553_n547# Clk_Out GND sky130_fd_pr__nfet_01v8_PW5BNL
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/FD_v5.ext b/mag/3-stage_cs-vco_dp9/FD_v5.ext
new file mode 100755
index 0000000..66eb6aa
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD_v5.ext
@@ -0,0 +1,453 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0 1 0 -25 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0 1 0 -273 0 1 -422
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0 1 0 -273 0 1 -227
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0 1 0 -25 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW4BNL sky130_fd_pr__nfet_01v8_PW4BNL_0 1 0 562 0 1 -422
+use sky130_fd_pr__pfet_01v8_A4DS5R sky130_fd_pr__pfet_01v8_A4DS5R_0 1 0 562 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin 1 0 1329 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1 1 0 1845 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin 1 0 1329 0 1 -227
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1 1 0 1845 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1 1 0 2383 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1 1 0 2383 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2 1 0 3277 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2 1 0 3277 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2 1 0 3821 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2 1 0 3821 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb 1 0 4704 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb 1 0 4704 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1 1 0 5187 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2 1 0 5347 0 1 -422
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1 1 0 5187 0 1 -227
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2 1 0 5347 0 1 -227
+port "Clk_Out" 4 5510 -368 5544 -334 m1
+port "Clk_In" 1 -382 -369 -357 -335 m1
+port "VDD" 2 156 95 190 153 m1
+port "GND" 3 184 -760 218 -702 m1
+node "li_5126_n470#" 12 33.5477 5126 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3760_n667#" 354 984.836 3760 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2322_n667#" 354 982.926 2322 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5129_n369#" 12 32.2015 5129 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5462_n270#" 22 5.19444 5462 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 49 159.577 5510 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 7088 468 0 0 0 0 0 0 0 0 0 0
+node "5" 363 274.157 3304 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34442 2094 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 217 1546.63 1788 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17204 1148 138368 6108 0 0 0 0 0 0 0 0 0 0
+node "3" 350 272.852 1872 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33150 2018 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In_buf" 164 179.781 1356 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15504 980 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 50 218.18 -382 -369 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 7224 476 0 0 0 0 0 0 0 0 0 0
+node "6" 713 1109.97 3848 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64496 3944 21652 1290 0 0 0 0 0 0 0 0 0 0
+node "4" 571 529.467 2410 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53582 3234 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3760_n126#" 122 0 3760 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_2322_n126#" 122 0 2322 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_4024_n83#" 15 0 4024 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3848_n92#" 31 0 3848 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2586_n83#" 15 0 2586 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2410_n92#" 31 0 2410 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_90_n270#" 22 5.19444 90 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "dus" 225 534.77 2 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26540 1472 27052 1224 0 0 0 0 0 0 0 0 0 0
+node "7" 190 550.562 5126 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8296 760 31936 1828 0 0 0 0 0 0 0 0 0 0
+node "li_1356_17#" 12 0 1356 17 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb_int" 247 661.691 -246 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10846 978 33290 1872 0 0 0 0 0 0 0 0 0 0
+node "a_2222_n669#" 682 2777.76 2222 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14984 892 0 0 6732 600 88919 3942 0 0 0 0 0 0 0 0 0 0
+node "a_5260_n585#" 1440 0 5260 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n585#" 1440 0 -112 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n40_n319#" 903 65.9549 -40 -319 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2266 434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_5260_n263#" 4053 0 5260 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n263#" 4053 0 -112 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_3651_1#" 772 43.4388 3651 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 968 0 0 10812 840 161874 7130 0 0 0 0 0 0 0 0 0 0
+node "Clkb_buf" 1844 3803.45 2213 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31376 1860 0 0 43860 2988 289445 12672 0 0 0 0 0 0 0 0 0 0
+node "VDD" 40269 8766.5 156 95 m1 0 0 0 0 2909902 12836 0 0 158814 9478 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 284716 16816 343766 11970 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 184 -760 m1 0 0 0 0 0 0 0 0 0 0 201484 11920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 339320 20028 343708 11968 0 0 0 0 0 0 0 0 0 0
+cap "li_2322_n667#" "3" 6.03226
+cap "6" "li_4024_n83#" 22
+cap "Clkb_int" "a_n112_n585#" 7.0744
+cap "Clk_Out" "li_5462_n270#" 1.83333
+cap "4" "li_2586_n83#" 22
+cap "6" "a_3651_1#" 3.33929
+cap "li_3760_n126#" "2" 90.9805
+cap "4" "3" 170.035
+cap "VDD" "Clk_In" 5.1
+cap "4" "li_2410_n92#" 23.2941
+cap "li_2322_n126#" "Clkb_buf" 245.012
+cap "li_3760_n126#" "VDD" 408.583
+cap "2" "5" 307.459
+cap "Clkb_int" "a_n112_n263#" 2.9155
+cap "li_1356_17#" "a_3651_1#" 17
+cap "dus" "VDD" 98.7105
+cap "a_2222_n669#" "2" 270.978
+cap "li_1356_17#" "Clk_In_buf" 3.9507
+cap "2" "Clkb_buf" 2298.82
+cap "3" "a_3651_1#" 121.852
+cap "dus" "Clk_In" 18.3829
+cap "li_4024_n83#" "li_3848_n92#" 9.52817
+cap "5" "VDD" 254.495
+cap "li_2322_n126#" "4" 12.6168
+cap "Clk_In_buf" "3" 16.3922
+cap "Clk_Out" "li_5129_n369#" 5.31754
+cap "li_3760_n667#" "6" 88.9945
+cap "VDD" "Clkb_buf" 3417.21
+cap "4" "2" 415.856
+cap "li_3760_n126#" "5" 14.7632
+cap "7" "Clk_Out" 92.3198
+cap "6" "li_3848_n92#" 23.2941
+cap "VDD" "a_n40_n319#" 59.4
+cap "li_2322_n126#" "a_3651_1#" 170.315
+cap "4" "VDD" 275.264
+cap "dus" "Clkb_buf" 97.1345
+cap "li_90_n270#" "VDD" 45.9225
+cap "6" "li_5129_n369#" 74.8
+cap "dus" "a_n40_n319#" 15.0989
+cap "2" "a_3651_1#" 1934.53
+cap "5" "Clkb_buf" 28.3979
+cap "VDD" "Clk_Out" 30.2767
+cap "6" "7" 146.867
+cap "Clk_In_buf" "2" 5.13697
+cap "VDD" "li_4024_n83#" 39.5697
+cap "a_2222_n669#" "Clkb_buf" 653.464
+cap "li_2410_n92#" "li_2586_n83#" 9.52817
+cap "dus" "li_90_n270#" 26.2851
+cap "Clkb_int" "VDD" 280.253
+cap "6" "li_5126_n470#" 29.5263
+cap "VDD" "a_3651_1#" 2978.55
+cap "6" "2" 578.272
+cap "4" "5" 18.9494
+cap "a_2222_n669#" "li_2322_n667#" 602.691
+cap "7" "li_5462_n270#" 3.71523
+cap "Clkb_int" "Clk_In" 235.533
+cap "Clk_In_buf" "VDD" 70.9841
+cap "4" "a_2222_n669#" 9
+cap "li_3760_n126#" "a_3651_1#" 235.31
+cap "Clkb_int" "dus" 96.2735
+cap "4" "Clkb_buf" 3.33929
+cap "6" "VDD" 275.264
+cap "4" "li_2322_n667#" 88.9945
+cap "li_2322_n126#" "3" 14.7632
+cap "5" "a_3651_1#" 84.9256
+cap "VDD" "li_5462_n270#" 45.9225
+cap "li_3760_n126#" "6" 12.6168
+cap "li_2322_n126#" "li_2410_n92#" 1.88
+cap "3" "2" 331.614
+cap "a_2222_n669#" "a_3651_1#" 259.483
+cap "li_1356_17#" "VDD" 101.091
+cap "Clkb_buf" "a_3651_1#" 1409.52
+cap "VDD" "li_2586_n83#" 39.5697
+cap "6" "5" 171.334
+cap "a_2222_n669#" "Clk_In_buf" 10.6857
+cap "Clk_In_buf" "Clkb_buf" 74.1789
+cap "7" "li_5129_n369#" 61.6231
+cap "3" "VDD" 238.741
+cap "VDD" "li_3848_n92#" 43.293
+cap "li_5126_n470#" "li_5129_n369#" 15.2687
+cap "6" "Clkb_buf" 35.6561
+cap "4" "a_3651_1#" 121.852
+cap "Clkb_int" "li_90_n270#" 5.79139
+cap "li_2410_n92#" "VDD" 43.293
+cap "2" "li_5129_n369#" 5.96809
+cap "li_2322_n126#" "2" 90.9805
+cap "li_5126_n470#" "7" 181.929
+cap "7" "2" 12.3056
+cap "li_3760_n126#" "li_3848_n92#" 1.88
+cap "li_3760_n667#" "5" 6.03226
+cap "li_2322_n126#" "VDD" 408.583
+cap "li_1356_17#" "Clkb_buf" 27.0946
+cap "7" "VDD" 269.598
+cap "6" "Clk_Out" 8.23846
+cap "a_2222_n669#" "3" 7.94891
+cap "li_3760_n667#" "Clkb_buf" 602.691
+cap "Clk_In_buf" "a_3651_1#" 87.5799
+cap "3" "Clkb_buf" 24.1398
+cap "2" "VDD" 92.652
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" -138.428
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" -30.7228
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" 288.302
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" 11.4
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 145.425
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" -9.58974
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 529.086
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MNClkin/a_15_n163#" 21.3071
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 374.693
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" 135.963
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" 46.6931
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" 61.2575
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 75.8306
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "MNinv1/a_191_n163#" 53.3624
+cap "MNTgate1/a_15_n163#" "MNClkin/a_15_n163#" -6.873
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MNinv1/a_n73_37#" 195.054
+cap "MNTgate1/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 1.23612
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" -213.068
+cap "MNinv1/a_n73_37#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 13.7802
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 217.334
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "MNClkin/a_15_n163#" 4.00786
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MNinv1/a_191_n163#" 275.689
+cap "MNinv1/a_n73_37#" "MNinv1/a_191_n163#" 187.723
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 82.8018
+cap "MNTgate1/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 17.5757
+cap "MNTgate1/a_15_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 1.8255
+cap "MNinv1/a_n73_37#" "MNClkin/a_15_n163#" 135.831
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MNClkin/a_15_n163#" 522.162
+cap "MNTgate1/a_15_n163#" "MNinv1/a_191_n163#" 14.2405
+cap "MNClkin/a_15_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" -151.945
+cap "MNinv1/a_191_n163#" "MNClkin/a_15_n163#" 67.1697
+cap "MNinv1/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" -6.48841
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 217.945
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 33
+cap "MNinv2/a_191_n163#" "MNinv1/a_191_n163#" 26.5082
+cap "2" "MNinv2/a_191_n163#" -1.42109e-14
+cap "MPinv1/a_279_n36#" "MNTgate2/a_15_n163#" 20.6585
+cap "MPinv1/a_279_n36#" "MPTgate2/a_n15_n81#" 12.7582
+cap "MNinv2/a_n73_n163#" "MNinv2/a_191_n163#" 37.1757
+cap "MPinv1/a_279_n36#" "MNinv2/a_191_n163#" -14.6416
+cap "MNTgate1/a_n15_n199#" "MNTgate2/a_n15_n199#" 109.567
+cap "MNTgate1/a_15_n163#" "MNinv1/a_191_n163#" 307.928
+cap "2" "MNTgate1/a_15_n163#" 123.703
+cap "MNinv2/a_n73_n163#" "MNTgate1/a_15_n163#" 52.0859
+cap "MNTgate2/a_n15_n199#" "MPTgate2/a_n15_n81#" 2.43269
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_15_n163#" 6.53314
+cap "MPTgate1/a_n15_n81#" "MNinv1/a_191_n163#" 150.312
+cap "MNTgate2/a_n15_n199#" "MNinv2/a_191_n163#" 81.901
+cap "MPinv1/a_279_n36#" "MNTgate1/a_15_n163#" -163.785
+cap "MPTgate2/a_n15_n81#" "MNinv2/a_191_n163#" 85.0149
+cap "MPinv1/a_279_n36#" "MPTgate1/a_n15_n81#" -215.618
+cap "MNTgate2/a_15_n163#" "MNinv2/a_191_n163#" -2.92226
+cap "MNTgate1/a_n15_n199#" "MNTgate1/a_15_n163#" 24.0588
+cap "MNTgate1/a_n15_n199#" "MNinv1/a_n73_37#" 0.332021
+cap "MNTgate2/a_n15_n199#" "MNTgate1/a_15_n163#" -159.294
+cap "MNTgate1/a_n15_n199#" "MPTgate1/a_n15_n81#" 27.0803
+cap "MNTgate1/a_15_n163#" "MPTgate2/a_n15_n81#" -166.446
+cap "MNTgate1/a_15_n163#" "MNinv2/a_191_n163#" 218.748
+cap "MPTgate1/a_n15_n81#" "MPTgate2/a_n15_n81#" 71.815
+cap "MNinv2/a_n73_n163#" "MNinv1/a_191_n163#" 69.7567
+cap "MPinv1/a_279_n36#" "MNinv1/a_191_n163#" -167.423
+cap "MNinv2/a_n73_n163#" "MPinv1/a_279_n36#" 16.5
+cap "MNTgate1/a_15_n163#" "MPTgate1/a_n15_n81#" -75.8445
+cap "MNTgate1/a_n15_n199#" "MNinv1/a_191_n163#" 79.491
+cap "MPTgate1/a_n15_n81#" "MNinv1/a_n73_37#" 0.96988
+cap "MNTgate2/a_n15_n199#" "MNinv1/a_191_n163#" 204.7
+cap "MNinv2/a_n73_n163#" "MNTgate2/a_n15_n199#" 102.35
+cap "MPTgate2/a_n15_n81#" "MNinv1/a_191_n163#" 59.2502
+cap "MNfb/a_n73_n163#" "MNfb/a_15_n163#" 69.8638
+cap "MNbuf1/a_n73_n163#" "MPinv2/a_279_n36#" -4.98108
+cap "MPinv2/a_279_n36#" "MPTgate2/a_n15_n81#" -235.15
+cap "MNinv2/a_191_n163#" "MNfb/a_n73_n163#" 73.6429
+cap "MNbuf2/a_15_n163#" "MNfb/a_n73_n163#" 20.5987
+cap "MNbuf1/a_n73_n163#" "MNfb/a_n73_n163#" -46.4039
+cap "MNinv2/a_191_n163#" "MNfb/a_15_n163#" 27.7597
+cap "MNTgate2/a_15_n163#" "MNfb/a_n73_n163#" 258.11
+cap "MNbuf1/a_n73_n163#" "MNfb/a_15_n163#" 129.706
+cap "MNTgate2/a_15_n163#" "MNfb/a_15_n163#" 440.45
+cap "MNTgate2/a_15_n163#" "MNbuf2/a_15_n163#" 4.24837
+cap "MPinv2/a_279_n36#" "MNfb/a_n73_n163#" 17.2279
+cap "MNTgate2/a_15_n163#" "MNinv2/a_191_n163#" 388.409
+cap "MNbuf1/a_n73_n163#" "MNbuf2/a_15_n163#" 37.9346
+cap "MNTgate2/a_15_n163#" "MNbuf1/a_n73_n163#" 97.3094
+cap "MPinv2/a_279_n36#" "MNfb/a_15_n163#" 31.9471
+cap "MNinv2/a_191_n163#" "MPTgate2/a_n15_n81#" 159.969
+cap "MNTgate2/a_n15_n199#" "MNinv2/a_191_n163#" 79.491
+cap "MNTgate2/a_n15_n199#" "MPinv2/a_n15_n133#" 2.04298
+cap "MNTgate2/a_15_n163#" "MPTgate2/a_n15_n81#" 140.389
+cap "MPTgate2/a_n15_n81#" "MPinv2/a_n15_n133#" 3.10902
+cap "MNTgate2/a_15_n163#" "MNTgate2/a_n15_n199#" 25.6357
+cap "MNinv2/a_191_n163#" "MPinv2/a_279_n36#" -182.47
+cap "MNTgate2/a_n15_n199#" "MPTgate2/a_n15_n81#" 31.2823
+cap "MPinv2/a_279_n36#" "MNbuf2/a_15_n163#" 45.2648
+cap "MNTgate2/a_15_n163#" "MPinv2/a_279_n36#" -214.066
+cap "MPfb/a_103_n36#" "MNfb/a_191_n163#" 31.8522
+cap "MNbuf1/a_n73_n163#" "MPfb/a_103_n36#" 66.7316
+cap "MNbuf1/a_n73_n163#" "MNbuf1/a_n73_37#" 30.087
+cap "MNbuf2/a_15_n163#" "MNfb/a_103_n163#" 57.4821
+cap "MNfb/a_103_n163#" "MNfb/a_191_n163#" 21.0913
+cap "MNbuf1/a_n73_n163#" "MNfb/a_103_n163#" -23.09
+cap "MNbuf1/a_n73_37#" "MNfb/a_103_n163#" 21.1947
+cap "MPfb/a_103_n36#" "MNfb/a_103_n163#" 19.0137
+cap "MNbuf2/a_15_n163#" "MNbuf1/a_n73_n163#" 143.468
+cap "MPfb/a_n15_n133#" "MNbuf1/a_n73_n163#" 5.41463
+cap "MNbuf1/a_n73_n163#" "MNfb/a_191_n163#" 0.0772348
+cap "MNbuf2/a_15_n163#" "MNbuf1/a_n73_37#" 4.24837
+cap "MNbuf2/a_15_n163#" "MPfb/a_103_n36#" 89.1249
+merge "MPbuf2/a_103_n36#" "li_5462_n270#" -5338.22 0 0 0 0 -1793600 -19228 0 0 0 0 28800 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27738 -3248 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_5462_n270#" "MPbuf2/a_n73_n36#"
+merge "MPbuf2/a_n73_n36#" "MPbuf2/w_n109_n86#"
+merge "MPbuf2/w_n109_n86#" "MPbuf1/a_15_n36#"
+merge "MPbuf1/a_15_n36#" "a_5260_n263#"
+merge "a_5260_n263#" "MPbuf1/w_n109_n86#"
+merge "MPbuf1/w_n109_n86#" "MPfb/a_279_n36#"
+merge "MPfb/a_279_n36#" "MPfb/a_103_n36#"
+merge "MPfb/a_103_n36#" "MPfb/a_n73_n36#"
+merge "MPfb/a_n73_n36#" "MPfb/w_n109_n86#"
+merge "MPfb/w_n109_n86#" "MPTgate2/w_n109_n86#"
+merge "MPTgate2/w_n109_n86#" "MPinv2/a_279_n36#"
+merge "MPinv2/a_279_n36#" "MPinv2/a_103_n36#"
+merge "MPinv2/a_103_n36#" "MPinv2/a_n73_n36#"
+merge "MPinv2/a_n73_n36#" "MPinv2/w_n109_n86#"
+merge "MPinv2/w_n109_n86#" "MPTgate1/w_n109_n86#"
+merge "MPTgate1/w_n109_n86#" "MPinv1/a_n73_n36#"
+merge "MPinv1/a_n73_n36#" "MPinv1/a_279_n36#"
+merge "MPinv1/a_279_n36#" "MPinv1/a_103_n36#"
+merge "MPinv1/a_103_n36#" "MPinv1/w_n109_n86#"
+merge "MPinv1/w_n109_n86#" "MPClkin/a_279_n36#"
+merge "MPClkin/a_279_n36#" "MPClkin/a_103_n36#"
+merge "MPClkin/a_103_n36#" "MPClkin/a_n73_n36#"
+merge "MPClkin/a_n73_n36#" "MPClkin/w_n109_n86#"
+merge "MPClkin/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_455_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_455_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#" "li_90_n270#"
+merge "li_90_n270#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#" "a_n112_n263#"
+merge "a_n112_n263#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "VDD"
+merge "MNTgate2/a_n15_n199#" "MPTgate1/a_n15_n81#" -547.99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21032 -778 0 0 15354 -724 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate1/a_n15_n81#" "MPClkin/a_n15_n133#"
+merge "MPClkin/a_n15_n133#" "MNClkin/a_n73_37#"
+merge "MNClkin/a_n73_37#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_543_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_543_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_15_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_191_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_367_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_367_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "Clkb_buf"
+merge "MPbuf2/VSUBS" "MPbuf1/VSUBS" -952.932 0 0 0 0 0 0 0 0 16800 -1344 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120463 -5192 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf1/VSUBS" "MNbuf2/VSUBS"
+merge "MNbuf2/VSUBS" "MNbuf2/a_103_n163#"
+merge "MNbuf2/a_103_n163#" "MNbuf2/a_n73_n163#"
+merge "MNbuf2/a_n73_n163#" "MNbuf1/VSUBS"
+merge "MNbuf1/VSUBS" "MNbuf1/a_15_n163#"
+merge "MNbuf1/a_15_n163#" "a_5260_n585#"
+merge "a_5260_n585#" "MPfb/VSUBS"
+merge "MPfb/VSUBS" "MNfb/VSUBS"
+merge "MNfb/VSUBS" "MNfb/a_103_n163#"
+merge "MNfb/a_103_n163#" "MNfb/a_n73_n163#"
+merge "MNfb/a_n73_n163#" "MPTgate2/VSUBS"
+merge "MPTgate2/VSUBS" "MNTgate2/VSUBS"
+merge "MNTgate2/VSUBS" "MPinv2/VSUBS"
+merge "MPinv2/VSUBS" "MNinv2/VSUBS"
+merge "MNinv2/VSUBS" "MNinv2/a_103_n163#"
+merge "MNinv2/a_103_n163#" "MNinv2/a_n73_n163#"
+merge "MNinv2/a_n73_n163#" "MPTgate1/VSUBS"
+merge "MPTgate1/VSUBS" "MNTgate1/VSUBS"
+merge "MNTgate1/VSUBS" "MPinv1/VSUBS"
+merge "MPinv1/VSUBS" "MNinv1/VSUBS"
+merge "MNinv1/VSUBS" "MNinv1/a_103_n163#"
+merge "MNinv1/a_103_n163#" "MNinv1/a_n73_n163#"
+merge "MNinv1/a_n73_n163#" "MNClkin/a_103_n163#"
+merge "MNClkin/a_103_n163#" "MPClkin/VSUBS"
+merge "MPClkin/VSUBS" "MNClkin/VSUBS"
+merge "MNClkin/VSUBS" "MNClkin/a_n73_n163#"
+merge "MNClkin/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW4BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_279_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_279_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS" "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "GND"
+merge "GND" "a_n112_n585#"
+merge "MPinv2/a_n15_n133#" "MNinv2/a_n73_37#" -156.783 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7139 -538 0 0 59406 -1688 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNinv2/a_n73_37#" "MNTgate1/a_543_n163#"
+merge "MNTgate1/a_543_n163#" "MPTgate1/a_367_n36#"
+merge "MPTgate1/a_367_n36#" "MPTgate1/a_191_n36#"
+merge "MPTgate1/a_191_n36#" "li_2586_n83#"
+merge "li_2586_n83#" "MPTgate1/a_15_n36#"
+merge "MPTgate1/a_15_n36#" "li_2410_n92#"
+merge "li_2410_n92#" "MNTgate1/a_367_n163#"
+merge "MNTgate1/a_367_n163#" "MNTgate1/a_191_n163#"
+merge "MNTgate1/a_191_n163#" "MNTgate1/a_15_n163#"
+merge "MNTgate1/a_15_n163#" "4"
+merge "MPfb/a_191_n36#" "MPfb/a_15_n36#" -1112.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7170 -538 0 0 -3128 -524 -64400 -2800 0 0 0 0 0 0 0 0 0 0
+merge "MPfb/a_15_n36#" "MNfb/a_191_n163#"
+merge "MNfb/a_191_n163#" "MNfb/a_15_n163#"
+merge "MNfb/a_15_n163#" "MPinv1/a_n15_n133#"
+merge "MPinv1/a_n15_n133#" "MNinv1/a_n73_37#"
+merge "MNinv1/a_n73_37#" "2"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#" -406.518 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -824 0 0 -10166 -938 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "Clkb_int"
+merge "Clkb_int" "a_n40_n319#"
+merge "MPTgate2/a_n15_n81#" "MNTgate1/a_n15_n199#" 82.773 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12930 -240 0 0 79092 -1088 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n15_n199#" "MPClkin/a_191_n36#"
+merge "MPClkin/a_191_n36#" "MNClkin/a_191_n163#"
+merge "MNClkin/a_191_n163#" "MPClkin/a_15_n36#"
+merge "MPClkin/a_15_n36#" "li_1356_17#"
+merge "li_1356_17#" "a_3651_1#"
+merge "a_3651_1#" "MNClkin/a_15_n163#"
+merge "MNClkin/a_15_n163#" "Clk_In_buf"
+merge "Clk_In_buf" "a_2222_n669#"
+merge "MPbuf2/a_n15_n133#" "MPbuf1/a_n73_n36#" -348.154 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2487 -338 0 0 6478 -856 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf1/a_n73_n36#" "MNbuf2/a_n73_37#"
+merge "MNbuf2/a_n73_37#" "MNbuf1/a_n73_n163#"
+merge "MNbuf1/a_n73_n163#" "7"
+merge "7" "li_5126_n470#"
+merge "MNTgate2/a_631_n163#" "MNTgate2/a_455_n163#" -232.712 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36339 -1722 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate2/a_455_n163#" "MPTgate2/a_279_n36#"
+merge "MPTgate2/a_279_n36#" "MPTgate2/a_103_n36#"
+merge "MPTgate2/a_103_n36#" "MPTgate2/a_n73_n36#"
+merge "MPTgate2/a_n73_n36#" "li_3760_n126#"
+merge "li_3760_n126#" "MNTgate2/a_103_n163#"
+merge "MNTgate2/a_103_n163#" "MNTgate2/a_n73_n163#"
+merge "MNTgate2/a_n73_n163#" "MNTgate2/a_279_n163#"
+merge "MNTgate2/a_279_n163#" "li_3760_n667#"
+merge "li_3760_n667#" "MPinv2/a_191_n36#"
+merge "MPinv2/a_191_n36#" "MPinv2/a_15_n36#"
+merge "MPinv2/a_15_n36#" "MNinv2/a_15_n163#"
+merge "MNinv2/a_15_n163#" "MNinv2/a_191_n163#"
+merge "MNinv2/a_191_n163#" "5"
+merge "MNTgate1/a_631_n163#" "MNTgate1/a_455_n163#" -235.078 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34869 -1658 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_455_n163#" "MPTgate1/a_279_n36#"
+merge "MPTgate1/a_279_n36#" "MPTgate1/a_103_n36#"
+merge "MPTgate1/a_103_n36#" "MPTgate1/a_n73_n36#"
+merge "MPTgate1/a_n73_n36#" "li_2322_n126#"
+merge "li_2322_n126#" "MNTgate1/a_103_n163#"
+merge "MNTgate1/a_103_n163#" "MNTgate1/a_n73_n163#"
+merge "MNTgate1/a_n73_n163#" "MNTgate1/a_279_n163#"
+merge "MNTgate1/a_279_n163#" "li_2322_n667#"
+merge "li_2322_n667#" "MPinv1/a_191_n36#"
+merge "MPinv1/a_191_n36#" "MPinv1/a_15_n36#"
+merge "MPinv1/a_15_n36#" "MNinv1/a_15_n163#"
+merge "MNinv1/a_15_n163#" "MNinv1/a_191_n163#"
+merge "MNinv1/a_191_n163#" "3"
+merge "MPbuf1/a_n15_n133#" "MNbuf1/a_n73_37#" -335.515 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5417 -680 0 0 81336 -1884 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf1/a_n73_37#" "li_5129_n369#"
+merge "li_5129_n369#" "MPfb/a_n15_n133#"
+merge "MPfb/a_n15_n133#" "MNfb/a_n73_37#"
+merge "MNfb/a_n73_37#" "MNTgate2/a_543_n163#"
+merge "MNTgate2/a_543_n163#" "MPTgate2/a_367_n36#"
+merge "MPTgate2/a_367_n36#" "MPTgate2/a_191_n36#"
+merge "MPTgate2/a_191_n36#" "li_4024_n83#"
+merge "li_4024_n83#" "MPTgate2/a_15_n36#"
+merge "MPTgate2/a_15_n36#" "li_3848_n92#"
+merge "li_3848_n92#" "MNTgate2/a_367_n163#"
+merge "MNTgate2/a_367_n163#" "MNTgate2/a_191_n163#"
+merge "MNTgate2/a_191_n163#" "MNTgate2/a_15_n163#"
+merge "MNTgate2/a_15_n163#" "6"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" -255.794 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4258 -338 0 0 -2244 -200 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "Clk_In"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_37#" -474.404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -790 -934 0 0 -1190 -478 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "dus"
+merge "MPbuf2/a_15_n36#" "MNbuf2/a_15_n163#" -80.8137 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf2/a_15_n163#" "Clk_Out"
diff --git a/mag/3-stage_cs-vco_dp9/FD_v5.mag b/mag/3-stage_cs-vco_dp9/FD_v5.mag
new file mode 100755
index 0000000..5df315f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/FD_v5.mag
@@ -0,0 +1,544 @@
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+magscale 1 2
+timestamp 1647613837
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+rect 5462 -714 5496 -486
+rect -382 -748 -314 -714
+rect -27 -748 1331 -714
+rect 5345 -748 5544 -714
+<< viali >>
+rect -270 107 89 141
+rect 1303 107 5461 141
+rect -246 -147 -212 -113
+rect 2229 17 2263 51
+rect 2855 17 2889 51
+rect 3667 17 3701 51
+rect 4293 17 4327 51
+rect 5126 -21 5160 13
+rect -246 -235 -212 -201
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+rect 2 -368 355 -334
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+rect 619 -369 973 -335
+rect 1272 -369 1306 -335
+rect -246 -456 -212 -422
+rect 1788 -369 1822 -335
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+rect 5290 -369 5324 -335
+rect 5374 -368 5408 -334
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+rect 3111 -645 3145 -611
+rect 4564 -504 4598 -470
+rect 5054 -467 5088 -433
+rect 3676 -645 3710 -611
+rect 4549 -645 4583 -611
+rect 5126 -619 5160 -585
+rect -289 -748 -27 -714
+rect 1331 -748 5345 -714
+<< metal1 >>
+rect -383 141 5544 153
+rect -383 107 -270 141
+rect 89 107 1303 141
+rect 5461 107 5544 141
+rect -383 95 5544 107
+rect 1265 51 2917 57
+rect 1265 17 2229 51
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+rect 3647 51 4355 57
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+rect 5120 13 5166 25
+rect -252 -113 -206 -101
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+rect -212 -235 -206 -201
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+rect -208 -369 -202 -335
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+rect -4 -327 42 -322
+rect 1265 -325 1311 11
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+rect 1390 -235 1396 -49
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+rect 1353 -605 1399 -580
+rect 3653 -605 3699 -465
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+rect 1353 -645 2238 -611
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+rect 3145 -645 3157 -611
+rect 1353 -651 3157 -645
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+rect 3647 -645 3676 -611
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+rect 5120 -631 5166 -619
+rect 3647 -651 4595 -645
+rect 3653 -660 3699 -651
+rect -382 -714 5544 -702
+rect -382 -748 -289 -714
+rect -27 -748 1331 -714
+rect 5345 -748 5544 -714
+rect -382 -760 5544 -748
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin
+timestamp 1647613837
+transform 1 0 1329 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1
+timestamp 1647613837
+transform 1 0 2383 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2
+timestamp 1647613837
+transform 1 0 3821 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1
+timestamp 1647613837
+transform 1 0 5187 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2
+timestamp 1647613837
+transform 1 0 5347 0 1 -422
+box -73 -199 161 103
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb
+timestamp 1647613837
+transform 1 0 4704 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1
+timestamp 1647613837
+transform 1 0 1845 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2
+timestamp 1647613837
+transform 1 0 3277 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin
+timestamp 1647613837
+transform 1 0 1329 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 1 0 2383 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2
+timestamp 1647613837
+transform 1 0 3821 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1
+timestamp 1647613837
+transform 1 0 5187 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2
+timestamp 1647613837
+transform 1 0 5347 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb
+timestamp 1647613837
+transform 1 0 4704 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1
+timestamp 1647613837
+transform 1 0 1845 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2
+timestamp 1647613837
+transform 1 0 3277 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW4BNL sky130_fd_pr__nfet_01v8_PW4BNL_0
+timestamp 1647613837
+transform 1 0 562 0 1 -422
+box -73 -199 425 103
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647613837
+transform 1 0 -25 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0
+timestamp 1647613837
+transform 1 0 -273 0 1 -422
+box -73 -199 161 103
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0
+timestamp 1647613837
+transform 1 0 -273 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0
+timestamp 1647613837
+transform 1 0 -25 0 1 -227
+box -109 -86 461 314
+use sky130_fd_pr__pfet_01v8_A4DS5R sky130_fd_pr__pfet_01v8_A4DS5R_0
+timestamp 1647613837
+transform 1 0 562 0 1 -227
+box -109 -133 637 314
+<< labels >>
+rlabel metal1 -382 -369 -357 -335 1 Clk_In
+port 1 n
+rlabel metal1 -95 -364 -56 -332 1 Clkb_int
+rlabel metal1 184 -760 218 -702 1 GND
+port 3 n
+rlabel metal1 156 95 190 153 1 VDD
+port 2 n
+rlabel locali 1938 -335 1963 -311 1 3
+rlabel locali 2416 -321 2441 -297 1 4
+rlabel locali 3309 -323 3334 -299 1 5
+rlabel locali 4735 -321 4760 -297 1 2
+rlabel locali 4568 -430 4592 -404 1 6
+rlabel metal1 5224 -363 5249 -339 1 7
+rlabel metal1 5510 -368 5544 -334 1 Clk_Out
+port 4 n
+rlabel metal1 1209 -365 1238 -342 1 Clkb_buf
+rlabel locali 1359 -328 1387 -296 1 Clk_In_buf
+rlabel metal1 416 -366 453 -336 1 dus
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/bsim4v5.out b/mag/3-stage_cs-vco_dp9/bsim4v5.out
new file mode 100755
index 0000000..f0cb474
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/bsim4v5.out
@@ -0,0 +1,5 @@
+BSIM4v5: Berkeley Short Channel IGFET Model-4
+Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
+
+++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++
+Model = x1.xxm23.x0:sky130_fd_pr__pfet_01v8__model.34
diff --git a/mag/3-stage_cs-vco_dp9/comp.out b/mag/3-stage_cs-vco_dp9/comp.out
new file mode 100755
index 0000000..68d6ba6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/comp.out
@@ -0,0 +1,85 @@
+Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: FD |Circuit 2: FD
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (8) |sky130_fd_pr__nfet_01v8 (8)
+sky130_fd_pr__pfet_01v8 (8) |sky130_fd_pr__pfet_01v8 (8)
+Number of devices: 16 |Number of devices: 16
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+NET mismatches: Class fragments follow (with fanout counts):
+Circuit 1: FD |Circuit 2: FD
+
+---------------------------------------------------------------------------------------
+Net: a_1194_132# |Net: 6
+ sky130_fd_pr__nfet_01v8/1 = 1 | sky130_fd_pr__nfet_01v8/1 = 1
+ sky130_fd_pr__pfet_01v8/2 = 2 | sky130_fd_pr__pfet_01v8/2 = 2
+ sky130_fd_pr__pfet_01v8/1 = 1 | sky130_fd_pr__pfet_01v8/1 = 1
+ sky130_fd_pr__nfet_01v8/2 = 2 | sky130_fd_pr__nfet_01v8/2 = 2
+---------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------
+Net: GND |Net: vss
+ sky130_fd_pr__nfet_01v8/3 = 5 | sky130_fd_pr__nfet_01v8/3 = 6
+ sky130_fd_pr__nfet_01v8/4 = 8 | sky130_fd_pr__nfet_01v8/4 = 8
+ sky130_fd_pr__nfet_01v8/1 = 1 |
+ |
+Net: VDD |Net: vdd
+ sky130_fd_pr__pfet_01v8/3 = 5 | sky130_fd_pr__pfet_01v8/3 = 6
+ sky130_fd_pr__pfet_01v8/4 = 8 | sky130_fd_pr__pfet_01v8/4 = 8
+ sky130_fd_pr__pfet_01v8/1 = 1 |
+---------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------
+Net: a_1574_124# |Net: 7
+ sky130_fd_pr__nfet_01v8/2 = 1 | sky130_fd_pr__nfet_01v8/2 = 1
+ sky130_fd_pr__pfet_01v8/3 = 1 | sky130_fd_pr__nfet_01v8/1 = 1
+ sky130_fd_pr__pfet_01v8/2 = 1 | sky130_fd_pr__pfet_01v8/2 = 1
+ sky130_fd_pr__nfet_01v8/3 = 1 | sky130_fd_pr__pfet_01v8/1 = 1
+---------------------------------------------------------------------------------------
+DEVICE mismatches: Class fragments follow (with node fanout counts):
+Circuit 1: FD |Circuit 2: FD
+
+---------------------------------------------------------------------------------------
+Instance: sky130_fd_pr__pfet_01v8:10 |Instance: sky130_fd_pr__pfet_01v8:M11
+ 1 = 14 | 1 = 4
+ 2 = 6 | 2 = 6
+ 3 = 4 | 3 = 14
+ 4 = 14 | 4 = 14
+---------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------
+Instance: sky130_fd_pr__nfet_01v8:15 |Instance: sky130_fd_pr__nfet_01v8:M12
+ 1 = 14 | 1 = 4
+ 2 = 6 | 2 = 6
+ 3 = 4 | 3 = 14
+ 4 = 14 | 4 = 14
+---------------------------------------------------------------------------------------
+Netlists do not match.
+Netlists do not match.
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5.ext
new file mode 100755
index 0000000..8d4d958
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5.ext
@@ -0,0 +1,415 @@
+timestamp 1645443682
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -926 0 1 1033
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -720 0 1 1033
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 -514 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 -308 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM9 1 0 -102 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM10 1 0 105 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM10 1 0 312 0 1 897
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23 1 0 1049 0 1 681
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12 1 0 633 0 1 701
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 314 0 1 381
+use sky130_fd_pr__pfet_01v8_BKC9WK XM5 1 0 97 0 1 362
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3 1 0 -103 0 1 362
+use sky130_fd_pr__pfet_01v8_BKC9WK XM1 1 0 -307 0 1 362
+use sky130_fd_pr__nfet_01v8_Q665WF XM24 1 0 940 0 1 -97
+use sky130_fd_pr__nfet_01v8_86PVFD XM13 1 0 621 0 1 -88
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 306 0 1 105
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM8 1 0 316 0 1 -391
+use sky130_fd_pr__nfet_01v8_26QSQN XM8 1 0 110 0 1 -391
+use sky130_fd_pr__nfet_01v8_LS29AB XM6 1 0 104 0 1 105
+use sky130_fd_pr__nfet_01v8_26QSQN XM7 1 0 -96 0 1 -393
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 1 0 -304 0 1 -397
+use sky130_fd_pr__nfet_01v8_LS29AB XM2 1 0 -306 0 1 106
+use sky130_fd_pr__nfet_01v8_LS29AB XM4 1 0 -102 0 1 105
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -717 0 1 -540
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -923 0 1 -540
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16 1 0 -510 0 1 -397
+port "out" 2 1544 118 1744 318 m1
+port "vss" 1 798 -918 998 -718 m1
+port "vctrl" 3 -1386 -752 -1186 -552 m1
+port "vdd" 0 768 1328 968 1528 m1
+node "m1_40_n138#" 1 216.652 40 -138 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0
+node "m1_n166_n140#" 1 216.652 -166 -140 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0
+node "out" 5 897.372 1544 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104560 4028 0 0 0 0 0 0 0 0 0 0
+node "m1_554_n2#" 8 927.774 554 -2 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104148 5328 0 0 0 0 0 0 0 0 0 0
+node "m1_327_30#" 6 816.784 327 30 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91306 4366 0 0 0 0 0 0 0 0 0 0
+node "m1_32_418#" 1 -27.88 32 418 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15560 858 0 0 0 0 0 0 0 0 0 0
+node "m1_n44_34#" 2 299.346 -44 34 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24616 1300 0 0 0 0 0 0 0 0 0 0
+node "m1_n368_n144#" 1 216.652 -368 -144 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0
+node "vss" 10 7658.74 798 -918 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 894204 16748 0 0 0 0 0 0 0 0 0 0
+node "vctrl" 5 1450.9 -1386 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58320 1892 91600 3150 0 0 0 0 0 0 0 0
+node "m1_n248_34#" 2 297.81 -248 34 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25028 1320 0 0 0 0 0 0 0 0 0 0
+node "m1_n390_206#" 5 491.594 -390 206 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36212 1880 26640 1376 0 0 0 0 0 0 0 0
+node "m1_n166_424#" 1 -27.88 -166 424 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15160 838 0 0 0 0 0 0 0 0 0 0
+node "m1_n370_410#" 1 -27.88 -370 410 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15640 862 0 0 0 0 0 0 0 0 0 0
+node "m1_n784_n440#" 9 424.444 -784 -440 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81424 4222 49952 1896 0 0 0 0 0 0 0 0
+node "vdd" 7 680.351 768 1328 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 840042 14376 0 0 0 0 0 0 0 0 0 0
+node "w_n1130_242#" 19436 8685.3 -1130 242 nw 0 0 0 0 2895100 7450 0 0 134708 7992 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134708 7992 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "w_n1130_n834#" 0 0 -1130 -834 pw 2819120 7392 0 0 0 0 0 0 0 0 142596 8456 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 142806 8496 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_n166_424#" "m1_n248_34#" 11.5714
+cap "m1_n390_206#" "m1_327_30#" 98.7204
+cap "m1_32_418#" "m1_327_30#" 5.75188
+cap "m1_n166_424#" "w_n1130_242#" 232.636
+cap "m1_n166_424#" "m1_n166_n140#" 4.81283
+cap "m1_554_n2#" "w_n1130_242#" 682.342
+cap "m1_n248_34#" "vss" 4.51187
+cap "m1_40_n138#" "m1_n368_n144#" 22.5
+cap "m1_n784_n440#" "m1_n368_n144#" 22.7394
+cap "out" "m1_554_n2#" 165.479
+cap "m1_40_n138#" "m1_32_418#" 3.93443
+cap "m1_n390_206#" "m1_40_n138#" 14.4
+cap "m1_32_418#" "m1_n784_n440#" 0.272727
+cap "m1_n390_206#" "m1_n784_n440#" 8.11017
+cap "m1_n166_n140#" "vss" 35.6629
+cap "out" "vss" 137.551
+cap "m1_n166_424#" "vdd" 41.7857
+cap "m1_554_n2#" "vdd" 694.694
+cap "m1_n248_34#" "m1_n368_n144#" 6.75
+cap "m1_32_418#" "m1_n248_34#" 1.125
+cap "m1_n390_206#" "m1_n248_34#" 383.756
+cap "m1_n44_34#" "vss" 5.81167
+cap "m1_n166_n140#" "m1_n368_n144#" 51.6667
+cap "m1_n390_206#" "w_n1130_242#" 322.978
+cap "m1_32_418#" "w_n1130_242#" 236.996
+cap "vctrl" "m1_n784_n440#" 2.41935
+cap "m1_n390_206#" "m1_n166_n140#" 2.46094
+cap "m1_n784_n440#" "m1_n370_410#" 47.5909
+cap "m1_n44_34#" "m1_n368_n144#" 1.90141
+cap "m1_n44_34#" "m1_32_418#" 19.2756
+cap "m1_n390_206#" "m1_n44_34#" 411.911
+cap "m1_32_418#" "vdd" 88.75
+cap "m1_n390_206#" "vdd" 10.7276
+cap "m1_40_n138#" "m1_327_30#" 4.0081
+cap "m1_n248_34#" "m1_n370_410#" 7.68293
+cap "m1_554_n2#" "vss" 574.927
+cap "m1_n370_410#" "w_n1130_242#" 237.868
+cap "m1_327_30#" "w_n1130_242#" 532.835
+cap "m1_n166_424#" "m1_32_418#" 107.943
+cap "m1_n44_34#" "m1_n370_410#" 2.2028
+cap "m1_40_n138#" "m1_n248_34#" 3.26613
+cap "m1_n368_n144#" "vss" 42.9981
+cap "m1_n784_n440#" "w_n1130_242#" 1034.92
+cap "m1_n390_206#" "vss" 28.2402
+cap "m1_n166_n140#" "m1_40_n138#" 50.9639
+cap "m1_n44_34#" "m1_327_30#" 30.0712
+cap "m1_327_30#" "vdd" 623.624
+cap "m1_n248_34#" "w_n1130_242#" 133.378
+cap "m1_n44_34#" "m1_40_n138#" 32.0198
+cap "m1_n166_n140#" "m1_n248_34#" 29.4176
+cap "m1_n784_n440#" "vdd" 1604.46
+cap "m1_n390_206#" "m1_n368_n144#" 13.4759
+cap "vctrl" "vss" 1658.75
+cap "m1_n166_424#" "m1_n370_410#" 103.445
+cap "out" "w_n1130_242#" 331.712
+cap "m1_n44_34#" "m1_n248_34#" 288.01
+cap "m1_n44_34#" "w_n1130_242#" 128.294
+cap "vdd" "w_n1130_242#" 3514.77
+cap "m1_554_n2#" "m1_327_30#" 491.768
+cap "m1_n44_34#" "m1_n166_n140#" 8.78049
+cap "m1_327_30#" "vss" 412.247
+cap "out" "vdd" 43.8679
+cap "m1_n166_424#" "m1_n784_n440#" 0.54878
+cap "m1_n370_410#" "m1_n368_n144#" 4.6978
+cap "m1_32_418#" "m1_n370_410#" 47.6105
+cap "m1_n390_206#" "m1_n370_410#" 13.4132
+cap "m1_40_n138#" "vss" 58.2769
+cap "m1_n784_n440#" "vss" 158.901
+cap "XM4/a_n33_33#" "XM4/a_15_n68#" 144.68
+cap "XM3/a_n73_n14#" "XM4/a_n73_n68#" 7.48452
+cap "XM11/a_18_n276#" "XM4/a_n33_33#" 6.32567
+cap "XM4/a_n33_33#" "XM2/a_n73_n68#" 4.21453
+cap "XM1/a_n73_n14#" "XM4/a_n33_33#" -7.68293
+cap "XMDUM16/a_n76_n209#" "XM4/a_n73_n68#" 494.995
+cap "XM2/a_n33_33#" "XM4/a_n73_n68#" 10.2316
+cap "XM2/a_n33_33#" "XM3/a_n73_n14#" 12.0364
+cap "XM4/a_n33_33#" "XM1/w_n109_n114#" -46.9992
+cap "XM26/a_n76_n69#" "XM1/a_n73_n14#" 4.52732
+cap "XM26/a_n76_n69#" "XM2/a_n73_n68#" 49.819
+cap "XM6/a_n73_n68#" "XM4/a_n73_n68#" 91.1737
+cap "XMDUM16/a_n76_n209#" "XM2/a_n33_33#" 0.119134
+cap "XM4/a_n33_33#" "XM5/a_n73_n14#" 10.8281
+cap "XM4/a_n33_33#" "XM9/a_n33_235#" 4.15826
+cap "XMDUM16/a_n76_n209#" "XM6/a_n73_n68#" 165.821
+cap "XM13/w_n211_n330#" "XM26/a_n33_n157#" 753.59
+cap "XM4/a_15_n68#" "XM4/a_n73_n68#" 1.33946
+cap "XM4/a_n33_33#" "XM9/a_18_n276#" 0.10443
+cap "XMDUM16/a_n76_n209#" "XM4/a_15_n68#" 21.646
+cap "XM2/a_n73_n68#" "XM4/a_n73_n68#" 181.477
+cap "XM26/a_n33_n157#" "XM4/a_n33_33#" 9.35902
+cap "XM2/a_n33_33#" "XM4/a_15_n68#" 43.0514
+cap "XM11/a_18_n276#" "XM2/a_n33_33#" 0.208861
+cap "XM1/a_n73_n14#" "XM3/a_n73_n14#" 35.563
+cap "XMDUM16/a_n76_n209#" "XM2/a_n73_n68#" 597.62
+cap "XM4/a_15_n68#" "XM6/a_n73_n68#" 45.1426
+cap "XM26/a_n76_n69#" "XM26/a_n33_n157#" 1.24001
+cap "XM2/a_n33_33#" "XM2/a_n73_n68#" 10.7304
+cap "XM3/a_n73_n14#" "XM5/a_n73_n14#" 18.2121
+cap "XM1/a_n73_n14#" "XM2/a_n33_33#" 4.32761
+cap "XM3/a_n73_n14#" "XM1/w_n109_n114#" -21.0811
+cap "XM13/w_n211_n330#" "XM4/a_n33_33#" 365.835
+cap "XM2/a_n73_n68#" "XM6/a_n73_n68#" 40.7168
+cap "XM26/a_n76_n69#" "XM13/w_n211_n330#" 166.843
+cap "XM2/a_n33_33#" "XM1/w_n109_n114#" -25.8829
+cap "XM4/a_15_n68#" "XM21/a_15_n22#" 4.44812
+cap "XM4/a_15_n68#" "XM2/a_n73_n68#" 21.4809
+cap "XM1/a_n73_n14#" "XM4/a_15_n68#" 21.4892
+cap "XM26/a_n33_n157#" "XM4/a_n73_n68#" 1.47516
+cap "XM4/a_15_n68#" "XM22/a_15_n68#" 4.20079
+cap "XM4/a_15_n68#" "XM5/a_n73_n14#" 53.8689
+cap "XM1/a_n73_n14#" "XM2/a_n73_n68#" 7.64866
+cap "XM4/a_15_n68#" "XM1/w_n109_n114#" -19.4255
+cap "XM13/w_n211_n330#" "XM3/a_n73_n14#" 3.01613
+cap "XM13/w_n211_n330#" "XM4/a_n73_n68#" 428.385
+cap "XM26/a_n33_n157#" "XMDUM16/a_n76_n209#" 173.166
+cap "XM26/a_n33_n157#" "XM2/a_n33_33#" 9.38498
+cap "XM1/a_n73_n14#" "XM5/a_n73_n14#" 7.65346
+cap "XM1/a_n73_n14#" "XM1/w_n109_n114#" -27.1851
+cap "XM13/w_n211_n330#" "XMDUM16/a_n76_n209#" 1529.91
+cap "XM13/w_n211_n330#" "XM2/a_n33_33#" 288.739
+cap "XM4/a_15_n68#" "XM9/a_18_n276#" 6.12445
+cap "XM21/a_n73_n22#" "XM3/a_n73_n14#" 7.51239
+cap "XM4/a_n33_33#" "XM3/a_n73_n14#" 110.632
+cap "XM4/a_n33_33#" "XM4/a_n73_n68#" 104.739
+cap "XMDUM16/a_n76_n209#" "XM4/a_n33_33#" 11.632
+cap "XM2/a_n33_33#" "XM4/a_n33_33#" 169.016
+cap "XM26/a_n33_n157#" "XM2/a_n73_n68#" 1.83755
+cap "XM13/w_n211_n330#" "XM4/a_15_n68#" 88.1699
+cap "XM26/a_n76_n69#" "XMDUM16/a_n76_n209#" 302.755
+cap "XM4/a_n33_33#" "XM6/a_n73_n68#" 9.56124
+cap "XM11/a_n33_235#" "XM2/a_n33_33#" 4.16098
+cap "XM13/w_n211_n330#" "XM2/a_n73_n68#" 431.195
+cap "XM21/a_n73_n22#" "XM4/a_15_n68#" 8.08426
+cap "XM13/w_n211_n330#" "XM1/a_n73_n14#" 3.01613
+cap "XM3/w_n109_n114#" "XM22/a_15_n68#" 136.057
+cap "XM6/a_n73_n68#" "XM4/a_n73_n68#" 91.1737
+cap "XM4/a_n33_33#" "XM2/a_n33_33#" 24.0645
+cap "XM4/a_15_n68#" "XM21/a_n73_n22#" 8.08426
+cap "XM5/a_n73_n14#" "XM6/a_n73_n68#" 6.49068
+cap "XM16/a_18_n209#" "XM4/a_15_n68#" 305.605
+cap "XM16/a_18_n209#" "XM23/a_n173_n220#" 8.94024
+cap "XM16/a_n33_n297#" "XM4/a_15_n68#" 9.50224
+cap "XM3/w_n109_n114#" "XM4/a_15_n68#" -21.7639
+cap "XM23/a_n173_n220#" "XM3/w_n109_n114#" 2.08333
+cap "XM2/a_n33_33#" "XM16/a_18_n209#" 547.667
+cap "XM6/a_n73_n68#" "XM22/a_15_n68#" 19.7697
+cap "XM24/a_18_n129#" "XM12/a_n73_n240#" 2.18254
+cap "XM2/a_n33_33#" "XM21/a_n73_n22#" 59.5578
+cap "XM5/a_n73_n14#" "XM22/a_15_n68#" 17.2882
+cap "XM5/a_n73_n14#" "XM1/a_n73_n14#" 7.65346
+cap "XM22/a_15_n68#" "XM13/a_n73_n120#" 214.278
+cap "XMDUM10/a_18_n276#" "XM2/a_n33_33#" 0.270492
+cap "XM16/a_18_n209#" "XM21/a_n73_n22#" 12.3509
+cap "XM2/a_n33_33#" "XMDUM10/a_n33_235#" 4.37035
+cap "XM2/a_n33_33#" "XM3/w_n109_n114#" -27.643
+cap "XM16/a_18_n209#" "XM3/w_n109_n114#" 312.382
+cap "XM23/a_n173_n220#" "XM24/a_18_n129#" 7.10543e-15
+cap "XM23/a_n33_251#" "XM22/a_15_n68#" 1.56136
+cap "XM16/a_18_n209#" "XM16/a_n33_n297#" 296.4
+cap "XM6/a_n73_n68#" "XM4/a_15_n68#" 58.1657
+cap "XM23/a_n173_n220#" "XM13/a_n73_n120#" 13.68
+cap "XM5/a_n73_n14#" "XM4/a_15_n68#" 57.9216
+cap "XM3/w_n109_n114#" "XM21/a_n73_n22#" 15.1719
+cap "XM4/a_n33_33#" "XM6/a_n73_n68#" 9.56124
+cap "XM5/a_n73_n14#" "XM4/a_n33_33#" 10.8281
+cap "XM6/a_n73_n68#" "XM2/a_n73_n68#" 40.7168
+cap "XM2/a_n33_33#" "XM3/a_n73_n14#" 12.0364
+cap "XM22/a_15_n68#" "XM12/a_n73_n240#" 7.33339
+cap "XM2/a_n33_33#" "XM10/a_18_n276#" 5.35141
+cap "XM2/a_n33_33#" "XM13/a_n73_n120#" 0.417722
+cap "XM2/a_n33_33#" "XM4/a_n73_n68#" 10.2316
+cap "XM2/a_n33_33#" "XM6/a_n73_n68#" -3.83103
+cap "XM3/a_n73_n14#" "XM21/a_n73_n22#" 7.51239
+cap "XM22/a_15_n68#" "XM4/a_15_n68#" 10.5717
+cap "XM16/a_18_n209#" "XM24/a_18_n129#" 95.9334
+cap "XM10/a_n33_235#" "XM4/a_15_n68#" 3.86608
+cap "XM16/a_18_n209#" "XM4/a_n73_n68#" 79.298
+cap "XM21/a_n73_n22#" "XM13/a_n73_n120#" 1.94638
+cap "XM16/a_18_n209#" "XM13/a_n73_n120#" 497.657
+cap "XM5/a_n73_n14#" "XM16/a_18_n209#" 3.01613
+cap "XM5/a_n73_n14#" "XM21/a_n73_n22#" 31.882
+cap "XM16/a_18_n209#" "XM6/a_n73_n68#" 932.989
+cap "XM3/w_n109_n114#" "XM24/a_18_n129#" 4.63636
+cap "XM23/a_n173_n220#" "XM12/a_n73_n240#" 2.92553
+cap "XM3/w_n109_n114#" "XM13/a_n73_n120#" 102.686
+cap "XM6/a_n73_n68#" "XM16/a_n33_n297#" 0.011162
+cap "XM5/a_n73_n14#" "XM3/w_n109_n114#" -14.5116
+cap "XM2/a_n33_33#" "XM22/a_15_n68#" 68.5268
+cap "XM4/a_n33_33#" "XM4/a_15_n68#" 31.5164
+cap "XM16/a_18_n209#" "XM22/a_15_n68#" 144.011
+cap "XM22/a_15_n68#" "XM21/a_n73_n22#" 9.45975
+cap "XM16/a_18_n209#" "XM12/a_n73_n240#" 4.47012
+cap "XM5/a_n73_n14#" "XM3/a_n73_n14#" 18.2121
+cap "XM24/a_18_n129#" "XM13/a_n73_n120#" 78.0274
+cap "XMDUM10/a_18_n276#" "XM22/a_15_n68#" 7.32564
+cap "XM21/a_n73_n22#" "XM12/a_n73_n240#" 2.54737
+cap "XM2/a_n33_33#" "XM4/a_15_n68#" 172.582
+cap "XM23/a_114_n220#" "w_n1130_242#" -3.28
+cap "XM23/a_114_n220#" "XM23/a_63_n317#" 0.5625
+cap "XM11/a_18_n276#" "XM3/a_n73_n14#" 593.073
+cap "XM6/a_n33_33#" "XM11/a_18_n276#" 6.12445
+cap "XM1/w_n109_n114#" "XM1/a_n73_n14#" -9.86236
+cap "XM5/a_n73_n14#" "XM1/a_n73_n14#" 31.1981
+cap "XM2/a_n33_33#" "XM1/a_n73_n14#" -4.2419
+cap "XM11/a_n33_235#" "XM1/a_n73_n14#" 38.0734
+cap "XM2/a_n33_33#" "XM1/w_n109_n114#" 7.91899
+cap "XM3/a_n73_n14#" "XM1/a_n73_n14#" 139.92
+cap "XM11/a_n33_235#" "XM1/w_n109_n114#" -64.3553
+cap "XM4/a_n33_33#" "XM1/w_n109_n114#" 15.011
+cap "XM11/a_18_n276#" "XM1/a_n73_n14#" 632.298
+cap "XM3/a_n73_n14#" "XM1/w_n109_n114#" -11.5596
+cap "XM3/a_n73_n14#" "XM5/a_n73_n14#" 68.9586
+cap "XM2/a_n33_33#" "XM11/a_n33_235#" 4.16098
+cap "XM6/a_n33_33#" "XM1/w_n109_n114#" 7.10127
+cap "XM4/a_n33_33#" "XM11/a_n33_235#" 4.15826
+cap "XM11/a_18_n276#" "XM1/w_n109_n114#" 110.901
+cap "XM11/a_18_n276#" "XM5/a_n73_n14#" 219.962
+cap "XM3/a_n73_n14#" "XM11/a_n33_235#" -0.482172
+cap "XM3/a_n73_n14#" "XM4/a_n33_33#" -3.98822
+cap "XM2/a_n33_33#" "XM11/a_18_n276#" 0.208861
+cap "XM11/a_18_n276#" "XM11/a_n33_235#" 455.414
+cap "XM11/a_18_n276#" "XM4/a_n33_33#" 6.4301
+cap "XM13/w_n211_n330#" "XM11/a_18_n276#" 0.609231
+cap "XM11/a_n33_235#" "XM11/a_18_n276#" 9.74058
+cap "XM5/a_n73_n14#" "XM11/a_18_n276#" 492.821
+cap "XM5/a_n73_n14#" "XM11/a_n33_235#" 1.34113
+cap "XM12/a_15_n240#" "XM21/a_15_n22#" 79.9476
+cap "XM23/a_n78_n220#" "XM12/a_15_n240#" 273.614
+cap "XM11/a_18_n276#" "XM6/a_n33_33#" 7.90971
+cap "XM11/a_n33_235#" "XM6/a_n33_33#" 3.86608
+cap "XM5/a_n73_n14#" "XM6/a_n33_33#" -3.56843
+cap "XM11/a_18_n276#" "XM21/a_15_n22#" 768.197
+cap "XM11/a_18_n276#" "XM2/a_n33_33#" 25.0502
+cap "XM23/a_n78_n220#" "XM11/a_18_n276#" 300.586
+cap "XM1/a_n73_n14#" "XM5/a_n73_n14#" 31.1981
+cap "XM11/a_18_n276#" "XM3/a_n73_n14#" 79.2898
+cap "XM5/a_n73_n14#" "XM3/a_n73_n14#" 68.9586
+cap "XM11/a_18_n276#" "XM12/a_15_n240#" 912.953
+merge "XM10/a_n76_n276#" "XM5/a_n73_n14#" -45.3813 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 425 -276 0 0 0 0 0 0 0 0 0 0
+merge "XM5/a_n73_n14#" "m1_32_418#"
+merge "XM23/w_n311_n439#" "XM12/w_n211_n459#" -2740.91 0 0 0 0 -796452 -7004 0 0 -15222 -1404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -15222 -1404 59092 -4272 0 0 0 0 0 0 0 0 0 0
+merge "XM12/w_n211_n459#" "XM9/w_n112_n338#"
+merge "XM9/w_n112_n338#" "XM10/w_n112_n338#"
+merge "XM10/w_n112_n338#" "XMDUM10/w_n112_n338#"
+merge "XMDUM10/w_n112_n338#" "XM21/w_n109_n122#"
+merge "XM21/w_n109_n122#" "XM5/w_n109_n114#"
+merge "XM5/w_n109_n114#" "XM3/w_n109_n114#"
+merge "XM3/w_n109_n114#" "XMDUM25/w_n112_n198#"
+merge "XMDUM25/w_n112_n198#" "XM25/w_n112_n198#"
+merge "XM25/w_n112_n198#" "XMDUM11/w_n112_n338#"
+merge "XMDUM11/w_n112_n338#" "XM11/w_n112_n338#"
+merge "XM11/w_n112_n338#" "XM1/w_n109_n114#"
+merge "XM1/w_n109_n114#" "w_n1130_242#"
+merge "w_n1130_242#" "XM9/a_18_n276#"
+merge "XM9/a_18_n276#" "XM10/a_18_n276#"
+merge "XM10/a_18_n276#" "XMDUM10/a_18_n276#"
+merge "XMDUM10/a_18_n276#" "XMDUM10/a_n33_235#"
+merge "XMDUM10/a_n33_235#" "XMDUM25/a_18_n136#"
+merge "XMDUM25/a_18_n136#" "XMDUM25/a_n76_n136#"
+merge "XMDUM25/a_n76_n136#" "XMDUM25/a_n33_95#"
+merge "XMDUM25/a_n33_95#" "XM25/a_18_n136#"
+merge "XM25/a_18_n136#" "XMDUM11/a_n33_235#"
+merge "XMDUM11/a_n33_235#" "XMDUM11/a_18_n276#"
+merge "XMDUM11/a_18_n276#" "XMDUM11/a_n76_n276#"
+merge "XMDUM11/a_n76_n276#" "XM11/a_18_n276#"
+merge "XM11/a_18_n276#" "XM23/a_18_n220#"
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#"
+merge "XM23/a_n173_n220#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XMDUM10/a_n76_n276#"
+merge "XMDUM10/a_n76_n276#" "XM21/a_n73_n22#"
+merge "XM21/a_n73_n22#" "vdd"
+merge "XM21/a_n33_n119#" "XM5/a_15_n14#" -309.762 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228273 -916 0 0 0 0 0 0 0 0 0 0
+merge "XM5/a_15_n14#" "XM1/a_n33_n111#"
+merge "XM1/a_n33_n111#" "XM22/a_n33_33#"
+merge "XM22/a_n33_33#" "XM6/a_15_n68#"
+merge "XM6/a_15_n68#" "XM2/a_n33_33#"
+merge "XM2/a_n33_33#" "m1_n390_206#"
+merge "XM16/a_n76_n209#" "XM2/a_n73_n68#" -389.56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 302 -162 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_n73_n68#" "m1_n368_n144#"
+merge "XM23/VSUBS" "XM12/VSUBS" -1661.91 126520 -5604 0 0 0 0 0 0 0 0 -187117 -1458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -176107 -1498 145246 -3279 0 0 0 0 0 0 0 0 0 0
+merge "XM12/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM24/w_n214_n339#"
+merge "XM24/w_n214_n339#" "XM9/VSUBS"
+merge "XM9/VSUBS" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "XM22/a_n73_n68#"
+merge "XM22/a_n73_n68#" "XMDUM8/a_n33_n297#"
+merge "XMDUM8/a_n33_n297#" "XMDUM8/a_18_n209#"
+merge "XMDUM8/a_18_n209#" "XMDUM8/a_n76_n209#"
+merge "XMDUM8/a_n76_n209#" "XM8/a_18_n209#"
+merge "XM8/a_18_n209#" "XM7/a_18_n209#"
+merge "XM7/a_18_n209#" "XM16/a_18_n209#"
+merge "XM16/a_18_n209#" "XM26/a_18_n69#"
+merge "XM26/a_18_n69#" "XMDUM26/a_n33_n157#"
+merge "XMDUM26/a_n33_n157#" "XMDUM26/a_18_n69#"
+merge "XMDUM26/a_18_n69#" "XMDUM26/a_n76_n69#"
+merge "XMDUM26/a_n76_n69#" "XMDUM16/a_n33_n297#"
+merge "XMDUM16/a_n33_n297#" "XMDUM16/a_18_n209#"
+merge "XMDUM16/a_18_n209#" "XMDUM16/a_n76_n209#"
+merge "XMDUM16/a_n76_n209#" "vss"
+merge "vss" "XM10/VSUBS"
+merge "XM10/VSUBS" "XMDUM10/VSUBS"
+merge "XMDUM10/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "XM5/VSUBS"
+merge "XM5/VSUBS" "XM3/VSUBS"
+merge "XM3/VSUBS" "XMDUM25/VSUBS"
+merge "XMDUM25/VSUBS" "XM25/VSUBS"
+merge "XM25/VSUBS" "XMDUM11/VSUBS"
+merge "XMDUM11/VSUBS" "XM11/VSUBS"
+merge "XM11/VSUBS" "XM1/VSUBS"
+merge "XM1/VSUBS" "XM13/w_n211_n330#"
+merge "XM13/w_n211_n330#" "XM22/VSUBS"
+merge "XM22/VSUBS" "XMDUM8/VSUBS"
+merge "XMDUM8/VSUBS" "XM8/VSUBS"
+merge "XM8/VSUBS" "XM6/VSUBS"
+merge "XM6/VSUBS" "XM7/VSUBS"
+merge "XM7/VSUBS" "XM16/VSUBS"
+merge "XM16/VSUBS" "XM2/VSUBS"
+merge "XM2/VSUBS" "XM4/VSUBS"
+merge "XM4/VSUBS" "XM26/VSUBS"
+merge "XM26/VSUBS" "XMDUM26/VSUBS"
+merge "XMDUM26/VSUBS" "XMDUM16/VSUBS"
+merge "XMDUM16/VSUBS" "w_n1130_n834#"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -122.706 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2368 -360 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "XM3/a_n33_n111#" "XM1/a_15_n14#" -272.305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6808 -592 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_15_n14#" "XM2/a_15_n68#"
+merge "XM2/a_15_n68#" "XM4/a_n33_33#"
+merge "XM4/a_n33_33#" "m1_n248_34#"
+merge "XM12/a_n33_n337#" "XM13/a_n33_n208#" -471.419 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -228940 -1158 0 0 0 0 0 0 0 0 0 0
+merge "XM13/a_n33_n208#" "XM21/a_15_n22#"
+merge "XM21/a_15_n22#" "XM22/a_15_n68#"
+merge "XM22/a_15_n68#" "m1_327_30#"
+merge "XM9/a_n33_235#" "XM10/a_n33_235#" -217.598 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -21064 -1198 0 0 0 0 0 0 0 0 0 0
+merge "XM10/a_n33_235#" "XM25/a_n76_n136#"
+merge "XM25/a_n76_n136#" "XM25/a_n33_95#"
+merge "XM25/a_n33_95#" "XM11/a_n33_235#"
+merge "XM11/a_n33_235#" "XM26/a_n76_n69#"
+merge "XM26/a_n76_n69#" "m1_n784_n440#"
+merge "XM8/a_n33_n297#" "XM7/a_n33_n297#" -796.372 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6578 -824 0 0 0 0 0 0 0 0 0 0
+merge "XM7/a_n33_n297#" "XM16/a_n33_n297#"
+merge "XM16/a_n33_n297#" "XM26/a_n33_n157#"
+merge "XM26/a_n33_n157#" "vctrl"
+merge "XM7/a_n76_n209#" "XM4/a_n73_n68#" -389.236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 600 -172 0 0 0 0 0 0 0 0 0 0
+merge "XM4/a_n73_n68#" "m1_n166_n140#"
+merge "XM23/a_n33_251#" "XM23/a_63_n317#" -493.916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -69354 -1202 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_63_n317#" "XM23/a_n129_n317#"
+merge "XM23/a_n129_n317#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "m1_554_n2#"
+merge "XM8/a_n76_n209#" "XM6/a_n73_n68#" -389.647 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -112 -176 0 0 0 0 0 0 0 0 0 0
+merge "XM6/a_n73_n68#" "m1_40_n138#"
+merge "XM5/a_n33_n111#" "XM3/a_15_n14#" -284.186 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -67092 -568 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_15_n14#" "XM6/a_n33_33#"
+merge "XM6/a_n33_33#" "XM4/a_15_n68#"
+merge "XM4/a_15_n68#" "m1_n44_34#"
+merge "XM11/a_n76_n276#" "XM1/a_n73_n14#" 36.8639 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125832 -284 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_n73_n14#" "m1_n370_410#"
+merge "XM9/a_n76_n276#" "XM3/a_n73_n14#" -11.668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5200 -264 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_n73_n14#" "m1_n166_424#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5.spice
new file mode 100755
index 0000000..77aa4f4
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n211_n459# 0.64fF
+C1 a_15_n240# a_n73_n240# 0.52fF
+C2 a_n73_n240# a_n33_n337# 0.01fF
+C3 a_15_n240# w_n211_n459# 0.64fF
+C4 w_n211_n459# a_n33_n337# 0.48fF
+C5 a_15_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.31fF
+C7 a_n73_n240# VSUBS -0.31fF
+C8 a_n33_n337# VSUBS -0.14fF
+C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n129_n317# a_n78_n220# 0.00fF
+C1 a_n78_n220# a_114_n220# 0.18fF
+C2 a_18_n220# a_114_n220# 0.31fF
+C3 w_n311_n439# a_n78_n220# 0.49fF
+C4 a_18_n220# w_n311_n439# 0.44fF
+C5 a_18_n220# a_63_n317# 0.00fF
+C6 a_n129_n317# w_n311_n439# 0.23fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_18_n220# a_n33_251# 0.00fF
+C9 w_n311_n439# a_114_n220# 0.58fF
+C10 a_63_n317# a_n129_n317# 0.04fF
+C11 a_n78_n220# a_n173_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n129_n317# a_n33_251# 0.02fF
+C15 a_63_n317# w_n311_n439# 0.23fF
+C16 a_n129_n317# a_n173_n220# 0.00fF
+C17 a_18_n220# a_n78_n220# 0.31fF
+C18 w_n311_n439# a_n33_251# 0.28fF
+C19 a_114_n220# a_n173_n220# 0.07fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 w_n311_n439# a_n173_n220# 0.53fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.07fF
+C27 a_n129_n317# VSUBS -0.07fF
+C28 a_n33_251# VSUBS -0.07fF
+C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.22fF
+C1 a_n73_n120# a_n33_n208# 0.02fF
+C2 a_n33_n208# a_15_n120# 0.02fF
+C3 a_15_n120# w_n211_n330# 0.20fF
+C4 a_n73_n120# w_n211_n330# 0.20fF
+C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.21fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# w_n214_n339# 0.21fF
+C4 a_n76_n129# w_n214_n339# 0.21fF
+C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_18_n136# 0.16fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 a_n33_95# a_18_n136# 0.00fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 w_n112_n198# a_n76_n136# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_18_n276# 0.32fF
+C1 a_n33_235# a_n76_n276# 0.00fF
+C2 a_n33_235# a_18_n276# 0.00fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 w_n112_n338# a_n76_n276# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 w_n109_n122# a_15_n22# 0.11fF
+C1 a_n33_n119# a_n73_n22# 0.01fF
+C2 a_n33_n119# a_15_n22# 0.01fF
+C3 a_n33_n119# w_n109_n122# 0.19fF
+C4 a_15_n22# a_n73_n22# 0.13fF
+C5 w_n109_n122# a_n73_n22# 0.11fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.07fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 m1_32_418# m1_327_30# 0.02fF
+C1 m1_n370_410# m1_n166_424# 0.28fF
+C2 m1_n784_n440# m1_n166_424# 0.00fF
+C3 m1_n248_34# m1_40_n138# 0.02fF
+C4 m1_n44_34# m1_n370_410# 0.02fF
+C5 m1_n44_34# m1_n784_n440# 0.01fF
+C6 m1_n248_34# m1_n368_n144# 0.01fF
+C7 out vdd 0.68fF
+C8 m1_40_n138# m1_n390_206# 0.01fF
+C9 m1_n368_n144# m1_n390_206# 0.02fF
+C10 m1_40_n138# m1_327_30# 0.02fF
+C11 m1_n248_34# m1_n390_206# 0.58fF
+C12 m1_n44_34# vctrl 0.01fF
+C13 m1_32_418# m1_n166_424# 0.28fF
+C14 m1_n166_n140# m1_n166_424# 0.01fF
+C15 m1_554_n2# m1_n390_206# 0.00fF
+C16 m1_327_30# m1_n390_206# 0.17fF
+C17 m1_n44_34# m1_32_418# 0.13fF
+C18 m1_n44_34# m1_n166_n140# 0.01fF
+C19 m1_554_n2# m1_327_30# 0.79fF
+C20 m1_n44_34# m1_40_n138# 0.14fF
+C21 m1_n44_34# m1_n368_n144# 0.02fF
+C22 m1_n248_34# m1_n166_424# 0.12fF
+C23 m1_n166_424# m1_n390_206# 0.02fF
+C24 m1_n44_34# m1_n248_34# 0.46fF
+C25 m1_n44_34# m1_n390_206# 0.63fF
+C26 m1_n370_410# vdd 0.83fF
+C27 m1_n784_n440# vdd 3.04fF
+C28 m1_n44_34# m1_327_30# 0.05fF
+C29 m1_n784_n440# m1_n370_410# 0.09fF
+C30 m1_32_418# vdd 1.06fF
+C31 m1_554_n2# out 0.52fF
+C32 vctrl m1_n784_n440# 0.00fF
+C33 m1_n370_410# m1_32_418# 0.13fF
+C34 m1_n784_n440# m1_32_418# 0.00fF
+C35 m1_n248_34# vdd 0.11fF
+C36 vdd m1_n390_206# 0.38fF
+C37 vdd m1_327_30# 2.08fF
+C38 m1_554_n2# vdd 2.41fF
+C39 vctrl m1_n166_n140# 0.00fF
+C40 m1_n368_n144# m1_n370_410# 0.01fF
+C41 m1_n368_n144# m1_n784_n440# 0.07fF
+C42 m1_n248_34# m1_n784_n440# 0.01fF
+C43 vctrl m1_40_n138# 0.00fF
+C44 m1_n370_410# m1_n390_206# 0.01fF
+C45 m1_n784_n440# m1_n390_206# 0.02fF
+C46 vctrl m1_n368_n144# 0.00fF
+C47 vdd m1_n166_424# 0.93fF
+C48 m1_40_n138# m1_32_418# 0.01fF
+C49 vctrl m1_n248_34# 0.01fF
+C50 m1_40_n138# m1_n166_n140# 0.23fF
+C51 vctrl m1_n390_206# 0.01fF
+C52 m1_n44_34# vdd 0.13fF
+C53 m1_n368_n144# m1_n166_n140# 0.23fF
+C54 m1_n248_34# m1_32_418# 0.02fF
+C55 m1_n248_34# m1_n166_n140# 0.13fF
+C56 m1_n166_n140# m1_n390_206# 0.02fF
+C57 m1_n368_n144# m1_40_n138# 0.10fF
+C58 m1_327_30# vss 1.18fF
+C59 vdd vss 9.21fF
+C60 m1_40_n138# vss 0.99fF
+C61 m1_32_418# vss -0.48fF
+C62 m1_n44_34# vss 0.40fF
+C63 m1_n166_n140# vss 0.88fF
+C64 m1_n248_34# vss 0.37fF
+C65 m1_n166_424# vss -0.45fF
+C66 m1_n368_n144# vss 0.91fF
+C67 m1_n390_206# vss 1.06fF
+C68 m1_n370_410# vss -0.40fF
+C69 m1_n784_n440# vss 0.42fF
+C70 vctrl vss 4.00fF
+C71 out vss 0.56fF
+C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_before_0p36um_nmos.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_before_0p36um_nmos.spice
new file mode 100755
index 0000000..35b6839
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_before_0p36um_nmos.spice
@@ -0,0 +1,76 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220#
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ALRCN6 a_n33_33# a_15_n73# a_n73_n73# VSUBS
+X0 a_15_n73# a_n33_33# a_n73_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_N32XHY a_n33_33# a_15_n73# a_n73_n73# VSUBS
+X0 a_15_n73# a_n33_33# a_n73_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out sky130_fd_pr__pfet_01v8_9P8X3X
+XXM12 m1_554_n2# vdd vdd m1_326_30# sky130_fd_pr__pfet_01v8_V5LP55
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM13 m1_554_n2# vss vss m1_326_30# sky130_fd_pr__nfet_01v8_86PVFD
+Xsky130_fd_pr__nfet_01v8_ALRCN6_0 m1_n44_34# m1_n390_206# m1_40_n138# vss sky130_fd_pr__nfet_01v8_ALRCN6
+Xsky130_fd_pr__nfet_01v8_ALRCN6_1 m1_n248_34# m1_n44_34# m1_n166_n140# vss sky130_fd_pr__nfet_01v8_ALRCN6
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_0 vdd vdd m1_n686_n440# m1_32_418# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__nfet_01v8_ALRCN6_2 m1_n390_206# m1_n248_34# m1_n368_n144# vss sky130_fd_pr__nfet_01v8_ALRCN6
+Xsky130_fd_pr__pfet_01v8_XZZ25Z_0 vdd m1_n686_n440# vdd m1_n686_n440# sky130_fd_pr__pfet_01v8_XZZ25Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_1 vdd vdd m1_n686_n440# m1_n166_424# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_2 vdd vdd m1_n686_n440# m1_n370_410# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_BKC9WK_0 m1_32_418# m1_n44_34# vdd m1_n390_206# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_1 m1_n166_424# m1_n248_34# vdd m1_n44_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_2 m1_n370_410# m1_n390_206# vdd m1_n248_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__nfet_01v8_26QSQN_0 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_1 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_2 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_N32XHY_0 m1_n390_206# m1_326_30# vss vss sky130_fd_pr__nfet_01v8_N32XHY
+Xsky130_fd_pr__nfet_01v8_B87NCT_0 m1_n686_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM21 m1_326_30# m1_n390_206# vdd vdd sky130_fd_pr__pfet_01v8_AZHELG
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_just_for_LVS_works_fine.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_just_for_LVS_works_fine.spice
new file mode 100755
index 0000000..2e32713
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_just_for_LVS_works_fine.spice
@@ -0,0 +1,72 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220#
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out sky130_fd_pr__pfet_01v8_9P8X3X
+XXM12 m1_554_n2# vdd vdd m1_327_30# sky130_fd_pr__pfet_01v8_V5LP55
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_0 vdd vdd m1_n686_n440# m1_32_418# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_XZZ25Z_0 vdd m1_n686_n440# vdd m1_n686_n440# sky130_fd_pr__pfet_01v8_XZZ25Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_1 vdd vdd m1_n686_n440# m1_n166_424# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_2 vdd vdd m1_n686_n440# m1_n370_410# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_BKC9WK_0 m1_32_418# m1_n44_34# vdd m1_n390_206# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_1 m1_n166_424# m1_n248_34# vdd m1_n44_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_2 m1_n370_410# m1_n390_206# vdd m1_n248_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__nfet_01v8_26QSQN_0 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_1 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_2 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_LS29AB_0 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_1 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_2 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_3 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_B87NCT_0 m1_n686_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM21 m1_327_30# m1_n390_206# vdd vdd sky130_fd_pr__pfet_01v8_AZHELG
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_vdd_hack.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_vdd_hack.spice
new file mode 100755
index 0000000..b9cb2cd
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_-_vdd_hack.spice
@@ -0,0 +1,72 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220#
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vctrl vss out vdd
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out sky130_fd_pr__pfet_01v8_9P8X3X
+XXM12 m1_554_n2# vdd vdd m1_327_30# sky130_fd_pr__pfet_01v8_V5LP55
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_0 vdd vdd m1_n686_n440# m1_32_418# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_XZZ25Z_0 vdd m1_n686_n440# vdd m1_n686_n440# sky130_fd_pr__pfet_01v8_XZZ25Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_1 vdd vdd m1_n686_n440# m1_n166_424# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_2 vdd vdd m1_n686_n440# m1_n370_410# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_BKC9WK_0 m1_32_418# m1_n44_34# vdd m1_n390_206# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_1 m1_n166_424# m1_n248_34# vdd m1_n44_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_2 m1_n370_410# m1_n390_206# vdd m1_n248_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__nfet_01v8_26QSQN_0 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_1 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_2 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_LS29AB_0 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_1 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_2 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_3 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_B87NCT_0 m1_n686_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM21 m1_327_30# m1_n390_206# vdd vdd sky130_fd_pr__pfet_01v8_AZHELG
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ALL_CAPS_COMMENTED_OUT.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ALL_CAPS_COMMENTED_OUT.spice
new file mode 100755
index 0000000..78d9025
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ALL_CAPS_COMMENTED_OUT.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+*C0 a_n73_n240# w_n211_n459# 0.64fF
+*C1 a_15_n240# a_n73_n240# 0.52fF
+*C2 a_n73_n240# a_n33_n337# 0.01fF
+*C3 a_15_n240# w_n211_n459# 0.64fF
+*C4 w_n211_n459# a_n33_n337# 0.48fF
+*C5 a_15_n240# a_n33_n337# 0.01fF
+*C6 a_15_n240# VSUBS -0.31fF
+*C7 a_n73_n240# VSUBS -0.31fF
+*C8 a_n33_n337# VSUBS -0.14fF
+*C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+*C0 a_n129_n317# a_n78_n220# 0.00fF
+*C1 a_n78_n220# a_114_n220# 0.18fF
+*C2 a_18_n220# a_114_n220# 0.31fF
+*C3 w_n311_n439# a_n78_n220# 0.49fF
+*C4 a_18_n220# w_n311_n439# 0.44fF
+*C5 a_18_n220# a_63_n317# 0.00fF
+*C6 a_n129_n317# w_n311_n439# 0.23fF
+*C7 a_n78_n220# a_n33_251# 0.00fF
+*C8 a_18_n220# a_n33_251# 0.00fF
+*C9 w_n311_n439# a_114_n220# 0.58fF
+*C10 a_63_n317# a_n129_n317# 0.04fF
+*C11 a_n78_n220# a_n173_n220# 0.31fF
+*C12 a_18_n220# a_n173_n220# 0.14fF
+*C13 a_63_n317# a_114_n220# 0.00fF
+*C14 a_n129_n317# a_n33_251# 0.02fF
+*C15 a_63_n317# w_n311_n439# 0.23fF
+*C16 a_n129_n317# a_n173_n220# 0.00fF
+*C17 a_18_n220# a_n78_n220# 0.31fF
+*C18 w_n311_n439# a_n33_251# 0.28fF
+*C19 a_114_n220# a_n173_n220# 0.07fF
+*C20 a_63_n317# a_n33_251# 0.02fF
+*C21 w_n311_n439# a_n173_n220# 0.53fF
+*C22 a_114_n220# VSUBS -0.33fF
+*C23 a_18_n220# VSUBS -0.27fF
+*C24 a_n78_n220# VSUBS -0.33fF
+*C25 a_n173_n220# VSUBS -0.27fF
+*C26 a_63_n317# VSUBS -0.07fF
+*C27 a_n129_n317# VSUBS -0.07fF
+*C28 a_n33_251# VSUBS -0.07fF
+*C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+*C0 a_n73_n120# a_15_n120# 0.22fF
+*C1 a_n73_n120# a_n33_n208# 0.02fF
+*C2 a_n33_n208# a_15_n120# 0.02fF
+*C3 a_15_n120# w_n211_n330# 0.20fF
+*C4 a_n73_n120# w_n211_n330# 0.20fF
+*C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+*C0 a_n76_n129# a_18_n129# 0.21fF
+*C1 a_n76_n129# a_n33_n217# 0.01fF
+*C2 a_n33_n217# a_18_n129# 0.01fF
+*C3 a_18_n129# w_n214_n339# 0.21fF
+*C4 a_n76_n129# w_n214_n339# 0.21fF
+*C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+*C0 w_n112_n198# a_18_n136# 0.16fF
+*C1 a_n33_95# a_n76_n136# 0.00fF
+*C2 a_n33_95# a_18_n136# 0.00fF
+*C3 a_n33_95# w_n112_n198# 0.19fF
+*C4 a_18_n136# a_n76_n136# 0.20fF
+*C5 w_n112_n198# a_n76_n136# 0.16fF
+*C6 a_18_n136# VSUBS -0.15fF
+*C7 a_n76_n136# VSUBS -0.15fF
+*C8 a_n33_95# VSUBS -0.07fF
+*C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+*C0 a_n76_n69# a_18_n69# 0.17fF
+*C1 a_n76_n69# a_n33_n157# 0.00fF
+*C2 a_n33_n157# a_18_n69# 0.01fF
+*C3 a_18_n69# VSUBS 0.00fF
+*C4 a_n76_n69# VSUBS 0.00fF
+*C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+*C0 a_n76_n209# a_18_n209# 0.35fF
+*C1 a_n76_n209# a_n33_n297# 0.00fF
+*C2 a_n33_n297# a_18_n209# 0.00fF
+*C3 a_18_n209# VSUBS 0.00fF
+*C4 a_n76_n209# VSUBS 0.00fF
+*C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+*C0 w_n112_n338# a_18_n276# 0.32fF
+*C1 a_n33_235# a_n76_n276# 0.00fF
+*C2 a_n33_235# a_18_n276# 0.00fF
+*C3 a_n33_235# w_n112_n338# 0.19fF
+*C4 a_18_n276# a_n76_n276# 0.46fF
+*C5 w_n112_n338# a_n76_n276# 0.32fF
+*C6 a_18_n276# VSUBS -0.31fF
+*C7 a_n76_n276# VSUBS -0.31fF
+*C8 a_n33_235# VSUBS -0.07fF
+*C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+*C0 w_n109_n114# a_15_n14# 0.10fF
+*C1 a_n33_n111# a_n73_n14# 0.01fF
+*C2 a_n33_n111# a_15_n14# 0.01fF
+*C3 a_n33_n111# w_n109_n114# 0.19fF
+*C4 a_15_n14# a_n73_n14# 0.12fF
+*C5 w_n109_n114# a_n73_n14# 0.10fF
+*C6 a_15_n14# VSUBS -0.10fF
+*C7 a_n73_n14# VSUBS -0.10fF
+*C8 a_n33_n111# VSUBS -0.07fF
+*C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+*C0 a_n73_n68# a_15_n68# 0.11fF
+*C1 a_n73_n68# a_n33_33# 0.01fF
+*C2 a_n33_33# a_15_n68# 0.01fF
+*C3 a_15_n68# VSUBS 0.01fF
+*C4 a_n73_n68# VSUBS 0.01fF
+*C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+*C0 w_n109_n122# a_15_n22# 0.11fF
+*C1 a_n33_n119# a_n73_n22# 0.01fF
+*C2 a_n33_n119# a_15_n22# 0.01fF
+*C3 a_n33_n119# w_n109_n122# 0.19fF
+*C4 a_15_n22# a_n73_n22# 0.13fF
+*C5 w_n109_n122# a_n73_n22# 0.11fF
+*C6 a_15_n22# VSUBS -0.10fF
+*C7 a_n73_n22# VSUBS -0.11fF
+*C8 a_n33_n119# VSUBS -0.07fF
+*C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+*C0 m1_32_418# m1_327_30# 0.02fF
+*C1 m1_n370_410# m1_n166_424# 0.28fF
+*C2 m1_n784_n440# m1_n166_424# 0.00fF
+*C3 m1_n248_34# m1_40_n138# 0.02fF
+*C4 m1_n44_34# m1_n370_410# 0.02fF
+*C5 m1_n44_34# m1_n784_n440# 0.01fF
+*C6 m1_n248_34# m1_n368_n144# 0.01fF
+*C7 out vdd 0.68fF
+*C8 m1_40_n138# m1_n390_206# 0.01fF
+*C9 m1_n368_n144# m1_n390_206# 0.02fF
+*C10 m1_40_n138# m1_327_30# 0.02fF
+*C11 m1_n248_34# m1_n390_206# 0.58fF
+*C12 m1_n44_34# vctrl 0.01fF
+*C13 m1_32_418# m1_n166_424# 0.28fF
+*C14 m1_n166_n140# m1_n166_424# 0.01fF
+*C15 m1_554_n2# m1_n390_206# 0.00fF
+*C16 m1_327_30# m1_n390_206# 0.17fF
+*C17 m1_n44_34# m1_32_418# 0.13fF
+*C18 m1_n44_34# m1_n166_n140# 0.01fF
+*C19 m1_554_n2# m1_327_30# 0.79fF
+*C20 m1_n44_34# m1_40_n138# 0.14fF
+*C21 m1_n44_34# m1_n368_n144# 0.02fF
+*C22 m1_n248_34# m1_n166_424# 0.12fF
+*C23 m1_n166_424# m1_n390_206# 0.02fF
+*C24 m1_n44_34# m1_n248_34# 0.46fF
+*C25 m1_n44_34# m1_n390_206# 0.63fF
+*C26 m1_n370_410# vdd 0.83fF
+*C27 m1_n784_n440# vdd 3.04fF
+*C28 m1_n44_34# m1_327_30# 0.05fF
+*C29 m1_n784_n440# m1_n370_410# 0.09fF
+*C30 m1_32_418# vdd 1.06fF
+*C31 m1_554_n2# out 0.52fF
+*C32 vctrl m1_n784_n440# 0.00fF
+*C33 m1_n370_410# m1_32_418# 0.13fF
+*C34 m1_n784_n440# m1_32_418# 0.00fF
+*C35 m1_n248_34# vdd 0.11fF
+*C36 vdd m1_n390_206# 0.38fF
+*C37 vdd m1_327_30# 2.08fF
+*C38 m1_554_n2# vdd 2.41fF
+*C39 vctrl m1_n166_n140# 0.00fF
+*C40 m1_n368_n144# m1_n370_410# 0.01fF
+*C41 m1_n368_n144# m1_n784_n440# 0.07fF
+*C42 m1_n248_34# m1_n784_n440# 0.01fF
+*C43 vctrl m1_40_n138# 0.00fF
+*C44 m1_n370_410# m1_n390_206# 0.01fF
+*C45 m1_n784_n440# m1_n390_206# 0.02fF
+*C46 vctrl m1_n368_n144# 0.00fF
+*C47 vdd m1_n166_424# 0.93fF
+*C48 m1_40_n138# m1_32_418# 0.01fF
+*C49 vctrl m1_n248_34# 0.01fF
+*C50 m1_40_n138# m1_n166_n140# 0.23fF
+*C51 vctrl m1_n390_206# 0.01fF
+*C52 m1_n44_34# vdd 0.13fF
+*C53 m1_n368_n144# m1_n166_n140# 0.23fF
+*C54 m1_n248_34# m1_32_418# 0.02fF
+*C55 m1_n248_34# m1_n166_n140# 0.13fF
+*C56 m1_n166_n140# m1_n390_206# 0.02fF
+*C57 m1_n368_n144# m1_40_n138# 0.10fF
+*C58 m1_327_30# vss 1.18fF
+*C59 vdd vss 9.21fF
+*C60 m1_40_n138# vss 0.99fF
+*C61 m1_32_418# vss -0.48fF
+*C62 m1_n44_34# vss 0.40fF
+*C63 m1_n166_n140# vss 0.88fF
+*C64 m1_n248_34# vss 0.37fF
+*C65 m1_n166_424# vss -0.45fF
+*C66 m1_n368_n144# vss 0.91fF
+*C67 m1_n390_206# vss 1.06fF
+*C68 m1_n370_410# vss -0.40fF
+*C69 m1_n784_n440# vss 0.42fF
+*C70 vctrl vss 4.00fF
+*C71 out vss 0.56fF
+*C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ALL_TOP_LEVEL_SUBCKT_CAPS_COMMENTED_OUT.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ALL_TOP_LEVEL_SUBCKT_CAPS_COMMENTED_OUT.spice
new file mode 100755
index 0000000..68200c1
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ALL_TOP_LEVEL_SUBCKT_CAPS_COMMENTED_OUT.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n211_n459# 0.64fF
+C1 a_15_n240# a_n73_n240# 0.52fF
+C2 a_n73_n240# a_n33_n337# 0.01fF
+C3 a_15_n240# w_n211_n459# 0.64fF
+C4 w_n211_n459# a_n33_n337# 0.48fF
+C5 a_15_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.31fF
+C7 a_n73_n240# VSUBS -0.31fF
+C8 a_n33_n337# VSUBS -0.14fF
+C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n129_n317# a_n78_n220# 0.00fF
+C1 a_n78_n220# a_114_n220# 0.18fF
+C2 a_18_n220# a_114_n220# 0.31fF
+C3 w_n311_n439# a_n78_n220# 0.49fF
+C4 a_18_n220# w_n311_n439# 0.44fF
+C5 a_18_n220# a_63_n317# 0.00fF
+C6 a_n129_n317# w_n311_n439# 0.23fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_18_n220# a_n33_251# 0.00fF
+C9 w_n311_n439# a_114_n220# 0.58fF
+C10 a_63_n317# a_n129_n317# 0.04fF
+C11 a_n78_n220# a_n173_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n129_n317# a_n33_251# 0.02fF
+C15 a_63_n317# w_n311_n439# 0.23fF
+C16 a_n129_n317# a_n173_n220# 0.00fF
+C17 a_18_n220# a_n78_n220# 0.31fF
+C18 w_n311_n439# a_n33_251# 0.28fF
+C19 a_114_n220# a_n173_n220# 0.07fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 w_n311_n439# a_n173_n220# 0.53fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.07fF
+C27 a_n129_n317# VSUBS -0.07fF
+C28 a_n33_251# VSUBS -0.07fF
+C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.22fF
+C1 a_n73_n120# a_n33_n208# 0.02fF
+C2 a_n33_n208# a_15_n120# 0.02fF
+C3 a_15_n120# w_n211_n330# 0.20fF
+C4 a_n73_n120# w_n211_n330# 0.20fF
+C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.21fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# w_n214_n339# 0.21fF
+C4 a_n76_n129# w_n214_n339# 0.21fF
+C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_18_n136# 0.16fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 a_n33_95# a_18_n136# 0.00fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 w_n112_n198# a_n76_n136# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_18_n276# 0.32fF
+C1 a_n33_235# a_n76_n276# 0.00fF
+C2 a_n33_235# a_18_n276# 0.00fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 w_n112_n338# a_n76_n276# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 w_n109_n122# a_15_n22# 0.11fF
+C1 a_n33_n119# a_n73_n22# 0.01fF
+C2 a_n33_n119# a_15_n22# 0.01fF
+C3 a_n33_n119# w_n109_n122# 0.19fF
+C4 a_15_n22# a_n73_n22# 0.13fF
+C5 w_n109_n122# a_n73_n22# 0.11fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.07fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+*C0 m1_32_418# m1_327_30# 0.02fF
+*C1 m1_n370_410# m1_n166_424# 0.28fF
+*C2 m1_n784_n440# m1_n166_424# 0.00fF
+*C3 m1_n248_34# m1_40_n138# 0.02fF
+*C4 m1_n44_34# m1_n370_410# 0.02fF
+*C5 m1_n44_34# m1_n784_n440# 0.01fF
+*C6 m1_n248_34# m1_n368_n144# 0.01fF
+*C7 out vdd 0.68fF
+*C8 m1_40_n138# m1_n390_206# 0.01fF
+*C9 m1_n368_n144# m1_n390_206# 0.02fF
+*C10 m1_40_n138# m1_327_30# 0.02fF
+*C11 m1_n248_34# m1_n390_206# 0.58fF
+*C12 m1_n44_34# vctrl 0.01fF
+*C13 m1_32_418# m1_n166_424# 0.28fF
+*C14 m1_n166_n140# m1_n166_424# 0.01fF
+*C15 m1_554_n2# m1_n390_206# 0.00fF
+*C16 m1_327_30# m1_n390_206# 0.17fF
+*C17 m1_n44_34# m1_32_418# 0.13fF
+*C18 m1_n44_34# m1_n166_n140# 0.01fF
+*C19 m1_554_n2# m1_327_30# 0.79fF
+*C20 m1_n44_34# m1_40_n138# 0.14fF
+*C21 m1_n44_34# m1_n368_n144# 0.02fF
+*C22 m1_n248_34# m1_n166_424# 0.12fF
+*C23 m1_n166_424# m1_n390_206# 0.02fF
+*C24 m1_n44_34# m1_n248_34# 0.46fF
+*C25 m1_n44_34# m1_n390_206# 0.63fF
+*C26 m1_n370_410# vdd 0.83fF
+*C27 m1_n784_n440# vdd 3.04fF
+*C28 m1_n44_34# m1_327_30# 0.05fF
+*C29 m1_n784_n440# m1_n370_410# 0.09fF
+*C30 m1_32_418# vdd 1.06fF
+*C31 m1_554_n2# out 0.52fF
+*C32 vctrl m1_n784_n440# 0.00fF
+*C33 m1_n370_410# m1_32_418# 0.13fF
+*C34 m1_n784_n440# m1_32_418# 0.00fF
+*C35 m1_n248_34# vdd 0.11fF
+*C36 vdd m1_n390_206# 0.38fF
+*C37 vdd m1_327_30# 2.08fF
+*C38 m1_554_n2# vdd 2.41fF
+*C39 vctrl m1_n166_n140# 0.00fF
+*C40 m1_n368_n144# m1_n370_410# 0.01fF
+*C41 m1_n368_n144# m1_n784_n440# 0.07fF
+*C42 m1_n248_34# m1_n784_n440# 0.01fF
+*C43 vctrl m1_40_n138# 0.00fF
+*C44 m1_n370_410# m1_n390_206# 0.01fF
+*C45 m1_n784_n440# m1_n390_206# 0.02fF
+*C46 vctrl m1_n368_n144# 0.00fF
+*C47 vdd m1_n166_424# 0.93fF
+*C48 m1_40_n138# m1_32_418# 0.01fF
+*C49 vctrl m1_n248_34# 0.01fF
+*C50 m1_40_n138# m1_n166_n140# 0.23fF
+*C51 vctrl m1_n390_206# 0.01fF
+*C52 m1_n44_34# vdd 0.13fF
+*C53 m1_n368_n144# m1_n166_n140# 0.23fF
+*C54 m1_n248_34# m1_32_418# 0.02fF
+*C55 m1_n248_34# m1_n166_n140# 0.13fF
+*C56 m1_n166_n140# m1_n390_206# 0.02fF
+*C57 m1_n368_n144# m1_40_n138# 0.10fF
+*C58 m1_327_30# vss 1.18fF
+*C59 vdd vss 9.21fF
+*C60 m1_40_n138# vss 0.99fF
+*C61 m1_32_418# vss -0.48fF
+*C62 m1_n44_34# vss 0.40fF
+*C63 m1_n166_n140# vss 0.88fF
+*C64 m1_n248_34# vss 0.37fF
+*C65 m1_n166_424# vss -0.45fF
+*C66 m1_n368_n144# vss 0.91fF
+*C67 m1_n390_206# vss 1.06fF
+*C68 m1_n370_410# vss -0.40fF
+*C69 m1_n784_n440# vss 0.42fF
+*C70 vctrl vss 4.00fF
+*C71 out vss 0.56fF
+*C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET10_CAPS_COMMENTED_OUT.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET10_CAPS_COMMENTED_OUT.spice
new file mode 100755
index 0000000..229f277
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET10_CAPS_COMMENTED_OUT.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n211_n459# 0.64fF
+C1 a_15_n240# a_n73_n240# 0.52fF
+C2 a_n73_n240# a_n33_n337# 0.01fF
+C3 a_15_n240# w_n211_n459# 0.64fF
+C4 w_n211_n459# a_n33_n337# 0.48fF
+C5 a_15_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.31fF
+C7 a_n73_n240# VSUBS -0.31fF
+C8 a_n33_n337# VSUBS -0.14fF
+C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n129_n317# a_n78_n220# 0.00fF
+C1 a_n78_n220# a_114_n220# 0.18fF
+C2 a_18_n220# a_114_n220# 0.31fF
+C3 w_n311_n439# a_n78_n220# 0.49fF
+C4 a_18_n220# w_n311_n439# 0.44fF
+C5 a_18_n220# a_63_n317# 0.00fF
+C6 a_n129_n317# w_n311_n439# 0.23fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_18_n220# a_n33_251# 0.00fF
+C9 w_n311_n439# a_114_n220# 0.58fF
+C10 a_63_n317# a_n129_n317# 0.04fF
+C11 a_n78_n220# a_n173_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n129_n317# a_n33_251# 0.02fF
+C15 a_63_n317# w_n311_n439# 0.23fF
+C16 a_n129_n317# a_n173_n220# 0.00fF
+C17 a_18_n220# a_n78_n220# 0.31fF
+C18 w_n311_n439# a_n33_251# 0.28fF
+C19 a_114_n220# a_n173_n220# 0.07fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 w_n311_n439# a_n173_n220# 0.53fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.07fF
+C27 a_n129_n317# VSUBS -0.07fF
+C28 a_n33_251# VSUBS -0.07fF
+C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.22fF
+C1 a_n73_n120# a_n33_n208# 0.02fF
+C2 a_n33_n208# a_15_n120# 0.02fF
+C3 a_15_n120# w_n211_n330# 0.20fF
+C4 a_n73_n120# w_n211_n330# 0.20fF
+C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.21fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# w_n214_n339# 0.21fF
+C4 a_n76_n129# w_n214_n339# 0.21fF
+C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_18_n136# 0.16fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 a_n33_95# a_18_n136# 0.00fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 w_n112_n198# a_n76_n136# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_18_n276# 0.32fF
+C1 a_n33_235# a_n76_n276# 0.00fF
+C2 a_n33_235# a_18_n276# 0.00fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 w_n112_n338# a_n76_n276# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 w_n109_n122# a_15_n22# 0.11fF
+C1 a_n33_n119# a_n73_n22# 0.01fF
+C2 a_n33_n119# a_15_n22# 0.01fF
+C3 a_n33_n119# w_n109_n122# 0.19fF
+C4 a_15_n22# a_n73_n22# 0.13fF
+C5 w_n109_n122# a_n73_n22# 0.11fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.07fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 m1_32_418# m1_327_30# 0.02fF
+C1 m1_n370_410# m1_n166_424# 0.28fF
+C2 m1_n784_n440# m1_n166_424# 0.00fF
+C3 m1_n248_34# m1_40_n138# 0.02fF
+C4 m1_n44_34# m1_n370_410# 0.02fF
+C5 m1_n44_34# m1_n784_n440# 0.01fF
+C6 m1_n248_34# m1_n368_n144# 0.01fF
+C7 out vdd 0.68fF
+*C8 m1_40_n138# m1_n390_206# 0.01fF
+*C9 m1_n368_n144# m1_n390_206# 0.02fF
+C10 m1_40_n138# m1_327_30# 0.02fF
+*C11 m1_n248_34# m1_n390_206# 0.58fF
+C12 m1_n44_34# vctrl 0.01fF
+C13 m1_32_418# m1_n166_424# 0.28fF
+C14 m1_n166_n140# m1_n166_424# 0.01fF
+C15 m1_554_n2# m1_n390_206# 0.00fF
+*C16 m1_327_30# m1_n390_206# 0.17fF
+C17 m1_n44_34# m1_32_418# 0.13fF
+C18 m1_n44_34# m1_n166_n140# 0.01fF
+C19 m1_554_n2# m1_327_30# 0.79fF
+C20 m1_n44_34# m1_40_n138# 0.14fF
+C21 m1_n44_34# m1_n368_n144# 0.02fF
+C22 m1_n248_34# m1_n166_424# 0.12fF
+*C23 m1_n166_424# m1_n390_206# 0.02fF
+C24 m1_n44_34# m1_n248_34# 0.46fF
+*C25 m1_n44_34# m1_n390_206# 0.63fF
+C26 m1_n370_410# vdd 0.83fF
+C27 m1_n784_n440# vdd 3.04fF
+C28 m1_n44_34# m1_327_30# 0.05fF
+C29 m1_n784_n440# m1_n370_410# 0.09fF
+C30 m1_32_418# vdd 1.06fF
+C31 m1_554_n2# out 0.52fF
+C32 vctrl m1_n784_n440# 0.00fF
+C33 m1_n370_410# m1_32_418# 0.13fF
+C34 m1_n784_n440# m1_32_418# 0.00fF
+C35 m1_n248_34# vdd 0.11fF
+*C36 vdd m1_n390_206# 0.38fF
+C37 vdd m1_327_30# 2.08fF
+C38 m1_554_n2# vdd 2.41fF
+C39 vctrl m1_n166_n140# 0.00fF
+C40 m1_n368_n144# m1_n370_410# 0.01fF
+C41 m1_n368_n144# m1_n784_n440# 0.07fF
+C42 m1_n248_34# m1_n784_n440# 0.01fF
+C43 vctrl m1_40_n138# 0.00fF
+*C44 m1_n370_410# m1_n390_206# 0.01fF
+*C45 m1_n784_n440# m1_n390_206# 0.02fF
+C46 vctrl m1_n368_n144# 0.00fF
+C47 vdd m1_n166_424# 0.93fF
+C48 m1_40_n138# m1_32_418# 0.01fF
+C49 vctrl m1_n248_34# 0.01fF
+C50 m1_40_n138# m1_n166_n140# 0.23fF
+*C51 vctrl m1_n390_206# 0.01fF
+C52 m1_n44_34# vdd 0.13fF
+C53 m1_n368_n144# m1_n166_n140# 0.23fF
+C54 m1_n248_34# m1_32_418# 0.02fF
+C55 m1_n248_34# m1_n166_n140# 0.13fF
+*C56 m1_n166_n140# m1_n390_206# 0.02fF
+C57 m1_n368_n144# m1_40_n138# 0.10fF
+C58 m1_327_30# vss 1.18fF
+C59 vdd vss 9.21fF
+C60 m1_40_n138# vss 0.99fF
+C61 m1_32_418# vss -0.48fF
+C62 m1_n44_34# vss 0.40fF
+C63 m1_n166_n140# vss 0.88fF
+C64 m1_n248_34# vss 0.37fF
+C65 m1_n166_424# vss -0.45fF
+C66 m1_n368_n144# vss 0.91fF
+*C67 m1_n390_206# vss 1.06fF
+C68 m1_n370_410# vss -0.40fF
+C69 m1_n784_n440# vss 0.42fF
+C70 vctrl vss 4.00fF
+C71 out vss 0.56fF
+C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET10_NET9_NET8_CAPS_COMMENTED_OUT.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET10_NET9_NET8_CAPS_COMMENTED_OUT.spice
new file mode 100755
index 0000000..8ab2be5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET10_NET9_NET8_CAPS_COMMENTED_OUT.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n211_n459# 0.64fF
+C1 a_15_n240# a_n73_n240# 0.52fF
+C2 a_n73_n240# a_n33_n337# 0.01fF
+C3 a_15_n240# w_n211_n459# 0.64fF
+C4 w_n211_n459# a_n33_n337# 0.48fF
+C5 a_15_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.31fF
+C7 a_n73_n240# VSUBS -0.31fF
+C8 a_n33_n337# VSUBS -0.14fF
+C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n129_n317# a_n78_n220# 0.00fF
+C1 a_n78_n220# a_114_n220# 0.18fF
+C2 a_18_n220# a_114_n220# 0.31fF
+C3 w_n311_n439# a_n78_n220# 0.49fF
+C4 a_18_n220# w_n311_n439# 0.44fF
+C5 a_18_n220# a_63_n317# 0.00fF
+C6 a_n129_n317# w_n311_n439# 0.23fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_18_n220# a_n33_251# 0.00fF
+C9 w_n311_n439# a_114_n220# 0.58fF
+C10 a_63_n317# a_n129_n317# 0.04fF
+C11 a_n78_n220# a_n173_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n129_n317# a_n33_251# 0.02fF
+C15 a_63_n317# w_n311_n439# 0.23fF
+C16 a_n129_n317# a_n173_n220# 0.00fF
+C17 a_18_n220# a_n78_n220# 0.31fF
+C18 w_n311_n439# a_n33_251# 0.28fF
+C19 a_114_n220# a_n173_n220# 0.07fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 w_n311_n439# a_n173_n220# 0.53fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.07fF
+C27 a_n129_n317# VSUBS -0.07fF
+C28 a_n33_251# VSUBS -0.07fF
+C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.22fF
+C1 a_n73_n120# a_n33_n208# 0.02fF
+C2 a_n33_n208# a_15_n120# 0.02fF
+C3 a_15_n120# w_n211_n330# 0.20fF
+C4 a_n73_n120# w_n211_n330# 0.20fF
+C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.21fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# w_n214_n339# 0.21fF
+C4 a_n76_n129# w_n214_n339# 0.21fF
+C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_18_n136# 0.16fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 a_n33_95# a_18_n136# 0.00fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 w_n112_n198# a_n76_n136# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_18_n276# 0.32fF
+C1 a_n33_235# a_n76_n276# 0.00fF
+C2 a_n33_235# a_18_n276# 0.00fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 w_n112_n338# a_n76_n276# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 w_n109_n122# a_15_n22# 0.11fF
+C1 a_n33_n119# a_n73_n22# 0.01fF
+C2 a_n33_n119# a_15_n22# 0.01fF
+C3 a_n33_n119# w_n109_n122# 0.19fF
+C4 a_15_n22# a_n73_n22# 0.13fF
+C5 w_n109_n122# a_n73_n22# 0.11fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.07fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 m1_32_418# m1_327_30# 0.02fF
+C1 m1_n370_410# m1_n166_424# 0.28fF
+C2 m1_n784_n440# m1_n166_424# 0.00fF
+*C3 m1_n248_34# m1_40_n138# 0.02fF
+*C4 m1_n44_34# m1_n370_410# 0.02fF
+*C5 m1_n44_34# m1_n784_n440# 0.01fF
+*C6 m1_n248_34# m1_n368_n144# 0.01fF
+C7 out vdd 0.68fF
+*C8 m1_40_n138# m1_n390_206# 0.01fF
+*C9 m1_n368_n144# m1_n390_206# 0.02fF
+C10 m1_40_n138# m1_327_30# 0.02fF
+*C11 m1_n248_34# m1_n390_206# 0.58fF
+*C12 m1_n44_34# vctrl 0.01fF
+C13 m1_32_418# m1_n166_424# 0.28fF
+C14 m1_n166_n140# m1_n166_424# 0.01fF
+C15 m1_554_n2# m1_n390_206# 0.00fF
+*C16 m1_327_30# m1_n390_206# 0.17fF
+*C17 m1_n44_34# m1_32_418# 0.13fF
+*C18 m1_n44_34# m1_n166_n140# 0.01fF
+C19 m1_554_n2# m1_327_30# 0.79fF
+*C20 m1_n44_34# m1_40_n138# 0.14fF
+*C21 m1_n44_34# m1_n368_n144# 0.02fF
+*C22 m1_n248_34# m1_n166_424# 0.12fF
+*C23 m1_n166_424# m1_n390_206# 0.02fF
+*C24 m1_n44_34# m1_n248_34# 0.46fF
+*C25 m1_n44_34# m1_n390_206# 0.63fF
+C26 m1_n370_410# vdd 0.83fF
+C27 m1_n784_n440# vdd 3.04fF
+*C28 m1_n44_34# m1_327_30# 0.05fF
+C29 m1_n784_n440# m1_n370_410# 0.09fF
+C30 m1_32_418# vdd 1.06fF
+C31 m1_554_n2# out 0.52fF
+C32 vctrl m1_n784_n440# 0.00fF
+C33 m1_n370_410# m1_32_418# 0.13fF
+C34 m1_n784_n440# m1_32_418# 0.00fF
+*C35 m1_n248_34# vdd 0.11fF
+*C36 vdd m1_n390_206# 0.38fF
+C37 vdd m1_327_30# 2.08fF
+C38 m1_554_n2# vdd 2.41fF
+C39 vctrl m1_n166_n140# 0.00fF
+C40 m1_n368_n144# m1_n370_410# 0.01fF
+C41 m1_n368_n144# m1_n784_n440# 0.07fF
+*C42 m1_n248_34# m1_n784_n440# 0.01fF
+C43 vctrl m1_40_n138# 0.00fF
+*C44 m1_n370_410# m1_n390_206# 0.01fF
+*C45 m1_n784_n440# m1_n390_206# 0.02fF
+C46 vctrl m1_n368_n144# 0.00fF
+C47 vdd m1_n166_424# 0.93fF
+C48 m1_40_n138# m1_32_418# 0.01fF
+*C49 vctrl m1_n248_34# 0.01fF
+C50 m1_40_n138# m1_n166_n140# 0.23fF
+*C51 vctrl m1_n390_206# 0.01fF
+*C52 m1_n44_34# vdd 0.13fF
+C53 m1_n368_n144# m1_n166_n140# 0.23fF
+*C54 m1_n248_34# m1_32_418# 0.02fF
+*C55 m1_n248_34# m1_n166_n140# 0.13fF
+*C56 m1_n166_n140# m1_n390_206# 0.02fF
+C57 m1_n368_n144# m1_40_n138# 0.10fF
+C58 m1_327_30# vss 1.18fF
+C59 vdd vss 9.21fF
+C60 m1_40_n138# vss 0.99fF
+C61 m1_32_418# vss -0.48fF
+*C62 m1_n44_34# vss 0.40fF
+C63 m1_n166_n140# vss 0.88fF
+*C64 m1_n248_34# vss 0.37fF
+C65 m1_n166_424# vss -0.45fF
+C66 m1_n368_n144# vss 0.91fF
+*C67 m1_n390_206# vss 1.06fF
+C68 m1_n370_410# vss -0.40fF
+C69 m1_n784_n440# vss 0.42fF
+C70 vctrl vss 4.00fF
+C71 out vss 0.56fF
+C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET8_CAPS_COMMENTED_OUT.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET8_CAPS_COMMENTED_OUT.spice
new file mode 100755
index 0000000..9178afe
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET8_CAPS_COMMENTED_OUT.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n211_n459# 0.64fF
+C1 a_15_n240# a_n73_n240# 0.52fF
+C2 a_n73_n240# a_n33_n337# 0.01fF
+C3 a_15_n240# w_n211_n459# 0.64fF
+C4 w_n211_n459# a_n33_n337# 0.48fF
+C5 a_15_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.31fF
+C7 a_n73_n240# VSUBS -0.31fF
+C8 a_n33_n337# VSUBS -0.14fF
+C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n129_n317# a_n78_n220# 0.00fF
+C1 a_n78_n220# a_114_n220# 0.18fF
+C2 a_18_n220# a_114_n220# 0.31fF
+C3 w_n311_n439# a_n78_n220# 0.49fF
+C4 a_18_n220# w_n311_n439# 0.44fF
+C5 a_18_n220# a_63_n317# 0.00fF
+C6 a_n129_n317# w_n311_n439# 0.23fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_18_n220# a_n33_251# 0.00fF
+C9 w_n311_n439# a_114_n220# 0.58fF
+C10 a_63_n317# a_n129_n317# 0.04fF
+C11 a_n78_n220# a_n173_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n129_n317# a_n33_251# 0.02fF
+C15 a_63_n317# w_n311_n439# 0.23fF
+C16 a_n129_n317# a_n173_n220# 0.00fF
+C17 a_18_n220# a_n78_n220# 0.31fF
+C18 w_n311_n439# a_n33_251# 0.28fF
+C19 a_114_n220# a_n173_n220# 0.07fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 w_n311_n439# a_n173_n220# 0.53fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.07fF
+C27 a_n129_n317# VSUBS -0.07fF
+C28 a_n33_251# VSUBS -0.07fF
+C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.22fF
+C1 a_n73_n120# a_n33_n208# 0.02fF
+C2 a_n33_n208# a_15_n120# 0.02fF
+C3 a_15_n120# w_n211_n330# 0.20fF
+C4 a_n73_n120# w_n211_n330# 0.20fF
+C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.21fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# w_n214_n339# 0.21fF
+C4 a_n76_n129# w_n214_n339# 0.21fF
+C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_18_n136# 0.16fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 a_n33_95# a_18_n136# 0.00fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 w_n112_n198# a_n76_n136# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_18_n276# 0.32fF
+C1 a_n33_235# a_n76_n276# 0.00fF
+C2 a_n33_235# a_18_n276# 0.00fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 w_n112_n338# a_n76_n276# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 w_n109_n122# a_15_n22# 0.11fF
+C1 a_n33_n119# a_n73_n22# 0.01fF
+C2 a_n33_n119# a_15_n22# 0.01fF
+C3 a_n33_n119# w_n109_n122# 0.19fF
+C4 a_15_n22# a_n73_n22# 0.13fF
+C5 w_n109_n122# a_n73_n22# 0.11fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.07fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 m1_32_418# m1_327_30# 0.02fF
+C1 m1_n370_410# m1_n166_424# 0.28fF
+C2 m1_n784_n440# m1_n166_424# 0.00fF
+*C3 m1_n248_34# m1_40_n138# 0.02fF
+C4 m1_n44_34# m1_n370_410# 0.02fF
+C5 m1_n44_34# m1_n784_n440# 0.01fF
+*C6 m1_n248_34# m1_n368_n144# 0.01fF
+C7 out vdd 0.68fF
+C8 m1_40_n138# m1_n390_206# 0.01fF
+C9 m1_n368_n144# m1_n390_206# 0.02fF
+C10 m1_40_n138# m1_327_30# 0.02fF
+*C11 m1_n248_34# m1_n390_206# 0.58fF
+C12 m1_n44_34# vctrl 0.01fF
+C13 m1_32_418# m1_n166_424# 0.28fF
+C14 m1_n166_n140# m1_n166_424# 0.01fF
+C15 m1_554_n2# m1_n390_206# 0.00fF
+C16 m1_327_30# m1_n390_206# 0.17fF
+C17 m1_n44_34# m1_32_418# 0.13fF
+C18 m1_n44_34# m1_n166_n140# 0.01fF
+C19 m1_554_n2# m1_327_30# 0.79fF
+C20 m1_n44_34# m1_40_n138# 0.14fF
+C21 m1_n44_34# m1_n368_n144# 0.02fF
+*C22 m1_n248_34# m1_n166_424# 0.12fF
+C23 m1_n166_424# m1_n390_206# 0.02fF
+*C24 m1_n44_34# m1_n248_34# 0.46fF
+C25 m1_n44_34# m1_n390_206# 0.63fF
+C26 m1_n370_410# vdd 0.83fF
+C27 m1_n784_n440# vdd 3.04fF
+C28 m1_n44_34# m1_327_30# 0.05fF
+C29 m1_n784_n440# m1_n370_410# 0.09fF
+C30 m1_32_418# vdd 1.06fF
+C31 m1_554_n2# out 0.52fF
+C32 vctrl m1_n784_n440# 0.00fF
+C33 m1_n370_410# m1_32_418# 0.13fF
+C34 m1_n784_n440# m1_32_418# 0.00fF
+*C35 m1_n248_34# vdd 0.11fF
+C36 vdd m1_n390_206# 0.38fF
+C37 vdd m1_327_30# 2.08fF
+C38 m1_554_n2# vdd 2.41fF
+C39 vctrl m1_n166_n140# 0.00fF
+C40 m1_n368_n144# m1_n370_410# 0.01fF
+C41 m1_n368_n144# m1_n784_n440# 0.07fF
+*C42 m1_n248_34# m1_n784_n440# 0.01fF
+C43 vctrl m1_40_n138# 0.00fF
+C44 m1_n370_410# m1_n390_206# 0.01fF
+C45 m1_n784_n440# m1_n390_206# 0.02fF
+C46 vctrl m1_n368_n144# 0.00fF
+C47 vdd m1_n166_424# 0.93fF
+C48 m1_40_n138# m1_32_418# 0.01fF
+*C49 vctrl m1_n248_34# 0.01fF
+C50 m1_40_n138# m1_n166_n140# 0.23fF
+C51 vctrl m1_n390_206# 0.01fF
+C52 m1_n44_34# vdd 0.13fF
+C53 m1_n368_n144# m1_n166_n140# 0.23fF
+*C54 m1_n248_34# m1_32_418# 0.02fF
+*C55 m1_n248_34# m1_n166_n140# 0.13fF
+C56 m1_n166_n140# m1_n390_206# 0.02fF
+C57 m1_n368_n144# m1_40_n138# 0.10fF
+C58 m1_327_30# vss 1.18fF
+C59 vdd vss 9.21fF
+C60 m1_40_n138# vss 0.99fF
+C61 m1_32_418# vss -0.48fF
+C62 m1_n44_34# vss 0.40fF
+C63 m1_n166_n140# vss 0.88fF
+*C64 m1_n248_34# vss 0.37fF
+C65 m1_n166_424# vss -0.45fF
+C66 m1_n368_n144# vss 0.91fF
+C67 m1_n390_206# vss 1.06fF
+C68 m1_n370_410# vss -0.40fF
+C69 m1_n784_n440# vss 0.42fF
+C70 vctrl vss 4.00fF
+C71 out vss 0.56fF
+C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET9_CAPS_COMMENTED_OUT.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET9_CAPS_COMMENTED_OUT.spice
new file mode 100755
index 0000000..3ccbf8e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_NET9_CAPS_COMMENTED_OUT.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n211_n459# 0.64fF
+C1 a_15_n240# a_n73_n240# 0.52fF
+C2 a_n73_n240# a_n33_n337# 0.01fF
+C3 a_15_n240# w_n211_n459# 0.64fF
+C4 w_n211_n459# a_n33_n337# 0.48fF
+C5 a_15_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.31fF
+C7 a_n73_n240# VSUBS -0.31fF
+C8 a_n33_n337# VSUBS -0.14fF
+C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n129_n317# a_n78_n220# 0.00fF
+C1 a_n78_n220# a_114_n220# 0.18fF
+C2 a_18_n220# a_114_n220# 0.31fF
+C3 w_n311_n439# a_n78_n220# 0.49fF
+C4 a_18_n220# w_n311_n439# 0.44fF
+C5 a_18_n220# a_63_n317# 0.00fF
+C6 a_n129_n317# w_n311_n439# 0.23fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_18_n220# a_n33_251# 0.00fF
+C9 w_n311_n439# a_114_n220# 0.58fF
+C10 a_63_n317# a_n129_n317# 0.04fF
+C11 a_n78_n220# a_n173_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n129_n317# a_n33_251# 0.02fF
+C15 a_63_n317# w_n311_n439# 0.23fF
+C16 a_n129_n317# a_n173_n220# 0.00fF
+C17 a_18_n220# a_n78_n220# 0.31fF
+C18 w_n311_n439# a_n33_251# 0.28fF
+C19 a_114_n220# a_n173_n220# 0.07fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 w_n311_n439# a_n173_n220# 0.53fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.07fF
+C27 a_n129_n317# VSUBS -0.07fF
+C28 a_n33_251# VSUBS -0.07fF
+C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.22fF
+C1 a_n73_n120# a_n33_n208# 0.02fF
+C2 a_n33_n208# a_15_n120# 0.02fF
+C3 a_15_n120# w_n211_n330# 0.20fF
+C4 a_n73_n120# w_n211_n330# 0.20fF
+C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.21fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# w_n214_n339# 0.21fF
+C4 a_n76_n129# w_n214_n339# 0.21fF
+C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_18_n136# 0.16fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 a_n33_95# a_18_n136# 0.00fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 w_n112_n198# a_n76_n136# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_18_n276# 0.32fF
+C1 a_n33_235# a_n76_n276# 0.00fF
+C2 a_n33_235# a_18_n276# 0.00fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 w_n112_n338# a_n76_n276# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 w_n109_n122# a_15_n22# 0.11fF
+C1 a_n33_n119# a_n73_n22# 0.01fF
+C2 a_n33_n119# a_15_n22# 0.01fF
+C3 a_n33_n119# w_n109_n122# 0.19fF
+C4 a_15_n22# a_n73_n22# 0.13fF
+C5 w_n109_n122# a_n73_n22# 0.11fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.07fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 m1_32_418# m1_327_30# 0.02fF
+C1 m1_n370_410# m1_n166_424# 0.28fF
+C2 m1_n784_n440# m1_n166_424# 0.00fF
+C3 m1_n248_34# m1_40_n138# 0.02fF
+*C4 m1_n44_34# m1_n370_410# 0.02fF
+*C5 m1_n44_34# m1_n784_n440# 0.01fF
+C6 m1_n248_34# m1_n368_n144# 0.01fF
+C7 out vdd 0.68fF
+C8 m1_40_n138# m1_n390_206# 0.01fF
+C9 m1_n368_n144# m1_n390_206# 0.02fF
+C10 m1_40_n138# m1_327_30# 0.02fF
+C11 m1_n248_34# m1_n390_206# 0.58fF
+*C12 m1_n44_34# vctrl 0.01fF
+C13 m1_32_418# m1_n166_424# 0.28fF
+C14 m1_n166_n140# m1_n166_424# 0.01fF
+C15 m1_554_n2# m1_n390_206# 0.00fF
+C16 m1_327_30# m1_n390_206# 0.17fF
+*C17 m1_n44_34# m1_32_418# 0.13fF
+*C18 m1_n44_34# m1_n166_n140# 0.01fF
+C19 m1_554_n2# m1_327_30# 0.79fF
+*C20 m1_n44_34# m1_40_n138# 0.14fF
+*C21 m1_n44_34# m1_n368_n144# 0.02fF
+C22 m1_n248_34# m1_n166_424# 0.12fF
+C23 m1_n166_424# m1_n390_206# 0.02fF
+*C24 m1_n44_34# m1_n248_34# 0.46fF
+*C25 m1_n44_34# m1_n390_206# 0.63fF
+C26 m1_n370_410# vdd 0.83fF
+C27 m1_n784_n440# vdd 3.04fF
+*C28 m1_n44_34# m1_327_30# 0.05fF
+C29 m1_n784_n440# m1_n370_410# 0.09fF
+C30 m1_32_418# vdd 1.06fF
+C31 m1_554_n2# out 0.52fF
+C32 vctrl m1_n784_n440# 0.00fF
+C33 m1_n370_410# m1_32_418# 0.13fF
+C34 m1_n784_n440# m1_32_418# 0.00fF
+C35 m1_n248_34# vdd 0.11fF
+C36 vdd m1_n390_206# 0.38fF
+C37 vdd m1_327_30# 2.08fF
+C38 m1_554_n2# vdd 2.41fF
+C39 vctrl m1_n166_n140# 0.00fF
+C40 m1_n368_n144# m1_n370_410# 0.01fF
+C41 m1_n368_n144# m1_n784_n440# 0.07fF
+C42 m1_n248_34# m1_n784_n440# 0.01fF
+C43 vctrl m1_40_n138# 0.00fF
+C44 m1_n370_410# m1_n390_206# 0.01fF
+C45 m1_n784_n440# m1_n390_206# 0.02fF
+C46 vctrl m1_n368_n144# 0.00fF
+C47 vdd m1_n166_424# 0.93fF
+C48 m1_40_n138# m1_32_418# 0.01fF
+C49 vctrl m1_n248_34# 0.01fF
+C50 m1_40_n138# m1_n166_n140# 0.23fF
+C51 vctrl m1_n390_206# 0.01fF
+*C52 m1_n44_34# vdd 0.13fF
+C53 m1_n368_n144# m1_n166_n140# 0.23fF
+C54 m1_n248_34# m1_32_418# 0.02fF
+C55 m1_n248_34# m1_n166_n140# 0.13fF
+C56 m1_n166_n140# m1_n390_206# 0.02fF
+C57 m1_n368_n144# m1_40_n138# 0.10fF
+C58 m1_327_30# vss 1.18fF
+C59 vdd vss 9.21fF
+C60 m1_40_n138# vss 0.99fF
+C61 m1_32_418# vss -0.48fF
+*C62 m1_n44_34# vss 0.40fF
+C63 m1_n166_n140# vss 0.88fF
+C64 m1_n248_34# vss 0.37fF
+C65 m1_n166_424# vss -0.45fF
+C66 m1_n368_n144# vss 0.91fF
+C67 m1_n390_206# vss 1.06fF
+C68 m1_n370_410# vss -0.40fF
+C69 m1_n784_n440# vss 0.42fF
+C70 vctrl vss 4.00fF
+C71 out vss 0.56fF
+C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ONLY_DELAY_CELL_TRANS_SUBCKT_CAPS_INSERTED.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ONLY_DELAY_CELL_TRANS_SUBCKT_CAPS_INSERTED.spice
new file mode 100755
index 0000000..e47c372
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_ONLY_DELAY_CELL_TRANS_SUBCKT_CAPS_INSERTED.spice
@@ -0,0 +1,266 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+*C0 a_n73_n240# w_n211_n459# 0.64fF
+*C1 a_15_n240# a_n73_n240# 0.52fF
+*C2 a_n73_n240# a_n33_n337# 0.01fF
+*C3 a_15_n240# w_n211_n459# 0.64fF
+*C4 w_n211_n459# a_n33_n337# 0.48fF
+*C5 a_15_n240# a_n33_n337# 0.01fF
+*C6 a_15_n240# VSUBS -0.31fF
+*C7 a_n73_n240# VSUBS -0.31fF
+*C8 a_n33_n337# VSUBS -0.14fF
+*C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+*C0 a_n129_n317# a_n78_n220# 0.00fF
+*C1 a_n78_n220# a_114_n220# 0.18fF
+*C2 a_18_n220# a_114_n220# 0.31fF
+*C3 w_n311_n439# a_n78_n220# 0.49fF
+*C4 a_18_n220# w_n311_n439# 0.44fF
+*C5 a_18_n220# a_63_n317# 0.00fF
+*C6 a_n129_n317# w_n311_n439# 0.23fF
+*C7 a_n78_n220# a_n33_251# 0.00fF
+*C8 a_18_n220# a_n33_251# 0.00fF
+*C9 w_n311_n439# a_114_n220# 0.58fF
+*C10 a_63_n317# a_n129_n317# 0.04fF
+*C11 a_n78_n220# a_n173_n220# 0.31fF
+*C12 a_18_n220# a_n173_n220# 0.14fF
+*C13 a_63_n317# a_114_n220# 0.00fF
+*C14 a_n129_n317# a_n33_251# 0.02fF
+*C15 a_63_n317# w_n311_n439# 0.23fF
+*C16 a_n129_n317# a_n173_n220# 0.00fF
+*C17 a_18_n220# a_n78_n220# 0.31fF
+*C18 w_n311_n439# a_n33_251# 0.28fF
+*C19 a_114_n220# a_n173_n220# 0.07fF
+*C20 a_63_n317# a_n33_251# 0.02fF
+*C21 w_n311_n439# a_n173_n220# 0.53fF
+*C22 a_114_n220# VSUBS -0.33fF
+*C23 a_18_n220# VSUBS -0.27fF
+*C24 a_n78_n220# VSUBS -0.33fF
+*C25 a_n173_n220# VSUBS -0.27fF
+*C26 a_63_n317# VSUBS -0.07fF
+*C27 a_n129_n317# VSUBS -0.07fF
+*C28 a_n33_251# VSUBS -0.07fF
+*C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+*C0 a_n73_n120# a_15_n120# 0.22fF
+*C1 a_n73_n120# a_n33_n208# 0.02fF
+*C2 a_n33_n208# a_15_n120# 0.02fF
+*C3 a_15_n120# w_n211_n330# 0.20fF
+*C4 a_n73_n120# w_n211_n330# 0.20fF
+*C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+*C0 a_n76_n129# a_18_n129# 0.21fF
+*C1 a_n76_n129# a_n33_n217# 0.01fF
+*C2 a_n33_n217# a_18_n129# 0.01fF
+*C3 a_18_n129# w_n214_n339# 0.21fF
+*C4 a_n76_n129# w_n214_n339# 0.21fF
+*C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+*C0 w_n112_n198# a_18_n136# 0.16fF
+*C1 a_n33_95# a_n76_n136# 0.00fF
+*C2 a_n33_95# a_18_n136# 0.00fF
+*C3 a_n33_95# w_n112_n198# 0.19fF
+*C4 a_18_n136# a_n76_n136# 0.20fF
+*C5 w_n112_n198# a_n76_n136# 0.16fF
+*C6 a_18_n136# VSUBS -0.15fF
+*C7 a_n76_n136# VSUBS -0.15fF
+*C8 a_n33_95# VSUBS -0.07fF
+*C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+*C0 a_n76_n69# a_18_n69# 0.17fF
+*C1 a_n76_n69# a_n33_n157# 0.00fF
+*C2 a_n33_n157# a_18_n69# 0.01fF
+*C3 a_18_n69# VSUBS 0.00fF
+*C4 a_n76_n69# VSUBS 0.00fF
+*C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+*C0 a_n76_n209# a_18_n209# 0.35fF
+*C1 a_n76_n209# a_n33_n297# 0.00fF
+*C2 a_n33_n297# a_18_n209# 0.00fF
+*C3 a_18_n209# VSUBS 0.00fF
+*C4 a_n76_n209# VSUBS 0.00fF
+*C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+*C0 w_n112_n338# a_18_n276# 0.32fF
+*C1 a_n33_235# a_n76_n276# 0.00fF
+*C2 a_n33_235# a_18_n276# 0.00fF
+*C3 a_n33_235# w_n112_n338# 0.19fF
+*C4 a_18_n276# a_n76_n276# 0.46fF
+*C5 w_n112_n338# a_n76_n276# 0.32fF
+*C6 a_18_n276# VSUBS -0.31fF
+*C7 a_n76_n276# VSUBS -0.31fF
+*C8 a_n33_235# VSUBS -0.07fF
+*C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_15_n14# 0.10fF
+C1 a_n33_n111# a_n73_n14# 0.01fF
+C2 a_n33_n111# a_15_n14# 0.01fF
+C3 a_n33_n111# w_n109_n114# 0.19fF
+C4 a_15_n14# a_n73_n14# 0.12fF
+C5 w_n109_n114# a_n73_n14# 0.10fF
+C6 a_15_n14# VSUBS -0.10fF
+C7 a_n73_n14# VSUBS -0.10fF
+C8 a_n33_n111# VSUBS -0.07fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.11fF
+C1 a_n73_n68# a_n33_33# 0.01fF
+C2 a_n33_33# a_15_n68# 0.01fF
+C3 a_15_n68# VSUBS 0.01fF
+C4 a_n73_n68# VSUBS 0.01fF
+C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+*C0 w_n109_n122# a_15_n22# 0.11fF
+*C1 a_n33_n119# a_n73_n22# 0.01fF
+*C2 a_n33_n119# a_15_n22# 0.01fF
+*C3 a_n33_n119# w_n109_n122# 0.19fF
+*C4 a_15_n22# a_n73_n22# 0.13fF
+*C5 w_n109_n122# a_n73_n22# 0.11fF
+*C6 a_15_n22# VSUBS -0.10fF
+*C7 a_n73_n22# VSUBS -0.11fF
+*C8 a_n33_n119# VSUBS -0.07fF
+*C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM2 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM6 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM7 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM8 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM10 vdd vdd m1_n784_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd m1_n784_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+*C0 m1_32_418# m1_327_30# 0.02fF
+*C1 m1_n370_410# m1_n166_424# 0.28fF
+*C2 m1_n784_n440# m1_n166_424# 0.00fF
+*C3 m1_n248_34# m1_40_n138# 0.02fF
+*C4 m1_n44_34# m1_n370_410# 0.02fF
+*C5 m1_n44_34# m1_n784_n440# 0.01fF
+*C6 m1_n248_34# m1_n368_n144# 0.01fF
+*C7 out vdd 0.68fF
+*C8 m1_40_n138# m1_n390_206# 0.01fF
+*C9 m1_n368_n144# m1_n390_206# 0.02fF
+*C10 m1_40_n138# m1_327_30# 0.02fF
+*C11 m1_n248_34# m1_n390_206# 0.58fF
+*C12 m1_n44_34# vctrl 0.01fF
+*C13 m1_32_418# m1_n166_424# 0.28fF
+*C14 m1_n166_n140# m1_n166_424# 0.01fF
+*C15 m1_554_n2# m1_n390_206# 0.00fF
+*C16 m1_327_30# m1_n390_206# 0.17fF
+*C17 m1_n44_34# m1_32_418# 0.13fF
+*C18 m1_n44_34# m1_n166_n140# 0.01fF
+*C19 m1_554_n2# m1_327_30# 0.79fF
+*C20 m1_n44_34# m1_40_n138# 0.14fF
+*C21 m1_n44_34# m1_n368_n144# 0.02fF
+*C22 m1_n248_34# m1_n166_424# 0.12fF
+*C23 m1_n166_424# m1_n390_206# 0.02fF
+*C24 m1_n44_34# m1_n248_34# 0.46fF
+*C25 m1_n44_34# m1_n390_206# 0.63fF
+*C26 m1_n370_410# vdd 0.83fF
+*C27 m1_n784_n440# vdd 3.04fF
+*C28 m1_n44_34# m1_327_30# 0.05fF
+*C29 m1_n784_n440# m1_n370_410# 0.09fF
+*C30 m1_32_418# vdd 1.06fF
+*C31 m1_554_n2# out 0.52fF
+*C32 vctrl m1_n784_n440# 0.00fF
+*C33 m1_n370_410# m1_32_418# 0.13fF
+*C34 m1_n784_n440# m1_32_418# 0.00fF
+*C35 m1_n248_34# vdd 0.11fF
+*C36 vdd m1_n390_206# 0.38fF
+*C37 vdd m1_327_30# 2.08fF
+*C38 m1_554_n2# vdd 2.41fF
+*C39 vctrl m1_n166_n140# 0.00fF
+*C40 m1_n368_n144# m1_n370_410# 0.01fF
+*C41 m1_n368_n144# m1_n784_n440# 0.07fF
+*C42 m1_n248_34# m1_n784_n440# 0.01fF
+*C43 vctrl m1_40_n138# 0.00fF
+*C44 m1_n370_410# m1_n390_206# 0.01fF
+*C45 m1_n784_n440# m1_n390_206# 0.02fF
+*C46 vctrl m1_n368_n144# 0.00fF
+*C47 vdd m1_n166_424# 0.93fF
+*C48 m1_40_n138# m1_32_418# 0.01fF
+*C49 vctrl m1_n248_34# 0.01fF
+*C50 m1_40_n138# m1_n166_n140# 0.23fF
+*C51 vctrl m1_n390_206# 0.01fF
+*C52 m1_n44_34# vdd 0.13fF
+*C53 m1_n368_n144# m1_n166_n140# 0.23fF
+*C54 m1_n248_34# m1_32_418# 0.02fF
+*C55 m1_n248_34# m1_n166_n140# 0.13fF
+*C56 m1_n166_n140# m1_n390_206# 0.02fF
+*C57 m1_n368_n144# m1_40_n138# 0.10fF
+*C58 m1_327_30# vss 1.18fF
+*C59 vdd vss 9.21fF
+*C60 m1_40_n138# vss 0.99fF
+*C61 m1_32_418# vss -0.48fF
+*C62 m1_n44_34# vss 0.40fF
+*C63 m1_n166_n140# vss 0.88fF
+*C64 m1_n248_34# vss 0.37fF
+*C65 m1_n166_424# vss -0.45fF
+*C66 m1_n368_n144# vss 0.91fF
+*C67 m1_n390_206# vss 1.06fF
+*C68 m1_n370_410# vss -0.40fF
+*C69 m1_n784_n440# vss 0.42fF
+*C70 vctrl vss 4.00fF
+*C71 out vss 0.56fF
+*C72 m1_554_n2# vss 1.69fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_BUT_NOCAPS.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_BUT_NOCAPS.spice
new file mode 100755
index 0000000..ca9220d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_BUT_NOCAPS.spice
@@ -0,0 +1,260 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+*C0 a_15_n240# a_n33_n337# 0.01fF
+*C1 a_n33_n337# a_n73_n240# 0.01fF
+*C2 a_15_n240# a_n73_n240# 0.52fF
+*C3 w_n211_n459# a_n33_n337# 0.48fF
+*C4 w_n211_n459# a_15_n240# 0.64fF
+*C5 w_n211_n459# a_n73_n240# 0.64fF
+*C6 a_15_n240# VSUBS -0.31fF
+*C7 a_n73_n240# VSUBS -0.31fF
+*C8 a_n33_n337# VSUBS -0.14fF
+*C9 w_n211_n459# VSUBS 1.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+*C0 a_63_n317# a_n33_251# 0.02fF
+*C1 a_n78_n220# a_18_n220# 0.31fF
+*C2 a_n33_251# a_n129_n317# 0.02fF
+*C3 w_n311_n439# a_n173_n220# 0.53fF
+*C4 a_114_n220# a_63_n317# 0.00fF
+*C5 a_18_n220# a_n33_251# 0.00fF
+*C6 a_63_n317# a_n129_n317# 0.04fF
+*C7 a_n173_n220# a_n78_n220# 0.31fF
+*C8 w_n311_n439# a_n78_n220# 0.49fF
+*C9 a_63_n317# a_18_n220# 0.00fF
+*C10 a_114_n220# a_18_n220# 0.31fF
+*C11 w_n311_n439# a_n33_251# 0.28fF
+*C12 a_n78_n220# a_n33_251# 0.00fF
+*C13 w_n311_n439# a_63_n317# 0.23fF
+*C14 a_114_n220# a_n173_n220# 0.07fF
+*C15 w_n311_n439# a_114_n220# 0.58fF
+*C16 a_n173_n220# a_n129_n317# 0.00fF
+*C17 w_n311_n439# a_n129_n317# 0.23fF
+*C18 a_114_n220# a_n78_n220# 0.18fF
+*C19 a_n78_n220# a_n129_n317# 0.00fF
+*C20 a_n173_n220# a_18_n220# 0.14fF
+*C21 w_n311_n439# a_18_n220# 0.44fF
+*C22 a_114_n220# VSUBS -0.33fF
+*C23 a_18_n220# VSUBS -0.27fF
+*C24 a_n78_n220# VSUBS -0.33fF
+*C25 a_n173_n220# VSUBS -0.27fF
+*C26 a_63_n317# VSUBS -0.07fF
+*C27 a_n129_n317# VSUBS -0.07fF
+*C28 a_n33_251# VSUBS -0.07fF
+*C29 w_n311_n439# VSUBS 1.60fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+*C0 a_n73_n120# a_n33_n208# 0.02fF
+*C1 a_15_n120# a_n73_n120# 0.22fF
+*C2 a_15_n120# a_n33_n208# 0.02fF
+*C3 a_15_n120# w_n211_n330# 0.20fF
+*C4 a_n73_n120# w_n211_n330# 0.20fF
+*C5 a_n33_n208# w_n211_n330# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+*C0 a_n76_n129# a_n33_n217# 0.01fF
+*C1 a_18_n129# a_n76_n129# 0.21fF
+*C2 a_18_n129# a_n33_n217# 0.01fF
+*C3 a_18_n129# w_n214_n339# 0.21fF
+*C4 a_n76_n129# w_n214_n339# 0.21fF
+*C5 a_n33_n217# w_n214_n339# 0.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+*C0 a_n33_235# w_n112_n338# 0.19fF
+*C1 a_n76_n276# a_18_n276# 0.46fF
+*C2 a_n76_n276# a_n33_235# 0.00fF
+*C3 a_n33_235# a_18_n276# 0.00fF
+*C4 a_n76_n276# w_n112_n338# 0.32fF
+*C5 a_18_n276# w_n112_n338# 0.32fF
+*C6 a_18_n276# VSUBS -0.31fF
+*C7 a_n76_n276# VSUBS -0.31fF
+*C8 a_n33_235# VSUBS -0.07fF
+*C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+*C0 a_n33_95# w_n112_n198# 0.19fF
+*C1 a_n76_n136# a_18_n136# 0.20fF
+*C2 a_n76_n136# a_n33_95# 0.00fF
+*C3 a_n33_95# a_18_n136# 0.00fF
+*C4 a_n76_n136# w_n112_n198# 0.16fF
+*C5 a_18_n136# w_n112_n198# 0.16fF
+*C6 a_18_n136# VSUBS -0.15fF
+*C7 a_n76_n136# VSUBS -0.15fF
+*C8 a_n33_95# VSUBS -0.07fF
+*C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+*C0 a_n33_n111# w_n109_n114# 0.19fF
+*C1 a_n73_n14# a_15_n14# 0.12fF
+*C2 a_n73_n14# a_n33_n111# 0.01fF
+*C3 a_n33_n111# a_15_n14# 0.01fF
+*C4 a_n73_n14# w_n109_n114# 0.10fF
+*C5 a_15_n14# w_n109_n114# 0.10fF
+*C6 a_15_n14# VSUBS -0.10fF
+*C7 a_n73_n14# VSUBS -0.10fF
+*C8 a_n33_n111# VSUBS -0.07fF
+*C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+*C0 a_n76_n209# a_n33_n297# 0.00fF
+*C1 a_18_n209# a_n76_n209# 0.35fF
+*C2 a_18_n209# a_n33_n297# 0.00fF
+*C3 a_18_n209# VSUBS 0.00fF
+*C4 a_n76_n209# VSUBS 0.00fF
+*C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+*C0 a_n73_n68# a_n33_33# 0.01fF
+*C1 a_15_n68# a_n73_n68# 0.11fF
+*C2 a_15_n68# a_n33_33# 0.01fF
+*C3 a_15_n68# VSUBS 0.01fF
+*C4 a_n73_n68# VSUBS 0.01fF
+*C5 a_n33_33# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+*C0 a_n76_n69# a_n33_n157# 0.00fF
+*C1 a_18_n69# a_n76_n69# 0.17fF
+*C2 a_18_n69# a_n33_n157# 0.01fF
+*C3 a_18_n69# VSUBS 0.00fF
+*C4 a_n76_n69# VSUBS 0.00fF
+*C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+*C0 a_n33_n119# w_n109_n122# 0.19fF
+*C1 a_n73_n22# a_15_n22# 0.13fF
+*C2 a_n73_n22# a_n33_n119# 0.01fF
+*C3 a_n33_n119# a_15_n22# 0.01fF
+*C4 a_n73_n22# w_n109_n122# 0.11fF
+*C5 a_15_n22# w_n109_n122# 0.11fF
+*C6 a_15_n22# VSUBS -0.10fF
+*C7 a_n73_n22# VSUBS -0.11fF
+*C8 a_n33_n119# VSUBS -0.07fF
+*C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM12 m1_554_n2# vdd vdd m1_327_30# vss sky130_fd_pr__pfet_01v8_V5LP55
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out vss sky130_fd_pr__pfet_01v8_9P8X3X
+XXM13 m1_554_n2# vss vss m1_327_30# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_0 vdd vdd m1_n686_n440# m1_32_418# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_1 vdd vdd m1_n686_n440# m1_n166_424# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_XZZ25Z_0 vdd m1_n686_n440# vdd m1_n686_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_2 vdd vdd m1_n686_n440# m1_n370_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_BKC9WK_0 m1_32_418# m1_n44_34# vdd m1_n390_206# vss sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_1 m1_n166_424# m1_n248_34# vdd m1_n44_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_2 m1_n370_410# m1_n390_206# vdd m1_n248_34# vss sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__nfet_01v8_26QSQN_0 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_1 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_2 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_LS29AB_0 m1_n390_206# vss m1_327_30# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_1 m1_n390_206# m1_n368_n144# m1_n248_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_LS29AB_2 m1_n248_34# m1_n166_n140# m1_n44_34# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xsky130_fd_pr__nfet_01v8_B87NCT_0 m1_n686_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+Xsky130_fd_pr__nfet_01v8_LS29AB_3 m1_n44_34# m1_40_n138# m1_n390_206# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM21 m1_327_30# m1_n390_206# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+*C0 m1_32_418# m1_40_n138# 0.01fF
+*C1 m1_n166_424# m1_n248_34# 0.12fF
+*C2 out m1_554_n2# 0.52fF
+*C3 m1_40_n138# m1_327_30# 0.03fF
+*C4 m1_n248_34# m1_n44_34# 0.46fF
+*C5 m1_n166_424# m1_n166_n140# 0.01fF
+*C6 m1_n368_n144# vctrl 0.00fF
+*C7 vctrl m1_n390_206# 0.01fF
+*C8 m1_32_418# vdd 0.74fF
+*C9 m1_32_418# m1_327_30# 0.03fF
+*C10 m1_n44_34# m1_n166_n140# 0.01fF
+*C11 m1_n248_34# m1_n166_n140# 0.13fF
+*C12 vdd m1_327_30# 2.01fF
+*C13 m1_n368_n144# m1_40_n138# 0.10fF
+*C14 m1_40_n138# m1_n390_206# 0.01fF
+*C15 m1_32_418# m1_n370_410# 0.12fF
+*C16 vctrl m1_n686_n440# 0.02fF
+*C17 m1_n390_206# vdd 0.33fF
+*C18 vdd m1_n370_410# 0.24fF
+*C19 m1_n390_206# m1_327_30# 0.18fF
+*C20 m1_n44_34# vctrl 0.01fF
+*C21 m1_n248_34# vctrl 0.01fF
+*C22 m1_n686_n440# m1_32_418# 0.00fF
+*C23 m1_n368_n144# m1_n390_206# 0.02fF
+*C24 m1_n368_n144# m1_n370_410# 0.01fF
+*C25 m1_n390_206# m1_n370_410# 0.01fF
+*C26 m1_n686_n440# vdd 1.62fF
+*C27 vdd m1_554_n2# 2.32fF
+*C28 m1_n44_34# m1_40_n138# 0.14fF
+*C29 m1_n248_34# m1_40_n138# 0.02fF
+*C30 m1_327_30# m1_554_n2# 0.79fF
+*C31 vctrl m1_n166_n140# 0.00fF
+*C32 m1_n166_424# m1_32_418# 0.27fF
+*C33 m1_n166_424# vdd 0.63fF
+*C34 m1_n44_34# m1_32_418# 0.13fF
+*C35 m1_n166_n140# m1_40_n138# 0.23fF
+*C36 m1_n248_34# m1_32_418# 0.02fF
+*C37 m1_n44_34# vdd 0.10fF
+*C38 m1_n248_34# vdd 0.09fF
+*C39 m1_n368_n144# m1_n686_n440# 0.10fF
+*C40 m1_n686_n440# m1_n390_206# 0.04fF
+*C41 m1_n686_n440# m1_n370_410# 0.12fF
+*C42 m1_n390_206# m1_554_n2# 0.00fF
+*C43 m1_n44_34# m1_327_30# 0.05fF
+*C44 m1_n166_424# m1_n390_206# 0.02fF
+*C45 out vdd 0.68fF
+*C46 m1_n166_424# m1_n370_410# 0.27fF
+*C47 m1_n44_34# m1_n368_n144# 0.02fF
+*C48 m1_n44_34# m1_n390_206# 0.63fF
+*C49 m1_n248_34# m1_n368_n144# 0.01fF
+*C50 m1_n248_34# m1_n390_206# 0.58fF
+*C51 m1_n44_34# m1_n370_410# 0.02fF
+*C52 vctrl m1_40_n138# 0.00fF
+*C53 m1_n368_n144# m1_n166_n140# 0.23fF
+*C54 m1_n166_n140# m1_n390_206# 0.02fF
+*C55 m1_n166_424# m1_n686_n440# 0.00fF
+*C56 m1_n44_34# m1_n686_n440# 0.02fF
+*C57 m1_n248_34# m1_n686_n440# 0.06fF
+*C58 m1_40_n138# vss 0.71fF
+*C59 m1_n686_n440# vss 0.05fF
+*C60 m1_n44_34# vss 0.49fF
+*C61 m1_n166_n140# vss 0.61fF
+*C62 m1_n248_34# vss 0.29fF
+*C63 m1_n368_n144# vss 0.32fF
+*C64 m1_n390_206# vss 0.80fF
+*C65 m1_327_30# vss 1.08fF
+*C66 vctrl vss 3.16fF
+*C67 m1_n370_410# vss -0.46fF
+*C68 m1_n166_424# vss -0.43fF
+*C69 vdd vss 10.51fF
+*C70 m1_32_418# vss -0.41fF
+*C71 out vss 0.72fF
+*C72 m1_554_n2# vss 1.61fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..ac5f289
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_tb.log
@@ -0,0 +1,227 @@
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Warning - approaching max data size: current size = 602.207 MB, limit = 624.668 MB
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12452:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12452:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 5.18461e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.45543e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.808841e+00 at= 1.867500e-08
+vlow_outside_while = 1.789902e+00 at= 1.814500e-08
+peak_to_peak_outside_while= 1.89387e-02
+supply_current_rms = 5.75475e-05 from= 0.00000e+00 to= 1.00000e-07
+
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.376852e-10 targ= 1.841501e-08 trig= 1.807733e-08
+fvco_outside_while = 2.96134e+09
+supply_current_rms_outside_while= 2.18337e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.97375e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.908372e+00 at= 1.458500e-08
+vlow_outside_while = -3.783208e-02 at= 1.670500e-08
+peak_to_peak_outside_while= 1.94620e+00
+supply_current_rms = 2.17432e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.440884e-10 targ= 1.392323e-08 trig= 1.367914e-08
+fvco_outside_while = 4.09688e+09
+supply_current_rms_outside_while= 2.93730e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.86115e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.942664e+00 at= 1.135500e-08
+vlow_outside_while = -8.077369e-02 at= 1.829500e-08
+peak_to_peak_outside_while= 2.02344e+00
+supply_current_rms = 2.91626e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Warning - approaching max data size: current size = 610.211 MB, limit = 624.668 MB
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.440884e-10 targ= 1.392323e-08 trig= 1.367914e-08
+Original line no.: 0, new internal line no.: 12452:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.09687621632871437e+09 " u=" 4.09687621632871437e+09" id=0
+fvco_outside_while = 4.09688e+09
+supply_current_rms_outside_while= 2.93730e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.86115e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.942664e+00 at= 1.135500e-08
+vlow_outside_while = -8.077369e-02 at= 1.829500e-08
+Original line no.: 0, new internal line no.: 12458:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.02343724276732928e+00 " u=" 2.02343724276732928e+00" id=0
+peak_to_peak_outside_while= 2.02344e+00
+supply_current_rms = 2.91626e-04 from= 0.00000e+00 to= 1.00000e-07
+
+
+Total analysis time (seconds) = 5.737
+
+Total elapsed time (seconds) = 108.717
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 129.902 MB.
+Total ngspice program size = 610.211 MB.
+Resident set size = 590.312 MB.
+Shared ngspice pages = 8.023 MB.
+Text (code) pages = 5.070 MB.
+Stack = 0 bytes.
+Library pages = 590.465 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_tidiedup_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_tidiedup_tb.log
new file mode 100755
index 0000000..40c23b0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_POST-LAYOUT_tidiedup_tb.log
@@ -0,0 +1,573 @@
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 9.430612e-10 targ= 4.736951e-08 trig= 4.642644e-08
+fvco_outside_while = 1.06038e+09
+supply_current_rms_outside_while= 1.35374e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.05698e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.863026e+00 at= 1.507500e-08
+vlow_outside_while = -5.003285e-02 at= 1.526500e-08
+peak_to_peak_outside_while= 1.91306e+00
+supply_current_rms = 1.34132e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 4.930775e-10 targ= 2.577781e-08 trig= 2.528473e-08
+fvco_outside_while = 2.02808e+09
+supply_current_rms_outside_while= 2.06070e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.86060e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927691e+00 at= 1.767500e-08
+vlow_outside_while = -8.540428e-02 at= 1.342500e-08
+peak_to_peak_outside_while= 2.01310e+00
+supply_current_rms = 2.03399e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.200203e-10 targ= 1.748846e-08 trig= 1.716844e-08
+fvco_outside_while = 3.12480e+09
+supply_current_rms_outside_while= 6.20379e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.40373e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.943754e+00 at= 1.028500e-08
+vlow_outside_while = -8.609276e-02 at= 1.010500e-08
+peak_to_peak_outside_while= 2.02985e+00
+supply_current_rms = 2.82235e-03 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.716640e-10 targ= 1.517972e-08 trig= 1.490806e-08
+fvco_outside_while = 3.68102e+09
+supply_current_rms_outside_while= 3.14805e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.09213e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945295e+00 at= 1.829500e-08
+vlow_outside_while = -8.607225e-02 at= 1.760500e-08
+peak_to_peak_outside_while= 2.03137e+00
+supply_current_rms = 3.12053e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.547877e-10 targ= 1.436912e-08 trig= 1.411434e-08
+fvco_outside_while = 3.92484e+09
+supply_current_rms_outside_while= 3.51004e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.46249e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945235e+00 at= 1.193500e-08
+vlow_outside_while = -8.433378e-02 at= 1.052500e-08
+peak_to_peak_outside_while= 2.02957e+00
+supply_current_rms = 3.47991e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.474186e-10 targ= 1.399738e-08 trig= 1.374996e-08
+fvco_outside_while = 4.04173e+09
+supply_current_rms_outside_while= 3.77912e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.72162e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945139e+00 at= 1.954500e-08
+vlow_outside_while = -8.351504e-02 at= 1.669500e-08
+peak_to_peak_outside_while= 2.02865e+00
+supply_current_rms = 3.74192e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.437355e-10 targ= 1.381452e-08 trig= 1.357079e-08
+fvco_outside_while = 4.10281e+09
+supply_current_rms_outside_while= 3.95817e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.86576e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.944965e+00 at= 1.124500e-08
+vlow_outside_while = -8.295009e-02 at= 1.963500e-08
+peak_to_peak_outside_while= 2.02792e+00
+supply_current_rms = 3.92228e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.409984e-10 targ= 1.370199e-08 trig= 1.346099e-08
+fvco_outside_while = 4.14941e+09
+supply_current_rms_outside_while= 4.27966e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.95678e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.944846e+00 at= 1.959500e-08
+vlow_outside_while = -8.265960e-02 at= 1.223500e-08
+peak_to_peak_outside_while= 2.02751e+00
+supply_current_rms = 4.23982e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.394882e-10 targ= 1.362809e-08 trig= 1.338860e-08
+fvco_outside_while = 4.17557e+09
+supply_current_rms_outside_while= 4.37503e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.24568e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945779e+00 at= 1.876500e-08
+vlow_outside_while = -8.322231e-02 at= 1.480500e-08
+peak_to_peak_outside_while= 2.02900e+00
+supply_current_rms = 4.36306e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.382168e-10 targ= 1.357181e-08 trig= 1.333359e-08
+fvco_outside_while = 4.19786e+09
+supply_current_rms_outside_while= 4.20263e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.06225e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945287e+00 at= 1.844500e-08
+vlow_outside_while = -8.288671e-02 at= 1.879500e-08
+peak_to_peak_outside_while= 2.02817e+00
+supply_current_rms = 4.16051e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.373921e-10 targ= 1.352939e-08 trig= 1.329200e-08
+fvco_outside_while = 4.21244e+09
+supply_current_rms_outside_while= 4.18070e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.07300e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945115e+00 at= 1.743500e-08
+vlow_outside_while = -8.256464e-02 at= 1.089500e-08
+peak_to_peak_outside_while= 2.02768e+00
+supply_current_rms = 4.14359e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Scale set
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+net1 1.8
+out 6.80528e-09
+net2 0
+vctrl 0
+vdd 1.8
+buf1_out 2.60627e-09
+net4 4.9501e-09
+net5 4.9501e-09
+net3 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+vmeas_current_gnd#branch 1.51199e-06
+vmeas_current_vdd#branch 1.51199e-06
+v2#branch -1.51209e-06
+
+
+No. of Data Rows : 10020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.369945e-10 targ= 1.349674e-08 trig= 1.325975e-08
+fvco_outside_while = 4.21951e+09
+supply_current_rms_outside_while= 4.18015e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.09211e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945018e+00 at= 1.786500e-08
+vlow_outside_while = -8.257644e-02 at= 1.276500e-08
+peak_to_peak_outside_while= 2.02759e+00
+supply_current_rms = 4.14430e-04 from= 0.00000e+00 to= 1.00000e-07
+
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.369945e-10 targ= 1.349674e-08 trig= 1.325975e-08
+Original line no.: 0, new internal line no.: 12452:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.21950753884956503e+09 " u=" 4.21950753884956503e+09" id=0
+fvco_outside_while = 4.21951e+09
+supply_current_rms_outside_while= 4.18015e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.09211e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.945018e+00 at= 1.786500e-08
+vlow_outside_while = -8.257644e-02 at= 1.276500e-08
+Original line no.: 0, new internal line no.: 12458:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.02759407072807374e+00 " u=" 2.02759407072807374e+00" id=0
+peak_to_peak_outside_while= 2.02759e+00
+supply_current_rms = 4.14430e-04 from= 0.00000e+00 to= 1.00000e-07
+
+
+Total analysis time (seconds) = 8.105
+
+Total elapsed time (seconds) = 257.803
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 125.895 MB.
+Total ngspice program size = 610.195 MB.
+Resident set size = 590.176 MB.
+Shared ngspice pages = 7.902 MB.
+Text (code) pages = 5.070 MB.
+Stack = 0 bytes.
+Library pages = 590.449 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.ext
new file mode 100755
index 0000000..0fec1f8
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.ext
@@ -0,0 +1,48 @@
+timestamp 1645106689
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_Q665WF XM24 1 0 1050 0 1 -189
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23 1 0 1049 0 1 681
+port "vss" 1 920 -808 1120 -608 m1
+port "out" 2 1668 118 1868 318 m1
+port "net12" 3 278 126 478 326 m1
+port "vdd" 0 768 1328 968 1528 m1
+node "vss" 1 763.568 920 -808 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 178104 3160 0 0 0 0 0 0 0 0 0 0
+node "out" 5 958.232 1668 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110480 4324 0 0 0 0 0 0 0 0 0 0
+node "net12" 10 1685.48 278 126 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 177200 7660 0 0 0 0 0 0 0 0 0 0
+node "vdd" 1 1001.59 768 1328 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 337396 3816 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "vdd" "net12" 659.683
+cap "vdd" "out" 62.8302
+cap "net12" "out" 392.244
+cap "net12" "vss" 477.691
+cap "out" "vss" 118.401
+cap "XM24/a_n33_n217#" "XM23/a_n173_n220#" 5.88785
+cap "XM23/w_n311_n439#" "XM24/a_18_n129#" 244.507
+cap "XM24/a_n76_n129#" "XM23/w_n311_n439#" 74.9934
+cap "XM24/a_n33_n217#" "XM24/a_18_n129#" 85.7679
+cap "XM24/a_n76_n129#" "XM24/a_n33_n217#" 585.935
+cap "XM23/a_n173_n220#" "XM24/a_18_n129#" 124.039
+cap "XM24/a_n76_n129#" "XM23/a_n173_n220#" 6.54227
+cap "XM23/w_n311_n439#" "XM24/a_n33_n217#" 192.868
+cap "XM24/a_n76_n129#" "XM24/a_18_n129#" 283.321
+cap "XM23/w_n311_n439#" "XM23/a_n78_n220#" 176.838
+cap "XM23/a_n78_n220#" "XM23/a_n33_251#" 53.1817
+cap "XM23/w_n311_n439#" "XM23/a_n33_251#" 241.068
+merge "XM23/VSUBS" "XM24/w_n214_n339#" -239.584 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 103140 -828 0 0 0 0 0 0 0 0 0 0
+merge "XM24/w_n214_n339#" "VSUBS"
+merge "VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "vss"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -575.473 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65082 -898 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "XM23/w_n311_n439#" "XM23/a_18_n220#" -430.39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13600 -1360 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#"
+merge "XM23/a_n173_n220#" "vdd"
+merge "XM23/a_63_n317#" "XM23/a_n129_n317#" -792.149 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -211564 -980 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n129_n317#" "XM23/a_n33_251#"
+merge "XM23/a_n33_251#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "net12"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.mag
new file mode 100755
index 0000000..4f6d014
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.mag
@@ -0,0 +1,49 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645106689
+<< metal1 >>
+rect 768 1380 968 1528
+rect 566 1042 1408 1380
+rect 652 948 1084 988
+rect 652 414 692 948
+rect 1232 906 1272 1042
+rect 828 866 1272 906
+rect 828 508 1438 548
+rect 652 374 1218 414
+rect 278 228 478 326
+rect 652 228 692 374
+rect 278 188 692 228
+rect 278 126 478 188
+rect 652 14 692 188
+rect 1398 234 1438 508
+rect 1668 234 1868 318
+rect 1398 194 1868 234
+rect 652 -26 1184 14
+rect 652 -354 692 -26
+rect 1398 -56 1438 194
+rect 1668 118 1868 194
+rect 1080 -96 1438 -56
+rect 978 -276 1324 -236
+rect 652 -394 1156 -354
+rect 1284 -454 1324 -276
+rect 742 -626 1444 -454
+rect 920 -808 1120 -626
+use sky130_fd_pr__nfet_01v8_Q665WF XM24
+timestamp 1645106608
+transform 1 0 1050 0 1 -189
+box -214 -339 214 339
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23
+timestamp 1645106328
+transform 1 0 1049 0 1 681
+box -311 -439 311 439
+<< labels >>
+flabel metal1 768 1328 968 1528 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 920 -808 1120 -608 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 278 126 478 326 0 FreeSans 256 0 0 0 net12
+port 3 nsew
+flabel metal1 1668 118 1868 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.spice
new file mode 100755
index 0000000..659f2ca
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step1.spice
@@ -0,0 +1,18 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5_layout_step1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220#
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt x3-stage_cs-vco_dp5_layout_step1 vdd vss out net12
+XXM23 vdd vdd out net12 net12 vdd net12 out sky130_fd_pr__pfet_01v8_9P8X3X
+XXM24 net12 vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.ext
new file mode 100755
index 0000000..f7ef431
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.ext
@@ -0,0 +1,115 @@
+timestamp 1645135092
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12 1 0 633 0 1 701
+use sky130_fd_pr__nfet_01v8_Q665WF XM24 1 0 940 0 1 -97
+use sky130_fd_pr__nfet_01v8_86PVFD XM13 1 0 621 0 1 -88
+use sky130_fd_pr__nfet_01v8_D7TJRJ XM22 1 0 305 0 1 -10
+use sky130_fd_pr__pfet_01v8_NCD769 XM21 1 0 317 0 1 519
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23 1 0 1049 0 1 681
+port "vss" 1 920 -698 1120 -498 m1
+port "out" 2 1668 118 1868 318 m1
+port "vdd" 0 768 1328 968 1528 m1
+node "vss" 1 700.445 920 -698 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 159208 2912 0 0 0 0 0 0 0 0 0 0
+node "m1_642_n166#" 1 144.474 642 -166 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12222 666 0 0 0 0 0 0 0 0 0 0
+node "m1_274_n138#" 0 52.438 274 -138 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3720 244 0 0 0 0 0 0 0 0 0 0
+node "m1_192_n232#" 1 149.688 192 -232 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13304 688 0 0 0 0 0 0 0 0 0 0
+node "net10" 3 408.465 -200 170 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38008 1872 0 0 0 0 0 0 0 0 0 0
+node "out" 5 947.768 1668 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 109520 4276 0 0 0 0 0 0 0 0 0 0
+node "m1_554_n2#" 8 1168.96 554 -2 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104148 5328 0 0 0 0 0 0 0 0 0 0
+node "m1_282_618#" 0 53.245 282 618 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3700 248 0 0 0 0 0 0 0 0 0 0
+node "m1_182_506#" 1 154.176 182 506 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12640 712 0 0 0 0 0 0 0 0 0 0
+node "m1_326_n44#" 6 954.614 326 -44 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91668 4366 0 0 0 0 0 0 0 0 0 0
+node "vdd" 2 1155.35 768 1328 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 347514 4534 0 0 0 0 0 0 0 0 0 0
+substrate "w_682_n264#" 0 0 682 -264 pw 1832 204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_642_n166#" "m1_554_n2#" 150.246
+cap "net10" "m1_326_n44#" 102.219
+cap "vdd" "m1_326_n44#" 418.579
+cap "vss" "m1_326_n44#" 5.23256
+cap "net10" "m1_274_n138#" 15.3235
+cap "net10" "m1_192_n232#" 22.5
+cap "vdd" "out" 43.8679
+cap "vss" "out" 308.814
+cap "vdd" "m1_554_n2#" 686.986
+cap "vss" "m1_554_n2#" 360.837
+cap "vss" "m1_642_n166#" 105.141
+cap "m1_182_506#" "m1_282_618#" 45
+cap "m1_326_n44#" "m1_282_618#" 29.4473
+cap "m1_182_506#" "m1_326_n44#" 76.923
+cap "m1_274_n138#" "m1_326_n44#" 31.2353
+cap "m1_326_n44#" "m1_192_n232#" 100.693
+cap "m1_326_n44#" "m1_554_n2#" 491.768
+cap "m1_326_n44#" "m1_642_n166#" 92.6003
+cap "out" "m1_554_n2#" 165.479
+cap "m1_274_n138#" "m1_192_n232#" 76.7857
+cap "net10" "m1_282_618#" 10.2273
+cap "m1_554_n2#" "m1_192_n232#" 3.66667
+cap "net10" "m1_182_506#" 20.5061
+cap "m1_274_n138#" "m1_642_n166#" 2.05882
+cap "XM12/w_n211_n459#" "XM24/w_n214_n339#" 479.123
+cap "XM12/a_n33_n337#" "XM24/w_n214_n339#" 866.87
+cap "XM12/a_15_n240#" "XM12/w_n211_n459#" 713.46
+cap "XM12/a_n33_n337#" "XM12/a_15_n240#" 280.828
+cap "XM24/a_18_n129#" "XM24/w_n214_n339#" 277.85
+cap "XM22/a_n33_n130#" "XM24/w_n214_n339#" 351.767
+cap "XM12/a_15_n240#" "XM24/a_18_n129#" 240.916
+cap "XM12/a_n33_n337#" "XM12/w_n211_n459#" 691.161
+cap "XM12/a_15_n240#" "XM22/a_n33_n130#" 19.7329
+cap "XM24/a_18_n129#" "XM12/w_n211_n459#" 171.087
+cap "XM22/a_n33_n130#" "XM12/w_n211_n459#" 188.301
+cap "XM12/a_n33_n337#" "XM22/a_n33_n130#" 17.3301
+cap "XM12/a_15_n240#" "XM24/w_n214_n339#" 1419
+cap "XM24/a_18_n129#" "XM24/a_n76_n129#" 0.396127
+cap "XM24/a_n33_n217#" "XM23/a_n173_n220#" -66.157
+cap "XM24/a_n33_n217#" "XM24/a_n76_n129#" 0.341172
+cap "XM24/a_18_n129#" "XM24/a_n33_n217#" -1.03921
+cap "XM24/a_18_n129#" "XM23/a_n173_n220#" 62.8779
+cap "XM12/w_n211_n459#" "XM12/a_15_n240#" 891.024
+cap "XM12/a_n33_n337#" "XM12/w_n211_n459#" 625.608
+cap "XM12/w_n211_n459#" "XM23/a_n78_n220#" 167.791
+cap "XM12/a_n33_n337#" "XM12/a_15_n240#" 41.7165
+cap "XM21/a_n33_n155#" "XM12/w_n211_n459#" 8.71566
+cap "XM12/a_15_n240#" "XM23/a_n78_n220#" 110.122
+cap "XM23/a_n173_n220#" "XM23/a_n78_n220#" -299.313
+cap "XM23/a_n173_n220#" "XM23/a_n33_251#" 0.511759
+cap "XM23/a_n78_n220#" "XM23/a_n33_251#" 0.72973
+merge "XM23/VSUBS" "XM21/VSUBS" -586.376 117664 -2956 0 0 0 0 0 0 0 0 -34680 -2176 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -34680 -2176 -12804 -1604 0 0 0 0 0 0 0 0 0 0
+merge "XM21/VSUBS" "XM22/w_n211_n252#"
+merge "XM22/w_n211_n252#" "XM22/a_n73_n42#"
+merge "XM22/a_n73_n42#" "m1_192_n232#"
+merge "m1_192_n232#" "XM13/w_n211_n330#"
+merge "XM13/w_n211_n330#" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "m1_642_n166#"
+merge "m1_642_n166#" "XM24/w_n214_n339#"
+merge "XM24/w_n214_n339#" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "vss"
+merge "vss" "XM12/VSUBS"
+merge "XM12/VSUBS" "w_682_n264#"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -231.766 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42048 -360 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#" 21.8983 0 0 0 0 87644 -3288 0 0 436252 -2712 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 299496 -2712 -6460 -2224 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n173_n220#" "XM23/w_n311_n439#"
+merge "XM23/w_n311_n439#" "XM21/a_n73_n58#"
+merge "XM21/a_n73_n58#" "XM21/w_n211_n277#"
+merge "XM21/w_n211_n277#" "m1_182_506#"
+merge "m1_182_506#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XM12/w_n211_n459#"
+merge "XM12/w_n211_n459#" "vdd"
+merge "XM21/a_15_n58#" "XM22/a_15_n42#" -1319.57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -181692 -1174 0 0 0 0 0 0 0 0 0 0
+merge "XM22/a_15_n42#" "XM13/a_n33_n208#"
+merge "XM13/a_n33_n208#" "XM12/a_n33_n337#"
+merge "XM12/a_n33_n337#" "m1_326_n44#"
+merge "XM21/a_n33_n155#" "m1_282_618#" -439.434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10124 -744 0 0 0 0 0 0 0 0 0 0
+merge "m1_282_618#" "XM22/a_n33_n130#"
+merge "XM22/a_n33_n130#" "m1_274_n138#"
+merge "m1_274_n138#" "net10"
+merge "XM23/a_63_n317#" "XM23/a_n129_n317#" -1688.31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -274154 -1202 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n129_n317#" "XM23/a_n33_251#"
+merge "XM23/a_n33_251#" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "m1_554_n2#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.mag
new file mode 100755
index 0000000..764b325
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.mag
@@ -0,0 +1,95 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645135092
+<< pwell >>
+rect 752 -210 792 -166
+rect 682 -264 688 -252
+<< metal1 >>
+rect 768 1422 968 1528
+rect 566 1084 1408 1422
+rect 490 986 654 1026
+rect 182 546 222 750
+rect 282 618 356 668
+rect 490 554 530 986
+rect 695 947 741 1084
+rect 566 901 741 947
+rect 790 948 1084 988
+rect 566 800 612 901
+rect 790 864 830 948
+rect 1232 906 1272 1084
+rect 882 866 1272 906
+rect 654 824 830 864
+rect 654 802 700 824
+rect 182 506 294 546
+rect 338 490 530 554
+rect 490 414 530 490
+rect 790 414 830 824
+rect 962 508 1438 548
+rect -200 244 -134 270
+rect 290 244 332 414
+rect 490 374 666 414
+rect 790 374 1218 414
+rect -200 204 332 244
+rect -200 170 -134 204
+rect 290 70 332 204
+rect 493 106 528 374
+rect 790 106 830 374
+rect 1398 234 1438 508
+rect 1668 234 1868 318
+rect 1398 194 1868 234
+rect 486 66 662 106
+rect 790 66 980 106
+rect 486 20 526 66
+rect 790 34 830 66
+rect 192 -42 284 20
+rect 192 -232 232 -42
+rect 326 -44 526 20
+rect 554 -2 830 34
+rect 274 -138 336 -78
+rect 486 -246 526 -44
+rect 642 -166 724 -124
+rect 486 -286 644 -246
+rect 682 -375 724 -166
+rect 790 -260 830 -2
+rect 1398 -56 1438 194
+rect 1668 118 1868 194
+rect 970 -96 1438 -56
+rect 870 -180 1214 -140
+rect 790 -300 980 -260
+rect 1174 -342 1214 -180
+rect 740 -514 1334 -342
+rect 920 -698 1120 -514
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12
+timestamp 1645134758
+transform 1 0 633 0 1 701
+box -211 -459 211 459
+use sky130_fd_pr__nfet_01v8_Q665WF XM24
+timestamp 1645106608
+transform 1 0 940 0 1 -97
+box -214 -339 214 339
+use sky130_fd_pr__nfet_01v8_86PVFD XM13
+timestamp 1645123349
+transform 1 0 621 0 1 -88
+box -211 -330 211 330
+use sky130_fd_pr__nfet_01v8_D7TJRJ XM22
+timestamp 1645134235
+transform 1 0 305 0 1 -10
+box -211 -252 211 252
+use sky130_fd_pr__pfet_01v8_NCD769 XM21
+timestamp 1645133562
+transform 1 0 317 0 1 519
+box -211 -277 211 277
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23
+timestamp 1645106328
+transform 1 0 1049 0 1 681
+box -311 -439 311 439
+<< labels >>
+flabel metal1 1668 118 1868 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 768 1328 968 1528 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 920 -698 1120 -498 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 -200 170 -134 270 5 net10
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.spice
new file mode 100755
index 0000000..48fa255
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step2.spice
@@ -0,0 +1,38 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5_layout_step2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220#
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NCD769 w_n211_n277# a_15_n58# a_n73_n58# a_n33_n155#
+X0 a_15_n58# a_n33_n155# a_n73_n58# w_n211_n277# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_D7TJRJ a_n33_n130# a_15_n42# a_n73_n42# w_n211_n252#
+X0 a_15_n42# a_n33_n130# a_n73_n42# w_n211_n252# sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp5_layout_step2 vdd vss out
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out sky130_fd_pr__pfet_01v8_9P8X3X
+XXM12 m1_554_n2# vdd vdd m1_326_n44# sky130_fd_pr__pfet_01v8_V5LP55
+XXM13 m1_554_n2# vss vss m1_326_n44# sky130_fd_pr__nfet_01v8_86PVFD
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM21 vdd m1_326_n44# vdd net10 sky130_fd_pr__pfet_01v8_NCD769
+XXM22 net10 m1_326_n44# vss vss sky130_fd_pr__nfet_01v8_D7TJRJ
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.ext
new file mode 100755
index 0000000..f4b5070
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.ext
@@ -0,0 +1,337 @@
+timestamp 1645189256
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_1 1 0 -103 0 1 95
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_0 1 0 103 0 1 93
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_2 1 0 -305 0 1 97
+use sky130_fd_pr__nfet_01v8_26QSQN sky130_fd_pr__nfet_01v8_26QSQN_2 1 0 -304 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN sky130_fd_pr__nfet_01v8_26QSQN_1 1 0 -96 0 1 -393
+use sky130_fd_pr__nfet_01v8_26QSQN sky130_fd_pr__nfet_01v8_26QSQN_0 1 0 110 0 1 -391
+use sky130_fd_pr__nfet_01v8_N32XHY sky130_fd_pr__nfet_01v8_N32XHY_0 1 0 305 0 1 103
+use sky130_fd_pr__nfet_01v8_86PVFD XM13 1 0 621 0 1 -88
+use sky130_fd_pr__nfet_01v8_Q665WF XM24 1 0 940 0 1 -97
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_1 1 0 -103 0 1 362
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_0 1 0 97 0 1 362
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_2 1 0 -307 0 1 362
+use sky130_fd_pr__pfet_01v8_TPJM7Z sky130_fd_pr__pfet_01v8_TPJM7Z_2 1 0 -308 0 1 858
+use sky130_fd_pr__pfet_01v8_TPJM7Z sky130_fd_pr__pfet_01v8_TPJM7Z_1 1 0 -102 0 1 858
+use sky130_fd_pr__pfet_01v8_TPJM7Z sky130_fd_pr__pfet_01v8_TPJM7Z_0 1 0 105 0 1 859
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 314 0 1 381
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12 1 0 633 0 1 701
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23 1 0 1049 0 1 681
+port "vss" 1 920 -698 1120 -498 m1
+port "out" 2 1668 118 1868 318 m1
+port "vdd" 0 768 1328 968 1528 m1
+node "m1_642_n166#" 1 269.524 642 -166 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12222 666 0 0 0 0 0 0 0 0 0 0
+node "vss" 8 3381.61 920 -698 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 352496 9514 0 0 0 0 0 0 0 0 0 0
+node "vctrl" 3 843.922 -652 -694 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26740 1456 28784 1140 0 0 0 0 0 0 0 0
+node "m1_40_n138#" 1 193.54 40 -138 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0
+node "m1_n166_n140#" 1 193.54 -166 -140 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0
+node "out" 5 766.04 1668 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 109520 4276 0 0 0 0 0 0 0 0 0 0
+node "m1_554_n2#" 8 862.174 554 -2 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104148 5328 0 0 0 0 0 0 0 0 0 0
+node "m1_326_30#" 6 806.519 326 30 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92944 4448 0 0 0 0 0 0 0 0 0 0
+node "m1_32_418#" 1 0 32 418 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14080 784 0 0 0 0 0 0 0 0 0 0
+node "m1_n44_34#" 2 304.43 -44 34 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24868 1312 0 0 0 0 0 0 0 0 0 0
+node "m1_n368_n144#" 1 193.54 -368 -144 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0
+node "m1_n248_34#" 2 297.81 -248 34 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25028 1320 0 0 0 0 0 0 0 0 0 0
+node "m1_n390_206#" 5 491.594 -390 206 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36212 1880 26640 1376 0 0 0 0 0 0 0 0
+node "m1_n166_424#" 1 0 -166 424 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13680 764 0 0 0 0 0 0 0 0 0 0
+node "m1_n370_410#" 1 0 -370 410 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14160 788 0 0 0 0 0 0 0 0 0 0
+node "net1" 3 -25.3076 -534 1094 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20360 1180 27104 1080 0 0 0 0 0 0 0 0
+node "vdd" 7 630.045 768 1328 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 473238 10434 0 0 0 0 0 0 0 0 0 0
+node "w_n420_804#" 3204 5596.85 -420 804 nw 0 0 0 0 1865616 5740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "w_n474_n842#" 0 0 -474 -842 pw 1275520 6068 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_326_30#" "m1_n390_206#" 102.025
+cap "m1_n368_n144#" "m1_n390_206#" 13.4759
+cap "m1_40_n138#" "m1_n390_206#" 14.4
+cap "m1_32_418#" "m1_n248_34#" 1.125
+cap "vdd" "m1_n390_206#" 10.7276
+cap "vss" "m1_n166_n140#" 22.5
+cap "w_n420_804#" "m1_n44_34#" 128.294
+cap "net1" "m1_n370_410#" 5.33835
+cap "m1_32_418#" "m1_326_30#" 5.75188
+cap "m1_n248_34#" "m1_n166_n140#" 29.4176
+cap "w_n420_804#" "m1_n166_424#" 165.512
+cap "m1_40_n138#" "m1_32_418#" 3.93443
+cap "m1_n248_34#" "m1_n370_410#" 7.68293
+cap "vdd" "m1_32_418#" 79.5
+cap "w_n420_804#" "m1_554_n2#" 682.342
+cap "m1_n368_n144#" "m1_n166_n140#" 51.6667
+cap "m1_n368_n144#" "m1_n370_410#" 4.6978
+cap "m1_40_n138#" "m1_n166_n140#" 50.9639
+cap "w_n420_804#" "net1" 399.814
+cap "vss" "m1_n44_34#" 5.62874
+cap "w_n420_804#" "m1_n248_34#" 133.378
+cap "m1_n166_424#" "net1" 0.54878
+cap "m1_n44_34#" "m1_n248_34#" 288.996
+cap "w_n420_804#" "out" 181.728
+cap "m1_n248_34#" "m1_n166_424#" 11.5714
+cap "w_n420_804#" "m1_326_30#" 541.295
+cap "vss" "m1_554_n2#" 366.793
+cap "m1_n44_34#" "m1_326_30#" 31.3316
+cap "m1_n368_n144#" "m1_n44_34#" 1.90141
+cap "m1_n166_n140#" "m1_n390_206#" 2.46094
+cap "w_n420_804#" "vdd" 1816.53
+cap "m1_n44_34#" "m1_40_n138#" 32.4573
+cap "m1_n370_410#" "m1_n390_206#" 13.4132
+cap "vss" "m1_n248_34#" 4.51187
+cap "out" "m1_554_n2#" 165.479
+cap "vdd" "m1_n166_424#" 37.381
+cap "m1_326_30#" "m1_554_n2#" 491.768
+cap "vss" "out" 308.814
+cap "vss" "m1_326_30#" 89.2566
+cap "m1_32_418#" "m1_n370_410#" 43.011
+cap "vdd" "m1_554_n2#" 694.694
+cap "w_n420_804#" "m1_n390_206#" 322.978
+cap "m1_554_n2#" "m1_642_n166#" 150.246
+cap "vss" "m1_40_n138#" 50.5556
+cap "m1_n368_n144#" "m1_n248_34#" 6.75
+cap "m1_n44_34#" "m1_n390_206#" 416.266
+cap "vdd" "net1" 578.195
+cap "vss" "m1_642_n166#" 115.807
+cap "m1_40_n138#" "m1_n248_34#" 3.26613
+cap "w_n420_804#" "m1_32_418#" 169.872
+cap "vss" "vctrl" 814.014
+cap "m1_40_n138#" "m1_326_30#" 4.02439
+cap "vdd" "out" 43.8679
+cap "m1_n368_n144#" "m1_40_n138#" 22.5
+cap "m1_n44_34#" "m1_32_418#" 19.2756
+cap "vdd" "m1_326_30#" 577.383
+cap "m1_326_30#" "m1_642_n166#" 92.6003
+cap "vss" "m1_n390_206#" 26.7692
+cap "m1_32_418#" "m1_n166_424#" 97.4051
+cap "m1_n248_34#" "m1_n390_206#" 383.756
+cap "w_n420_804#" "m1_n370_410#" 170.744
+cap "m1_n44_34#" "m1_n166_n140#" 8.78049
+cap "m1_n44_34#" "m1_n370_410#" 2.2028
+cap "m1_n166_424#" "m1_n166_n140#" 4.81283
+cap "m1_n166_424#" "m1_n370_410#" 93.2927
+cap "m1_32_418#" "net1" 0.272727
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 17.2882
+cap "XM13/a_n73_n120#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 2.2526
+cap "XM24/a_n76_n129#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" 45.2737
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" -62.0102
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 11.292
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 202.863
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" 180.084
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 10.2409
+cap "XM21/a_n73_n22#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 9.45975
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 19.8425
+cap "XM13/a_n73_n120#" "XM23/a_n78_n220#" 5.74655
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_n33_235#" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_n33_235#" 0.134503
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 17.7914
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 0.011162
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 97.1903
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" -34.2864
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" -28.1824
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" 137.553
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 4.08268
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "XM21/a_n73_n22#" 31.882
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 749.48
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" 111.871
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 24.0728
+cap "XM23/a_n78_n220#" "XM12/a_n73_n240#" 4.40873
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 6.47672
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" 6.36381
+cap "XM13/a_n73_n120#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 194.059
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" 744.846
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 7.37489
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 9.91295
+cap "XM21/a_n73_n22#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" 16.1685
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_18_n276#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" 7.46996
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" 92.6601
+cap "XM13/a_n73_n120#" "XM23/a_n173_n220#" 12.9076
+cap "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" "XM12/a_n73_n240#" 7.33339
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 21.6562
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" -76.6937
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" 21.3453
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 677.116
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 252.03
+cap "XM21/a_n73_n22#" "XM13/a_n73_n120#" 1.94638
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" 80.3081
+cap "XM23/a_n173_n220#" "XM12/a_n73_n240#" 5.90957
+cap "XM24/a_n76_n129#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 6.67151
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 185.257
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_18_n276#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 0.119134
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 20.396
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 17.5642
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" 15.3069
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 36.4243
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_18_n276#" 7.73343
+cap "XM21/a_n73_n22#" "XM12/a_n73_n240#" 2.54737
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" -0.351399
+cap "XM24/a_18_n129#" "XM13/a_n73_n120#" 18.4024
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" 21.4892
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" 364.313
+cap "XM21/a_n73_n22#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 15.0248
+cap "XM21/a_n73_n22#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" 9.10601
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" 171.775
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 9.99979
+cap "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 68.9707
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" 825.326
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_n33_235#" 10.2504
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_18_n276#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 6.4542
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" -21.6128
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" 1.47516
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" 6.97622
+cap "XM23/a_n173_n220#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" 4.20833
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" 451.084
+cap "XM13/a_n73_n120#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" 9.32404
+cap "XM24/a_18_n129#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" 19.9149
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" -7.68293
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" 329.538
+cap "XM21/a_n73_n22#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" 4.38343
+cap "XM24/a_n76_n129#" "XM13/a_n73_n120#" 19.2606
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" -56.2004
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 110.797
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 213.93
+cap "XM21/a_n73_n22#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 59.6663
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_n33_235#" 0.061008
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" -8.26364
+cap "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "XM12/a_n73_n240#" 4.47012
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_n33_235#" 0.270588
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_n33_235#" 11.2793
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_18_n276#" 0.487011
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" -2.43958
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" 179.855
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 35.563
+cap "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" 8.82462
+cap "XM13/a_n73_n120#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" 4.63636
+cap "XM13/a_n73_n120#" "XM24/a_18_n129#" 123.077
+cap "XM24/a_18_n129#" "XM13/w_n211_n330#" 257.935
+cap "XM12/a_n73_n240#" "XM24/a_18_n129#" 4.40873
+cap "XM12/w_n211_n459#" "XM23/a_n173_n220#" 4.20833
+cap "XM23/a_n173_n220#" "XM13/w_n211_n330#" 8.94024
+cap "XM13/a_n73_n120#" "XM23/a_n173_n220#" 20.1977
+cap "XM12/a_n73_n240#" "XM23/a_n173_n220#" 5.90957
+cap "XM12/w_n211_n459#" "XM13/a_n33_n208#" 5.12782
+cap "XM12/w_n211_n459#" "XM13/w_n211_n330#" 174.22
+cap "XM13/a_n73_n120#" "XM12/w_n211_n459#" 152.359
+cap "XM13/w_n211_n330#" "XM13/a_n33_n208#" 10.5048
+cap "XM13/a_n73_n120#" "XM13/a_n33_n208#" 22.1203
+cap "XM13/a_n73_n120#" "XM13/w_n211_n330#" 522.991
+cap "XM23/a_n173_n220#" "XM24/a_18_n129#" 58.9826
+cap "XM12/w_n211_n459#" "XM24/a_18_n129#" 7.86836
+cap "XM12/a_15_n240#" "XM23/a_n78_n220#" 37.5489
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n33_33#" 3.67773
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" 1.30806
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" -130.793
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" 62.1509
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" 51.8897
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "XM21/a_15_n22#" 622.657
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n33_n111#" 7.85256
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "XM23/a_n173_n220#" 45.6782
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "XM12/a_15_n240#" 68.3088
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n33_33#" 5.5371
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" 137.358
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n33_33#" -3.05569
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 418.96
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" 5.38931
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "XM23/a_n78_n220#" 28.6714
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n33_n111#" 5.53081
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_15_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" -2.41239
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_15_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" 7.46996
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" 478.64
+cap "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" -0.494928
+cap "XM21/a_15_n22#" "XM23/a_n173_n220#" 8.37358
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" 139.378
+cap "XM21/a_15_n22#" "XM12/a_15_n240#" 77.4007
+cap "XM12/a_15_n240#" "XM23/a_n173_n220#" 70.18
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n33_n111#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" -2.8545
+cap "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_15_n14#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" 5.07866
+cap "XM12/a_15_n240#" "XM23/a_n78_n220#" 168.637
+cap "XM12/a_n33_n337#" "XM12/w_n211_n459#" 8.37358
+cap "XM12/a_n33_n337#" "XM12/a_15_n240#" 2.54684
+cap "XM12/w_n211_n459#" "XM12/a_15_n240#" 625.922
+cap "XM12/w_n211_n459#" "XM23/a_n78_n220#" 203.065
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_n33_235#" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_n33_235#" -47.145 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7891 -620 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_n33_235#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n33_235#" "net1"
+merge "XM23/VSUBS" "XM12/VSUBS" -1164.11 -83784 -4984 0 0 0 0 0 0 0 0 3000 -1244 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3000 -1244 -15940 -2102 0 0 0 0 0 0 0 0 0 0
+merge "XM12/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "sky130_fd_pr__pfet_01v8_TPJM7Z_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_0/VSUBS" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_1/VSUBS" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_2/VSUBS" "sky130_fd_pr__pfet_01v8_BKC9WK_2/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_2/VSUBS" "sky130_fd_pr__pfet_01v8_BKC9WK_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_0/VSUBS" "sky130_fd_pr__pfet_01v8_BKC9WK_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_1/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM24/w_n214_n339#"
+merge "XM24/w_n214_n339#" "XM13/w_n211_n330#"
+merge "XM13/w_n211_n330#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n73_n73#"
+merge "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n73_n73#" "sky130_fd_pr__nfet_01v8_26QSQN_0/a_18_n209#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_0/a_18_n209#" "sky130_fd_pr__nfet_01v8_26QSQN_1/a_18_n209#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_1/a_18_n209#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_2/a_18_n209#" "vss"
+merge "vss" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "m1_642_n166#"
+merge "m1_642_n166#" "sky130_fd_pr__nfet_01v8_N32XHY_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_N32XHY_0/VSUBS" "sky130_fd_pr__nfet_01v8_26QSQN_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_0/VSUBS" "sky130_fd_pr__nfet_01v8_26QSQN_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_1/VSUBS" "sky130_fd_pr__nfet_01v8_26QSQN_2/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_2/VSUBS" "sky130_fd_pr__nfet_01v8_ALRCN6_2/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_2/VSUBS" "sky130_fd_pr__nfet_01v8_ALRCN6_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_0/VSUBS" "sky130_fd_pr__nfet_01v8_ALRCN6_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_1/VSUBS" "w_n474_n842#"
+merge "XM21/a_n33_n119#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n33_n111#" -517.838 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -92752 -880 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n33_n111#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_15_n14#"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_15_n14#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n33_33#"
+merge "sky130_fd_pr__nfet_01v8_N32XHY_0/a_n33_33#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n33_33#"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n33_33#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_15_n73#" "m1_n390_206#"
+merge "XM12/a_n33_n337#" "XM21/a_15_n22#" -410.605 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -73320 -1162 0 0 0 0 0 0 0 0 0 0
+merge "XM21/a_15_n22#" "XM13/a_n33_n208#"
+merge "XM13/a_n33_n208#" "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#"
+merge "sky130_fd_pr__nfet_01v8_N32XHY_0/a_15_n73#" "m1_326_30#"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -220.698 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7832 -360 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "XM23/w_n311_n439#" "XM23/a_18_n220#" -3921.84 0 0 0 0 -1233161 -14748 0 0 -4480 -1680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4480 -1680 -6748 -2234 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#"
+merge "XM23/a_n173_n220#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XM21/a_n73_n22#"
+merge "XM21/a_n73_n22#" "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_18_n276#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_18_n276#" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_18_n276#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_18_n276#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_18_n276#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_18_n276#" "vdd"
+merge "vdd" "XM12/w_n211_n459#"
+merge "XM12/w_n211_n459#" "XM21/w_n109_n122#"
+merge "XM21/w_n109_n122#" "sky130_fd_pr__pfet_01v8_TPJM7Z_0/w_n112_n338#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_0/w_n112_n338#" "sky130_fd_pr__pfet_01v8_TPJM7Z_1/w_n112_n338#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_1/w_n112_n338#" "sky130_fd_pr__pfet_01v8_TPJM7Z_2/w_n112_n338#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_2/w_n112_n338#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/w_n109_n114#"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_2/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/w_n109_n114#"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_0/w_n109_n114#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_1/w_n109_n114#" "w_n420_804#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n76_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" -394.103 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -400 -180 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_n73_n73#" "m1_n368_n144#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_0/a_n33_n297#" "sky130_fd_pr__nfet_01v8_26QSQN_1/a_n33_n297#" -609.793 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7820 -616 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_26QSQN_1/a_n33_n297#" "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_2/a_n33_n297#" "vctrl"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_1/a_n76_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" -394.103 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -640 -192 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n73_n73#" "m1_n166_n140#"
+merge "sky130_fd_pr__nfet_01v8_26QSQN_0/a_n76_n209#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" -394.103 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -800 -200 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n73_n73#" "m1_40_n138#"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_15_n14#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n33_n111#" -304.418 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -46632 -574 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n33_n111#" "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_15_n73#"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_2/a_15_n73#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_n33_33#" "m1_n248_34#"
+merge "XM23/a_63_n317#" "XM23/a_n129_n317#" -615.841 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -254654 -1202 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n129_n317#" "XM23/a_n33_251#"
+merge "XM23/a_n33_251#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "m1_554_n2#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_2/a_n76_n276#" "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" -47.7726 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4454 -288 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_2/a_n73_n14#" "m1_n370_410#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_1/a_n76_n276#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" -16.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2160 -268 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_n73_n14#" "m1_n166_424#"
+merge "sky130_fd_pr__pfet_01v8_TPJM7Z_0/a_n76_n276#" "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" -48.632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4650 -280 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n73_n14#" "m1_32_418#"
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_0/a_n33_n111#" "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_15_n14#" -284.545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -38316 -550 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_BKC9WK_1/a_15_n14#" "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n33_33#"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_0/a_n33_33#" "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#"
+merge "sky130_fd_pr__nfet_01v8_ALRCN6_1/a_15_n73#" "m1_n44_34#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.mag
new file mode 100755
index 0000000..1eb8f6c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.mag
@@ -0,0 +1,244 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645189256
+<< nwell >>
+rect -420 1244 538 1332
+rect -420 804 1360 1244
+rect -416 242 1360 804
+<< pwell >>
+rect -472 -314 410 242
+rect 460 -314 920 242
+rect -474 -368 920 -314
+rect -474 -842 484 -368
+<< metal1 >>
+rect 768 1422 968 1528
+rect 566 1350 1408 1422
+rect -274 1302 1408 1350
+rect -334 1156 -278 1162
+rect -534 1142 -482 1152
+rect -534 1102 -334 1142
+rect -534 1094 -482 1102
+rect -334 1094 -278 1100
+rect -248 974 -208 1302
+rect -130 1156 -74 1162
+rect -130 1094 -74 1100
+rect -284 926 -208 974
+rect -34 970 6 1302
+rect 70 1100 76 1156
+rect 132 1100 138 1156
+rect 168 974 208 1302
+rect -284 916 -238 926
+rect -78 922 6 970
+rect 130 926 208 974
+rect -370 410 -330 764
+rect -166 424 -126 766
+rect -340 264 -298 302
+rect -384 258 -298 264
+rect -390 206 -384 258
+rect -332 206 -298 258
+rect -384 200 -298 206
+rect -340 148 -298 200
+rect -248 256 -208 424
+rect -134 256 -92 304
+rect -248 216 -92 256
+rect -368 -144 -328 46
+rect -248 34 -208 216
+rect -134 150 -92 216
+rect -44 258 -4 424
+rect 32 418 72 770
+rect 252 452 292 1302
+rect 566 1084 1408 1302
+rect 490 986 654 1026
+rect 490 452 530 986
+rect 695 947 741 1084
+rect 566 901 741 947
+rect 790 948 1084 988
+rect 566 800 612 901
+rect 790 864 830 948
+rect 1232 906 1272 1084
+rect 882 866 1272 906
+rect 654 824 830 864
+rect 654 802 700 824
+rect 338 414 530 452
+rect 790 414 830 824
+rect 962 508 1438 548
+rect 120 362 210 402
+rect 338 388 666 414
+rect 490 374 666 388
+rect 790 374 1218 414
+rect 66 258 108 296
+rect 170 264 210 362
+rect -44 218 108 258
+rect -166 -140 -126 50
+rect -44 34 -4 218
+rect 66 142 108 218
+rect 164 258 216 264
+rect 276 256 318 314
+rect 216 216 318 256
+rect 493 252 528 374
+rect 164 200 216 206
+rect 170 76 210 200
+rect 276 190 318 216
+rect 452 212 528 252
+rect 493 106 528 212
+rect 790 106 830 374
+rect 1398 234 1438 508
+rect 1668 234 1868 318
+rect 1398 194 1868 234
+rect 486 94 662 106
+rect 40 -138 80 52
+rect 130 36 210 76
+rect 340 68 662 94
+rect 326 66 662 68
+rect 790 66 980 106
+rect -338 -628 -282 -622
+rect -652 -640 -582 -632
+rect -344 -640 -338 -628
+rect -652 -680 -338 -640
+rect -652 -694 -582 -680
+rect -344 -684 -338 -680
+rect -282 -684 -276 -628
+rect -338 -690 -282 -684
+rect -246 -724 -206 -345
+rect -128 -628 -72 -622
+rect -134 -684 -128 -628
+rect -72 -684 -64 -628
+rect -128 -690 -72 -684
+rect -36 -724 4 -345
+rect 84 -628 140 -622
+rect 84 -690 140 -684
+rect 170 -724 210 -341
+rect 242 -724 282 44
+rect 326 30 526 66
+rect 790 34 830 66
+rect 486 -246 526 30
+rect 554 -2 830 34
+rect 642 -166 724 -124
+rect 486 -286 644 -246
+rect 682 -375 724 -166
+rect 790 -260 830 -2
+rect 1398 -56 1438 194
+rect 1668 118 1868 194
+rect 970 -96 1438 -56
+rect 870 -180 1214 -140
+rect 790 -300 980 -260
+rect 1174 -342 1214 -180
+rect 740 -514 1334 -342
+rect 774 -724 858 -514
+rect 920 -698 1120 -514
+rect -324 -808 858 -724
+<< via1 >>
+rect -334 1100 -278 1156
+rect -130 1100 -74 1156
+rect 76 1100 132 1156
+rect -384 206 -332 258
+rect 164 206 216 258
+rect -338 -684 -282 -628
+rect -128 -684 -72 -628
+rect 84 -684 140 -628
+<< metal2 >>
+rect 76 1156 132 1162
+rect -340 1100 -334 1156
+rect -278 1100 -130 1156
+rect -74 1100 76 1156
+rect 76 1094 132 1100
+rect -384 258 -332 264
+rect -390 206 -384 258
+rect -332 252 -326 258
+rect 158 252 164 258
+rect -332 212 164 252
+rect -332 206 -326 212
+rect 158 206 164 212
+rect 216 206 222 258
+rect -384 200 -332 206
+rect -338 -628 -282 -622
+rect -128 -628 -72 -622
+rect -344 -684 -338 -628
+rect -282 -684 -128 -628
+rect -72 -684 84 -628
+rect 140 -684 146 -628
+rect -338 -690 -282 -684
+rect -128 -690 -72 -684
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_1
+timestamp 1645180687
+transform 1 0 -103 0 1 95
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_0
+timestamp 1645180687
+transform 1 0 103 0 1 93
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_2
+timestamp 1645180687
+transform 1 0 -305 0 1 97
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_26QSQN sky130_fd_pr__nfet_01v8_26QSQN_2
+timestamp 1645187587
+transform 1 0 -304 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN sky130_fd_pr__nfet_01v8_26QSQN_1
+timestamp 1645187587
+transform 1 0 -96 0 1 -393
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN sky130_fd_pr__nfet_01v8_26QSQN_0
+timestamp 1645187587
+transform 1 0 110 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_N32XHY sky130_fd_pr__nfet_01v8_N32XHY_0
+timestamp 1645180687
+transform 1 0 305 0 1 103
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_86PVFD XM13
+timestamp 1645123349
+transform 1 0 621 0 1 -88
+box -211 -330 211 330
+use sky130_fd_pr__nfet_01v8_Q665WF XM24
+timestamp 1645106608
+transform 1 0 940 0 1 -97
+box -214 -339 214 339
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_1
+timestamp 1645182413
+transform 1 0 -103 0 1 362
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_0
+timestamp 1645182413
+transform 1 0 97 0 1 362
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_2
+timestamp 1645182413
+transform 1 0 -307 0 1 362
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z sky130_fd_pr__pfet_01v8_TPJM7Z_2
+timestamp 1645187069
+transform 1 0 -308 0 1 858
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z sky130_fd_pr__pfet_01v8_TPJM7Z_1
+timestamp 1645187069
+transform 1 0 -102 0 1 858
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z sky130_fd_pr__pfet_01v8_TPJM7Z_0
+timestamp 1645187069
+transform 1 0 105 0 1 859
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645182011
+transform 1 0 314 0 1 381
+box -109 -122 109 156
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12
+timestamp 1645134758
+transform 1 0 633 0 1 701
+box -211 -459 211 459
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23
+timestamp 1645106328
+transform 1 0 1049 0 1 681
+box -311 -439 311 439
+<< labels >>
+flabel metal1 1668 118 1868 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 768 1328 968 1528 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 920 -698 1120 -498 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 -652 -694 -582 -632 1 vctrl
+rlabel metal1 -534 1094 -482 1152 1 net1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.spice
new file mode 100755
index 0000000..20fdcf0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3.spice
@@ -0,0 +1,66 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5_layout_step3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_9P8X3X a_n173_n220# a_18_n220# a_114_n220# a_n129_n317#
++ a_63_n317# w_n311_n439# a_n33_251# a_n78_n220#
+X0 a_114_n220# a_63_n317# a_18_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n311_n439# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_V5LP55 a_15_n240# w_n211_n459# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n211_n459# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_Q665WF a_n33_n217# a_n76_n129# a_18_n129# w_n214_n339#
+X0 a_18_n129# a_n33_n217# a_n76_n129# w_n214_n339# sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_86PVFD a_n73_n120# a_15_n120# w_n211_n330# a_n33_n208#
+X0 a_15_n120# a_n33_n208# a_n73_n120# w_n211_n330# sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ALRCN6 a_n33_33# a_15_n73# a_n73_n73# VSUBS
+X0 a_15_n73# a_n33_33# a_n73_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_N32XHY a_n33_33# a_15_n73# a_n73_n73# VSUBS
+X0 a_15_n73# a_n33_33# a_n73_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp5_layout_step3 vdd vss out
+XXM23 vdd vdd out m1_554_n2# m1_554_n2# vdd m1_554_n2# out sky130_fd_pr__pfet_01v8_9P8X3X
+XXM12 m1_554_n2# vdd vdd m1_326_30# sky130_fd_pr__pfet_01v8_V5LP55
+XXM24 m1_554_n2# vss out vss sky130_fd_pr__nfet_01v8_Q665WF
+XXM13 m1_554_n2# vss vss m1_326_30# sky130_fd_pr__nfet_01v8_86PVFD
+Xsky130_fd_pr__nfet_01v8_ALRCN6_0 m1_n44_34# m1_n390_206# m1_40_n138# vss sky130_fd_pr__nfet_01v8_ALRCN6
+Xsky130_fd_pr__nfet_01v8_ALRCN6_1 m1_n248_34# m1_n44_34# m1_n166_n140# vss sky130_fd_pr__nfet_01v8_ALRCN6
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_0 vdd vdd net1 m1_32_418# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__nfet_01v8_ALRCN6_2 m1_n390_206# m1_n248_34# m1_n368_n144# vss sky130_fd_pr__nfet_01v8_ALRCN6
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_1 vdd vdd net1 m1_n166_424# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_TPJM7Z_2 vdd vdd net1 m1_n370_410# sky130_fd_pr__pfet_01v8_TPJM7Z
+Xsky130_fd_pr__pfet_01v8_BKC9WK_0 m1_32_418# m1_n44_34# vdd m1_n390_206# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_1 m1_n166_424# m1_n248_34# vdd m1_n44_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__pfet_01v8_BKC9WK_2 m1_n370_410# m1_n390_206# vdd m1_n248_34# sky130_fd_pr__pfet_01v8_BKC9WK
+Xsky130_fd_pr__nfet_01v8_26QSQN_0 m1_40_n138# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_1 m1_n166_n140# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_26QSQN_2 m1_n368_n144# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+Xsky130_fd_pr__nfet_01v8_N32XHY_0 m1_n390_206# m1_326_30# vss vss sky130_fd_pr__nfet_01v8_N32XHY
+XXM21 m1_326_30# m1_n390_206# vdd vdd sky130_fd_pr__pfet_01v8_AZHELG
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3_-_seccopy_18-2-2022_12y16.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3_-_seccopy_18-2-2022_12y16.mag
new file mode 100755
index 0000000..a57f773
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_layout_step3_-_seccopy_18-2-2022_12y16.mag
@@ -0,0 +1,137 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645182981
+<< nwell >>
+rect -328 248 460 1058
+rect -416 242 422 248
+<< pwell >>
+rect -472 -368 410 242
+rect 460 -368 920 242
+<< metal1 >>
+rect 768 1422 968 1528
+rect 566 1084 1408 1422
+rect 490 986 654 1026
+rect -370 410 -330 628
+rect -166 424 -126 637
+rect -340 148 -298 302
+rect -248 256 -208 424
+rect -134 256 -92 304
+rect -248 216 -92 256
+rect -368 -144 -328 46
+rect -248 34 -208 216
+rect -134 150 -92 216
+rect -44 258 -4 424
+rect 32 418 72 626
+rect 252 452 292 656
+rect 490 452 530 986
+rect 695 947 741 1084
+rect 566 901 741 947
+rect 790 948 1084 988
+rect 566 800 612 901
+rect 790 864 830 948
+rect 1232 906 1272 1084
+rect 882 866 1272 906
+rect 654 824 830 864
+rect 654 802 700 824
+rect 338 414 530 452
+rect 790 414 830 824
+rect 962 508 1438 548
+rect 120 362 210 402
+rect 338 388 666 414
+rect 490 374 666 388
+rect 790 374 1218 414
+rect 66 258 108 296
+rect -44 218 108 258
+rect -166 -140 -126 50
+rect -44 34 -4 218
+rect 66 142 108 218
+rect 170 256 210 362
+rect 276 256 318 314
+rect 170 216 318 256
+rect 170 76 210 216
+rect 276 190 318 216
+rect 493 106 528 374
+rect 790 106 830 374
+rect 1398 234 1438 508
+rect 1668 234 1868 318
+rect 1398 194 1868 234
+rect 486 94 662 106
+rect 40 -138 80 52
+rect 130 36 210 76
+rect 340 68 662 94
+rect 326 66 662 68
+rect 790 66 980 106
+rect 242 -132 282 58
+rect 326 30 526 66
+rect 790 34 830 66
+rect 486 -246 526 30
+rect 554 -2 830 34
+rect 642 -166 724 -124
+rect 486 -286 644 -246
+rect 682 -375 724 -166
+rect 790 -260 830 -2
+rect 1398 -56 1438 194
+rect 1668 118 1868 194
+rect 970 -96 1438 -56
+rect 870 -180 1214 -140
+rect 790 -300 980 -260
+rect 1174 -342 1214 -180
+rect 740 -514 1334 -342
+rect 920 -698 1120 -514
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645182011
+transform 1 0 314 0 1 381
+box -109 -122 109 156
+use sky130_fd_pr__nfet_01v8_N32XHY sky130_fd_pr__nfet_01v8_N32XHY_0
+timestamp 1645180687
+transform 1 0 305 0 1 103
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_1
+timestamp 1645182413
+transform 1 0 -103 0 1 362
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_0
+timestamp 1645182413
+transform 1 0 97 0 1 362
+box -109 -114 109 148
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_1
+timestamp 1645180687
+transform 1 0 -103 0 1 95
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_86PVFD XM13
+timestamp 1645123349
+transform 1 0 621 0 1 -88
+box -211 -330 211 330
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_0
+timestamp 1645180687
+transform 1 0 103 0 1 93
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12
+timestamp 1645134758
+transform 1 0 633 0 1 701
+box -211 -459 211 459
+use sky130_fd_pr__nfet_01v8_Q665WF XM24
+timestamp 1645106608
+transform 1 0 940 0 1 -97
+box -214 -339 214 339
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23
+timestamp 1645106328
+transform 1 0 1049 0 1 681
+box -311 -439 311 439
+use sky130_fd_pr__pfet_01v8_BKC9WK sky130_fd_pr__pfet_01v8_BKC9WK_2
+timestamp 1645182413
+transform 1 0 -307 0 1 362
+box -109 -114 109 148
+use sky130_fd_pr__nfet_01v8_ALRCN6 sky130_fd_pr__nfet_01v8_ALRCN6_2
+timestamp 1645180687
+transform 1 0 -305 0 1 97
+box -73 -99 73 99
+<< labels >>
+flabel metal1 1668 118 1868 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 768 1328 968 1528 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 920 -698 1120 -498 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li.ext
new file mode 100755
index 0000000..26aa1b7
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li.ext
@@ -0,0 +1,420 @@
+timestamp 1645540046
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_9P8X3X XM23 1 0 1049 0 1 681
+use sky130_fd_pr__pfet_01v8_V5LP55 XM12 1 0 633 0 1 701
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM9 1 0 -102 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM10 1 0 105 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM10 1 0 312 0 1 897
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 314 0 1 381
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3 1 0 -103 0 1 362
+use sky130_fd_pr__pfet_01v8_BKC9WK XM5 1 0 97 0 1 362
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -926 0 1 1033
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -720 0 1 1033
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 -514 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 -308 0 1 897
+use sky130_fd_pr__pfet_01v8_BKC9WK XM1 1 0 -307 0 1 362
+use sky130_fd_pr__nfet_01v8_Q665WF XM24 1 0 940 0 1 -97
+use sky130_fd_pr__nfet_01v8_86PVFD XM13 1 0 621 0 1 -88
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM8 1 0 316 0 1 -391
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 306 0 1 105
+use sky130_fd_pr__nfet_01v8_26QSQN XM8 1 0 110 0 1 -391
+use sky130_fd_pr__nfet_01v8_26QSQN XM7 1 0 -96 0 1 -393
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 1 0 -304 0 1 -397
+use sky130_fd_pr__nfet_01v8_LS29AB XM2 1 0 -306 0 1 106
+use sky130_fd_pr__nfet_01v8_LS29AB XM4 1 0 -102 0 1 105
+use sky130_fd_pr__nfet_01v8_LS29AB XM6 1 0 104 0 1 105
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -717 0 1 -540
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16 1 0 -510 0 1 -397
+use sky130_fd_pr__nfet_01v8_CJ56PH XMDUM26 1 0 -923 0 1 -509
+port "vctrl" 3 -1386 -752 -1186 -552 m1
+port "out" 2 1544 118 1744 318 m1
+port "vdd" 0 768 1542 968 1742 m1
+port "vss" 1 798 -1174 998 -974 m1
+node "vctrl" 5 1450.9 -1386 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58320 1892 91600 3150 0 0 0 0 0 0 0 0
+node "out" 5 897.372 1544 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104560 4028 0 0 0 0 0 0 0 0 0 0
+node "m1_554_n2#" 8 927.774 554 -2 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104148 5328 0 0 0 0 0 0 0 0 0 0
+node "m1_n964_n380#" 0 114.315 -964 -380 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4300 272 0 0 0 0 0 0 0 0 0 0
+node "m1_n784_n440#" 9 424.444 -784 -440 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81424 4222 49952 1896 0 0 0 0 0 0 0 0
+node "vdd" 8 795.911 768 1542 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 882842 14804 0 0 0 0 0 0 0 0 0 0
+node "vss" 22 7908.08 798 -1174 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 946776 17316 0 0 0 0 0 0 0 0 0 0
+node "li_39_10#" 13 317.625 39 10 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 8536 496 0 0 0 0 0 0 0 0 0 0
+node "li_n167_10#" 13 318.408 -167 10 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 8479 498 0 0 0 0 0 0 0 0 0 0
+node "li_337_51#" 18 891.588 337 51 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 91958 4376 0 0 0 0 0 0 0 0 0 0
+node "li_n371_6#" 29 344.419 -371 6 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2652 224 8428 496 0 0 0 0 0 0 0 0 0 0
+node "li_n341_207#" 264 793.23 -341 207 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20036 1372 31364 1750 0 0 0 0 0 0 0 0 0 0
+node "li_n76_366#" 219 349.289 -76 366 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21090 1298 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n280_366#" 220 317.938 -280 366 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21296 1308 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_36_432#" 13 -27.88 36 432 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 16262 884 0 0 0 0 0 0 0 0 0 0
+node "li_n164_432#" 13 -27.88 -164 432 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 16102 876 0 0 0 0 0 0 0 0 0 0
+node "li_n368_432#" 13 -27.88 -368 432 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 16022 872 0 0 0 0 0 0 0 0 0 0
+node "w_n1130_242#" 19436 8685.3 -1130 242 nw 0 0 0 0 2895100 7450 0 0 134708 7992 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134708 7992 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "w_n1130_n834#" 0 0 -1130 -834 pw 2819120 7392 0 0 0 0 0 0 0 0 142596 8456 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 142806 8496 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n164_432#" "li_n167_10#" 9.22196
+cap "out" "vss" 137.551
+cap "m1_n964_n380#" "m1_n784_n440#" 23.9362
+cap "li_337_51#" "w_n1130_242#" 532.835
+cap "m1_554_n2#" "li_337_51#" 491.768
+cap "m1_n784_n440#" "li_n368_432#" 46.6832
+cap "li_n341_207#" "li_n167_10#" 16.9108
+cap "vss" "li_n341_207#" 21.5132
+cap "li_n76_366#" "li_n341_207#" 229.844
+cap "li_39_10#" "li_337_51#" 4.125
+cap "vdd" "li_36_432#" 88.9224
+cap "li_n76_366#" "w_n1130_242#" 157.3
+cap "m1_554_n2#" "vss" 575.054
+cap "m1_n964_n380#" "vss" 38.2249
+cap "li_n164_432#" "li_36_432#" 117.367
+cap "li_39_10#" "li_n167_10#" 59.1058
+cap "li_n371_6#" "li_n341_207#" 9.79169
+cap "li_39_10#" "vss" 68.5415
+cap "li_n76_366#" "li_39_10#" 10.2
+cap "out" "vdd" 43.8679
+cap "vdd" "li_n164_432#" 41.8112
+cap "li_n341_207#" "li_36_432#" 13.6517
+cap "vctrl" "m1_n784_n440#" 2.41935
+cap "li_36_432#" "w_n1130_242#" 288.242
+cap "li_39_10#" "li_n371_6#" 25.7397
+cap "vdd" "li_n341_207#" 10.4097
+cap "li_n371_6#" "li_n368_432#" 9.4544
+cap "li_n280_366#" "li_n167_10#" 5.47934
+cap "vdd" "w_n1130_242#" 3514.77
+cap "m1_554_n2#" "vdd" 694.694
+cap "li_n280_366#" "li_n76_366#" 165.24
+cap "li_39_10#" "li_36_432#" 8.89
+cap "li_n341_207#" "li_n164_432#" 13.6517
+cap "li_36_432#" "li_n368_432#" 50.7445
+cap "m1_n784_n440#" "vss" 158.901
+cap "out" "w_n1130_242#" 331.712
+cap "vctrl" "vss" 1658.75
+cap "li_n164_432#" "w_n1130_242#" 286.498
+cap "vss" "li_337_51#" 424.204
+cap "m1_554_n2#" "out" 165.479
+cap "li_n76_366#" "li_337_51#" 1.26923
+cap "li_n280_366#" "li_n371_6#" 6.3871
+cap "li_n341_207#" "w_n1130_242#" 234.333
+cap "m1_n784_n440#" "li_n371_6#" 22.9681
+cap "li_n164_432#" "li_n368_432#" 112.774
+cap "vss" "li_n167_10#" 39.4438
+cap "m1_554_n2#" "w_n1130_242#" 682.342
+cap "m1_n784_n440#" "li_36_432#" 0.272727
+cap "li_39_10#" "li_n341_207#" 16.8387
+cap "li_36_432#" "li_337_51#" 5.71154
+cap "li_n341_207#" "li_n368_432#" 8.74818
+cap "m1_n784_n440#" "vdd" 1604.46
+cap "li_n368_432#" "w_n1130_242#" 285.626
+cap "li_n371_6#" "li_n167_10#" 59.6554
+cap "vss" "li_n371_6#" 42.9981
+cap "li_n76_366#" "li_n371_6#" 1.48872
+cap "vdd" "li_337_51#" 623.624
+cap "li_n280_366#" "li_n164_432#" 8.56489
+cap "m1_n784_n440#" "li_n164_432#" 0.54878
+cap "li_n76_366#" "li_36_432#" 5.40164
+cap "li_n280_366#" "li_n341_207#" 211.171
+cap "m1_n784_n440#" "li_n341_207#" 5.29412
+cap "li_n280_366#" "w_n1130_242#" 178.026
+cap "m1_n784_n440#" "w_n1130_242#" 1034.92
+cap "li_n341_207#" "li_337_51#" 50.3207
+cap "XM6/a_n73_n68#" "XM4/a_n73_n68#" 81.8725
+cap "XM6/a_n33_33#" "XM13/w_n211_n330#" 46.01
+cap "XM2/a_n73_n68#" "XM1/a_n73_n14#" 0.543952
+cap "XM6/a_15_n68#" "XM1/w_n109_n114#" 1.59211
+cap "XM6/a_n33_33#" "XM22/a_15_n68#" 2.90158
+cap "XM6/a_n73_n68#" "XM4/a_n33_33#" 4.75872
+cap "XM6/a_15_n68#" "XMDUM26/a_n33_n188#" 0.119134
+cap "XM6/a_15_n68#" "XM11/a_n76_n276#" 0.0421995
+cap "XM13/w_n211_n330#" "XM26/a_n33_n157#" 753.59
+cap "XM6/a_n33_33#" "XMDUM26/a_n33_n188#" 11.9785
+cap "XM4/a_n73_n68#" "XM13/w_n211_n330#" 341.085
+cap "XM26/a_n33_n157#" "XM26/a_n76_n69#" 1.24001
+cap "XM2/a_n73_n68#" "XM6/a_n73_n68#" 36.4031
+cap "XM6/a_15_n68#" "XM6/a_n33_33#" 2.4056
+cap "XM4/a_n33_33#" "XM13/w_n211_n330#" 249.177
+cap "XM26/a_n33_n157#" "XMDUM26/a_n33_n188#" 173.218
+cap "XM6/a_15_n68#" "XM26/a_n33_n157#" 8.20549
+cap "XM4/a_n73_n68#" "XMDUM26/a_n33_n188#" 490.64
+cap "XM4/a_n73_n68#" "XM6/a_15_n68#" 5.45945
+cap "XM4/a_n33_33#" "XM1/w_n109_n114#" 1.58746
+cap "XM4/a_n73_n68#" "XM6/a_n33_33#" -7.10543e-15
+cap "XM4/a_n33_33#" "XMDUM26/a_n33_n188#" 7.06251
+cap "XM2/a_n73_n68#" "XM13/w_n211_n330#" 314.967
+cap "XM4/a_n33_33#" "XM6/a_15_n68#" 43.4324
+cap "XM2/a_n73_n68#" "XM26/a_n76_n69#" 42.784
+cap "XM3/a_n73_n14#" "XM13/w_n211_n330#" 1.42386
+cap "XM4/a_n73_n68#" "XM26/a_n33_n157#" 1.47516
+cap "XM2/a_n73_n68#" "XMDUM26/a_n33_n188#" 597.62
+cap "XM4/a_n33_33#" "XM6/a_n33_33#" 33.831
+cap "XM6/a_15_n68#" "XM11/a_n33_235#" 1.06154
+cap "XM2/a_n73_n68#" "XM6/a_15_n68#" 0.267257
+cap "XM1/a_n73_n14#" "XM13/w_n211_n330#" 1.42386
+cap "XM2/a_n73_n68#" "XM6/a_n33_33#" 8.04912
+cap "XM4/a_n33_33#" "XM26/a_n33_n157#" 8.16593
+cap "XM4/a_n33_33#" "XM9/a_n33_235#" 1.05882
+cap "XM4/a_n33_33#" "XM4/a_n73_n68#" 53.0071
+cap "XM2/a_n73_n68#" "XM26/a_n33_n157#" 1.83755
+cap "XM2/a_n73_n68#" "XM4/a_n73_n68#" 161.743
+cap "XM1/a_n73_n14#" "XM6/a_15_n68#" 0.0377601
+cap "XM4/a_n73_n68#" "XM3/a_n73_n14#" 0.687583
+cap "XM2/a_n73_n68#" "XM4/a_n33_33#" -6.3871
+cap "XM6/a_n73_n68#" "XMDUM26/a_n33_n188#" 165.821
+cap "XM6/a_n73_n68#" "XM6/a_n33_33#" 24.1204
+cap "XM13/w_n211_n330#" "XM26/a_n76_n69#" 166.843
+cap "XM13/w_n211_n330#" "XMDUM26/a_n33_n188#" 1693.05
+cap "XM6/a_15_n68#" "XM13/w_n211_n330#" 234.109
+cap "XM26/a_n76_n69#" "XMDUM26/a_n33_n188#" 302.755
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+merge "XM6/a_n33_33#" "li_n76_366#"
+merge "XM23/a_n33_251#" "XM12/a_15_n240#" -547.336 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -151538 -1202 0 0 0 0 0 0 0 0 0 0
+merge "XM12/a_15_n240#" "XM23/a_63_n317#"
+merge "XM23/a_63_n317#" "XM23/a_n129_n317#"
+merge "XM23/a_n129_n317#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "m1_554_n2#"
+merge "XM11/a_n76_n276#" "XM1/a_n73_n14#" -85.0393 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 13244 -162 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_n73_n14#" "li_n368_432#"
+merge "XM8/a_n76_n209#" "XM6/a_n73_n68#" -375.507 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -81 -86 -14 -82 0 0 0 0 0 0 0 0 0 0
+merge "XM6/a_n73_n68#" "li_39_10#"
+merge "XM7/a_n76_n209#" "XM4/a_n73_n68#" -374.008 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1017 -86 100 -82 0 0 0 0 0 0 0 0 0 0
+merge "XM4/a_n73_n68#" "li_n167_10#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.ext
new file mode 100755
index 0000000..23be5db
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.ext
@@ -0,0 +1,367 @@
+timestamp 1645552146
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_LS29AB XM2 0 -1 -425 1 0 101
+use sky130_fd_pr__nfet_01v8_CJ56PH XMDUM26 1 0 -923 0 1 -509
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16 1 0 -510 0 1 -397
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -717 0 1 -540
+use sky130_fd_pr__nfet_01v8_LS29AB XM6 0 -1 83 1 0 101
+use sky130_fd_pr__nfet_01v8_LS29AB XM4 0 -1 -177 1 0 101
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 1 0 -304 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM7 1 0 -96 0 1 -393
+use sky130_fd_pr__nfet_01v8_26QSQN XM8 1 0 110 0 1 -391
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 670 0 1 -89
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 306 0 1 105
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM8 1 0 316 0 1 -391
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 940 0 1 -90
+use sky130_fd_pr__pfet_01v8_BKC9WK XM1 0 1 -430 -1 0 351
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 -308 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 -514 0 1 897
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -720 0 1 1033
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -926 0 1 1033
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3 0 1 -164 -1 0 351
+use sky130_fd_pr__pfet_01v8_BKC9WK XM5 0 1 101 -1 0 351
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 314 0 1 381
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM10 1 0 312 0 1 897
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM10 1 0 105 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM9 1 0 -102 0 1 897
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 658 0 1 699
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1049 0 1 684
+port "vctrl" 3 -1386 -752 -1186 -552 m1
+port "out" 2 1544 118 1744 318 m1
+port "vdd" 0 768 1542 968 1742 m1
+port "vss" 1 798 -1174 998 -974 m1
+node "vctrl" 5 3111 -1386 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58320 1892 91600 3150 0 0 0 0 0 0 0 0
+node "out" 5 948.226 1544 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104560 4028 0 0 0 0 0 0 0 0 0 0
+node "m1_n964_n380#" 0 152.54 -964 -380 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4300 272 0 0 0 0 0 0 0 0 0 0
+node "m1_n784_n440#" 9 583.345 -784 -440 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81424 4222 49952 1896 0 0 0 0 0 0 0 0
+node "li_77_10#" 13 418.709 77 10 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 9836 546 0 0 0 0 0 0 0 0 0 0
+node "li_n167_10#" 13 357.851 -167 10 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 8479 498 0 0 0 0 0 0 0 0 0 0
+node "li_n389_6#" 13 376.775 -389 6 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 9118 526 0 0 0 0 0 0 0 0 0 0
+node "li_685_596#" 743 915.205 685 596 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96748 4936 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n107_132#" 136 293.3 -107 132 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12886 826 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n144_145#" 52 103.016 -144 145 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n410_155#" 52 94.1473 -410 155 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n525_68#" 285 950.288 -525 68 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26300 1628 25614 1538 0 0 0 0 0 0 0 0 0 0
+node "li_n370_290#" 135 185.195 -370 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12784 820 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_105_412#" 14 -27.88 105 412 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 20745 1046 0 0 0 0 0 0 0 0 0 0
+node "li_n159_412#" 13 -27.88 -159 412 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 17547 926 0 0 0 0 0 0 0 0 0 0
+node "li_n394_411#" 13 -27.88 -394 411 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 19240 970 0 0 0 0 0 0 0 0 0 0
+node "li_337_51#" 643 1493.81 337 51 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71001 3940 31930 1254 0 0 0 0 0 0 0 0 0 0
+node "vdd" 23385 9514.89 768 1542 m1 0 0 0 0 2895100 7450 0 0 171496 10088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 171496 10088 883358 14776 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 798 -1174 m1 2819120 7392 0 0 0 0 0 0 0 0 169592 9976 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170748 10112 955546 16914 0 0 0 0 0 0 0 0 0 0
+cap "li_n144_145#" "li_n159_412#" 5.13934
+cap "li_105_412#" "m1_n784_n440#" 0.272727
+cap "li_n394_411#" "li_n410_155#" 5.35135
+cap "li_n525_68#" "li_n159_412#" 16.8038
+cap "li_n159_412#" "vdd" 335.469
+cap "li_337_51#" "li_105_412#" 15.463
+cap "li_n389_6#" "li_n394_411#" 11.8136
+cap "li_n394_411#" "li_n525_68#" 22.649
+cap "li_n394_411#" "vdd" 303.592
+cap "li_n389_6#" "m1_n784_n440#" 23.269
+cap "li_n525_68#" "m1_n784_n440#" 10
+cap "vctrl" "m1_n784_n440#" 2.41935
+cap "li_n167_10#" "li_n159_412#" 9.42321
+cap "vdd" "m1_n784_n440#" 2639.38
+cap "li_n394_411#" "li_n370_290#" 3.7931
+cap "li_685_596#" "li_337_51#" 246.434
+cap "li_77_10#" "li_337_51#" 4.90099
+cap "li_n525_68#" "li_337_51#" 16.9286
+cap "li_337_51#" "vdd" 1284.87
+cap "li_77_10#" "li_105_412#" 11.3017
+cap "li_n107_132#" "li_337_51#" 1.88889
+cap "li_n144_145#" "li_n410_155#" 19.2026
+cap "li_n525_68#" "li_105_412#" 39.1261
+cap "li_105_412#" "vdd" 413.768
+cap "li_n394_411#" "li_n159_412#" 117.023
+cap "li_n389_6#" "li_n410_155#" 3.73043
+cap "li_n525_68#" "li_n410_155#" 94.3287
+cap "li_n159_412#" "m1_n784_n440#" 0.54878
+cap "li_n410_155#" "vdd" 37.4312
+cap "li_n410_155#" "li_n370_290#" 93.4052
+cap "li_n389_6#" "li_77_10#" 22.5
+cap "li_n144_145#" "li_n525_68#" 78.547
+cap "li_n144_145#" "vdd" 32.8152
+cap "li_685_596#" "vdd" 755.418
+cap "li_n394_411#" "m1_n784_n440#" 50.7819
+cap "li_77_10#" "li_n525_68#" 24.316
+cap "li_n389_6#" "li_n525_68#" 20.4037
+cap "li_n107_132#" "li_n410_155#" 12.9254
+cap "out" "vdd" 375.58
+cap "li_n144_145#" "li_n370_290#" 58.3537
+cap "li_n525_68#" "vdd" 211.993
+cap "li_n389_6#" "li_n370_290#" 1.98
+cap "li_n525_68#" "li_n370_290#" 93.0243
+cap "vdd" "li_n370_290#" 119.375
+cap "li_n159_412#" "li_105_412#" 121.197
+cap "m1_n964_n380#" "m1_n784_n440#" 23.9362
+cap "li_n144_145#" "li_n107_132#" 266.276
+cap "li_n167_10#" "li_n144_145#" 3.59406
+cap "li_n167_10#" "li_77_10#" 56.7024
+cap "li_n107_132#" "li_n525_68#" 132.101
+cap "li_n389_6#" "li_n167_10#" 58.0362
+cap "li_n107_132#" "vdd" 63.4953
+cap "li_n167_10#" "li_n525_68#" 16.9108
+cap "li_n107_132#" "li_n370_290#" 42.4286
+cap "li_n394_411#" "li_105_412#" 49.9724
+cap "XMDUM26/a_n33_n188#" "XM26/a_n33_n157#" 926.809
+cap "XM26/a_n76_n69#" "XM26/a_n33_n157#" 1.24001
+cap "XM2/a_15_n68#" "XM1/a_n73_n14#" 0.885161
+cap "XM2/a_n33_33#" "XM2/a_15_n68#" 32.6768
+cap "XM2/a_n33_33#" "XM6/a_n33_33#" 2.80958
+cap "XMDUM26/a_n33_n188#" "XM6/a_n73_n68#" 165.821
+cap "XM6/a_n33_33#" "XM3/a_n73_n14#" 0.805082
+cap "XM2/a_n73_n68#" "XM1/a_n73_n14#" 2.24596
+cap "XM4/a_n73_n68#" "XM26/a_n33_n157#" 1.47516
+cap "XM2/a_n33_33#" "XM2/a_n73_n68#" 0.771429
+cap "XMDUM26/a_n33_n188#" "XM2/a_15_n68#" 242.423
+cap "XMDUM26/a_n33_n188#" "XM6/a_n33_33#" 25.9475
+cap "XM2/a_n73_n68#" "XMDUM26/a_n33_n188#" 971.682
+cap "XM2/a_n73_n68#" "XM26/a_n76_n69#" 42.784
+cap "XM4/a_n73_n68#" "XM6/a_n73_n68#" 77.8655
+cap "XM1/w_n109_n114#" "XM2/a_15_n68#" 0.0592859
+cap "XM4/a_n73_n68#" "XM6/a_n33_33#" 2.93576
+cap "XM1/w_n109_n114#" "XM6/a_n33_33#" -0.373501
+cap "XM2/a_n33_33#" "XMDUM26/a_n33_n188#" 237.437
+cap "XM2/a_n73_n68#" "XM4/a_n73_n68#" 154.559
+cap "XM22/a_15_n68#" "XM6/a_n33_33#" -0.0510836
+cap "XM26/a_n33_n157#" "XM2/a_15_n68#" 3.91758
+cap "XMDUM26/a_n33_n188#" "XM26/a_n76_n69#" 469.598
+cap "XM2/a_n33_33#" "XM1/w_n109_n114#" 0.706549
+cap "XM2/a_n33_33#" "XM4/a_n73_n68#" 1.00715
+cap "XM2/a_n73_n68#" "XM26/a_n33_n157#" 1.83755
+cap "XM4/a_n73_n68#" "XM3/a_n73_n14#" 1.67352
+cap "XM6/a_n73_n68#" "XM2/a_15_n68#" 0.108911
+cap "XMDUM26/a_n33_n188#" "XM4/a_n73_n68#" 848.406
+cap "XM6/a_n33_33#" "XM2/a_15_n68#" 25.9263
+cap "XM2/a_n73_n68#" "XM6/a_n73_n68#" 33.4629
+cap "XM2/a_n73_n68#" "XM2/a_15_n68#" 0.438278
+cap "XM2/a_n73_n68#" "XM6/a_n33_33#" 0.185915
+cap "XM3/w_n109_n114#" "XM6/a_n33_33#" -1.40656
+cap "XM6/a_n73_n68#" "XM2/a_15_n68#" 0.108911
+cap "XM2/a_15_n68#" "XM6/a_n33_33#" -1.16003
+cap "XM16/a_18_n209#" "XM4/a_n73_n68#" 73.2463
+cap "XM6/a_15_n68#" "XMDUM10/a_n33_235#" 1.05882
+cap "XM16/a_18_n209#" "XM6/a_15_n68#" 268.057
+cap "XM23/a_n173_n220#" "XM13/a_15_n120#" 1.63557
+cap "XM24/a_18_n129#" "XM16/a_18_n209#" 165.226
+cap "XM6/a_n73_n68#" "XM6/a_n33_33#" 0.2489
+cap "XM6/a_15_n68#" "XMDUM10/a_n76_n276#" 1.05499
+cap "XM6/a_15_n68#" "XM13/a_n33_n208#" 2.3956
+cap "XM6/a_n73_n68#" "XM16/a_n33_n297#" 0.011162
+cap "XM10/a_18_n276#" "XM6/a_15_n68#" 0.589286
+cap "XM6/a_15_n68#" "XM21/a_n73_n22#" 2.55814
+cap "XM6/a_n73_n68#" "XM16/a_18_n209#" 849.594
+cap "XM16/a_18_n209#" "XM6/a_n33_33#" 191.449
+cap "XM12/a_n73_n240#" "XM13/a_n33_n208#" 1.20226
+cap "XM6/a_15_n68#" "XM5/a_n73_n14#" 2.98213
+cap "XM13/a_15_n120#" "XM16/a_18_n209#" 766.697
+cap "XM6/a_n73_n68#" "XM13/a_n33_n208#" 9.34329
+cap "XM16/a_18_n209#" "XM16/a_n33_n297#" 296.4
+cap "XM6/a_n33_33#" "XM13/a_n33_n208#" 2.88889
+cap "XM13/a_15_n120#" "XM13/a_n33_n208#" 70.9421
+cap "XM6/a_n73_n68#" "XM2/a_n73_n68#" 33.4629
+cap "XM6/a_n73_n68#" "XM5/a_n73_n14#" 2.30241
+cap "XM6/a_n33_33#" "XM2/a_n73_n68#" 0.0894309
+cap "XM16/a_18_n209#" "XM13/a_n33_n208#" 650.119
+cap "XM3/w_n109_n114#" "XM6/a_15_n68#" 2.99925
+cap "XM2/a_15_n68#" "XM6/a_15_n68#" 0.459793
+cap "XM6/a_n73_n68#" "XM4/a_n73_n68#" 77.8655
+cap "XM6/a_n33_33#" "XM4/a_n73_n68#" 0.272727
+cap "XM6/a_n73_n68#" "XM6/a_15_n68#" 2.38408
+cap "XM6/a_15_n68#" "XM6/a_n33_33#" 16.3192
+cap "XM24/a_18_n129#" "XM13/a_15_n120#" 106.704
+cap "XM16/a_18_n209#" "XM21/a_n73_n22#" 5.62637
+cap "XM2/a_n73_n68#" "XM1/a_n73_n14#" 2.24596
+cap "XM3/a_n73_n14#" "XM11/a_n33_235#" -0.482172
+cap "XM1/a_n73_n14#" "XM11/a_n33_235#" 38.0734
+cap "XM3/a_n73_n14#" "XM4/a_n73_n68#" 1.67352
+cap "XM5/a_n73_n14#" "XM2/a_15_n68#" 0.3
+cap "XM1/w_n109_n114#" "XM5/a_n73_n14#" 219.962
+cap "XM6/a_n33_33#" "XM2/a_n33_33#" 10.4337
+cap "XM21/a_15_n22#" "XM6/a_n33_33#" 1.4633
+cap "XM3/a_n73_n14#" "XM5/a_n73_n14#" 71.7777
+cap "XM1/a_n73_n14#" "XM5/a_n73_n14#" 31.1981
+cap "vss" "XM6/a_n33_33#" -14.4883
+cap "XM2/a_15_n68#" "XM2/a_n33_33#" 31.8417
+cap "XM1/w_n109_n114#" "XM2/a_n33_33#" -0.284284
+cap "XM3/a_n73_n14#" "XM2/a_n33_33#" 0.598187
+cap "XM6/a_n33_33#" "XM1/w_n109_n114#" -5.44312
+cap "XM2/a_n73_n68#" "XM2/a_n33_33#" 0.365854
+cap "XM6/a_n33_33#" "XM2/a_15_n68#" 40.8782
+cap "vss" "XM2/a_15_n68#" -31.1081
+cap "XM11/a_n33_235#" "XM2/a_n33_33#" 0.803493
+cap "XM4/a_n73_n68#" "XM2/a_n33_33#" 0.369863
+cap "XM1/a_n73_n14#" "XM6/a_n33_33#" 0.540984
+cap "XM3/a_n73_n14#" "XM6/a_n33_33#" 2.48481
+cap "XM1/w_n109_n114#" "XM2/a_15_n68#" -45.9239
+cap "XM6/a_n33_33#" "XM4/a_n73_n68#" 0.427747
+cap "XM3/a_n73_n14#" "XM1/w_n109_n114#" 582.857
+cap "XM1/a_n73_n14#" "XM1/w_n109_n114#" 616.647
+cap "XM1/a_n73_n14#" "XM2/a_15_n68#" -0.864141
+cap "XM2/a_n73_n68#" "XM2/a_15_n68#" 0.631774
+cap "XM1/w_n109_n114#" "XM11/a_n33_235#" 391.059
+cap "XM3/a_n73_n14#" "XM1/a_n73_n14#" 145.53
+cap "XM6/a_n73_n68#" "XM5/a_n73_n14#" 2.30241
+cap "XM2/a_15_n68#" "XM6/a_n33_33#" 4.68363
+cap "XM13/a_n33_n208#" "XM6/a_15_n68#" 1.36667
+cap "XM24/a_n33_n217#" "XM11/a_18_n276#" 558.768
+cap "XM22/a_n73_n68#" "XM6/a_15_n68#" 2.7349
+cap "XM6/a_15_n68#" "XMDUM8/a_18_n209#" 0.0418782
+cap "XM2/a_15_n68#" "XM6/a_15_n68#" 0.882293
+cap "XM13/a_n33_n208#" "XM5/a_n73_n14#" 15.5871
+cap "XM3/a_n73_n14#" "XM5/a_n73_n14#" 71.7777
+cap "XM13/a_n33_n208#" "XM13/a_n73_n120#" 0.827434
+cap "vss" "XM11/a_18_n276#" 1.46475
+cap "XM5/a_n73_n14#" "XM6/a_15_n68#" -0.501112
+cap "XM2/a_15_n68#" "XM5/a_n73_n14#" 0.3
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diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.mag
new file mode 100755
index 0000000..97b28b6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.mag
@@ -0,0 +1,412 @@
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+rect -684 1137 -334 1193
+rect -278 1137 -130 1193
+rect -74 1137 76 1193
+rect 76 1131 132 1137
+rect -742 -632 -680 -626
+rect -338 -628 -282 -622
+rect -128 -628 -72 -622
+rect -344 -632 -338 -628
+rect -1333 -694 -1327 -632
+rect -1265 -694 -742 -632
+rect -680 -684 -338 -632
+rect -282 -684 -128 -628
+rect -72 -684 84 -628
+rect 140 -684 146 -628
+rect -680 -694 -235 -684
+rect -128 -690 -72 -684
+rect -742 -700 -680 -694
+use sky130_fd_pr__nfet_01v8_LS29AB XM2
+timestamp 1645537996
+transform 0 -1 -425 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_CJ56PH XMDUM26
+timestamp 1645532764
+transform 1 0 -923 0 1 -509
+box -76 -188 76 188
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16
+timestamp 1645187587
+transform 1 0 -510 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -717 0 1 -540
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_LS29AB XM6
+timestamp 1645537996
+transform 0 -1 83 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_LS29AB XM4
+timestamp 1645537996
+transform 0 -1 -177 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform 1 0 -304 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM7
+timestamp 1645187587
+transform 1 0 -96 0 1 -393
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM8
+timestamp 1645187587
+transform 1 0 110 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645550823
+transform 1 0 670 0 1 -89
+box -73 -208 73 208
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 306 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM8
+timestamp 1645187587
+transform 1 0 316 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 940 0 1 -90
+box -76 -217 76 217
+use sky130_fd_pr__pfet_01v8_BKC9WK XM1
+timestamp 1645537996
+transform 0 1 -430 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 -308 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 -514 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -720 0 1 1033
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -926 0 1 1033
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3
+timestamp 1645537996
+transform 0 1 -164 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_BKC9WK XM5
+timestamp 1645537996
+transform 0 1 101 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645543725
+transform 1 0 314 0 1 381
+box -109 -122 109 156
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM10
+timestamp 1645187069
+transform 1 0 312 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM10
+timestamp 1645187069
+transform 1 0 105 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM9
+timestamp 1645187069
+transform 1 0 -102 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645550202
+transform 1 0 658 0 1 699
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1049 0 1 684
+box -209 -320 209 320
+<< labels >>
+flabel metal1 1544 118 1744 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+rlabel metal1 -1386 -752 -1186 -552 1 vctrl
+port 3 n
+flabel metal1 798 -1174 998 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 768 1542 968 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.spice
new file mode 100755
index 0000000..de8d7bb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp5_li_v2.spice
@@ -0,0 +1,271 @@
+* NGSPICE file created from 3-stage_cs-vco_dp5_li_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n78_n220# a_n173_n220# 0.31fF
+C1 a_n33_251# a_63_n317# 0.02fF
+C2 w_n209_n320# a_n173_n220# 0.28fF
+C3 a_n78_n220# a_n33_251# 0.00fF
+C4 w_n209_n320# a_63_n317# 0.14fF
+C5 a_114_n220# a_n173_n220# 0.07fF
+C6 a_18_n220# a_n173_n220# 0.14fF
+C7 w_n209_n320# a_n78_n220# 0.33fF
+C8 w_n209_n320# a_n33_251# 0.14fF
+C9 a_114_n220# a_63_n317# 0.00fF
+C10 a_18_n220# a_63_n317# 0.00fF
+C11 a_n78_n220# a_114_n220# 0.18fF
+C12 a_18_n220# a_n78_n220# 0.31fF
+C13 a_18_n220# a_n33_251# 0.00fF
+C14 w_n209_n320# a_114_n220# 0.33fF
+C15 a_18_n220# w_n209_n320# 0.28fF
+C16 a_n173_n220# a_n129_n317# 0.00fF
+C17 a_18_n220# a_114_n220# 0.31fF
+C18 a_63_n317# a_n129_n317# 0.03fF
+C19 a_n78_n220# a_n129_n317# 0.00fF
+C20 a_n33_251# a_n129_n317# 0.02fF
+C21 w_n209_n320# a_n129_n317# 0.14fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_15_n240# a_n73_n240# 0.20fF
+C1 a_15_n240# a_n33_n337# 0.01fF
+C2 a_n73_n240# w_n109_n340# 0.31fF
+C3 a_n33_n337# w_n109_n340# 0.24fF
+C4 a_15_n240# w_n109_n340# 0.17fF
+C5 a_n73_n240# a_n33_n337# 0.01fF
+C6 a_15_n240# VSUBS -0.16fF
+C7 a_n73_n240# VSUBS -0.32fF
+C8 a_n33_n337# VSUBS -0.03fF
+C9 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n136# a_n76_n136# 0.20fF
+C1 a_18_n136# a_n33_95# 0.00fF
+C2 a_n76_n136# w_n112_n198# 0.16fF
+C3 a_n33_95# w_n112_n198# 0.19fF
+C4 a_18_n136# w_n112_n198# 0.16fF
+C5 a_n76_n136# a_n33_95# 0.00fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_18_n129# a_n33_n217# 0.01fF
+C1 a_n76_n129# a_n33_n217# 0.01fF
+C2 a_18_n129# a_n76_n129# 0.21fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_n208# VSUBS
+X0 a_15_n120# a_n33_n208# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_15_n120# a_n33_n208# 0.01fF
+C1 a_n73_n120# a_n33_n208# 0.01fF
+C2 a_15_n120# a_n73_n120# 0.15fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.00fF
+C5 a_n33_n208# VSUBS 0.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n69# a_n33_n157# 0.01fF
+C1 a_n76_n69# a_n33_n157# 0.00fF
+C2 a_18_n69# a_n76_n69# 0.17fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n33_n297# 0.00fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_18_n209# a_n76_n209# 0.35fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n276# a_n76_n276# 0.46fF
+C1 a_18_n276# a_n33_235# 0.00fF
+C2 a_n76_n276# w_n112_n338# 0.32fF
+C3 a_n33_235# w_n112_n338# 0.19fF
+C4 a_18_n276# w_n112_n338# 0.32fF
+C5 a_n76_n276# a_n33_235# 0.00fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n14# a_n73_n14# 0.04fF
+C1 a_15_n14# a_n33_n111# 0.00fF
+C2 a_n73_n14# w_n109_n114# 0.04fF
+C3 a_n33_n111# w_n109_n114# 0.14fF
+C4 a_15_n14# w_n109_n114# 0.04fF
+C5 a_n73_n14# a_n33_n111# 0.00fF
+C6 a_15_n14# VSUBS -0.04fF
+C7 a_n73_n14# VSUBS -0.04fF
+C8 a_n33_n111# VSUBS -0.01fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CJ56PH a_n76_n100# a_n33_n188# a_18_n100# VSUBS
+X0 a_18_n100# a_n33_n188# a_n76_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n100# a_n33_n188# 0.01fF
+C1 a_n76_n100# a_n33_n188# 0.01fF
+C2 a_18_n100# a_n76_n100# 0.17fF
+C3 a_18_n100# VSUBS 0.00fF
+C4 a_n76_n100# VSUBS 0.00fF
+C5 a_n33_n188# VSUBS 0.18fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_15_n68# a_n33_33# 0.00fF
+C1 a_n73_n68# a_n33_33# 0.00fF
+C2 a_15_n68# a_n73_n68# 0.04fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122#
++ VSUBS
+X0 a_15_n22# a_n33_n119# a_n73_n22# w_n109_n122# sky130_fd_pr__pfet_01v8 ad=1.682e+11p pd=1.74e+06u as=1.682e+11p ps=1.74e+06u w=580000u l=150000u
+C0 a_15_n22# a_n73_n22# 0.13fF
+C1 a_15_n22# a_n33_n119# 0.00fF
+C2 a_n73_n22# w_n109_n122# 0.11fF
+C3 a_n33_n119# w_n109_n122# 0.14fF
+C4 a_15_n22# w_n109_n122# 0.11fF
+C5 a_n73_n22# a_n33_n119# 0.00fF
+C6 a_15_n22# VSUBS -0.10fF
+C7 a_n73_n22# VSUBS -0.11fF
+C8 a_n33_n119# VSUBS -0.01fF
+C9 w_n109_n122# VSUBS 0.18fF
+.ends
+
+.subckt x3-stage_cs-vco_dp5 vdd vss out vctrl
+XXM23 vdd vdd out vdd li_685_596# li_685_596# li_685_596# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 li_685_596# vdd vdd li_337_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM25 vdd m1_n784_n440# vdd m1_n784_n440# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM24 li_685_596# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss li_685_596# li_337_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM26 m1_n784_n440# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 li_n389_6# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM10 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 li_n394_411# li_n525_68# vdd li_n410_155# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_CJ56PH
+XXM2 li_n525_68# li_n389_6# li_n410_155# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM3 li_n159_412# li_n410_155# vdd li_n144_145# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 li_n410_155# li_n167_10# li_n144_145# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 li_105_412# li_n144_145# vdd li_n525_68# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXMDUM8 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM6 li_n144_145# li_77_10# li_n525_68# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM7 li_n167_10# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM9 vdd vdd m1_n784_n440# li_n159_412# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM8 li_77_10# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM10 vdd vdd m1_n784_n440# li_105_412# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 li_337_51# li_n525_68# vdd vdd vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11 vdd vdd m1_n784_n440# li_n394_411# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 li_n525_68# vss li_337_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+C0 li_685_596# vdd 1.32fF
+C1 li_n389_6# vctrl 0.00fF
+C2 li_105_412# li_n410_155# 0.00fF
+C3 li_105_412# li_77_10# 0.02fF
+C4 li_337_51# vdd 1.94fF
+C5 li_337_51# li_n144_145# 0.01fF
+C6 li_337_51# li_105_412# 0.03fF
+C7 li_n144_145# li_n389_6# 0.00fF
+C8 out vdd 0.66fF
+C9 li_n525_68# li_n167_10# 0.02fF
+C10 vdd li_n144_145# 0.08fF
+C11 vdd li_n159_412# 1.00fF
+C12 li_n144_145# li_n159_412# 0.01fF
+C13 vdd li_105_412# 1.18fF
+C14 li_77_10# li_n167_10# 0.21fF
+C15 li_105_412# li_n159_412# 0.26fF
+C16 li_n525_68# li_n394_411# 0.02fF
+C17 m1_n784_n440# li_n394_411# 0.09fF
+C18 li_n525_68# m1_n784_n440# 0.01fF
+C19 vctrl li_n167_10# 0.00fF
+C20 li_n389_6# li_n167_10# 0.21fF
+C21 li_n394_411# li_n410_155# 0.01fF
+C22 li_n525_68# li_n410_155# 0.25fF
+C23 li_n525_68# li_77_10# 0.03fF
+C24 li_n144_145# li_n167_10# 0.01fF
+C25 li_n159_412# li_n167_10# 0.01fF
+C26 li_n525_68# li_337_51# 0.02fF
+C27 li_77_10# li_n410_155# 0.00fF
+C28 m1_n784_n440# vctrl 0.00fF
+C29 li_n394_411# li_n389_6# 0.02fF
+C30 li_n525_68# li_n389_6# 0.02fF
+C31 m1_n784_n440# li_n389_6# 0.07fF
+C32 li_337_51# li_77_10# 0.01fF
+C33 vdd li_n394_411# 0.92fF
+C34 li_n410_155# vctrl 0.00fF
+C35 li_77_10# vctrl 0.00fF
+C36 li_n394_411# li_n144_145# 0.00fF
+C37 li_n525_68# vdd 0.20fF
+C38 m1_n784_n440# vdd 3.04fF
+C39 li_685_596# li_337_51# 0.43fF
+C40 li_n525_68# li_n144_145# 0.25fF
+C41 li_n394_411# li_n159_412# 0.26fF
+C42 li_n389_6# li_n410_155# 0.01fF
+C43 li_77_10# li_n389_6# 0.09fF
+C44 li_n525_68# li_n159_412# 0.02fF
+C45 m1_n784_n440# li_n159_412# 0.00fF
+C46 li_n394_411# li_105_412# 0.11fF
+C47 li_n525_68# li_105_412# 0.04fF
+C48 m1_n784_n440# li_105_412# 0.00fF
+C49 vdd li_n410_155# 0.11fF
+C50 out li_685_596# 0.41fF
+C51 li_n144_145# li_n410_155# 0.20fF
+C52 li_n144_145# li_77_10# 0.00fF
+C53 li_337_51# vss 1.89fF
+C54 li_77_10# vss 1.11fF
+C55 li_n144_145# vss 0.50fF
+C56 li_105_412# vss -0.48fF
+C57 li_n167_10# vss 0.95fF
+C58 li_n159_412# vss -0.45fF
+C59 li_n410_155# vss 0.39fF
+C60 li_n389_6# vss 1.12fF
+C61 li_n525_68# vss 1.35fF
+C62 li_n394_411# vss -0.77fF
+C63 vdd vss 11.56fF
+C64 m1_n784_n440# vss 0.44fF
+C65 vctrl vss 4.00fF
+C66 li_685_596# vss 1.38fF
+C67 out vss 0.13fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.ext
new file mode 100755
index 0000000..fea910f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.ext
@@ -0,0 +1,366 @@
+timestamp 1645796186
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -363 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -157 0 1 -537
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 50 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 -1 0 256 0 1 -397
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -391
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1356 0 1 -4
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -187 1 0 101
+use sky130_fd_pr__pfet_01v8_BT7HXK XM1 0 1 -215 -1 0 351
+use sky130_fd_pr__nfet_01v8_LS29AB XM4 0 -1 83 1 0 101
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3 0 1 101 -1 0 351
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 49 0 1 899
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 256 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1 1 0 350 0 1 898
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_FYZURS XM5 0 -1 517 1 0 351
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 886 0 1 105
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 597
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -366 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -160 0 1 1039
+port "vctrl" 3 -826 -752 -626 -552 m1
+port "out" 2 1849 118 2049 318 m1
+port "vdd" 0 1172 1542 1372 1742 m1
+port "vss" 1 1202 -1174 1402 -974 m1
+node "vctrl" 6 2630.33 -826 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61400 1964 59232 2984 0 0 0 0 0 0 0 0
+node "out" 3 727.503 1849 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 88560 3228 0 0 0 0 0 0 0 0 0 0
+node "m1_n457_n334#" 5 920.182 -457 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85514 3810 0 0 0 0 0 0 0 0 0 0
+node "m1_n230_1050#" 5 -312.83 -230 1050 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27610 1394 35424 1808 0 0 0 0 0 0 0 0
+node "li_528_n678#" 55 209.787 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_n678#" 57 216.793 223 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 119 377.338 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11254 730 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n210_7#" 41 2379.78 -210 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 51612 2186 0 0 0 0 0 0 0 0 0 0
+node "li_1213_134#" 52 151.34 1213 134 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_917_51#" 207 373.634 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 410.13 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n360_106#" 204 985.475 -360 106 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14450 1036 27470 1650 0 0 0 0 0 0 0 0 0 0
+node "li_132_290#" 193 324.181 132 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17943 1134 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n112_286#" 178 308.593 -112 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16898 1062 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_338#" 172 52.2552 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16286 1026 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n267_410#" 53 -27.88 -267 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 65032 2816 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 141 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13362 854 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 -11.48 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_1149#" 57 -11.48 223 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_16_1150#" 24 0 16 1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 108.297 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_n694#" 114 108.297 289 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 61.7185 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_1133#" 114 4.8972 289 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 22168 8650.33 1172 1542 m1 0 0 0 0 2613265 6942 0 0 160990 9470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 188700 11304 925487 18900 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 1202 -1174 m1 2547045 6886 0 0 0 0 0 0 0 0 160412 9436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 171700 10304 985732 20050 0 0 0 0 0 0 0 0 0 0
+cap "li_n210_7#" "m1_n457_n334#" 44.1353
+cap "a_589_1133#" "a_289_1133#" 5.58088
+cap "vdd" "li_1179_338#" 198.559
+cap "li_1213_134#" "li_611_133#" 4.49096
+cap "li_1179_338#" "li_917_51#" 32.2616
+cap "li_611_133#" "a_879_204#" 11.55
+cap "vdd" "a_589_1133#" 51.7
+cap "m1_n230_1050#" "m1_n457_n334#" 29.1549
+cap "a_590_n694#" "vctrl" 42.185
+cap "li_n267_410#" "m1_n457_n334#" 61.7541
+cap "vdd" "li_611_133#" 94.682
+cap "li_917_51#" "li_611_133#" 28.2715
+cap "li_223_n678#" "vctrl" 130.927
+cap "li_n112_286#" "li_132_290#" 50.6002
+cap "li_16_1150#" "vdd" 116.501
+cap "li_611_133#" "li_n360_106#" 25.3289
+cap "li_223_1149#" "li_16_1150#" 7.7234
+cap "vdd" "li_1179_712#" 286.665
+cap "a_590_n694#" "li_528_n678#" 25.2972
+cap "m1_n230_1050#" "a_289_1133#" 35.605
+cap "li_n210_7#" "li_n360_106#" 120.432
+cap "vdd" "m1_n230_1050#" 2196.83
+cap "li_223_1149#" "m1_n230_1050#" 122.556
+cap "li_1179_338#" "li_1179_712#" 3.3
+cap "li_223_n678#" "li_528_n678#" 7.73793
+cap "vdd" "li_n267_410#" 1775.85
+cap "vdd" "li_n112_286#" 136.956
+cap "m1_n230_1050#" "a_589_1133#" 35.605
+cap "li_n267_410#" "li_n360_106#" 123.51
+cap "li_n112_286#" "li_n360_106#" 79.617
+cap "a_289_n694#" "vctrl" 42.185
+cap "vctrl" "m1_n457_n334#" 2.925
+cap "vdd" "li_523_1149#" 163.88
+cap "li_223_1149#" "li_523_1149#" 8.01429
+cap "li_1213_134#" "li_1179_n70#" 15.4737
+cap "li_16_1150#" "m1_n230_1050#" 22
+cap "li_523_1149#" "a_589_1133#" 25.2972
+cap "vdd" "m1_n457_n334#" 565.999
+cap "vdd" "li_132_290#" 166.115
+cap "li_n210_7#" "li_n267_410#" 27.8642
+cap "li_n360_106#" "m1_n457_n334#" 53.0769
+cap "li_n210_7#" "li_n112_286#" 3.16013
+cap "li_917_51#" "li_1179_n70#" 0.798387
+cap "li_132_290#" "li_n360_106#" 171.146
+cap "li_917_51#" "li_1213_134#" 12.6752
+cap "vdd" "a_879_204#" 11
+cap "m1_n230_1050#" "li_n267_410#" 11.0106
+cap "vdd" "out" 311.915
+cap "li_1179_338#" "li_1179_n70#" 10.1455
+cap "li_528_n678#" "vctrl" 103.249
+cap "li_1179_338#" "li_1213_134#" 37.5411
+cap "vdd" "a_289_1133#" 51.7
+cap "a_590_n694#" "a_289_n694#" 5.56044
+cap "vdd" "li_917_51#" 126.227
+cap "li_223_1149#" "a_289_1133#" 25.2972
+cap "li_223_1149#" "vdd" 160.213
+cap "li_611_133#" "li_132_290#" 19.0555
+cap "li_523_1149#" "m1_n230_1050#" 124.538
+cap "vdd" "li_n360_106#" 210.51
+cap "li_223_n678#" "a_289_n694#" 25.2972
+cap "XM16B_1/a_n76_n209#" "XM1/a_n73_n64#" 3.73718
+cap "XM22/a_15_n68#" "XMDUM26/a_n76_n69#" 0.048105
+cap "XM1/a_n73_n64#" "XM2/a_n33_63#" 1.09798
+cap "XM4/a_15_n68#" "XM26/a_n33_n157#" 3.82892
+cap "XMDUM26/a_n76_n69#" "XM4/a_15_n68#" 201.059
+cap "XM16B_1/a_n76_n209#" "XM26/a_n33_n157#" 80.8016
+cap "XM16B_1/a_n76_n209#" "XMDUM26/a_n76_n69#" 918.745
+cap "XMDUM26/a_n76_n69#" "XM2/a_n33_63#" 351.778
+cap "XM4/a_15_n68#" "XM2/a_15_n103#" 30.9976
+cap "XM16B_1/a_n76_n209#" "XM2/a_15_n103#" 8.97523
+cap "XM2/a_15_n103#" "XM2/a_n33_63#" 34.9625
+cap "XM3/a_n73_n14#" "XM4/a_15_n68#" 3.63271
+cap "XM4/a_15_n68#" "XM1/w_n109_n164#" 3.60186
+cap "XMDUM26/a_n76_n69#" "XM26/a_n33_n157#" 524.749
+cap "XM3/a_n73_n14#" "XM2/a_n33_63#" 14.5903
+cap "XM2/a_15_n103#" "XM1/a_n73_n64#" 11.5347
+cap "XM1/w_n109_n164#" "XM2/a_n33_63#" 8.63425
+cap "XMDUM26/a_n76_n69#" "XM2/a_15_n103#" 273.212
+cap "XM26/a_n76_n69#" "XM26/a_n33_n157#" 0.734364
+cap "XMDUM26/a_n76_n69#" "XM26/a_n76_n69#" 533.409
+cap "XM3/a_n73_n14#" "XMDUM26/a_n76_n69#" 4.35662
+cap "XM16B_1/a_n76_n209#" "XM4/a_15_n68#" 5.2212
+cap "XM4/a_15_n68#" "XM2/a_n33_63#" -0.414227
+cap "XM1/w_n109_n164#" "XM2/a_15_n103#" 5.37945
+cap "XM16B_1/a_n76_n209#" "XM6/a_15_n175#" 4.41732
+cap "XM16B_1/a_n76_n209#" "XM16B_1/a_n33_n297#" -61.7246
+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 60.3698
+cap "XM21/a_n72_n22#" "XM16B_1/a_18_n209#" 5.57731
+cap "XM16B_1/a_n76_n209#" "XM16B_1/a_18_n209#" 825.254
+cap "XM5/a_15_n236#" "XM6/a_15_n175#" 2.78408
+cap "XM6/a_n33_135#" "XM6/a_15_n175#" -0.99603
+cap "XMDUM11B/a_n33_235#" "XM6/a_15_n175#" 0.676471
+cap "XM16B_1/a_18_n209#" "XM5/a_15_n236#" 1.28206
+cap "XM6/a_n33_135#" "XM16B_1/a_n33_n297#" 3.21505
+cap "XM16B_1/a_18_n209#" "XM24/a_18_n129#" 246.158
+cap "XM6/a_n33_135#" "XM16B_1/a_18_n209#" 47.167
+cap "XM13/a_15_n120#" "XM6/a_15_n175#" 0.444378
+cap "XM12/a_n73_n240#" "XM16B_1/a_18_n209#" 7.62219
+cap "XM13/a_15_n120#" "XM16B_1/a_18_n209#" 620.764
+cap "XM11B_1/w_n112_n338#" "XM6/a_15_n175#" -0.166742
+cap "XM13/a_15_n120#" "XM23/a_n173_n220#" 3.1875
+cap "XM13/a_n33_142#" "XM24/a_18_n129#" 5.15315
+cap "XM16B_1/a_18_n209#" "XM6/a_15_n175#" 211.694
+cap "XM13/a_n33_142#" "XM12/a_n73_n240#" -2.56667
+cap "XM16B_1/a_18_n209#" "XM16B_1/a_n33_n297#" -11.9129
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 28.1783
+cap "XM16B_1/a_18_n209#" "XM23/a_n173_n220#" 2.29918
+cap "XM13/a_n33_142#" "XM6/a_15_n175#" 6.9818
+cap "XM13/a_n33_142#" "XM16B_1/a_18_n209#" 243.429
+cap "XM21/a_n72_n22#" "XM6/a_15_n175#" 8.01429
+cap "XM1/w_n109_n164#" "XM21/a_15_n22#" 1.22222
+cap "XM2/a_n33_63#" "XM1/a_n73_n64#" 1.09798
+cap "XM4/a_n73_n68#" "XM4/a_15_n68#" 2.19146
+cap "XM16B_1/a_n76_n209#" "XM1/a_n73_n64#" 3.73718
+cap "XM2/a_n33_63#" "vss" 10.0366
+cap "XM4/a_n73_n68#" "XM1/w_n109_n164#" 4.35662
+cap "XM1/a_n73_n64#" "XM4/a_15_n68#" 3.23597
+cap "XM2/a_n33_63#" "XM4/a_15_n68#" 9.10597
+cap "XM2/a_n33_63#" "XM1/w_n109_n164#" 34.1417
+cap "XM1/a_n73_n64#" "XM1/w_n109_n164#" 255.814
+cap "vss" "XM4/a_15_n68#" 1.40094
+cap "XM1/a_n73_n64#" "XM11B_1/a_n33_235#" 74.0844
+cap "XM2/a_15_n103#" "XM1/a_n73_n64#" 12.3495
+cap "XM2/a_15_n103#" "XM2/a_n33_63#" 47.6859
+cap "XM4/a_15_n68#" "XM1/w_n109_n164#" -45.2743
+cap "XM4/a_15_n68#" "XM11B_1/a_n33_235#" 4.05283
+cap "XM2/a_15_n103#" "XM16B_1/a_n76_n209#" 10.021
+cap "XM2/a_15_n103#" "vss" 8.98567
+cap "XM2/a_15_n103#" "XM4/a_15_n68#" 29.3183
+cap "XM1/w_n109_n164#" "XM11B_1/a_n33_235#" 147.023
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diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.mag
new file mode 100755
index 0000000..8a4fb16
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.mag
@@ -0,0 +1,446 @@
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+rect 161 -50 751 -19
+rect -120 -125 627 -79
+rect 280 -153 326 -125
+rect 581 -152 627 -125
+rect -457 -334 -181 -288
+rect -227 -423 -181 -334
+rect -826 -635 -626 -552
+rect -826 -687 -762 -635
+rect -710 -687 -626 -635
+rect -826 -752 -626 -687
+rect -430 -724 -390 -457
+rect -336 -724 -296 -457
+rect -130 -553 -49 -457
+rect -194 -635 -114 -623
+rect -194 -687 -183 -635
+rect -131 -687 -114 -635
+rect -194 -691 -114 -687
+rect -183 -693 -131 -691
+rect -86 -724 -49 -553
+rect -16 -724 24 -191
+rect 76 -724 116 -191
+rect 158 -610 227 -169
+rect 158 -724 198 -610
+rect 278 -635 330 -629
+rect 227 -684 278 -638
+rect 330 -684 379 -638
+rect 278 -693 330 -687
+rect 418 -724 487 -263
+rect 681 -602 751 -50
+rect 822 -55 862 0
+rect 1426 -10 1743 30
+rect 578 -635 630 -629
+rect 528 -684 578 -638
+rect 630 -684 680 -638
+rect 578 -693 630 -687
+rect 711 -724 751 -602
+rect 786 -94 930 -55
+rect 786 -632 826 -94
+rect 890 -632 930 -94
+rect 1086 -342 1128 -47
+rect 1288 -342 1328 -63
+rect 1086 -344 1652 -342
+rect 786 -678 930 -632
+rect 786 -724 826 -678
+rect 890 -724 930 -678
+rect 973 -411 1652 -344
+rect 973 -663 989 -411
+rect 1023 -663 1652 -411
+rect 973 -724 1652 -663
+rect -569 -747 1755 -724
+rect -569 -781 -529 -747
+rect 894 -781 1755 -747
+rect -569 -872 1755 -781
+rect 1202 -1174 1402 -872
+<< via1 >>
+rect -186 1141 -134 1193
+rect 277 1141 329 1193
+rect 578 1141 630 1193
+rect -762 -687 -710 -635
+rect -183 -687 -131 -635
+rect 278 -687 330 -635
+rect 578 -687 630 -635
+<< metal2 >>
+rect -192 1141 -186 1193
+rect -134 1187 -128 1193
+rect 271 1187 277 1193
+rect -134 1147 277 1187
+rect -134 1141 -128 1147
+rect 271 1141 277 1147
+rect 329 1187 335 1193
+rect 572 1187 578 1193
+rect 329 1147 578 1187
+rect 329 1141 335 1147
+rect 572 1141 578 1147
+rect 630 1141 636 1193
+rect -768 -687 -762 -635
+rect -710 -641 -704 -635
+rect -189 -641 -183 -635
+rect -710 -681 -183 -641
+rect -710 -687 -704 -681
+rect -189 -687 -183 -681
+rect -131 -641 -125 -635
+rect 272 -641 278 -635
+rect -131 -681 278 -641
+rect -131 -687 -125 -681
+rect 272 -687 278 -681
+rect 330 -641 336 -635
+rect 572 -641 578 -635
+rect 330 -681 578 -641
+rect 330 -687 336 -681
+rect 572 -687 578 -681
+rect 630 -687 636 -635
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -363 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -157 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -187 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_BT7HXK XM1
+timestamp 1645723234
+transform 0 1 -215 -1 0 351
+box -109 -164 109 198
+use sky130_fd_pr__nfet_01v8_LS29AB XM4
+timestamp 1645537996
+transform 0 -1 83 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3
+timestamp 1645537996
+transform 0 1 101 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_FYZURS XM5
+timestamp 1645722298
+transform 0 -1 517 1 0 351
+box -109 -298 109 264
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -366 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -160 0 1 1039
+box -112 -198 112 164
+<< labels >>
+rlabel metal1 -826 -752 -626 -552 1 vctrl
+port 3 n
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.spice
new file mode 100755
index 0000000..7d3e0a0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7.spice
@@ -0,0 +1,302 @@
+* NGSPICE file created from 3-stage_cs-vco_dp7.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_18_n220# a_114_n220# 0.31fF
+C1 a_114_n220# a_63_n317# 0.00fF
+C2 a_n78_n220# w_n209_n320# 0.33fF
+C3 a_n129_n317# a_63_n317# 0.03fF
+C4 a_18_n220# a_n173_n220# 0.14fF
+C5 a_18_n220# a_n33_251# 0.00fF
+C6 a_n33_251# a_63_n317# 0.02fF
+C7 a_114_n220# a_n173_n220# 0.07fF
+C8 a_n129_n317# a_n173_n220# 0.00fF
+C9 a_n129_n317# a_n33_251# 0.02fF
+C10 a_18_n220# a_n78_n220# 0.31fF
+C11 a_n78_n220# a_114_n220# 0.18fF
+C12 a_n78_n220# a_n129_n317# 0.00fF
+C13 a_n78_n220# a_n173_n220# 0.31fF
+C14 a_18_n220# w_n209_n320# 0.28fF
+C15 w_n209_n320# a_63_n317# 0.14fF
+C16 a_n78_n220# a_n33_251# 0.00fF
+C17 w_n209_n320# a_114_n220# 0.33fF
+C18 w_n209_n320# a_n129_n317# 0.14fF
+C19 w_n209_n320# a_n173_n220# 0.28fF
+C20 w_n209_n320# a_n33_251# 0.14fF
+C21 a_18_n220# a_63_n317# 0.00fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 w_n109_n340# a_n33_n337# 0.11fF
+C1 w_n109_n340# a_n73_n240# 0.19fF
+C2 a_15_n240# w_n109_n340# 0.17fF
+C3 a_15_n240# a_n73_n240# 0.20fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 w_n112_n198# a_n33_95# 0.19fF
+C1 a_n76_n136# a_n33_95# 0.00fF
+C2 w_n112_n198# a_n76_n136# 0.16fF
+C3 a_18_n136# a_n33_95# 0.00fF
+C4 a_18_n136# w_n112_n198# 0.16fF
+C5 a_18_n136# a_n76_n136# 0.20fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n33_n217# a_n76_n129# 0.01fF
+C1 a_18_n129# a_n76_n129# 0.21fF
+C2 a_n33_n217# a_18_n129# 0.01fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n33_142# a_n73_n120# 0.01fF
+C1 a_15_n120# a_n73_n120# 0.15fF
+C2 a_n33_142# a_15_n120# 0.00fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n33_n157# a_n76_n69# 0.00fF
+C1 a_18_n69# a_n76_n69# 0.17fF
+C2 a_n33_n157# a_18_n69# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n33_n297# a_n76_n209# 0.00fF
+C1 a_18_n209# a_n76_n209# 0.35fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 w_n112_n338# a_n33_235# 0.19fF
+C1 a_n76_n276# a_n33_235# 0.00fF
+C2 w_n112_n338# a_n76_n276# 0.32fF
+C3 a_18_n276# a_n33_235# 0.00fF
+C4 a_18_n276# w_n112_n338# 0.32fF
+C5 a_18_n276# a_n76_n276# 0.46fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BT7HXK a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+C0 w_n109_n164# a_n33_n161# 0.14fF
+C1 a_n73_n64# a_n33_n161# 0.00fF
+C2 w_n109_n164# a_n73_n64# 0.10fF
+C3 a_15_n64# a_n33_n161# 0.00fF
+C4 a_15_n64# w_n109_n164# 0.10fF
+C5 a_15_n64# a_n73_n64# 0.11fF
+C6 a_15_n64# VSUBS -0.08fF
+C7 a_n73_n64# VSUBS -0.08fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n33_n297# a_n76_n209# 0.00fF
+C1 a_18_n209# a_n76_n209# 0.47fF
+C2 a_n33_n297# a_18_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_n33_63# a_n73_n103# 0.00fF
+C1 a_15_n103# a_n73_n103# 0.07fF
+C2 a_n33_63# a_15_n103# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 w_n109_n114# a_n33_n111# 0.14fF
+C1 a_n73_n14# a_n33_n111# 0.00fF
+C2 w_n109_n114# a_n73_n14# 0.04fF
+C3 a_15_n14# a_n33_n111# 0.00fF
+C4 a_15_n14# w_n109_n114# 0.04fF
+C5 a_15_n14# a_n73_n14# 0.04fF
+C6 a_15_n14# VSUBS -0.04fF
+C7 a_n73_n14# VSUBS -0.04fF
+C8 a_n33_n111# VSUBS -0.01fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n33_33# a_n73_n68# 0.00fF
+C1 a_15_n68# a_n73_n68# 0.04fF
+C2 a_n33_33# a_15_n68# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_FYZURS a_n33_195# a_n73_n236# w_n109_n298# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_195# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=150000u
+C0 w_n109_n298# a_n33_195# 0.14fF
+C1 a_n73_n236# a_n33_195# 0.00fF
+C2 w_n109_n298# a_n73_n236# 0.18fF
+C3 a_15_n236# a_n33_195# 0.00fF
+C4 a_15_n236# w_n109_n298# 0.18fF
+C5 a_15_n236# a_n73_n236# 0.22fF
+C6 a_15_n236# VSUBS -0.16fF
+C7 a_n73_n236# VSUBS -0.16fF
+C8 a_n33_195# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.37fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_n33_135# a_n73_n175# 0.00fF
+C1 a_15_n175# a_n73_n175# 0.16fF
+C2 a_n33_135# a_15_n175# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 w_n109_n58# a_n15_n53# 0.05fF
+C1 w_n109_n58# a_n72_n22# 0.14fF
+C2 a_15_n22# w_n109_n58# 0.08fF
+C3 a_15_n22# a_n72_n22# 0.09fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt x3-stage_cs-vco_dp7 vdd vss out vctrl
+XXM23 vdd vdd out vdd li_1213_134# li_1213_134# li_1213_134# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 li_1213_134# vdd vdd li_917_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM25 vdd a_589_1133# vdd a_589_1133# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM24 li_1213_134# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss li_1213_134# li_917_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM26 a_589_1133# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 li_n210_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM16_1 li_n210_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B_1 li_n210_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 li_n267_410# a_879_204# vdd li_n112_286# vss sky130_fd_pr__pfet_01v8_BT7HXK
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM2 li_n210_7# li_n112_286# a_879_204# vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd li_n112_286# vdd li_132_290# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 li_n112_286# vss li_132_290# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 li_132_290# a_879_204# vdd vdd vss sky130_fd_pr__pfet_01v8_FYZURS
+XXM6 li_132_290# a_879_204# vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXM11B_1 vdd vdd a_589_1133# li_n267_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B li_n210_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11_1 vdd vdd a_589_1133# li_n267_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 vdd li_917_51# vdd a_879_204# vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11B li_n267_410# vdd a_589_1133# vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 a_879_204# vss li_917_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 li_n267_410# vdd a_589_1133# vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 vdd li_1213_134# 0.88fF
+C1 vdd li_132_290# 0.13fF
+C2 li_n210_7# li_n112_286# 0.02fF
+C3 vss vdd 0.04fF
+C4 li_917_51# a_879_204# 0.05fF
+C5 li_n112_286# a_879_204# 0.16fF
+C6 a_589_1133# li_n267_410# 0.08fF
+C7 vdd a_879_204# 0.39fF
+C8 a_589_1133# li_132_290# 0.00fF
+C9 vss a_589_1133# 0.53fF
+C10 li_n210_7# a_589_1133# 0.04fF
+C11 li_132_290# vctrl 0.01fF
+C12 a_589_1133# a_879_204# 0.05fF
+C13 vdd li_917_51# 0.14fF
+C14 vss vctrl 0.51fF
+C15 vdd li_n112_286# 0.14fF
+C16 li_n210_7# vctrl 0.02fF
+C17 vdd a_589_1133# 3.21fF
+C18 li_n267_410# li_132_290# 0.00fF
+C19 out li_1213_134# 0.27fF
+C20 vss out 0.25fF
+C21 li_n210_7# li_n267_410# 0.04fF
+C22 vss li_1213_134# 0.61fF
+C23 li_n267_410# a_879_204# 0.13fF
+C24 vss li_132_290# 0.25fF
+C25 li_1213_134# a_879_204# 0.00fF
+C26 li_n210_7# li_132_290# 0.01fF
+C27 vss li_n210_7# 1.74fF
+C28 a_879_204# li_132_290# 0.20fF
+C29 a_589_1133# vctrl 0.00fF
+C30 vss a_879_204# 0.58fF
+C31 li_n112_286# li_n267_410# 0.02fF
+C32 li_n210_7# a_879_204# 0.12fF
+C33 li_917_51# out 0.01fF
+C34 li_917_51# li_1213_134# 0.11fF
+C35 vdd li_n267_410# 2.14fF
+C36 li_917_51# li_132_290# 0.00fF
+C37 li_n112_286# li_132_290# 0.11fF
+C38 vdd out 0.56fF
+C39 vss li_917_51# 0.29fF
+C40 vss li_n112_286# 0.28fF
+C41 vctrl 0 3.09fF
+C42 li_1213_134# 0 0.23fF
+C43 a_589_1133# 0 0.22fF
+C44 li_917_51# 0 0.21fF
+C45 li_132_290# 0 0.23fF
+C46 li_n112_286# 0 0.12fF
+C47 a_879_204# 0 1.16fF
+C48 vss 0 -3.63fF
+C49 li_n267_410# 0 -0.69fF
+C50 vdd 0 11.29fF
+C51 li_n210_7# 0 1.42fF
+C52 out 0 -0.17fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_-_seccopy_25-2-2022_14y01.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_-_seccopy_25-2-2022_14y01.mag
new file mode 100755
index 0000000..d886b77
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_-_seccopy_25-2-2022_14y01.mag
@@ -0,0 +1,444 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645793411
+<< error_s >>
+rect 67 86 79 116
+rect 151 86 163 116
+rect 871 109 901 121
+rect 871 25 901 37
+<< nwell >>
+rect -570 243 1795 1347
+rect -570 242 -278 243
+rect -218 242 1795 243
+<< pwell >>
+rect -570 241 -278 242
+rect -218 241 1795 242
+rect -570 -835 1795 241
+<< psubdiff >>
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+rect -529 -747 -495 -647
+rect 989 -747 1023 -663
+rect -529 -781 -492 -747
+rect 894 -781 1023 -747
+<< nsubdiff >>
+rect -531 1252 -458 1286
+rect 930 1252 1023 1286
+rect -531 1226 -497 1252
+rect -531 565 -497 572
+rect 989 565 1023 1252
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+rect -531 278 -497 531
+<< psubdiffcont >>
+rect -529 -62 894 -28
+rect -529 -647 -495 -136
+rect 989 -663 1023 -411
+rect -492 -781 894 -747
+<< nsubdiffcont >>
+rect -458 1252 930 1286
+rect -531 572 -497 1226
+rect -458 531 930 565
+<< poly >>
+rect 289 1133 317 1199
+rect 589 1133 617 1199
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+rect 590 -694 618 -628
+<< locali >>
+rect -531 1252 -458 1286
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+rect -529 -747 -495 -647
+rect 223 -678 383 -644
+rect 528 -678 680 -644
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+rect 894 -781 1023 -747
+<< viali >>
+rect -458 1252 930 1286
+rect -267 410 -128 444
+rect 137 412 171 446
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+rect -360 207 -326 241
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+rect -529 -781 -492 -747
+rect -492 -781 894 -747
+<< metal1 >>
+rect 1172 1443 1372 1742
+rect -510 1442 1372 1443
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+rect -569 -781 -529 -747
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+rect 1202 -1174 1402 -872
+<< via1 >>
+rect -186 1141 -134 1193
+rect 277 1141 329 1193
+rect 578 1141 630 1193
+rect -762 -687 -710 -635
+rect -183 -687 -131 -635
+rect 278 -687 330 -635
+rect 578 -687 630 -635
+<< metal2 >>
+rect -192 1141 -186 1193
+rect -134 1187 -128 1193
+rect 271 1187 277 1193
+rect -134 1147 277 1187
+rect -134 1141 -128 1147
+rect 271 1141 277 1147
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+rect -710 -641 -704 -635
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+rect -710 -687 -704 -681
+rect -189 -687 -183 -681
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+rect -131 -687 -125 -681
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+rect 572 -641 578 -635
+rect 330 -681 578 -641
+rect 330 -687 336 -681
+rect 572 -687 578 -681
+rect 630 -687 636 -635
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -363 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -157 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -187 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_BT7HXK XM1
+timestamp 1645723234
+transform 0 1 -215 -1 0 351
+box -109 -164 109 198
+use sky130_fd_pr__nfet_01v8_LS29AB XM4
+timestamp 1645537996
+transform 0 -1 83 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3
+timestamp 1645537996
+transform 0 1 101 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_FYZURS XM5
+timestamp 1645722298
+transform 0 -1 517 1 0 351
+box -109 -298 109 264
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645791712
+transform 1 0 894 0 1 381
+box -109 -122 109 156
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -366 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -160 0 1 1039
+box -112 -198 112 164
+<< labels >>
+rlabel metal1 -826 -752 -626 -552 1 vctrl
+port 3 n
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..b4ec08e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb.log
@@ -0,0 +1,2361 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.82703e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.32034e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 6.069309e-06 at= 1.000500e-08
+vlow_outside_while = -6.047239e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.21165e-05
+supply_current_rms = 5.31205e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.24525e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 9.08057e-06 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.392334e-07 at= 1.000500e-08
+vlow_outside_while = -1.217968e-07 at= 1.998500e-08
+peak_to_peak_outside_while= 2.61030e-07
+supply_current_rms = 5.10645e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.06262e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.19881e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 5.055944e-06 at= 1.000500e-08
+vlow_outside_while = -5.032939e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.00889e-05
+supply_current_rms = 5.33067e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.51097e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.33524e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.025890e-06 at= 1.000500e-08
+vlow_outside_while = -3.008855e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 6.03475e-06
+supply_current_rms = 5.93341e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.88578e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.26002e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.091754e-06 at= 1.000500e-08
+vlow_outside_while = -2.073792e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 4.16555e-06
+supply_current_rms = 5.14649e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 8.40097e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.59100e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.909158e+00 at= 1.778500e-08
+vlow_outside_while = -7.737419e-02 at= 1.768500e-08
+peak_to_peak_outside_while= 1.98653e+00
+supply_current_rms = 9.36485e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.39740e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.09785e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925105e+00 at= 1.185500e-08
+vlow_outside_while = -7.576951e-02 at= 1.084500e-08
+peak_to_peak_outside_while= 2.00087e+00
+supply_current_rms = 1.13992e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 4.050321e-10 targ= 2.099878e-08 trig= 2.059375e-08
+fvco_outside_while = 2.46894e+09
+supply_current_rms_outside_while= 2.72852e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.86298e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928871e+00 at= 1.273500e-08
+vlow_outside_while = -7.913834e-02 at= 1.084500e-08
+peak_to_peak_outside_while= 2.00801e+00
+supply_current_rms = 2.73012e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.861045e-10 targ= 1.586015e-08 trig= 1.557404e-08
+fvco_outside_while = 3.49523e+09
+supply_current_rms_outside_while= 3.85991e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.81517e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927336e+00 at= 1.855500e-08
+vlow_outside_while = -8.207872e-02 at= 1.669500e-08
+peak_to_peak_outside_while= 2.00941e+00
+supply_current_rms = 3.81693e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.689004e-10 targ= 1.503567e-08 trig= 1.476677e-08
+fvco_outside_while = 3.71885e+09
+supply_current_rms_outside_while= 4.14086e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.13694e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925431e+00 at= 1.836500e-08
+vlow_outside_while = -8.136220e-02 at= 1.178500e-08
+peak_to_peak_outside_while= 2.00679e+00
+supply_current_rms = 4.10064e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.639576e-10 targ= 1.480330e-08 trig= 1.453935e-08
+fvco_outside_while = 3.78849e+09
+supply_current_rms_outside_while= 4.42853e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.40599e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924422e+00 at= 1.305500e-08
+vlow_outside_while = -8.134393e-02 at= 1.451500e-08
+peak_to_peak_outside_while= 2.00577e+00
+supply_current_rms = 4.37730e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.615959e-10 targ= 1.469719e-08 trig= 1.443559e-08
+fvco_outside_while = 3.82269e+09
+supply_current_rms_outside_while= 4.74619e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.68641e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923786e+00 at= 1.950500e-08
+vlow_outside_while = -8.138805e-02 at= 1.964500e-08
+peak_to_peak_outside_while= 2.00517e+00
+supply_current_rms = 4.69329e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.604852e-10 targ= 1.464378e-08 trig= 1.438329e-08
+fvco_outside_while = 3.83899e+09
+supply_current_rms_outside_while= 5.42198e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.91991e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923406e+00 at= 1.239500e-08
+vlow_outside_while = -8.140321e-02 at= 1.253500e-08
+peak_to_peak_outside_while= 2.00481e+00
+supply_current_rms = 5.36757e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.600154e-10 targ= 1.462108e-08 trig= 1.436107e-08
+fvco_outside_while = 3.84593e+09
+supply_current_rms_outside_while= 3.37032e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.19336e-03 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922708e+00 at= 1.003500e-08
+vlow_outside_while = -8.083502e-02 at= 1.017500e-08
+peak_to_peak_outside_while= 2.00354e+00
+supply_current_rms = 5.35448e-03 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.595389e-10 targ= 1.460214e-08 trig= 1.434260e-08
+fvco_outside_while = 3.85299e+09
+supply_current_rms_outside_while= 7.67031e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.74765e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922986e+00 at= 1.729500e-08
+vlow_outside_while = -8.138276e-02 at= 1.717500e-08
+peak_to_peak_outside_while= 2.00437e+00
+supply_current_rms = 7.36851e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.594543e-10 targ= 1.459060e-08 trig= 1.433115e-08
+fvco_outside_while = 3.85424e+09
+supply_current_rms_outside_while= 5.95473e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.28028e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923008e+00 at= 1.520500e-08
+vlow_outside_while = -8.132815e-02 at= 1.041500e-08
+peak_to_peak_outside_while= 2.00434e+00
+supply_current_rms = 5.86964e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.590348e-10 targ= 1.458280e-08 trig= 1.432376e-08
+fvco_outside_while = 3.86048e+09
+supply_current_rms_outside_while= 5.67402e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.24414e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923034e+00 at= 1.208500e-08
+vlow_outside_while = -8.127742e-02 at= 1.585500e-08
+peak_to_peak_outside_while= 2.00431e+00
+supply_current_rms = 5.57819e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.593316e-10 targ= 1.457705e-08 trig= 1.431772e-08
+fvco_outside_while = 3.85607e+09
+supply_current_rms_outside_while= 5.58777e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.24734e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923047e+00 at= 1.052500e-08
+vlow_outside_while = -8.123211e-02 at= 1.999500e-08
+peak_to_peak_outside_while= 2.00428e+00
+supply_current_rms = 5.48928e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15221e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -4.56262e-210
+x2:clk#branch 0
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 3.41127e-05
+vmeas_current_vdd#branch 3.41127e-05
+v2#branch -3.41128e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 3.41127e-05
+x1:vdd#branch -3.41127e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.588883e-10 targ= 1.457167e-08 trig= 1.431278e-08
+fvco_outside_while = 3.86267e+09
+supply_current_rms_outside_while= 5.54318e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.25611e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923054e+00 at= 1.518500e-08
+vlow_outside_while = -8.121322e-02 at= 1.247500e-08
+peak_to_peak_outside_while= 2.00427e+00
+supply_current_rms = 5.43529e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.588883e-10 targ= 1.457167e-08 trig= 1.431278e-08
+Original line no.: 0, new internal line no.: 12503:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.862669028224071e+09 " u=" 3.862669028224071e+09 " id=0
+fvco_outside_while = 3.86267e+09
+supply_current_rms_outside_while= 5.54318e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.25611e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923054e+00 at= 1.518500e-08
+vlow_outside_while = -8.121322e-02 at= 1.247500e-08
+Original line no.: 0, new internal line no.: 12509:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.004267694949307e+00 " u=" 2.004267694949307e+00 " id=0
+peak_to_peak_outside_while= 2.00427e+00
+supply_current_rms = 5.43529e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 8.14383
+
+Total CPU time (seconds) = 167.147
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 1603.668 MB.
+Maximum ngspice program size = 684.789 MB.
+Current ngspice program size = 665.348 MB.
+
+Shared ngspice pages = 8.277 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.309 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb.spice
new file mode 100755
index 0000000..622757e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb.spice
@@ -0,0 +1,483 @@
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/3-stage_cs-vco_tb.sch
+**.subckt 3-stage_cs-vco_tb vctrl out buf16_out
+*.iopin vctrl
+*.iopin out
+*.iopin buf16_out
+
+*POST-LAYOUT DUT:
+x1 net1 net2 out vctrl x3-stage_cs-vco_dp7
+
+V2 vdd GND 1.8
+Vmeas_current_vdd vdd net1 0
+Vmeas_current_gnd net2 GND 0
+x2 vdd out GND fdiv2_loadmodel
+x3 out GND GND vdd vdd buf1_out sky130_fd_sc_hd__clkbuf_1
+x4 buf1_out GND GND vdd vdd net4 sky130_fd_sc_hd__clkbuf_2
+x5 net4 GND GND vdd vdd net5 sky130_fd_sc_hd__clkbuf_4
+x6 net5 GND GND vdd vdd net3 sky130_fd_sc_hd__clkbuf_8
+x7 net3 GND GND vdd vdd buf16_out sky130_fd_sc_hd__clkbuf_16
+**** begin user architecture code
+
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+*V1 vctrl GND 0.9
+V1 vctrl GND pwl(0, 0, 1n, 0, 1.1n, 0.9, 2n, 0.9, 2.1n, {vcontrol_par})
+
+*.options savecurrents
+
+*Trying to get the syntax right for probing M26 and M7 current:
+*POST-LAYOUT current probes:
+ .probe tran all @m.x1.xxm26.x0.msky130_fd_pr__nfet_01v8[id]
+ .save tran all @m.x1.xxm26.x0.msky130_fd_pr__nfet_01v8[id]
+ .probe tran all @m.x1.xxm16.x0.msky130_fd_pr__nfet_01v8[id]
+ .save tran all @m.x1.xxm16.x0.msky130_fd_pr__nfet_01v8[id]
+ .probe tran all @m.x1.xxm16b.x0.msky130_fd_pr__nfet_01v8[id]
+ .save tran all @m.x1.xxm16b.x0.msky130_fd_pr__nfet_01v8[id]
+
+
+
+*Instantiate Ring Osc Parasitic Caps:
+*This worked BUT it gave slightly different Fvco numbers, some gmin convergence.
+*Better to put the parasitic caps inside the VCO subcircuit.
+*Cnet10 x1.net10 x1.vss {paracap}
+*Cnet9 x1.net9 x1.vss {0.686*paracap}
+*Cnet8 x1.net8 x1.vss {0.628*paracap}
+
+
+
+
+.control
+
+
+let do_vctrl_sweep = 1
+let do_dimensions_sweep = 0
+let do_2dimensions_sweep = 0
+let do_paracap_sweep = 0
+
+
+.param vcontrol_par = 0.9
+.param paracap = 2.93f
+
+
+
+*-------------------------------
+*DP5 dimensions:
+.param W_delay_pmos = 0.5
+.param W_delay_nmos = 0.36
+.param M21_W = 0.58
+.param M22_W =0.36
+.param L_of_mirrors = 0.18
+.param W_of_mirrors = 2.4
+.param W_of_input_mirror = 1
+*-------------------------------
+
+*-------------------------------
+*DP6 dimensions:
+.param W_delay_pmos = 0.5
+.param W_delay_nmos = 0.36
+*.param M5_and_M6_multiple = 1
+*Strong M5 M6:
+.param M5_and_M6_multiple = 4
+.param L_of_mirrors = 0.18
+*.param W_of_mirrors = 2.4
+.param W_of_mirrors = 19.2
+.param W_of_input_mirror = 1
+*-------------------------------
+
+
+*-------------------------------
+*DP6 with M5/M6 optimization:
+.param W_delay_pmos = 0.5
+.param W_delay_nmos = 0.36
+*.param M5_and_M6_multiple = 1
+*Strong M5 M6:
+.param M5_and_M6_multiple = 4
+.param L_of_mirrors = 0.18
+.param W_of_mirrors = 2.4
+.param W_of_input_mirror = 1
+.param W_m5 = 0.5
+.param W_m6 = 0.36
+*-------------------------------
+
+
+
+*This is to parameterize transient step/stop/start times
+*using variables:
+set t_start = 0
+set t_step = 10p
+let expected_frequency_vec = 1G
+let nperiods_vec = 70
+let t_stop_vec = nperiods_vec / expected_frequency_vec
+set t_stop = $&t_stop_vec
+
+*-----------------------
+*SEE IF THIS DOESN'T BREAK IT:
+*Trying to sync the params with the variables:
+*Just for the measure statements:
+.param t_start_par = 0
+.param t_step_par = 10p
+.param t_stop_par = 100n
+alterparam t_start_par = $t_start
+alterparam t_step_par = $t_step
+alterparam t_stop_par = $t_stop
+reset
+*-----------------------
+
+
+
+
+if do_vctrl_sweep = 1
+ *-------- WHILE LOOP FOR VCTRL SWEEP-----------------
+ let start_vctrl = 0.0
+ let stop_vctrl = 1.81
+ let increment = 0.1
+ let vctrl_next = start_vctrl
+
+ let debug_1 = 1234
+ let debug_2 = 5678
+
+ let iteration = 1
+
+ while vctrl_next le stop_vctrl
+
+ *alter V1 dc = vctrl_next
+ set vctrl_next_var = $&vctrl_next
+ alterparam vcontrol_par = $vctrl_next_var
+ reset
+
+ *This for fast frequencies:
+ *tran 10ps 100ns
+
+ *This for slow frequencies:
+ *tran 1000ps 100000ns
+
+ *This is using the (set) variables:
+ tran $t_step $t_stop $t_start
+
+ *This is to TRY to parameterize the tran
+ *using the global params BUT it doesn't seem
+ *to work if the tran is inside the .control.
+ *tran 't_step_par' 't_stop_par'
+
+
+ let vctrl_next = vctrl_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_vctrl_sweep = 1
+
+
+
+if do_dimensions_sweep = 1
+ *-------- WHILE LOOP FOR DIMENSIONS SWEEP-----------------
+ let start_w = 1
+ let stop_w = 8.1
+ let increment = 1
+ let w_next = start_w
+ *let w_next_extra_for_the_nmos = 0.36
+
+ let iteration = 1
+
+ while w_next le stop_w
+
+ set w_next_var = $&w_next
+
+
+ *----------------------------
+ *Trying to see if wider delay cell devices can charge parasitic caps better
+ *set w_next_var_extra_for_the_nmos = $&w_next_extra_for_the_nmos
+ *alterparam W_delay_pmos = $w_next_var
+ *alterparam W_delay_nmos = $w_next_var_extra_for_the_nmos
+ *Maybe I should increase the Para Cap when I increase the devices...
+ *The RESET is required after the alterparam (manual says)
+ *reset
+ *----------------------------
+
+ *----------------------------
+ *Trying to see if making M5 and M6 stronger helps
+ alterparam M5_and_M6_multiple = $w_next_var
+ reset
+ *----------------------------
+
+ *alterparam W_delay_pmos = 0.42
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam M21_W = 2.88
+ *alterparam M22_W = 1.44
+ *reset
+
+
+ *alterparam M21_W = $w_next_var
+ *alterparam M22_W = {$w_next_var / 2}
+ *reset
+
+
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+ *alterparam M21_W = 0.58
+ *alterparam M22_W = 0.36
+ *reset
+
+
+ *----------------------------------
+ *Trying to extend Vctrl range:
+ *----------------------------------
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam W_of_mirrors = $w_next_var
+ *alterparam W_of_input_mirror = { $w_next_var * 1.01 / 2.4 }
+ *alterparam vcontrol_par = 0.7
+ *reset
+
+ *----------------------------------
+ *Measure M26 current at Vctrl 0.7 in DP5
+
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam W_of_mirrors = 2.4
+ *alterparam W_of_input_mirror = 1.01
+ *alterparam vcontrol_par = 0.7
+ *reset
+ *----------------------------------
+
+ *----------------------------
+ *Trying more current in mirrors to see if that can charge para caps faster
+ *alterparam W_of_mirrors = $w_next_var
+ *reset
+ *----------------------------
+
+
+
+ tran $t_step $t_stop $t_start
+ *tran 't_step_par' 't_stop_par'
+
+ print iteration
+ echo Width_In_This_Iteration = $w_next_var
+
+ let w_next = w_next + increment
+ *let w_next_extra_for_the_nmos = w_next_extra_for_the_nmos + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_dimensions_sweep = 1
+
+
+
+if do_paracap_sweep = 1
+ *-------- WHILE LOOP FOR RING OSC PARASITIC CAPS SWEEP-----------------
+ let start_paracap = 0f
+ let stop_paracap = 3.1f
+ let increment = 1f
+ let paracap_next = start_paracap
+
+ let iteration = 1
+
+ while paracap_next le stop_paracap
+
+ set paracap_next_var = $¶cap_next
+
+ alterparam paracap = $paracap_next_var
+ reset
+
+ tran $t_step $t_stop $t_start
+ *tran 't_step_par' 't_stop_par'
+
+ print iteration
+ echo paracap = $paracap_next_var
+
+ let paracap_next = paracap_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+ end
+
+end
+*-------------- END SWEEP PARA CAP -----------------
+
+
+
+
+if do_2dimensions_sweep = 1
+ *-------- WHILE LOOP FOR 2 DIMENSIONS SWEEP-----------------
+ let start_w_pmos = 0.6
+ let stop_w_pmos = 2.61
+ let increment_w_pmos = 0.2
+ let w_next_pmos = start_w_pmos
+
+ let start_w_nmos = 0.6
+ let stop_w_nmos = 1.61
+ let increment_w_nmos = 0.2
+ let w_next_nmos = start_w_nmos
+
+ let iteration = 1
+
+ set w_next_pmos_var = $&start_w_pmos
+ set w_next_nmos_var = $&start_w_nmos
+
+ while w_next_pmos le stop_w_pmos
+
+
+ while w_next_nmos le stop_w_nmos
+
+ alterparam W_m5 = $w_next_pmos_var
+ alterparam W_m6 = $w_next_nmos_var
+ reset
+
+ tran $t_step $t_stop $t_start
+
+ print iteration
+ echo Width_PMOS_In_This_Iteration = $w_next_pmos_var
+ echo Width_NMOS_In_This_Iteration = $w_next_nmos_var
+
+ let w_next_nmos = w_next_nmos + increment_w_nmos
+ set w_next_nmos_var = $&w_next_nmos
+ let iteration = iteration + 1
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+ end $ end inner nmos while loop
+
+
+ let w_next_pmos = w_next_pmos + increment_w_pmos
+ set w_next_pmos_var = $&w_next_pmos
+
+ let w_next_nmos = start_w_nmos
+ set w_next_nmos_var = $&w_next_nmos
+
+
+ end $ end outer pmos while loop
+
+end $end the IF do_2dimensions_sweep = 1
+*-------- END LOOP FOR 2 DIMENSIONS SWEEP-----------------
+
+
+
+
+.endc
+
+
+
+
+
+*THESE WORK:
+.meas tran Tvco_OUTSIDE_WHILE TRIG v(out) VAL=0.5*1.8 RISE=50 TARG v(out) VAL=0.5*1.8 RISE=51
+*.meas tran Tvco_OUTSIDE_WHILE TRIG v(out) VAL=0.5*1.8 RISE=4 TARG v(out) VAL=0.5*1.8 RISE=5
+.meas tran fvco_OUTSIDE_WHILE PARAM='1/Tvco_OUTSIDE_WHILE'
+.meas tran Supply_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_vdd) FROM=10e-9 TO=40e-9
+.meas tran Ground_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_gnd) FROM=10e-9 TO=40e-9
+.meas tran vctrl_avg_OUTSIDE_WHILE AVG v(vctrl) FROM=10e-9 TO=20e-9
+.meas tran vhigh_OUTSIDE_WHILE MAX v(out) FROM=10e-9 TO=20e-9
+.meas tran vlow_OUTSIDE_WHILE MIN v(out) FROM=10e-9 TO=20e-9
+.meas tran peak_to_peak_OUTSIDE_WHILE PARAM='vhigh_OUTSIDE_WHILE-vlow_OUTSIDE_WHILE'
+
+.meas tran supply_current_rms RMS i(vmeas_current_vdd) FROM='t_start_par' TO='t_stop_par'
+
+*IF NORMAL circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+ *.meas tran m7_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+*IF LVT circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_lvt_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2'
++ TO='t_stop_par'
+ *.meas tran m7_lvt_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2' TO='t_stop_par'
+
+
+
+
+
+**** end user architecture code
+**.ends
+
+
+
+
+
+
+*POST-LAYOUT DUT EXTRACTED NETLISTS:
+*This is the FULL POST-LAYOUT netlist for DP7:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dp7.spice
+
+*This is DP8 LAYOUT which is like DP7 but with just one 4.8um mirror instead of 2x, to make it less abrupt
+*since it appeared like faster in layout that in Sch.
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dp8.spice
+
+*This is DP_GUTFEEL layout as it looked decent on SCH sim with paracaps (y eso que era a ojillo)
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dpgutfeel.spice
+
+*This is DP_GUTFEEL_v2 layout which is same as GUTFEEL but just 1x 4.8um mirror overall, like DP8 in that sense
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dpgutfeel_v2.spice
+
+*This is DP_GUTFEEL_v3 layout which is same as GUTFEEL and _V2 but just 1x 2.4um mirror overall,
+*like this would be 0.5x the current of GUTFEEL_V2, the goal is to save current.
+.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dpgutfeel_v3.spice
+
+
+
+
+
+*---------------------------------------------------------------------
+*THESE ARE DP5 NETLISTS I USED TO UNDERSTAND FREQUENCY DROP DUE TO PARASITIC CAPS IN RING OSC:
+*These are netlists to debug the cap on which net degrades the speed (net10, net9, net8):
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET10_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET9_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET8_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET10_NET9_NET8_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ALL_TOP_LEVEL_SUBCKT_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ALL_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_DELAY_CELL_TRANS_SUBCKT_CAPS_INSERTED.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_NET10_NET9_NET8_TOP_LEVEL_SUBCKT_CAPS_INSERTED.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_NET10_NET9_NET8_TOP_LEVEL_AND_TRANSISTOR_SUBCKT_CAPS_INSERTED.spice
+
+*This is Layout with LI on delay cells, full extracted layout:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_li/3-stage_cs-vco_dp5_li.spice
+
+*This is Layout with LI on delay cells (v2 is with rotated FETs on delay cells, some more LI, etc), full extracted layout:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_li_v2/3-stage_cs-vco_dp5_li_v2.spice
+*---------------------------------------------------------------------
+
+
+
+
+
+
+* expanding symbol: fdiv2_loadmodel.sym # of pins=3
+** sym_path: /home/darunix/GitSandboxes/VCO/vco/xschem/fdiv2_loadmodel.sym
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/fdiv2_loadmodel.sch
+.subckt fdiv2_loadmodel vdd clk vss
+*.ipin clk
+*.iopin vdd
+*.iopin vss
+XM3 vdd clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 vss clk vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.36 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 vss clk vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 vdd clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb_INITIAL.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb_INITIAL.spice
new file mode 100755
index 0000000..f9fef88
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp7_POST-LAYOUT_tb_INITIAL.spice
@@ -0,0 +1,325 @@
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/3-stage_cs-vco_tb.sch
+**.subckt 3-stage_cs-vco_tb vctrl out buf16_out
+*.iopin vctrl
+*.iopin out
+*.iopin buf16_out
+
+*POST-LAYOUT
+x1 net1 net2 out vctrl x3-stage_cs-vco_dp7
+
+V2 vdd GND 1.8
+Vmeas_current_vdd vdd net1 0
+Vmeas_current_gnd net2 GND 0
+x2 vdd out GND fdiv2_loadmodel
+x3 out GND GND vdd vdd buf1_out sky130_fd_sc_hd__clkbuf_1
+x4 buf1_out GND GND vdd vdd net4 sky130_fd_sc_hd__clkbuf_2
+x5 net4 GND GND vdd vdd net5 sky130_fd_sc_hd__clkbuf_4
+x6 net5 GND GND vdd vdd net3 sky130_fd_sc_hd__clkbuf_8
+x7 net3 GND GND vdd vdd buf16_out sky130_fd_sc_hd__clkbuf_16
+**** begin user architecture code
+
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+*V1 vctrl GND 0.9
+V1 vctrl GND pwl(0, 0, 1n, 0, 1.1n, 0.9, 2n, 0.9, 2.1n, {vcontrol_par})
+
+*.options savecurrents
+
+*Trying to get the syntax right for probing M26 current:
+*.probe tran I(m.x1.xm26,1)
+*.save tran I(m.x1.xm26,1)
+*.probe tran @m.x1.xm26[id]
+*.save tran @m.x1.xm26[id]
+*.probe tran @m.x1.xm26.msky130_fd_pr__nfet_01v8[id]
+*.save tran @m.x1.xm26.msky130_fd_pr__nfet_01v8[id]
+
+
+*NEXT THIS:
+*PROBES FOR M26 AND M7 CURRENT IN POST-LAYOUT NETLIST:
+ .probe tran all @m.x1.xxm26.x0.msky130_fd_pr__nfet_01v8[id]
+ .save tran all @m.x1.xxm26.x0.msky130_fd_pr__nfet_01v8[id]
+ .probe tran all @m.x1.xxm16.x0.msky130_fd_pr__nfet_01v8[id]
+ .save tran all @m.x1.xxm16.x0.msky130_fd_pr__nfet_01v8[id]
+
+
+*IF NORMAL circuit: (couldn't wrap this inside an if)
+ * .probe tran all @m.x1.xm26.msky130_fd_pr__nfet_01v8[id]
+ * .save tran all @m.x1.xm26.msky130_fd_pr__nfet_01v8[id]
+ * .probe tran all @m.x1.xm7.msky130_fd_pr__nfet_01v8[id]
+ * .save tran all @m.x1.xm7.msky130_fd_pr__nfet_01v8[id]
+
+*IF LVT circuit: (couldn't wrap this inside an if)
+ *.probe tran all @m.x1.xm26.msky130_fd_pr__nfet_01v8_lvt[id]
+ *.save tran all @m.x1.xm26.msky130_fd_pr__nfet_01v8_lvt[id]
+ *.probe tran all @m.x1.xm7.msky130_fd_pr__nfet_01v8_lvt[id]
+ *.save tran all @m.x1.xm7.msky130_fd_pr__nfet_01v8_lvt[id]
+
+
+
+
+
+.control
+
+
+let do_vctrl_sweep = 1
+let do_dimensions_sweep = 0
+
+
+.param vcontrol_par = 0.9
+
+
+
+
+
+*This is to parameterize transient step/stop/start times
+*using variables:
+set t_start = 0
+set t_step = 10p
+let expected_frequency_vec = 1G
+let nperiods_vec = 100
+let t_stop_vec = nperiods_vec / expected_frequency_vec
+set t_stop = $&t_stop_vec
+
+*-----------------------
+*SEE IF THIS DOESN'T BREAK IT:
+*Trying to sync the params with the variables:
+*Just for the measure statements:
+.param t_start_par = 0
+.param t_step_par = 10p
+.param t_stop_par = 100n
+alterparam t_start_par = $t_start
+alterparam t_step_par = $t_step
+alterparam t_stop_par = $t_stop
+reset
+*-----------------------
+
+
+
+
+if do_vctrl_sweep = 1
+ *-------- WHILE LOOP FOR VCTRL SWEEP-----------------
+ let start_vctrl = 0.5
+ let stop_vctrl = 1.81
+ let increment = 0.1
+ let vctrl_next = start_vctrl
+
+ let debug_1 = 1234
+ let debug_2 = 5678
+
+ let iteration = 1
+
+ while vctrl_next le stop_vctrl
+
+ *alter V1 dc = vctrl_next
+ set vctrl_next_var = $&vctrl_next
+ alterparam vcontrol_par = $vctrl_next_var
+ reset
+
+ *This for fast frequencies:
+ *tran 10ps 100ns
+
+ *This for slow frequencies:
+ *tran 1000ps 100000ns
+
+ *This is using the (set) variables:
+ tran $t_step $t_stop $t_start
+
+ *This is to TRY to parameterize the tran
+ *using the global params BUT it doesn't seem
+ *to work if the tran is inside the .control.
+ *tran 't_step_par' 't_stop_par'
+
+
+ let vctrl_next = vctrl_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_vctrl_sweep = 1
+
+
+
+if do_dimensions_sweep = 1
+ *-------- WHILE LOOP FOR DIMENSIONS SWEEP-----------------
+ let start_w = 8.5
+ let stop_w = 14.1
+ let increment = 0.5
+ let w_next = start_w
+
+ let iteration = 1
+
+ while w_next le stop_w
+
+ set w_next_var = $&w_next
+
+ *alterparam W_delay_pmos = $w_next_var
+ *alterparam W_delay_nmos = $w_next_var
+ *The RESET is required after the alterparam (manual says)
+ *reset
+
+ *alterparam W_delay_pmos = 0.42
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam M21_W = 2.88
+ *alterparam M22_W = 1.44
+ *reset
+
+
+ *alterparam M21_W = $w_next_var
+ *alterparam M22_W = {$w_next_var / 2}
+ *reset
+
+
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+ *alterparam M21_W = 0.58
+ *alterparam M22_W = 0.36
+ *reset
+
+
+
+
+
+ *----------------------------------
+ *Trying to extend Vctrl range:
+ *----------------------------------
+ *alterparam W_delay_pmos = 0.5
+ *alterparam W_delay_nmos = 0.36
+
+ *alterparam W_of_mirrors = $w_next_var
+ *alterparam W_of_input_mirror = { $w_next_var * 1.01 / 2.4 }
+ *alterparam vcontrol_par = 0.7
+ *reset
+
+ *----------------------------------
+ *Measure M26 current at Vctrl 0.7 in DP5
+
+ alterparam W_delay_pmos = 0.5
+ alterparam W_delay_nmos = 0.36
+
+ alterparam W_of_mirrors = 2.4
+ alterparam W_of_input_mirror = 1.01
+ alterparam vcontrol_par = 0.7
+ reset
+ *----------------------------------
+
+
+
+
+ tran $t_step $t_stop $t_start
+ *tran 't_step_par' 't_stop_par'
+
+ print iteration
+ echo W_delay_pmos = $w_next_var
+
+ let w_next = w_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write 3-stage_cs-vco_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_dimensions_sweep = 1
+
+
+
+
+
+
+.endc
+
+
+
+
+
+*THESE WORK:
+.meas tran Tvco_OUTSIDE_WHILE TRIG v(out) VAL=0.5*1.8 RISE=50 TARG v(out) VAL=0.5*1.8 RISE=51
+*.meas tran Tvco_OUTSIDE_WHILE TRIG v(out) VAL=0.5*1.8 RISE=4 TARG v(out) VAL=0.5*1.8 RISE=5
+.meas tran fvco_OUTSIDE_WHILE PARAM='1/Tvco_OUTSIDE_WHILE'
+.meas tran Supply_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_vdd) FROM=10e-9 TO=40e-9
+.meas tran Ground_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_gnd) FROM=10e-9 TO=40e-9
+.meas tran vctrl_avg_OUTSIDE_WHILE AVG v(vctrl) FROM=10e-9 TO=20e-9
+.meas tran vhigh_OUTSIDE_WHILE MAX v(out) FROM=10e-9 TO=20e-9
+.meas tran vlow_OUTSIDE_WHILE MIN v(out) FROM=10e-9 TO=20e-9
+.meas tran peak_to_peak_OUTSIDE_WHILE PARAM='vhigh_OUTSIDE_WHILE-vlow_OUTSIDE_WHILE'
+
+.meas tran supply_current_rms RMS i(vmeas_current_vdd) FROM='t_start_par' TO='t_stop_par'
+
+*IF NORMAL circuit: (couldn't wrap this inside an if)
+ * .meas tran m26_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+ * .meas tran m7_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+*IF LVT circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_lvt_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2'
++ TO='t_stop_par'
+ *.meas tran m7_lvt_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2' TO='t_stop_par'
+
+
+
+
+
+**** end user architecture code
+**.ends
+
+
+*DUT:
+
+*This is the FULL POST-LAYOUT netlist:
+.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp7/3-stage_cs-vco_dp7.spice
+
+
+*These are netlists to debug the cap on which net degrades the speed (net10, net9, net8):
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET10_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET9_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET8_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_NET10_NET9_NET8_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ALL_TOP_LEVEL_SUBCKT_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ALL_CAPS_COMMENTED_OUT.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_DELAY_CELL_TRANS_SUBCKT_CAPS_INSERTED.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_NET10_NET9_NET8_TOP_LEVEL_SUBCKT_CAPS_INSERTED.spice
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_ONLY_NET10_NET9_NET8_TOP_LEVEL_AND_TRANSISTOR_SUBCKT_CAPS_INSERTED.spice
+
+*This is Layout with LI on delay cells, full extracted layout:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_li/3-stage_cs-vco_dp5_li.spice
+
+*This is Layout with LI on delay cells (v2 is with rotated FETs on delay cells, some more LI, etc), full extracted layout:
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp5_li_v2/3-stage_cs-vco_dp5_li_v2.spice
+
+
+
+
+
+
+
+* expanding symbol: fdiv2_loadmodel.sym # of pins=3
+** sym_path: /home/darunix/GitSandboxes/VCO/vco/xschem/fdiv2_loadmodel.sym
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/fdiv2_loadmodel.sch
+.subckt fdiv2_loadmodel vdd clk vss
+*.ipin clk
+*.iopin vdd
+*.iopin vss
+XM3 vdd clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 vss clk vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.36 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 vss clk vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 vdd clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.ext
new file mode 100755
index 0000000..e1ff706
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.ext
@@ -0,0 +1,357 @@
+timestamp 1645799856
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -160 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -366 0 1 1039
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 597
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 886 0 1 105
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__pfet_01v8_FYZURS XM5 0 -1 517 1 0 351
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1 1 0 350 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 256 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 49 0 1 899
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3 0 1 101 -1 0 351
+use sky130_fd_pr__nfet_01v8_LS29AB XM4 0 -1 83 1 0 101
+use sky130_fd_pr__pfet_01v8_BT7HXK XM1 0 1 -215 -1 0 351
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -187 1 0 101
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1356 0 1 -4
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -391
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 -1 0 256 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 50 0 1 -397
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -157 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -363 0 1 -537
+port "vctrl" 3 -826 -752 -626 -552 m1
+port "out" 2 1849 118 2049 318 m1
+port "vdd" 0 1172 1542 1372 1742 m1
+port "vss" 1 1202 -1174 1402 -974 m1
+node "vctrl" 5 2118.25 -826 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53472 1532 51344 2604 0 0 0 0 0 0 0 0
+node "out" 3 727.503 1849 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 88560 3228 0 0 0 0 0 0 0 0 0 0
+node "m1_n457_n334#" 5 920.182 -457 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85514 3810 0 0 0 0 0 0 0 0 0 0
+node "m1_n230_1050#" 3 -222.47 -230 1050 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19682 962 27376 1420 0 0 0 0 0 0 0 0
+node "li_528_n678#" 55 313.035 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_n678#" 57 216.793 223 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 119 377.338 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11254 730 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n210_7#" 41 1670.38 -210 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 40480 1702 0 0 0 0 0 0 0 0 0 0
+node "li_1213_134#" 52 151.34 1213 134 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_917_51#" 207 373.634 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 410.13 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n360_106#" 204 985.475 -360 106 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14450 1036 27470 1650 0 0 0 0 0 0 0 0 0 0
+node "li_132_290#" 193 324.181 132 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17943 1134 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n112_286#" 178 308.593 -112 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16898 1062 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_338#" 172 52.2552 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16286 1026 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n267_410#" 53 -27.88 -267 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 49714 2150 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 141 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13362 854 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 -11.48 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_1149#" 57 -11.48 223 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_16_1150#" 24 0 16 1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 146.484 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_n694#" 114 108.297 289 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 61.7185 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_1133#" 114 4.8972 289 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 22170 8566.81 1172 1542 m1 0 0 0 0 2613265 6942 0 0 160990 9470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 188700 11304 954801 20252 5488 340 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 1202 -1174 m1 2547045 6886 0 0 0 0 0 0 0 0 160412 9436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 171700 10304 1010333 21150 5968 364 0 0 0 0 0 0 0 0
+cap "li_1213_134#" "li_611_133#" 4.49096
+cap "li_n360_106#" "li_n267_410#" 123.51
+cap "vdd" "li_1179_338#" 198.559
+cap "li_132_290#" "vdd" 166.115
+cap "li_n360_106#" "li_611_133#" 25.3289
+cap "li_1213_134#" "li_1179_338#" 37.5411
+cap "li_n267_410#" "m1_n457_n334#" 61.7541
+cap "li_611_133#" "a_879_204#" 11.55
+cap "m1_n230_1050#" "li_16_1150#" 22
+cap "a_289_n694#" "a_590_n694#" 5.56044
+cap "li_n360_106#" "li_132_290#" 171.146
+cap "li_1179_712#" "vdd" 286.665
+cap "li_n112_286#" "li_132_290#" 50.6002
+cap "li_1179_n70#" "li_917_51#" 0.798387
+cap "li_611_133#" "li_917_51#" 28.2715
+cap "li_223_n678#" "a_289_n694#" 25.2972
+cap "vdd" "out" 311.915
+cap "m1_n230_1050#" "vdd" 1720.18
+cap "li_223_n678#" "vctrl" 130.927
+cap "li_917_51#" "li_1179_338#" 32.2616
+cap "li_16_1150#" "vdd" 116.501
+cap "a_289_n694#" "vctrl" 42.185
+cap "a_289_1133#" "m1_n230_1050#" 35.605
+cap "li_1179_n70#" "li_1179_338#" 10.1455
+cap "m1_n230_1050#" "li_223_1149#" 122.556
+cap "li_16_1150#" "li_223_1149#" 7.7234
+cap "m1_n230_1050#" "m1_n457_n334#" 29.1549
+cap "li_132_290#" "li_611_133#" 19.0555
+cap "li_n210_7#" "li_n360_106#" 120.432
+cap "vdd" "a_589_1133#" 89.685
+cap "li_n112_286#" "li_n210_7#" 3.16013
+cap "a_289_1133#" "vdd" 51.7
+cap "li_n210_7#" "m1_n457_n334#" 44.1353
+cap "li_523_1149#" "vdd" 288.418
+cap "a_289_1133#" "a_589_1133#" 5.58088
+cap "li_n360_106#" "vdd" 210.51
+cap "vdd" "li_223_1149#" 160.213
+cap "li_523_1149#" "a_589_1133#" 25.2972
+cap "vctrl" "m1_n457_n334#" 2.925
+cap "li_n112_286#" "vdd" 136.956
+cap "vdd" "a_879_204#" 11
+cap "a_289_1133#" "li_223_1149#" 25.2972
+cap "vdd" "m1_n457_n334#" 565.999
+cap "li_528_n678#" "a_590_n694#" 25.2972
+cap "li_523_1149#" "li_223_1149#" 8.01429
+cap "li_1179_712#" "li_1179_338#" 3.3
+cap "m1_n230_1050#" "li_n267_410#" 5.50532
+cap "li_n112_286#" "li_n360_106#" 79.617
+cap "li_n360_106#" "m1_n457_n334#" 53.0769
+cap "li_n210_7#" "li_n267_410#" 27.8642
+cap "li_917_51#" "vdd" 126.227
+cap "li_528_n678#" "li_223_n678#" 7.73793
+cap "li_1213_134#" "li_917_51#" 12.6752
+cap "vdd" "li_n267_410#" 1236.03
+cap "li_1179_n70#" "li_1213_134#" 15.4737
+cap "li_611_133#" "vdd" 94.682
+cap "XM2/a_15_n103#" "XM16_1/a_n76_n209#" 8.97523
+cap "XM22/a_15_n68#" "XMDUM26/a_n76_n69#" 0.048105
+cap "XM1/a_n73_n64#" "XM16_1/a_n76_n209#" 3.73718
+cap "XM2/a_n33_63#" "XM4/a_15_n68#" -0.414227
+cap "XM2/a_15_n103#" "XM4/a_15_n68#" 30.9976
+cap "XMDUM26/a_n76_n69#" "XM2/a_n33_63#" 351.778
+cap "XM4/a_15_n68#" "XM3/a_n73_n14#" 3.63271
+cap "XMDUM26/a_n76_n69#" "XM2/a_15_n103#" 273.212
+cap "XMDUM26/a_n76_n69#" "XM3/a_n73_n14#" 4.35662
+cap "XM1/w_n109_n164#" "XM4/a_15_n68#" 3.60186
+cap "XM4/a_15_n68#" "XM16_1/a_n76_n209#" 5.2212
+cap "XMDUM26/a_n76_n69#" "XM26/a_n76_n69#" 533.409
+cap "XMDUM26/a_n76_n69#" "XM16_1/a_n76_n209#" 896.951
+cap "XMDUM26/a_n76_n69#" "XM4/a_15_n68#" 201.059
+cap "XM2/a_n33_63#" "XM2/a_15_n103#" 34.9625
+cap "XM2/a_n33_63#" "XM1/a_n73_n64#" 1.09798
+cap "XM26/a_n33_n157#" "XM26/a_n76_n69#" 0.734364
+cap "XM1/a_n73_n64#" "XM2/a_15_n103#" 11.5347
+cap "XM2/a_n33_63#" "XM3/a_n73_n14#" 14.5903
+cap "XM26/a_n33_n157#" "XM16_1/a_n76_n209#" 66.5772
+cap "XM26/a_n33_n157#" "XM4/a_15_n68#" 3.82892
+cap "XM1/w_n109_n164#" "XM2/a_15_n103#" 5.37945
+cap "XM2/a_n33_63#" "XM1/w_n109_n164#" 8.63425
+cap "XM26/a_n33_n157#" "XMDUM26/a_n76_n69#" 601.313
+cap "XM16B_1/a_n33_n297#" "XM12/a_n73_n240#" 7.62219
+cap "XM13/a_15_n120#" "XM6/a_15_n175#" 0.444378
+cap "XM13/a_n33_142#" "XM24/a_18_n129#" 5.15315
+cap "XM16B_1/a_n33_n297#" "XM24/a_18_n129#" 246.158
+cap "XM16B_1/a_n33_n297#" "XM16_1/a_n76_n209#" 82.3606
+cap "XM6/a_15_n175#" "XM6/a_n33_135#" -0.99603
+cap "XM6/a_15_n175#" "XMDUM11B/a_n33_235#" 0.676471
+cap "XM13/a_n33_142#" "XM6/a_15_n175#" 6.9818
+cap "XM16B_1/a_n33_n297#" "XM6/a_15_n175#" 216.112
+cap "XM6/a_15_n175#" "XM21/a_n72_n22#" 8.01429
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 28.1783
+cap "XM13/a_15_n120#" "XM16B_1/a_n33_n297#" 620.764
+cap "XM6/a_15_n175#" "XM5/a_15_n236#" 2.78408
+cap "XM6/a_15_n175#" "XM11B_1/w_n112_n338#" -0.166742
+cap "XM13/a_15_n120#" "XM23/a_n173_n220#" 3.1875
+cap "XM16B_1/a_n33_n297#" "XM6/a_n33_135#" 50.3821
+cap "XM13/a_n33_142#" "XM16B_1/a_n33_n297#" 243.429
+cap "XM16_1/a_n33_n297#" "XM16B_1/a_n33_n297#" 0.426467
+cap "XM16B_1/a_n33_n297#" "XM21/a_n72_n22#" 5.57731
+cap "XM23/a_n173_n220#" "XM16B_1/a_n33_n297#" 2.29918
+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 60.3698
+cap "XM16B_1/a_n33_n297#" "XM5/a_15_n236#" 1.28206
+cap "XM13/a_n33_142#" "XM12/a_n73_n240#" -2.56667
+cap "XM1/a_n73_n64#" "XM1/w_n109_n164#" 193.602
+cap "XM4/a_n73_n68#" "XM2/a_n33_63#" 14.5903
+cap "XM1/w_n109_n164#" "XM2/a_n33_63#" 34.1417
+cap "XM2/a_15_n103#" "XM1/w_n109_n164#" -6.76538
+cap "XM4/a_15_n68#" "XM11/a_n33_235#" 4.05283
+cap "XM4/a_n73_n68#" "XM1/w_n109_n164#" 4.35662
+cap "XM1/w_n109_n164#" "XM21/a_15_n22#" 1.22222
+cap "XM4/a_15_n68#" "XM1/a_n73_n64#" 3.23597
+cap "XM4/a_15_n68#" "vss" 1.40094
+cap "XM4/a_15_n68#" "XM2/a_n33_63#" 9.10597
+cap "XM4/a_15_n68#" "XM2/a_15_n103#" 29.3183
+cap "XM1/a_n73_n64#" "XM16_1/a_n76_n209#" 3.73718
+cap "XM2/a_15_n103#" "XM16_1/a_n76_n209#" 10.021
+cap "XM4/a_15_n68#" "XM4/a_n73_n68#" 2.19146
+cap "XM4/a_15_n68#" "XM1/w_n109_n164#" -45.2743
+cap "XM1/a_n73_n64#" "XM11/a_n33_235#" 57.9334
+cap "XM2/a_15_n103#" "XM1/a_n73_n64#" 12.3495
+cap "XM1/a_n73_n64#" "XM2/a_n33_63#" 1.09798
+cap "XM2/a_15_n103#" "vss" 8.98567
+cap "XM2/a_n33_63#" "vss" 10.0366
+cap "XM2/a_15_n103#" "XM2/a_n33_63#" 47.6859
+cap "XM1/w_n109_n164#" "XM11/a_n33_235#" 272.154
+cap "XM11/a_18_n276#" "XM11B_1/w_n112_n338#" 84.2043
+cap "XM24/a_n76_n129#" "XM13/a_15_n120#" 3.35928
+cap "vss" "XM13/a_n33_142#" 41.7792
+cap "XM11B_1/w_n112_n338#" "XM24/a_18_n129#" 251.852
+cap "XM6/a_n73_n175#" "XM11B_1/w_n112_n338#" 1.28206
+cap "XM11B_1/w_n112_n338#" "XM13/a_n73_n120#" 7.62219
+cap "XM6/a_n33_135#" "XM6/a_15_n175#" -1.25069
+cap "XM6/a_15_n175#" "XM11B_1/w_n112_n338#" 13.3765
+cap "XM13/a_15_n120#" "XM11B_1/w_n112_n338#" 394.213
+cap "XM11/a_n33_235#" "XM11B_1/w_n112_n338#" -3.41003
+cap "XM6/a_15_n175#" "XM6/a_n73_n175#" 2.82639
+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 214.413
+cap "XM11B_1/w_n112_n338#" "vss" 1.85762
+cap "XM6/a_n33_135#" "XM13/a_n33_142#" 0.385475
+cap "XM11B_1/w_n112_n338#" "XM13/a_n33_142#" 13.6743
+cap "XM24/a_n76_n129#" "XM11B_1/w_n112_n338#" 2.29918
+cap "XM13/a_15_n120#" "vss" -13.94
+cap "XM6/a_15_n175#" "vss" -8.67038
+cap "XM13/a_n73_n120#" "XM13/a_n33_142#" 7.5625
+cap "XM6/a_15_n175#" "XM13/a_n33_142#" 11.0353
+cap "XM11B_1/w_n112_n338#" "XM22/a_n73_n68#" 3.7197
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 39.9911
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#" 2016.92 0 0 0 0 2383 -21282 0 0 446352 0 -1392 -1556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3828 -264 0 0 422730 -3342 2496724 -5472 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n173_n220#" "XM25/a_18_n136#"
+merge "XM25/a_18_n136#" "XM25/w_n112_n198#"
+merge "XM25/w_n112_n198#" "XMDUM25/a_18_n136#"
+merge "XMDUM25/a_18_n136#" "XMDUM25/a_n76_n136#"
+merge "XMDUM25/a_n76_n136#" "XMDUM25/a_n33_95#"
+merge "XMDUM25/a_n33_95#" "XMDUM25/w_n112_n198#"
+merge "XMDUM25/w_n112_n198#" "XMDUM11B/a_18_n276#"
+merge "XMDUM11B/a_18_n276#" "XMDUM11B/a_n33_235#"
+merge "XMDUM11B/a_n33_235#" "XMDUM11B/a_n76_n276#"
+merge "XMDUM11B/a_n76_n276#" "XM11_1/a_18_n276#"
+merge "XM11_1/a_18_n276#" "XM11/a_n76_n276#"
+merge "XM11/a_n76_n276#" "XM11B/a_n76_n276#"
+merge "XM11B/a_n76_n276#" "XM11B/a_n33_235#"
+merge "XM11B/a_n33_235#" "XM11B_1/a_18_n276#"
+merge "XM11B_1/a_18_n276#" "XM11B/a_18_n276#"
+merge "XM11B/a_18_n276#" "XM11B_1/a_n76_n276#"
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+merge "XM11B_1/a_n33_235#" "li_523_1149#"
+merge "li_523_1149#" "a_589_1133#"
+merge "a_589_1133#" "XMDUM11/a_18_n276#"
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+merge "XMDUM11/a_n76_n276#" "XMDUM11/a_n33_235#"
+merge "XMDUM11/a_n33_235#" "li_16_1150#"
+merge "li_16_1150#" "XM23/w_n209_n320#"
+merge "XM23/w_n209_n320#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XM12/w_n109_n340#"
+merge "XM12/w_n109_n340#" "XMDUM11B/w_n112_n338#"
+merge "XMDUM11B/w_n112_n338#" "XM21/a_n72_n22#"
+merge "XM21/a_n72_n22#" "XM21/w_n109_n58#"
+merge "XM21/w_n109_n58#" "XM5/a_15_n236#"
+merge "XM5/a_15_n236#" "XM5/w_n109_n298#"
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+merge "XM11B/w_n112_n338#" "XM11B_1/w_n112_n338#"
+merge "XM11B_1/w_n112_n338#" "XMDUM11/w_n112_n338#"
+merge "XMDUM11/w_n112_n338#" "XM3/a_n73_n14#"
+merge "XM3/a_n73_n14#" "XM3/w_n109_n114#"
+merge "XM3/w_n109_n114#" "XM1/w_n109_n164#"
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+merge "XM16/a_n76_n209#" "XM16_1/a_n76_n209#"
+merge "XM16_1/a_n76_n209#" "li_n210_7#"
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+merge "XM11/a_18_n276#" "XM1/a_n73_n64#"
+merge "XM1/a_n73_n64#" "li_n267_410#"
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+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "XM22/a_n33_33#" "XM21/a_n15_n53#" -408.51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5775 -120 0 0 15183 -892 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM21/a_n15_n53#" "a_879_204#"
+merge "a_879_204#" "XM5/a_n73_n236#"
+merge "XM5/a_n73_n236#" "XM6/a_15_n175#"
+merge "XM6/a_15_n175#" "li_611_133#"
+merge "li_611_133#" "XM1/a_n33_n161#"
+merge "XM1/a_n33_n161#" "XM2/a_n33_63#"
+merge "XM2/a_n33_63#" "li_n360_106#"
+merge "XM25/VSUBS" "XMDUM25/VSUBS" -4490.35 116876 -2399 0 0 0 0 0 0 18972 -1076 345160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3960 -264 0 0 291580 -2148 194072 -6496 0 0 0 0 0 0 0 0 0 0
+merge "XMDUM25/VSUBS" "XM23/VSUBS"
+merge "XM23/VSUBS" "XM12/VSUBS"
+merge "XM12/VSUBS" "XM24/VSUBS"
+merge "XM24/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM13/VSUBS"
+merge "XM13/VSUBS" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "XM22/VSUBS"
+merge "XM22/VSUBS" "XM22/a_n73_n68#"
+merge "XM22/a_n73_n68#" "XMDUM11B/VSUBS"
+merge "XMDUM11B/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "XM5/VSUBS"
+merge "XM5/VSUBS" "XM6/VSUBS"
+merge "XM6/VSUBS" "XM6/a_n73_n175#"
+merge "XM6/a_n73_n175#" "XM11_1/VSUBS"
+merge "XM11_1/VSUBS" "XM11/VSUBS"
+merge "XM11/VSUBS" "XM11B/VSUBS"
+merge "XM11B/VSUBS" "XM11B_1/VSUBS"
+merge "XM11B_1/VSUBS" "XMDUM11/VSUBS"
+merge "XMDUM11/VSUBS" "XM3/VSUBS"
+merge "XM3/VSUBS" "XM4/VSUBS"
+merge "XM4/VSUBS" "XM4/a_n73_n68#"
+merge "XM4/a_n73_n68#" "XM1/VSUBS"
+merge "XM1/VSUBS" "XM2/VSUBS"
+merge "XM2/VSUBS" "XMDUM16B/VSUBS"
+merge "XMDUM16B/VSUBS" "XMDUM16B/a_n33_n297#"
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+merge "XMDUM16B/a_18_n209#" "XMDUM16B/a_n76_n209#"
+merge "XMDUM16B/a_n76_n209#" "XM16/VSUBS"
+merge "XM16/VSUBS" "XM16/a_18_n209#"
+merge "XM16/a_18_n209#" "XM16_1/VSUBS"
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+merge "XM16B/a_n76_n209#" "XM16B_1/VSUBS"
+merge "XM16B_1/VSUBS" "XM16B_1/a_n76_n209#"
+merge "XM16B_1/a_n76_n209#" "XM16B_1/a_n33_n297#"
+merge "XM16B_1/a_n33_n297#" "li_528_n678#"
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+merge "a_590_n694#" "XM16B_1/a_18_n209#"
+merge "XM16B_1/a_18_n209#" "XMDUM16/VSUBS"
+merge "XMDUM16/VSUBS" "XMDUM16/a_n33_n297#"
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+merge "XM16_1/a_n33_n297#" "XM26/a_n33_n157#"
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+merge "XM4/a_n33_33#" "XM1/a_15_n64#"
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+merge "XM26/a_n76_n69#" "m1_n457_n334#"
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+merge "m1_n230_1050#" "li_223_1149#"
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+merge "XM12/a_n33_n337#" "XM13/a_n33_142#" -257.54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 132 -166 0 0 -68246 -456 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM13/a_n33_142#" "XM22/a_15_n68#"
+merge "XM22/a_15_n68#" "XM21/a_15_n22#"
+merge "XM21/a_15_n22#" "li_917_51#"
+merge "XM23/a_n33_251#" "XM23/a_63_n317#" -377.853 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8792 -1066 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_63_n317#" "li_1179_712#"
+merge "li_1179_712#" "XM23/a_n129_n317#"
+merge "XM23/a_n129_n317#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "li_1179_338#"
+merge "li_1179_338#" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "li_1179_n70#"
+merge "li_1179_n70#" "li_1213_134#"
+merge "XM5/a_n33_195#" "XM6/a_n33_135#" -182.158 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19937 -506 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM6/a_n33_135#" "XM3/a_15_n14#"
+merge "XM3/a_15_n14#" "XM4/a_15_n68#"
+merge "XM4/a_15_n68#" "li_132_290#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.mag
new file mode 100755
index 0000000..4494f59
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.mag
@@ -0,0 +1,458 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645799856
+<< error_s >>
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+rect 871 25 901 37
+<< nwell >>
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+<< psubdiffcont >>
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+<< via1 >>
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+rect -762 -687 -710 -635
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+<< metal2 >>
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+rect 572 -687 578 -681
+rect 630 -687 636 -635
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -363 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -157 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -187 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_BT7HXK XM1
+timestamp 1645723234
+transform 0 1 -215 -1 0 351
+box -109 -164 109 198
+use sky130_fd_pr__nfet_01v8_LS29AB XM4
+timestamp 1645537996
+transform 0 -1 83 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3
+timestamp 1645537996
+transform 0 1 101 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_FYZURS XM5
+timestamp 1645722298
+transform 0 -1 517 1 0 351
+box -109 -298 109 264
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -366 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -160 0 1 1039
+box -112 -198 112 164
+<< labels >>
+rlabel metal1 -826 -752 -626 -552 1 vctrl
+port 3 n
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.spice
new file mode 100755
index 0000000..274b0ac
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8.spice
@@ -0,0 +1,302 @@
+* NGSPICE file created from 3-stage_cs-vco_dp8.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 w_n109_n340# a_15_n240# 0.17fF
+C1 w_n109_n340# a_n73_n240# 0.19fF
+C2 w_n109_n340# a_n33_n337# 0.11fF
+C3 a_n73_n240# a_15_n240# 0.20fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n33_251# a_18_n220# 0.00fF
+C1 a_n129_n317# a_n33_251# 0.02fF
+C2 a_n78_n220# a_n173_n220# 0.31fF
+C3 a_n173_n220# a_114_n220# 0.07fF
+C4 a_n173_n220# a_18_n220# 0.14fF
+C5 a_n173_n220# a_n129_n317# 0.00fF
+C6 a_n78_n220# w_n209_n320# 0.33fF
+C7 w_n209_n320# a_63_n317# 0.14fF
+C8 w_n209_n320# a_114_n220# 0.33fF
+C9 w_n209_n320# a_18_n220# 0.28fF
+C10 w_n209_n320# a_n129_n317# 0.14fF
+C11 w_n209_n320# a_n33_251# 0.14fF
+C12 a_n78_n220# a_114_n220# 0.18fF
+C13 a_63_n317# a_114_n220# 0.00fF
+C14 a_n78_n220# a_18_n220# 0.31fF
+C15 a_18_n220# a_63_n317# 0.00fF
+C16 a_18_n220# a_114_n220# 0.31fF
+C17 a_n173_n220# w_n209_n320# 0.28fF
+C18 a_n78_n220# a_n129_n317# 0.00fF
+C19 a_n129_n317# a_63_n317# 0.03fF
+C20 a_n78_n220# a_n33_251# 0.00fF
+C21 a_n33_251# a_63_n317# 0.02fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_15_n120# a_n73_n120# 0.15fF
+C1 a_15_n120# a_n33_142# 0.00fF
+C2 a_n33_142# a_n73_n120# 0.01fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_18_n129# a_n76_n129# 0.21fF
+C1 a_18_n129# a_n33_n217# 0.01fF
+C2 a_n33_n217# a_n76_n129# 0.01fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n136# a_n76_n136# 0.20fF
+C1 a_n76_n136# a_n33_95# 0.00fF
+C2 a_n76_n136# w_n112_n198# 0.16fF
+C3 a_18_n136# a_n33_95# 0.00fF
+C4 w_n112_n198# a_n33_95# 0.19fF
+C5 a_18_n136# w_n112_n198# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n69# a_n76_n69# 0.17fF
+C1 a_18_n69# a_n33_n157# 0.01fF
+C2 a_n33_n157# a_n76_n69# 0.00fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n76_n209# 0.35fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_n76_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n276# a_n76_n276# 0.46fF
+C1 a_n76_n276# a_n33_235# 0.00fF
+C2 a_n76_n276# w_n112_n338# 0.32fF
+C3 a_18_n276# a_n33_235# 0.00fF
+C4 w_n112_n338# a_n33_235# 0.19fF
+C5 a_18_n276# w_n112_n338# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n76_n209# 0.47fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n33_n297# a_n76_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BT7HXK a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+C0 a_15_n64# a_n73_n64# 0.11fF
+C1 a_n73_n64# a_n33_n161# 0.00fF
+C2 a_n73_n64# w_n109_n164# 0.10fF
+C3 a_15_n64# a_n33_n161# 0.00fF
+C4 w_n109_n164# a_n33_n161# 0.14fF
+C5 a_15_n64# w_n109_n164# 0.10fF
+C6 a_15_n64# VSUBS -0.08fF
+C7 a_n73_n64# VSUBS -0.08fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_15_n103# a_n73_n103# 0.07fF
+C1 a_15_n103# a_n33_63# 0.00fF
+C2 a_n33_63# a_n73_n103# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BKC9WK a_n73_n14# a_n33_n111# w_n109_n114# a_15_n14#
++ VSUBS
+X0 a_15_n14# a_n33_n111# a_n73_n14# w_n109_n114# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n14# a_n73_n14# 0.04fF
+C1 a_n73_n14# a_n33_n111# 0.00fF
+C2 a_n73_n14# w_n109_n114# 0.04fF
+C3 a_15_n14# a_n33_n111# 0.00fF
+C4 w_n109_n114# a_n33_n111# 0.14fF
+C5 a_15_n14# w_n109_n114# 0.04fF
+C6 a_15_n14# VSUBS -0.04fF
+C7 a_n73_n14# VSUBS -0.04fF
+C8 a_n33_n111# VSUBS -0.01fF
+C9 w_n109_n114# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_15_n68# a_n73_n68# 0.04fF
+C1 a_15_n68# a_n33_33# 0.00fF
+C2 a_n33_33# a_n73_n68# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_FYZURS a_n33_195# a_n73_n236# w_n109_n298# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_195# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=150000u
+C0 a_15_n236# a_n73_n236# 0.22fF
+C1 a_n73_n236# a_n33_195# 0.00fF
+C2 a_n73_n236# w_n109_n298# 0.18fF
+C3 a_15_n236# a_n33_195# 0.00fF
+C4 w_n109_n298# a_n33_195# 0.14fF
+C5 a_15_n236# w_n109_n298# 0.18fF
+C6 a_15_n236# VSUBS -0.16fF
+C7 a_n73_n236# VSUBS -0.16fF
+C8 a_n33_195# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.37fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_15_n175# a_n73_n175# 0.16fF
+C1 a_15_n175# a_n33_135# 0.00fF
+C2 a_n33_135# a_n73_n175# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 a_15_n22# a_n72_n22# 0.09fF
+C1 a_n72_n22# w_n109_n58# 0.14fF
+C2 w_n109_n58# a_n15_n53# 0.05fF
+C3 a_15_n22# w_n109_n58# 0.08fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt x3-stage_cs-vco_dp8 vdd vss out vctrl
+XXM12 li_1213_134# vdd vdd li_917_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd vdd out vdd li_1213_134# li_1213_134# li_1213_134# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM13 vss li_1213_134# li_917_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 li_1213_134# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM25 vdd a_289_1133# vdd a_289_1133# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 a_289_1133# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 li_n210_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16_1 li_n210_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM16B_1 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM1 li_n267_410# a_879_204# vdd li_n112_286# vss sky130_fd_pr__pfet_01v8_BT7HXK
+XXM2 li_n210_7# li_n112_286# a_879_204# vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd li_n112_286# vdd li_132_290# vss sky130_fd_pr__pfet_01v8_BKC9WK
+XXM4 li_n112_286# vss li_132_290# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM5 li_132_290# a_879_204# vdd vdd vss sky130_fd_pr__pfet_01v8_FYZURS
+XXM6 li_132_290# a_879_204# vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXM11B_1 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11_1 vdd vdd a_289_1133# li_n267_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 vdd li_917_51# vdd a_879_204# vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11 li_n267_410# vdd a_289_1133# vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 a_879_204# vss li_917_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+C0 vdd a_289_1133# 2.81fF
+C1 vdd li_1213_134# 0.88fF
+C2 vdd li_132_290# 0.13fF
+C3 vdd vss 0.04fF
+C4 li_917_51# li_1213_134# 0.11fF
+C5 vdd li_n267_410# 1.51fF
+C6 li_917_51# li_132_290# 0.00fF
+C7 li_917_51# vss 0.29fF
+C8 vdd a_879_204# 0.40fF
+C9 a_289_1133# li_132_290# 0.00fF
+C10 vss a_289_1133# 0.53fF
+C11 li_n267_410# a_289_1133# 0.13fF
+C12 li_917_51# a_879_204# 0.05fF
+C13 vss li_1213_134# 0.61fF
+C14 vss li_132_290# 0.26fF
+C15 a_289_1133# a_879_204# 0.05fF
+C16 li_n267_410# li_132_290# 0.00fF
+C17 li_n210_7# a_289_1133# 0.04fF
+C18 vdd li_n112_286# 0.14fF
+C19 li_1213_134# a_879_204# 0.00fF
+C20 a_879_204# li_132_290# 0.20fF
+C21 vss a_879_204# 0.59fF
+C22 li_n210_7# li_132_290# 0.01fF
+C23 li_n267_410# a_879_204# 0.13fF
+C24 li_n210_7# vss 0.98fF
+C25 li_n267_410# li_n210_7# 0.04fF
+C26 a_289_1133# vctrl 0.00fF
+C27 vdd out 0.56fF
+C28 li_n210_7# a_879_204# 0.12fF
+C29 li_917_51# out 0.01fF
+C30 li_n112_286# li_132_290# 0.11fF
+C31 vss li_n112_286# 0.28fF
+C32 li_n267_410# li_n112_286# 0.02fF
+C33 vctrl li_132_290# 0.00fF
+C34 vss vctrl 0.62fF
+C35 li_n112_286# a_879_204# 0.16fF
+C36 li_n210_7# li_n112_286# 0.02fF
+C37 out li_1213_134# 0.27fF
+C38 li_n210_7# vctrl 0.07fF
+C39 vss out 0.25fF
+C40 li_917_51# vdd 0.14fF
+C41 vctrl 0 2.21fF
+C42 li_1213_134# 0 0.23fF
+C43 a_289_1133# 0 0.43fF
+C44 li_917_51# 0 0.21fF
+C45 li_132_290# 0 0.23fF
+C46 li_n112_286# 0 0.12fF
+C47 a_879_204# 0 1.16fF
+C48 li_n267_410# 0 -0.47fF
+C49 vdd 0 10.81fF
+C50 vss 0 -3.34fF
+C51 li_n210_7# 0 0.90fF
+C52 out 0 -0.17fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..8aa94fb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp8_POST-LAYOUT_tb.log
@@ -0,0 +1,2361 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.67365e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 9.38284e-06 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.268855e-06 at= 1.000500e-08
+vlow_outside_while = -3.251299e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 6.52015e-06
+supply_current_rms = 6.38002e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.91112e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.28653e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.955698e-06 at= 1.001500e-08
+vlow_outside_while = -2.946381e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 5.90208e-06
+supply_current_rms = 4.88644e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.68335e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.93479e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.267482e-06 at= 1.001500e-08
+vlow_outside_while = -1.257764e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 2.52525e-06
+supply_current_rms = 5.19737e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.31150e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.37176e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.150640e-06 at= 1.998500e-08
+vlow_outside_while = -1.137131e-06 at= 1.999500e-08
+peak_to_peak_outside_while= 2.28777e-06
+supply_current_rms = 6.10642e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 4.53128e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.34202e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.212277e-06 at= 1.001500e-08
+vlow_outside_while = -2.204058e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 4.41634e-06
+supply_current_rms = 6.18481e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 7.74040e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 6.63516e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.918852e+00 at= 1.348500e-08
+vlow_outside_while = -7.389946e-02 at= 1.335500e-08
+peak_to_peak_outside_while= 1.99275e+00
+supply_current_rms = 8.17056e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 8.11565e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.88392e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.921662e+00 at= 1.167500e-08
+vlow_outside_while = -6.328921e-02 at= 1.178500e-08
+peak_to_peak_outside_while= 1.98495e+00
+supply_current_rms = 9.73306e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 5.777835e-10 targ= 2.918899e-08 trig= 2.861121e-08
+fvco_outside_while = 1.73075e+09
+supply_current_rms_outside_while= 2.18747e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.27846e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928310e+00 at= 1.341500e-08
+vlow_outside_while = -8.311601e-02 at= 1.414500e-08
+peak_to_peak_outside_while= 2.01143e+00
+supply_current_rms = 2.19651e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.396455e-10 targ= 1.843434e-08 trig= 1.809470e-08
+fvco_outside_while = 2.94425e+09
+supply_current_rms_outside_while= 5.92151e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.63428e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928236e+00 at= 1.315500e-08
+vlow_outside_while = -8.425124e-02 at= 1.161500e-08
+peak_to_peak_outside_while= 2.01249e+00
+supply_current_rms = 5.58990e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.883517e-10 targ= 1.598556e-08 trig= 1.569721e-08
+fvco_outside_while = 3.46799e+09
+supply_current_rms_outside_while= 3.95428e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.96059e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927415e+00 at= 1.293500e-08
+vlow_outside_while = -8.202425e-02 at= 1.221500e-08
+peak_to_peak_outside_while= 2.00944e+00
+supply_current_rms = 3.91226e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.749599e-10 targ= 1.535789e-08 trig= 1.508293e-08
+fvco_outside_while = 3.63689e+09
+supply_current_rms_outside_while= 4.32936e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.31686e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925649e+00 at= 1.024500e-08
+vlow_outside_while = -8.117005e-02 at= 1.038500e-08
+peak_to_peak_outside_while= 2.00682e+00
+supply_current_rms = 4.27679e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.699945e-10 targ= 1.512048e-08 trig= 1.485049e-08
+fvco_outside_while = 3.70378e+09
+supply_current_rms_outside_while= 4.63461e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.61857e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925520e+00 at= 1.981500e-08
+vlow_outside_while = -8.056952e-02 at= 1.995500e-08
+peak_to_peak_outside_while= 2.00609e+00
+supply_current_rms = 4.56556e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.677555e-10 targ= 1.500843e-08 trig= 1.474068e-08
+fvco_outside_while = 3.73475e+09
+supply_current_rms_outside_while= 4.84555e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.83551e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925443e+00 at= 1.591500e-08
+vlow_outside_while = -8.105041e-02 at= 1.150500e-08
+peak_to_peak_outside_while= 2.00649e+00
+supply_current_rms = 4.78759e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.662862e-10 targ= 1.495283e-08 trig= 1.468654e-08
+fvco_outside_while = 3.75536e+09
+supply_current_rms_outside_while= 4.96387e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.95612e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925321e+00 at= 1.132500e-08
+vlow_outside_while = -8.091688e-02 at= 1.066500e-08
+peak_to_peak_outside_while= 2.00624e+00
+supply_current_rms = 4.90214e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.658055e-10 targ= 1.491882e-08 trig= 1.465302e-08
+fvco_outside_while = 3.76215e+09
+supply_current_rms_outside_while= 5.03670e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.02216e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925280e+00 at= 1.794500e-08
+vlow_outside_while = -8.081058e-02 at= 1.675500e-08
+peak_to_peak_outside_while= 2.00609e+00
+supply_current_rms = 4.97464e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.655607e-10 targ= 1.489559e-08 trig= 1.463003e-08
+fvco_outside_while = 3.76562e+09
+supply_current_rms_outside_while= 5.08546e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.07243e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925255e+00 at= 1.685500e-08
+vlow_outside_while = -8.070855e-02 at= 1.805500e-08
+peak_to_peak_outside_while= 2.00596e+00
+supply_current_rms = 5.02143e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
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+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
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+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
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+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
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+x3:x#branch 0
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+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.650126e-10 targ= 1.487817e-08 trig= 1.461316e-08
+fvco_outside_while = 3.77341e+09
+supply_current_rms_outside_while= 5.11835e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.10325e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925237e+00 at= 1.736500e-08
+vlow_outside_while = -8.066406e-02 at= 1.008500e-08
+peak_to_peak_outside_while= 2.00590e+00
+supply_current_rms = 5.05735e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
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+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
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+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
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+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.649621e-10 targ= 1.486547e-08 trig= 1.460051e-08
+fvco_outside_while = 3.77413e+09
+supply_current_rms_outside_while= 5.14554e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.13014e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925224e+00 at= 1.708500e-08
+vlow_outside_while = -8.061056e-02 at= 1.563500e-08
+peak_to_peak_outside_while= 2.00583e+00
+supply_current_rms = 5.08324e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15222e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
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+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
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+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
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+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.19019e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch -2.44395e-222
+x2:clk#branch 8.07794e-27
+x2:vdd#branch 5.32907e-15
+vmeas_current_gnd#branch 3.44866e-05
+vmeas_current_vdd#branch 3.44866e-05
+v2#branch -3.44867e-05
+x1:vctrl#branch 0
+x1:out#branch -8.07794e-27
+x1:vss#branch 3.44866e-05
+x1:vdd#branch -3.44866e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.647641e-10 targ= 1.485531e-08 trig= 1.459055e-08
+fvco_outside_while = 3.77695e+09
+supply_current_rms_outside_while= 5.17083e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.15132e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925208e+00 at= 1.363500e-08
+vlow_outside_while = -8.057643e-02 at= 1.271500e-08
+peak_to_peak_outside_while= 2.00578e+00
+supply_current_rms = 5.10305e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.647641e-10 targ= 1.485531e-08 trig= 1.459055e-08
+Original line no.: 0, new internal line no.: 12503:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.776946639089947e+09 " u=" 3.776946639089947e+09 " id=0
+fvco_outside_while = 3.77695e+09
+supply_current_rms_outside_while= 5.17083e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.15132e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.925208e+00 at= 1.363500e-08
+vlow_outside_while = -8.057643e-02 at= 1.271500e-08
+Original line no.: 0, new internal line no.: 12509:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.005784323259211e+00 " u=" 2.005784323259211e+00 " id=0
+peak_to_peak_outside_while= 2.00578e+00
+supply_current_rms = 5.10305e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 7.31221
+
+Total CPU time (seconds) = 167.869
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 1136.219 MB.
+Maximum ngspice program size = 684.684 MB.
+Current ngspice program size = 665.363 MB.
+
+Shared ngspice pages = 8.391 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.203 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_19y29.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_19y29.mag
new file mode 100755
index 0000000..fcedf46
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_19y29.mag
@@ -0,0 +1,839 @@
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+rect -1134 -1428 1183 -1388
+rect 1183 -1447 1243 -1438
+<< via2 >>
+rect -1297 1542 -1237 1602
+rect 9 -411 65 -355
+rect -1088 -691 -1032 -635
+rect 168 -688 172 -632
+rect 172 -688 224 -632
+rect 1492 -691 1552 -631
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+<< metal3 >>
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+rect -1302 1542 -1297 1602
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+rect -1302 1537 -1232 1542
+rect -1297 1438 -1237 1537
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+rect 1178 -1378 1248 -1373
+rect 1178 -1438 1183 -1378
+rect 1243 -1438 1248 -1378
+rect 1178 -1443 1248 -1438
+use vco_switch_n vco_switch_n_1
+timestamp 1646416938
+transform 1 0 -721 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_0
+timestamp 1646416938
+transform 1 0 -1367 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_3
+timestamp 1646416938
+transform 1 0 -78 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_2
+timestamp 1646416938
+transform 1 0 568 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -478 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 -271 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -410 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -616 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -204 0 1 1040
+box -112 -198 112 164
+<< labels >>
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1673 -1753 1873 -1553 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 -1354 -752 -1154 -552 1 vctrl
+port 3 n
+rlabel metal1 302 -1215 333 -1180 5 in
+port 0 n
+rlabel metal1 945 -1215 976 -1180 5 in
+port 0 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y01.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y01.mag
new file mode 100755
index 0000000..83a7abc
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y01.mag
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+rect 172 -688 224 -632
+rect 1492 -691 1552 -631
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+rect 7 -795 67 -735
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+rect -1088 -876 -1032 -820
+rect -342 -876 -286 -820
+rect 305 -876 361 -820
+rect 948 -876 1004 -820
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+rect -487 -1042 -437 -990
+rect -437 -1042 -427 -990
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+rect 210 -1035 226 -983
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+rect 848 -1035 852 -983
+rect 852 -1035 904 -983
+rect 904 -1035 908 -983
+rect 848 -1039 908 -1035
+rect -487 -1046 -427 -1042
+rect 1494 -985 1554 -981
+rect 1494 -1037 1498 -985
+rect 1498 -1037 1550 -985
+rect 1550 -1037 1554 -985
+rect 1494 -1041 1554 -1037
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+rect 1185 -1129 1241 -1073
+rect -1090 -1198 -1030 -1138
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+rect 303 -1198 363 -1138
+rect 946 -1198 1006 -1138
+rect -90 -1278 -30 -1218
+rect 557 -1358 617 -1298
+rect 1183 -1438 1243 -1378
+<< metal3 >>
+rect -1090 2025 -1030 2114
+rect 7 2110 67 2114
+rect -490 2103 -424 2108
+rect -490 2047 -485 2103
+rect -429 2047 -424 2103
+rect -490 2042 -424 2047
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+rect -1032 1964 -1027 2020
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+rect -1090 1707 -1030 1959
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+rect 2 2040 72 2045
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+rect -427 1794 -422 1854
+rect -492 1789 -422 1794
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+rect 166 1867 226 2114
+rect 794 2107 860 2112
+rect 794 2051 799 2107
+rect 855 2051 860 2107
+rect 794 2046 860 2051
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+rect -93 1729 -88 1785
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+rect -349 1635 -279 1642
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+rect 554 -1117 620 -1112
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+rect 298 -1198 303 -1138
+rect 363 -1198 368 -1138
+rect 298 -1205 368 -1198
+rect -95 -1218 -25 -1213
+rect -95 -1278 -90 -1218
+rect -30 -1278 -25 -1218
+rect -95 -1283 -25 -1278
+rect 557 -1293 617 -1117
+rect 974 -1133 1034 -881
+rect 1494 -976 1554 -696
+rect 1489 -981 1559 -976
+rect 1489 -1041 1494 -981
+rect 1554 -1041 1559 -981
+rect 1489 -1046 1559 -1041
+rect 941 -1138 1034 -1133
+rect 1176 -1073 1250 -1065
+rect 1176 -1129 1185 -1073
+rect 1241 -1129 1250 -1073
+rect 1176 -1137 1250 -1129
+rect 941 -1198 946 -1138
+rect 1006 -1198 1034 -1138
+rect 941 -1205 1034 -1198
+rect 552 -1298 622 -1293
+rect 552 -1358 557 -1298
+rect 617 -1358 622 -1298
+rect 552 -1363 622 -1358
+rect 1183 -1373 1243 -1137
+rect 1178 -1378 1248 -1373
+rect 1178 -1438 1183 -1378
+rect 1243 -1438 1248 -1378
+rect 1178 -1443 1248 -1438
+use vco_switch_n vco_switch_n_1
+timestamp 1646416938
+transform 1 0 -721 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_0
+timestamp 1646416938
+transform 1 0 -1367 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -478 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 -271 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use vco_switch_n vco_switch_n_3
+timestamp 1646416938
+transform 1 0 -78 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use vco_switch_n vco_switch_n_2
+timestamp 1646416938
+transform 1 0 568 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use vco_switch_n vco_switch_n_4
+timestamp 1646416938
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_5
+timestamp 1646416938
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_6
+timestamp 1646416938
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_7
+timestamp 1646416938
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1673 -1753 1873 -1553 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 302 -1215 333 -1180 5 in
+port 0 n
+rlabel metal1 945 -1215 976 -1180 5 in
+port 0 n
+rlabel metal1 -1354 -682 -1154 -482 1 vctrl
+port 3 n
+flabel metal1 1695 1542 1895 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+rlabel metal1 945 1625 976 1660 5 in
+port 0 n
+rlabel metal1 302 1625 333 1660 5 in
+port 0 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y25.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y25.mag
new file mode 100755
index 0000000..626c4ed
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y25.mag
@@ -0,0 +1,1149 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646421905
+<< error_s >>
+rect 7 2110 67 2114
+rect 2 2105 72 2110
+rect 2 2045 7 2105
+rect 2 2040 72 2045
+rect -93 1184 -35 1190
+rect 114 1184 172 1190
+rect -93 1150 -81 1184
+rect 114 1150 126 1184
+rect 321 1183 379 1189
+rect -93 1144 -35 1150
+rect 114 1144 172 1150
+rect 321 1149 333 1183
+rect 321 1143 379 1149
+rect -93 896 -35 902
+rect -93 862 -81 896
+rect -93 856 -35 862
+rect 871 109 901 121
+rect 871 25 901 37
+<< nwell >>
+rect -1098 242 1795 1691
+rect -1098 -1641 1795 -1149
+<< pwell >>
+rect -1098 1711 1795 2114
+rect -1098 1705 1176 1711
+rect 1250 1705 1795 1711
+rect -1098 1691 1160 1705
+rect 1264 1691 1795 1705
+rect -1098 -1129 1795 242
+rect -1098 -1135 1176 -1129
+rect 1250 -1135 1795 -1129
+rect -1098 -1149 1160 -1135
+rect 1264 -1149 1795 -1135
+<< psubdiff >>
+rect -1057 2059 -1020 2093
+rect 894 2059 1023 2093
+rect -1057 -28 -1023 216
+rect 894 -62 1023 -28
+rect -1057 -136 -1023 -62
+rect 989 -411 1023 -62
+rect -1057 -747 -1023 -647
+rect 989 -747 1023 -663
+rect -1057 -781 -1020 -747
+rect 894 -781 1023 -747
+<< nsubdiff >>
+rect -1059 1252 -986 1286
+rect 930 1252 1023 1286
+rect -1059 1226 -1025 1252
+rect -1059 565 -1025 572
+rect 989 565 1023 1252
+rect -1059 531 -986 565
+rect 930 531 1023 565
+rect -1059 278 -1025 531
+<< psubdiffcont >>
+rect -1020 2059 894 2093
+rect -1057 -62 894 -28
+rect -1057 -647 -1023 -136
+rect 989 -663 1023 -411
+rect -1020 -781 894 -747
+<< nsubdiffcont >>
+rect -986 1252 930 1286
+rect -1059 572 -1025 1226
+rect -986 531 930 565
+<< poly >>
+rect 589 1133 617 1199
+rect 879 204 909 247
+rect 590 -694 618 -628
+<< locali >>
+rect 894 2059 1023 2093
+rect -1059 1252 -986 1286
+rect 930 1252 1023 1286
+rect -1059 1226 -1025 1252
+rect 523 1149 683 1183
+rect -1059 565 -1025 572
+rect 989 565 1023 1252
+rect 1179 829 1420 863
+rect -1059 531 -986 565
+rect 930 531 1023 565
+rect -1059 278 -1025 531
+rect 1179 712 1213 829
+rect 1179 338 1256 372
+rect -244 320 -210 334
+rect -690 241 -656 318
+rect -545 286 -210 320
+rect -118 291 -94 324
+rect -118 290 -79 291
+rect -29 290 106 324
+rect -1057 -28 -1023 216
+rect -690 207 -610 241
+rect -610 140 -576 207
+rect -244 166 -210 286
+rect 72 166 106 290
+rect 349 241 383 308
+rect -610 131 -516 140
+rect -478 132 -210 166
+rect -97 134 306 166
+rect -102 132 306 134
+rect 349 132 383 207
+rect 611 204 645 309
+rect 959 274 1053 308
+rect 1222 295 1256 338
+rect 1019 259 1053 274
+rect 1119 259 1185 295
+rect 1019 225 1185 259
+rect 611 187 919 204
+rect 611 170 898 187
+rect 611 133 645 170
+rect 853 154 898 170
+rect -610 106 -523 131
+rect -244 68 -210 132
+rect 272 68 306 132
+rect 1019 111 1053 225
+rect 1119 212 1185 225
+rect 1222 261 1329 295
+rect 1373 261 1517 295
+rect 1222 168 1256 261
+rect 1329 246 1390 261
+rect 1213 134 1256 168
+rect 951 85 1053 111
+rect 917 77 1053 85
+rect 917 51 951 77
+rect 894 -62 1023 -28
+rect -1057 -136 -1023 -62
+rect 989 -411 1023 -62
+rect 1179 -70 1255 -36
+rect 1221 -122 1255 -70
+rect 1221 -156 1375 -122
+rect -1057 -747 -1023 -647
+rect 528 -678 680 -644
+rect 989 -747 1023 -663
+rect 894 -781 1023 -747
+<< viali >>
+rect -1057 2059 -1020 2093
+rect -1020 2059 894 2093
+rect -986 1252 930 1286
+rect -517 410 -378 444
+rect -113 412 -79 446
+rect 364 416 741 450
+rect 1091 406 1125 810
+rect -610 207 -576 241
+rect 349 207 383 241
+rect -460 7 -352 41
+rect -131 10 -97 44
+rect 365 15 629 49
+rect 821 8 855 42
+rect -1057 -781 -1020 -747
+rect -1020 -781 894 -747
+<< metal1 >>
+rect -1075 2093 1640 2114
+rect -1075 2059 -1057 2093
+rect 894 2059 1640 2093
+rect -1075 2051 1640 2059
+rect 210 1857 262 1863
+rect -437 1850 -385 1856
+rect 210 1799 262 1805
+rect 852 1857 904 1863
+rect 852 1799 904 1805
+rect 1498 1855 1550 1861
+rect -437 1792 -385 1798
+rect -739 1778 -687 1784
+rect -428 1752 -394 1792
+rect -97 1787 -23 1793
+rect -739 1720 -687 1726
+rect -97 1727 -90 1787
+rect -30 1727 -23 1787
+rect 218 1752 253 1799
+rect 550 1786 624 1792
+rect -97 1721 -23 1727
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+rect 617 1726 624 1786
+rect 861 1752 895 1799
+rect 1498 1797 1550 1803
+rect 1176 1769 1250 1775
+rect 550 1720 624 1726
+rect 1176 1709 1183 1769
+rect 1243 1709 1250 1769
+rect 1507 1752 1541 1797
+rect -1099 1702 -1021 1709
+rect -1099 1642 -1090 1702
+rect -1030 1660 -1021 1702
+rect -353 1702 -275 1709
+rect -1030 1642 -956 1660
+rect -1099 1625 -956 1642
+rect -353 1642 -344 1702
+rect -284 1660 -275 1702
+rect 294 1702 372 1709
+rect -284 1642 -237 1660
+rect -353 1625 -237 1642
+rect 294 1642 303 1702
+rect 363 1660 372 1702
+rect 937 1702 1015 1709
+rect 1176 1703 1250 1709
+rect 363 1642 379 1660
+rect 294 1625 379 1642
+rect 937 1642 946 1702
+rect 1006 1660 1015 1702
+rect 1006 1642 1022 1660
+rect 937 1625 1022 1642
+rect 1695 1306 1895 2381
+rect -1038 1286 1895 1306
+rect -1038 1252 -986 1286
+rect 930 1252 1895 1286
+rect -1038 1237 1895 1252
+rect -1003 1236 81 1237
+rect -964 1045 -918 1236
+rect -870 1047 -824 1236
+rect -758 1193 -652 1205
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+rect 298 -1205 368 -1198
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+rect -30 -1278 -25 -1218
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+rect 1489 -1041 1494 -981
+rect 1554 -1041 1559 -981
+rect 1489 -1046 1559 -1041
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+rect 1176 -1073 1250 -1065
+rect 1176 -1129 1185 -1073
+rect 1241 -1129 1250 -1073
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+rect 552 -1363 622 -1358
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+rect 1178 -1378 1248 -1373
+rect 1178 -1438 1183 -1378
+rect 1243 -1438 1248 -1378
+rect 1178 -1443 1248 -1438
+use vco_switch_n vco_switch_n_1
+timestamp 1646416938
+transform 1 0 -721 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_0
+timestamp 1646416938
+transform 1 0 -1367 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_3
+timestamp 1646416938
+transform 1 0 -78 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_2
+timestamp 1646416938
+transform 1 0 568 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -478 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 -271 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 -271 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_1
+timestamp 1646420956
+transform 1 0 -64 0 1 791
+box -112 -158 112 124
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use vco_switch_n vco_switch_n_4
+timestamp 1646416938
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_5
+timestamp 1646416938
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_0
+timestamp 1646420956
+transform 1 0 -64 0 1 1079
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_KQRM7Z sky130_fd_pr__pfet_01v8_KQRM7Z_0
+timestamp 1646420801
+transform 1 0 143 0 1 1019
+box -112 -218 112 184
+use vco_switch_n vco_switch_n_6
+timestamp 1646416938
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_7
+timestamp 1646416938
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1673 -1753 1873 -1553 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 302 -1215 333 -1180 5 in
+port 0 n
+rlabel metal1 945 -1215 976 -1180 5 in
+port 0 n
+rlabel metal1 -1354 -682 -1154 -482 1 vctrl
+port 3 n
+rlabel metal1 945 1625 976 1660 5 in
+port 0 n
+rlabel metal1 302 1625 333 1660 5 in
+port 0 n
+flabel metal1 1695 2181 1895 2381 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y38.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y38.mag
new file mode 100755
index 0000000..6fba62c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_20y38.mag
@@ -0,0 +1,1215 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646422707
+<< error_s >>
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+rect 871 109 901 121
+rect 871 25 901 37
+<< nwell >>
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+rect -1098 -1641 1795 -1149
+<< pwell >>
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+rect -1098 1705 1176 1711
+rect 1250 1705 1795 1711
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+rect 1264 1691 1795 1705
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+rect -1098 -1135 1176 -1129
+rect 1250 -1135 1795 -1129
+rect -1098 -1149 1160 -1135
+rect 1264 -1149 1795 -1135
+<< psubdiff >>
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+rect 894 -781 1023 -747
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+rect 989 565 1023 1252
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+rect 930 531 1023 565
+rect -1059 278 -1025 531
+<< psubdiffcont >>
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+rect -1057 -62 894 -28
+rect -1057 -647 -1023 -136
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+rect -1020 -781 894 -747
+<< nsubdiffcont >>
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+rect -1059 572 -1025 1226
+rect -986 531 930 565
+<< poly >>
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+rect 879 204 909 247
+rect 590 -694 618 -628
+<< locali >>
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+transform 1 0 568 0 -1 -304
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+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -478 0 1 -537
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+timestamp 1645726643
+transform 1 0 -271 0 1 -397
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+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 -271 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_1
+timestamp 1646420956
+transform 1 0 -64 0 1 791
+box -112 -158 112 124
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use vco_switch_n vco_switch_n_4
+timestamp 1646416938
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_5
+timestamp 1646416938
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_0
+timestamp 1646420956
+transform 1 0 -64 0 1 1079
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_KQRM7Z sky130_fd_pr__pfet_01v8_KQRM7Z_0
+timestamp 1646420801
+transform 1 0 143 0 1 1019
+box -112 -218 112 184
+use vco_switch_n vco_switch_n_6
+timestamp 1646416938
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_7
+timestamp 1646416938
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1673 -1753 1873 -1553 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 302 -1215 333 -1180 5 in
+port 0 n
+rlabel metal1 945 -1215 976 -1180 5 in
+port 0 n
+rlabel metal1 -1354 -682 -1154 -482 1 vctrl
+port 3 n
+rlabel metal1 945 1625 976 1660 5 in
+port 0 n
+rlabel metal1 302 1625 333 1660 5 in
+port 0 n
+flabel metal1 1695 2181 1895 2381 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_21y27.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_21y27.mag
new file mode 100755
index 0000000..db85ca9
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_21y27.mag
@@ -0,0 +1,1301 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646425657
+<< error_s >>
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+rect 871 25 901 37
+<< nwell >>
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+rect -1098 -1641 1795 -1149
+<< pwell >>
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+rect -1098 1705 1176 1711
+rect 1250 1705 1795 1711
+rect -1098 1691 1160 1705
+rect 1264 1691 1795 1705
+rect -1098 -1129 1795 242
+rect -1098 -1135 1176 -1129
+rect 1250 -1135 1795 -1129
+rect -1098 -1149 1160 -1135
+rect 1264 -1149 1795 -1135
+<< psubdiff >>
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+rect -1057 -747 -1023 -647
+rect 989 -747 1023 -663
+rect -1057 -781 -1020 -747
+rect 894 -781 1023 -747
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+rect 930 531 1023 565
+rect -1059 278 -1025 531
+rect -1049 -1593 -1011 -1559
+rect 1565 -1593 1602 -1559
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+rect -1057 -62 894 -28
+rect -1057 -647 -1023 -136
+rect 989 -663 1023 -411
+rect -1020 -781 894 -747
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+rect -1059 572 -1025 1226
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+rect -1011 -1593 1565 -1559
+<< poly >>
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+rect 879 204 909 247
+rect 590 -694 618 -628
+<< locali >>
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+rect 894 -781 1023 -747
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+rect -1020 2059 894 2093
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+rect -1051 -1598 1688 -1593
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+use vco_switch_n vco_switch_n_1
+timestamp 1646416938
+transform 1 0 -721 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_0
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+transform 1 0 -1367 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_3
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+transform 1 0 -78 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_2
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+transform 1 0 568 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -478 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 -271 0 1 -397
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+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
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+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 -271 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_1
+timestamp 1646420956
+transform 1 0 -64 0 1 791
+box -112 -158 112 124
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use vco_switch_n vco_switch_n_4
+timestamp 1646416938
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_5
+timestamp 1646416938
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_0
+timestamp 1646420956
+transform 1 0 -64 0 1 1079
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_KQRM7Z sky130_fd_pr__pfet_01v8_KQRM7Z_0
+timestamp 1646420801
+transform 1 0 143 0 1 1019
+box -112 -218 112 184
+use vco_switch_n vco_switch_n_6
+timestamp 1646416938
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_7
+timestamp 1646416938
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+rlabel metal1 302 -1215 333 -1180 5 in
+port 0 n
+rlabel metal1 945 -1215 976 -1180 5 in
+port 0 n
+rlabel metal1 945 1625 976 1660 5 in
+port 0 n
+rlabel metal1 302 1625 333 1660 5 in
+port 0 n
+rlabel metal1 -1753 -752 -1553 -552 1 vctrl
+port 3 n
+flabel metal1 2104 118 2304 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1633 2181 1833 2381 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1893 2181 2093 2381 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_21y48.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_21y48.mag
new file mode 100755
index 0000000..d37d28f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_4-3-2022_21y48.mag
@@ -0,0 +1,1301 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646426578
+<< error_s >>
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+rect 871 25 901 37
+<< nwell >>
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+rect -1098 -1641 1795 -1149
+<< pwell >>
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+rect 1250 1705 1795 1711
+rect -1098 1691 1160 1705
+rect 1264 1691 1795 1705
+rect -1098 -1129 1795 242
+rect -1098 -1135 1176 -1129
+rect 1250 -1135 1795 -1129
+rect -1098 -1149 1160 -1135
+rect 1264 -1149 1795 -1135
+<< psubdiff >>
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+rect 894 -62 1023 -28
+rect -1057 -136 -1023 -62
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+rect -1057 -747 -1023 -647
+rect 989 -747 1023 -663
+rect -1057 -781 -1020 -747
+rect 894 -781 1023 -747
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+rect 930 531 1023 565
+rect -1059 278 -1025 531
+rect -1049 -1593 -1011 -1559
+rect 1565 -1593 1602 -1559
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+rect -1057 -62 894 -28
+rect -1057 -647 -1023 -136
+rect 989 -663 1023 -411
+rect -1020 -781 894 -747
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+rect -1059 572 -1025 1226
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+rect -1011 -1593 1565 -1559
+<< poly >>
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+rect 879 204 909 247
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+<< locali >>
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+rect 894 -781 1023 -747
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+rect 1565 -1593 1581 -1559
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+rect -1020 2059 894 2093
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+rect -1051 -1598 1688 -1593
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+rect -1051 -1607 1843 -1598
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+use vco_switch_n vco_switch_n_1
+timestamp 1646416938
+transform 1 0 -721 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_0
+timestamp 1646416938
+transform 1 0 -1367 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_3
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+transform 1 0 -78 0 -1 -304
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_2
+timestamp 1646416938
+transform 1 0 568 0 -1 -304
+box 376 462 987 1215
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -478 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 -271 0 1 -397
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+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
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+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 -271 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_1
+timestamp 1646420956
+transform 1 0 -64 0 1 791
+box -112 -158 112 124
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use vco_switch_n vco_switch_n_4
+timestamp 1646416938
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_5
+timestamp 1646416938
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_0
+timestamp 1646420956
+transform 1 0 -64 0 1 1079
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_KQRM7Z sky130_fd_pr__pfet_01v8_KQRM7Z_0
+timestamp 1646420801
+transform 1 0 143 0 1 1019
+box -112 -218 112 184
+use vco_switch_n vco_switch_n_6
+timestamp 1646416938
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use vco_switch_n vco_switch_n_7
+timestamp 1646416938
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+rlabel metal1 -1753 -752 -1553 -552 1 vctrl
+port 3 n
+flabel metal1 2104 118 2304 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1633 2181 1833 2381 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1893 2181 2093 2381 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 -1436 1674 -1404 1706 1 sel0
+port 4 n
+rlabel metal1 -1359 1519 -1327 1551 1 sel1
+port 5 n
+rlabel metal1 -1279 1445 -1247 1477 1 sel2
+port 6 n
+rlabel metal1 -1190 1364 -1158 1396 1 sel3
+port 7 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_5-3-2022_11y30 b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_5-3-2022_11y30
new file mode 100755
index 0000000..46399e5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_-_seccopy_5-3-2022_11y30
@@ -0,0 +1,1342 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646475960
+<< error_s >>
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+rect 871 25 901 37
+<< nwell >>
+rect -1098 242 1795 1691
+rect -1098 -1641 1795 -1149
+<< pwell >>
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+rect 1250 1705 1795 1711
+rect -1098 1691 1160 1705
+rect 1264 1691 1795 1705
+rect -1098 -1129 1795 242
+rect -1098 -1135 1176 -1129
+rect 1250 -1135 1795 -1129
+rect -1098 -1149 1160 -1135
+rect 1264 -1149 1795 -1135
+<< psubdiff >>
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+rect -1057 -136 -1023 -62
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+rect -1057 -747 -1023 -647
+rect 989 -747 1023 -663
+rect -1057 -781 -1020 -747
+rect 894 -781 1023 -747
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+rect 930 1252 1023 1286
+rect -1059 1226 -1025 1252
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+rect 930 531 1023 565
+rect -1059 278 -1025 531
+rect -1049 -1593 -1011 -1559
+rect 1565 -1593 1602 -1559
+<< psubdiffcont >>
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+rect -1057 -62 894 -28
+rect -1057 -647 -1023 -136
+rect 989 -663 1023 -411
+rect -1020 -781 894 -747
+<< nsubdiffcont >>
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+rect -1059 572 -1025 1226
+rect -986 531 930 565
+rect -1011 -1593 1565 -1559
+<< poly >>
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+rect 879 204 909 247
+rect 590 -694 618 -628
+<< locali >>
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+rect 894 -781 1023 -747
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+rect 1565 -1593 1581 -1559
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+rect -1051 -1598 1688 -1593
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+rect -1051 -1607 1843 -1598
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+transform 1 0 568 0 -1 -304
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+timestamp 1645190808
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+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 -271 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -891 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -685 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_NNRSEG XM16
+timestamp 1646403993
+transform -1 0 -64 0 1 -577
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_MV8TJR sky130_fd_pr__nfet_01v8_MV8TJR_0
+timestamp 1646403993
+transform -1 0 143 0 1 -517
+box -76 -177 76 177
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_NNRSEG sky130_fd_pr__nfet_01v8_NNRSEG_0
+timestamp 1646403993
+transform -1 0 -64 0 1 -299
+box -76 -117 76 117
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1646413593
+transform 1 0 1357 0 1 45
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 -271 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_1
+timestamp 1646420956
+transform 1 0 -64 0 1 791
+box -112 -158 112 124
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 562
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use vco_switch_p vco_switch_p_1
+timestamp 1646473968
+transform 1 0 -721 0 -1 2536
+box 376 462 987 1215
+use vco_switch_p vco_switch_p_0
+timestamp 1646473968
+transform 1 0 -1367 0 -1 2536
+box 376 462 987 1215
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -482 0 1 1040
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -688 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -894 0 1 1039
+box -112 -198 112 164
+use vco_switch_p vco_switch_p_2
+timestamp 1646473968
+transform 1 0 -78 0 -1 2536
+box 376 462 987 1215
+use sky130_fd_pr__pfet_01v8_4XEGTB sky130_fd_pr__pfet_01v8_4XEGTB_0
+timestamp 1646420956
+transform 1 0 -64 0 1 1079
+box -112 -158 112 124
+use sky130_fd_pr__pfet_01v8_KQRM7Z sky130_fd_pr__pfet_01v8_KQRM7Z_0
+timestamp 1646420801
+transform 1 0 143 0 1 1019
+box -112 -218 112 184
+use vco_switch_p vco_switch_p_3
+timestamp 1646473968
+transform 1 0 568 0 -1 2536
+box 376 462 987 1215
+<< labels >>
+rlabel metal1 -1753 -752 -1553 -552 1 vctrl
+port 3 n
+flabel metal1 2104 118 2304 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+flabel metal1 1633 2181 1833 2381 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1893 2181 2093 2381 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+rlabel metal1 -1436 1674 -1404 1706 1 sel0
+port 4 n
+rlabel metal1 -1359 1519 -1327 1551 1 sel1
+port 5 n
+rlabel metal1 -1279 1445 -1247 1477 1 sel2
+port 6 n
+rlabel metal1 -1190 1364 -1158 1396 1 sel3
+port 7 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_pre-labelling.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_pre-labelling.spice
new file mode 100755
index 0000000..454edbe
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dp9_pre-labelling.spice
@@ -0,0 +1,662 @@
+* NGSPICE file created from 3-stage_cs-vco_dp9.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n33_n337# w_n109_n340# 0.11fF
+C1 w_n109_n340# a_n73_n240# 0.19fF
+C2 a_15_n240# a_n73_n240# 0.20fF
+C3 a_15_n240# w_n109_n340# 0.17fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_18_n220# a_63_n317# 0.00fF
+C1 a_n78_n220# a_18_n220# 0.31fF
+C2 a_n33_251# w_n209_n320# 0.14fF
+C3 a_63_n317# a_n33_251# 0.02fF
+C4 w_n209_n320# a_n129_n317# 0.14fF
+C5 a_n173_n220# a_18_n220# 0.14fF
+C6 a_63_n317# a_n129_n317# 0.03fF
+C7 a_n78_n220# a_n33_251# 0.00fF
+C8 a_114_n220# w_n209_n320# 0.33fF
+C9 a_114_n220# a_63_n317# 0.00fF
+C10 a_n78_n220# a_n129_n317# 0.00fF
+C11 a_n78_n220# a_114_n220# 0.18fF
+C12 a_63_n317# w_n209_n320# 0.14fF
+C13 a_n173_n220# a_n129_n317# 0.00fF
+C14 a_n173_n220# a_114_n220# 0.07fF
+C15 a_n78_n220# w_n209_n320# 0.33fF
+C16 a_18_n220# a_n33_251# 0.00fF
+C17 a_n173_n220# w_n209_n320# 0.28fF
+C18 a_18_n220# a_114_n220# 0.31fF
+C19 a_n78_n220# a_n173_n220# 0.31fF
+C20 a_n33_251# a_n129_n317# 0.02fF
+C21 a_18_n220# w_n209_n320# 0.28fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
++ VSUBS
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n33_67# w_n112_n170# 0.19fF
+C1 a_18_n108# w_n112_n170# 0.15fF
+C2 a_n76_n108# w_n112_n170# 0.15fF
+C3 a_18_n108# a_n33_67# 0.01fF
+C4 a_n76_n108# a_n33_67# 0.01fF
+C5 a_18_n108# a_n76_n108# 0.22fF
+C6 a_18_n108# VSUBS -0.13fF
+C7 a_n76_n108# VSUBS -0.13fF
+C8 a_n33_67# VSUBS -0.07fF
+C9 w_n112_n170# VSUBS 0.21fF
+.ends
+
+.subckt sky130_fd_sc_hd__inv_1 A VGND VPWR Y VNB VPB
+X0 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=1.69e+11p pd=1.82e+06u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u
+X1 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.6e+11p pd=2.52e+06u as=2.6e+11p ps=2.52e+06u w=1e+06u l=150000u
+C0 Y VPB 0.12fF
+C1 VPWR Y 0.26fF
+C2 A Y 0.14fF
+C3 VPWR VGND 0.01fF
+C4 A VGND 0.06fF
+C5 VPWR VPB 0.33fF
+C6 Y VGND 0.20fF
+C7 A VPB 0.07fF
+C8 VPWR A 0.06fF
+C9 VGND VNB 0.37fF
+C10 Y VNB 0.06fF
+C11 VPWR VNB -0.02fF
+C12 A VNB 0.15fF
+C13 VPB VNB 0.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+C0 a_18_n73# a_n18_n99# 0.03fF
+C1 a_18_n73# a_n76_n73# 0.05fF
+C2 a_18_n73# VSUBS 0.02fF
+C3 a_n76_n73# VSUBS 0.02fF
+C4 a_n18_n99# VSUBS 0.13fF
+.ends
+
+.subckt vco_switch_n in sel out vdd vss x1/Y
+XXM25 vdd in out x1/Y vss sky130_fd_pr__pfet_01v8_ACAZ2B
+Xx1 sel vss vdd x1/Y vss vdd sky130_fd_sc_hd__inv_1
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss x1/Y out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+C0 in x1/Y 0.27fF
+C1 sel x1/Y 0.35fF
+C2 sel in 0.55fF
+C3 out vdd 0.11fF
+C4 vdd x1/Y 0.07fF
+C5 in vdd 0.30fF
+C6 sel vdd 0.04fF
+C7 out x1/Y 0.07fF
+C8 out in 0.19fF
+C9 sel out 0.07fF
+C10 sel vss 0.75fF
+C11 x1/Y vss 0.81fF
+C12 vdd vss 0.60fF
+C13 out vss 0.16fF
+C14 in vss 0.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
++ VSUBS
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+C0 a_n76_n156# a_n33_115# 0.00fF
+C1 a_18_n156# a_n33_115# 0.00fF
+C2 a_n76_n156# w_n112_n218# 0.18fF
+C3 a_18_n156# w_n112_n218# 0.18fF
+C4 a_18_n156# a_n76_n156# 0.24fF
+C5 a_n33_115# w_n112_n218# 0.19fF
+C6 a_18_n156# VSUBS -0.18fF
+C7 a_n76_n156# VSUBS -0.18fF
+C8 a_n33_115# VSUBS -0.07fF
+C9 w_n112_n218# VSUBS 0.27fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n136# a_n33_95# 0.00fF
+C1 a_18_n136# a_n33_95# 0.00fF
+C2 a_n76_n136# w_n112_n198# 0.16fF
+C3 a_18_n136# w_n112_n198# 0.16fF
+C4 a_18_n136# a_n76_n136# 0.20fF
+C5 a_n33_95# w_n112_n198# 0.19fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_15_n120# a_n73_n120# 0.15fF
+C1 a_15_n120# a_n33_142# 0.00fF
+C2 a_n73_n120# a_n33_142# 0.01fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_18_n129# a_n76_n129# 0.21fF
+C1 a_18_n129# a_n33_n217# 0.00fF
+C2 a_n76_n129# a_n33_n217# 0.00fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+C0 a_18_n89# a_n76_n89# 0.19fF
+C1 a_18_n89# a_n33_n177# 0.01fF
+C2 a_n76_n89# a_n33_n177# 0.00fF
+C3 a_18_n89# VSUBS 0.00fF
+C4 a_n76_n89# VSUBS 0.00fF
+C5 a_n33_n177# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n69# a_n76_n69# 0.17fF
+C1 a_18_n69# a_n33_n157# 0.01fF
+C2 a_n76_n69# a_n33_n157# 0.00fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+C0 a_18_n29# a_n76_n29# 0.12fF
+C1 a_18_n29# a_n33_n117# 0.01fF
+C2 a_n76_n29# a_n33_n117# 0.01fF
+C3 a_18_n29# VSUBS 0.00fF
+C4 a_n76_n29# VSUBS 0.00fF
+C5 a_n33_n117# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n96# a_n73_n96# 0.06fF
+C1 a_15_n96# a_n33_33# 0.00fF
+C2 a_n73_n96# a_n33_33# 0.00fF
+C3 a_15_n96# VSUBS 0.02fF
+C4 a_n73_n96# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n276# a_n33_235# 0.00fF
+C1 a_18_n276# a_n33_235# 0.00fF
+C2 a_n76_n276# w_n112_n338# 0.32fF
+C3 a_18_n276# w_n112_n338# 0.32fF
+C4 a_18_n276# a_n76_n276# 0.46fF
+C5 a_n33_235# w_n112_n338# 0.19fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n76_n209# 0.35fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n76_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n76_n209# 0.47fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n76_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
++ VSUBS
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+C0 a_n73_n144# a_n33_n241# 0.00fF
+C1 a_15_n144# a_n33_n241# 0.00fF
+C2 a_n73_n144# w_n109_n244# 0.13fF
+C3 a_15_n144# w_n109_n244# 0.13fF
+C4 a_15_n144# a_n73_n144# 0.15fF
+C5 a_n33_n241# w_n109_n244# 0.14fF
+C6 a_15_n144# VSUBS -0.11fF
+C7 a_n73_n144# VSUBS -0.11fF
+C8 a_n33_n241# VSUBS -0.01fF
+C9 w_n109_n244# VSUBS 0.29fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_15_n103# a_n73_n103# 0.07fF
+C1 a_15_n103# a_n33_63# 0.00fF
+C2 a_n73_n103# a_n33_63# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
++ VSUBS
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+C0 a_n76_n96# a_n33_55# 0.01fF
+C1 a_18_n96# a_n33_55# 0.01fF
+C2 a_n76_n96# w_n112_n158# 0.11fF
+C3 a_18_n96# w_n112_n158# 0.11fF
+C4 a_18_n96# a_n76_n96# 0.13fF
+C5 a_n33_55# w_n112_n158# 0.19fF
+C6 a_18_n96# VSUBS -0.11fF
+C7 a_n76_n96# VSUBS -0.11fF
+C8 a_n33_55# VSUBS -0.07fF
+C9 w_n112_n158# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_15_n175# a_n73_n175# 0.16fF
+C1 a_15_n175# a_n33_135# 0.00fF
+C2 a_n73_n175# a_n33_135# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+C0 a_n73_n236# a_n33_395# 0.00fF
+C1 a_15_n236# a_n33_395# 0.00fF
+C2 a_n73_n236# w_n109_n298# 0.26fF
+C3 a_15_n236# w_n109_n298# 0.26fF
+C4 a_15_n236# a_n73_n236# 0.32fF
+C5 a_n33_395# w_n109_n298# 0.14fF
+C6 a_15_n236# VSUBS -0.25fF
+C7 a_n73_n236# VSUBS -0.25fF
+C8 a_n33_395# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.50fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+C0 a_n73_n64# a_n33_n161# 0.00fF
+C1 a_15_n64# a_n33_n161# 0.00fF
+C2 a_n73_n64# w_n109_n164# 0.06fF
+C3 a_15_n64# w_n109_n164# 0.06fF
+C4 a_15_n64# a_n73_n64# 0.07fF
+C5 a_n33_n161# w_n109_n164# 0.14fF
+C6 a_15_n64# VSUBS -0.06fF
+C7 a_n73_n64# VSUBS -0.06fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
++ VSUBS
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n76_n72# w_n112_n134# 0.15fF
+C1 a_18_n72# w_n112_n134# 0.15fF
+C2 a_18_n72# a_n76_n72# 0.22fF
+C3 a_n18_n98# w_n112_n134# 0.05fF
+C4 a_18_n72# VSUBS -0.13fF
+C5 a_n76_n72# VSUBS -0.13fF
+C6 a_n18_n98# VSUBS 0.00fF
+C7 w_n112_n134# VSUBS 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
++ VSUBS
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+C0 a_n73_n100# w_n109_n136# 0.10fF
+C1 a_15_n100# w_n109_n136# 0.10fF
+C2 a_15_n100# a_n73_n100# 0.13fF
+C3 a_n15_n132# w_n109_n136# 0.05fF
+C4 a_15_n100# VSUBS -0.08fF
+C5 a_n73_n100# VSUBS -0.08fF
+C6 a_n15_n132# VSUBS 0.00fF
+C7 w_n109_n136# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+C0 a_15_n96# a_n73_n96# 0.08fF
+C1 a_n73_n96# a_n73_56# 0.03fF
+C2 a_15_n96# VSUBS 0.02fF
+C3 a_n73_n96# VSUBS 0.02fF
+C4 a_n73_56# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
++ VSUBS
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n76_n108# a_n68_67# 0.03fF
+C1 a_n76_n108# w_n112_n170# 0.15fF
+C2 a_18_n108# w_n112_n170# 0.15fF
+C3 a_18_n108# a_n76_n108# 0.22fF
+C4 a_n68_67# w_n112_n170# 0.16fF
+C5 a_18_n108# VSUBS -0.13fF
+C6 a_n76_n108# VSUBS -0.13fF
+C7 a_n68_67# VSUBS -0.01fF
+C8 w_n112_n170# VSUBS 0.21fF
+.ends
+
+.subckt vco_switch_p in sel out vss vdd li_610_903#
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out vss sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd li_610_903# vdd sel vss sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 li_610_903# sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd li_610_903# in out vss sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+C0 in sel 0.75fF
+C1 sel vdd 0.91fF
+C2 in out 0.19fF
+C3 in li_610_903# 0.11fF
+C4 out vdd -0.04fF
+C5 li_610_903# vdd 0.06fF
+C6 sel out 0.14fF
+C7 li_610_903# sel 0.35fF
+C8 li_610_903# out 0.05fF
+C9 in vdd 0.40fF
+C10 sel vss 0.75fF
+C11 in vss 0.01fF
+C12 li_610_903# vss 0.05fF
+C13 out vss 0.15fF
+C14 vdd vss 0.50fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 a_15_n22# a_n72_n22# 0.09fF
+C1 w_n109_n58# a_n15_n53# 0.05fF
+C2 a_15_n22# w_n109_n58# 0.08fF
+C3 a_n72_n22# w_n109_n58# 0.14fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n33_33# a_n73_n68# 0.00fF
+C1 a_15_n68# a_n73_n68# 0.04fF
+C2 a_15_n68# a_n33_33# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt x3-stage_cs-vco_dp9 vdd vss out vctrl sel0 sel1 sel2 sel3
+XXM12 li_1329_246# vdd vdd li_917_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd vdd out vdd li_1329_246# li_1329_246# li_1329_246# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+Xvco_switch_n_1 vctrl sel1 vco_switch_n_1/out vdd vss vco_switch_n_1/x1/Y vco_switch_n
+Xsky130_fd_pr__pfet_01v8_KQRM7Z_0 vdd li_n517_410# vdd vco_switch_p_1/out vss sky130_fd_pr__pfet_01v8_KQRM7Z
+XXM25 vdd vco_switch_p_3/in vdd vco_switch_p_3/in vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM13 vss li_1329_246# li_917_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 li_1329_246# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+Xvco_switch_n_2 vctrl sel3 vco_switch_n_2/out vdd vss vco_switch_n_2/x1/Y vco_switch_n
+Xsky130_fd_pr__nfet_01v8_MV8TJR_0 li_n460_7# vss vco_switch_n_1/out vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM26 vco_switch_p_3/in vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_3 vctrl sel2 vco_switch_n_3/out vdd vss vco_switch_n_3/x1/Y vco_switch_n
+Xsky130_fd_pr__nfet_01v8_NNRSEG_0 li_n460_7# vco_switch_n_0/out vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16 li_n460_7# vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM25B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM4GUT li_n545_286# li_n118_290# vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM16_1 li_n460_7# vss vco_switch_n_3/out vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B_1 li_n460_7# vss vco_switch_n_2/out vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XM1GUT li_n517_410# a_879_204# li_n545_286# vdd vss sky130_fd_pr__pfet_01v8_MP1P4U
+XXM2 li_n460_7# li_n545_286# a_879_204# vss sky130_fd_pr__nfet_01v8_EMZ8SC
+Xsky130_fd_pr__pfet_01v8_4XEGTB_0 vdd vdd vco_switch_p_3/in li_n517_410# vss sky130_fd_pr__pfet_01v8_4XEGTB
+Xsky130_fd_pr__pfet_01v8_4XEGTB_1 vdd vdd vco_switch_p_0/out li_n517_410# vss sky130_fd_pr__pfet_01v8_4XEGTB
+XXM6 li_n118_290# a_879_204# vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXM11B_1 vdd vdd vco_switch_p_3/out li_n517_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5GUT a_879_204# vdd li_n118_290# vdd vss sky130_fd_pr__pfet_01v8_MP3P0U
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B li_n460_7# vss vco_switch_n_2/out vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XMX3GUT vdd li_n545_286# vdd li_n118_290# vss sky130_fd_pr__pfet_01v8_MP0P75
+Xvco_switch_p_0 vco_switch_p_3/in sel0 vco_switch_p_0/out vss vdd vco_switch_p_0/li_610_903#
++ vco_switch_p
+XXM11_1 vdd vdd vco_switch_p_2/out li_n517_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_2 vco_switch_p_3/in sel2 vco_switch_p_2/out vss vdd vco_switch_p_2/li_610_903#
++ vco_switch_p
+Xvco_switch_p_1 vco_switch_p_3/in sel1 vco_switch_p_1/out vss vdd vco_switch_p_1/li_610_903#
++ vco_switch_p
+XXM21 vdd li_917_51# vdd a_879_204# vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11B li_n517_410# vdd vco_switch_p_3/out vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_3 vco_switch_p_3/in sel3 vco_switch_p_3/out vss vdd vco_switch_p_3/li_610_903#
++ vco_switch_p
+XXM22 a_879_204# vss li_917_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+Xvco_switch_n_0 vctrl sel0 vco_switch_n_0/out vdd vss vco_switch_n_0/x1/Y vco_switch_n
+C0 vco_switch_n_1/out vdd 0.11fF
+C1 vco_switch_n_2/out sel3 0.04fF
+C2 vco_switch_p_1/li_610_903# vco_switch_p_2/li_610_903# 0.00fF
+C3 vco_switch_p_2/out vco_switch_p_2/li_610_903# 0.02fF
+C4 vco_switch_p_2/out vco_switch_p_3/out 0.34fF
+C5 vco_switch_p_2/li_610_903# vco_switch_p_3/out 0.01fF
+C6 vctrl vco_switch_n_0/out 1.74fF
+C7 vco_switch_n_1/out sel3 0.02fF
+C8 li_n517_410# vco_switch_p_0/out 0.17fF
+C9 vco_switch_p_1/li_610_903# vdd 0.02fF
+C10 vco_switch_n_3/x1/Y sel2 0.22fF
+C11 li_n460_7# vco_switch_n_3/out 0.02fF
+C12 vco_switch_n_2/out vco_switch_n_3/out 0.40fF
+C13 li_n118_290# li_n460_7# 0.01fF
+C14 li_n118_290# vco_switch_n_2/out 0.00fF
+C15 vco_switch_p_1/li_610_903# vco_switch_p_3/in 0.01fF
+C16 li_n118_290# li_n517_410# 0.00fF
+C17 vco_switch_p_2/out vdd 1.69fF
+C18 li_n460_7# vco_switch_n_1/x1/Y 0.01fF
+C19 vdd vco_switch_p_2/li_610_903# 0.02fF
+C20 vco_switch_p_2/out vco_switch_p_3/li_610_903# 0.05fF
+C21 vdd vco_switch_p_3/out 1.67fF
+C22 vco_switch_p_2/out vco_switch_p_3/in 1.40fF
+C23 vco_switch_p_2/li_610_903# vco_switch_p_3/li_610_903# 0.00fF
+C24 vco_switch_p_2/li_610_903# vco_switch_p_3/in 0.01fF
+C25 vco_switch_p_3/out vco_switch_p_3/in 0.24fF
+C26 vco_switch_n_1/out vco_switch_n_3/out 0.08fF
+C27 vco_switch_p_1/li_610_903# sel3 0.01fF
+C28 sel0 vco_switch_n_0/out 0.04fF
+C29 vco_switch_n_1/out vco_switch_n_1/x1/Y 0.03fF
+C30 vco_switch_n_2/out vco_switch_n_2/x1/Y 0.02fF
+C31 vco_switch_p_2/out sel3 0.50fF
+C32 vco_switch_p_2/li_610_903# sel3 0.02fF
+C33 vdd vco_switch_p_3/li_610_903# 0.00fF
+C34 vdd vco_switch_p_3/in 7.37fF
+C35 vco_switch_p_3/out sel3 0.27fF
+C36 vco_switch_p_1/li_610_903# vco_switch_p_0/out 0.05fF
+C37 sel1 vco_switch_n_0/out 0.11fF
+C38 vco_switch_p_3/li_610_903# vco_switch_p_3/in 0.01fF
+C39 vco_switch_p_2/out vco_switch_p_0/out 0.02fF
+C40 a_879_204# li_n460_7# 0.16fF
+C41 vdd sel3 5.20fF
+C42 a_879_204# li_n517_410# 0.18fF
+C43 sel3 vco_switch_p_3/li_610_903# 0.22fF
+C44 sel3 vco_switch_p_3/in 3.29fF
+C45 vco_switch_n_0/out sel2 0.24fF
+C46 vdd vco_switch_p_0/out 2.47fF
+C47 vdd li_917_51# 0.13fF
+C48 vco_switch_p_3/in vco_switch_p_0/out 2.03fF
+C49 vco_switch_n_0/x1/Y vdd 0.03fF
+C50 vco_switch_p_1/out sel1 0.14fF
+C51 vdd vco_switch_n_3/out 0.11fF
+C52 li_n118_290# vdd 0.19fF
+C53 vco_switch_n_0/x1/Y vco_switch_p_3/in 0.00fF
+C54 vdd vco_switch_n_1/x1/Y 0.03fF
+C55 vctrl li_n460_7# 0.01fF
+C56 sel3 vco_switch_p_0/out 0.30fF
+C57 vctrl vco_switch_n_2/out 0.25fF
+C58 li_n545_286# vco_switch_n_0/out 0.00fF
+C59 vco_switch_n_0/x1/Y sel3 0.01fF
+C60 vco_switch_p_1/out sel2 0.51fF
+C61 sel3 vco_switch_n_3/out 0.06fF
+C62 vdd vco_switch_n_2/x1/Y 0.03fF
+C63 vco_switch_p_1/li_610_903# vco_switch_p_0/li_610_903# 0.00fF
+C64 vco_switch_n_1/out vctrl 0.62fF
+C65 li_n118_290# li_917_51# 0.00fF
+C66 li_n118_290# vco_switch_n_3/out 0.00fF
+C67 sel3 vco_switch_n_2/x1/Y 0.32fF
+C68 vdd a_879_204# 0.47fF
+C69 li_1329_246# out 0.28fF
+C70 vco_switch_n_0/x1/Y vco_switch_n_1/x1/Y 0.00fF
+C71 a_879_204# vco_switch_p_3/in 0.02fF
+C72 vdd vco_switch_p_0/li_610_903# 0.02fF
+C73 vco_switch_p_0/li_610_903# vco_switch_p_3/in 0.01fF
+C74 vco_switch_n_2/x1/Y vco_switch_n_3/out 0.06fF
+C75 vco_switch_n_1/out sel1 0.04fF
+C76 vco_switch_n_2/out sel2 0.02fF
+C77 sel3 vco_switch_p_0/li_610_903# 0.01fF
+C78 li_n517_410# sel2 0.00fF
+C79 vco_switch_n_2/out vco_switch_n_3/x1/Y 0.04fF
+C80 a_879_204# li_917_51# 0.05fF
+C81 vctrl vdd 0.62fF
+C82 vctrl vco_switch_p_3/in 0.00fF
+C83 li_n118_290# a_879_204# 0.15fF
+C84 vco_switch_p_0/li_610_903# vco_switch_p_0/out 0.02fF
+C85 vco_switch_n_1/out sel2 0.27fF
+C86 vco_switch_p_1/li_610_903# sel1 0.20fF
+C87 vco_switch_n_1/out vco_switch_n_3/x1/Y 0.07fF
+C88 vctrl sel3 0.37fF
+C89 li_n545_286# li_n460_7# 0.02fF
+C90 li_n545_286# li_n517_410# 0.02fF
+C91 vdd sel0 0.04fF
+C92 sel0 vco_switch_p_3/in 0.25fF
+C93 vco_switch_p_1/li_610_903# sel2 0.05fF
+C94 vdd sel1 1.31fF
+C95 vco_switch_n_0/x1/Y vctrl 0.09fF
+C96 vctrl vco_switch_n_3/out 1.22fF
+C97 vco_switch_p_2/out sel2 0.26fF
+C98 vco_switch_p_3/in sel1 1.27fF
+C99 vco_switch_p_2/li_610_903# sel2 0.11fF
+C100 vco_switch_p_3/out sel2 0.04fF
+C101 sel0 sel3 0.84fF
+C102 vctrl vco_switch_n_1/x1/Y 0.09fF
+C103 vco_switch_n_0/out li_n460_7# 0.16fF
+C104 sel0 vco_switch_p_0/out 0.06fF
+C105 sel3 sel1 2.04fF
+C106 vdd sel2 2.01fF
+C107 vctrl vco_switch_n_2/x1/Y 0.01fF
+C108 vdd vco_switch_n_3/x1/Y 0.03fF
+C109 vco_switch_n_0/x1/Y sel0 0.06fF
+C110 vco_switch_p_3/in sel2 1.47fF
+C111 vdd li_1329_246# 0.84fF
+C112 vco_switch_n_1/out vco_switch_n_0/out 0.12fF
+C113 sel1 vco_switch_p_0/out 0.37fF
+C114 vco_switch_n_0/x1/Y sel1 0.20fF
+C115 sel3 sel2 7.17fF
+C116 sel3 vco_switch_n_3/x1/Y 0.00fF
+C117 sel1 vco_switch_n_1/x1/Y 0.39fF
+C118 vco_switch_p_1/out li_n517_410# 0.00fF
+C119 vdd li_n545_286# 0.28fF
+C120 vco_switch_p_0/out sel2 0.43fF
+C121 vco_switch_n_0/x1/Y sel2 0.06fF
+C122 vco_switch_n_3/out sel2 0.06fF
+C123 li_1329_246# li_917_51# 0.20fF
+C124 vco_switch_n_3/x1/Y vco_switch_n_3/out 0.03fF
+C125 vco_switch_n_1/x1/Y sel2 0.06fF
+C126 vco_switch_n_3/x1/Y vco_switch_n_1/x1/Y 0.00fF
+C127 vdd vco_switch_n_0/out 0.11fF
+C128 sel0 vco_switch_p_0/li_610_903# 0.03fF
+C129 vco_switch_p_1/li_610_903# vco_switch_p_1/out 0.02fF
+C130 vco_switch_n_3/x1/Y vco_switch_n_2/x1/Y 0.00fF
+C131 li_n118_290# li_n545_286# 0.08fF
+C132 vco_switch_p_2/out vco_switch_p_1/out 0.07fF
+C133 vco_switch_p_0/li_610_903# sel1 0.17fF
+C134 vco_switch_p_1/out vco_switch_p_2/li_610_903# 0.05fF
+C135 vco_switch_p_1/out vco_switch_p_3/out 0.02fF
+C136 vco_switch_n_2/out li_n460_7# 0.05fF
+C137 sel3 vco_switch_n_0/out 0.02fF
+C138 li_n517_410# li_n460_7# 0.04fF
+C139 vctrl sel0 0.54fF
+C140 vdd vco_switch_p_1/out 0.84fF
+C141 a_879_204# li_1329_246# 0.01fF
+C142 vco_switch_n_1/out li_n460_7# 0.00fF
+C143 vco_switch_p_1/out vco_switch_p_3/in 0.81fF
+C144 vco_switch_n_1/out vco_switch_n_2/out 0.02fF
+C145 vco_switch_p_0/li_610_903# sel2 0.05fF
+C146 vco_switch_n_0/x1/Y vco_switch_n_0/out 0.03fF
+C147 vctrl sel1 0.90fF
+C148 vco_switch_n_0/out vco_switch_n_3/out 0.01fF
+C149 vco_switch_n_0/out vco_switch_n_1/x1/Y 0.06fF
+C150 vdd out 0.81fF
+C151 vco_switch_p_1/out sel3 0.10fF
+C152 a_879_204# li_n545_286# 0.17fF
+C153 vctrl sel2 0.41fF
+C154 vco_switch_p_1/li_610_903# li_n517_410# 0.00fF
+C155 vctrl vco_switch_n_3/x1/Y 0.08fF
+C156 vco_switch_p_1/out vco_switch_p_0/out 0.11fF
+C157 sel0 sel1 3.63fF
+C158 vco_switch_p_2/out li_n517_410# 0.02fF
+C159 vco_switch_p_3/out li_n517_410# 0.06fF
+C160 li_917_51# out 0.01fF
+C161 vdd vco_switch_n_2/out 0.30fF
+C162 sel0 sel2 1.72fF
+C163 vdd li_n517_410# 4.18fF
+C164 vco_switch_p_3/in li_n460_7# 0.03fF
+C165 li_n517_410# vco_switch_p_3/in 0.04fF
+C166 sel1 sel2 6.56fF
+C167 vco_switch_n_2/out vss 2.58fF
+C168 vco_switch_n_0/x1/Y vss 0.37fF
+C169 vco_switch_n_0/out vss 2.02fF
+C170 li_917_51# vss 0.58fF
+C171 sel3 vss 0.68fF
+C172 vco_switch_p_3/li_610_903# vss -0.05fF
+C173 vco_switch_p_3/out vss 0.32fF
+C174 sel1 vss 0.85fF
+C175 vco_switch_p_1/li_610_903# vss -0.05fF
+C176 vco_switch_p_1/out vss -0.19fF
+C177 sel2 vss 1.03fF
+C178 vco_switch_p_2/li_610_903# vss -0.05fF
+C179 vco_switch_p_2/out vss -0.55fF
+C180 sel0 vss 2.18fF
+C181 vco_switch_p_0/li_610_903# vss -0.05fF
+C182 vco_switch_p_0/out vss -0.94fF
+C183 a_879_204# vss 1.96fF
+C184 li_n517_410# vss -1.31fF
+C185 li_n118_290# vss 0.55fF
+C186 li_n545_286# vss 0.32fF
+C187 li_n460_7# vss 5.56fF
+C188 vco_switch_n_3/x1/Y vss 0.38fF
+C189 vco_switch_n_3/out vss 1.76fF
+C190 vco_switch_p_3/in vss -1.62fF
+C191 vco_switch_n_2/x1/Y vss 0.31fF
+C192 out vss 0.14fF
+C193 li_1329_246# vss 0.55fF
+C194 vco_switch_n_1/x1/Y vss 0.36fF
+C195 vdd vss 18.14fF
+C196 vco_switch_n_1/out vss 1.14fF
+C197 vctrl vss 4.79fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.ext
new file mode 100755
index 0000000..9e467ee
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.ext
@@ -0,0 +1,368 @@
+timestamp 1645814297
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -613 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -407 0 1 -537
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -616 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -410 0 1 1039
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT 0 1 -465 -1 0 351
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -437 1 0 101
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT 0 -1 517 1 0 351
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 597
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 886 0 1 105
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1 1 0 350 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 256 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 49 0 1 899
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT 0 1 -99 -1 0 351
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT 0 -1 -167 1 0 101
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1356 0 1 -4
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -391
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 -1 0 256 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 50 0 1 -397
+port "vctrl" 3 -1076 -752 -876 -552 m1
+port "out" 2 1849 118 2049 318 m1
+port "vdd" 0 1172 1542 1372 1742 m1
+port "vss" 1 1202 -1174 1402 -974 m1
+node "vctrl" 7 2763.54 -1076 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61400 1964 69232 3484 0 0 0 0 0 0 0 0
+node "out" 3 727.503 1849 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 88560 3228 0 0 0 0 0 0 0 0 0 0
+node "m1_n707_n334#" 5 800.165 -707 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85514 3810 0 0 0 0 0 0 0 0 0 0
+node "m1_n480_1050#" 5 -312.83 -480 1050 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27610 1394 45424 2308 0 0 0 0 0 0 0 0
+node "li_528_n678#" 55 209.787 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_n678#" 57 216.793 223 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 119 377.338 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11254 730 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n460_7#" 42 2980.19 -460 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 63112 2686 0 0 0 0 0 0 0 0 0 0
+node "li_1213_134#" 52 151.34 1213 134 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_917_51#" 207 373.634 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 410.13 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n102_132#" 264 581.568 -102 132 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24694 1530 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n118_290#" 51 6.86424 -118 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 831 146 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n690_207#" 232 1333.42 -690 207 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17102 1192 35970 2150 0 0 0 0 0 0 0 0 0 0
+node "li_n545_286#" 287 457.118 -545 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27234 1670 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_338#" 172 52.2552 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16286 1026 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n517_410#" 54 -27.88 -517 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 76532 3316 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 141 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13362 854 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 -11.48 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_1149#" 57 -11.48 223 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_16_1150#" 24 0 16 1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 108.297 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_n694#" 114 108.297 289 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 61.7185 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_1133#" 114 4.8972 289 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 24491 9546.11 1172 1542 m1 0 0 0 0 2889575 7440 0 0 177990 10470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 205700 12304 985737 19900 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 1202 -1174 m1 2816355 7384 0 0 0 0 0 0 0 0 177412 10436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 188700 11304 1030482 21050 0 0 0 0 0 0 0 0 0 0
+cap "li_n118_290#" "li_n102_132#" 23.2619
+cap "li_n517_410#" "vdd" 2147.46
+cap "a_289_1133#" "vdd" 51.7
+cap "li_n690_207#" "li_n545_286#" 77.2976
+cap "li_n690_207#" "li_611_133#" 25.3289
+cap "li_528_n678#" "vctrl" 103.249
+cap "li_n460_7#" "li_n545_286#" 53.7118
+cap "li_917_51#" "li_1213_134#" 12.6752
+cap "li_n690_207#" "m1_n707_n334#" 124.571
+cap "li_917_51#" "li_611_133#" 28.2715
+cap "a_589_1133#" "li_523_1149#" 25.2972
+cap "a_289_n694#" "vctrl" 42.185
+cap "li_523_1149#" "m1_n480_1050#" 124.538
+cap "li_n460_7#" "m1_n707_n334#" 44.1353
+cap "li_n690_207#" "vdd" 276.123
+cap "li_n690_207#" "li_n102_132#" 80.6316
+cap "li_528_n678#" "li_223_n678#" 7.73793
+cap "li_917_51#" "vdd" 126.227
+cap "li_1179_338#" "li_1213_134#" 37.5411
+cap "li_523_1149#" "vdd" 163.88
+cap "a_289_n694#" "li_223_n678#" 25.2972
+cap "li_917_51#" "li_1179_n70#" 0.798387
+cap "li_n690_207#" "li_n517_410#" 157.498
+cap "a_590_n694#" "vctrl" 42.185
+cap "li_1179_712#" "vdd" 286.665
+cap "li_1179_338#" "vdd" 198.559
+cap "li_n460_7#" "li_n517_410#" 27.8642
+cap "li_223_1149#" "m1_n480_1050#" 122.556
+cap "li_611_133#" "a_879_204#" 11.55
+cap "li_1179_n70#" "li_1179_338#" 10.1455
+cap "li_223_1149#" "li_16_1150#" 7.7234
+cap "li_223_1149#" "vdd" 160.213
+cap "li_611_133#" "li_1213_134#" 4.49096
+cap "a_879_204#" "vdd" 11
+cap "li_n460_7#" "li_n690_207#" 159.767
+cap "li_223_1149#" "a_289_1133#" 25.2972
+cap "a_589_1133#" "m1_n480_1050#" 35.605
+cap "a_590_n694#" "li_528_n678#" 25.2972
+cap "m1_n707_n334#" "m1_n480_1050#" 29.1549
+cap "li_n545_286#" "vdd" 259.942
+cap "out" "vdd" 311.915
+cap "vctrl" "m1_n707_n334#" 2.925
+cap "li_n102_132#" "li_n545_286#" 30.6658
+cap "a_289_n694#" "a_590_n694#" 5.56044
+cap "li_n118_290#" "li_n545_286#" 12.1957
+cap "li_917_51#" "li_1179_338#" 32.2616
+cap "li_611_133#" "vdd" 94.682
+cap "a_589_1133#" "vdd" 51.7
+cap "li_16_1150#" "m1_n480_1050#" 22
+cap "li_n102_132#" "li_611_133#" 3.57049
+cap "vdd" "m1_n707_n334#" 522.229
+cap "vdd" "m1_n480_1050#" 2204.76
+cap "li_n517_410#" "li_n545_286#" 64.4913
+cap "li_1179_n70#" "li_1213_134#" 15.4737
+cap "li_16_1150#" "vdd" 116.501
+cap "a_589_1133#" "a_289_1133#" 5.58088
+cap "li_1179_338#" "li_1179_712#" 3.3
+cap "li_n517_410#" "m1_n707_n334#" 61.7541
+cap "vctrl" "li_223_n678#" 130.927
+cap "li_223_1149#" "li_523_1149#" 8.01429
+cap "li_n517_410#" "m1_n480_1050#" 11.0106
+cap "li_n102_132#" "vdd" 146.063
+cap "a_289_1133#" "m1_n480_1050#" 35.605
+cap "li_n118_290#" "vdd" 47.8032
+cap "XMDUM16/a_n76_n209#" "XM26/a_n33_n157#" 423.34
+cap "XMDUM16/a_n76_n209#" "XM4GUT/a_15_n96#" 127.376
+cap "XM26/a_n76_n69#" "XM26/a_n33_n157#" 0.734364
+cap "XMDUM16/a_n76_n209#" "MX3GUT/a_n73_n64#" 3.35404
+cap "XM4GUT/a_n33_33#" "XM16B_1/a_n76_n209#" -34.9764
+cap "XM4GUT/a_15_n96#" "XM16B_1/a_n76_n209#" 5.03684
+cap "XM16B_1/a_n76_n209#" "XM26/a_n33_n157#" 49.7847
+cap "XM4GUT/a_n33_33#" "XM4GUT/a_15_n96#" 21.0955
+cap "XM4GUT/a_15_n96#" "XM26/a_n33_n157#" 1.23214
+cap "XM4GUT/a_15_n96#" "MX3GUT/a_n73_n64#" 20.1161
+cap "XM2/a_n33_63#" "M1GUT/a_n73_n144#" 7.94326
+cap "MX3GUT/w_n109_n164#" "XM4GUT/a_15_n96#" 3.60186
+cap "M1GUT/a_n73_n144#" "XM16B_1/a_n76_n209#" 3.73718
+cap "XMDUM16/a_n76_n209#" "XM2/a_n33_63#" 239.861
+cap "XM4GUT/a_n33_33#" "M1GUT/a_n73_n144#" 4.9252
+cap "XMDUM16/a_n76_n209#" "XM26/a_n76_n69#" 393.635
+cap "XM4GUT/a_n33_33#" "XM2/a_n33_63#" 37.1179
+cap "XM2/a_n33_63#" "XM4GUT/a_15_n96#" 20.7815
+cap "XMDUM16/a_n76_n209#" "XM16B_1/a_n76_n209#" 737.189
+cap "XMDUM16/a_n76_n209#" "XM4GUT/a_n33_33#" 136.545
+cap "XM6/a_15_n175#" "XMDUM11/w_n112_n338#" 8.46751
+cap "XMDUM16/a_n76_n209#" "XM4GUT/a_15_n96#" 36.9403
+cap "XMDUM16/a_n76_n209#" "XM21/a_n72_n22#" 5.57731
+cap "XM23/a_n173_n220#" "XM13/a_15_n120#" 3.1875
+cap "XM6/a_15_n175#" "XM21/a_n72_n22#" 8.01429
+cap "XM4GUT/a_15_n96#" "XM6/a_15_n175#" -1.76347
+cap "XM24/a_18_n129#" "XM13/a_15_n120#" 60.3698
+cap "XMDUM16/a_n76_n209#" "XM16B_1/a_n33_n297#" 217.032
+cap "XM23/a_n173_n220#" "XMDUM16/a_n76_n209#" 2.29918
+cap "XM12/a_n73_n240#" "XMDUM16/a_n76_n209#" 7.62219
+cap "XM5GUT/a_15_n236#" "XMDUM16/a_n76_n209#" 3.78464
+cap "XM5GUT/a_15_n236#" "XM6/a_15_n175#" 17.3744
+cap "XMDUM16/a_n76_n209#" "XM16B_1/a_n76_n209#" 983.695
+cap "XM6/a_15_n175#" "XM16B_1/a_n76_n209#" 4.41732
+cap "XM24/a_18_n129#" "XMDUM16/a_n76_n209#" 238.368
+cap "XM13/a_n33_142#" "XM12/a_n73_n240#" -2.56667
+cap "XM24/a_18_n129#" "XM13/a_n33_142#" 5.15315
+cap "XMDUM16/a_n76_n209#" "XM13/a_15_n120#" 620.764
+cap "XM13/a_15_n120#" "XM6/a_15_n175#" 0.444378
+cap "XM13/a_n33_142#" "XM13/a_15_n120#" 28.1783
+cap "XMDUM16/a_n76_n209#" "XM6/a_15_n175#" 334.121
+cap "XM13/a_n33_142#" "XMDUM16/a_n76_n209#" 243.429
+cap "XM13/a_n33_142#" "XM6/a_15_n175#" 6.9818
+cap "XM4GUT/a_15_n96#" "XM16B_1/a_n33_n297#" 5.81183
+cap "XM6/a_15_n175#" "XMDUM11B/a_n33_235#" 0.676471
+cap "XM16B_1/a_n33_n297#" "XM16B_1/a_n76_n209#" 66.5872
+cap "XM24/a_18_n129#" "vss" -27.47
+cap "XM24/a_n76_n129#" "XM24/a_18_n129#" 2.12372
+cap "XM16B_1/a_n76_n209#" "XM4GUT/a_n33_33#" 3.42098
+cap "MX3GUT/w_n109_n164#" "XM4GUT/a_15_n96#" -23.7578
+cap "M1GUT/a_n73_n144#" "XM4GUT/a_n33_33#" -45.2266
+cap "vss" "XM4GUT/a_15_n96#" 3.99528
+cap "XM4GUT/a_n73_n96#" "MX3GUT/w_n109_n164#" 3.35404
+cap "MX3GUT/w_n109_n164#" "XM2/a_n33_63#" 57.7703
+cap "vss" "XM2/a_n33_63#" 9.19586
+cap "XM11B_1/a_n33_235#" "M1GUT/a_n73_n144#" 41.998
+cap "XM4GUT/a_n73_n96#" "XM4GUT/a_15_n96#" 4.29146
+cap "XM2/a_n33_63#" "XM4GUT/a_15_n96#" 47.5508
+cap "M1GUT/a_n73_n144#" "MX3GUT/w_n109_n164#" 162.738
+cap "M1GUT/a_n73_n144#" "XM4GUT/a_15_n96#" 0.166247
+cap "M1GUT/a_n73_n144#" "XM2/a_n33_63#" 16.4545
+cap "MX3GUT/w_n109_n164#" "XM4GUT/a_n33_33#" -116.517
+cap "vss" "XM4GUT/a_n33_33#" 3.57325
+cap "XM4GUT/a_n33_33#" "XM4GUT/a_15_n96#" 22.2006
+cap "XM11B_1/a_n33_235#" "MX3GUT/w_n109_n164#" 117.804
+cap "XM16B_1/a_n76_n209#" "M1GUT/a_n73_n144#" 3.73718
+cap "XM4GUT/a_n33_33#" "XM2/a_n33_63#" 67.0322
+cap "XM11B_1/a_n33_235#" "XM2/a_n33_63#" 66.4329
+cap "XM22/a_n73_n68#" "XMDUM11/w_n112_n338#" 3.7197
+cap "XMDUM11/w_n112_n338#" "XM11B_1/a_n33_235#" -322.13
+cap "XM6/a_n73_n175#" "XMDUM11/w_n112_n338#" 3.78464
+cap "vss" "XM13/a_15_n120#" -13.94
+cap "XMDUM11/w_n112_n338#" "XM11B_1/a_n76_n276#" 252.258
+cap "XM6/a_n73_n175#" "XM6/a_15_n175#" 17.4167
+cap "XM6/a_15_n175#" "XM11B_1/a_n76_n276#" 3.7651
+cap "XMDUM11/w_n112_n338#" "XM24/a_18_n129#" 247.957
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 39.9911
+cap "XMDUM11/w_n112_n338#" "XM13/a_15_n120#" 394.213
+cap "XM11B_1/a_n33_235#" "XM11B_1/a_n76_n276#" 57.7179
+cap "vss" "XM13/a_n33_142#" 41.7792
+cap "XM24/a_n76_n129#" "XM13/a_15_n120#" 3.35928
+cap "vss" "XMDUM11/w_n112_n338#" 1.85762
+cap "XM6/a_15_n175#" "vss" 2.67994
+cap "XM13/a_n73_n120#" "XM13/a_n33_142#" 7.5625
+cap "XM13/a_n33_142#" "XM4GUT/a_15_n96#" 0.385475
+cap "XMDUM11/w_n112_n338#" "XM13/a_n33_142#" 13.6743
+cap "XM6/a_15_n175#" "XM13/a_n33_142#" 11.0353
+cap "XM13/a_n73_n120#" "XMDUM11/w_n112_n338#" 7.62219
+cap "XM24/a_n76_n129#" "XMDUM11/w_n112_n338#" 2.29918
+cap "XM6/a_15_n175#" "XM4GUT/a_15_n96#" -1.49383
+cap "XM6/a_15_n175#" "XMDUM11/w_n112_n338#" 44.7253
+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 214.413
+merge "XM5GUT/a_n33_395#" "XM6/a_n33_135#" -142.171 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12015 -610 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM6/a_n33_135#" "MX3GUT/a_15_n64#"
+merge "MX3GUT/a_15_n64#" "li_n118_290#"
+merge "li_n118_290#" "XM4GUT/a_15_n96#"
+merge "XM4GUT/a_15_n96#" "li_n102_132#"
+merge "XM2/a_n73_n103#" "XM16/a_n76_n209#" -1050.23 0 0 0 0 0 0 0 0 23524 -2152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -141455 -2314 -269004 -1230 0 0 0 0 0 0 0 0 0 0
+merge "XM16/a_n76_n209#" "XM16_1/a_n76_n209#"
+merge "XM16_1/a_n76_n209#" "XM16B/a_n76_n209#"
+merge "XM16B/a_n76_n209#" "XM16B_1/a_n76_n209#"
+merge "XM16B_1/a_n76_n209#" "li_n460_7#"
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#" 737.667 0 0 0 0 -339424 -21940 0 0 652392 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 650760 -1898 2693946 -4408 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n173_n220#" "XMDUM11B/a_18_n276#"
+merge "XMDUM11B/a_18_n276#" "XMDUM11B/a_n33_235#"
+merge "XMDUM11B/a_n33_235#" "XMDUM11B/a_n76_n276#"
+merge "XMDUM11B/a_n76_n276#" "XMDUM25/a_18_n136#"
+merge "XMDUM25/a_18_n136#" "XMDUM25/a_n76_n136#"
+merge "XMDUM25/a_n76_n136#" "XMDUM25/a_n33_95#"
+merge "XMDUM25/a_n33_95#" "XMDUM25/w_n112_n198#"
+merge "XMDUM25/w_n112_n198#" "XM25/a_18_n136#"
+merge "XM25/a_18_n136#" "XM25/w_n112_n198#"
+merge "XM25/w_n112_n198#" "XM11_1/a_18_n276#"
+merge "XM11_1/a_18_n276#" "XM11/a_n76_n276#"
+merge "XM11/a_n76_n276#" "XM11B/a_n76_n276#"
+merge "XM11B/a_n76_n276#" "XM11B_1/a_18_n276#"
+merge "XM11B_1/a_18_n276#" "XMDUM11/a_18_n276#"
+merge "XMDUM11/a_18_n276#" "XMDUM11/a_n76_n276#"
+merge "XMDUM11/a_n76_n276#" "XMDUM11/a_n33_235#"
+merge "XMDUM11/a_n33_235#" "li_16_1150#"
+merge "li_16_1150#" "XM23/w_n209_n320#"
+merge "XM23/w_n209_n320#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XM12/w_n109_n340#"
+merge "XM12/w_n109_n340#" "XMDUM11B/w_n112_n338#"
+merge "XMDUM11B/w_n112_n338#" "XM21/a_n72_n22#"
+merge "XM21/a_n72_n22#" "XM21/w_n109_n58#"
+merge "XM21/w_n109_n58#" "XM5GUT/a_15_n236#"
+merge "XM5GUT/a_15_n236#" "XM5GUT/w_n109_n298#"
+merge "XM5GUT/w_n109_n298#" "XM11_1/w_n112_n338#"
+merge "XM11_1/w_n112_n338#" "XM11/w_n112_n338#"
+merge "XM11/w_n112_n338#" "XM11B/w_n112_n338#"
+merge "XM11B/w_n112_n338#" "XM11B_1/w_n112_n338#"
+merge "XM11B_1/w_n112_n338#" "M1GUT/w_n109_n244#"
+merge "M1GUT/w_n109_n244#" "XMDUM11/w_n112_n338#"
+merge "XMDUM11/w_n112_n338#" "MX3GUT/a_n73_n64#"
+merge "MX3GUT/a_n73_n64#" "MX3GUT/w_n109_n164#"
+merge "MX3GUT/w_n109_n164#" "vdd"
+merge "XM22/a_n33_33#" "XM21/a_n15_n53#" -386.939 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 630 -120 0 0 21108 -888 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM21/a_n15_n53#" "a_879_204#"
+merge "a_879_204#" "XM5GUT/a_n73_n236#"
+merge "XM5GUT/a_n73_n236#" "XM6/a_15_n175#"
+merge "XM6/a_15_n175#" "li_611_133#"
+merge "li_611_133#" "M1GUT/a_n33_n241#"
+merge "M1GUT/a_n33_n241#" "XM2/a_n33_63#"
+merge "XM2/a_n33_63#" "li_n690_207#"
+merge "XM11_1/a_n76_n276#" "XM11/a_18_n276#" 673.393 0 0 0 0 0 0 0 0 0 0 337920 -2152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47852 -2378 266292 -1192 0 0 0 0 0 0 0 0 0 0
+merge "XM11/a_18_n276#" "XM11B/a_18_n276#"
+merge "XM11B/a_18_n276#" "XM11B_1/a_n76_n276#"
+merge "XM11B_1/a_n76_n276#" "M1GUT/a_n73_n144#"
+merge "M1GUT/a_n73_n144#" "li_n517_410#"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -329.556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -207218 -424 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "M1GUT/a_15_n144#" "XM2/a_15_n103#" -203.836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11148 -1156 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_15_n103#" "MX3GUT/a_n33_n161#"
+merge "MX3GUT/a_n33_n161#" "XM4GUT/a_n33_33#"
+merge "XM4GUT/a_n33_33#" "li_n545_286#"
+merge "XMDUM25/VSUBS" "XM25/VSUBS" -4290 -117171 -3779 0 0 0 0 0 0 0 0 489940 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 430785 -720 303586 -5594 0 0 0 0 0 0 0 0 0 0
+merge "XM25/VSUBS" "XM23/VSUBS"
+merge "XM23/VSUBS" "XM22/VSUBS"
+merge "XM22/VSUBS" "XM22/a_n73_n68#"
+merge "XM22/a_n73_n68#" "XM12/VSUBS"
+merge "XM12/VSUBS" "XMDUM11B/VSUBS"
+merge "XMDUM11B/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "XM24/VSUBS"
+merge "XM24/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM13/VSUBS"
+merge "XM13/VSUBS" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "XMDUM16B/VSUBS"
+merge "XMDUM16B/VSUBS" "XMDUM16B/a_n33_n297#"
+merge "XMDUM16B/a_n33_n297#" "XMDUM16B/a_18_n209#"
+merge "XMDUM16B/a_18_n209#" "XMDUM16B/a_n76_n209#"
+merge "XMDUM16B/a_n76_n209#" "XM5GUT/VSUBS"
+merge "XM5GUT/VSUBS" "XM6/VSUBS"
+merge "XM6/VSUBS" "XM6/a_n73_n175#"
+merge "XM6/a_n73_n175#" "XM11_1/VSUBS"
+merge "XM11_1/VSUBS" "XM11/VSUBS"
+merge "XM11/VSUBS" "XM11B/VSUBS"
+merge "XM11B/VSUBS" "XM11B_1/VSUBS"
+merge "XM11B_1/VSUBS" "M1GUT/VSUBS"
+merge "M1GUT/VSUBS" "XM2/VSUBS"
+merge "XM2/VSUBS" "XMDUM11/VSUBS"
+merge "XMDUM11/VSUBS" "MX3GUT/VSUBS"
+merge "MX3GUT/VSUBS" "XM4GUT/VSUBS"
+merge "XM4GUT/VSUBS" "XM4GUT/a_n73_n96#"
+merge "XM4GUT/a_n73_n96#" "XM16/VSUBS"
+merge "XM16/VSUBS" "XM16/a_18_n209#"
+merge "XM16/a_18_n209#" "XM16_1/VSUBS"
+merge "XM16_1/VSUBS" "XM16_1/a_18_n209#"
+merge "XM16_1/a_18_n209#" "XM16B/VSUBS"
+merge "XM16B/VSUBS" "XM16B/a_18_n209#"
+merge "XM16B/a_18_n209#" "XM16B_1/VSUBS"
+merge "XM16B_1/VSUBS" "XM16B_1/a_18_n209#"
+merge "XM16B_1/a_18_n209#" "XMDUM26/VSUBS"
+merge "XMDUM26/VSUBS" "XMDUM26/a_n33_n157#"
+merge "XMDUM26/a_n33_n157#" "XMDUM26/a_18_n69#"
+merge "XMDUM26/a_18_n69#" "XMDUM26/a_n76_n69#"
+merge "XMDUM26/a_n76_n69#" "XM26/VSUBS"
+merge "XM26/VSUBS" "XM26/a_18_n69#"
+merge "XM26/a_18_n69#" "XMDUM16/VSUBS"
+merge "XMDUM16/VSUBS" "XMDUM16/a_n33_n297#"
+merge "XMDUM16/a_n33_n297#" "XMDUM16/a_18_n209#"
+merge "XMDUM16/a_18_n209#" "XMDUM16/a_n76_n209#"
+merge "XMDUM16/a_n76_n209#" "vss"
+merge "XM16/a_n33_n297#" "XM16_1/a_n33_n297#" -854.799 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39732 -528 0 0 9418 -784 11546 -1040 0 0 0 0 0 0 0 0 0 0
+merge "XM16_1/a_n33_n297#" "li_223_n678#"
+merge "li_223_n678#" "a_289_n694#"
+merge "a_289_n694#" "XM16B/a_n33_n297#"
+merge "XM16B/a_n33_n297#" "XM16B_1/a_n33_n297#"
+merge "XM16B_1/a_n33_n297#" "XM26/a_n33_n157#"
+merge "XM26/a_n33_n157#" "vctrl"
+merge "vctrl" "li_528_n678#"
+merge "li_528_n678#" "a_590_n694#"
+merge "XM25/a_n76_n136#" "XM26/a_n76_n69#" 85.7302 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39600 -528 0 0 8942 -800 10396 -1270 0 0 0 0 0 0 0 0 0 0
+merge "XM26/a_n76_n69#" "m1_n707_n334#"
+merge "m1_n707_n334#" "XM25/a_n33_95#"
+merge "XM25/a_n33_95#" "XM11_1/a_n33_235#"
+merge "XM11_1/a_n33_235#" "XM11/a_n33_235#"
+merge "XM11/a_n33_235#" "li_223_1149#"
+merge "li_223_1149#" "a_289_1133#"
+merge "a_289_1133#" "XM11B/a_n33_235#"
+merge "XM11B/a_n33_235#" "XM11B_1/a_n33_235#"
+merge "XM11B_1/a_n33_235#" "m1_n480_1050#"
+merge "m1_n480_1050#" "li_523_1149#"
+merge "li_523_1149#" "a_589_1133#"
+merge "XM22/a_15_n68#" "XM12/a_n33_n337#" -196.083 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 132 -166 0 0 -1806 -456 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM12/a_n33_n337#" "XM21/a_15_n22#"
+merge "XM21/a_15_n22#" "XM13/a_n33_142#"
+merge "XM13/a_n33_142#" "li_917_51#"
+merge "XM23/a_n33_251#" "XM23/a_63_n317#" -501.666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -125060 -1066 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_63_n317#" "li_1179_712#"
+merge "li_1179_712#" "XM23/a_n129_n317#"
+merge "XM23/a_n129_n317#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "li_1179_338#"
+merge "li_1179_338#" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "li_1179_n70#"
+merge "li_1179_n70#" "li_1213_134#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.mag
new file mode 100755
index 0000000..f656700
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.mag
@@ -0,0 +1,440 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645814297
+<< error_s >>
+rect 871 109 901 121
+rect 871 25 901 37
+<< nwell >>
+rect -820 242 1795 1347
+<< pwell >>
+rect -820 -835 1795 242
+<< psubdiff >>
+rect -779 -28 -745 216
+rect 894 -62 1023 -28
+rect -779 -136 -745 -62
+rect 989 -411 1023 -62
+rect -779 -747 -745 -647
+rect 989 -747 1023 -663
+rect -779 -781 -742 -747
+rect 894 -781 1023 -747
+<< nsubdiff >>
+rect -781 1252 -708 1286
+rect 930 1252 1023 1286
+rect -781 1226 -747 1252
+rect -781 565 -747 572
+rect 989 565 1023 1252
+rect -781 531 -708 565
+rect 930 531 1023 565
+rect -781 278 -747 531
+<< psubdiffcont >>
+rect -779 -62 894 -28
+rect -779 -647 -745 -136
+rect 989 -663 1023 -411
+rect -742 -781 894 -747
+<< nsubdiffcont >>
+rect -708 1252 930 1286
+rect -781 572 -747 1226
+rect -708 531 930 565
+<< poly >>
+rect 289 1133 317 1199
+rect 589 1133 617 1199
+rect 879 204 909 247
+rect 289 -694 317 -628
+rect 590 -694 618 -628
+<< locali >>
+rect -781 1252 -708 1286
+rect 930 1252 1023 1286
+rect -781 1226 -747 1252
+rect 16 1150 82 1184
+rect 223 1149 383 1183
+rect 523 1149 683 1183
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+rect 72 166 106 290
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+rect 1220 296 1517 330
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+rect 611 170 898 187
+rect 611 133 645 170
+rect 853 154 898 170
+rect -610 106 -550 131
+rect -244 68 -210 132
+rect 272 68 306 132
+rect 1019 111 1053 225
+rect 1119 212 1185 225
+rect 1339 197 1373 296
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+rect 1213 163 1329 168
+rect 1213 134 1256 163
+rect 951 85 1053 111
+rect 917 77 1053 85
+rect 917 51 951 77
+rect 894 -62 1023 -28
+rect -779 -136 -745 -62
+rect 989 -411 1023 -62
+rect 1179 -70 1255 -36
+rect 1221 -171 1255 -70
+rect 1221 -205 1375 -171
+rect -779 -747 -745 -647
+rect 223 -678 383 -644
+rect 528 -678 680 -644
+rect 989 -747 1023 -663
+rect 894 -781 1023 -747
+<< viali >>
+rect -708 1252 930 1286
+rect -517 410 -378 444
+rect -113 412 -79 446
+rect 364 416 741 450
+rect 1091 406 1125 810
+rect -610 207 -576 241
+rect 349 207 383 241
+rect -460 7 -352 41
+rect -131 10 -97 44
+rect 365 15 629 49
+rect 821 8 855 42
+rect 989 -663 1023 -411
+rect -779 -781 -742 -747
+rect -742 -781 894 -747
+<< metal1 >>
+rect 1172 1443 1372 1742
+rect -760 1442 1372 1443
+rect -760 1286 1713 1442
+rect -760 1252 -708 1286
+rect 930 1252 1713 1286
+rect -760 1237 1713 1252
+rect -725 1236 22 1237
+rect -686 1045 -640 1236
+rect -592 1047 -546 1236
+rect -480 1193 -374 1205
+rect -480 1141 -436 1193
+rect -384 1141 -374 1193
+rect -480 1131 -374 1141
+rect -480 1050 -434 1131
+rect -480 775 -434 979
+rect -346 953 -306 1236
+rect -18 1202 22 1236
+rect 76 1202 116 1237
+rect -18 1131 116 1202
+rect -18 943 22 1131
+rect 76 960 116 1131
+rect 154 954 194 1237
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+rect 223 1143 277 1189
+rect 329 1143 379 1189
+rect 277 1135 329 1141
+rect -707 729 -434 775
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+rect 578 1193 630 1199
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+rect 630 1143 679 1189
+rect 578 1135 630 1141
+rect 715 759 755 1237
+rect -707 -288 -661 729
+rect 280 618 326 759
+rect 580 618 626 759
+rect -354 572 626 618
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+rect 674 529 755 759
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+rect -104 495 755 529
+rect -104 458 -70 495
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+rect 348 450 755 465
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+rect 1085 1084 1713 1237
+rect 1085 810 1131 1084
+rect 1636 840 1676 1084
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+rect 824 377 870 452
+rect 1085 406 1091 810
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+rect 1286 800 1676 840
+rect 1382 460 1743 500
+rect 1085 382 1131 406
+rect -622 241 -564 247
+rect 337 241 395 247
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+rect -576 207 349 241
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+rect 337 201 395 207
+rect 1703 234 1743 460
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+rect -485 41 -324 51
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+rect -352 7 -324 41
+rect -485 -25 -324 7
+rect -168 44 -58 52
+rect -168 10 -131 44
+rect -97 10 -58 44
+rect -168 0 -58 10
+rect 330 49 751 55
+rect 330 15 365 49
+rect 629 15 751 49
+rect 330 9 751 15
+rect -370 -79 -324 -25
+rect -89 -19 -58 0
+rect 681 -19 751 9
+rect 807 42 868 52
+rect 807 8 821 42
+rect 855 8 868 42
+rect 1703 30 1743 194
+rect 1849 118 2049 194
+rect 807 0 868 8
+rect -89 -50 751 -19
+rect -370 -125 627 -79
+rect 280 -153 326 -125
+rect 581 -152 627 -125
+rect -707 -334 -431 -288
+rect -477 -423 -431 -334
+rect -1076 -635 -876 -552
+rect -1076 -687 -1012 -635
+rect -960 -687 -876 -635
+rect -1076 -752 -876 -687
+rect -680 -724 -640 -457
+rect -586 -724 -546 -457
+rect -380 -553 -299 -457
+rect -444 -635 -364 -623
+rect -444 -687 -433 -635
+rect -381 -687 -364 -635
+rect -444 -691 -364 -687
+rect -433 -693 -381 -691
+rect -336 -724 -299 -553
+rect -16 -724 24 -191
+rect 76 -724 116 -191
+rect 158 -610 227 -169
+rect 158 -724 198 -610
+rect 278 -635 330 -629
+rect 227 -684 278 -638
+rect 330 -684 379 -638
+rect 278 -693 330 -687
+rect 418 -724 487 -263
+rect 681 -602 751 -50
+rect 822 -55 862 0
+rect 1426 -10 1743 30
+rect 578 -635 630 -629
+rect 528 -684 578 -638
+rect 630 -684 680 -638
+rect 578 -693 630 -687
+rect 711 -724 751 -602
+rect 786 -94 930 -55
+rect 786 -632 826 -94
+rect 890 -632 930 -94
+rect 1086 -342 1128 -47
+rect 1288 -342 1328 -63
+rect 1086 -344 1652 -342
+rect 786 -678 930 -632
+rect 786 -724 826 -678
+rect 890 -724 930 -678
+rect 973 -411 1652 -344
+rect 973 -663 989 -411
+rect 1023 -663 1652 -411
+rect 973 -724 1652 -663
+rect -819 -747 1755 -724
+rect -819 -781 -779 -747
+rect 894 -781 1755 -747
+rect -819 -872 1755 -781
+rect 1202 -1174 1402 -872
+<< via1 >>
+rect -436 1141 -384 1193
+rect 277 1141 329 1193
+rect 578 1141 630 1193
+rect -1012 -687 -960 -635
+rect -433 -687 -381 -635
+rect 278 -687 330 -635
+rect 578 -687 630 -635
+<< metal2 >>
+rect -442 1141 -436 1193
+rect -384 1187 -378 1193
+rect 271 1187 277 1193
+rect -384 1147 277 1187
+rect -384 1141 -378 1147
+rect 271 1141 277 1147
+rect 329 1187 335 1193
+rect 572 1187 578 1193
+rect 329 1147 578 1187
+rect 329 1141 335 1147
+rect 572 1141 578 1147
+rect 630 1141 636 1193
+rect -1018 -687 -1012 -635
+rect -960 -641 -954 -635
+rect -439 -641 -433 -635
+rect -960 -681 -433 -641
+rect -960 -687 -954 -681
+rect -439 -687 -433 -681
+rect -381 -641 -375 -635
+rect 272 -641 278 -635
+rect -381 -681 278 -641
+rect -381 -687 -375 -681
+rect 272 -687 278 -681
+rect 330 -641 336 -635
+rect 572 -641 578 -635
+rect 330 -681 578 -641
+rect 330 -687 336 -681
+rect 572 -687 578 -681
+rect 630 -687 636 -635
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -410 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -616 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -407 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -613 0 1 -537
+box -76 -157 76 157
+<< labels >>
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+rlabel metal1 -1076 -752 -876 -552 1 vctrl
+port 3 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.spice
new file mode 100755
index 0000000..de4320c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel.spice
@@ -0,0 +1,311 @@
+* NGSPICE file created from 3-stage_cs-vco_dpgutfeel.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n109_n340# 0.19fF
+C1 w_n109_n340# a_n33_n337# 0.11fF
+C2 a_15_n240# w_n109_n340# 0.17fF
+C3 a_n73_n240# a_15_n240# 0.20fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n173_n220# a_18_n220# 0.14fF
+C1 a_114_n220# a_n173_n220# 0.07fF
+C2 a_18_n220# w_n209_n320# 0.28fF
+C3 a_114_n220# w_n209_n320# 0.33fF
+C4 a_114_n220# a_18_n220# 0.31fF
+C5 a_n173_n220# a_n129_n317# 0.00fF
+C6 a_n129_n317# w_n209_n320# 0.14fF
+C7 w_n209_n320# a_n33_251# 0.14fF
+C8 a_n173_n220# a_n78_n220# 0.31fF
+C9 a_n78_n220# w_n209_n320# 0.33fF
+C10 a_18_n220# a_n33_251# 0.00fF
+C11 a_n78_n220# a_18_n220# 0.31fF
+C12 a_114_n220# a_n78_n220# 0.18fF
+C13 a_n129_n317# a_n33_251# 0.02fF
+C14 a_63_n317# w_n209_n320# 0.14fF
+C15 a_n78_n220# a_n129_n317# 0.00fF
+C16 a_18_n220# a_63_n317# 0.00fF
+C17 a_114_n220# a_63_n317# 0.00fF
+C18 a_n78_n220# a_n33_251# 0.00fF
+C19 a_n129_n317# a_63_n317# 0.03fF
+C20 a_63_n317# a_n33_251# 0.02fF
+C21 a_n173_n220# w_n209_n320# 0.28fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_15_n120# a_n33_142# 0.00fF
+C1 a_15_n120# a_n73_n120# 0.15fF
+C2 a_n33_142# a_n73_n120# 0.01fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_18_n129# a_n33_n217# 0.01fF
+C1 a_18_n129# a_n76_n129# 0.21fF
+C2 a_n33_n217# a_n76_n129# 0.01fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n136# w_n112_n198# 0.16fF
+C1 a_n76_n136# a_18_n136# 0.20fF
+C2 a_n76_n136# a_n33_95# 0.00fF
+C3 a_18_n136# w_n112_n198# 0.16fF
+C4 w_n112_n198# a_n33_95# 0.19fF
+C5 a_18_n136# a_n33_95# 0.00fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n69# a_n33_n157# 0.01fF
+C1 a_18_n69# a_n76_n69# 0.17fF
+C2 a_n33_n157# a_n76_n69# 0.00fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n33_n297# 0.00fF
+C1 a_18_n209# a_n76_n209# 0.35fF
+C2 a_n33_n297# a_n76_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n96# a_n33_33# 0.00fF
+C1 a_15_n96# a_n73_n96# 0.06fF
+C2 a_n33_33# a_n73_n96# 0.00fF
+C3 a_15_n96# VSUBS 0.02fF
+C4 a_n73_n96# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n276# w_n112_n338# 0.32fF
+C1 a_n76_n276# a_18_n276# 0.46fF
+C2 a_n76_n276# a_n33_235# 0.00fF
+C3 a_18_n276# w_n112_n338# 0.32fF
+C4 w_n112_n338# a_n33_235# 0.19fF
+C5 a_18_n276# a_n33_235# 0.00fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n33_n297# 0.00fF
+C1 a_18_n209# a_n76_n209# 0.47fF
+C2 a_n33_n297# a_n76_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_15_n103# a_n33_63# 0.00fF
+C1 a_15_n103# a_n73_n103# 0.07fF
+C2 a_n33_63# a_n73_n103# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
++ VSUBS
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+C0 a_n73_n144# w_n109_n244# 0.13fF
+C1 a_n73_n144# a_15_n144# 0.15fF
+C2 a_n73_n144# a_n33_n241# 0.00fF
+C3 a_15_n144# w_n109_n244# 0.13fF
+C4 w_n109_n244# a_n33_n241# 0.14fF
+C5 a_15_n144# a_n33_n241# 0.00fF
+C6 a_15_n144# VSUBS -0.11fF
+C7 a_n73_n144# VSUBS -0.11fF
+C8 a_n33_n241# VSUBS -0.01fF
+C9 w_n109_n244# VSUBS 0.29fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_15_n175# a_n33_135# 0.00fF
+C1 a_15_n175# a_n73_n175# 0.16fF
+C2 a_n33_135# a_n73_n175# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+C0 a_n73_n236# w_n109_n298# 0.26fF
+C1 a_n73_n236# a_15_n236# 0.32fF
+C2 a_n73_n236# a_n33_395# 0.00fF
+C3 a_15_n236# w_n109_n298# 0.26fF
+C4 w_n109_n298# a_n33_395# 0.14fF
+C5 a_15_n236# a_n33_395# 0.00fF
+C6 a_15_n236# VSUBS -0.25fF
+C7 a_n73_n236# VSUBS -0.25fF
+C8 a_n33_395# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.50fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+C0 a_n73_n64# w_n109_n164# 0.06fF
+C1 a_n73_n64# a_15_n64# 0.07fF
+C2 a_n73_n64# a_n33_n161# 0.00fF
+C3 a_15_n64# w_n109_n164# 0.06fF
+C4 w_n109_n164# a_n33_n161# 0.14fF
+C5 a_15_n64# a_n33_n161# 0.00fF
+C6 a_15_n64# VSUBS -0.06fF
+C7 a_n73_n64# VSUBS -0.06fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 a_n72_n22# w_n109_n58# 0.14fF
+C1 a_n72_n22# a_15_n22# 0.09fF
+C2 a_15_n22# w_n109_n58# 0.08fF
+C3 w_n109_n58# a_n15_n53# 0.05fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_15_n68# a_n33_33# 0.00fF
+C1 a_15_n68# a_n73_n68# 0.04fF
+C2 a_n33_33# a_n73_n68# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt x3-stage_cs-vco_dp7 vdd vss out vctrl
+XXM12 li_1213_134# vdd vdd li_917_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd vdd out vdd li_1213_134# li_1213_134# li_1213_134# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM13 vss li_1213_134# li_917_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 li_1213_134# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM25 vdd a_589_1133# vdd a_589_1133# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 a_589_1133# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16_1 li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM4GUT li_n545_286# li_n118_290# vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM16B_1 li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM2 li_n460_7# li_n545_286# a_879_204# vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XM1GUT li_n517_410# a_879_204# li_n545_286# vdd vss sky130_fd_pr__pfet_01v8_MP1P4U
+XXM6 li_n118_290# a_879_204# vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXM11B_1 vdd vdd a_589_1133# li_n517_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5GUT a_879_204# vdd li_n118_290# vdd vss sky130_fd_pr__pfet_01v8_MP3P0U
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XMX3GUT vdd li_n545_286# vdd li_n118_290# vss sky130_fd_pr__pfet_01v8_MP0P75
+XXM11_1 vdd vdd a_589_1133# li_n517_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11B li_n517_410# vdd a_589_1133# vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 vdd li_917_51# vdd a_879_204# vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11 li_n517_410# vdd a_589_1133# vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 a_879_204# vss li_917_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+C0 vctrl li_n460_7# 0.12fF
+C1 a_589_1133# vss 0.39fF
+C2 li_n545_286# li_n517_410# 0.02fF
+C3 li_n118_290# vss 0.17fF
+C4 a_589_1133# a_879_204# 0.19fF
+C5 li_1213_134# vss 0.61fF
+C6 li_n118_290# a_879_204# 0.15fF
+C7 li_1213_134# a_879_204# 0.00fF
+C8 vdd a_589_1133# 2.98fF
+C9 li_n545_286# vss 0.14fF
+C10 vctrl vss 0.64fF
+C11 li_n118_290# vdd 0.19fF
+C12 vdd li_1213_134# 0.88fF
+C13 li_1213_134# out 0.27fF
+C14 li_n545_286# a_879_204# 0.18fF
+C15 li_n545_286# vdd 0.14fF
+C16 li_n460_7# li_n517_410# 0.04fF
+C17 li_n460_7# vss 1.72fF
+C18 li_n460_7# a_879_204# 0.16fF
+C19 vctrl a_589_1133# 0.00fF
+C20 li_917_51# vss 0.29fF
+C21 a_879_204# li_n517_410# 0.19fF
+C22 li_n118_290# li_n545_286# 0.09fF
+C23 vctrl li_n118_290# 0.01fF
+C24 li_917_51# a_879_204# 0.05fF
+C25 vdd li_n517_410# 2.56fF
+C26 a_879_204# vss 0.60fF
+C27 vdd li_917_51# 0.14fF
+C28 li_917_51# out 0.01fF
+C29 vdd vss 0.05fF
+C30 vss out 0.21fF
+C31 li_n460_7# a_589_1133# 0.04fF
+C32 vdd a_879_204# 0.52fF
+C33 li_n460_7# li_n118_290# 0.01fF
+C34 a_589_1133# li_n517_410# 0.17fF
+C35 li_n118_290# li_n517_410# 0.00fF
+C36 vdd out 0.56fF
+C37 li_n118_290# li_917_51# 0.00fF
+C38 li_917_51# li_1213_134# 0.11fF
+C39 li_n460_7# li_n545_286# 0.02fF
+C40 vctrl 0 3.13fF
+C41 li_1213_134# 0 0.10fF
+C42 a_589_1133# 0 0.08fF
+C43 vdd 0 11.39fF
+C44 li_n517_410# 0 -0.73fF
+C45 a_879_204# 0 1.45fF
+C46 vss 0 -3.84fF
+C47 li_n460_7# 0 1.94fF
+C48 li_n118_290# 0 0.52fF
+C49 li_n545_286# 0 0.26fF
+C50 out 0 -0.25fF
+C51 li_917_51# 0 0.27fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..1592046
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_POST-LAYOUT_tb.log
@@ -0,0 +1,2361 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.62553e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.84734e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 6.006177e-06 at= 1.000500e-08
+vlow_outside_while = -5.981220e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.19874e-05
+supply_current_rms = 5.51701e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.59364e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.70511e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 4.275696e-06 at= 1.000500e-08
+vlow_outside_while = -4.255813e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 8.53151e-06
+supply_current_rms = 5.45065e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.39922e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.10555e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.140470e-06 at= 1.001500e-08
+vlow_outside_while = -1.128042e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 2.26851e-06
+supply_current_rms = 5.35560e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.39965e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.07788e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 3.376966e-06 at= 1.000500e-08
+vlow_outside_while = -3.356315e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 6.73328e-06
+supply_current_rms = 5.66274e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.19121e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.27630e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.056711e-06 at= 1.000500e-08
+vlow_outside_while = -2.040387e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 4.09710e-06
+supply_current_rms = 5.59314e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.46547e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 8.02524e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.251210e-01 at= 1.588500e-08
+vlow_outside_while = -5.922048e-02 at= 1.583500e-08
+peak_to_peak_outside_while= 2.84342e-01
+supply_current_rms = 1.16729e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.45479e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 9.18971e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928503e+00 at= 1.100500e-08
+vlow_outside_while = -8.134060e-02 at= 1.005500e-08
+peak_to_peak_outside_while= 2.00984e+00
+supply_current_rms = 1.53182e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 4.252541e-10 targ= 2.180345e-08 trig= 2.137819e-08
+fvco_outside_while = 2.35154e+09
+supply_current_rms_outside_while= 2.95837e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.02020e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929857e+00 at= 1.144500e-08
+vlow_outside_while = -7.714702e-02 at= 1.497500e-08
+peak_to_peak_outside_while= 2.00700e+00
+supply_current_rms = 2.94130e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.796168e-10 targ= 1.552873e-08 trig= 1.524911e-08
+fvco_outside_while = 3.57632e+09
+supply_current_rms_outside_while= 5.42020e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.23725e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927602e+00 at= 1.759500e-08
+vlow_outside_while = -8.337864e-02 at= 1.522500e-08
+peak_to_peak_outside_while= 2.01098e+00
+supply_current_rms = 5.24338e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.575129e-10 targ= 1.447668e-08 trig= 1.421917e-08
+fvco_outside_while = 3.88330e+09
+supply_current_rms_outside_while= 4.59497e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.57237e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922230e+00 at= 1.173500e-08
+vlow_outside_while = -8.340872e-02 at= 1.419500e-08
+peak_to_peak_outside_while= 2.00564e+00
+supply_current_rms = 4.54144e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.511065e-10 targ= 1.419816e-08 trig= 1.394705e-08
+fvco_outside_while = 3.98237e+09
+supply_current_rms_outside_while= 4.83419e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.84369e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.917886e+00 at= 1.930500e-08
+vlow_outside_while = -8.361652e-02 at= 1.065500e-08
+peak_to_peak_outside_while= 2.00150e+00
+supply_current_rms = 4.78015e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.487839e-10 targ= 1.407491e-08 trig= 1.382613e-08
+fvco_outside_while = 4.01955e+09
+supply_current_rms_outside_while= 5.09968e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.10737e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.914849e+00 at= 1.340500e-08
+vlow_outside_while = -8.372164e-02 at= 1.504500e-08
+peak_to_peak_outside_while= 1.99857e+00
+supply_current_rms = 5.03768e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.472385e-10 targ= 1.401300e-08 trig= 1.376576e-08
+fvco_outside_while = 4.04468e+09
+supply_current_rms_outside_while= 5.30730e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.31701e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.912884e+00 at= 1.532500e-08
+vlow_outside_while = -8.375353e-02 at= 1.522500e-08
+peak_to_peak_outside_while= 1.99664e+00
+supply_current_rms = 5.24026e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.465702e-10 targ= 1.398249e-08 trig= 1.373592e-08
+fvco_outside_while = 4.05564e+09
+supply_current_rms_outside_while= 5.41381e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.42430e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.911980e+00 at= 1.726500e-08
+vlow_outside_while = -8.375336e-02 at= 1.568500e-08
+peak_to_peak_outside_while= 1.99573e+00
+supply_current_rms = 5.34732e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.465469e-10 targ= 1.396429e-08 trig= 1.371775e-08
+fvco_outside_while = 4.05602e+09
+supply_current_rms_outside_while= 5.47868e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.49278e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.911503e+00 at= 1.699500e-08
+vlow_outside_while = -8.373515e-02 at= 1.763500e-08
+peak_to_peak_outside_while= 1.99524e+00
+supply_current_rms = 5.41205e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.458357e-10 targ= 1.395152e-08 trig= 1.370569e-08
+fvco_outside_while = 4.06776e+09
+supply_current_rms_outside_while= 5.52205e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.53673e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.911202e+00 at= 1.279500e-08
+vlow_outside_while = -8.371560e-02 at= 1.466500e-08
+peak_to_peak_outside_while= 1.99492e+00
+supply_current_rms = 5.45623e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.458044e-10 targ= 1.394250e-08 trig= 1.369670e-08
+fvco_outside_while = 4.06828e+09
+supply_current_rms_outside_while= 5.55577e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.57042e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910996e+00 at= 1.106500e-08
+vlow_outside_while = -8.370287e-02 at= 1.588500e-08
+peak_to_peak_outside_while= 1.99470e+00
+supply_current_rms = 5.48888e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.461096e-10 targ= 1.393586e-08 trig= 1.368975e-08
+fvco_outside_while = 4.06323e+09
+supply_current_rms_outside_while= 5.58282e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.59597e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910831e+00 at= 1.425500e-08
+vlow_outside_while = -8.368798e-02 at= 1.833500e-08
+peak_to_peak_outside_while= 1.99452e+00
+supply_current_rms = 5.51521e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_out_x1_3 6.80528e-09
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.1522e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07608e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -4.84676e-27
+x2:vdd#branch 4.96131e-15
+vmeas_current_gnd#branch 4.57125e-05
+vmeas_current_vdd#branch 4.57125e-05
+v2#branch -4.57126e-05
+x1:vctrl#branch 0
+x1:out#branch 4.84676e-27
+x1:vss#branch 4.57125e-05
+x1:vdd#branch -4.57125e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.453048e-10 targ= 1.393020e-08 trig= 1.368490e-08
+fvco_outside_while = 4.07656e+09
+supply_current_rms_outside_while= 5.60259e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.61536e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910717e+00 at= 1.621500e-08
+vlow_outside_while = -8.367983e-02 at= 1.562500e-08
+peak_to_peak_outside_while= 1.99440e+00
+supply_current_rms = 5.53405e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.453048e-10 targ= 1.393020e-08 trig= 1.368490e-08
+Original line no.: 0, new internal line no.: 12503:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.076560964643878e+09 " u=" 4.076560964643878e+09 " id=0
+fvco_outside_while = 4.07656e+09
+supply_current_rms_outside_while= 5.60259e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.61536e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.910717e+00 at= 1.621500e-08
+vlow_outside_while = -8.367983e-02 at= 1.562500e-08
+Original line no.: 0, new internal line no.: 12509:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 1.994396963740868e+00 " u=" 1.994396963740868e+00 " id=0
+peak_to_peak_outside_while= 1.99440e+00
+supply_current_rms = 5.53405e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 9.0219
+
+Total CPU time (seconds) = 175.509
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 120.273 MB.
+Maximum ngspice program size = 684.711 MB.
+Current ngspice program size = 665.734 MB.
+
+Shared ngspice pages = 8.738 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.230 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_V2_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_V2_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..2a77c71
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_V2_POST-LAYOUT_tb.log
@@ -0,0 +1,2361 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.53138e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.26057e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.129125e-06 at= 1.001500e-08
+vlow_outside_while = -1.118302e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 2.24743e-06
+supply_current_rms = 5.47458e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.15793e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.87151e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.886023e-06 at= 1.000500e-08
+vlow_outside_while = -2.868703e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 5.75473e-06
+supply_current_rms = 5.73279e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 3.39398e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.09614e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 7.266411e-07 at= 1.001500e-08
+vlow_outside_while = -7.143019e-07 at= 1.000500e-08
+peak_to_peak_outside_while= 1.44094e-06
+supply_current_rms = 5.89225e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 2.63014e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.62008e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 8.848695e-07 at= 1.814500e-08
+vlow_outside_while = -8.712259e-07 at= 1.815500e-08
+peak_to_peak_outside_while= 1.75610e-06
+supply_current_rms = 5.46776e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.65309e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.45277e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 5.051472e-06 at= 1.000500e-08
+vlow_outside_while = -5.030846e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 1.00823e-05
+supply_current_rms = 5.19956e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 7.04542e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 6.75481e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.922754e+00 at= 1.472500e-08
+vlow_outside_while = -8.342222e-02 at= 1.459500e-08
+peak_to_peak_outside_while= 2.00618e+00
+supply_current_rms = 8.42989e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 9.13072e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.05355e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923655e+00 at= 1.197500e-08
+vlow_outside_while = -8.147752e-02 at= 1.011500e-08
+peak_to_peak_outside_while= 2.00513e+00
+supply_current_rms = 1.04676e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 6.149339e-10 targ= 3.079698e-08 trig= 3.018205e-08
+fvco_outside_while = 1.62619e+09
+supply_current_rms_outside_while= 2.28230e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.35744e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929407e+00 at= 1.956500e-08
+vlow_outside_while = -8.148000e-02 at= 1.171500e-08
+peak_to_peak_outside_while= 2.01089e+00
+supply_current_rms = 2.29102e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.402937e-10 targ= 1.843733e-08 trig= 1.809704e-08
+fvco_outside_while = 2.93864e+09
+supply_current_rms_outside_while= 3.95843e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.81187e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929528e+00 at= 1.927500e-08
+vlow_outside_while = -8.477888e-02 at= 1.126500e-08
+peak_to_peak_outside_while= 2.01431e+00
+supply_current_rms = 3.93347e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.811130e-10 targ= 1.563638e-08 trig= 1.535526e-08
+fvco_outside_while = 3.55729e+09
+supply_current_rms_outside_while= 4.44171e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.34395e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927479e+00 at= 1.771500e-08
+vlow_outside_while = -8.313838e-02 at= 1.842500e-08
+peak_to_peak_outside_while= 2.01062e+00
+supply_current_rms = 4.39213e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.645656e-10 targ= 1.482535e-08 trig= 1.456079e-08
+fvco_outside_while = 3.77978e+09
+supply_current_rms_outside_while= 4.77452e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.73556e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924861e+00 at= 1.201500e-08
+vlow_outside_while = -8.294165e-02 at= 1.189500e-08
+peak_to_peak_outside_while= 2.00780e+00
+supply_current_rms = 4.71489e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.580450e-10 targ= 1.453970e-08 trig= 1.428165e-08
+fvco_outside_while = 3.87529e+09
+supply_current_rms_outside_while= 5.14205e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.05654e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.923061e+00 at= 1.669500e-08
+vlow_outside_while = -8.314189e-02 at= 1.890500e-08
+peak_to_peak_outside_while= 2.00620e+00
+supply_current_rms = 5.07687e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.551504e-10 targ= 1.440888e-08 trig= 1.415373e-08
+fvco_outside_while = 3.91926e+09
+supply_current_rms_outside_while= 5.28857e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.28067e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.921963e+00 at= 1.960500e-08
+vlow_outside_while = -8.310749e-02 at= 1.157500e-08
+peak_to_peak_outside_while= 2.00507e+00
+supply_current_rms = 5.22046e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.543894e-10 targ= 1.434598e-08 trig= 1.409159e-08
+fvco_outside_while = 3.93098e+09
+supply_current_rms_outside_while= 5.40069e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.40066e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.921515e+00 at= 1.646500e-08
+vlow_outside_while = -8.303452e-02 at= 1.330500e-08
+peak_to_peak_outside_while= 2.00455e+00
+supply_current_rms = 5.33387e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.530863e-10 targ= 1.430734e-08 trig= 1.405426e-08
+fvco_outside_while = 3.95122e+09
+supply_current_rms_outside_while= 5.65461e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.46543e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.920838e+00 at= 1.008500e-08
+vlow_outside_while = -8.223664e-02 at= 1.073500e-08
+peak_to_peak_outside_while= 2.00308e+00
+supply_current_rms = 5.89111e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.528223e-10 targ= 1.428095e-08 trig= 1.402813e-08
+fvco_outside_while = 3.95535e+09
+supply_current_rms_outside_while= 5.51524e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.51855e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.921123e+00 at= 1.967500e-08
+vlow_outside_while = -8.289089e-02 at= 1.501500e-08
+peak_to_peak_outside_while= 2.00401e+00
+supply_current_rms = 5.45116e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.525764e-10 targ= 1.426188e-08 trig= 1.400930e-08
+fvco_outside_while = 3.95920e+09
+supply_current_rms_outside_while= 5.55120e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.55420e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.921023e+00 at= 1.308500e-08
+vlow_outside_while = -8.283867e-02 at= 1.398500e-08
+peak_to_peak_outside_while= 2.00386e+00
+supply_current_rms = 5.48506e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.517866e-10 targ= 1.424729e-08 trig= 1.399550e-08
+fvco_outside_while = 3.97162e+09
+supply_current_rms_outside_while= 5.58213e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.58070e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.920948e+00 at= 1.584500e-08
+vlow_outside_while = -8.280451e-02 at= 1.447500e-08
+peak_to_peak_outside_while= 2.00375e+00
+supply_current_rms = 5.51428e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15224e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03802e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80998e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch 0
+x2:vdd#branch 4.88498e-15
+vmeas_current_gnd#branch 4.62723e-05
+vmeas_current_vdd#branch 4.62723e-05
+v2#branch -4.62724e-05
+x1:vctrl#branch 0
+x1:out#branch 0
+x1:vss#branch 4.62723e-05
+x1:vdd#branch -4.62723e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.517535e-10 targ= 1.423614e-08 trig= 1.398439e-08
+fvco_outside_while = 3.97214e+09
+supply_current_rms_outside_while= 5.60065e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.59951e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.920877e+00 at= 1.356500e-08
+vlow_outside_while = -8.274649e-02 at= 1.068500e-08
+peak_to_peak_outside_while= 2.00362e+00
+supply_current_rms = 5.53288e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.517535e-10 targ= 1.423614e-08 trig= 1.398439e-08
+Original line no.: 0, new internal line no.: 12503:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.972140146074597e+09 " u=" 3.972140146074597e+09 " id=0
+fvco_outside_while = 3.97214e+09
+supply_current_rms_outside_while= 5.60065e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.59951e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.920877e+00 at= 1.356500e-08
+vlow_outside_while = -8.274649e-02 at= 1.068500e-08
+Original line no.: 0, new internal line no.: 12509:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.003623330469933e+00 " u=" 2.003623330469933e+00 " id=0
+peak_to_peak_outside_while= 2.00362e+00
+supply_current_rms = 5.53288e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 11.1922
+
+Total CPU time (seconds) = 226.012
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 1973.199 MB.
+Maximum ngspice program size = 684.738 MB.
+Current ngspice program size = 665.977 MB.
+
+Shared ngspice pages = 8.957 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.258 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_V3_POST-LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_V3_POST-LAYOUT_tb.log
new file mode 100755
index 0000000..21022c8
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_V3_POST-LAYOUT_tb.log
@@ -0,0 +1,2361 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.47059e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.44399e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 0.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.049010e-06 at= 1.001500e-08
+vlow_outside_while = -2.038777e-06 at= 1.000500e-08
+peak_to_peak_outside_while= 4.08779e-06
+supply_current_rms = 4.56254e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.88155e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.46054e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 2.096252e-07 at= 1.998500e-08
+vlow_outside_while = -1.961523e-07 at= 1.999500e-08
+peak_to_peak_outside_while= 4.05777e-07
+supply_current_rms = 4.71433e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.52743e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.24555e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 2.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 5.763693e-07 at= 1.598500e-08
+vlow_outside_while = -5.627312e-07 at= 1.599500e-08
+peak_to_peak_outside_while= 1.13910e-06
+supply_current_rms = 4.58081e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 5.51130e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.45017e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 3.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.596008e-06 at= 1.022500e-08
+vlow_outside_while = -1.582167e-06 at= 1.023500e-08
+peak_to_peak_outside_while= 3.17817e-06
+supply_current_rms = 6.80625e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 6.76109e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.29137e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 4.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 4.346318e-06 at= 1.000500e-08
+vlow_outside_while = -4.327548e-06 at= 1.001500e-08
+peak_to_peak_outside_while= 8.67387e-06
+supply_current_rms = 8.41469e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 8.73517e-05 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.44835e-05 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 5.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926721e+00 at= 1.581500e-08
+vlow_outside_while = -8.179972e-02 at= 1.394500e-08
+peak_to_peak_outside_while= 2.00852e+00
+supply_current_rms = 8.44256e-05 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+
+Error: measure tvco_outside_while (TRIG) : out of interval
+ .meas tran tvco_outside_while trig v(out) val=0.5*1.8 rise=50 targ v(out) val=0.5*1.8 rise=51 failed!
+
+Original line no.: 0, new internal line no.: 12503:
+Undefined number [tvco_outside_while]
+Original line no.: 0, new internal line no.: 12503:
+Cannot compute substitute
+fvco_outside_while = failed
+supply_current_rms_outside_while= 1.15670e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.02342e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 6.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.924313e+00 at= 1.037500e-08
+vlow_outside_while = -7.743863e-02 at= 1.051500e-08
+peak_to_peak_outside_while= 2.00175e+00
+supply_current_rms = 1.20398e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 8.826840e-10 targ= 4.389865e-08 trig= 4.301596e-08
+fvco_outside_while = 1.13291e+09
+supply_current_rms_outside_while= 1.83363e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 1.81406e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 7.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928989e+00 at= 1.897500e-08
+vlow_outside_while = -8.555207e-02 at= 1.385500e-08
+peak_to_peak_outside_while= 2.01454e+00
+supply_current_rms = 1.84201e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 4.637176e-10 targ= 2.442657e-08 trig= 2.396285e-08
+fvco_outside_while = 2.15649e+09
+supply_current_rms_outside_while= 2.61182e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 2.68829e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 8.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929607e+00 at= 1.725500e-08
+vlow_outside_while = -8.595637e-02 at= 1.559500e-08
+peak_to_peak_outside_while= 2.01556e+00
+supply_current_rms = 2.59629e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 3.487510e-10 targ= 1.894535e-08 trig= 1.859660e-08
+fvco_outside_while = 2.86738e+09
+supply_current_rms_outside_while= 3.55934e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 3.63062e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.929410e+00 at= 1.352500e-08
+vlow_outside_while = -8.520573e-02 at= 1.264500e-08
+peak_to_peak_outside_while= 2.01462e+00
+supply_current_rms = 3.52328e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.967953e-10 targ= 1.644517e-08 trig= 1.614837e-08
+fvco_outside_while = 3.36933e+09
+supply_current_rms_outside_while= 4.42089e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.40911e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.000000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.928784e+00 at= 1.182500e-08
+vlow_outside_while = -8.338599e-02 at= 1.523500e-08
+peak_to_peak_outside_while= 2.01217e+00
+supply_current_rms = 4.36889e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.788511e-10 targ= 1.560083e-08 trig= 1.532198e-08
+fvco_outside_while = 3.58614e+09
+supply_current_rms_outside_while= 5.04380e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.86517e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927736e+00 at= 1.738500e-08
+vlow_outside_while = -8.257120e-02 at= 1.111500e-08
+peak_to_peak_outside_while= 2.01031e+00
+supply_current_rms = 4.97943e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.720737e-10 targ= 1.527910e-08 trig= 1.500702e-08
+fvco_outside_while = 3.67548e+09
+supply_current_rms_outside_while= 5.11892e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.11521e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.200000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.927179e+00 at= 1.048500e-08
+vlow_outside_while = -8.202654e-02 at= 1.035500e-08
+peak_to_peak_outside_while= 2.00921e+00
+supply_current_rms = 5.05620e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.691380e-10 targ= 1.513224e-08 trig= 1.486311e-08
+fvco_outside_while = 3.71557e+09
+supply_current_rms_outside_while= 5.26048e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.24946e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926977e+00 at= 1.577500e-08
+vlow_outside_while = -8.166619e-02 at= 1.268500e-08
+peak_to_peak_outside_while= 2.00864e+00
+supply_current_rms = 5.19211e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.677119e-10 targ= 1.504503e-08 trig= 1.477732e-08
+fvco_outside_while = 3.73536e+09
+supply_current_rms_outside_while= 5.34244e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.33178e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.400000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926869e+00 at= 1.862500e-08
+vlow_outside_while = -8.141402e-02 at= 1.662500e-08
+peak_to_peak_outside_while= 2.00828e+00
+supply_current_rms = 5.27572e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.663868e-10 targ= 1.498637e-08 trig= 1.471999e-08
+fvco_outside_while = 3.75394e+09
+supply_current_rms_outside_while= 5.39918e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.39074e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926801e+00 at= 1.189500e-08
+vlow_outside_while = -8.123174e-02 at= 1.123500e-08
+peak_to_peak_outside_while= 2.00803e+00
+supply_current_rms = 5.33251e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.656366e-10 targ= 1.494456e-08 trig= 1.467892e-08
+fvco_outside_while = 3.76454e+09
+supply_current_rms_outside_while= 5.44575e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.43064e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.600000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926759e+00 at= 1.345500e-08
+vlow_outside_while = -8.109526e-02 at= 1.863500e-08
+peak_to_peak_outside_while= 2.00785e+00
+supply_current_rms = 5.37592e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.648203e-10 targ= 1.491306e-08 trig= 1.464824e-08
+fvco_outside_while = 3.77615e+09
+supply_current_rms_outside_while= 5.48073e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.46400e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926740e+00 at= 1.554500e-08
+vlow_outside_while = -8.097988e-02 at= 1.859500e-08
+peak_to_peak_outside_while= 2.00772e+00
+supply_current_rms = 5.41173e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/3-stage_cs-vco_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+int_out_x1_3 6.80528e-09
+int_net1_x1_1 1.8
+int_net2_x1_2 0
+int_vctrl_x1_4 0
+net1 1.8
+net2 0
+out 6.80528e-09
+vctrl 0
+vdd 1.8
+int_vdd_x2_1 1.8
+int_out_x2_2 6.80528e-09
+int_gnd_x2_3 0
+int_gnd_x3_2 0
+int_out_x3_1 6.80528e-09
+int_gnd_x3_3 0
+int_buf1_out_x3_6 2.60627e-09
+int_vdd_x3_5 1.8
+int_vdd_x3_4 1.8
+buf1_out 2.60627e-09
+int_buf1_out_x4_1 2.60627e-09
+int_vdd_x4_5 1.8
+int_vdd_x4_4 1.8
+int_gnd_x4_2 0
+int_gnd_x4_3 0
+int_net4_x4_6 4.9501e-09
+net4 4.9501e-09
+int_vdd_x5_5 1.8
+int_net5_x5_6 4.9501e-09
+int_vdd_x5_4 1.8
+int_net4_x5_1 4.9501e-09
+int_gnd_x5_2 0
+int_gnd_x5_3 0
+net5 4.9501e-09
+int_net3_x6_6 4.9501e-09
+int_gnd_x6_2 0
+int_gnd_x6_3 0
+int_net5_x6_1 4.9501e-09
+int_vdd_x6_5 1.8
+int_vdd_x6_4 1.8
+net3 4.9501e-09
+int_vdd_x7_5 1.8
+int_buf16_out_x7_6 4.9501e-09
+int_vdd_x7_4 1.8
+int_gnd_x7_2 0
+int_gnd_x7_3 0
+int_net3_x7_1 4.9501e-09
+buf16_out 4.9501e-09
+v1#branch 0
+x7:x#branch 0
+x7:vpwr#branch -8.17036e-12
+x7:vpb#branch -4.15223e-11
+x7:vnb#branch 7.2401e-12
+x7:vgnd#branch 4.24513e-11
+x7:a#branch 0
+x6:x#branch 0
+x6:vpwr#branch -4.08518e-12
+x6:vpb#branch -2.07605e-11
+x6:vnb#branch 3.62005e-12
+x6:vgnd#branch 2.12257e-11
+x6:a#branch 0
+x5:x#branch 0
+x5:vpwr#branch -2.04259e-12
+x5:vpb#branch -1.03803e-11
+x5:vnb#branch 1.81003e-12
+x5:vgnd#branch 1.06128e-11
+x5:a#branch 0
+x4:x#branch 0
+x4:vpwr#branch -1.9439e-12
+x4:vpb#branch -5.1902e-12
+x4:vnb#branch 1.81003e-12
+x4:vgnd#branch 5.32401e-12
+x4:a#branch 0
+x3:x#branch 0
+x3:vpwr#branch -2.01847e-12
+x3:vpb#branch -1.80997e-12
+x3:vnb#branch 1.81009e-12
+x3:vgnd#branch 2.01837e-12
+x3:a#branch 0
+x2:vss#branch 0
+x2:clk#branch -1.13091e-26
+x2:vdd#branch 5.77316e-15
+vmeas_current_gnd#branch 4.74707e-05
+vmeas_current_vdd#branch 4.74707e-05
+v2#branch -4.74708e-05
+x1:vctrl#branch 0
+x1:out#branch 1.13091e-26
+x1:vss#branch 4.74707e-05
+x1:vdd#branch -4.74707e-05
+
+
+No. of Data Rows : 7020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.639002e-10 targ= 1.488874e-08 trig= 1.462484e-08
+fvco_outside_while = 3.78931e+09
+supply_current_rms_outside_while= 5.51154e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.49154e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926720e+00 at= 1.710500e-08
+vlow_outside_while = -8.090649e-02 at= 1.301500e-08
+peak_to_peak_outside_while= 2.00763e+00
+supply_current_rms = 5.43891e-04 from= 0.00000e+00 to= 7.00000e-08
+
+binary raw file "3-stage_cs-vco_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.639002e-10 targ= 1.488874e-08 trig= 1.462484e-08
+Original line no.: 0, new internal line no.: 12503:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 3.789310826506999e+09 " u=" 3.789310826506999e+09 " id=0
+fvco_outside_while = 3.78931e+09
+supply_current_rms_outside_while= 5.51154e-04 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.49154e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.800000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.926720e+00 at= 1.710500e-08
+vlow_outside_while = -8.090649e-02 at= 1.301500e-08
+Original line no.: 0, new internal line no.: 12509:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 2.007626762667582e+00 " u=" 2.007626762667582e+00 " id=0
+peak_to_peak_outside_while= 2.00763e+00
+supply_current_rms = 5.43891e-04 from= 0.00000e+00 to= 7.00000e-08
+
+
+Total analysis time (seconds) = 10.9962
+
+Total CPU time (seconds) = 239.461
+
+Total DRAM available = 7955.125 MB.
+DRAM currently available = 1391.191 MB.
+Maximum ngspice program size = 684.719 MB.
+Current ngspice program size = 665.906 MB.
+
+Shared ngspice pages = 8.906 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 657.238 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.ext
new file mode 100755
index 0000000..ff72b06
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.ext
@@ -0,0 +1,376 @@
+timestamp 1645896155
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B 1 0 -200 0 1 -537
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 50 0 1 -397
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -407 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -613 0 1 -537
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 -1 0 256 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -391
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1356 0 1 -4
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT 0 -1 -167 1 0 101
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT 0 1 -99 -1 0 351
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 49 0 1 899
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -437 1 0 101
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT 0 1 -465 -1 0 351
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 256 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1 1 0 350 0 1 898
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT 0 -1 517 1 0 351
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 886 0 1 105
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 597
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -410 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -616 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B 1 0 -204 0 1 1040
+port "vctrl" 3 -1076 -752 -876 -552 m1
+port "out" 2 1849 118 2049 318 m1
+port "vdd" 0 1172 1542 1372 1742 m1
+port "vss" 1 1202 -1174 1402 -974 m1
+node "vctrl" 6 2218.82 -1076 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53472 1532 58184 2946 0 0 0 0 0 0 0 0
+node "m1_488_n269#" 1 1064.12 488 -269 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14116 712 0 0 0 0 0 0 0 0 0 0
+node "out" 3 727.503 1849 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 88560 3228 0 0 0 0 0 0 0 0 0 0
+node "m1_n707_n334#" 5 800.165 -707 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85514 3810 0 0 0 0 0 0 0 0 0 0
+node "m1_n480_1050#" 4 -241.09 -480 1050 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19682 962 34376 1770 0 0 0 0 0 0 0 0
+node "li_528_n678#" 55 277.715 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_n678#" 57 216.793 223 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 119 377.338 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11254 730 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n460_7#" 41 1985.43 -460 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 48024 2030 0 0 0 0 0 0 0 0 0 0
+node "li_1213_134#" 52 151.34 1213 134 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_917_51#" 207 373.634 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 410.13 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n102_132#" 264 581.568 -102 132 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24694 1530 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n118_290#" 51 6.86424 -118 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 831 146 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n690_207#" 232 1333.42 -690 207 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17102 1192 35970 2150 0 0 0 0 0 0 0 0 0 0
+node "li_n545_286#" 287 457.118 -545 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27234 1670 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_338#" 172 52.2552 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16286 1026 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n517_410#" 53 -27.88 -517 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 56246 2434 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 141 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13362 854 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 -11.48 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_1149#" 57 -11.48 223 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_16_1150#" 24 0 16 1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 129.284 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_n694#" 114 108.297 289 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 61.7185 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_1133#" 114 4.8972 289 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 24493 9526.43 1172 1542 m1 0 0 0 0 2889575 7440 0 0 177990 10470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 205700 12304 1032616 22016 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 1202 -1174 m1 2816355 7384 0 0 0 0 0 0 0 0 177412 10436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 188700 11304 1061862 22532 0 0 0 0 0 0 0 0 0 0
+cap "li_223_1149#" "li_523_1149#" 8.01429
+cap "li_n118_290#" "vdd" 47.8032
+cap "li_611_133#" "li_n690_207#" 25.3289
+cap "vdd" "li_223_1149#" 160.213
+cap "li_n517_410#" "m1_n707_n334#" 61.7541
+cap "li_16_1150#" "m1_n480_1050#" 22
+cap "vdd" "a_289_1133#" 51.7
+cap "li_n545_286#" "vdd" 259.942
+cap "li_n460_7#" "li_n690_207#" 148.715
+cap "vdd" "m1_n480_1050#" 1814.32
+cap "li_1179_338#" "li_1213_134#" 37.5411
+cap "li_n545_286#" "li_n690_207#" 77.2976
+cap "m1_n707_n334#" "vctrl" 2.925
+cap "li_1179_n70#" "li_917_51#" 0.798387
+cap "li_917_51#" "li_611_133#" 28.2715
+cap "m1_n707_n334#" "li_n460_7#" 44.1353
+cap "a_289_n694#" "vctrl" 42.185
+cap "m1_n480_1050#" "m1_n707_n334#" 29.1549
+cap "li_n517_410#" "li_n460_7#" 27.8642
+cap "li_n545_286#" "li_n517_410#" 64.4913
+cap "vdd" "li_n102_132#" 146.063
+cap "li_n517_410#" "m1_n480_1050#" 5.50532
+cap "li_n102_132#" "li_n690_207#" 80.6316
+cap "li_1179_338#" "vdd" 198.559
+cap "m1_488_n269#" "li_n460_7#" 25.3203
+cap "li_917_51#" "li_1213_134#" 12.6752
+cap "a_589_1133#" "a_289_1133#" 5.58088
+cap "vdd" "li_16_1150#" 116.501
+cap "li_n545_286#" "li_n118_290#" 12.1957
+cap "a_289_1133#" "li_223_1149#" 25.2972
+cap "vdd" "li_523_1149#" 251.869
+cap "a_289_n694#" "li_223_n678#" 25.2972
+cap "m1_n480_1050#" "li_223_1149#" 125.626
+cap "a_879_204#" "vdd" 11
+cap "li_223_n678#" "vctrl" 133.998
+cap "li_1179_n70#" "li_1213_134#" 15.4737
+cap "li_n545_286#" "li_n460_7#" 53.7118
+cap "vdd" "li_n690_207#" 276.123
+cap "li_528_n678#" "li_223_n678#" 7.73793
+cap "li_1179_338#" "li_1179_712#" 3.3
+cap "li_1213_134#" "li_611_133#" 4.49096
+cap "m1_n480_1050#" "a_289_1133#" 35.605
+cap "vdd" "li_1179_712#" 286.665
+cap "li_1179_338#" "li_917_51#" 32.2616
+cap "vdd" "m1_n707_n334#" 522.229
+cap "li_n102_132#" "li_611_133#" 3.57049
+cap "a_289_n694#" "a_590_n694#" 5.56044
+cap "m1_n707_n334#" "li_n690_207#" 124.571
+cap "li_n118_290#" "li_n102_132#" 23.2619
+cap "li_917_51#" "vdd" 126.227
+cap "li_n517_410#" "vdd" 1353.63
+cap "li_1179_n70#" "li_1179_338#" 10.1455
+cap "li_528_n678#" "a_590_n694#" 25.2972
+cap "li_n517_410#" "li_n690_207#" 147.972
+cap "li_n545_286#" "li_n102_132#" 30.6658
+cap "a_589_1133#" "li_523_1149#" 25.2972
+cap "li_16_1150#" "li_223_1149#" 7.7234
+cap "vdd" "out" 311.915
+cap "vdd" "li_611_133#" 94.682
+cap "a_879_204#" "li_611_133#" 11.55
+cap "vdd" "a_589_1133#" 72.485
+cap "M1GUT/a_n73_n144#" "XM16_1/a_n76_n209#" 3.73718
+cap "XM2/a_n33_63#" "XM4GUT/a_15_n96#" 20.7815
+cap "XMDUM26B/a_n76_n69#" "XM4GUT/a_n33_33#" 136.545
+cap "XMDUM26B/a_n76_n69#" "XM26/a_n76_n69#" 496.397
+cap "M1GUT/a_n73_n144#" "XM2/a_n33_63#" 7.94326
+cap "XM26/a_n33_n157#" "XM16_1/a_n76_n209#" 49.7847
+cap "XMDUM26B/a_n76_n69#" "XM4GUT/a_15_n96#" 127.376
+cap "MX3GUT/a_n73_n64#" "XM4GUT/a_15_n96#" 20.1161
+cap "XMDUM26B/a_n76_n69#" "XM16_1/a_n76_n209#" 767.223
+cap "XMDUM26B/a_n76_n69#" "XM26/a_n33_n157#" 500.676
+cap "MX3GUT/w_n109_n164#" "XM4GUT/a_15_n96#" 3.60186
+cap "XM4GUT/a_n33_33#" "XM4GUT/a_15_n96#" 21.0955
+cap "M1GUT/a_n73_n144#" "XM4GUT/a_n33_33#" 4.9252
+cap "XMDUM26B/a_n76_n69#" "XM2/a_n33_63#" 239.861
+cap "XM4GUT/a_n33_33#" "XM16_1/a_n76_n209#" -34.9764
+cap "XM26/a_n33_n157#" "XM26/a_n76_n69#" 0.734364
+cap "XMDUM26B/a_n76_n69#" "MX3GUT/a_n73_n64#" 3.35404
+cap "XM2/a_n33_63#" "XM4GUT/a_n33_33#" 37.1179
+cap "XM4GUT/a_15_n96#" "XM16_1/a_n76_n209#" 5.03684
+cap "XM26/a_n33_n157#" "XM4GUT/a_15_n96#" 1.23214
+cap "XMDUM16/a_n76_n209#" "XM16_1/a_n76_n209#" 207.988
+cap "XM12/a_n73_n240#" "XM13/a_n33_142#" -2.56667
+cap "XM6/a_15_n175#" "XMDUM11B/a_n33_235#" 0.676471
+cap "XM21/a_n72_n22#" "XMDUM16/a_n76_n209#" 5.57731
+cap "XMDUM16/a_n76_n209#" "XM13/a_15_n120#" 620.764
+cap "XM6/a_15_n175#" "XMDUM11/w_n112_n338#" 8.46751
+cap "XM21/a_n72_n22#" "XM6/a_15_n175#" 8.01429
+cap "XM4GUT/a_15_n96#" "XM16_1/a_n33_n297#" 2.59677
+cap "XM6/a_15_n175#" "XM13/a_15_n120#" 0.444378
+cap "XM6/a_15_n175#" "XMDUM16/a_n76_n209#" 338.538
+cap "XM24/a_18_n129#" "XM13/a_n33_142#" 5.15315
+cap "XM4GUT/a_15_n96#" "XMDUM16/a_n76_n209#" 40.1554
+cap "XMDUM16/a_n76_n209#" "XM12/a_n73_n240#" 7.62219
+cap "XM5GUT/a_15_n236#" "XMDUM16/a_n76_n209#" 3.78464
+cap "XM4GUT/a_15_n96#" "XM6/a_15_n175#" -1.76347
+cap "XM5GUT/a_15_n236#" "XM6/a_15_n175#" 17.3744
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 28.1783
+cap "XM24/a_18_n129#" "XM13/a_15_n120#" 60.3698
+cap "XMDUM16/a_n76_n209#" "XM13/a_n33_142#" 243.429
+cap "XM16_1/a_n33_n297#" "XM16_1/a_n76_n209#" 0.0100099
+cap "XM24/a_18_n129#" "XMDUM16/a_n76_n209#" 238.368
+cap "XM6/a_15_n175#" "XM13/a_n33_142#" 6.9818
+cap "XMDUM16/a_n76_n209#" "XM16_1/a_n33_n297#" 65.4542
+cap "XM23/a_n173_n220#" "XM13/a_15_n120#" 3.1875
+cap "XM23/a_n173_n220#" "XMDUM16/a_n76_n209#" 2.29918
+cap "XM24/a_18_n129#" "XM24/a_n76_n129#" 2.12372
+cap "XM24/a_18_n129#" "vss" -27.47
+cap "XM4GUT/a_n73_n96#" "MX3GUT/w_n109_n164#" 3.35404
+cap "XM4GUT/a_15_n96#" "XM4GUT/a_n73_n96#" 4.29146
+cap "vss" "XM2/a_n33_63#" 9.19586
+cap "vss" "XM4GUT/a_n33_33#" 3.57325
+cap "XM2/a_n33_63#" "MX3GUT/w_n109_n164#" 57.7703
+cap "XM4GUT/a_15_n96#" "XM2/a_n33_63#" 47.5508
+cap "XM4GUT/a_n33_33#" "MX3GUT/w_n109_n164#" -116.517
+cap "XM2/a_n33_63#" "M1GUT/a_n73_n144#" 16.4545
+cap "XM4GUT/a_15_n96#" "XM4GUT/a_n33_33#" 22.2006
+cap "XM4GUT/a_n33_33#" "M1GUT/a_n73_n144#" -45.2266
+cap "XM4GUT/a_n33_33#" "XM16_1/a_n76_n209#" 3.42098
+cap "XM2/a_n33_63#" "XM11/a_n33_235#" 66.4329
+cap "XM4GUT/a_15_n96#" "vss" 3.99528
+cap "XM4GUT/a_15_n96#" "MX3GUT/w_n109_n164#" -23.7578
+cap "XM4GUT/a_15_n96#" "M1GUT/a_n73_n144#" 0.166247
+cap "M1GUT/a_n73_n144#" "MX3GUT/w_n109_n164#" 187.641
+cap "XM11/a_n33_235#" "MX3GUT/w_n109_n164#" 320.214
+cap "XM16_1/a_n76_n209#" "M1GUT/a_n73_n144#" 3.73718
+cap "M1GUT/a_n73_n144#" "XM11/a_n33_235#" 41.998
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+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 214.413
+cap "XM13/a_n73_n120#" "XM13/a_n33_142#" 7.5625
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+cap "XM13/a_15_n120#" "XM24/a_n76_n129#" 3.35928
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+cap "XM4GUT/a_15_n96#" "XM6/a_15_n175#" -1.49383
+cap "XM13/a_15_n120#" "XMDUM11/w_n112_n338#" 394.213
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+cap "XM4GUT/a_15_n96#" "XM13/a_n33_142#" 0.385475
+cap "XM11/a_n33_235#" "XMDUM11/w_n112_n338#" -71.6596
+cap "XMDUM11/w_n112_n338#" "XM6/a_15_n175#" 48.4904
+cap "XM13/a_15_n120#" "vss" -13.94
+cap "XMDUM11/w_n112_n338#" "XM13/a_n33_142#" 13.6743
+cap "XMDUM11/w_n112_n338#" "XM6/a_n73_n175#" 3.78464
+cap "vss" "XM6/a_15_n175#" 2.67994
+cap "XM11/a_n33_235#" "XM11/a_18_n276#" -0.215568
+cap "vss" "XM13/a_n33_142#" 41.7792
+cap "XM13/a_n73_n120#" "XMDUM11/w_n112_n338#" 7.62219
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 39.9911
+cap "XMDUM11/w_n112_n338#" "XM24/a_18_n129#" 247.957
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+cap "XM6/a_15_n175#" "XM6/a_n73_n175#" 17.4167
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+merge "XM13/a_15_n120#" "li_1179_n70#"
+merge "li_1179_n70#" "li_1213_134#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.mag
new file mode 100755
index 0000000..4dacc13
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.mag
@@ -0,0 +1,446 @@
+magic
+tech sky130A
+magscale 1 2
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+rect -146 399 -70 412
+rect 348 450 755 465
+rect 790 486 830 1237
+rect 884 957 924 1237
+rect 1085 1084 1713 1237
+rect 1085 810 1131 1084
+rect 1636 840 1676 1084
+rect 790 452 870 486
+rect 348 416 364 450
+rect 741 416 755 450
+rect 348 402 755 416
+rect 824 377 870 452
+rect 1085 406 1091 810
+rect 1125 406 1131 810
+rect 1286 800 1676 840
+rect 1382 460 1743 500
+rect 1085 382 1131 406
+rect -622 241 -564 247
+rect 337 241 395 247
+rect -622 207 -610 241
+rect -576 207 349 241
+rect 383 207 395 241
+rect -622 201 -564 207
+rect 337 201 395 207
+rect 1703 234 1743 460
+rect 1849 234 2049 318
+rect 1703 194 2049 234
+rect -485 41 -324 51
+rect -485 7 -460 41
+rect -352 7 -324 41
+rect -485 -25 -324 7
+rect -168 44 -58 52
+rect -168 10 -131 44
+rect -97 10 -58 44
+rect -168 0 -58 10
+rect 330 49 751 55
+rect 330 15 365 49
+rect 629 15 751 49
+rect 330 9 751 15
+rect -370 -79 -324 -25
+rect -89 -19 -58 0
+rect 681 -19 751 9
+rect 807 42 868 52
+rect 807 8 821 42
+rect 855 8 868 42
+rect 1703 30 1743 194
+rect 1849 118 2049 194
+rect 807 0 868 8
+rect -89 -50 751 -19
+rect -370 -125 326 -79
+rect 280 -153 326 -125
+rect 488 -125 627 -79
+rect -707 -334 -431 -288
+rect -477 -423 -431 -334
+rect -1076 -635 -876 -552
+rect -1076 -687 -1012 -635
+rect -960 -687 -876 -635
+rect -1076 -752 -876 -687
+rect -680 -724 -640 -457
+rect -586 -724 -546 -457
+rect -380 -553 -299 -457
+rect -444 -635 -364 -623
+rect -444 -687 -433 -635
+rect -381 -687 -364 -635
+rect -444 -691 -364 -687
+rect -433 -693 -381 -691
+rect -336 -724 -299 -553
+rect -266 -724 -226 -448
+rect -172 -724 -132 -454
+rect -16 -724 24 -191
+rect 76 -724 116 -191
+rect 158 -610 227 -169
+rect 158 -724 198 -610
+rect 278 -635 330 -629
+rect 227 -684 278 -638
+rect 330 -684 379 -638
+rect 278 -693 330 -687
+rect 418 -724 487 -263
+rect 488 -269 533 -125
+rect 581 -152 627 -125
+rect 681 -602 751 -50
+rect 822 -55 862 0
+rect 1426 -10 1743 30
+rect 578 -638 630 -629
+rect 528 -684 680 -638
+rect 578 -724 630 -684
+rect 711 -724 751 -602
+rect 786 -94 930 -55
+rect 786 -632 826 -94
+rect 890 -632 930 -94
+rect 1086 -342 1128 -47
+rect 1288 -342 1328 -63
+rect 1086 -344 1652 -342
+rect 786 -678 930 -632
+rect 786 -724 826 -678
+rect 890 -724 930 -678
+rect 973 -411 1652 -344
+rect 973 -663 989 -411
+rect 1023 -663 1652 -411
+rect 973 -724 1652 -663
+rect -819 -747 1755 -724
+rect -819 -781 -779 -747
+rect 894 -781 1755 -747
+rect -819 -872 1755 -781
+rect 1202 -1174 1402 -872
+<< via1 >>
+rect -436 1141 -384 1193
+rect 277 1141 329 1193
+rect -1012 -687 -960 -635
+rect -433 -687 -381 -635
+rect 278 -687 330 -635
+<< metal2 >>
+rect -442 1141 -436 1193
+rect -384 1187 -378 1193
+rect 271 1187 277 1193
+rect -384 1147 277 1187
+rect -384 1141 -378 1147
+rect 271 1141 277 1147
+rect 329 1187 335 1193
+rect 329 1147 379 1187
+rect 329 1141 335 1147
+rect -1018 -687 -1012 -635
+rect -960 -641 -954 -635
+rect -439 -641 -433 -635
+rect -960 -681 -433 -641
+rect -960 -687 -954 -681
+rect -439 -687 -433 -681
+rect -381 -641 -375 -635
+rect 272 -641 278 -635
+rect -381 -681 278 -641
+rect -381 -687 -375 -681
+rect 272 -687 278 -681
+rect 330 -641 336 -635
+rect 330 -681 379 -641
+rect 330 -687 336 -681
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -200 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -407 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -613 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -410 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -616 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -204 0 1 1040
+box -112 -198 112 164
+<< labels >>
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+rlabel metal1 -1076 -752 -876 -552 1 vctrl
+port 3 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.spice
new file mode 100755
index 0000000..82d871e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v2.spice
@@ -0,0 +1,313 @@
+* NGSPICE file created from 3-stage_cs-vco_dpgutfeel_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n78_n220# a_n173_n220# 0.31fF
+C1 a_114_n220# a_n78_n220# 0.18fF
+C2 a_114_n220# a_n173_n220# 0.07fF
+C3 a_n129_n317# a_n33_251# 0.02fF
+C4 a_n78_n220# w_n209_n320# 0.33fF
+C5 a_n173_n220# w_n209_n320# 0.28fF
+C6 a_114_n220# w_n209_n320# 0.33fF
+C7 a_114_n220# a_63_n317# 0.00fF
+C8 a_n33_251# a_18_n220# 0.00fF
+C9 a_63_n317# w_n209_n320# 0.14fF
+C10 a_n78_n220# a_n129_n317# 0.00fF
+C11 a_n173_n220# a_n129_n317# 0.00fF
+C12 a_n129_n317# w_n209_n320# 0.14fF
+C13 a_n78_n220# a_n33_251# 0.00fF
+C14 a_63_n317# a_n129_n317# 0.03fF
+C15 a_n78_n220# a_18_n220# 0.31fF
+C16 a_n173_n220# a_18_n220# 0.14fF
+C17 a_114_n220# a_18_n220# 0.31fF
+C18 a_n33_251# w_n209_n320# 0.14fF
+C19 a_63_n317# a_n33_251# 0.02fF
+C20 a_18_n220# w_n209_n320# 0.28fF
+C21 a_63_n317# a_18_n220# 0.00fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_15_n240# a_n73_n240# 0.20fF
+C1 a_15_n240# w_n109_n340# 0.17fF
+C2 a_n73_n240# w_n109_n340# 0.19fF
+C3 a_n33_n337# w_n109_n340# 0.11fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n136# a_n76_n136# 0.20fF
+C1 a_18_n136# a_n33_95# 0.00fF
+C2 a_n76_n136# a_n33_95# 0.00fF
+C3 a_18_n136# w_n112_n198# 0.16fF
+C4 a_n76_n136# w_n112_n198# 0.16fF
+C5 a_n33_95# w_n112_n198# 0.19fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_18_n129# a_n76_n129# 0.21fF
+C1 a_18_n129# a_n33_n217# 0.01fF
+C2 a_n76_n129# a_n33_n217# 0.01fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_15_n120# a_n73_n120# 0.15fF
+C1 a_15_n120# a_n33_142# 0.00fF
+C2 a_n73_n120# a_n33_142# 0.01fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n69# a_n76_n69# 0.17fF
+C1 a_18_n69# a_n33_n157# 0.01fF
+C2 a_n76_n69# a_n33_n157# 0.00fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n76_n209# 0.35fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n76_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n276# a_n76_n276# 0.46fF
+C1 a_18_n276# a_n33_235# 0.00fF
+C2 a_n76_n276# a_n33_235# 0.00fF
+C3 a_18_n276# w_n112_n338# 0.32fF
+C4 a_n76_n276# w_n112_n338# 0.32fF
+C5 a_n33_235# w_n112_n338# 0.19fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n96# a_n73_n96# 0.06fF
+C1 a_15_n96# a_n33_33# 0.00fF
+C2 a_n73_n96# a_n33_33# 0.00fF
+C3 a_15_n96# VSUBS 0.02fF
+C4 a_n73_n96# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n76_n209# 0.47fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n76_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
++ VSUBS
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+C0 a_15_n144# a_n73_n144# 0.15fF
+C1 a_15_n144# a_n33_n241# 0.00fF
+C2 a_n73_n144# a_n33_n241# 0.00fF
+C3 a_15_n144# w_n109_n244# 0.13fF
+C4 a_n73_n144# w_n109_n244# 0.13fF
+C5 a_n33_n241# w_n109_n244# 0.14fF
+C6 a_15_n144# VSUBS -0.11fF
+C7 a_n73_n144# VSUBS -0.11fF
+C8 a_n33_n241# VSUBS -0.01fF
+C9 w_n109_n244# VSUBS 0.29fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_15_n103# a_n73_n103# 0.07fF
+C1 a_15_n103# a_n33_63# 0.00fF
+C2 a_n73_n103# a_n33_63# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_15_n175# a_n73_n175# 0.16fF
+C1 a_15_n175# a_n33_135# 0.00fF
+C2 a_n73_n175# a_n33_135# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+C0 a_15_n236# a_n73_n236# 0.32fF
+C1 a_15_n236# a_n33_395# 0.00fF
+C2 a_n73_n236# a_n33_395# 0.00fF
+C3 a_15_n236# w_n109_n298# 0.26fF
+C4 a_n73_n236# w_n109_n298# 0.26fF
+C5 a_n33_395# w_n109_n298# 0.14fF
+C6 a_15_n236# VSUBS -0.25fF
+C7 a_n73_n236# VSUBS -0.25fF
+C8 a_n33_395# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.50fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+C0 a_15_n64# a_n73_n64# 0.07fF
+C1 a_15_n64# a_n33_n161# 0.00fF
+C2 a_n73_n64# a_n33_n161# 0.00fF
+C3 a_15_n64# w_n109_n164# 0.06fF
+C4 a_n73_n64# w_n109_n164# 0.06fF
+C5 a_n33_n161# w_n109_n164# 0.14fF
+C6 a_15_n64# VSUBS -0.06fF
+C7 a_n73_n64# VSUBS -0.06fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 a_15_n22# a_n72_n22# 0.09fF
+C1 a_15_n22# w_n109_n58# 0.08fF
+C2 a_n72_n22# w_n109_n58# 0.14fF
+C3 a_n15_n53# w_n109_n58# 0.05fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_15_n68# a_n73_n68# 0.04fF
+C1 a_15_n68# a_n33_33# 0.00fF
+C2 a_n73_n68# a_n33_33# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt x3-stage_cs-vco_dp7 vdd vss out vctrl
+XXM23 vdd vdd out vdd li_1213_134# li_1213_134# li_1213_134# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 li_1213_134# vdd vdd li_917_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM25 vdd a_289_1133# vdd a_289_1133# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM24 li_1213_134# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss li_1213_134# li_917_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM26 a_289_1133# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM25B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4GUT li_n545_286# li_n118_290# vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM16_1 li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B_1 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XM1GUT li_n517_410# a_879_204# li_n545_286# vdd vss sky130_fd_pr__pfet_01v8_MP1P4U
+XXM2 li_n460_7# li_n545_286# a_879_204# vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM6 li_n118_290# a_879_204# vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXM11B_1 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5GUT a_879_204# vdd li_n118_290# vdd vss sky130_fd_pr__pfet_01v8_MP3P0U
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XMX3GUT vdd li_n545_286# vdd li_n118_290# vss sky130_fd_pr__pfet_01v8_MP0P75
+XXM11_1 vdd vdd a_289_1133# li_n517_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 vdd li_917_51# vdd a_879_204# vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 a_879_204# vss li_917_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 li_n517_410# vdd a_289_1133# vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 li_1213_134# vdd 0.88fF
+C1 li_917_51# out 0.01fF
+C2 vss a_879_204# 0.61fF
+C3 vss a_289_1133# 0.50fF
+C4 out vdd 0.56fF
+C5 li_917_51# a_879_204# 0.05fF
+C6 li_n460_7# li_n545_286# 0.02fF
+C7 li_n545_286# li_n517_410# 0.02fF
+C8 a_879_204# vdd 0.52fF
+C9 a_289_1133# vdd 2.84fF
+C10 li_n460_7# li_n517_410# 0.04fF
+C11 li_n460_7# vctrl 0.05fF
+C12 a_879_204# li_n545_286# 0.18fF
+C13 out li_1213_134# 0.27fF
+C14 li_n460_7# a_879_204# 0.15fF
+C15 a_879_204# li_n517_410# 0.17fF
+C16 li_n460_7# a_289_1133# 0.04fF
+C17 li_n517_410# a_289_1133# 0.11fF
+C18 vss li_n118_290# 0.18fF
+C19 a_879_204# li_1213_134# 0.00fF
+C20 vctrl a_289_1133# 0.00fF
+C21 li_917_51# li_n118_290# 0.00fF
+C22 li_917_51# vss 0.29fF
+C23 li_n118_290# vdd 0.19fF
+C24 vss vdd 0.05fF
+C25 a_879_204# a_289_1133# 0.19fF
+C26 li_917_51# vdd 0.14fF
+C27 li_n118_290# li_n545_286# 0.09fF
+C28 vss li_n545_286# 0.14fF
+C29 li_n118_290# li_n460_7# 0.01fF
+C30 li_n118_290# li_n517_410# 0.00fF
+C31 vss li_n460_7# 1.00fF
+C32 li_n118_290# vctrl 0.00fF
+C33 vss vctrl 0.58fF
+C34 li_n545_286# vdd 0.14fF
+C35 vss li_1213_134# 0.61fF
+C36 vss out 0.21fF
+C37 li_n517_410# vdd 1.68fF
+C38 li_917_51# li_1213_134# 0.11fF
+C39 li_n118_290# a_879_204# 0.15fF
+C40 vctrl 0 2.27fF
+C41 li_1213_134# 0 0.10fF
+C42 a_289_1133# 0 0.11fF
+C43 vdd 0 10.74fF
+C44 a_879_204# 0 1.45fF
+C45 li_n517_410# 0 -0.64fF
+C46 li_n460_7# 0 1.59fF
+C47 li_n118_290# 0 0.52fF
+C48 li_n545_286# 0 0.26fF
+C49 vss 0 -3.43fF
+C50 li_917_51# 0 0.27fF
+C51 out 0 -0.25fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.ext b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.ext
new file mode 100755
index 0000000..461a0a6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.ext
@@ -0,0 +1,378 @@
+timestamp 1645902895
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B 1 0 -200 0 1 -537
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16 1 0 50 0 1 -397
+use sky130_fd_pr__nfet_01v8_B87NCT XM26 1 0 -407 0 1 -537
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26 1 0 -613 0 1 -537
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1 1 0 651 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B -1 0 557 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1 1 0 350 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XM16 -1 0 256 0 1 -397
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B 1 0 858 0 1 -391
+use sky130_fd_pr__nfet_01v8_44BYND XM13 1 0 1152 0 1 54
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24 1 0 1356 0 1 -4
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT 0 -1 -167 1 0 101
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT 0 1 -99 -1 0 351
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11 1 0 49 0 1 899
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2 0 -1 -437 1 0 101
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT 0 1 -465 -1 0 351
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1 1 0 650 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B 1 0 556 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11 1 0 256 0 1 898
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1 1 0 350 0 1 898
+use sky130_fd_pr__nfet_01v8_8T82FM XM6 0 -1 466 1 0 101
+use sky130_fd_pr__pfet_01v8_AZHELG XM21 1 0 894 0 1 300
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B 1 0 858 0 1 897
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT 0 -1 517 1 0 351
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12 1 0 1152 0 1 582
+use sky130_fd_pr__nfet_01v8_LS29AB XM22 1 0 886 0 1 105
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23 1 0 1453 0 1 597
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25 1 0 -410 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25 1 0 -616 0 1 1039
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B 1 0 -204 0 1 1040
+port "vctrl" 3 -1076 -752 -876 -552 m1
+port "out" 2 1849 118 2049 318 m1
+port "vdd" 0 1172 1542 1372 1742 m1
+port "vss" 1 1202 -1174 1402 -974 m1
+node "m1_230_n469#" 0 4211.79 230 -469 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35638 758 0 0 0 0 0 0 0 0 0 0
+node "vctrl" 4 1760.27 -1076 -752 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48872 1332 46304 2352 0 0 0 0 0 0 0 0
+node "m1_488_n269#" 1 1054.51 488 -269 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14116 712 0 0 0 0 0 0 0 0 0 0
+node "out" 3 727.503 1849 118 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 88560 3228 0 0 0 0 0 0 0 0 0 0
+node "m1_326_759#" 1 0 326 759 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9888 508 0 0 0 0 0 0 0 0 0 0
+node "m1_n707_n334#" 5 800.165 -707 -334 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85514 3810 0 0 0 0 0 0 0 0 0 0
+node "m1_n480_1050#" 3 -131.48 -480 1050 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15926 786 22456 1174 0 0 0 0 0 0 0 0
+node "li_528_n678#" 55 277.715 528 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_n678#" 57 304.782 223 -678 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_n70#" 119 377.338 1179 -70 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11254 730 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n460_7#" 41 1225.88 -460 7 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 284 38134 1600 0 0 0 0 0 0 0 0 0 0
+node "li_1213_134#" 52 151.34 1213 134 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4930 358 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_917_51#" 207 373.634 917 51 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21084 1268 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_611_133#" 169 410.13 611 133 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15663 1000 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n102_132#" 264 581.568 -102 132 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24694 1530 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n118_290#" 51 6.86424 -118 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 831 146 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n690_207#" 232 1324.35 -690 207 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17102 1192 35970 2150 0 0 0 0 0 0 0 0 0 0
+node "li_n545_286#" 287 457.118 -545 286 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27234 1670 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1179_338#" 172 52.2552 1179 338 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16286 1026 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n517_410#" 52 -27.88 -517 410 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4726 346 43592 1870 0 0 0 0 0 0 0 0 0 0
+node "li_1179_712#" 141 0 1179 712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13362 854 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_523_1149#" 57 -11.48 523 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_223_1149#" 57 -11.48 223 1149 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5440 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_16_1150#" 24 0 16 1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_590_n694#" 114 129.284 590 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_n694#" 114 129.284 289 -694 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_879_204#" 69 61.7185 879 204 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1290 146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_589_1133#" 114 4.8972 589 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_289_1133#" 114 4.8972 289 1133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1848 188 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "vdd" 24493 9506.75 1172 1542 m1 0 0 0 0 2889575 7440 0 0 177990 10470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 205700 12304 1037750 21514 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 1202 -1174 m1 2816355 7384 0 0 0 0 0 0 0 0 177412 10436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 188700 11304 1036673 20864 0 0 0 0 0 0 0 0 0 0
+cap "li_223_1149#" "li_523_1149#" 8.01429
+cap "vctrl" "m1_n707_n334#" 2.925
+cap "li_1213_134#" "li_611_133#" 4.49096
+cap "a_289_n694#" "a_590_n694#" 5.56044
+cap "li_528_n678#" "a_590_n694#" 25.2972
+cap "li_n517_410#" "m1_n480_1050#" 1.2605
+cap "li_1213_134#" "li_1179_338#" 37.5411
+cap "li_16_1150#" "vdd" 75.1051
+cap "li_1213_134#" "li_1179_n70#" 15.4737
+cap "a_879_204#" "vdd" 11
+cap "li_1179_712#" "li_1179_338#" 3.3
+cap "li_1213_134#" "li_917_51#" 12.6752
+cap "li_16_1150#" "li_223_1149#" 7.7234
+cap "li_n517_410#" "li_n545_286#" 64.4913
+cap "vdd" "li_1179_712#" 286.665
+cap "a_289_n694#" "li_223_n678#" 25.2972
+cap "li_611_133#" "li_n102_132#" 3.57049
+cap "li_n118_290#" "li_n545_286#" 12.1957
+cap "vdd" "m1_n480_1050#" 1305.61
+cap "li_n545_286#" "li_n102_132#" 30.6658
+cap "li_223_n678#" "li_528_n678#" 7.73793
+cap "li_917_51#" "li_611_133#" 28.2715
+cap "m1_488_n269#" "m1_230_n469#" 3.17647
+cap "li_1179_n70#" "li_1179_338#" 10.1455
+cap "li_n517_410#" "li_n460_7#" 27.8642
+cap "li_n118_290#" "li_n102_132#" 23.2619
+cap "li_n460_7#" "li_n545_286#" 53.7118
+cap "li_917_51#" "li_1179_338#" 32.2616
+cap "li_n517_410#" "vdd" 798.322
+cap "li_917_51#" "li_1179_n70#" 0.798387
+cap "li_611_133#" "vdd" 94.682
+cap "vdd" "li_n545_286#" 259.942
+cap "a_289_1133#" "a_589_1133#" 5.58088
+cap "li_n517_410#" "li_n690_207#" 107.187
+cap "li_n517_410#" "m1_326_759#" 2.7
+cap "li_611_133#" "li_n690_207#" 25.3289
+cap "a_289_1133#" "vdd" 72.485
+cap "li_n690_207#" "li_n545_286#" 77.2976
+cap "vdd" "li_1179_338#" 198.559
+cap "out" "vdd" 311.915
+cap "li_n118_290#" "vdd" 47.8032
+cap "vdd" "li_n102_132#" 146.063
+cap "li_917_51#" "vdd" 126.227
+cap "li_n690_207#" "li_n102_132#" 80.6316
+cap "m1_n480_1050#" "m1_n707_n334#" 29.1549
+cap "vdd" "a_589_1133#" 72.485
+cap "a_289_1133#" "li_223_1149#" 25.2972
+cap "li_n460_7#" "li_n690_207#" 101.512
+cap "li_n517_410#" "m1_n707_n334#" 61.7541
+cap "li_n690_207#" "vdd" 276.123
+cap "m1_326_759#" "vdd" 608.376
+cap "li_n460_7#" "vctrl" 0.230179
+cap "li_223_1149#" "vdd" 239.711
+cap "li_n460_7#" "m1_n707_n334#" 44.1353
+cap "li_16_1150#" "m1_n480_1050#" 55.3554
+cap "li_523_1149#" "a_589_1133#" 25.2972
+cap "vdd" "m1_n707_n334#" 522.229
+cap "li_523_1149#" "vdd" 251.869
+cap "li_n690_207#" "m1_n707_n334#" 124.571
+cap "a_879_204#" "li_611_133#" 11.55
+cap "XMDUM16/a_n76_n209#" "XM4GUT/a_15_n96#" 4.41732
+cap "XMDUM16/a_n76_n209#" "XM4GUT/a_n33_33#" -34.9764
+cap "XMDUM16/a_n76_n209#" "XMDUM16/a_n33_n297#" -0.188512
+cap "XM26/a_n76_n69#" "XMDUM26B/a_n76_n69#" 496.397
+cap "XM4GUT/a_n33_33#" "XM4GUT/a_15_n96#" 21.0955
+cap "MX3GUT/a_n73_n64#" "XM4GUT/a_15_n96#" 20.1161
+cap "XMDUM16/a_n33_n297#" "XM26/a_n76_n69#" 0.734364
+cap "M1GUT/a_n73_n144#" "XM2/a_n33_63#" 7.94326
+cap "XMDUM16/a_n76_n209#" "M1GUT/a_n73_n144#" 3.73718
+cap "MX3GUT/w_n109_n164#" "XM4GUT/a_15_n96#" 3.60186
+cap "M1GUT/a_n73_n144#" "XM4GUT/a_n33_33#" 4.9252
+cap "XMDUM26B/a_n76_n69#" "XM2/a_n33_63#" 245.518
+cap "XMDUM16/a_n76_n209#" "XMDUM26B/a_n76_n69#" 669.219
+cap "XM4GUT/a_n33_33#" "XMDUM26B/a_n76_n69#" 136.545
+cap "XMDUM26B/a_n76_n69#" "XM4GUT/a_15_n96#" 129.228
+cap "XMDUM16/a_n33_n297#" "XMDUM26B/a_n76_n69#" 693.72
+cap "XM4GUT/a_n33_33#" "XM2/a_n33_63#" 37.1179
+cap "MX3GUT/a_n73_n64#" "XMDUM26B/a_n76_n69#" 3.35404
+cap "XM4GUT/a_15_n96#" "XM2/a_n33_63#" 20.7815
+cap "XMDUM16/a_n76_n209#" "XMDUM16/a_18_n209#" 25.4627
+cap "XM13/a_15_n120#" "XM23/a_n173_n220#" 3.1875
+cap "XM24/a_18_n129#" "XMDUM16/a_18_n209#" 238.368
+cap "XM6/a_15_n175#" "XMDUM11/w_n112_n338#" 8.46751
+cap "XM13/a_n33_142#" "XM12/a_n73_n240#" -2.56667
+cap "XMDUM16/a_n33_n297#" "XMDUM16/a_18_n209#" 0.573315
+cap "XM13/a_15_n120#" "XMDUM16/a_18_n209#" 620.764
+cap "XM13/a_n33_142#" "XMDUM16/a_18_n209#" 243.429
+cap "XMDUM16/a_18_n209#" "XM5GUT/a_15_n236#" 3.78464
+cap "XM23/a_n173_n220#" "XMDUM16/a_18_n209#" 2.29918
+cap "XM6/a_15_n175#" "XM13/a_15_n120#" 0.444378
+cap "XM6/a_15_n175#" "XM13/a_n33_142#" 6.9818
+cap "XM12/a_n73_n240#" "XMDUM16/a_18_n209#" 7.62219
+cap "XM6/a_15_n175#" "XMDUM11B/a_n33_235#" 0.676471
+cap "XM4GUT/a_15_n96#" "XMDUM16/a_18_n209#" 42.7521
+cap "XM21/a_n72_n22#" "XMDUM16/a_18_n209#" 5.57731
+cap "XM6/a_15_n175#" "XM5GUT/a_15_n236#" 17.3744
+cap "XM6/a_15_n175#" "XM4GUT/a_15_n96#" -1.76347
+cap "XM6/a_15_n175#" "XM21/a_n72_n22#" 8.01429
+cap "XM6/a_15_n175#" "XMDUM16/a_18_n209#" 338.796
+cap "XM13/a_15_n120#" "XM24/a_18_n129#" 60.3698
+cap "XM13/a_n33_142#" "XM24/a_18_n129#" 5.15315
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 28.1783
+cap "vss" "XM24/a_18_n129#" -27.47
+cap "XM24/a_18_n129#" "XM24/a_n76_n129#" 2.12372
+cap "XM4GUT/a_15_n96#" "XM4GUT/a_n33_33#" 22.2006
+cap "XM4GUT/a_15_n96#" "XMDUM11/a_n76_n276#" 3.96964
+cap "XMDUM11/a_n33_235#" "XMDUM11/a_n76_n276#" 0.0122156
+cap "XM4GUT/a_n73_n96#" "XM4GUT/a_15_n96#" 4.29146
+cap "XM4GUT/a_15_n96#" "vss" 3.99528
+cap "MX3GUT/w_n109_n164#" "XM4GUT/a_n33_33#" -116.517
+cap "MX3GUT/w_n109_n164#" "XMDUM11/a_n76_n276#" 291.137
+cap "XMDUM11/a_n33_235#" "XM2/a_n33_63#" 66.4329
+cap "XM4GUT/a_n73_n96#" "MX3GUT/w_n109_n164#" 3.35404
+cap "XM4GUT/a_15_n96#" "XM2/a_n33_63#" 47.5508
+cap "MX3GUT/w_n109_n164#" "XM2/a_n33_63#" 61.5354
+cap "XM16_1/a_n76_n209#" "XM2/a_n33_63#" 2.68293
+cap "XM4GUT/a_15_n96#" "XMDUM11/a_n33_235#" 1.18779
+cap "XM4GUT/a_15_n96#" "MX3GUT/w_n109_n164#" -28.7489
+cap "MX3GUT/w_n109_n164#" "XMDUM11/a_n33_235#" 343.594
+cap "XMDUM11/a_n76_n276#" "XM4GUT/a_n33_33#" -45.2266
+cap "vss" "XM4GUT/a_n33_33#" 3.57325
+cap "XM2/a_n33_63#" "XM4GUT/a_n33_33#" 67.0322
+cap "XM2/a_n73_n103#" "XM4GUT/a_n33_33#" 3.42098
+cap "XMDUM11/a_n76_n276#" "XM2/a_n33_63#" 12.6894
+cap "vss" "XM2/a_n33_63#" 9.19586
+cap "XM2/a_n73_n103#" "XMDUM11/a_n76_n276#" 3.73718
+cap "vss" "XMDUM11/w_n112_n338#" 1.85762
+cap "XMDUM11/a_n33_235#" "XMDUM11/w_n112_n338#" -1.50648
+cap "XMDUM11/a_n76_n276#" "XMDUM11/w_n112_n338#" 21.6568
+cap "XM6/a_15_n175#" "XM13/a_n33_142#" 11.0353
+cap "vss" "XM6/a_15_n175#" 2.67994
+cap "XM22/a_n73_n68#" "XMDUM11/w_n112_n338#" 3.7197
+cap "XM13/a_15_n120#" "XM24/a_n76_n129#" 3.35928
+cap "XM13/a_n33_142#" "XM4GUT/a_15_n96#" 0.385475
+cap "XM13/a_n73_n120#" "XM13/a_n33_142#" 7.5625
+cap "XM24/a_18_n129#" "XM13/a_15_n120#" 214.413
+cap "XM6/a_15_n175#" "XMDUM11/w_n112_n338#" 48.4904
+cap "XM6/a_15_n175#" "XM16_1/a_n76_n209#" 0.121951
+cap "XM13/a_15_n120#" "vss" -13.94
+cap "XM13/a_15_n120#" "XM13/a_n33_142#" 39.9911
+cap "XM13/a_n73_n120#" "XMDUM11/w_n112_n338#" 7.62219
+cap "XM6/a_n73_n175#" "XMDUM11/w_n112_n338#" 3.78464
+cap "XM24/a_n76_n129#" "XMDUM11/w_n112_n338#" 2.29918
+cap "vss" "XM13/a_n33_142#" 41.7792
+cap "XM6/a_15_n175#" "XM4GUT/a_15_n96#" -1.49383
+cap "XM6/a_n73_n175#" "XM6/a_15_n175#" 17.4167
+cap "XM13/a_15_n120#" "XMDUM11/w_n112_n338#" 394.213
+cap "XM24/a_18_n129#" "XMDUM11/w_n112_n338#" 247.957
+cap "XM13/a_n33_142#" "XMDUM11/w_n112_n338#" 13.6743
+merge "XM5GUT/a_n33_395#" "XM6/a_n33_135#" -142.171 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12015 -610 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM6/a_n33_135#" "MX3GUT/a_15_n64#"
+merge "MX3GUT/a_15_n64#" "li_n118_290#"
+merge "li_n118_290#" "XM4GUT/a_15_n96#"
+merge "XM4GUT/a_15_n96#" "li_n102_132#"
+merge "XMDUM25B/VSUBS" "XMDUM25/VSUBS" -4969.15 -117171 -3779 0 0 0 0 0 0 23524 -2152 489940 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39732 -528 0 0 319808 -3592 -38620 -8606 0 0 0 0 0 0 0 0 0 0
+merge "XMDUM25/VSUBS" "XM25/VSUBS"
+merge "XM25/VSUBS" "XM23/VSUBS"
+merge "XM23/VSUBS" "XM22/VSUBS"
+merge "XM22/VSUBS" "XM22/a_n73_n68#"
+merge "XM22/a_n73_n68#" "XM12/VSUBS"
+merge "XM12/VSUBS" "XMDUM11B/VSUBS"
+merge "XMDUM11B/VSUBS" "XM21/VSUBS"
+merge "XM21/VSUBS" "XM24/VSUBS"
+merge "XM24/VSUBS" "XM24/a_n76_n129#"
+merge "XM24/a_n76_n129#" "XM13/VSUBS"
+merge "XM13/VSUBS" "XM13/a_n73_n120#"
+merge "XM13/a_n73_n120#" "XMDUM16B/VSUBS"
+merge "XMDUM16B/VSUBS" "XMDUM16B/a_n33_n297#"
+merge "XMDUM16B/a_n33_n297#" "XMDUM16B/a_18_n209#"
+merge "XMDUM16B/a_18_n209#" "XMDUM16B/a_n76_n209#"
+merge "XMDUM16B/a_n76_n209#" "XM5GUT/VSUBS"
+merge "XM5GUT/VSUBS" "XM6/VSUBS"
+merge "XM6/VSUBS" "XM6/a_n73_n175#"
+merge "XM6/a_n73_n175#" "XM11_1/VSUBS"
+merge "XM11_1/VSUBS" "XM11/VSUBS"
+merge "XM11/VSUBS" "XM11B/VSUBS"
+merge "XM11B/VSUBS" "XM11B_1/VSUBS"
+merge "XM11B_1/VSUBS" "M1GUT/VSUBS"
+merge "M1GUT/VSUBS" "XM2/VSUBS"
+merge "XM2/VSUBS" "XMDUM11/VSUBS"
+merge "XMDUM11/VSUBS" "MX3GUT/VSUBS"
+merge "MX3GUT/VSUBS" "XM4GUT/VSUBS"
+merge "XM4GUT/VSUBS" "XM4GUT/a_n73_n96#"
+merge "XM4GUT/a_n73_n96#" "XM16/VSUBS"
+merge "XM16/VSUBS" "XM16/a_18_n209#"
+merge "XM16/a_18_n209#" "XM16/a_n33_n297#"
+merge "XM16/a_n33_n297#" "XM16/a_n76_n209#"
+merge "XM16/a_n76_n209#" "XM16_1/VSUBS"
+merge "XM16_1/VSUBS" "XM16_1/a_18_n209#"
+merge "XM16_1/a_18_n209#" "XM16_1/a_n76_n209#"
+merge "XM16_1/a_n76_n209#" "m1_230_n469#"
+merge "m1_230_n469#" "XM16_1/a_n33_n297#"
+merge "XM16_1/a_n33_n297#" "li_223_n678#"
+merge "li_223_n678#" "a_289_n694#"
+merge "a_289_n694#" "XM16B/VSUBS"
+merge "XM16B/VSUBS" "XM16B/a_18_n209#"
+merge "XM16B/a_18_n209#" "XM16B/a_n76_n209#"
+merge "XM16B/a_n76_n209#" "XM16B_1/a_n76_n209#"
+merge "XM16B_1/a_n76_n209#" "m1_488_n269#"
+merge "m1_488_n269#" "XM16B/a_n33_n297#"
+merge "XM16B/a_n33_n297#" "XM16B_1/VSUBS"
+merge "XM16B_1/VSUBS" "XM16B_1/a_n33_n297#"
+merge "XM16B_1/a_n33_n297#" "li_528_n678#"
+merge "li_528_n678#" "a_590_n694#"
+merge "a_590_n694#" "XM16B_1/a_18_n209#"
+merge "XM16B_1/a_18_n209#" "XMDUM26/VSUBS"
+merge "XMDUM26/VSUBS" "XMDUM26/a_n33_n157#"
+merge "XMDUM26/a_n33_n157#" "XMDUM26/a_18_n69#"
+merge "XMDUM26/a_18_n69#" "XMDUM26/a_n76_n69#"
+merge "XMDUM26/a_n76_n69#" "XM26/VSUBS"
+merge "XM26/VSUBS" "XM26/a_18_n69#"
+merge "XM26/a_18_n69#" "XMDUM16/VSUBS"
+merge "XMDUM16/VSUBS" "XMDUM16/a_18_n209#"
+merge "XMDUM16/a_18_n209#" "XMDUM26B/VSUBS"
+merge "XMDUM26B/VSUBS" "XMDUM26B/a_n33_n157#"
+merge "XMDUM26B/a_n33_n157#" "XMDUM26B/a_18_n69#"
+merge "XMDUM26B/a_18_n69#" "XMDUM26B/a_n76_n69#"
+merge "XMDUM26B/a_n76_n69#" "vss"
+merge "XM23/a_18_n220#" "XM23/a_n173_n220#" 2410.57 0 0 0 0 -420512 -23112 0 0 652392 0 337920 -2152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39600 -528 0 0 750342 -4586 3025346 -8118 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n173_n220#" "XMDUM11B/a_18_n276#"
+merge "XMDUM11B/a_18_n276#" "XMDUM11B/a_n33_235#"
+merge "XMDUM11B/a_n33_235#" "XMDUM11B/a_n76_n276#"
+merge "XMDUM11B/a_n76_n276#" "XMDUM25B/a_n33_95#"
+merge "XMDUM25B/a_n33_95#" "XMDUM25B/a_18_n136#"
+merge "XMDUM25B/a_18_n136#" "XMDUM25B/a_n76_n136#"
+merge "XMDUM25B/a_n76_n136#" "XMDUM25B/w_n112_n198#"
+merge "XMDUM25B/w_n112_n198#" "XMDUM25/a_18_n136#"
+merge "XMDUM25/a_18_n136#" "XMDUM25/a_n76_n136#"
+merge "XMDUM25/a_n76_n136#" "XMDUM25/a_n33_95#"
+merge "XMDUM25/a_n33_95#" "XMDUM25/w_n112_n198#"
+merge "XMDUM25/w_n112_n198#" "XM25/a_18_n136#"
+merge "XM25/a_18_n136#" "XM25/w_n112_n198#"
+merge "XM25/w_n112_n198#" "XM11_1/a_18_n276#"
+merge "XM11_1/a_18_n276#" "XM11_1/a_n33_235#"
+merge "XM11_1/a_n33_235#" "XM11_1/a_n76_n276#"
+merge "XM11_1/a_n76_n276#" "m1_326_759#"
+merge "m1_326_759#" "XM11/a_18_n276#"
+merge "XM11/a_18_n276#" "XM11/a_n76_n276#"
+merge "XM11/a_n76_n276#" "XM11/a_n33_235#"
+merge "XM11/a_n33_235#" "li_223_1149#"
+merge "li_223_1149#" "a_289_1133#"
+merge "a_289_1133#" "XM11B/a_n76_n276#"
+merge "XM11B/a_n76_n276#" "XM11B/a_n33_235#"
+merge "XM11B/a_n33_235#" "XM11B_1/a_18_n276#"
+merge "XM11B_1/a_18_n276#" "XM11B/a_18_n276#"
+merge "XM11B/a_18_n276#" "XM11B_1/a_n76_n276#"
+merge "XM11B_1/a_n76_n276#" "XM11B_1/a_n33_235#"
+merge "XM11B_1/a_n33_235#" "li_523_1149#"
+merge "li_523_1149#" "a_589_1133#"
+merge "a_589_1133#" "XMDUM11/a_18_n276#"
+merge "XMDUM11/a_18_n276#" "XM23/w_n209_n320#"
+merge "XM23/w_n209_n320#" "XM12/a_n73_n240#"
+merge "XM12/a_n73_n240#" "XM12/w_n109_n340#"
+merge "XM12/w_n109_n340#" "XMDUM11B/w_n112_n338#"
+merge "XMDUM11B/w_n112_n338#" "XM21/a_n72_n22#"
+merge "XM21/a_n72_n22#" "XM21/w_n109_n58#"
+merge "XM21/w_n109_n58#" "XM5GUT/a_15_n236#"
+merge "XM5GUT/a_15_n236#" "XM5GUT/w_n109_n298#"
+merge "XM5GUT/w_n109_n298#" "XM11_1/w_n112_n338#"
+merge "XM11_1/w_n112_n338#" "XM11/w_n112_n338#"
+merge "XM11/w_n112_n338#" "XM11B/w_n112_n338#"
+merge "XM11B/w_n112_n338#" "XM11B_1/w_n112_n338#"
+merge "XM11B_1/w_n112_n338#" "M1GUT/w_n109_n244#"
+merge "M1GUT/w_n109_n244#" "XMDUM11/w_n112_n338#"
+merge "XMDUM11/w_n112_n338#" "MX3GUT/a_n73_n64#"
+merge "MX3GUT/a_n73_n64#" "MX3GUT/w_n109_n164#"
+merge "MX3GUT/w_n109_n164#" "vdd"
+merge "XM22/a_n33_33#" "XM21/a_n15_n53#" -386.939 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 630 -120 0 0 21108 -888 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM21/a_n15_n53#" "a_879_204#"
+merge "a_879_204#" "XM5GUT/a_n73_n236#"
+merge "XM5GUT/a_n73_n236#" "XM6/a_15_n175#"
+merge "XM6/a_15_n175#" "li_611_133#"
+merge "li_611_133#" "M1GUT/a_n33_n241#"
+merge "M1GUT/a_n33_n241#" "XM2/a_n33_63#"
+merge "XM2/a_n33_63#" "li_n690_207#"
+merge "XM23/a_114_n220#" "XM23/a_n78_n220#" -329.556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -207218 -424 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_n78_n220#" "XM24/a_18_n129#"
+merge "XM24/a_18_n129#" "out"
+merge "M1GUT/a_15_n144#" "XM2/a_15_n103#" -203.836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11148 -1156 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_15_n103#" "MX3GUT/a_n33_n161#"
+merge "MX3GUT/a_n33_n161#" "XM4GUT/a_n33_33#"
+merge "XM4GUT/a_n33_33#" "li_n545_286#"
+merge "XM26/a_n33_n157#" "XMDUM16/a_n33_n297#" -543.185 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18860 -404 0 0 0 0 0 0 0 0 0 0
+merge "XMDUM16/a_n33_n297#" "vctrl"
+merge "XMDUM11/a_n76_n276#" "M1GUT/a_n73_n144#" -290.384 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -48772 -290 -215623 -126 0 0 0 0 0 0 0 0 0 0
+merge "M1GUT/a_n73_n144#" "li_n517_410#"
+merge "XM25/a_n76_n136#" "XM26/a_n76_n69#" -47.8537 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 -200 4922 -646 0 0 0 0 0 0 0 0 0 0
+merge "XM26/a_n76_n69#" "m1_n707_n334#"
+merge "m1_n707_n334#" "XM25/a_n33_95#"
+merge "XM25/a_n33_95#" "XMDUM11/a_n33_235#"
+merge "XMDUM11/a_n33_235#" "m1_n480_1050#"
+merge "m1_n480_1050#" "li_16_1150#"
+merge "XM22/a_15_n68#" "XM12/a_n33_n337#" -196.083 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 132 -166 0 0 -1806 -456 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM12/a_n33_n337#" "XM21/a_15_n22#"
+merge "XM21/a_15_n22#" "XM13/a_n33_142#"
+merge "XM13/a_n33_142#" "li_917_51#"
+merge "XM2/a_n73_n103#" "XMDUM16/a_n76_n209#" -624.36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -21060 -226 -195488 -92 0 0 0 0 0 0 0 0 0 0
+merge "XMDUM16/a_n76_n209#" "li_n460_7#"
+merge "XM23/a_n33_251#" "XM23/a_63_n317#" -501.666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -125060 -1066 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM23/a_63_n317#" "li_1179_712#"
+merge "li_1179_712#" "XM23/a_n129_n317#"
+merge "XM23/a_n129_n317#" "XM12/a_15_n240#"
+merge "XM12/a_15_n240#" "XM24/a_n33_n217#"
+merge "XM24/a_n33_n217#" "li_1179_338#"
+merge "li_1179_338#" "XM13/a_15_n120#"
+merge "XM13/a_15_n120#" "li_1179_n70#"
+merge "li_1179_n70#" "li_1213_134#"
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.mag b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.mag
new file mode 100755
index 0000000..21da0bb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.mag
@@ -0,0 +1,446 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645902895
+<< error_s >>
+rect 871 109 901 121
+rect 871 25 901 37
+<< nwell >>
+rect -820 242 1795 1347
+<< pwell >>
+rect -820 -835 1795 242
+<< psubdiff >>
+rect -779 -28 -745 216
+rect 894 -62 1023 -28
+rect -779 -136 -745 -62
+rect 989 -411 1023 -62
+rect -779 -747 -745 -647
+rect 989 -747 1023 -663
+rect -779 -781 -742 -747
+rect 894 -781 1023 -747
+<< nsubdiff >>
+rect -781 1252 -708 1286
+rect 930 1252 1023 1286
+rect -781 1226 -747 1252
+rect -781 565 -747 572
+rect 989 565 1023 1252
+rect -781 531 -708 565
+rect 930 531 1023 565
+rect -781 278 -747 531
+<< psubdiffcont >>
+rect -779 -62 894 -28
+rect -779 -647 -745 -136
+rect 989 -663 1023 -411
+rect -742 -781 894 -747
+<< nsubdiffcont >>
+rect -708 1252 930 1286
+rect -781 572 -747 1226
+rect -708 531 930 565
+<< poly >>
+rect 289 1133 317 1199
+rect 589 1133 617 1199
+rect 879 204 909 247
+rect 289 -694 317 -628
+rect 590 -694 618 -628
+<< locali >>
+rect -781 1252 -708 1286
+rect 930 1252 1023 1286
+rect -781 1226 -747 1252
+rect 16 1150 82 1184
+rect 223 1149 383 1183
+rect 523 1149 683 1183
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+rect -610 106 -550 131
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+rect 272 68 306 132
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+rect 1339 197 1373 296
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+rect 951 85 1053 111
+rect 917 77 1053 85
+rect 917 51 951 77
+rect 894 -62 1023 -28
+rect -779 -136 -745 -62
+rect 989 -411 1023 -62
+rect 1179 -70 1255 -36
+rect 1221 -171 1255 -70
+rect 1221 -205 1375 -171
+rect -779 -747 -745 -647
+rect 223 -678 383 -644
+rect 528 -678 680 -644
+rect 989 -747 1023 -663
+rect 894 -781 1023 -747
+<< viali >>
+rect -708 1252 930 1286
+rect -517 410 -378 444
+rect -113 412 -79 446
+rect 364 416 741 450
+rect 1091 406 1125 810
+rect -610 207 -576 241
+rect 349 207 383 241
+rect -460 7 -352 41
+rect -131 10 -97 44
+rect 365 15 629 49
+rect 821 8 855 42
+rect 989 -663 1023 -411
+rect -779 -781 -742 -747
+rect -742 -781 894 -747
+<< metal1 >>
+rect 1172 1443 1372 1742
+rect -760 1442 1372 1443
+rect -760 1286 1713 1442
+rect -760 1252 -708 1286
+rect 930 1252 1713 1286
+rect -760 1237 1713 1252
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+rect -592 1047 -546 1236
+rect -480 1193 -374 1205
+rect -480 1141 -436 1193
+rect -384 1141 -374 1193
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+rect -480 1050 -434 1131
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+rect -346 953 -306 1236
+rect -274 1039 -228 1236
+rect -180 1039 -134 1236
+rect 16 1193 82 1200
+rect 16 1141 23 1193
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+rect 277 1189 329 1237
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+rect 119 952 192 966
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+rect -707 729 -434 775
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+rect -22 618 26 777
+rect 119 760 280 952
+rect 150 759 280 760
+rect 326 759 374 965
+rect 414 759 492 1237
+rect 578 1189 630 1237
+rect 527 1143 679 1189
+rect 578 1135 630 1143
+rect 715 759 755 1237
+rect -354 572 26 618
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+rect 580 618 626 759
+rect 489 572 626 618
+rect -354 465 -308 572
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+rect 348 450 755 465
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+rect 1085 1084 1713 1237
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+rect -168 0 -58 10
+rect 330 49 751 55
+rect 330 15 365 49
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+rect 330 9 751 15
+rect -370 -79 -324 -25
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+rect 807 42 868 52
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+rect 1703 30 1743 194
+rect 1849 118 2049 194
+rect 807 0 868 8
+rect -89 -50 751 -19
+rect -370 -125 26 -79
+rect -20 -238 26 -125
+rect 488 -125 627 -79
+rect 158 -261 227 -170
+rect -707 -334 -431 -288
+rect -477 -423 -431 -334
+rect -1076 -635 -876 -552
+rect -1076 -687 -1012 -635
+rect -960 -687 -876 -635
+rect -1076 -752 -876 -687
+rect -680 -724 -640 -457
+rect -586 -724 -546 -457
+rect -380 -553 -299 -457
+rect -444 -635 -364 -623
+rect -444 -687 -433 -635
+rect -381 -687 -364 -635
+rect -444 -691 -364 -687
+rect -433 -693 -381 -691
+rect -336 -724 -299 -553
+rect -266 -724 -226 -448
+rect -172 -724 -132 -454
+rect 120 -471 227 -261
+rect 230 -469 403 -263
+rect 158 -610 227 -471
+rect 24 -635 76 -629
+rect 24 -693 76 -687
+rect 158 -724 198 -610
+rect 278 -638 330 -629
+rect 227 -684 379 -638
+rect 278 -724 330 -684
+rect 418 -724 487 -263
+rect 488 -269 533 -125
+rect 581 -152 627 -125
+rect 681 -602 751 -50
+rect 822 -55 862 0
+rect 1426 -10 1743 30
+rect 578 -638 630 -629
+rect 528 -684 680 -638
+rect 578 -724 630 -684
+rect 711 -724 751 -602
+rect 786 -94 930 -55
+rect 786 -632 826 -94
+rect 890 -632 930 -94
+rect 1086 -342 1128 -47
+rect 1288 -342 1328 -63
+rect 1086 -344 1652 -342
+rect 786 -678 930 -632
+rect 786 -724 826 -678
+rect 890 -724 930 -678
+rect 973 -411 1652 -344
+rect 973 -663 989 -411
+rect 1023 -663 1652 -411
+rect 973 -724 1652 -663
+rect -819 -747 1755 -724
+rect -819 -781 -779 -747
+rect 894 -781 1755 -747
+rect -819 -872 1755 -781
+rect 1202 -1174 1402 -872
+<< via1 >>
+rect -436 1141 -384 1193
+rect 23 1141 75 1193
+rect -1012 -687 -960 -635
+rect -433 -687 -381 -635
+rect 24 -687 76 -635
+<< metal2 >>
+rect -442 1141 -436 1193
+rect -384 1187 -378 1193
+rect 17 1187 23 1193
+rect -384 1147 23 1187
+rect -384 1141 -378 1147
+rect 17 1141 23 1147
+rect 75 1141 81 1193
+rect -1018 -687 -1012 -635
+rect -960 -641 -954 -635
+rect -439 -641 -433 -635
+rect -960 -681 -433 -641
+rect -960 -687 -954 -681
+rect -439 -687 -433 -681
+rect -381 -641 -375 -635
+rect 18 -641 24 -635
+rect -381 -681 24 -641
+rect -381 -687 -375 -681
+rect 18 -687 24 -681
+rect 76 -687 82 -635
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26B
+timestamp 1645190808
+transform 1 0 -200 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -407 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -613 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_MP0P50 XM4GUT
+timestamp 1645814297
+transform 0 -1 -167 1 0 101
+box -73 -127 73 99
+use sky130_fd_pr__pfet_01v8_MP0P75 MX3GUT
+timestamp 1645814297
+transform 0 1 -99 -1 0 351
+box -109 -164 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -437 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_MP1P4U M1GUT
+timestamp 1645814297
+transform 0 1 -465 -1 0 351
+box -109 -244 109 198
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645796186
+transform 1 0 894 0 1 300
+box -109 -58 109 200
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_MP3P0U XM5GUT
+timestamp 1645814297
+transform 0 -1 517 1 0 351
+box -109 -298 109 464
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -410 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -616 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25B
+timestamp 1645268775
+transform 1 0 -204 0 1 1040
+box -112 -198 112 164
+<< labels >>
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+rlabel metal1 -1076 -752 -876 -552 1 vctrl
+port 3 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.spice b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.spice
new file mode 100755
index 0000000..fabe0bb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/3-stage_cs-vco_dpgutfeel_v3.spice
@@ -0,0 +1,313 @@
+* NGSPICE file created from 3-stage_cs-vco_dpgutfeel_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 w_n209_n320# a_n78_n220# 0.33fF
+C1 a_n78_n220# a_n129_n317# 0.00fF
+C2 w_n209_n320# a_18_n220# 0.28fF
+C3 a_63_n317# w_n209_n320# 0.14fF
+C4 a_63_n317# a_n129_n317# 0.03fF
+C5 a_n173_n220# a_114_n220# 0.07fF
+C6 a_114_n220# a_n78_n220# 0.18fF
+C7 w_n209_n320# a_n33_251# 0.14fF
+C8 a_18_n220# a_114_n220# 0.31fF
+C9 a_n33_251# a_n129_n317# 0.02fF
+C10 a_63_n317# a_114_n220# 0.00fF
+C11 a_n173_n220# a_n78_n220# 0.31fF
+C12 a_18_n220# a_n173_n220# 0.14fF
+C13 w_n209_n320# a_n129_n317# 0.14fF
+C14 a_18_n220# a_n78_n220# 0.31fF
+C15 a_63_n317# a_18_n220# 0.00fF
+C16 w_n209_n320# a_114_n220# 0.33fF
+C17 a_n33_251# a_n78_n220# 0.00fF
+C18 a_18_n220# a_n33_251# 0.00fF
+C19 a_63_n317# a_n33_251# 0.02fF
+C20 w_n209_n320# a_n173_n220# 0.28fF
+C21 a_n173_n220# a_n129_n317# 0.00fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_15_n240# w_n109_n340# 0.17fF
+C1 a_n33_n337# w_n109_n340# 0.11fF
+C2 a_n73_n240# a_15_n240# 0.20fF
+C3 a_n73_n240# w_n109_n340# 0.19fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_18_n136# w_n112_n198# 0.16fF
+C1 a_n33_95# w_n112_n198# 0.19fF
+C2 a_n76_n136# a_18_n136# 0.20fF
+C3 a_n33_95# a_n76_n136# 0.00fF
+C4 a_n33_95# a_18_n136# 0.00fF
+C5 a_n76_n136# w_n112_n198# 0.16fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_n33_n217# 0.01fF
+C1 a_n76_n129# a_18_n129# 0.21fF
+C2 a_18_n129# a_n33_n217# 0.01fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_n33_142# 0.01fF
+C1 a_n73_n120# a_15_n120# 0.15fF
+C2 a_15_n120# a_n33_142# 0.00fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_n33_n157# 0.00fF
+C1 a_n76_n69# a_18_n69# 0.17fF
+C2 a_18_n69# a_n33_n157# 0.01fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_n33_n297# 0.00fF
+C1 a_n76_n209# a_18_n209# 0.35fF
+C2 a_18_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n276# w_n112_n338# 0.32fF
+C1 a_n33_235# w_n112_n338# 0.19fF
+C2 a_n76_n276# a_18_n276# 0.46fF
+C3 a_n33_235# a_n76_n276# 0.00fF
+C4 a_n33_235# a_18_n276# 0.00fF
+C5 a_n76_n276# w_n112_n338# 0.32fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_n73_n96# a_n33_33# 0.00fF
+C1 a_n73_n96# a_15_n96# 0.06fF
+C2 a_15_n96# a_n33_33# 0.00fF
+C3 a_15_n96# VSUBS 0.02fF
+C4 a_n73_n96# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_n33_n297# 0.00fF
+C1 a_n76_n209# a_18_n209# 0.47fF
+C2 a_18_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
++ VSUBS
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+C0 a_15_n144# w_n109_n244# 0.13fF
+C1 a_n33_n241# w_n109_n244# 0.14fF
+C2 a_n73_n144# a_15_n144# 0.15fF
+C3 a_n33_n241# a_n73_n144# 0.00fF
+C4 a_n33_n241# a_15_n144# 0.00fF
+C5 a_n73_n144# w_n109_n244# 0.13fF
+C6 a_15_n144# VSUBS -0.11fF
+C7 a_n73_n144# VSUBS -0.11fF
+C8 a_n33_n241# VSUBS -0.01fF
+C9 w_n109_n244# VSUBS 0.29fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_n73_n103# a_n33_63# 0.00fF
+C1 a_n73_n103# a_15_n103# 0.07fF
+C2 a_15_n103# a_n33_63# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_n73_n175# a_n33_135# 0.00fF
+C1 a_n73_n175# a_15_n175# 0.16fF
+C2 a_15_n175# a_n33_135# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+C0 a_15_n236# w_n109_n298# 0.26fF
+C1 a_n33_395# w_n109_n298# 0.14fF
+C2 a_n73_n236# a_15_n236# 0.32fF
+C3 a_n33_395# a_n73_n236# 0.00fF
+C4 a_n33_395# a_15_n236# 0.00fF
+C5 a_n73_n236# w_n109_n298# 0.26fF
+C6 a_15_n236# VSUBS -0.25fF
+C7 a_n73_n236# VSUBS -0.25fF
+C8 a_n33_395# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.50fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+C0 a_15_n64# w_n109_n164# 0.06fF
+C1 a_n33_n161# w_n109_n164# 0.14fF
+C2 a_n73_n64# a_15_n64# 0.07fF
+C3 a_n33_n161# a_n73_n64# 0.00fF
+C4 a_n33_n161# a_15_n64# 0.00fF
+C5 a_n73_n64# w_n109_n164# 0.06fF
+C6 a_15_n64# VSUBS -0.06fF
+C7 a_n73_n64# VSUBS -0.06fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 a_15_n22# w_n109_n58# 0.08fF
+C1 a_n15_n53# w_n109_n58# 0.05fF
+C2 a_n72_n22# a_15_n22# 0.09fF
+C3 a_n72_n22# w_n109_n58# 0.14fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_n33_33# 0.00fF
+C1 a_n73_n68# a_15_n68# 0.04fF
+C2 a_15_n68# a_n33_33# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt x3-stage_cs-vco_dp7 vdd vss out vctrl
+XXM23 vdd vdd out vdd li_1213_134# li_1213_134# li_1213_134# out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 li_1213_134# vdd vdd li_917_51# vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM25 vdd li_16_1150# vdd li_16_1150# vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM24 li_1213_134# vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss li_1213_134# li_917_51# vss sky130_fd_pr__nfet_01v8_44BYND
+XXM26 li_16_1150# vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM25B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd li_16_1150# li_n517_410# vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4GUT li_n545_286# li_n118_290# vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM16_1 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B_1 vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 li_n460_7# vss vctrl vss sky130_fd_pr__nfet_01v8_TWMWTA
+XM1GUT li_n517_410# a_879_204# li_n545_286# vdd vss sky130_fd_pr__pfet_01v8_MP1P4U
+XXM2 li_n460_7# li_n545_286# a_879_204# vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM6 li_n118_290# a_879_204# vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXM11B_1 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5GUT a_879_204# vdd li_n118_290# vdd vss sky130_fd_pr__pfet_01v8_MP3P0U
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XMX3GUT vdd li_n545_286# vdd li_n118_290# vss sky130_fd_pr__pfet_01v8_MP0P75
+XXM11_1 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM21 vdd li_917_51# vdd a_879_204# vss sky130_fd_pr__pfet_01v8_AZHELG
+XXM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM22 a_879_204# vss li_917_51# vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 li_n545_286# li_n460_7# 0.02fF
+C1 li_n118_290# li_n545_286# 0.09fF
+C2 li_n517_410# li_n460_7# 0.04fF
+C3 li_n118_290# li_n517_410# 0.00fF
+C4 li_16_1150# vdd 2.25fF
+C5 a_879_204# li_n545_286# 0.18fF
+C6 li_n545_286# vss 0.14fF
+C7 li_16_1150# vctrl 0.00fF
+C8 a_879_204# li_n517_410# 0.13fF
+C9 li_917_51# out 0.01fF
+C10 li_1213_134# out 0.27fF
+C11 vdd li_917_51# 0.14fF
+C12 li_1213_134# vdd 0.88fF
+C13 vdd li_n118_290# 0.19fF
+C14 vctrl li_n460_7# 0.00fF
+C15 out vss 0.21fF
+C16 vdd a_879_204# 0.53fF
+C17 vdd vss 0.05fF
+C18 li_16_1150# li_n460_7# 0.04fF
+C19 li_16_1150# li_n118_290# 0.00fF
+C20 vctrl vss 0.69fF
+C21 li_1213_134# li_917_51# 0.11fF
+C22 li_n517_410# li_n545_286# 0.02fF
+C23 li_16_1150# a_879_204# 0.19fF
+C24 li_16_1150# vss 0.50fF
+C25 li_n118_290# li_917_51# 0.00fF
+C26 li_n118_290# li_n460_7# 0.00fF
+C27 a_879_204# li_917_51# 0.05fF
+C28 li_1213_134# a_879_204# 0.00fF
+C29 li_917_51# vss 0.29fF
+C30 li_1213_134# vss 0.61fF
+C31 a_879_204# li_n460_7# 0.10fF
+C32 a_879_204# li_n118_290# 0.15fF
+C33 vss li_n460_7# 0.69fF
+C34 li_n118_290# vss 0.18fF
+C35 vdd li_n545_286# 0.14fF
+C36 vdd li_n517_410# 1.11fF
+C37 a_879_204# vss 0.62fF
+C38 li_16_1150# li_n517_410# 0.06fF
+C39 vdd out 0.56fF
+C40 li_16_1150# 0 0.34fF
+C41 li_1213_134# 0 0.10fF
+C42 vdd 0 11.74fF
+C43 a_879_204# 0 1.44fF
+C44 li_n517_410# 0 -0.75fF
+C45 li_n460_7# 0 0.61fF
+C46 vctrl 0 1.45fF
+C47 li_n118_290# 0 0.52fF
+C48 li_n545_286# 0 0.26fF
+C49 vss 0 2.07fF
+C50 li_917_51# 0 0.27fF
+C51 out 0 -0.25fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3.ext b/mag/3-stage_cs-vco_dp9/old/FD_v3.ext
new file mode 100755
index 0000000..77bdcd5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3.ext
@@ -0,0 +1,351 @@
+timestamp 1647340102
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1 1 0 693 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1 1 0 693 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin 1 0 177 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin 1 0 177 0 1 -422
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1 1 0 1231 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1 1 0 1231 0 -1 -580
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2 1 0 2125 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2 1 0 2125 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2 1 0 2669 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2 1 0 2669 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb 1 0 3552 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb 1 0 3552 0 1 -227
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2 1 0 4195 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1 1 0 4035 0 1 -422
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1 1 0 4035 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2 1 0 4195 0 1 -422
+port "Clk_Out" 4 4358 -368 4392 -334 m1
+port "Clk_In" 1 68 -375 92 -329 m1
+port "VDD" 2 68 95 102 153 m1
+port "GND" 3 96 -760 130 -702 m1
+node "li_3974_n470#" 12 61.4277 3974 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2608_n667#" 354 1378.44 2608 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1170_n667#" 354 1376.53 1170 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3977_n369#" 12 60.0815 3977 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4310_n270#" 22 5.19444 4310 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 49 278.477 4358 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 7088 468 0 0 0 0 0 0 0 0 0 0
+node "5" 363 480.387 2152 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34442 2094 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 217 2591.72 636 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17204 1148 138368 6108 0 0 0 0 0 0 0 0 0 0
+node "3" 350 477.852 720 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33150 2018 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb" 164 322.461 204 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15504 980 0 0 0 0 0 0 0 0 0 0 0 0
+node "6" 713 1903.73 2696 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64496 3944 21652 1290 0 0 0 0 0 0 0 0 0 0
+node "4" 571 948.077 1258 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53582 3234 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2608_n126#" 122 -1.64 2608 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_1170_n126#" 122 -1.64 1170 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_2872_n83#" 15 0 2872 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2696_n92#" 31 0 2696 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1434_n83#" 15 0 1434 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1258_n92#" 31 0 1258 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "7" 190 869.952 3974 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8296 760 31936 1828 0 0 0 0 0 0 0 0 0 0
+node "a_2508_n669#" 678 4356.3 2508 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14984 892 0 0 5644 536 158792 6996 0 0 0 0 0 0 0 0 0 0
+node "a_4108_n585#" 1440 0 4108 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4108_n263#" 4053 0 4108 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 1485 3581.58 68 -375 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31376 1860 0 0 10132 936 262108 11488 0 0 0 0 0 0 0 0 0 0
+node "a_1061_1#" 722 -180.421 1061 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 968 0 0 5644 536 72634 3250 0 0 0 0 0 0 0 0 0 0
+node "VDD" 31887 6302.42 68 95 m1 0 0 0 0 2123084 9630 0 0 143106 8486 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 194412 11504 250792 8764 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 96 -760 m1 1971744 9560 0 0 0 0 0 0 0 0 147016 8716 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 230588 13632 250792 8764 0 0 0 0 0 0 0 0 0 0
+cap "Clk_In" "a_1061_1#" 286.772
+cap "4" "li_1434_n83#" 22
+cap "a_1061_1#" "4" 3.33929
+cap "VDD" "6" 275.264
+cap "2" "VDD" 92.652
+cap "Clk_In" "6" 3.33929
+cap "Clk_In" "2" 2205.51
+cap "Clk_Out" "li_3977_n369#" 5.31754
+cap "6" "7" 146.867
+cap "2" "7" 12.3056
+cap "li_1170_n126#" "3" 14.7632
+cap "2" "4" 415.856
+cap "5" "li_2608_n126#" 14.7632
+cap "a_2508_n669#" "Clkb" 72.3786
+cap "li_2696_n92#" "6" 23.2941
+cap "5" "a_2508_n669#" 28.3979
+cap "Clk_In" "li_1170_n667#" 602.691
+cap "VDD" "li_1258_n92#" 43.293
+cap "a_1061_1#" "li_1170_n126#" 182.29
+cap "VDD" "li_2608_n126#" 410.223
+cap "Clk_In" "li_2608_n126#" 235.31
+cap "li_3977_n369#" "6" 74.8
+cap "li_1170_n667#" "4" 88.9945
+cap "2" "li_3977_n369#" 5.96809
+cap "Clk_In" "a_2508_n669#" 1434.45
+cap "li_3974_n470#" "6" 29.5263
+cap "li_2608_n667#" "5" 6.03226
+cap "4" "li_1258_n92#" 23.2941
+cap "2" "li_1170_n126#" 90.9805
+cap "li_2696_n92#" "li_2608_n126#" 1.88
+cap "a_1061_1#" "3" 3.69079
+cap "li_4310_n270#" "VDD" 45.9225
+cap "li_4310_n270#" "7" 3.71523
+cap "Clk_Out" "6" 8.23846
+cap "2" "3" 331.614
+cap "VDD" "li_2872_n83#" 39.5697
+cap "li_1170_n126#" "li_1258_n92#" 1.88
+cap "a_2508_n669#" "li_1170_n126#" 62.7219
+cap "VDD" "Clkb" 70.9841
+cap "2" "a_1061_1#" 151.544
+cap "5" "VDD" 254.495
+cap "li_2696_n92#" "li_2872_n83#" 9.52817
+cap "Clk_In" "Clkb" 98.1656
+cap "li_1170_n667#" "3" 6.03226
+cap "Clk_In" "5" 84.9256
+cap "2" "6" 578.272
+cap "5" "4" 18.9494
+cap "a_2508_n669#" "3" 20.449
+cap "li_1258_n92#" "li_1434_n83#" 9.52817
+cap "Clk_In" "VDD" 3111.69
+cap "VDD" "7" 269.598
+cap "VDD" "4" 275.264
+cap "li_2696_n92#" "VDD" 43.293
+cap "Clk_In" "4" 130.852
+cap "Clk_Out" "li_4310_n270#" 1.83333
+cap "li_2608_n126#" "6" 12.6168
+cap "2" "li_2608_n126#" 90.9805
+cap "a_2508_n669#" "6" 35.6561
+cap "2" "a_2508_n669#" 2147.27
+cap "VDD" "li_1170_n126#" 410.223
+cap "li_3977_n369#" "7" 61.6231
+cap "Clkb" "3" 16.3922
+cap "Clk_In" "li_1170_n126#" 170.315
+cap "li_3974_n470#" "7" 181.929
+cap "li_2608_n667#" "6" 88.9945
+cap "li_1170_n126#" "4" 12.6168
+cap "li_2872_n83#" "6" 22
+cap "a_1061_1#" "Clkb" 3.9507
+cap "VDD" "3" 238.741
+cap "Clk_Out" "VDD" 30.2767
+cap "Clk_In" "3" 129.801
+cap "li_3974_n470#" "li_3977_n369#" 15.2687
+cap "Clk_Out" "7" 92.3198
+cap "VDD" "li_1434_n83#" 39.5697
+cap "4" "3" 170.035
+cap "5" "6" 171.334
+cap "2" "Clkb" 5.13697
+cap "2" "5" 307.459
+cap "li_2608_n667#" "a_2508_n669#" 602.691
+cap "VDD" "a_1061_1#" 3285.37
+cap "MPClkin/a_n15_n133#" "MPTgate1/a_15_n36#" 21.671
+cap "MPinv1/a_n15_n133#" "MPinv1/a_15_n36#" 187.723
+cap "MNinv1/a_n73_n163#" "MPinv1/a_n15_n133#" 639.615
+cap "MPClkin/a_191_n36#" "MPinv1/a_15_n36#" 537.537
+cap "MPinv1/w_n109_n86#" "MPTgate1/a_15_n36#" -153.863
+cap "MPClkin/a_n15_n133#" "MPinv1/a_n15_n133#" 182.054
+cap "MNinv1/a_n73_n163#" "MPClkin/a_191_n36#" -69.8304
+cap "MPinv1/w_n109_n86#" "MPinv1/a_n15_n133#" 13.7802
+cap "MPClkin/a_191_n36#" "MPClkin/a_n15_n133#" 408.539
+cap "MPinv1/w_n109_n86#" "MPClkin/a_191_n36#" 67.3787
+cap "MNinv1/a_n73_n163#" "MPinv1/a_15_n36#" 275.611
+cap "MPClkin/a_191_n36#" "MPTgate1/a_15_n36#" 221.528
+cap "MPClkin/a_n15_n133#" "MPinv1/a_15_n36#" 99.8385
+cap "MNinv1/a_n73_n163#" "MPClkin/a_n15_n133#" 1098.8
+cap "MPinv1/w_n109_n86#" "MPinv1/a_15_n36#" 150.947
+cap "MPClkin/a_191_n36#" "MPinv1/a_n15_n133#" 129.401
+cap "MNinv1/a_n73_n163#" "MPinv1/w_n109_n86#" 33
+cap "MPinv1/a_15_n36#" "MPTgate1/a_15_n36#" 199.197
+cap "MPinv1/w_n109_n86#" "MPClkin/a_n15_n133#" 250.063
+cap "MNinv1/a_n73_n163#" "MPTgate1/a_15_n36#" 177.014
+cap "MNinv2/a_191_n163#" "2" 4.26326e-14
+cap "MPTgate2/a_n15_n81#" "MNinv2/a_191_n163#" 198.251
+cap "MPTgate1/a_n73_n36#" "MPTgate1/a_15_n36#" 152.269
+cap "MNinv2/a_n73_n163#" "MNinv2/a_191_n163#" 259.424
+cap "MPTgate1/a_15_n36#" "MNTgate2/a_n15_n199#" -207.659
+cap "MPTgate2/a_n15_n81#" "MPTgate1/a_n73_n36#" 36.5951
+cap "MPTgate1/w_n109_n86#" "MNinv2/a_191_n163#" 39.2964
+cap "MPTgate1/a_n15_n81#" "MPTgate1/a_15_n36#" -129.298
+cap "MNinv2/a_n73_n163#" "MPTgate1/a_n73_n36#" 255.018
+cap "MPTgate1/a_n73_n36#" "MNTgate1/a_n15_n199#" 52.994
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_n15_n199#" 19.9038
+cap "MNinv2/a_n73_n163#" "MNTgate2/a_n15_n199#" 173.49
+cap "MPTgate1/w_n109_n86#" "MPTgate1/a_n73_n36#" -19.4985
+cap "MPTgate1/a_n15_n81#" "MPTgate2/a_n15_n81#" 30.8075
+cap "MNTgate1/a_n15_n199#" "MNTgate2/a_n15_n199#" 78.2625
+cap "MPTgate1/a_n73_n36#" "MNinv2/a_191_n163#" 26.5082
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_15_n163#" 54.4807
+cap "MNinv2/a_n73_n163#" "MNTgate2/a_15_n163#" 88.5072
+cap "MPTgate1/a_n15_n81#" "MNTgate1/a_n15_n199#" 13.8111
+cap "MPTgate1/w_n109_n86#" "MPTgate1/a_n15_n81#" -60.6255
+cap "MNinv2/a_191_n163#" "MNTgate2/a_n15_n199#" 136.278
+cap "MPTgate1/a_15_n36#" "2" 188.843
+cap "MPTgate1/w_n109_n86#" "MNTgate2/a_15_n163#" -60.3153
+cap "MPTgate2/a_n15_n81#" "MPTgate1/a_15_n36#" -172.652
+cap "MNinv2/a_n73_n163#" "MPTgate1/a_15_n36#" 960.389
+cap "MPTgate1/a_n73_n36#" "MNTgate2/a_n15_n199#" 195.345
+cap "MNinv2/a_191_n163#" "MNTgate2/a_15_n163#" 122.568
+cap "MPTgate1/a_15_n36#" "MNTgate1/a_n15_n199#" 24.0588
+cap "MNinv2/a_n73_n163#" "2" -74.5699
+cap "MPTgate1/a_n15_n81#" "MPTgate1/a_n73_n36#" 81.583
+cap "MPTgate1/w_n109_n86#" "MPTgate1/a_15_n36#" -38.5111
+cap "MPTgate1/a_15_n36#" "MNinv2/a_191_n163#" 218.748
+cap "MNinv2/a_n73_n163#" "MNTgate1/a_n15_n199#" 457.968
+cap "MNinv2/a_n73_n163#" "MPTgate1/w_n109_n86#" 16.5
+cap "MPTgate1/w_n109_n86#" "MPTgate2/a_n15_n81#" 54.9576
+cap "MNfb/a_n73_n163#" "MNfb/a_15_n163#" 121.552
+cap "MNTgate2/a_279_n163#" "MNTgate2/a_15_n163#" 290.798
+cap "MPTgate2/w_n109_n86#" "MPTgate2/a_n15_n81#" -63.0874
+cap "MNfb/a_n73_n163#" "MNTgate2/a_15_n163#" 1385.66
+cap "MNbuf1/a_n73_n163#" "MPbuf2/a_15_n36#" 174.145
+cap "MNTgate2/a_15_n163#" "MNTgate2/a_n15_n199#" 25.6357
+cap "MPTgate2/w_n109_n86#" "MPbuf2/a_15_n36#" 103.281
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_279_n163#" 81.583
+cap "MNTgate2/a_15_n163#" "MNfb/a_15_n163#" 495.19
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_n15_n199#" 13.8111
+cap "MNfb/a_n73_n163#" "MPbuf2/a_15_n36#" 96.292
+cap "MPTgate2/w_n109_n86#" "MNbuf1/a_n73_n163#" 177.406
+cap "MPTgate2/w_n109_n86#" "MNTgate2/a_279_n163#" -20.3383
+cap "MNfb/a_n73_n163#" "MNbuf1/a_n73_n163#" -24.6505
+cap "MNfb/a_n73_n163#" "MPTgate2/w_n109_n86#" 33
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_15_n163#" 36.8866
+cap "MNfb/a_n73_n163#" "MNTgate2/a_279_n163#" 258.905
+cap "MNTgate2/a_15_n163#" "MPbuf2/a_15_n36#" 8.49674
+cap "MNbuf1/a_n73_n163#" "MNfb/a_15_n163#" 129.784
+cap "MPTgate2/w_n109_n86#" "MNfb/a_15_n163#" 46.1036
+cap "MNTgate2/a_279_n163#" "MNTgate2/a_n15_n199#" 52.994
+cap "MNfb/a_n73_n163#" "MNTgate2/a_n15_n199#" 515.281
+cap "MNTgate2/a_279_n163#" "MNfb/a_15_n163#" 27.7597
+cap "MNTgate2/a_15_n163#" "MNbuf1/a_n73_n163#" 132.888
+cap "MPTgate2/w_n109_n86#" "MNTgate2/a_15_n163#" -133.092
+cap "MPbuf2/a_15_n36#" "MNbuf1/a_n73_n163#" 5.7275
+cap "MNbuf1/a_15_n163#" "MNbuf1/a_n73_37#" 3.66176
+cap "MPbuf2/w_n109_n86#" "MNbuf1/a_n73_n163#" 14.3146
+cap "MPbuf2/a_15_n36#" "MPbuf2/w_n109_n86#" 4.77396e-15
+cap "MNbuf1/a_n73_37#" "MNbuf1/a_n73_n163#" 9.60092
+cap "MNbuf1/a_15_n163#" "MNbuf1/a_n73_n163#" -10.7352
+cap "MNbuf1/a_15_n163#" "MPbuf2/a_15_n36#" -12.963
+cap "MNbuf1/a_15_n163#" "MPbuf2/w_n109_n86#" 3.24165
+merge "MPbuf1/a_15_n36#" "MPbuf1/w_n109_n86#" -3293.31 0 0 0 0 -1102000 -13584 0 0 0 0 88128 -1152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4128 -1652 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf1/w_n109_n86#" "MPbuf2/a_103_n36#"
+merge "MPbuf2/a_103_n36#" "li_4310_n270#"
+merge "li_4310_n270#" "MPbuf2/a_n73_n36#"
+merge "MPbuf2/a_n73_n36#" "a_4108_n263#"
+merge "a_4108_n263#" "MPbuf2/w_n109_n86#"
+merge "MPbuf2/w_n109_n86#" "MPfb/a_279_n36#"
+merge "MPfb/a_279_n36#" "MPfb/a_103_n36#"
+merge "MPfb/a_103_n36#" "MPfb/a_n73_n36#"
+merge "MPfb/a_n73_n36#" "MPfb/w_n109_n86#"
+merge "MPfb/w_n109_n86#" "MPTgate2/w_n109_n86#"
+merge "MPTgate2/w_n109_n86#" "MPinv2/a_279_n36#"
+merge "MPinv2/a_279_n36#" "MPinv2/a_103_n36#"
+merge "MPinv2/a_103_n36#" "MPinv2/a_n73_n36#"
+merge "MPinv2/a_n73_n36#" "MPinv2/w_n109_n86#"
+merge "MPinv2/w_n109_n86#" "MPTgate1/w_n109_n86#"
+merge "MPTgate1/w_n109_n86#" "MPClkin/a_279_n36#"
+merge "MPClkin/a_279_n36#" "MPClkin/a_103_n36#"
+merge "MPClkin/a_103_n36#" "MPClkin/a_n73_n36#"
+merge "MPClkin/a_n73_n36#" "MPClkin/w_n109_n86#"
+merge "MPClkin/w_n109_n86#" "MPinv1/a_n73_n36#"
+merge "MPinv1/a_n73_n36#" "MPinv1/a_279_n36#"
+merge "MPinv1/a_279_n36#" "MPinv1/a_103_n36#"
+merge "MPinv1/a_103_n36#" "MPinv1/w_n109_n86#"
+merge "MPinv1/w_n109_n86#" "VDD"
+merge "MPinv2/a_n15_n133#" "MNinv2/a_n73_37#" -975.564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7170 -538 0 0 36670 -1862 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNinv2/a_n73_37#" "MNTgate1/a_543_n163#"
+merge "MNTgate1/a_543_n163#" "MNTgate1/a_367_n163#"
+merge "MNTgate1/a_367_n163#" "MNTgate1/a_191_n163#"
+merge "MNTgate1/a_191_n163#" "MNTgate1/a_15_n163#"
+merge "MNTgate1/a_15_n163#" "MPTgate1/a_367_n36#"
+merge "MPTgate1/a_367_n36#" "MPTgate1/a_191_n36#"
+merge "MPTgate1/a_191_n36#" "li_1434_n83#"
+merge "li_1434_n83#" "MPTgate1/a_15_n36#"
+merge "MPTgate1/a_15_n36#" "4"
+merge "4" "li_1258_n92#"
+merge "MPfb/a_191_n36#" "MPfb/a_15_n36#" -1321.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7170 -538 0 0 -3128 -524 -64400 -2800 0 0 0 0 0 0 0 0 0 0
+merge "MPfb/a_15_n36#" "MNfb/a_191_n163#"
+merge "MNfb/a_191_n163#" "MNfb/a_15_n163#"
+merge "MNfb/a_15_n163#" "MNinv1/a_n73_37#"
+merge "MNinv1/a_n73_37#" "2"
+merge "2" "MPinv1/a_n15_n133#"
+merge "MNTgate2/a_631_n163#" "MPTgate2/a_279_n36#" -1026.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23020 -1722 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate2/a_279_n36#" "MPTgate2/a_103_n36#"
+merge "MPTgate2/a_103_n36#" "MPTgate2/a_n73_n36#"
+merge "MPTgate2/a_n73_n36#" "li_2608_n126#"
+merge "li_2608_n126#" "MNTgate2/a_103_n163#"
+merge "MNTgate2/a_103_n163#" "MNTgate2/a_n73_n163#"
+merge "MNTgate2/a_n73_n163#" "MNTgate2/a_455_n163#"
+merge "MNTgate2/a_455_n163#" "MNTgate2/a_279_n163#"
+merge "MNTgate2/a_279_n163#" "li_2608_n667#"
+merge "li_2608_n667#" "MPinv2/a_191_n36#"
+merge "MPinv2/a_191_n36#" "MPinv2/a_15_n36#"
+merge "MPinv2/a_15_n36#" "MNinv2/a_15_n163#"
+merge "MNinv2/a_15_n163#" "MNinv2/a_191_n163#"
+merge "MNinv2/a_191_n163#" "5"
+merge "MNbuf2/VSUBS" "MNbuf2/a_103_n163#" -1014.17 0 0 0 0 0 0 0 0 51408 -672 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5080 -3134 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf2/a_103_n163#" "MNbuf2/a_n73_n163#"
+merge "MNbuf2/a_n73_n163#" "MPbuf1/VSUBS"
+merge "MPbuf1/VSUBS" "MNbuf1/VSUBS"
+merge "MNbuf1/VSUBS" "MNbuf1/a_15_n163#"
+merge "MNbuf1/a_15_n163#" "a_4108_n585#"
+merge "a_4108_n585#" "MPbuf2/VSUBS"
+merge "MPbuf2/VSUBS" "MPfb/VSUBS"
+merge "MPfb/VSUBS" "MNfb/VSUBS"
+merge "MNfb/VSUBS" "MNfb/a_103_n163#"
+merge "MNfb/a_103_n163#" "MNfb/a_n73_n163#"
+merge "MNfb/a_n73_n163#" "MPTgate2/VSUBS"
+merge "MPTgate2/VSUBS" "MNTgate2/VSUBS"
+merge "MNTgate2/VSUBS" "MPinv2/VSUBS"
+merge "MPinv2/VSUBS" "MNinv2/VSUBS"
+merge "MNinv2/VSUBS" "MNinv2/a_103_n163#"
+merge "MNinv2/a_103_n163#" "MNinv2/a_n73_n163#"
+merge "MNinv2/a_n73_n163#" "MNTgate1/VSUBS"
+merge "MNTgate1/VSUBS" "MPTgate1/VSUBS"
+merge "MPTgate1/VSUBS" "MNClkin/VSUBS"
+merge "MNClkin/VSUBS" "MNClkin/a_103_n163#"
+merge "MNClkin/a_103_n163#" "MNClkin/a_n73_n163#"
+merge "MNClkin/a_n73_n163#" "MPClkin/VSUBS"
+merge "MPClkin/VSUBS" "MNinv1/VSUBS"
+merge "MNinv1/VSUBS" "MNinv1/a_103_n163#"
+merge "MNinv1/a_103_n163#" "MNinv1/a_n73_n163#"
+merge "MNinv1/a_n73_n163#" "MPinv1/VSUBS"
+merge "MPinv1/VSUBS" "GND"
+merge "MNbuf2/a_n73_37#" "MPbuf2/a_n15_n133#" -505.054 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3678 -348 0 0 52732 -856 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_n15_n133#" "MPbuf1/a_n73_n36#"
+merge "MPbuf1/a_n73_n36#" "MNbuf1/a_n73_n163#"
+merge "MNbuf1/a_n73_n163#" "7"
+merge "7" "li_3974_n470#"
+merge "MNTgate1/a_631_n163#" "MNTgate1/a_103_n163#" -1024.47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25818 -1658 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_103_n163#" "MNTgate1/a_n73_n163#"
+merge "MNTgate1/a_n73_n163#" "MNTgate1/a_455_n163#"
+merge "MNTgate1/a_455_n163#" "MNTgate1/a_279_n163#"
+merge "MNTgate1/a_279_n163#" "li_1170_n667#"
+merge "li_1170_n667#" "MPTgate1/a_279_n36#"
+merge "MPTgate1/a_279_n36#" "MPTgate1/a_103_n36#"
+merge "MPTgate1/a_103_n36#" "MPTgate1/a_n73_n36#"
+merge "MPTgate1/a_n73_n36#" "li_1170_n126#"
+merge "li_1170_n126#" "MNinv1/a_15_n163#"
+merge "MNinv1/a_15_n163#" "MNinv1/a_191_n163#"
+merge "MNinv1/a_191_n163#" "MPinv1/a_191_n36#"
+merge "MPinv1/a_191_n36#" "MPinv1/a_15_n36#"
+merge "MPinv1/a_15_n36#" "3"
+merge "MPbuf1/a_n15_n133#" "MNbuf1/a_n73_37#" -1295.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 538 -680 0 0 53360 -1884 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf1/a_n73_37#" "li_3977_n369#"
+merge "li_3977_n369#" "MPfb/a_n15_n133#"
+merge "MPfb/a_n15_n133#" "MNfb/a_n73_37#"
+merge "MNfb/a_n73_37#" "MPTgate2/a_367_n36#"
+merge "MPTgate2/a_367_n36#" "MPTgate2/a_191_n36#"
+merge "MPTgate2/a_191_n36#" "li_2872_n83#"
+merge "li_2872_n83#" "MPTgate2/a_15_n36#"
+merge "MPTgate2/a_15_n36#" "li_2696_n92#"
+merge "li_2696_n92#" "MNTgate2/a_543_n163#"
+merge "MNTgate2/a_543_n163#" "MNTgate2/a_367_n163#"
+merge "MNTgate2/a_367_n163#" "MNTgate2/a_191_n163#"
+merge "MNTgate2/a_191_n163#" "MNTgate2/a_15_n163#"
+merge "MNTgate2/a_15_n163#" "6"
+merge "MPTgate2/a_n15_n81#" "MNTgate1/a_n15_n199#" -1440.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23670 -778 0 0 -1156 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n15_n199#" "MNClkin/a_n73_37#"
+merge "MNClkin/a_n73_37#" "Clk_In"
+merge "Clk_In" "MPClkin/a_n15_n133#"
+merge "MNTgate2/a_n15_n199#" "MPTgate1/a_n15_n81#" -1480.25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17880 -240 0 0 -2992 -584 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate1/a_n15_n81#" "MNClkin/a_15_n163#"
+merge "MNClkin/a_15_n163#" "a_2508_n669#"
+merge "a_2508_n669#" "MNClkin/a_191_n163#"
+merge "MNClkin/a_191_n163#" "MPClkin/a_15_n36#"
+merge "MPClkin/a_15_n36#" "a_1061_1#"
+merge "a_1061_1#" "MPClkin/a_191_n36#"
+merge "MPClkin/a_191_n36#" "Clkb"
+merge "MNbuf2/a_15_n163#" "MPbuf2/a_15_n36#" -172.671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_15_n36#" "Clk_Out"
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3.mag
new file mode 100755
index 0000000..3e25404
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3.mag
@@ -0,0 +1,410 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647340102
+<< nwell >>
+rect 68 -313 4392 178
+<< pwell >>
+rect 68 -769 4392 -313
+<< ndiff >>
+rect 4108 -585 4122 -417
+<< pdiff >>
+rect 4108 -263 4122 25
+<< psubdiff >>
+rect 68 -748 179 -714
+rect 4193 -748 4392 -714
+<< nsubdiff >>
+rect 127 107 151 141
+rect 4309 107 4336 141
+<< psubdiffcont >>
+rect 179 -748 4193 -714
+<< nsubdiffcont >>
+rect 151 107 4309 141
+<< poly >>
+rect 1061 52 1216 82
+rect 1598 52 1765 82
+rect 2499 52 2654 82
+rect 3036 52 3203 82
+rect 1061 51 1127 52
+rect 1061 17 1077 51
+rect 1111 17 1127 51
+rect 1061 1 1127 17
+rect 1687 51 1753 52
+rect 1687 17 1703 51
+rect 1737 17 1753 51
+rect 1687 1 1753 17
+rect 2499 51 2565 52
+rect 2499 17 2515 51
+rect 2549 17 2565 51
+rect 2499 1 2565 17
+rect 3125 51 3191 52
+rect 3125 17 3141 51
+rect 3175 17 3191 51
+rect 3125 1 3191 17
+rect 1070 -600 1137 -593
+rect 1943 -600 2010 -593
+rect 1070 -611 1216 -600
+rect 1070 -645 1086 -611
+rect 1120 -630 1216 -611
+rect 1862 -611 2010 -600
+rect 1862 -630 1959 -611
+rect 1120 -645 1137 -630
+rect 1070 -669 1137 -645
+rect 1943 -645 1959 -630
+rect 1993 -645 2010 -611
+rect 1943 -669 2010 -645
+rect 2508 -600 2575 -593
+rect 3381 -600 3448 -593
+rect 2508 -611 2654 -600
+rect 2508 -645 2524 -611
+rect 2558 -630 2654 -611
+rect 3300 -611 3448 -600
+rect 3300 -630 3397 -611
+rect 2558 -645 2575 -630
+rect 2508 -669 2575 -645
+rect 3381 -645 3397 -630
+rect 3431 -645 3448 -611
+rect 3381 -669 3448 -645
+<< polycont >>
+rect 1077 17 1111 51
+rect 1703 17 1737 51
+rect 2515 17 2549 51
+rect 3141 17 3175 51
+rect 1086 -645 1120 -611
+rect 1959 -645 1993 -611
+rect 2524 -645 2558 -611
+rect 3397 -645 3431 -611
+<< locali >>
+rect 68 107 151 141
+rect 4309 107 4392 141
+rect 116 13 150 107
+rect 292 13 326 107
+rect 468 13 502 107
+rect 632 29 666 107
+rect 808 13 842 107
+rect 984 13 1018 107
+rect 1077 51 1111 67
+rect 1077 1 1111 17
+rect 1703 51 1737 67
+rect 1703 1 1737 17
+rect 2064 13 2098 107
+rect 2240 13 2274 107
+rect 2416 13 2450 107
+rect 2515 51 2549 67
+rect 2515 1 2549 17
+rect 3141 51 3175 67
+rect 3141 1 3175 17
+rect 3491 13 3525 107
+rect 3667 13 3701 107
+rect 3843 13 3877 107
+rect 4062 13 4096 107
+rect 4134 13 4168 107
+rect 4310 13 4344 107
+rect 1258 -83 1292 -42
+rect 1434 -83 1468 -42
+rect 2696 -83 2730 -42
+rect 2872 -83 2906 -42
+rect 1258 -92 1262 -83
+rect 2696 -92 2700 -83
+rect 1258 -134 1262 -126
+rect 2696 -134 2700 -126
+rect 204 -334 238 -267
+rect 380 -334 414 -251
+rect 204 -368 414 -334
+rect 720 -303 754 -225
+rect 896 -303 930 -225
+rect 1170 -303 1204 -202
+rect 204 -403 238 -368
+rect 380 -429 414 -368
+rect 720 -337 1204 -303
+rect 720 -403 754 -337
+rect 896 -429 930 -337
+rect 1170 -413 1204 -337
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+rect 1434 -335 1468 -134
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+rect 2152 -303 2186 -209
+rect 2328 -303 2362 -209
+rect 2608 -303 2642 -202
+rect 1258 -369 2056 -335
+rect 2152 -337 2642 -303
+rect 1258 -415 1292 -369
+rect 1434 -415 1468 -369
+rect 1610 -417 1644 -369
+rect 1786 -403 1820 -369
+rect 2152 -403 2186 -337
+rect 2328 -429 2362 -337
+rect 2608 -413 2642 -337
+rect 2696 -335 2730 -134
+rect 2872 -335 2906 -134
+rect 3048 -335 3082 -134
+rect 3579 -335 3613 -209
+rect 3755 -335 3789 -267
+rect 4222 -334 4256 -267
+rect 4310 -270 4344 -209
+rect 2696 -369 3479 -335
+rect 3579 -369 3582 -335
+rect 3616 -369 3789 -335
+rect 2696 -415 2730 -369
+rect 2872 -415 2906 -369
+rect 3048 -417 3082 -369
+rect 3224 -403 3258 -369
+rect 3412 -470 3446 -369
+rect 3579 -403 3613 -369
+rect 3755 -403 3789 -369
+rect 3902 -369 3962 -335
+rect 3977 -369 4011 -335
+rect 116 -714 150 -503
+rect 292 -714 326 -503
+rect 632 -714 666 -477
+rect 808 -714 842 -477
+rect 1070 -645 1086 -611
+rect 1120 -645 1136 -611
+rect 1170 -633 1204 -599
+rect 1346 -633 1380 -599
+rect 1522 -633 1556 -573
+rect 1698 -633 1732 -573
+rect 1874 -633 1908 -573
+rect 1170 -667 1908 -633
+rect 1943 -645 1959 -611
+rect 1993 -645 2009 -611
+rect 2064 -714 2098 -488
+rect 2240 -714 2274 -488
+rect 3902 -433 3936 -369
+rect 4222 -403 4256 -368
+rect 2508 -645 2524 -611
+rect 2558 -645 2574 -611
+rect 2608 -633 2642 -599
+rect 2784 -633 2818 -599
+rect 2960 -633 2994 -573
+rect 3136 -633 3170 -573
+rect 3312 -633 3346 -573
+rect 2608 -667 3346 -633
+rect 3381 -645 3397 -611
+rect 3431 -645 3447 -611
+rect 3491 -714 3525 -501
+rect 3667 -714 3701 -501
+rect 3902 -510 3936 -467
+rect 3974 -470 4008 -436
+rect 3974 -585 4008 -477
+rect 4062 -714 4096 -486
+rect 4134 -714 4168 -486
+rect 4310 -714 4344 -486
+rect 68 -748 179 -714
+rect 4193 -748 4392 -714
+<< viali >>
+rect 151 107 4309 141
+rect 204 17 238 51
+rect 1077 17 1111 51
+rect 1703 17 1737 51
+rect 2515 17 2549 51
+rect 3141 17 3175 51
+rect 3974 -21 4008 13
+rect 1170 -126 1204 -92
+rect 1346 -126 1380 -92
+rect 1522 -126 1556 -92
+rect 2608 -126 2642 -92
+rect 2784 -126 2818 -92
+rect 2960 -126 2994 -92
+rect 120 -369 154 -335
+rect 204 -459 238 -425
+rect 636 -369 670 -335
+rect 3974 -262 4008 -228
+rect 3582 -369 3616 -335
+rect 4138 -369 4172 -335
+rect 4222 -368 4256 -334
+rect 1086 -645 1120 -611
+rect 1959 -645 1993 -611
+rect 3412 -504 3446 -470
+rect 3902 -467 3936 -433
+rect 2524 -645 2558 -611
+rect 3397 -645 3431 -611
+rect 3974 -619 4008 -585
+rect 179 -748 4193 -714
+<< metal1 >>
+rect 68 141 4392 153
+rect 68 107 151 141
+rect 4309 107 4392 141
+rect 68 95 4392 107
+rect 198 57 244 63
+rect 198 51 1765 57
+rect 198 17 204 51
+rect 238 17 1077 51
+rect 1111 17 1703 51
+rect 1737 17 1765 51
+rect 198 11 1765 17
+rect 2495 51 3203 57
+rect 2495 17 2515 51
+rect 2549 17 3141 51
+rect 3175 17 3203 51
+rect 2495 11 3203 17
+rect 3968 13 4014 25
+rect 198 5 244 11
+rect 1164 -92 1210 -80
+rect 1334 -92 1392 -86
+rect 1510 -92 1568 -86
+rect 1164 -126 1170 -92
+rect 1204 -126 1346 -92
+rect 1380 -126 1522 -92
+rect 1556 -126 1568 -92
+rect 1164 -138 1210 -126
+rect 1334 -132 1392 -126
+rect 1510 -132 1568 -126
+rect 2503 -236 2549 11
+rect 3968 -21 3974 13
+rect 4008 -21 4014 13
+rect 3968 -33 4014 -21
+rect 2602 -92 2648 -80
+rect 2772 -92 2830 -86
+rect 2948 -92 3006 -86
+rect 2602 -126 2608 -92
+rect 2642 -126 2784 -92
+rect 2818 -126 2960 -92
+rect 2994 -126 3006 -92
+rect 2602 -138 2648 -126
+rect 2772 -132 2830 -126
+rect 2948 -132 3006 -126
+rect 3974 -216 4008 -33
+rect 113 -282 2549 -236
+rect 3968 -228 4014 -216
+rect 3968 -262 3974 -228
+rect 4008 -262 4014 -228
+rect 3968 -274 4014 -262
+rect 113 -329 159 -282
+rect 68 -335 206 -329
+rect 68 -369 120 -335
+rect 154 -369 206 -335
+rect 68 -375 206 -369
+rect 620 -335 3628 -329
+rect 620 -369 636 -335
+rect 670 -369 3582 -335
+rect 3616 -369 3628 -335
+rect 620 -375 3628 -369
+rect 3974 -335 4008 -274
+rect 4126 -335 4184 -329
+rect 3974 -369 4138 -335
+rect 4172 -369 4184 -335
+rect 113 -605 159 -375
+rect 192 -425 2547 -419
+rect 192 -459 204 -425
+rect 238 -459 2547 -425
+rect 3896 -433 3942 -421
+rect 192 -465 2547 -459
+rect 2501 -605 2547 -465
+rect 3400 -470 3456 -458
+rect 3896 -467 3902 -433
+rect 3936 -467 3942 -433
+rect 3896 -470 3942 -467
+rect 3400 -504 3412 -470
+rect 3446 -479 3942 -470
+rect 3446 -504 3936 -479
+rect 3974 -501 4008 -369
+rect 4126 -375 4184 -369
+rect 4216 -334 4262 -322
+rect 4216 -368 4222 -334
+rect 4256 -368 4392 -334
+rect 4216 -380 4262 -368
+rect 3400 -512 3456 -504
+rect 3968 -585 4014 -501
+rect 113 -611 2005 -605
+rect 113 -645 1086 -611
+rect 1120 -645 1959 -611
+rect 1993 -645 2005 -611
+rect 113 -651 2005 -645
+rect 2495 -611 3443 -605
+rect 2495 -645 2524 -611
+rect 2558 -645 3397 -611
+rect 3431 -645 3443 -611
+rect 3968 -619 3974 -585
+rect 4008 -619 4014 -585
+rect 3968 -631 4014 -619
+rect 2495 -651 3443 -645
+rect 2501 -660 2547 -651
+rect 68 -714 4392 -702
+rect 68 -748 179 -714
+rect 4193 -748 4392 -714
+rect 68 -760 4392 -748
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1
+timestamp 1647279940
+transform 1 0 693 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1
+timestamp 1647276187
+transform 1 0 693 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin
+timestamp 1647279940
+transform 1 0 177 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1
+timestamp 1647282796
+transform 1 0 1231 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1
+timestamp 1647283104
+transform 1 0 1231 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2
+timestamp 1647276187
+transform 1 0 2125 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2
+timestamp 1647279940
+transform 1 0 2125 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2
+timestamp 1647283104
+transform 1 0 2669 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2
+timestamp 1647282796
+transform 1 0 2669 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb
+timestamp 1647276187
+transform 1 0 3552 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb
+timestamp 1647279940
+transform 1 0 3552 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2
+timestamp 1647281041
+transform 1 0 4195 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1
+timestamp 1647281419
+transform 1 0 4035 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1
+timestamp 1647281016
+transform 1 0 4035 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2
+timestamp 1647281419
+transform 1 0 4195 0 1 -422
+box -73 -199 161 103
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 786 -335 811 -311 1 3
+rlabel locali 1264 -321 1289 -297 1 4
+rlabel locali 2157 -323 2182 -299 1 5
+rlabel locali 3583 -321 3608 -297 1 2
+rlabel locali 3416 -430 3440 -404 1 6
+rlabel metal1 4072 -363 4097 -339 1 7
+rlabel metal1 4358 -368 4392 -334 1 Clk_Out
+port 4 n
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3.spice b/mag/3-stage_cs-vco_dp9/old/FD_v3.spice
new file mode 100755
index 0000000..ed812cd
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3.spice
@@ -0,0 +1,77 @@
+* NGSPICE file created from FD_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt FD_v3 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clkb GND Clk_In Clkb GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clkb VDD VDD Clkb VDD Clk_In sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMPTgate2 5 6 5 6 Clk_In 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y11.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y11.mag
new file mode 100755
index 0000000..02c7119
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y11.mag
@@ -0,0 +1,346 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647281419
+<< error_s >>
+rect 1378 17 1412 51
+rect 3901 -2263 3941 -2119
+rect 162 -2417 192 -2405
+rect 762 -2417 792 -2405
+rect 1864 -2417 1894 -2405
+rect 3168 -2417 3198 -2405
+rect 3799 -2417 3829 -2405
+rect 3959 -2417 3989 -2405
+rect 3901 -2489 3941 -2417
+rect 162 -2501 192 -2489
+rect 762 -2501 792 -2489
+rect 1864 -2501 1894 -2489
+rect 3168 -2501 3198 -2489
+rect 3799 -2501 3829 -2489
+rect 3959 -2501 3989 -2489
+<< nwell >>
+rect 68 -313 4171 178
+<< pwell >>
+rect 68 -769 4171 -313
+<< ndiff >>
+rect 3887 -585 3901 -417
+<< pdiff >>
+rect 3887 -263 3901 25
+<< psubdiff >>
+rect 68 -748 179 -714
+rect 3972 -748 4171 -714
+<< nsubdiff >>
+rect 127 107 151 141
+rect 4088 107 4115 141
+<< psubdiffcont >>
+rect 179 -748 3972 -714
+<< nsubdiffcont >>
+rect 151 107 4088 141
+<< poly >>
+rect 1234 -611 1301 -593
+rect 1234 -645 1250 -611
+rect 1284 -645 1301 -611
+rect 1234 -669 1301 -645
+rect 2371 -614 2450 -593
+rect 2371 -648 2386 -614
+rect 2420 -648 2450 -614
+rect 2371 -669 2450 -648
+<< polycont >>
+rect 1250 -645 1284 -611
+rect 2386 -648 2420 -614
+<< locali >>
+rect 68 107 151 141
+rect 4088 107 4171 141
+rect 116 13 150 107
+rect 292 13 326 107
+rect 468 13 502 107
+rect 716 29 750 107
+rect 892 13 926 107
+rect 1068 13 1102 107
+rect 1818 13 1852 107
+rect 2382 38 2515 58
+rect 2382 8 2388 38
+rect 2422 24 2515 38
+rect 2422 8 2428 24
+rect 3122 13 3156 107
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+rect 3913 13 3947 107
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+rect 204 -334 238 -267
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+rect 804 -303 838 -225
+rect 980 -303 1014 -225
+rect 1334 -303 1368 -202
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+rect 380 -429 414 -368
+rect 804 -337 1368 -303
+rect 804 -403 838 -337
+rect 980 -429 1014 -337
+rect 1334 -380 1368 -337
+rect 1422 -335 1456 -42
+rect 1906 -334 1940 -209
+rect 2477 -334 2511 -43
+rect 1422 -369 1810 -335
+rect 1906 -368 2511 -334
+rect 1422 -380 1456 -369
+rect 1906 -403 1940 -368
+rect 2477 -397 2511 -368
+rect 2565 -335 2599 -42
+rect 3610 -335 3644 -209
+rect 4001 -334 4035 -267
+rect 2565 -369 3110 -335
+rect 3610 -369 3613 -335
+rect 3681 -369 3741 -335
+rect 3756 -369 3790 -335
+rect 2565 -380 2599 -369
+rect 3043 -470 3077 -369
+rect 3610 -403 3644 -369
+rect 116 -714 150 -503
+rect 292 -714 326 -503
+rect 716 -714 750 -477
+rect 892 -714 926 -477
+rect 1234 -645 1250 -611
+rect 1284 -645 1300 -611
+rect 1818 -714 1852 -488
+rect 3681 -433 3715 -369
+rect 4001 -403 4035 -368
+rect 4089 -403 4123 -209
+rect 2370 -648 2386 -614
+rect 2420 -648 2436 -614
+rect 3122 -714 3156 -501
+rect 3681 -510 3715 -467
+rect 3753 -470 3787 -436
+rect 3753 -585 3787 -477
+rect 3841 -714 3875 -486
+rect 3913 -714 3947 -486
+rect 4089 -714 4123 -486
+rect 68 -748 179 -714
+rect 3972 -748 4171 -714
+<< viali >>
+rect 151 107 4088 141
+rect 204 17 238 51
+rect 1378 17 1412 51
+rect 2388 4 2422 38
+rect 3753 -21 3787 13
+rect 120 -369 154 -335
+rect 720 -369 754 -335
+rect 3753 -262 3787 -228
+rect 3613 -369 3647 -335
+rect 3917 -369 3951 -335
+rect 4001 -368 4035 -334
+rect 204 -486 238 -452
+rect 1250 -645 1284 -611
+rect 3043 -504 3077 -470
+rect 3681 -467 3715 -433
+rect 2386 -648 2420 -614
+rect 3753 -619 3787 -585
+rect 179 -748 3972 -714
+<< metal1 >>
+rect 68 141 4171 153
+rect 68 107 151 141
+rect 4088 107 4171 141
+rect 68 95 4171 107
+rect 198 57 244 63
+rect 198 51 1424 57
+rect 198 17 204 51
+rect 238 17 1378 51
+rect 1412 17 1424 51
+rect 198 11 1424 17
+rect 2382 38 2428 50
+rect 198 5 244 11
+rect 2382 4 2388 38
+rect 2422 4 2428 38
+rect 2382 -236 2428 4
+rect 3747 13 3793 25
+rect 3747 -21 3753 13
+rect 3787 -21 3793 13
+rect 3747 -33 3793 -21
+rect 3753 -216 3787 -33
+rect 113 -282 2428 -236
+rect 3747 -228 3793 -216
+rect 3747 -262 3753 -228
+rect 3787 -262 3793 -228
+rect 3747 -274 3793 -262
+rect 113 -329 159 -282
+rect 68 -335 206 -329
+rect 68 -369 120 -335
+rect 154 -369 206 -335
+rect 68 -375 206 -369
+rect 704 -335 3659 -329
+rect 704 -369 720 -335
+rect 754 -369 3613 -335
+rect 3647 -369 3659 -335
+rect 704 -375 3659 -369
+rect 3753 -335 3787 -274
+rect 3905 -335 3963 -329
+rect 3753 -369 3917 -335
+rect 3951 -369 3963 -335
+rect 113 -605 159 -375
+rect 3675 -433 3721 -421
+rect 192 -452 2426 -446
+rect 192 -486 204 -452
+rect 238 -486 2426 -452
+rect 192 -492 2426 -486
+rect 113 -611 1296 -605
+rect 113 -645 1250 -611
+rect 1284 -645 1296 -611
+rect 113 -651 1296 -645
+rect 2380 -614 2426 -492
+rect 3031 -470 3087 -458
+rect 3675 -467 3681 -433
+rect 3715 -467 3721 -433
+rect 3675 -470 3721 -467
+rect 3031 -504 3043 -470
+rect 3077 -479 3721 -470
+rect 3077 -504 3715 -479
+rect 3753 -501 3787 -369
+rect 3905 -375 3963 -369
+rect 3995 -334 4041 -322
+rect 3995 -368 4001 -334
+rect 4035 -368 4171 -334
+rect 3995 -380 4041 -368
+rect 3031 -588 3087 -504
+rect 3747 -585 3793 -501
+rect 2380 -648 2386 -614
+rect 2420 -648 2426 -614
+rect 3747 -619 3753 -585
+rect 3787 -619 3793 -585
+rect 3747 -631 3793 -619
+rect 2380 -660 2426 -648
+rect 68 -714 4171 -702
+rect 68 -748 179 -714
+rect 3972 -748 4171 -714
+rect 68 -760 4171 -748
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_0
+timestamp 1647118350
+transform 1 0 177 0 1 -2422
+box -73 -103 73 103
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_1
+timestamp 1647118350
+transform 1 0 777 0 1 -2422
+box -73 -103 73 103
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_0
+timestamp 1647117771
+transform 1 0 177 0 1 -2227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_1
+timestamp 1647117771
+transform 1 0 777 0 1 -2227
+box -109 -133 109 170
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_0
+timestamp 1647122709
+transform 1 0 1395 0 -1 -2499
+box -118 -141 73 98
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_2
+timestamp 1647118350
+transform 1 0 1879 0 1 -2422
+box -73 -103 73 103
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_0
+timestamp 1647119442
+transform 1 0 1395 0 1 -2173
+box -109 -140 109 106
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_2
+timestamp 1647117771
+transform 1 0 1879 0 1 -2227
+box -109 -133 109 170
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_3
+timestamp 1647117771
+transform 1 0 3183 0 1 -2227
+box -109 -133 109 170
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_3
+timestamp 1647118350
+transform 1 0 3183 0 1 -2422
+box -73 -103 73 103
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_1
+timestamp 1647122709
+transform 1 0 2538 0 -1 -2499
+box -118 -141 73 98
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_1
+timestamp 1647119442
+transform 1 0 2538 0 1 -2173
+box -109 -140 109 106
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_5
+timestamp 1647118350
+transform 1 0 3974 0 1 -2422
+box -73 -103 73 103
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_5
+timestamp 1647117771
+transform 1 0 3974 0 1 -2227
+box -109 -133 109 170
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_4
+timestamp 1647118350
+transform 1 0 3814 0 1 -2422
+box -73 -103 73 103
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_4
+timestamp 1647117771
+transform 1 0 3814 0 1 -2227
+box -109 -133 109 170
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_1
+timestamp 1647276187
+transform 1 0 777 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_1
+timestamp 1647279940
+transform 1 0 777 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_0
+timestamp 1647279940
+transform 1 0 177 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_2
+timestamp 1647276187
+transform 1 0 1879 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_2
+timestamp 1647279940
+transform 1 0 1879 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_3
+timestamp 1647276187
+transform 1 0 3183 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_3
+timestamp 1647279940
+transform 1 0 3183 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW7BNL sky130_fd_pr__nfet_01v8_PW7BNL_0
+timestamp 1647281419
+transform 1 0 3814 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0
+timestamp 1647281419
+transform 1 0 3974 0 1 -422
+box -73 -199 161 103
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0
+timestamp 1647281041
+transform 1 0 3974 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__pfet_01v8_A9DS5R sky130_fd_pr__pfet_01v8_A9DS5R_0
+timestamp 1647281016
+transform 1 0 3814 0 1 -227
+box -109 -133 109 314
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 870 -335 895 -311 1 3
+rlabel locali 1428 -321 1453 -297 1 4
+rlabel locali 1911 -323 1936 -299 1 5
+rlabel locali 2569 -318 2594 -294 1 6
+rlabel metal1 3851 -363 3876 -339 1 7
+rlabel locali 3614 -321 3639 -297 1 2
+rlabel metal1 4137 -368 4171 -334 1 Clk_Out
+port 4 n
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y50.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y50.mag
new file mode 100755
index 0000000..e9af982
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y50.mag
@@ -0,0 +1,401 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647283811
+<< nwell >>
+rect 68 83 5771 178
+rect 68 -7 1668 83
+rect 1834 -7 5771 83
+rect 68 -313 5771 -7
+<< pwell >>
+rect 68 -769 5771 -313
+<< ndiff >>
+rect 5487 -585 5501 -417
+<< pdiff >>
+rect 5487 -263 5501 25
+<< psubdiff >>
+rect 68 -748 179 -714
+rect 5572 -748 5771 -714
+<< nsubdiff >>
+rect 127 107 151 141
+rect 5688 107 5715 141
+<< psubdiffcont >>
+rect 179 -748 5572 -714
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+timestamp 1647276187
+transform 1 0 177 0 1 -422
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+timestamp 1647283104
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+transform 1 0 2679 0 1 -422
+box -73 -199 249 103
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+timestamp 1647281041
+transform 1 0 5574 0 1 -227
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+timestamp 1647281419
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+timestamp 1647281419
+transform 1 0 5414 0 1 -422
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+timestamp 1647281016
+transform 1 0 5414 0 1 -227
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+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_3
+timestamp 1647279940
+transform 1 0 4783 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_3
+timestamp 1647276187
+transform 1 0 4783 0 1 -422
+box -73 -199 249 103
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 870 -335 895 -311 1 3
+rlabel locali 2711 -323 2736 -299 1 5
+rlabel metal1 5737 -368 5771 -334 1 Clk_Out
+port 4 n
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+rlabel metal1 5451 -363 5476 -339 1 7
+rlabel locali 4647 -430 4671 -404 1 6
+rlabel locali 1428 -321 1453 -297 1 4
+rlabel locali 3381 -321 3406 -297 1 4
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y59.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y59.mag
new file mode 100755
index 0000000..ee58294
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_14-3-2022_19y59.mag
@@ -0,0 +1,412 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647284369
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+<< pdiff >>
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+<< psubdiff >>
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+<< psubdiffcont >>
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+timestamp 1647276187
+transform 1 0 777 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_1
+timestamp 1647279940
+transform 1 0 777 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_0
+timestamp 1647279940
+transform 1 0 177 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
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+timestamp 1647282796
+transform 1 0 1395 0 -1 1
+box -109 -86 461 314
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+timestamp 1647283104
+transform 1 0 1395 0 -1 -580
+box -73 -199 689 50
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+timestamp 1647279940
+transform 1 0 2679 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_2
+timestamp 1647276187
+transform 1 0 2679 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_1
+timestamp 1647282796
+transform 1 0 3348 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL sky130_fd_pr__nfet_01v8_PW9BNL_1
+timestamp 1647283104
+transform 1 0 3348 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW7BNL sky130_fd_pr__nfet_01v8_PW7BNL_0
+timestamp 1647281419
+transform 1 0 5414 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__pfet_01v8_A9DS5R sky130_fd_pr__pfet_01v8_A9DS5R_0
+timestamp 1647281016
+transform 1 0 5414 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_3
+timestamp 1647279940
+transform 1 0 4783 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_3
+timestamp 1647276187
+transform 1 0 4783 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0
+timestamp 1647281041
+transform 1 0 5574 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0
+timestamp 1647281419
+transform 1 0 5574 0 1 -422
+box -73 -199 161 103
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 870 -335 895 -311 1 3
+rlabel locali 2711 -323 2736 -299 1 5
+rlabel metal1 5737 -368 5771 -334 1 Clk_Out
+port 4 n
+rlabel metal1 5451 -363 5476 -339 1 7
+rlabel locali 4647 -430 4671 -404 1 6
+rlabel locali 1428 -321 1453 -297 1 4
+rlabel locali 4814 -321 4839 -297 1 2
+<< properties >>
+string LEFsite unithddb1
+string LEFclass CORE
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_15-3-2022_10y25.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_15-3-2022_10y25.mag
new file mode 100755
index 0000000..8903779
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_15-3-2022_10y25.mag
@@ -0,0 +1,409 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647284850
+<< nwell >>
+rect 68 -313 5771 178
+<< pwell >>
+rect 68 -769 5771 -313
+<< ndiff >>
+rect 5487 -585 5501 -417
+<< pdiff >>
+rect 5487 -263 5501 25
+<< psubdiff >>
+rect 68 -748 179 -714
+rect 5572 -748 5771 -714
+<< nsubdiff >>
+rect 127 107 151 141
+rect 5688 107 5715 141
+<< psubdiffcont >>
+rect 179 -748 5572 -714
+<< nsubdiffcont >>
+rect 151 107 5688 141
+<< poly >>
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+<< locali >>
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+rect 68 -760 5771 -748
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_1
+timestamp 1647276187
+transform 1 0 777 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_1
+timestamp 1647279940
+transform 1 0 777 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_0
+timestamp 1647279940
+transform 1 0 177 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0
+timestamp 1647282796
+transform 1 0 1395 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL sky130_fd_pr__nfet_01v8_PW9BNL_0
+timestamp 1647283104
+transform 1 0 1395 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_2
+timestamp 1647279940
+transform 1 0 2679 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_2
+timestamp 1647276187
+transform 1 0 2679 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_1
+timestamp 1647282796
+transform 1 0 3348 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL sky130_fd_pr__nfet_01v8_PW9BNL_1
+timestamp 1647283104
+transform 1 0 3348 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW7BNL sky130_fd_pr__nfet_01v8_PW7BNL_0
+timestamp 1647281419
+transform 1 0 5414 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__pfet_01v8_A9DS5R sky130_fd_pr__pfet_01v8_A9DS5R_0
+timestamp 1647281016
+transform 1 0 5414 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_3
+timestamp 1647279940
+transform 1 0 4783 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_3
+timestamp 1647276187
+transform 1 0 4783 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0
+timestamp 1647281041
+transform 1 0 5574 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0
+timestamp 1647281419
+transform 1 0 5574 0 1 -422
+box -73 -199 161 103
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 870 -335 895 -311 1 3
+rlabel locali 2711 -323 2736 -299 1 5
+rlabel metal1 5737 -368 5771 -334 1 Clk_Out
+port 4 n
+rlabel metal1 5451 -363 5476 -339 1 7
+rlabel locali 4647 -430 4671 -404 1 6
+rlabel locali 1428 -321 1453 -297 1 4
+rlabel locali 4814 -321 4839 -297 1 2
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_15-3-2022_11y23.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_15-3-2022_11y23.mag
new file mode 100755
index 0000000..4ad0d7d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3_-_seccopy_15-3-2022_11y23.mag
@@ -0,0 +1,410 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647339551
+<< nwell >>
+rect 68 -313 5771 178
+<< pwell >>
+rect 68 -769 5771 -313
+<< ndiff >>
+rect 5487 -585 5501 -417
+<< pdiff >>
+rect 5487 -263 5501 25
+<< psubdiff >>
+rect 68 -748 179 -714
+rect 5572 -748 5771 -714
+<< nsubdiff >>
+rect 127 107 151 141
+rect 5688 107 5715 141
+<< psubdiffcont >>
+rect 179 -748 5572 -714
+<< nsubdiffcont >>
+rect 151 107 5688 141
+<< poly >>
+rect 1225 52 1380 82
+rect 1762 52 1929 82
+rect 3178 52 3333 82
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+rect 1225 51 1291 52
+rect 1225 17 1241 51
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+rect 3187 -669 3254 -645
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+rect 4110 -645 4127 -611
+rect 4060 -669 4127 -645
+<< polycont >>
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+rect 3820 17 3854 51
+rect 1250 -645 1284 -611
+rect 2123 -645 2157 -611
+rect 3203 -645 3237 -611
+rect 4076 -645 4110 -611
+<< locali >>
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+rect 5513 -714 5547 -486
+rect 5689 -714 5723 -486
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+rect 5572 -748 5771 -714
+<< viali >>
+rect 151 107 5688 141
+rect 204 17 238 51
+rect 1241 17 1275 51
+rect 1867 17 1901 51
+rect 3194 17 3228 51
+rect 3820 17 3854 51
+rect 5353 -21 5387 13
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+rect 5353 -619 5387 -585
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+<< metal1 >>
+rect 68 141 5771 153
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+rect 192 -465 3226 -459
+rect 3180 -605 3226 -465
+rect 4631 -470 4687 -458
+rect 5275 -467 5281 -433
+rect 5315 -467 5321 -433
+rect 5275 -470 5321 -467
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+rect 4677 -479 5321 -470
+rect 4677 -504 5315 -479
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+rect 5505 -375 5563 -369
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+rect 5595 -368 5601 -334
+rect 5635 -368 5771 -334
+rect 5595 -380 5641 -368
+rect 4631 -588 4687 -504
+rect 5347 -585 5393 -501
+rect 113 -611 2169 -605
+rect 113 -645 1250 -611
+rect 1284 -645 2123 -611
+rect 2157 -645 2169 -611
+rect 113 -651 2169 -645
+rect 3174 -611 4122 -605
+rect 3174 -645 3203 -611
+rect 3237 -645 4076 -611
+rect 4110 -645 4122 -611
+rect 5347 -619 5353 -585
+rect 5387 -619 5393 -585
+rect 5347 -631 5393 -619
+rect 3174 -651 4122 -645
+rect 3180 -660 3226 -651
+rect 68 -714 5771 -702
+rect 68 -748 179 -714
+rect 5572 -748 5771 -714
+rect 68 -760 5771 -748
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1
+timestamp 1647276187
+transform 1 0 777 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1
+timestamp 1647279940
+transform 1 0 777 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin
+timestamp 1647279940
+transform 1 0 177 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1
+timestamp 1647282796
+transform 1 0 1395 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1
+timestamp 1647283104
+transform 1 0 1395 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2
+timestamp 1647279940
+transform 1 0 2679 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2
+timestamp 1647276187
+transform 1 0 2679 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2
+timestamp 1647282796
+transform 1 0 3348 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2
+timestamp 1647283104
+transform 1 0 3348 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1
+timestamp 1647281419
+transform 1 0 5414 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1
+timestamp 1647281016
+transform 1 0 5414 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb
+timestamp 1647279940
+transform 1 0 4783 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb
+timestamp 1647276187
+transform 1 0 4783 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2
+timestamp 1647281041
+transform 1 0 5574 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2
+timestamp 1647281419
+transform 1 0 5574 0 1 -422
+box -73 -199 161 103
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 870 -335 895 -311 1 3
+rlabel locali 2711 -323 2736 -299 1 5
+rlabel metal1 5737 -368 5771 -334 1 Clk_Out
+port 4 n
+rlabel metal1 5451 -363 5476 -339 1 7
+rlabel locali 4647 -430 4671 -404 1 6
+rlabel locali 1428 -321 1453 -297 1 4
+rlabel locali 4814 -321 4839 -297 1 2
+<< properties >>
+string LEFsite unithddb1
+string LEFclass CORE
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v3_crashes.mag b/mag/3-stage_cs-vco_dp9/old/FD_v3_crashes.mag
new file mode 100755
index 0000000..945f256
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v3_crashes.mag
@@ -0,0 +1,409 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647277268
+<< error_s >>
+rect 1729 322 1873 375
+rect 2054 317 2071 339
+rect 426 285 450 309
+rect 1361 285 1395 317
+rect 1449 285 1483 317
+rect 1537 285 1571 317
+rect 1865 285 1899 317
+rect 1953 285 1987 317
+rect 2008 312 2075 317
+rect 1999 301 2075 312
+rect 2008 285 2075 301
+rect 2096 285 2109 317
+rect 2157 301 2172 312
+rect 2214 301 2218 312
+rect 2245 301 2260 312
+rect 2302 301 2306 312
+rect 2168 285 2218 301
+rect 2256 285 2306 301
+rect 402 251 426 285
+rect 767 251 771 285
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+rect 1765 251 2338 285
+rect 426 227 450 251
+rect 117 141 150 175
+rect 151 141 167 157
+rect 204 141 238 173
+rect 380 157 414 173
+rect 380 141 426 157
+rect 117 125 442 141
+rect 117 123 426 125
+rect 117 107 442 123
+rect 117 73 150 107
+rect 151 91 167 107
+rect 414 91 426 107
+rect 1974 21 1987 251
+rect 2008 37 2075 251
+rect 2008 21 2021 37
+rect 2054 21 2075 37
+rect 1066 -70 1081 -55
+rect 1518 -70 1525 -28
+rect 955 -246 981 -129
+rect 1023 -136 1081 -70
+rect 1560 -72 1567 -70
+rect 2054 -72 2071 21
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+rect 2256 37 2306 251
+rect 2344 217 2372 317
+rect 1035 -151 1081 -136
+rect 947 -267 981 -246
+rect 989 -248 1023 -163
+rect 1035 -248 1069 -151
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+rect 2214 -429 2218 -418
+rect 2245 -429 2260 -418
+rect 2302 -429 2306 -418
+rect 2168 -573 2218 -429
+rect 2256 -573 2306 -429
+<< nwell >>
+rect 68 -313 2338 322
+<< pwell >>
+rect 68 -781 2338 -313
+<< ndiff >>
+rect 2142 -489 2156 -417
+<< pdiff >>
+rect 2142 -263 2156 -119
+<< psubdiff >>
+rect 68 -760 179 -726
+rect 2227 -760 2338 -726
+<< nsubdiff >>
+rect 771 251 805 285
+rect 1273 251 1307 285
+rect 1777 251 1811 285
+rect 2096 251 2130 285
+rect 2168 251 2202 285
+rect 2255 251 2282 285
+rect 127 107 151 141
+rect 292 107 326 141
+<< psubdiffcont >>
+rect 179 -760 2227 -726
+<< nsubdiffcont >>
+rect 426 251 771 285
+rect 805 251 1273 285
+rect 1307 251 1777 285
+rect 1811 251 2096 285
+rect 2130 251 2168 285
+rect 2202 251 2255 285
+rect 151 107 292 141
+rect 326 107 426 141
+<< poly >>
+rect 889 -539 956 -521
+rect 889 -573 905 -539
+rect 939 -573 956 -539
+rect 889 -597 956 -573
+rect 1426 -542 1505 -521
+rect 1426 -576 1441 -542
+rect 1475 -576 1505 -542
+rect 1426 -597 1505 -576
+<< polycont >>
+rect 905 -573 939 -539
+rect 1441 -576 1475 -542
+<< locali >>
+rect 68 251 151 285
+rect 116 -131 150 251
+rect 292 -131 326 251
+rect 771 -115 805 285
+rect 1273 -131 1307 285
+rect 1437 -106 1570 -86
+rect 1437 -136 1443 -106
+rect 1477 -120 1570 -106
+rect 1477 -136 1483 -120
+rect 1777 -131 1811 285
+rect 2096 -131 2130 285
+rect 2168 -131 2202 285
+rect 2255 251 2338 285
+rect 204 -403 238 -267
+rect 380 -403 414 -267
+rect 859 -280 893 -225
+rect 989 -280 1023 -202
+rect 859 -314 1023 -280
+rect 859 -403 893 -314
+rect 989 -380 1023 -314
+rect 1077 -335 1111 -186
+rect 1361 -334 1395 -209
+rect 1532 -334 1566 -187
+rect 1077 -369 1265 -335
+rect 1361 -368 1566 -334
+rect 1077 -380 1111 -369
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+rect 1620 -335 1654 -186
+rect 1865 -335 1899 -209
+rect 2256 -334 2290 -209
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+rect 1936 -369 1996 -335
+rect 2011 -369 2045 -335
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+rect 1865 -403 1899 -369
+rect 116 -726 150 -503
+rect 771 -726 805 -477
+rect 889 -573 905 -539
+rect 939 -573 955 -539
+rect 1273 -726 1307 -488
+rect 1936 -433 1970 -369
+rect 2256 -403 2290 -368
+rect 1425 -576 1441 -542
+rect 1475 -576 1491 -542
+rect 1777 -726 1811 -501
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+rect 2008 -470 2042 -436
+rect 2008 -513 2042 -477
+rect 2096 -726 2130 -486
+rect 2168 -726 2202 -486
+rect 68 -760 179 -726
+rect 2227 -760 2338 -726
+<< viali >>
+rect 151 251 426 285
+rect 426 251 771 285
+rect 204 -127 238 -93
+rect 805 251 1273 285
+rect 1033 -127 1067 -93
+rect 1307 251 1777 285
+rect 1443 -140 1477 -106
+rect 1811 251 2096 285
+rect 2130 251 2168 285
+rect 2202 251 2255 285
+rect 2008 -165 2042 -131
+rect 120 -369 154 -335
+rect 775 -369 809 -335
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+rect 2172 -369 2206 -335
+rect 2256 -368 2290 -334
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+rect 905 -573 939 -539
+rect 1698 -504 1732 -470
+rect 1936 -467 1970 -433
+rect 1441 -576 1475 -542
+rect 2008 -547 2042 -513
+rect 179 -760 2227 -726
+<< metal1 >>
+rect 68 285 2338 297
+rect 68 251 151 285
+rect 771 251 805 285
+rect 1273 251 1307 285
+rect 1777 251 1811 285
+rect 2096 251 2130 285
+rect 2168 251 2202 285
+rect 2255 251 2338 285
+rect 68 239 2338 251
+rect 198 -87 244 -81
+rect 198 -93 1079 -87
+rect 198 -127 204 -93
+rect 238 -127 1033 -93
+rect 1067 -127 1079 -93
+rect 198 -133 1079 -127
+rect 1437 -106 1483 -94
+rect 198 -139 244 -133
+rect 1437 -140 1443 -106
+rect 1477 -140 1483 -106
+rect 1437 -236 1483 -140
+rect 2002 -131 2048 -119
+rect 2002 -165 2008 -131
+rect 2042 -165 2048 -131
+rect 2002 -177 2048 -165
+rect 2008 -216 2042 -177
+rect 113 -282 1483 -236
+rect 2002 -228 2048 -216
+rect 2002 -262 2008 -228
+rect 2042 -262 2048 -228
+rect 2002 -274 2048 -262
+rect 113 -329 159 -282
+rect 68 -335 206 -329
+rect 68 -369 120 -335
+rect 154 -369 206 -335
+rect 68 -375 206 -369
+rect 759 -335 1914 -329
+rect 759 -369 775 -335
+rect 809 -369 1868 -335
+rect 1902 -369 1914 -335
+rect 759 -375 1914 -369
+rect 2008 -335 2042 -274
+rect 2160 -335 2218 -329
+rect 2008 -369 2172 -335
+rect 2206 -369 2218 -335
+rect 113 -533 159 -375
+rect 1930 -433 1976 -421
+rect 192 -452 1481 -446
+rect 192 -486 204 -452
+rect 238 -486 1481 -452
+rect 192 -492 1481 -486
+rect 113 -539 951 -533
+rect 113 -573 905 -539
+rect 939 -573 951 -539
+rect 113 -579 951 -573
+rect 1435 -542 1481 -492
+rect 1686 -470 1742 -458
+rect 1930 -467 1936 -433
+rect 1970 -467 1976 -433
+rect 1930 -470 1976 -467
+rect 1686 -504 1698 -470
+rect 1732 -479 1976 -470
+rect 1732 -504 1970 -479
+rect 2008 -501 2042 -369
+rect 2160 -375 2218 -369
+rect 2250 -334 2296 -322
+rect 2250 -368 2256 -334
+rect 2290 -368 2338 -334
+rect 2250 -380 2296 -368
+rect 1686 -516 1742 -504
+rect 2002 -513 2048 -501
+rect 1435 -576 1441 -542
+rect 1475 -576 1481 -542
+rect 2002 -547 2008 -513
+rect 2042 -547 2048 -513
+rect 2002 -559 2048 -547
+rect 1435 -588 1481 -576
+rect 68 -726 2338 -714
+rect 68 -760 179 -726
+rect 2227 -760 2338 -726
+rect 68 -772 2338 -760
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_1
+timestamp 1647276239
+transform 1 0 832 0 1 -227
+box -109 -133 285 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_1
+timestamp 1647276187
+transform 1 0 832 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_0
+timestamp 1647122709
+transform 1 0 1050 0 -1 -499
+box -118 -141 73 98
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_0
+timestamp 1647119442
+transform 1 0 1050 0 1 -173
+box -109 -140 109 106
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_1
+timestamp 1647122709
+transform 1 0 1593 0 -1 -499
+box -118 -141 73 98
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_2
+timestamp 1647276187
+transform 1 0 1334 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_1
+timestamp 1647119442
+transform 1 0 1593 0 1 -173
+box -109 -140 109 106
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_3
+timestamp 1647276187
+transform 1 0 1838 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_4
+timestamp 1647276187
+transform 1 0 2069 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_5
+timestamp 1647276187
+transform 1 0 2229 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_2
+timestamp 1647276239
+transform 1 0 1334 0 1 61
+box -109 -133 285 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_4
+timestamp 1647276239
+transform 1 0 2069 0 1 61
+box -109 -133 285 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_3
+timestamp 1647276239
+transform 1 0 1838 0 1 61
+box -109 -133 285 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_5
+timestamp 1647276239
+transform 1 0 2229 0 1 61
+box -109 -133 285 314
+use sky130_fd_pr__pfet_01v8_A8DS5R sky130_fd_pr__pfet_01v8_A8DS5R_0
+timestamp 1647276239
+transform 1 0 177 0 1 -83
+box -109 -133 285 314
+<< labels >>
+rlabel metal1 68 -375 92 -329 1 Clk_In
+port 1 n
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 2304 -368 2338 -334 1 Clk_Out
+port 4 n
+rlabel locali 925 -312 950 -288 1 3
+rlabel locali 1083 -321 1108 -297 1 4
+rlabel locali 1366 -323 1391 -299 1 5
+rlabel locali 1624 -318 1649 -294 1 6
+rlabel locali 1869 -321 1894 -297 1 2
+rlabel metal1 2106 -363 2131 -339 1 7
+rlabel metal1 96 -772 130 -714 1 GND
+port 3 n
+rlabel metal1 68 239 102 297 1 VDD
+port 2 n
+<< properties >>
+string LEFclass CORE
+string LEFsite unithddb1
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v4.ext b/mag/3-stage_cs-vco_dp9/old/FD_v4.ext
new file mode 100755
index 0000000..a63c3bb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v4.ext
@@ -0,0 +1,419 @@
+timestamp 1647362795
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0 1 0 -25 0 1 -422
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0 1 0 -25 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0 1 0 -273 0 1 -422
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0 1 0 -273 0 1 -227
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin 1 0 529 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin 1 0 529 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1 1 0 1045 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1 1 0 1045 0 1 -422
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1 1 0 1583 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1 1 0 1583 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2 1 0 2477 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2 1 0 2477 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2 1 0 3021 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2 1 0 3021 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb 1 0 3904 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb 1 0 3904 0 1 -227
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2 1 0 4547 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2 1 0 4547 0 1 -422
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1 1 0 4387 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1 1 0 4387 0 1 -422
+port "Clk_Out" 4 4710 -368 4744 -334 m1
+port "Clk_In" 1 -382 -369 -357 -335 m1
+port "VDD" 2 156 95 190 153 m1
+port "GND" 3 184 -760 218 -702 m1
+node "li_4326_n470#" 12 61.4277 4326 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2960_n667#" 354 1378.44 2960 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1522_n667#" 354 1376.53 1522 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4329_n369#" 12 60.0815 4329 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4662_n270#" 22 5.19444 4662 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 49 278.477 4710 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 7088 468 0 0 0 0 0 0 0 0 0 0
+node "5" 363 480.387 2504 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34442 2094 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 217 2591.72 988 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17204 1148 138368 6108 0 0 0 0 0 0 0 0 0 0
+node "3" 350 477.852 1072 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33150 2018 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb" 164 322.461 556 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15504 980 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 50 379.31 -382 -369 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 7224 476 0 0 0 0 0 0 0 0 0 0
+node "li_90_n270#" 22 5.19444 90 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "6" 713 1903.73 3048 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64496 3944 21652 1290 0 0 0 0 0 0 0 0 0 0
+node "4" 571 948.077 1610 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53582 3234 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2960_n126#" 122 -1.64 2960 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_1522_n126#" 122 -1.64 1522 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_3224_n83#" 15 0 3224 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3048_n92#" 31 0 3048 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1786_n83#" 15 0 1786 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1610_n92#" 31 0 1610 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "7" 190 869.952 4326 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8296 760 31936 1828 0 0 0 0 0 0 0 0 0 0
+node "Clkb_int" 247 1007.53 -246 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10846 978 33290 1872 0 0 0 0 0 0 0 0 0 0
+node "a_2860_n669#" 678 4356.3 2860 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14984 892 0 0 5644 536 158792 6996 0 0 0 0 0 0 0 0 0 0
+node "a_4460_n585#" 1440 0 4460 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n585#" 1440 0 -112 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n40_n319#" 903 125.905 -40 -319 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2266 434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4460_n263#" 4053 0 4460 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n263#" 4053 0 -112 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_in_buf" 1723 4283.16 1422 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31376 1860 0 0 32096 2296 280952 12384 0 0 0 0 0 0 0 0 0 0
+node "a_1413_1#" 722 -180.421 1413 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 968 0 0 5644 536 72634 3250 0 0 0 0 0 0 0 0 0 0
+node "VDD" 37076 7441.73 156 95 m1 0 0 0 0 2517102 11236 0 0 158814 9478 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 244732 14464 297366 10370 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 184 -760 m1 2337456 11164 0 0 0 0 0 0 0 0 174284 10320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 288864 17060 297308 10368 0 0 0 0 0 0 0 0 0 0
+cap "li_1522_n126#" "VDD" 410.223
+cap "4" "VDD" 275.264
+cap "3" "VDD" 238.741
+cap "li_4329_n369#" "6" 74.8
+cap "5" "6" 171.334
+cap "7" "Clk_Out" 92.3198
+cap "li_4329_n369#" "li_4326_n470#" 15.2687
+cap "li_1786_n83#" "li_1610_n92#" 9.52817
+cap "Clkb_int" "VDD" 283.123
+cap "li_4662_n270#" "7" 3.71523
+cap "li_1522_n126#" "a_2860_n669#" 62.7219
+cap "Clk_Out" "VDD" 30.2767
+cap "3" "a_2860_n669#" 20.449
+cap "VDD" "Clkb" 70.9841
+cap "li_4662_n270#" "VDD" 45.9225
+cap "a_2860_n669#" "Clkb" 72.3786
+cap "li_1522_n126#" "2" 90.9805
+cap "4" "2" 415.856
+cap "Clkb_int" "a_n112_n585#" 7.0744
+cap "3" "2" 331.614
+cap "VDD" "li_90_n270#" 45.9225
+cap "li_1522_n126#" "a_1413_1#" 182.29
+cap "VDD" "li_3224_n83#" 39.5697
+cap "a_1413_1#" "4" 3.33929
+cap "a_1413_1#" "3" 3.69079
+cap "2" "Clkb" 5.13697
+cap "li_3224_n83#" "li_3048_n92#" 9.52817
+cap "7" "VDD" 269.598
+cap "a_1413_1#" "Clkb" 3.9507
+cap "Clk_In" "Clk_in_buf" 20.974
+cap "li_2960_n126#" "VDD" 410.223
+cap "Clk_in_buf" "6" 3.33929
+cap "4" "5" 18.9494
+cap "VDD" "li_3048_n92#" 43.293
+cap "li_2960_n667#" "a_2860_n669#" 602.691
+cap "li_1522_n126#" "li_1610_n92#" 1.88
+cap "4" "li_1610_n92#" 23.2941
+cap "li_2960_n126#" "li_3048_n92#" 1.88
+cap "a_n40_n319#" "VDD" 59.4
+cap "li_4329_n369#" "Clk_Out" 5.31754
+cap "7" "2" 12.3056
+cap "li_4326_n470#" "6" 29.5263
+cap "Clkb_int" "a_n112_n263#" 2.9155
+cap "2" "VDD" 92.652
+cap "li_2960_n126#" "2" 90.9805
+cap "a_1413_1#" "VDD" 3289.76
+cap "2" "a_2860_n669#" 2147.27
+cap "7" "li_4329_n369#" 61.6231
+cap "li_2960_n667#" "5" 6.03226
+cap "li_1522_n126#" "Clk_in_buf" 170.315
+cap "4" "Clk_in_buf" 130.852
+cap "5" "VDD" 254.495
+cap "3" "Clk_in_buf" 129.801
+cap "li_1610_n92#" "VDD" 43.293
+cap "li_2960_n126#" "5" 14.7632
+cap "a_1413_1#" "2" 151.544
+cap "Clkb_int" "Clk_in_buf" 101.042
+cap "5" "a_2860_n669#" 28.3979
+cap "Clk_in_buf" "Clkb" 131.86
+cap "Clk_in_buf" "li_1522_n667#" 602.691
+cap "li_1786_n83#" "4" 22
+cap "Clkb_int" "Clk_In" 235.533
+cap "li_4329_n369#" "2" 5.96809
+cap "Clk_Out" "6" 8.23846
+cap "2" "5" 307.459
+cap "Clk_in_buf" "li_90_n270#" 26.2851
+cap "Clk_in_buf" "VDD" 3209.52
+cap "li_3224_n83#" "6" 22
+cap "li_2960_n126#" "Clk_in_buf" 235.31
+cap "li_2960_n667#" "6" 88.9945
+cap "7" "6" 146.867
+cap "a_n40_n319#" "Clk_in_buf" 15.0989
+cap "a_2860_n669#" "Clk_in_buf" 1434.45
+cap "Clk_In" "VDD" 5.1
+cap "7" "li_4326_n470#" 181.929
+cap "li_1522_n126#" "4" 12.6168
+cap "VDD" "6" 275.264
+cap "li_1522_n126#" "3" 14.7632
+cap "li_1786_n83#" "VDD" 39.5697
+cap "3" "4" 170.035
+cap "li_2960_n126#" "6" 12.6168
+cap "6" "li_3048_n92#" 23.2941
+cap "2" "Clk_in_buf" 2205.51
+cap "a_2860_n669#" "6" 35.6561
+cap "3" "Clkb" 16.3922
+cap "4" "li_1522_n667#" 88.9945
+cap "3" "li_1522_n667#" 6.03226
+cap "a_1413_1#" "Clk_in_buf" 286.772
+cap "li_4662_n270#" "Clk_Out" 1.83333
+cap "2" "6" 578.272
+cap "5" "Clk_in_buf" 84.9256
+cap "Clkb_int" "li_90_n270#" 5.79139
+cap "MPinv1/a_15_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" 47.1955
+cap "MPinv1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" -347.139
+cap "MPinv1/a_n15_n133#" "MPClkin/a_191_n36#" 0.396021
+cap "MPinv1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" 8.20812
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" 11.4
+cap "MPinv1/a_15_n36#" "MPClkin/a_191_n36#" 25.6667
+cap "MPinv1/a_15_n36#" "MPinv1/a_n15_n133#" -78.2357
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" 133.413
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 510.788
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" -10.7135
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" 433.967
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" 284.368
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" 46.4505
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 910.561
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "MPClkin/a_191_n36#" 117.123
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" 168.807
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "MPClkin/a_191_n36#" 429.202
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "MPinv1/a_n15_n133#" 13.3856
+cap "MPinv1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 32.9276
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "MPClkin/a_191_n36#" 92.7169
+cap "a_2860_n669#" "MPinv1/a_15_n36#" 435.356
+cap "MPTgate1/a_15_n36#" "MPinv1/a_15_n36#" 351.467
+cap "MPClkin/a_103_n36#" "MNClkin/a_103_n163#" 8.73529
+cap "MPClkin/a_103_n36#" "Clk_in_buf" -335.438
+cap "MNTgate1/a_n15_n199#" "MPinv1/a_15_n36#" 79.491
+cap "MPinv1/a_n15_n133#" "MPinv1/a_15_n36#" 187.723
+cap "a_2860_n669#" "MNTgate1/a_n15_n199#" 125.22
+cap "a_2860_n669#" "MPTgate1/a_15_n36#" 260.46
+cap "MPClkin/a_191_n36#" "MPinv1/a_15_n36#" 25.6667
+cap "MPTgate1/a_15_n36#" "MNTgate1/a_n15_n199#" 12.5626
+cap "MPTgate1/a_n15_n81#" "MPinv1/a_15_n36#" 327.776
+cap "MPinv1/a_n15_n133#" "MPTgate1/a_15_n36#" -63.2174
+cap "a_2860_n669#" "MPinv1/a_n15_n133#" 46.9575
+cap "MPinv1/a_15_n36#" "MPinv2/a_15_n36#" 13.2541
+cap "MPinv1/a_n15_n133#" "MNTgate1/a_n15_n199#" 49.7049
+cap "MPTgate1/a_n15_n81#" "MPTgate1/a_15_n36#" 166.942
+cap "MPClkin/a_191_n36#" "MPinv1/a_n15_n133#" -2.23506
+cap "MPTgate1/a_15_n36#" "MPinv2/a_15_n36#" -71.794
+cap "MPTgate1/a_n15_n81#" "MNTgate1/a_n15_n199#" 33.715
+cap "MPTgate1/a_n15_n81#" "MPinv1/a_n15_n133#" 82.0471
+cap "MPinv1/a_n15_n133#" "MNClkin/a_n73_37#" 25.8177
+cap "Clk_in_buf" "MPinv1/a_15_n36#" 109.937
+cap "MNClkin/a_103_n163#" "MPinv1/a_15_n36#" 513.972
+cap "MPTgate1/a_15_n36#" "Clk_in_buf" 36.372
+cap "MPClkin/a_103_n36#" "MPinv1/a_15_n36#" 84.2532
+cap "MNClkin/a_103_n163#" "MPTgate1/a_15_n36#" -31.7558
+cap "a_2860_n669#" "MNClkin/a_103_n163#" -785.649
+cap "MNClkin/a_103_n163#" "MNTgate1/a_n15_n199#" 1070.45
+cap "MPClkin/a_103_n36#" "MPTgate1/a_15_n36#" -208.389
+cap "MPinv1/a_n15_n133#" "Clk_in_buf" 75.53
+cap "MPinv1/a_n15_n133#" "MNClkin/a_103_n163#" 511.065
+cap "MPClkin/a_191_n36#" "MNClkin/a_103_n163#" 21.0926
+cap "MPClkin/a_103_n36#" "MPinv1/a_n15_n133#" 0.394635
+cap "MPTgate1/a_n15_n81#" "Clk_in_buf" 77.0187
+cap "MNClkin/a_103_n163#" "MPinv2/a_15_n36#" 7.10543e-15
+cap "MPClkin/a_191_n36#" "MPClkin/a_103_n36#" 31.8541
+cap "MPClkin/a_103_n36#" "MPTgate1/a_n15_n81#" -494.536
+cap "MPClkin/a_103_n36#" "MPinv2/a_15_n36#" -7.10543e-15
+cap "a_1413_1#" "MNTgate1/a_543_n163#" 0.837535
+cap "MPinv2/a_15_n36#" "MPTgate2/a_n15_n81#" 279.834
+cap "MPinv2/a_15_n36#" "MNinv2/a_n73_n163#" 481.507
+cap "MNfb/a_15_n163#" "MNTgate1/a_543_n163#" -389.255
+cap "MPinv2/a_15_n36#" "MNTgate2/a_n15_n199#" 189.272
+cap "MNTgate2/a_15_n163#" "MNfb/a_15_n163#" -89.388
+cap "MNinv2/a_n73_n163#" "MNTgate1/a_455_n163#" 34.7385
+cap "MPinv2/a_15_n36#" "MPinv2/w_n109_n86#" 18.9581
+cap "MNTgate1/a_543_n163#" "MPTgate2/a_n15_n81#" 95.3515
+cap "a_1413_1#" "MPinv2/w_n109_n86#" 0.603659
+cap "MNTgate2/a_15_n163#" "MPTgate2/a_n15_n81#" 166.968
+cap "MNinv2/a_n73_n163#" "MNTgate1/a_543_n163#" 519.649
+cap "MNfb/a_15_n163#" "MNinv2/a_n73_n163#" -68.9396
+cap "MNTgate2/a_15_n163#" "MNinv2/a_n73_n163#" 425.533
+cap "MNTgate2/a_n15_n199#" "MNTgate1/a_543_n163#" 57.8321
+cap "Clk_in_buf" "MNTgate1/a_543_n163#" 12.0022
+cap "MNTgate1/a_543_n163#" "MPinv2/w_n109_n86#" 16.0147
+cap "MNTgate2/a_15_n163#" "MNTgate2/a_n15_n199#" 12.8179
+cap "MPinv2/a_15_n36#" "MNTgate1/a_455_n163#" 13.2541
+cap "MNTgate2/a_15_n163#" "MPinv2/w_n109_n86#" -209.907
+cap "MNTgate2/a_n15_n199#" "MPTgate2/a_n15_n81#" 33.715
+cap "MPinv2/w_n109_n86#" "MPTgate2/a_n15_n81#" -327.581
+cap "MNTgate2/a_n15_n199#" "MNinv2/a_n73_n163#" 675.515
+cap "MPinv2/a_15_n36#" "MNfb/a_15_n163#" 13.8798
+cap "MPinv2/a_15_n36#" "MNTgate1/a_543_n163#" 216.792
+cap "MNinv2/a_n73_n163#" "MPinv2/w_n109_n86#" 16.2574
+cap "MNTgate2/a_15_n163#" "MPinv2/a_15_n36#" 413.367
+cap "MPfb/w_n109_n86#" "MPbuf2/a_n15_n133#" 191.721
+cap "MNfb/a_n73_n163#" "MPfb/w_n109_n86#" 36.2416
+cap "Clk_in_buf" "MPfb/w_n109_n86#" 0.626582
+cap "MPfb/w_n109_n86#" "MPbuf2/a_15_n36#" 103.281
+cap "a_2860_n669#" "MNTgate2/a_543_n163#" 12.8179
+cap "MNfb/a_15_n163#" "MPfb/w_n109_n86#" 46.1036
+cap "MPfb/w_n109_n86#" "MNTgate2/a_543_n163#" 16.5
+cap "MNfb/a_n73_n163#" "MPbuf2/a_n15_n133#" 174.714
+cap "MNfb/a_n73_n163#" "MNTgate2/a_455_n163#" 36.8215
+cap "MPbuf2/a_n15_n133#" "MPbuf2/a_15_n36#" 197.383
+cap "MNfb/a_15_n163#" "MPbuf2/a_n15_n133#" 129.784
+cap "MNfb/a_15_n163#" "MNTgate2/a_455_n163#" 13.8798
+cap "MNfb/a_n73_n163#" "MPbuf2/a_15_n36#" 83.329
+cap "MNfb/a_15_n163#" "MNfb/a_n73_n163#" 121.552
+cap "MNTgate2/a_543_n163#" "MPbuf2/a_n15_n133#" 140.801
+cap "Clk_in_buf" "MNTgate2/a_543_n163#" 0.864162
+cap "MNfb/a_n73_n163#" "MNTgate2/a_543_n163#" 1058.03
+cap "MNTgate2/a_543_n163#" "MPbuf2/a_15_n36#" 8.49674
+cap "MNfb/a_15_n163#" "MNTgate2/a_543_n163#" 467.192
+merge "MNTgate2/a_n15_n199#" "MPTgate1/a_n15_n81#" -972.402 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 224303 -240 0 0 33278 -584 -22660 -2800 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate1/a_n15_n81#" "MNClkin/a_15_n163#"
+merge "MNClkin/a_15_n163#" "a_2860_n669#"
+merge "a_2860_n669#" "MNClkin/a_191_n163#"
+merge "MNClkin/a_191_n163#" "MPClkin/a_15_n36#"
+merge "MPClkin/a_15_n36#" "a_1413_1#"
+merge "a_1413_1#" "MPClkin/a_191_n36#"
+merge "MPClkin/a_191_n36#" "Clkb"
+merge "MPbuf1/a_15_n36#" "MPbuf1/w_n109_n86#" -4349.33 0 0 0 0 -1458000 -16936 0 0 0 0 0 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10552 -2848 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf1/w_n109_n86#" "MPbuf2/a_103_n36#"
+merge "MPbuf2/a_103_n36#" "li_4662_n270#"
+merge "li_4662_n270#" "MPbuf2/a_n73_n36#"
+merge "MPbuf2/a_n73_n36#" "a_4460_n263#"
+merge "a_4460_n263#" "MPbuf2/w_n109_n86#"
+merge "MPbuf2/w_n109_n86#" "MPfb/a_279_n36#"
+merge "MPfb/a_279_n36#" "MPfb/a_103_n36#"
+merge "MPfb/a_103_n36#" "MPfb/a_n73_n36#"
+merge "MPfb/a_n73_n36#" "MPfb/w_n109_n86#"
+merge "MPfb/w_n109_n86#" "MPTgate2/w_n109_n86#"
+merge "MPTgate2/w_n109_n86#" "MPinv2/a_279_n36#"
+merge "MPinv2/a_279_n36#" "MPinv2/a_103_n36#"
+merge "MPinv2/a_103_n36#" "MPinv2/a_n73_n36#"
+merge "MPinv2/a_n73_n36#" "MPinv2/w_n109_n86#"
+merge "MPinv2/w_n109_n86#" "MPTgate1/w_n109_n86#"
+merge "MPTgate1/w_n109_n86#" "MPinv1/a_n73_n36#"
+merge "MPinv1/a_n73_n36#" "MPinv1/a_279_n36#"
+merge "MPinv1/a_279_n36#" "MPinv1/a_103_n36#"
+merge "MPinv1/a_103_n36#" "MPinv1/w_n109_n86#"
+merge "MPinv1/w_n109_n86#" "MPClkin/a_279_n36#"
+merge "MPClkin/a_279_n36#" "MPClkin/a_103_n36#"
+merge "MPClkin/a_103_n36#" "MPClkin/a_n73_n36#"
+merge "MPClkin/a_n73_n36#" "MPClkin/w_n109_n86#"
+merge "MPClkin/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#" "li_90_n270#"
+merge "li_90_n270#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#" "a_n112_n263#"
+merge "a_n112_n263#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "VDD"
+merge "MNbuf1/VSUBS" "MNbuf1/a_15_n163#" -1273.54 0 0 0 0 0 0 0 0 0 -1344 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35829 -4310 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf1/a_15_n163#" "MPbuf1/VSUBS"
+merge "MPbuf1/VSUBS" "MNbuf2/VSUBS"
+merge "MNbuf2/VSUBS" "MNbuf2/a_103_n163#"
+merge "MNbuf2/a_103_n163#" "MNbuf2/a_n73_n163#"
+merge "MNbuf2/a_n73_n163#" "a_4460_n585#"
+merge "a_4460_n585#" "MPbuf2/VSUBS"
+merge "MPbuf2/VSUBS" "MPfb/VSUBS"
+merge "MPfb/VSUBS" "MNfb/VSUBS"
+merge "MNfb/VSUBS" "MNfb/a_103_n163#"
+merge "MNfb/a_103_n163#" "MNfb/a_n73_n163#"
+merge "MNfb/a_n73_n163#" "MPTgate2/VSUBS"
+merge "MPTgate2/VSUBS" "MNTgate2/VSUBS"
+merge "MNTgate2/VSUBS" "MNinv2/VSUBS"
+merge "MNinv2/VSUBS" "MNinv2/a_103_n163#"
+merge "MNinv2/a_103_n163#" "MNinv2/a_n73_n163#"
+merge "MNinv2/a_n73_n163#" "MPinv2/VSUBS"
+merge "MPinv2/VSUBS" "MNTgate1/VSUBS"
+merge "MNTgate1/VSUBS" "MPTgate1/VSUBS"
+merge "MPTgate1/VSUBS" "MNinv1/VSUBS"
+merge "MNinv1/VSUBS" "MNinv1/a_103_n163#"
+merge "MNinv1/a_103_n163#" "MNinv1/a_n73_n163#"
+merge "MNinv1/a_n73_n163#" "MPinv1/VSUBS"
+merge "MPinv1/VSUBS" "MNClkin/VSUBS"
+merge "MNClkin/VSUBS" "MNClkin/a_103_n163#"
+merge "MNClkin/a_103_n163#" "MNClkin/a_n73_n163#"
+merge "MNClkin/a_n73_n163#" "MPClkin/VSUBS"
+merge "MPClkin/VSUBS" "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "GND"
+merge "GND" "a_n112_n585#"
+merge "MNinv2/a_n73_37#" "MPinv2/a_n15_n133#" -231.452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1431 -538 0 0 -16320 -1688 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPinv2/a_n15_n133#" "MNTgate1/a_543_n163#"
+merge "MNTgate1/a_543_n163#" "MNTgate1/a_367_n163#"
+merge "MNTgate1/a_367_n163#" "MNTgate1/a_191_n163#"
+merge "MNTgate1/a_191_n163#" "MNTgate1/a_15_n163#"
+merge "MNTgate1/a_15_n163#" "MPTgate1/a_367_n36#"
+merge "MPTgate1/a_367_n36#" "MPTgate1/a_191_n36#"
+merge "MPTgate1/a_191_n36#" "li_1786_n83#"
+merge "li_1786_n83#" "MPTgate1/a_15_n36#"
+merge "MPTgate1/a_15_n36#" "4"
+merge "4" "li_1610_n92#"
+merge "MPfb/a_191_n36#" "MPfb/a_15_n36#" -156.17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3447 -538 0 0 3484 -524 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPfb/a_15_n36#" "MNfb/a_191_n163#"
+merge "MNfb/a_191_n163#" "MNfb/a_15_n163#"
+merge "MNfb/a_15_n163#" "MNinv1/a_n73_37#"
+merge "MNinv1/a_n73_37#" "2"
+merge "2" "MPinv1/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#" -815.557 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -824 0 0 -10166 -938 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "Clkb_int"
+merge "Clkb_int" "a_n40_n319#"
+merge "MNbuf1/a_n73_n163#" "li_4326_n470#" -770.833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4258 -338 0 0 -8772 -856 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_4326_n470#" "MPbuf1/a_n73_n36#"
+merge "MPbuf1/a_n73_n36#" "MNbuf2/a_n73_37#"
+merge "MNbuf2/a_n73_37#" "7"
+merge "7" "MPbuf2/a_n15_n133#"
+merge "MPTgate2/a_279_n36#" "MPTgate2/a_103_n36#" -1024.39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24812 -1722 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate2/a_103_n36#" "MPTgate2/a_n73_n36#"
+merge "MPTgate2/a_n73_n36#" "li_2960_n126#"
+merge "li_2960_n126#" "MNTgate2/a_103_n163#"
+merge "MNTgate2/a_103_n163#" "MNTgate2/a_n73_n163#"
+merge "MNTgate2/a_n73_n163#" "MNTgate2/a_631_n163#"
+merge "MNTgate2/a_631_n163#" "MNTgate2/a_455_n163#"
+merge "MNTgate2/a_455_n163#" "MNTgate2/a_279_n163#"
+merge "MNTgate2/a_279_n163#" "li_2960_n667#"
+merge "li_2960_n667#" "MNinv2/a_15_n163#"
+merge "MNinv2/a_15_n163#" "MNinv2/a_191_n163#"
+merge "MNinv2/a_191_n163#" "MPinv2/a_191_n36#"
+merge "MPinv2/a_191_n36#" "MPinv2/a_15_n36#"
+merge "MPinv2/a_15_n36#" "5"
+merge "MNTgate1/a_103_n163#" "MNTgate1/a_n73_n163#" -1031 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18756 -1658 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n73_n163#" "MNTgate1/a_631_n163#"
+merge "MNTgate1/a_631_n163#" "MNTgate1/a_455_n163#"
+merge "MNTgate1/a_455_n163#" "MNTgate1/a_279_n163#"
+merge "MNTgate1/a_279_n163#" "li_1522_n667#"
+merge "li_1522_n667#" "MPTgate1/a_279_n36#"
+merge "MPTgate1/a_279_n36#" "MPTgate1/a_103_n36#"
+merge "MPTgate1/a_103_n36#" "MPTgate1/a_n73_n36#"
+merge "MPTgate1/a_n73_n36#" "li_1522_n126#"
+merge "li_1522_n126#" "MNinv1/a_15_n163#"
+merge "MNinv1/a_15_n163#" "MNinv1/a_191_n163#"
+merge "MNinv1/a_191_n163#" "MPinv1/a_191_n36#"
+merge "MPinv1/a_191_n36#" "MPinv1/a_15_n36#"
+merge "MPinv1/a_15_n36#" "3"
+merge "MNbuf1/a_n73_37#" "li_4329_n369#" -1322.52 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -960 -680 0 0 34535 -1884 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_4329_n369#" "MPbuf1/a_n15_n133#"
+merge "MPbuf1/a_n15_n133#" "MPfb/a_n15_n133#"
+merge "MPfb/a_n15_n133#" "MNfb/a_n73_37#"
+merge "MNfb/a_n73_37#" "MPTgate2/a_367_n36#"
+merge "MPTgate2/a_367_n36#" "MPTgate2/a_191_n36#"
+merge "MPTgate2/a_191_n36#" "li_3224_n83#"
+merge "li_3224_n83#" "MPTgate2/a_15_n36#"
+merge "MPTgate2/a_15_n36#" "li_3048_n92#"
+merge "li_3048_n92#" "MNTgate2/a_543_n163#"
+merge "MNTgate2/a_543_n163#" "MNTgate2/a_367_n163#"
+merge "MNTgate2/a_367_n163#" "MNTgate2/a_191_n163#"
+merge "MNTgate2/a_191_n163#" "MNTgate2/a_15_n163#"
+merge "MNTgate2/a_15_n163#" "6"
+merge "MPTgate2/a_n15_n81#" "MNTgate1/a_n15_n199#" -1799.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243049 -778 0 0 25906 -478 -22660 -2800 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n15_n199#" "MNClkin/a_n73_37#"
+merge "MNClkin/a_n73_37#" "MPClkin/a_n15_n133#"
+merge "MPClkin/a_n15_n133#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "Clk_in_buf"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" -491.152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4258 -338 0 0 -2244 -200 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "Clk_In"
+merge "MNbuf2/a_15_n163#" "MPbuf2/a_15_n36#" -172.671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_15_n36#" "Clk_Out"
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v4.mag b/mag/3-stage_cs-vco_dp9/old/FD_v4.mag
new file mode 100755
index 0000000..621feb5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v4.mag
@@ -0,0 +1,506 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647362795
+<< nwell >>
+rect -383 -58 4744 178
+rect -382 -313 4744 -58
+<< pwell >>
+rect -382 -769 4744 -313
+<< ndiff >>
+rect -112 -585 -98 -417
+rect 4460 -585 4474 -417
+<< pdiff >>
+rect -112 -263 -98 25
+rect 4460 -263 4474 25
+<< psubdiff >>
+rect -382 -748 -314 -714
+rect -27 -748 531 -714
+rect 4545 -748 4744 -714
+<< nsubdiff >>
+rect -346 107 -309 141
+rect 89 107 116 141
+rect 479 107 503 141
+rect 4661 107 4688 141
+<< psubdiffcont >>
+rect -314 -748 -27 -714
+rect 531 -748 4545 -714
+<< nsubdiffcont >>
+rect -309 107 89 141
+rect 503 107 4661 141
+<< poly >>
+rect 1413 52 1568 82
+rect 1950 52 2117 82
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+rect 2860 -669 2927 -645
+rect 3733 -645 3749 -630
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+<< polycont >>
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+rect 1438 -645 1472 -611
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+<< locali >>
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+rect 4662 -714 4696 -486
+rect -382 -748 -314 -714
+rect -27 -748 531 -714
+rect 4545 -748 4744 -714
+<< viali >>
+rect -270 107 89 141
+rect 503 107 4661 141
+rect -246 -147 -212 -113
+rect 556 17 590 51
+rect 1429 17 1463 51
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+rect 531 -748 4545 -714
+<< metal1 >>
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+rect 4320 -631 4366 -619
+rect 2847 -651 3795 -645
+rect 2853 -660 2899 -651
+rect -382 -714 4744 -702
+rect -382 -748 -289 -714
+rect -27 -748 531 -714
+rect 4545 -748 4744 -714
+rect -382 -760 4744 -748
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647276187
+transform 1 0 -25 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0
+timestamp 1647282796
+transform 1 0 -25 0 1 -227
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0
+timestamp 1647281419
+transform 1 0 -273 0 1 -422
+box -73 -199 161 103
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0
+timestamp 1647281041
+transform 1 0 -273 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin
+timestamp 1647279940
+transform 1 0 529 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin
+timestamp 1647276187
+transform 1 0 529 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1
+timestamp 1647279940
+transform 1 0 1045 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1
+timestamp 1647276187
+transform 1 0 1045 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1
+timestamp 1647282796
+transform 1 0 1583 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1
+timestamp 1647283104
+transform 1 0 1583 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2
+timestamp 1647279940
+transform 1 0 2477 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2
+timestamp 1647276187
+transform 1 0 2477 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2
+timestamp 1647283104
+transform 1 0 3021 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2
+timestamp 1647282796
+transform 1 0 3021 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb
+timestamp 1647276187
+transform 1 0 3904 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb
+timestamp 1647279940
+transform 1 0 3904 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2
+timestamp 1647281041
+transform 1 0 4547 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2
+timestamp 1647281419
+transform 1 0 4547 0 1 -422
+box -73 -199 161 103
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1
+timestamp 1647281016
+transform 1 0 4387 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1
+timestamp 1647281419
+transform 1 0 4387 0 1 -422
+box -73 -199 73 103
+<< labels >>
+rlabel metal1 -382 -369 -357 -335 1 Clk_In
+port 1 n
+rlabel metal1 -95 -364 -56 -332 1 Clkb_int
+rlabel metal1 132 -363 160 -340 1 Clk_in_buf
+rlabel metal1 184 -760 218 -702 1 GND
+port 3 n
+rlabel metal1 156 95 190 153 1 VDD
+port 2 n
+rlabel locali 1138 -335 1163 -311 1 3
+rlabel locali 1616 -321 1641 -297 1 4
+rlabel locali 2509 -323 2534 -299 1 5
+rlabel locali 3935 -321 3960 -297 1 2
+rlabel locali 3768 -430 3792 -404 1 6
+rlabel metal1 4424 -363 4449 -339 1 7
+rlabel metal1 4710 -368 4744 -334 1 Clk_Out
+port 4 n
+rlabel locali 560 -326 585 -298 1 Clkb
+<< properties >>
+string LEFsite unithddb1
+string LEFclass CORE
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v4.spice b/mag/3-stage_cs-vco_dp9/old/FD_v4.spice
new file mode 100755
index 0000000..b983b5b
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v4.spice
@@ -0,0 +1,81 @@
+* NGSPICE file created from FD_v4.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt FD_v4 Clk_In VDD GND Clk_Out
+XMNClkin_b1 li_n334_n619# Clk_In GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNClkin_b2 GND GND li_n334_n619# Clk_in_buf GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clkb GND Clk_in_buf Clkb GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clkb VDD VDD Clkb VDD Clk_in_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin_b1 VDD li_n334_n619# VDD Clk_In sky130_fd_pr__pfet_01v8_A9DS5R
+XMPClkin_b2 Clk_in_buf VDD VDD VDD li_n334_n619# sky130_fd_pr__pfet_01v8_A1DS5R
+XMPTgate1 3 4 3 4 Clkb 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMPTgate2 5 6 5 6 Clk_in_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_in_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v4_no_1st_buf.ext b/mag/3-stage_cs-vco_dp9/old/FD_v4_no_1st_buf.ext
new file mode 100755
index 0000000..7d9650b
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v4_no_1st_buf.ext
@@ -0,0 +1,351 @@
+timestamp 1647358846
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin 1 0 177 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin 1 0 177 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1 1 0 693 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1 1 0 693 0 1 -422
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1 1 0 1231 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1 1 0 1231 0 -1 -580
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2 1 0 2125 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2 1 0 2125 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2 1 0 2669 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2 1 0 2669 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb 1 0 3552 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb 1 0 3552 0 1 -227
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2 1 0 4195 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1 1 0 4035 0 1 -422
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1 1 0 4035 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2 1 0 4195 0 1 -422
+port "Clk_Out" 4 4358 -368 4392 -334 m1
+port "Clk_In" 1 -382 -369 -357 -335 m1
+port "VDD" 2 68 95 102 153 m1
+port "GND" 3 96 -760 130 -702 m1
+node "li_3974_n470#" 12 61.4277 3974 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2608_n667#" 354 1378.44 2608 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1170_n667#" 354 1376.53 1170 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3977_n369#" 12 60.0815 3977 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4310_n270#" 22 5.19444 4310 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 49 278.477 4358 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 7088 468 0 0 0 0 0 0 0 0 0 0
+node "5" 363 480.387 2152 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34442 2094 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 217 2591.72 636 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17204 1148 138368 6108 0 0 0 0 0 0 0 0 0 0
+node "3" 350 477.852 720 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33150 2018 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb" 164 322.461 204 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15504 980 0 0 0 0 0 0 0 0 0 0 0 0
+node "6" 713 1903.73 2696 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64496 3944 21652 1290 0 0 0 0 0 0 0 0 0 0
+node "4" 571 948.077 1258 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53582 3234 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2608_n126#" 122 -1.64 2608 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_1170_n126#" 122 -1.64 1170 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_2872_n83#" 15 0 2872 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2696_n92#" 31 0 2696 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1434_n83#" 15 0 1434 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1258_n92#" 31 0 1258 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "7" 190 869.952 3974 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8296 760 31936 1828 0 0 0 0 0 0 0 0 0 0
+node "a_2508_n669#" 678 4356.3 2508 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14984 892 0 0 5644 536 158792 6996 0 0 0 0 0 0 0 0 0 0
+node "a_4108_n585#" 1440 0 4108 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4108_n263#" 4053 0 4108 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 1486 4044.58 -382 -369 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31376 1860 0 0 10132 936 278701 12436 0 0 0 0 0 0 0 0 0 0
+node "a_1061_1#" 722 -180.421 1061 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 968 0 0 5644 536 72634 3250 0 0 0 0 0 0 0 0 0 0
+node "VDD" 35195 6930.42 68 95 m1 0 0 0 0 2344034 10530 0 0 155822 9302 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 212058 12542 276892 9664 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 96 -760 m1 2176944 10460 0 0 0 0 0 0 0 0 162316 9616 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 250376 14796 276892 9664 0 0 0 0 0 0 0 0 0 0
+cap "6" "li_2696_n92#" 23.2941
+cap "3" "2" 331.614
+cap "2" "li_1170_n126#" 90.9805
+cap "li_1170_n667#" "Clk_In" 602.691
+cap "3" "VDD" 238.741
+cap "li_2608_n667#" "a_2508_n669#" 602.691
+cap "3" "Clk_In" 129.801
+cap "3" "a_2508_n669#" 20.449
+cap "li_1170_n126#" "VDD" 410.223
+cap "li_1170_n126#" "Clk_In" 170.315
+cap "a_1061_1#" "4" 3.33929
+cap "li_1170_n126#" "a_2508_n669#" 62.7219
+cap "7" "li_3974_n470#" 181.929
+cap "6" "li_3974_n470#" 29.5263
+cap "Clk_Out" "7" 92.3198
+cap "6" "5" 171.334
+cap "6" "Clk_Out" 8.23846
+cap "li_1170_n126#" "li_1258_n92#" 1.88
+cap "6" "7" 146.867
+cap "li_1170_n667#" "4" 88.9945
+cap "3" "4" 170.035
+cap "li_1170_n126#" "4" 12.6168
+cap "VDD" "li_4310_n270#" 45.9225
+cap "2" "VDD" 92.652
+cap "2" "Clk_In" 2205.51
+cap "2" "a_2508_n669#" 2147.27
+cap "VDD" "Clk_In" 3111.69
+cap "a_1061_1#" "Clkb" 3.9507
+cap "VDD" "li_2872_n83#" 39.5697
+cap "Clk_In" "a_2508_n669#" 1434.45
+cap "2" "li_3977_n369#" 5.96809
+cap "5" "li_2608_n667#" 6.03226
+cap "VDD" "li_1258_n92#" 43.293
+cap "2" "li_2608_n126#" 90.9805
+cap "6" "li_2608_n667#" 88.9945
+cap "2" "4" 415.856
+cap "li_2608_n126#" "VDD" 410.223
+cap "li_2608_n126#" "Clk_In" 235.31
+cap "3" "Clkb" 16.3922
+cap "VDD" "4" 275.264
+cap "Clk_In" "4" 130.852
+cap "VDD" "li_2696_n92#" 43.293
+cap "li_2696_n92#" "li_2872_n83#" 9.52817
+cap "li_1258_n92#" "4" 23.2941
+cap "3" "a_1061_1#" 3.69079
+cap "li_1434_n83#" "VDD" 39.5697
+cap "a_1061_1#" "li_1170_n126#" 182.29
+cap "Clk_Out" "li_4310_n270#" 1.83333
+cap "7" "li_4310_n270#" 3.71523
+cap "li_2608_n126#" "li_2696_n92#" 1.88
+cap "2" "5" 307.459
+cap "2" "7" 12.3056
+cap "3" "li_1170_n667#" 6.03226
+cap "5" "VDD" 254.495
+cap "Clk_Out" "VDD" 30.2767
+cap "6" "2" 578.272
+cap "5" "Clk_In" 84.9256
+cap "li_1434_n83#" "li_1258_n92#" 9.52817
+cap "VDD" "7" 269.598
+cap "5" "a_2508_n669#" 28.3979
+cap "2" "Clkb" 5.13697
+cap "6" "VDD" 275.264
+cap "3" "li_1170_n126#" 14.7632
+cap "6" "Clk_In" 3.33929
+cap "VDD" "Clkb" 70.9841
+cap "6" "a_2508_n669#" 35.6561
+cap "li_3977_n369#" "li_3974_n470#" 15.2687
+cap "Clkb" "Clk_In" 98.1656
+cap "li_1434_n83#" "4" 22
+cap "6" "li_2872_n83#" 22
+cap "Clk_Out" "li_3977_n369#" 5.31754
+cap "Clkb" "a_2508_n669#" 72.3786
+cap "li_3977_n369#" "7" 61.6231
+cap "6" "li_3977_n369#" 74.8
+cap "2" "a_1061_1#" 151.544
+cap "5" "li_2608_n126#" 14.7632
+cap "5" "4" 18.9494
+cap "a_1061_1#" "VDD" 3285.37
+cap "a_1061_1#" "Clk_In" 286.772
+cap "6" "li_2608_n126#" 12.6168
+cap "MPinv1/a_15_n36#" "MPTgate1/a_15_n36#" 22.0335
+cap "MPClkin/a_n15_n133#" "MPinv1/a_n15_n133#" 176.492
+cap "MPTgate1/a_15_n36#" "MPClkin/w_n109_n86#" 21.175
+cap "MPinv1/a_n15_n133#" "MPinv1/a_15_n36#" 187.723
+cap "MPinv1/a_n15_n133#" "MPClkin/w_n109_n86#" 13.7802
+cap "MPinv1/a_n15_n133#" "MNClkin/a_n73_n163#" 639.615
+cap "MPClkin/a_n15_n133#" "MPinv1/a_15_n36#" 24.6224
+cap "MPinv1/a_n15_n133#" "MPClkin/a_191_n36#" 119.117
+cap "MPClkin/a_n15_n133#" "MPClkin/w_n109_n86#" 251.241
+cap "MPinv1/a_15_n36#" "MPClkin/w_n109_n86#" 169.657
+cap "MPClkin/a_n15_n133#" "MNClkin/a_n73_n163#" 685.832
+cap "MPinv1/a_15_n36#" "MNClkin/a_n73_n163#" 133.676
+cap "MPClkin/a_n15_n133#" "MPClkin/a_191_n36#" 295.467
+cap "MNClkin/a_n73_n163#" "MPClkin/w_n109_n86#" 33
+cap "MPinv1/a_15_n36#" "MPClkin/a_191_n36#" 237.953
+cap "MPClkin/a_191_n36#" "MPClkin/w_n109_n86#" 130.434
+cap "MPClkin/a_191_n36#" "MNClkin/a_n73_n163#" 66.5386
+cap "MNTgate1/a_n15_n199#" "MPinv1/a_15_n36#" 79.491
+cap "MNinv2/a_191_n163#" "MPTgate1/a_15_n36#" 218.748
+cap "MPinv1/a_15_n36#" "MPinv1/a_103_n36#" -38.2086
+cap "MPinv1/a_n15_n133#" "MPinv1/a_15_n36#" 0.00457
+cap "MPTgate2/a_n15_n81#" "MPinv1/a_103_n36#" -326.1
+cap "MNinv1/a_n73_n163#" "MPinv1/a_15_n36#" 396.954
+cap "MPinv1/a_15_n36#" "MPTgate1/a_n15_n81#" 250.937
+cap "MPinv1/a_15_n36#" "MPTgate1/a_15_n36#" 329.433
+cap "MNinv2/a_191_n163#" "MNTgate2/a_n15_n199#" 109.781
+cap "MNTgate2/a_15_n163#" "MPinv1/a_103_n36#" 18.2806
+cap "MPTgate2/a_n15_n81#" "MPTgate1/a_n15_n81#" 77.0187
+cap "MPTgate2/a_n15_n81#" "MPTgate1/a_15_n36#" 121.813
+cap "MPinv1/a_n15_n133#" "MNTgate1/a_n15_n199#" 5.56243
+cap "MNinv1/a_n73_n163#" "MPinv1/a_103_n36#" 16.5
+cap "MNinv1/a_n73_n163#" "MNTgate1/a_n15_n199#" 1089.83
+cap "MNinv1/a_n73_n163#" "MPinv1/a_n15_n133#" -74.5699
+cap "MNTgate2/a_n15_n199#" "MPinv1/a_15_n36#" 325.575
+cap "MNTgate1/a_n15_n199#" "MPTgate1/a_n15_n81#" 33.715
+cap "MPinv1/a_103_n36#" "MPTgate1/a_n15_n81#" -401.691
+cap "MNTgate1/a_n15_n199#" "MPTgate1/a_15_n36#" 24.0588
+cap "MPinv1/a_103_n36#" "MPTgate1/a_15_n36#" -213.549
+cap "MPinv1/a_n15_n133#" "MPTgate1/a_n15_n81#" 10.2836
+cap "MPinv1/a_n15_n133#" "MPTgate1/a_15_n36#" 188.843
+cap "MNinv2/a_191_n163#" "MPinv1/a_15_n36#" 26.5082
+cap "MNinv1/a_n73_n163#" "MPTgate1/a_15_n36#" 1137.4
+cap "MNinv2/a_191_n163#" "MPTgate2/a_n15_n81#" 29.0463
+cap "MPTgate1/a_n15_n81#" "MPTgate1/a_15_n36#" 167.779
+cap "MNTgate2/a_n15_n199#" "MNTgate1/a_n15_n199#" 125.22
+cap "MNinv2/a_191_n163#" "MNTgate2/a_15_n163#" 20.8473
+cap "MNinv1/a_n73_n163#" "MNTgate2/a_n15_n199#" -339.431
+cap "MPTgate2/a_n15_n81#" "MPinv1/a_15_n36#" 85.3142
+cap "MNinv2/a_191_n163#" "MPinv1/a_103_n36#" 26.295
+cap "MNTgate2/a_n15_n199#" "MPTgate1/a_15_n36#" 312.855
+cap "MNinv1/a_n73_n163#" "MNinv2/a_191_n163#" 117.666
+cap "MNinv2/a_n73_n163#" "MPinv2/w_n109_n86#" 16.5
+cap "MNTgate2/a_n15_n199#" "MNinv2/a_191_n163#" 79.491
+cap "MNTgate2/a_15_n163#" "MPinv2/w_n109_n86#" -193.407
+cap "MNinv2/a_n73_n163#" "MNTgate2/a_n15_n199#" 1089.83
+cap "MPinv2/w_n109_n86#" "MNbuf1/a_n73_n163#" 17.8901
+cap "MNfb/a_15_n163#" "MNinv2/a_191_n163#" 27.7597
+cap "MNTgate2/a_15_n163#" "MNTgate2/a_n15_n199#" 25.6357
+cap "MNinv2/a_n73_n163#" "MNfb/a_15_n163#" 100.332
+cap "MNinv2/a_n73_n163#" "MNinv2/a_191_n163#" 400.663
+cap "MNinv2/a_n73_37#" "MNTgate2/a_n15_n199#" 5.43729
+cap "MPinv2/w_n109_n86#" "MPTgate2/a_n15_n81#" -406.516
+cap "MNTgate2/a_15_n163#" "MNfb/a_15_n163#" 476.441
+cap "MNTgate2/a_15_n163#" "MNinv2/a_191_n163#" 392.52
+cap "MNfb/a_15_n163#" "MNbuf1/a_n73_n163#" 64.8918
+cap "MNinv2/a_n73_37#" "MNinv2/a_191_n163#" 0.0188398
+cap "MNTgate2/a_15_n163#" "MNinv2/a_n73_n163#" 1137.48
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_n15_n199#" 33.715
+cap "MNinv2/a_n73_n163#" "MNbuf1/a_n73_n163#" 5.92308
+cap "MPTgate2/a_n15_n81#" "MNinv2/a_191_n163#" 250.788
+cap "MNTgate2/a_15_n163#" "MNbuf1/a_n73_n163#" 5.24831
+cap "MNTgate2/a_15_n163#" "MPTgate2/a_n15_n81#" 167.832
+cap "MPTgate2/a_n15_n81#" "MNinv2/a_n73_37#" 9.91076
+cap "MPinv2/w_n109_n86#" "MNfb/a_15_n163#" 14.057
+cap "MPinv2/w_n109_n86#" "MNinv2/a_191_n163#" 32.7548
+cap "MNfb/a_15_n163#" "MNfb/a_n73_n163#" 21.2201
+cap "MNbuf1/a_n73_n163#" "MPfb/w_n109_n86#" 173.83
+cap "MNfb/a_n73_37#" "MNfb/a_n73_n163#" 115.944
+cap "MNfb/a_15_n163#" "MNbuf1/a_n73_n163#" 64.8918
+cap "MNfb/a_15_n163#" "MPfb/w_n109_n86#" 32.0466
+cap "MNfb/a_n73_37#" "MNbuf1/a_n73_n163#" 139.709
+cap "MPbuf2/a_15_n36#" "MNfb/a_n73_n163#" 83.329
+cap "MNfb/a_15_n163#" "MNfb/a_n73_37#" 18.7488
+cap "MPbuf2/a_15_n36#" "MPfb/w_n109_n86#" 103.281
+cap "MPbuf2/a_15_n36#" "MNbuf1/a_n73_n163#" 197.383
+cap "MPbuf2/a_15_n36#" "MNfb/a_n73_37#" 8.49674
+cap "MPfb/w_n109_n86#" "MNfb/a_n73_n163#" 19.7416
+cap "MNbuf1/a_n73_n163#" "MNfb/a_n73_n163#" 168.791
+merge "MPbuf2/a_103_n36#" "li_4310_n270#" -3536.52 0 0 0 0 -1188000 -13584 0 0 0 0 171072 -1152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16572 -1668 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_4310_n270#" "MPbuf1/a_15_n36#"
+merge "MPbuf1/a_15_n36#" "MPbuf1/w_n109_n86#"
+merge "MPbuf1/w_n109_n86#" "MPbuf2/a_n73_n36#"
+merge "MPbuf2/a_n73_n36#" "a_4108_n263#"
+merge "a_4108_n263#" "MPbuf2/w_n109_n86#"
+merge "MPbuf2/w_n109_n86#" "MPfb/a_279_n36#"
+merge "MPfb/a_279_n36#" "MPfb/a_103_n36#"
+merge "MPfb/a_103_n36#" "MPfb/a_n73_n36#"
+merge "MPfb/a_n73_n36#" "MPfb/w_n109_n86#"
+merge "MPfb/w_n109_n86#" "MPTgate2/w_n109_n86#"
+merge "MPTgate2/w_n109_n86#" "MPinv2/a_279_n36#"
+merge "MPinv2/a_279_n36#" "MPinv2/a_103_n36#"
+merge "MPinv2/a_103_n36#" "MPinv2/a_n73_n36#"
+merge "MPinv2/a_n73_n36#" "MPinv2/w_n109_n86#"
+merge "MPinv2/w_n109_n86#" "MPTgate1/w_n109_n86#"
+merge "MPTgate1/w_n109_n86#" "MPinv1/a_n73_n36#"
+merge "MPinv1/a_n73_n36#" "MPinv1/a_279_n36#"
+merge "MPinv1/a_279_n36#" "MPinv1/a_103_n36#"
+merge "MPinv1/a_103_n36#" "MPinv1/w_n109_n86#"
+merge "MPinv1/w_n109_n86#" "MPClkin/a_279_n36#"
+merge "MPClkin/a_279_n36#" "MPClkin/a_103_n36#"
+merge "MPClkin/a_103_n36#" "MPClkin/a_n73_n36#"
+merge "MPClkin/a_n73_n36#" "MPClkin/w_n109_n86#"
+merge "MPClkin/w_n109_n86#" "VDD"
+merge "MPinv2/a_n15_n133#" "MNinv2/a_n73_37#" -910.682 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2160 -538 0 0 41522 -1688 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNinv2/a_n73_37#" "MNTgate1/a_543_n163#"
+merge "MNTgate1/a_543_n163#" "MNTgate1/a_367_n163#"
+merge "MNTgate1/a_367_n163#" "MNTgate1/a_191_n163#"
+merge "MNTgate1/a_191_n163#" "MPTgate1/a_367_n36#"
+merge "MPTgate1/a_367_n36#" "MPTgate1/a_191_n36#"
+merge "MPTgate1/a_191_n36#" "li_1434_n83#"
+merge "li_1434_n83#" "MNTgate1/a_15_n163#"
+merge "MNTgate1/a_15_n163#" "MPTgate1/a_15_n36#"
+merge "MPTgate1/a_15_n36#" "4"
+merge "4" "li_1258_n92#"
+merge "MPfb/a_191_n36#" "MPfb/a_15_n36#" -1129.15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4176 -538 0 0 20594 -524 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPfb/a_15_n36#" "MNfb/a_191_n163#"
+merge "MNfb/a_191_n163#" "MNfb/a_15_n163#"
+merge "MNfb/a_15_n163#" "MNinv1/a_n73_37#"
+merge "MNinv1/a_n73_37#" "2"
+merge "2" "MPinv1/a_n15_n133#"
+merge "MPTgate2/a_279_n36#" "MNTgate2/a_631_n163#" -1014.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35944 -1722 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate2/a_631_n163#" "MNTgate2/a_455_n163#"
+merge "MNTgate2/a_455_n163#" "MNTgate2/a_279_n163#"
+merge "MNTgate2/a_279_n163#" "MPTgate2/a_103_n36#"
+merge "MPTgate2/a_103_n36#" "MPTgate2/a_n73_n36#"
+merge "MPTgate2/a_n73_n36#" "li_2608_n126#"
+merge "li_2608_n126#" "MNTgate2/a_103_n163#"
+merge "MNTgate2/a_103_n163#" "MNTgate2/a_n73_n163#"
+merge "MNTgate2/a_n73_n163#" "li_2608_n667#"
+merge "li_2608_n667#" "MPinv2/a_191_n36#"
+merge "MPinv2/a_191_n36#" "MPinv2/a_15_n36#"
+merge "MPinv2/a_15_n36#" "MNinv2/a_15_n163#"
+merge "MNinv2/a_15_n163#" "MNinv2/a_191_n163#"
+merge "MNinv2/a_191_n163#" "5"
+merge "MNbuf2/a_103_n163#" "MNbuf2/VSUBS" -844.06 0 0 0 0 0 0 0 0 99792 -672 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 178818 -3134 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf2/VSUBS" "MNbuf2/a_n73_n163#"
+merge "MNbuf2/a_n73_n163#" "MPbuf1/VSUBS"
+merge "MPbuf1/VSUBS" "MNbuf1/VSUBS"
+merge "MNbuf1/VSUBS" "MNbuf1/a_15_n163#"
+merge "MNbuf1/a_15_n163#" "a_4108_n585#"
+merge "a_4108_n585#" "MPbuf2/VSUBS"
+merge "MPbuf2/VSUBS" "MPfb/VSUBS"
+merge "MPfb/VSUBS" "MNfb/VSUBS"
+merge "MNfb/VSUBS" "MNfb/a_103_n163#"
+merge "MNfb/a_103_n163#" "MNfb/a_n73_n163#"
+merge "MNfb/a_n73_n163#" "MPTgate2/VSUBS"
+merge "MPTgate2/VSUBS" "MNTgate2/VSUBS"
+merge "MNTgate2/VSUBS" "MPinv2/VSUBS"
+merge "MPinv2/VSUBS" "MNinv2/VSUBS"
+merge "MNinv2/VSUBS" "MNinv2/a_103_n163#"
+merge "MNinv2/a_103_n163#" "MNinv2/a_n73_n163#"
+merge "MNinv2/a_n73_n163#" "MNTgate1/VSUBS"
+merge "MNTgate1/VSUBS" "MPTgate1/VSUBS"
+merge "MPTgate1/VSUBS" "MNinv1/VSUBS"
+merge "MNinv1/VSUBS" "MNinv1/a_103_n163#"
+merge "MNinv1/a_103_n163#" "MNinv1/a_n73_n163#"
+merge "MNinv1/a_n73_n163#" "MPinv1/VSUBS"
+merge "MPinv1/VSUBS" "MNClkin/VSUBS"
+merge "MNClkin/VSUBS" "MNClkin/a_103_n163#"
+merge "MNClkin/a_103_n163#" "MNClkin/a_n73_n163#"
+merge "MNClkin/a_n73_n163#" "MPClkin/VSUBS"
+merge "MPClkin/VSUBS" "GND"
+merge "MNbuf2/a_n73_37#" "MPbuf2/a_n15_n133#" -689.114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10584 -338 0 0 37052 -856 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_n15_n133#" "MPbuf1/a_n73_n36#"
+merge "MPbuf1/a_n73_n36#" "MNbuf1/a_n73_n163#"
+merge "MNbuf1/a_n73_n163#" "7"
+merge "7" "li_3974_n470#"
+merge "MNTgate1/a_631_n163#" "MNTgate1/a_455_n163#" -1019.71 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30966 -1658 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_455_n163#" "MNTgate1/a_279_n163#"
+merge "MNTgate1/a_279_n163#" "MPTgate1/a_279_n36#"
+merge "MPTgate1/a_279_n36#" "MNTgate1/a_103_n163#"
+merge "MNTgate1/a_103_n163#" "MNTgate1/a_n73_n163#"
+merge "MNTgate1/a_n73_n163#" "li_1170_n667#"
+merge "li_1170_n667#" "MPTgate1/a_103_n36#"
+merge "MPTgate1/a_103_n36#" "MPTgate1/a_n73_n36#"
+merge "MPTgate1/a_n73_n36#" "li_1170_n126#"
+merge "li_1170_n126#" "MNinv1/a_15_n163#"
+merge "MNinv1/a_15_n163#" "MNinv1/a_191_n163#"
+merge "MNinv1/a_191_n163#" "MPinv1/a_191_n36#"
+merge "MPinv1/a_191_n36#" "MPinv1/a_15_n36#"
+merge "MPinv1/a_15_n36#" "3"
+merge "MPbuf1/a_n15_n133#" "MNbuf1/a_n73_37#" -1048.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7511 -680 0 0 57280 -1884 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf1/a_n73_37#" "li_3977_n369#"
+merge "li_3977_n369#" "MPfb/a_n15_n133#"
+merge "MPfb/a_n15_n133#" "MNfb/a_n73_37#"
+merge "MNfb/a_n73_37#" "MPTgate2/a_367_n36#"
+merge "MPTgate2/a_367_n36#" "MPTgate2/a_191_n36#"
+merge "MPTgate2/a_191_n36#" "li_2872_n83#"
+merge "li_2872_n83#" "MNTgate2/a_543_n163#"
+merge "MNTgate2/a_543_n163#" "MNTgate2/a_367_n163#"
+merge "MNTgate2/a_367_n163#" "MNTgate2/a_191_n163#"
+merge "MNTgate2/a_191_n163#" "MPTgate2/a_15_n36#"
+merge "MPTgate2/a_15_n36#" "li_2696_n92#"
+merge "li_2696_n92#" "MNTgate2/a_15_n163#"
+merge "MNTgate2/a_15_n163#" "6"
+merge "MPTgate2/a_n15_n81#" "MNTgate1/a_n15_n199#" -1619.68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5850 -778 0 0 -1156 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n15_n199#" "MNClkin/a_n73_37#"
+merge "MNClkin/a_n73_37#" "Clk_In"
+merge "Clk_In" "MPClkin/a_n15_n133#"
+merge "MNTgate2/a_n15_n199#" "MPTgate1/a_n15_n81#" -1948.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54298 -240 0 0 22780 -584 30408 0 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate1/a_n15_n81#" "MNClkin/a_15_n163#"
+merge "MNClkin/a_15_n163#" "a_2508_n669#"
+merge "a_2508_n669#" "MNClkin/a_191_n163#"
+merge "MNClkin/a_191_n163#" "MPClkin/a_15_n36#"
+merge "MPClkin/a_15_n36#" "a_1061_1#"
+merge "a_1061_1#" "MPClkin/a_191_n36#"
+merge "MPClkin/a_191_n36#" "Clkb"
+merge "MNbuf2/a_15_n163#" "MPbuf2/a_15_n36#" -172.671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_15_n36#" "Clk_Out"
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v4_no_1st_buf.mag b/mag/3-stage_cs-vco_dp9/old/FD_v4_no_1st_buf.mag
new file mode 100755
index 0000000..cbe1334
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v4_no_1st_buf.mag
@@ -0,0 +1,430 @@
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+rect 3968 -33 4014 -21
+rect 2602 -92 2648 -80
+rect 2772 -92 2830 -86
+rect 2948 -92 3006 -86
+rect 2602 -126 2608 -92
+rect 2642 -126 2784 -92
+rect 2818 -126 2960 -92
+rect 2994 -126 3006 -92
+rect 2602 -138 2648 -126
+rect 2772 -132 2830 -126
+rect 2948 -132 3006 -126
+rect 3974 -216 4008 -33
+rect 113 -282 2549 -236
+rect 3968 -228 4014 -216
+rect 3968 -262 3974 -228
+rect 4008 -262 4014 -228
+rect 3968 -274 4014 -262
+rect -336 -335 -290 -323
+rect 113 -329 159 -282
+rect 55 -334 206 -329
+rect 22 -335 206 -334
+rect -382 -369 120 -335
+rect 154 -369 206 -335
+rect -336 -381 -290 -369
+rect 55 -375 206 -369
+rect 620 -335 3628 -329
+rect 620 -369 636 -335
+rect 670 -369 3582 -335
+rect 3616 -369 3628 -335
+rect 620 -375 3628 -369
+rect 3974 -335 4008 -274
+rect 4126 -335 4184 -329
+rect 3974 -369 4138 -335
+rect 4172 -369 4184 -335
+rect 113 -605 159 -375
+rect 192 -425 2547 -419
+rect 192 -459 204 -425
+rect 238 -459 2547 -425
+rect 3896 -433 3942 -421
+rect 192 -465 2547 -459
+rect 2501 -605 2547 -465
+rect 3400 -470 3456 -458
+rect 3896 -467 3902 -433
+rect 3936 -467 3942 -433
+rect 3896 -470 3942 -467
+rect 3400 -504 3412 -470
+rect 3446 -479 3942 -470
+rect 3446 -504 3936 -479
+rect 3974 -501 4008 -369
+rect 4126 -375 4184 -369
+rect 4216 -334 4262 -322
+rect 4216 -368 4222 -334
+rect 4256 -368 4392 -334
+rect 4216 -380 4262 -368
+rect 3400 -512 3456 -504
+rect 3968 -585 4014 -501
+rect 113 -611 2005 -605
+rect 113 -645 1086 -611
+rect 1120 -645 1959 -611
+rect 1993 -645 2005 -611
+rect 113 -651 2005 -645
+rect 2495 -611 3443 -605
+rect 2495 -645 2524 -611
+rect 2558 -645 3397 -611
+rect 3431 -645 3443 -611
+rect 3968 -619 3974 -585
+rect 4008 -619 4014 -585
+rect 3968 -631 4014 -619
+rect 2495 -651 3443 -645
+rect 2501 -660 2547 -651
+rect -382 -714 4392 -702
+rect -382 -748 -289 -714
+rect -115 -748 179 -714
+rect 4193 -748 4392 -714
+rect -382 -760 4392 -748
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin
+timestamp 1647279940
+transform 1 0 177 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin
+timestamp 1647276187
+transform 1 0 177 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1
+timestamp 1647279940
+transform 1 0 693 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1
+timestamp 1647276187
+transform 1 0 693 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1
+timestamp 1647282796
+transform 1 0 1231 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1
+timestamp 1647283104
+transform 1 0 1231 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2
+timestamp 1647276187
+transform 1 0 2125 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2
+timestamp 1647279940
+transform 1 0 2125 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2
+timestamp 1647283104
+transform 1 0 2669 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2
+timestamp 1647282796
+transform 1 0 2669 0 -1 1
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb
+timestamp 1647276187
+transform 1 0 3552 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb
+timestamp 1647279940
+transform 1 0 3552 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2
+timestamp 1647281041
+transform 1 0 4195 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1
+timestamp 1647281419
+transform 1 0 4035 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1
+timestamp 1647281016
+transform 1 0 4035 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2
+timestamp 1647281419
+transform 1 0 4195 0 1 -422
+box -73 -199 161 103
+<< labels >>
+rlabel locali 208 -326 233 -298 1 Clkb
+rlabel metal1 68 95 102 153 1 VDD
+port 2 n
+rlabel metal1 96 -760 130 -702 1 GND
+port 3 n
+rlabel locali 786 -335 811 -311 1 3
+rlabel locali 1264 -321 1289 -297 1 4
+rlabel locali 2157 -323 2182 -299 1 5
+rlabel locali 3583 -321 3608 -297 1 2
+rlabel locali 3416 -430 3440 -404 1 6
+rlabel metal1 4072 -363 4097 -339 1 7
+rlabel metal1 4358 -368 4392 -334 1 Clk_Out
+port 4 n
+rlabel metal1 -382 -369 -357 -335 1 Clk_In
+port 1 n
+<< properties >>
+string LEFsite unithddb1
+string LEFclass CORE
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v5_lasttry.ext b/mag/3-stage_cs-vco_dp9/old/FD_v5_lasttry.ext
new file mode 100755
index 0000000..21d57fd
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v5_lasttry.ext
@@ -0,0 +1,463 @@
+timestamp 1647369436
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0 1 0 -25 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0 1 0 -273 0 1 -422
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0 1 0 -273 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0 1 0 -25 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW4BNL sky130_fd_pr__nfet_01v8_PW4BNL_0 1 0 562 0 1 -422
+use sky130_fd_pr__pfet_01v8_A4DS5R sky130_fd_pr__pfet_01v8_A4DS5R_0 1 0 562 0 1 -227
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin 1 0 1329 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin 1 0 1329 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1 1 0 1845 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1 1 0 1845 0 1 -227
+use sky130_fd_pr__pfet_01v8_B2DS5R sky130_fd_pr__pfet_01v8_B2DS5R_0 1 0 2383 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1 1 0 2383 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2 1 0 3277 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2 1 0 3277 0 1 -422
+use sky130_fd_pr__pfet_01v8_B2DS5R sky130_fd_pr__pfet_01v8_B2DS5R_1 1 0 3821 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2 1 0 3821 0 -1 -580
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb 1 0 4704 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb 1 0 4704 0 1 -227
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1 1 0 5187 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1 1 0 5187 0 1 -422
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2 1 0 5347 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2 1 0 5347 0 1 -422
+port "Clk_Out" 4 5510 -368 5544 -334 m1
+port "Clk_In" 1 -382 -369 -357 -335 m1
+port "VDD" 2 156 95 190 153 m1
+port "GND" 3 184 -760 218 -702 m1
+node "li_5126_n470#" 12 61.4277 5126 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3760_n667#" 354 1378.44 3760 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2322_n667#" 354 1376.53 2322 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5129_n369#" 12 60.0815 5129 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5462_n270#" 22 5.19444 5462 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 49 278.477 5510 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 7088 468 0 0 0 0 0 0 0 0 0 0
+node "5" 363 480.387 3304 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34442 2094 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 217 2563.58 1788 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17204 1148 138368 6108 0 0 0 0 0 0 0 0 0 0
+node "3" 350 477.852 1872 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33150 2018 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In_buf" 164 322.461 1356 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15504 980 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 50 379.31 -382 -369 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 7224 476 0 0 0 0 0 0 0 0 0 0
+node "6" 794 1930.99 3848 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 72214 4398 21652 1290 0 0 0 0 0 0 0 0 0 0
+node "4" 652 975.336 2410 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61300 3688 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3760_n126#" 172 -1.64 3760 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 544 22912 1348 0 0 0 0 0 0 0 0 0 0
+node "li_2322_n126#" 172 -1.64 2322 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 544 22878 1346 0 0 0 0 0 0 0 0 0 0
+node "li_4024_n83#" 15 0 4024 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3848_n92#" 31 0 3848 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2586_n83#" 15 0 2586 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2410_n92#" 31 0 2410 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_90_n270#" 22 5.19444 90 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "dus" 225 912.175 2 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26540 1472 27052 1224 0 0 0 0 0 0 0 0 0 0
+node "7" 190 869.952 5126 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8296 760 31936 1828 0 0 0 0 0 0 0 0 0 0
+node "li_1356_17#" 12 0 1356 17 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb_int" 247 1007.53 -246 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10846 978 33290 1872 0 0 0 0 0 0 0 0 0 0
+node "a_2222_n669#" 682 3552.17 2222 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14984 892 0 0 6732 600 88919 3942 0 0 0 0 0 0 0 0 0 0
+node "a_5260_n585#" 1440 0 5260 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n585#" 1440 0 -112 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n40_n319#" 903 125.905 -40 -319 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2266 434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_5260_n263#" 4053 0 5260 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_3651_1#" 772 -272.671 3651 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 968 0 0 10812 840 169970 7482 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n263#" 4053 0 -112 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb_buf" 1825 5563.55 2213 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31016 1836 0 0 43860 2988 296713 12988 0 0 0 0 0 0 0 0 0 0
+node "VDD" 40269 8592.25 156 95 m1 0 0 0 0 2909902 12836 0 0 158814 9478 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 284716 16816 343766 11970 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 184 -760 m1 2702256 12764 0 0 0 0 0 0 0 0 201484 11920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 339320 20028 343708 11968 0 0 0 0 0 0 0 0 0 0
+cap "Clkb_buf" "li_2322_n126#" 350.099
+cap "Clk_In_buf" "a_2222_n669#" 10.6857
+cap "VDD" "li_1356_17#" 101.091
+cap "a_2222_n669#" "3" 7.94891
+cap "li_2322_n667#" "3" 6.03226
+cap "a_3651_1#" "4" 162.47
+cap "6" "li_3760_n126#" 17.9853
+cap "Clkb_buf" "4" 23.7883
+cap "dus" "a_n40_n319#" 15.0989
+cap "VDD" "Clk_Out" 30.2767
+cap "li_2322_n126#" "4" 17.9853
+cap "6" "li_4024_n83#" 22
+cap "VDD" "6" 365.909
+cap "VDD" "li_2586_n83#" 39.5697
+cap "dus" "li_90_n270#" 26.2851
+cap "7" "2" 12.3056
+cap "li_2410_n92#" "li_2586_n83#" 9.52817
+cap "5" "li_3760_n126#" 14.7632
+cap "6" "li_3760_n667#" 89.6163
+cap "VDD" "5" 254.495
+cap "li_3848_n92#" "li_3760_n126#" 1.88
+cap "VDD" "Clk_In" 5.1
+cap "VDD" "Clk_In_buf" 70.9841
+cap "li_3848_n92#" "li_4024_n83#" 9.52817
+cap "a_3651_1#" "li_1356_17#" 17
+cap "VDD" "3" 238.741
+cap "li_3848_n92#" "VDD" 43.293
+cap "5" "li_3760_n667#" 6.03226
+cap "VDD" "li_5462_n270#" 45.9225
+cap "6" "2" 597.987
+cap "Clkb_buf" "li_1356_17#" 27.0946
+cap "li_2322_n667#" "a_2222_n669#" 602.691
+cap "VDD" "a_n40_n319#" 59.4
+cap "5" "2" 307.459
+cap "6" "a_3651_1#" 3.33929
+cap "VDD" "li_90_n270#" 45.9225
+cap "6" "Clkb_buf" 35.6561
+cap "Clk_In_buf" "2" 5.13697
+cap "3" "2" 331.614
+cap "5" "a_3651_1#" 84.9256
+cap "5" "Clkb_buf" 28.3979
+cap "a_3651_1#" "Clk_In_buf" 87.5799
+cap "4" "li_2586_n83#" 22
+cap "a_3651_1#" "3" 121.852
+cap "Clk_In_buf" "Clkb_buf" 74.1789
+cap "dus" "VDD" 100.761
+cap "li_5129_n369#" "2" 5.96809
+cap "Clkb_buf" "3" 24.1398
+cap "Clkb_int" "Clk_In" 235.533
+cap "3" "li_2322_n126#" 14.7632
+cap "5" "4" 31.4735
+cap "3" "4" 170.035
+cap "Clk_Out" "7" 92.3198
+cap "6" "7" 146.867
+cap "li_5126_n470#" "7" 181.929
+cap "li_90_n270#" "Clkb_int" 5.79139
+cap "a_2222_n669#" "2" 270.978
+cap "VDD" "li_3760_n126#" 568.296
+cap "VDD" "li_4024_n83#" 39.5697
+cap "a_3651_1#" "a_2222_n669#" 259.483
+cap "Clk_Out" "6" 8.23846
+cap "VDD" "li_2410_n92#" 43.293
+cap "dus" "Clkb_buf" 97.1345
+cap "a_2222_n669#" "Clkb_buf" 653.464
+cap "li_5126_n470#" "6" 29.5263
+cap "li_5462_n270#" "7" 3.71523
+cap "Clk_In_buf" "li_1356_17#" 3.9507
+cap "dus" "Clkb_int" 96.2735
+cap "li_3760_n126#" "2" 130.387
+cap "6" "5" 171.334
+cap "a_2222_n669#" "4" 9
+cap "li_2322_n667#" "4" 89.6163
+cap "VDD" "2" 92.652
+cap "li_5129_n369#" "7" 61.6231
+cap "Clk_Out" "li_5462_n270#" 1.83333
+cap "li_3848_n92#" "6" 23.2941
+cap "a_3651_1#" "li_3760_n126#" 313.771
+cap "VDD" "a_3651_1#" 3557.37
+cap "VDD" "Clkb_buf" 3882
+cap "Clk_Out" "li_5129_n369#" 5.31754
+cap "Clkb_int" "a_n112_n585#" 7.0744
+cap "li_5129_n369#" "6" 74.8
+cap "VDD" "li_2322_n126#" 567.624
+cap "li_5129_n369#" "li_5126_n470#" 15.2687
+cap "Clk_In_buf" "3" 16.3922
+cap "VDD" "Clkb_int" 283.123
+cap "li_2322_n126#" "li_2410_n92#" 1.88
+cap "Clkb_buf" "li_3760_n667#" 602.691
+cap "VDD" "4" 365.909
+cap "a_3651_1#" "2" 1957.83
+cap "li_2410_n92#" "4" 23.2941
+cap "Clkb_buf" "2" 2319.73
+cap "li_2322_n126#" "2" 130.165
+cap "a_n112_n263#" "Clkb_int" 2.9155
+cap "a_3651_1#" "Clkb_buf" 1438.3
+cap "2" "4" 422.617
+cap "a_3651_1#" "li_2322_n126#" 243.275
+cap "dus" "Clk_In" 18.3829
+cap "VDD" "7" 269.598
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" 11.4
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 28.9026
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" 424.473
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" -10.7135
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" 284.368
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" 312.902
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" 168.807
+cap "MPClkin/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 21.3071
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" 133.413
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" 1144.89
+cap "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" 46.6931
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" 579.701
+cap "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 61.2575
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" 21.8807
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 9.12972
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" 17.1105
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" -203.463
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" -96.7025
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "MPClkin/a_15_n36#" 167.24
+cap "MNinv1/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 184.854
+cap "MNinv1/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 639.615
+cap "MNinv1/a_n73_37#" "MNinv1/a_191_n163#" 187.723
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MPClkin/a_15_n36#" 553.782
+cap "MPClkin/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" -1.63244
+cap "MNinv1/a_191_n163#" "MPClkin/a_15_n36#" 88.0797
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 33
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 464.624
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "MNinv1/a_191_n163#" 157.832
+cap "MPClkin/a_15_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" -5.438
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" 1.8255
+cap "MNinv1/a_n73_37#" "MPClkin/a_15_n36#" 125.631
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 620.603
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MNinv1/a_191_n163#" 338.419
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" 196.134
+cap "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "MNinv1/a_n73_37#" 13.7802
+cap "MPinv2/a_15_n36#" "MPinv1/a_279_n36#" 46.4484
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" 231.423
+cap "MPinv2/a_15_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" 3.83402
+cap "MPinv1/a_279_n36#" "MNinv2/a_n73_n163#" 16.5
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" 401.109
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "MNTgate2/a_n15_n199#" -126.853
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "MPinv2/a_15_n36#" 242.404
+cap "MPinv2/a_15_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" -2.92226
+cap "MNTgate1/a_n15_n199#" "MNinv1/a_n73_37#" 0.332021
+cap "MNTgate1/a_n15_n199#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" 39.8077
+cap "MNinv1/a_191_n163#" "MNTgate2/a_n15_n199#" 260.46
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MPinv1/a_279_n36#" 100.946
+cap "MNinv1/a_191_n163#" "MPinv2/a_15_n36#" 26.5082
+cap "MPinv2/a_15_n36#" "MNTgate2/a_n15_n199#" 109.781
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "MNinv2/a_n73_n163#" 1069.73
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" 92.4225
+cap "MNinv1/a_191_n163#" "MNinv2/a_n73_n163#" 334.496
+cap "MPinv2/a_15_n36#" "MNinv2/a_n73_n163#" 179.947
+cap "MNTgate1/a_n15_n199#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" 24.0588
+cap "MNinv2/a_n73_n163#" "MNTgate2/a_n15_n199#" -282.493
+cap "2" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" 188.843
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" -145.047
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" "MPinv1/a_279_n36#" -68.9253
+cap "MNTgate1/a_n15_n199#" "MNTgate2/a_n15_n199#" 109.567
+cap "MNTgate1/a_n15_n199#" "MNinv1/a_191_n163#" 79.491
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" "MNinv1/a_n73_37#" 0.96988
+cap "2" "MPinv2/a_15_n36#" -1.42109e-14
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" 6.53314
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MNinv1/a_191_n163#" 109.785
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MNTgate2/a_n15_n199#" 2.43269
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MPinv2/a_15_n36#" 105.925
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "MPinv1/a_279_n36#" -177.14
+cap "MNTgate1/a_n15_n199#" "MNinv2/a_n73_n163#" 891.974
+cap "2" "MNinv2/a_n73_n163#" -74.5699
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" -6.41006
+cap "MPinv1/a_279_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" 20.6585
+cap "MNinv1/a_191_n163#" "MPinv1/a_279_n36#" -17.5415
+cap "MPbuf1/a_n73_n36#" "MNfb/a_15_n163#" 129.706
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MNfb/a_15_n163#" 4.05263
+cap "MNfb/a_n73_n163#" "MPbuf2/a_15_n36#" 20.5987
+cap "MPinv2/a_191_n36#" "MNfb/a_n73_n163#" 338.382
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "MPbuf1/a_n73_n36#" 105.299
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "MNfb/a_15_n163#" 519.657
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" 210.799
+cap "MPinv2/a_279_n36#" "MPbuf1/a_n73_n36#" 124.989
+cap "MNTgate2/a_n15_n199#" "MPinv2/a_191_n36#" 79.491
+cap "MPinv2/a_279_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" -72.6296
+cap "MPinv2/a_279_n36#" "MNfb/a_15_n163#" 31.9471
+cap "MNTgate2/a_n15_n199#" "MNfb/a_n73_n163#" 961.756
+cap "MPinv2/a_279_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" -225.454
+cap "MPbuf2/a_15_n36#" "MPbuf1/a_n73_n36#" 37.9346
+cap "MNTgate2/a_n15_n199#" "MPinv2/a_n15_n133#" 2.04298
+cap "MPinv2/a_191_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" 251.727
+cap "MPinv2/a_191_n36#" "MNfb/a_15_n163#" 27.7597
+cap "MNfb/a_n73_n163#" "MPbuf1/a_n73_n36#" -226.214
+cap "MNfb/a_n73_n163#" "MNfb/a_15_n163#" 112.178
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "MPbuf2/a_15_n36#" 4.24837
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "MPinv2/a_191_n36#" 483.889
+cap "MNTgate2/a_n15_n199#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" 44.0096
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MPinv2/a_n15_n133#" 3.10902
+cap "MPinv2/a_279_n36#" "MPbuf2/a_15_n36#" 45.2648
+cap "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "MNfb/a_n73_n163#" 1444.78
+cap "MPinv2/a_279_n36#" "MPinv2/a_191_n36#" -18.2385
+cap "MPinv2/a_279_n36#" "MNfb/a_n73_n163#" 17.2279
+cap "MNTgate2/a_n15_n199#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" 25.6357
+cap "MPfb/a_n15_n133#" "MPbuf1/a_n73_n36#" 5.41463
+cap "MPbuf1/a_n73_n36#" "MNfb/a_103_n163#" 368.218
+cap "MNfb/a_191_n163#" "MNfb/a_103_n163#" 21.0913
+cap "MPbuf2/a_15_n36#" "MNfb/a_103_n163#" 83.329
+cap "MPbuf1/a_n73_n36#" "MPbuf1/a_n15_n133#" 30.087
+cap "MPbuf1/a_n15_n133#" "MPbuf2/a_15_n36#" 4.24837
+cap "MPfb/a_103_n36#" "MPbuf1/a_n73_n36#" 66.7316
+cap "MPfb/a_103_n36#" "MPbuf2/a_15_n36#" 89.1249
+cap "MPfb/a_103_n36#" "MNfb/a_191_n163#" 31.8522
+cap "MPbuf1/a_n15_n133#" "MNfb/a_103_n163#" 21.1947
+cap "MNfb/a_191_n163#" "MPbuf1/a_n73_n36#" 0.0772348
+cap "MPbuf1/a_n73_n36#" "MPbuf2/a_15_n36#" 159.448
+cap "MPfb/a_103_n36#" "MNfb/a_103_n163#" 19.0137
+merge "MNTgate2/a_631_n163#" "MNTgate2/a_455_n163#" -1118.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35183 -1858 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate2/a_455_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_455_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_455_n36#" "MNTgate2/a_103_n163#"
+merge "MNTgate2/a_103_n163#" "MNTgate2/a_n73_n163#"
+merge "MNTgate2/a_n73_n163#" "MNTgate2/a_279_n163#"
+merge "MNTgate2/a_279_n163#" "li_3760_n667#"
+merge "li_3760_n667#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_279_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_103_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n73_n36#" "li_3760_n126#"
+merge "li_3760_n126#" "MNinv2/a_15_n163#"
+merge "MNinv2/a_15_n163#" "MNinv2/a_191_n163#"
+merge "MNinv2/a_191_n163#" "MPinv2/a_191_n36#"
+merge "MPinv2/a_191_n36#" "MPinv2/a_15_n36#"
+merge "MPinv2/a_15_n36#" "5"
+merge "MPbuf2/a_103_n36#" "li_5462_n270#" -5760.62 0 0 0 0 -1934400 -19932 0 0 0 0 28800 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27738 -3248 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_5462_n270#" "MPbuf2/a_n73_n36#"
+merge "MPbuf2/a_n73_n36#" "MPbuf2/w_n109_n86#"
+merge "MPbuf2/w_n109_n86#" "MPbuf1/a_15_n36#"
+merge "MPbuf1/a_15_n36#" "a_5260_n263#"
+merge "a_5260_n263#" "MPbuf1/w_n109_n86#"
+merge "MPbuf1/w_n109_n86#" "MPfb/a_279_n36#"
+merge "MPfb/a_279_n36#" "MPfb/a_103_n36#"
+merge "MPfb/a_103_n36#" "MPfb/a_n73_n36#"
+merge "MPfb/a_n73_n36#" "MPfb/w_n109_n86#"
+merge "MPfb/w_n109_n86#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/w_n109_n86#" "MPinv2/a_279_n36#"
+merge "MPinv2/a_279_n36#" "MPinv2/a_103_n36#"
+merge "MPinv2/a_103_n36#" "MPinv2/a_n73_n36#"
+merge "MPinv2/a_n73_n36#" "MPinv2/w_n109_n86#"
+merge "MPinv2/w_n109_n86#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/w_n109_n86#" "MPinv1/a_n73_n36#"
+merge "MPinv1/a_n73_n36#" "MPinv1/a_279_n36#"
+merge "MPinv1/a_279_n36#" "MPinv1/a_103_n36#"
+merge "MPinv1/a_103_n36#" "MPinv1/w_n109_n86#"
+merge "MPinv1/w_n109_n86#" "MPClkin/a_279_n36#"
+merge "MPClkin/a_279_n36#" "MPClkin/a_103_n36#"
+merge "MPClkin/a_103_n36#" "MPClkin/a_n73_n36#"
+merge "MPClkin/a_n73_n36#" "MPClkin/w_n109_n86#"
+merge "MPClkin/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_455_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_455_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#" "li_90_n270#"
+merge "li_90_n270#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#" "a_n112_n263#"
+merge "a_n112_n263#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "VDD"
+merge "MNTgate2/a_n15_n199#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" -2546.91 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11042 -778 0 0 15354 -724 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n15_n81#" "MNClkin/a_n73_37#"
+merge "MNClkin/a_n73_37#" "MPClkin/a_n15_n133#"
+merge "MPClkin/a_n15_n133#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_543_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_543_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_15_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_191_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_367_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_367_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "Clkb_buf"
+merge "MNTgate1/a_631_n163#" "MNTgate1/a_455_n163#" -1121.06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33747 -1792 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_455_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_455_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_455_n36#" "MNTgate1/a_103_n163#"
+merge "MNTgate1/a_103_n163#" "MNTgate1/a_n73_n163#"
+merge "MNTgate1/a_n73_n163#" "MNTgate1/a_279_n163#"
+merge "MNTgate1/a_279_n163#" "li_2322_n667#"
+merge "li_2322_n667#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_n73_n36#" "li_2322_n126#"
+merge "li_2322_n126#" "MPinv1/a_191_n36#"
+merge "MPinv1/a_191_n36#" "MPinv1/a_15_n36#"
+merge "MPinv1/a_15_n36#" "MNinv1/a_15_n163#"
+merge "MNinv1/a_15_n163#" "MNinv1/a_191_n163#"
+merge "MNinv1/a_191_n163#" "3"
+merge "MNbuf2/VSUBS" "MNbuf2/a_103_n163#" -1511.55 0 0 0 0 0 0 0 0 16800 -1344 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120463 -5192 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf2/a_103_n163#" "MNbuf2/a_n73_n163#"
+merge "MNbuf2/a_n73_n163#" "MPbuf2/VSUBS"
+merge "MPbuf2/VSUBS" "MNbuf1/VSUBS"
+merge "MNbuf1/VSUBS" "MNbuf1/a_15_n163#"
+merge "MNbuf1/a_15_n163#" "a_5260_n585#"
+merge "a_5260_n585#" "MPbuf1/VSUBS"
+merge "MPbuf1/VSUBS" "MPfb/VSUBS"
+merge "MPfb/VSUBS" "MNfb/VSUBS"
+merge "MNfb/VSUBS" "MNfb/a_103_n163#"
+merge "MNfb/a_103_n163#" "MNfb/a_n73_n163#"
+merge "MNfb/a_n73_n163#" "MNTgate2/VSUBS"
+merge "MNTgate2/VSUBS" "sky130_fd_pr__pfet_01v8_B2DS5R_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/VSUBS" "MNinv2/VSUBS"
+merge "MNinv2/VSUBS" "MNinv2/a_103_n163#"
+merge "MNinv2/a_103_n163#" "MNinv2/a_n73_n163#"
+merge "MNinv2/a_n73_n163#" "MPinv2/VSUBS"
+merge "MPinv2/VSUBS" "MNTgate1/VSUBS"
+merge "MNTgate1/VSUBS" "sky130_fd_pr__pfet_01v8_B2DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/VSUBS" "MPinv1/VSUBS"
+merge "MPinv1/VSUBS" "MNinv1/VSUBS"
+merge "MNinv1/VSUBS" "MNinv1/a_103_n163#"
+merge "MNinv1/a_103_n163#" "MNinv1/a_n73_n163#"
+merge "MNinv1/a_n73_n163#" "MNClkin/a_103_n163#"
+merge "MNClkin/a_103_n163#" "MNClkin/VSUBS"
+merge "MNClkin/VSUBS" "MNClkin/a_n73_n163#"
+merge "MNClkin/a_n73_n163#" "MPClkin/VSUBS"
+merge "MPClkin/VSUBS" "sky130_fd_pr__pfet_01v8_A4DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW4BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_279_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_279_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#" "a_n112_n585#"
+merge "a_n112_n585#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS" "GND"
+merge "MPfb/a_191_n36#" "MPfb/a_15_n36#" -1303.54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7170 -538 0 0 -3128 -524 -64400 -2800 0 0 0 0 0 0 0 0 0 0
+merge "MPfb/a_15_n36#" "MNfb/a_191_n163#"
+merge "MNfb/a_191_n163#" "MNfb/a_15_n163#"
+merge "MNfb/a_15_n163#" "MPinv1/a_n15_n133#"
+merge "MPinv1/a_n15_n133#" "MNinv1/a_n73_37#"
+merge "MNinv1/a_n73_37#" "2"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" -815.557 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -824 0 0 -10166 -938 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" "a_n40_n319#"
+merge "a_n40_n319#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#" "Clkb_int"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_n15_n81#" "MNTgate1/a_n15_n199#" -1430.84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1800 -240 0 0 79092 -1088 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n15_n199#" "MNClkin/a_191_n163#"
+merge "MNClkin/a_191_n163#" "MPClkin/a_191_n36#"
+merge "MPClkin/a_191_n36#" "MNClkin/a_15_n163#"
+merge "MNClkin/a_15_n163#" "a_2222_n669#"
+merge "a_2222_n669#" "MPClkin/a_15_n36#"
+merge "MPClkin/a_15_n36#" "Clk_In_buf"
+merge "Clk_In_buf" "li_1356_17#"
+merge "li_1356_17#" "a_3651_1#"
+merge "MNbuf2/a_n73_37#" "MPbuf2/a_n15_n133#" -738.852 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2487 -338 0 0 6478 -856 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_n15_n133#" "MNbuf1/a_n73_n163#"
+merge "MNbuf1/a_n73_n163#" "li_5126_n470#"
+merge "li_5126_n470#" "MPbuf1/a_n73_n36#"
+merge "MPbuf1/a_n73_n36#" "7"
+merge "MNinv2/a_n73_37#" "MPinv2/a_n15_n133#" -854.705 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7139 -538 0 0 54408 -2050 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPinv2/a_n15_n133#" "MNTgate1/a_543_n163#"
+merge "MNTgate1/a_543_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_543_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_543_n36#" "MNTgate1/a_367_n163#"
+merge "MNTgate1/a_367_n163#" "MNTgate1/a_191_n163#"
+merge "MNTgate1/a_191_n163#" "MNTgate1/a_15_n163#"
+merge "MNTgate1/a_15_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_191_n36#" "li_2586_n83#"
+merge "li_2586_n83#" "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_0/a_15_n36#" "4"
+merge "4" "li_2410_n92#"
+merge "MNbuf1/a_n73_37#" "li_5129_n369#" -1256.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5417 -680 0 0 76338 -2246 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_5129_n369#" "MPbuf1/a_n15_n133#"
+merge "MPbuf1/a_n15_n133#" "MPfb/a_n15_n133#"
+merge "MPfb/a_n15_n133#" "MNfb/a_n73_37#"
+merge "MNfb/a_n73_37#" "MNTgate2/a_543_n163#"
+merge "MNTgate2/a_543_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_543_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_543_n36#" "MNTgate2/a_367_n163#"
+merge "MNTgate2/a_367_n163#" "MNTgate2/a_191_n163#"
+merge "MNTgate2/a_191_n163#" "MNTgate2/a_15_n163#"
+merge "MNTgate2/a_15_n163#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_367_n36#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_191_n36#" "li_4024_n83#"
+merge "li_4024_n83#" "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_B2DS5R_1/a_15_n36#" "6"
+merge "6" "li_3848_n92#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" -491.152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4258 -338 0 0 -2244 -200 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "Clk_In"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_37#" -1056.56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -790 -934 0 0 -1190 -478 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" "dus"
+merge "MNbuf2/a_15_n163#" "MPbuf2/a_15_n36#" -172.671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf2/a_15_n36#" "Clk_Out"
diff --git a/mag/3-stage_cs-vco_dp9/old/FD_v5_lasttry.mag b/mag/3-stage_cs-vco_dp9/old/FD_v5_lasttry.mag
new file mode 100755
index 0000000..a36b266
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/FD_v5_lasttry.mag
@@ -0,0 +1,556 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647369436
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+rect 5462 -714 5496 -486
+rect -382 -748 -314 -714
+rect -27 -748 1331 -714
+rect 5345 -748 5544 -714
+<< viali >>
+rect -270 107 89 141
+rect 1303 107 5461 141
+rect -246 -147 -212 -113
+rect 2229 17 2263 51
+rect 3029 17 3063 51
+rect 3667 17 3701 51
+rect 4469 17 4503 51
+rect 5126 -21 5160 13
+rect -246 -235 -212 -201
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+rect 5374 -368 5408 -334
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+rect 4549 -645 4583 -611
+rect 5126 -619 5160 -585
+rect -289 -748 -27 -714
+rect 1331 -748 5345 -714
+<< metal1 >>
+rect -383 141 5544 153
+rect -383 107 -270 141
+rect 89 107 1303 141
+rect 5461 107 5544 141
+rect -383 95 5544 107
+rect 1265 51 3075 57
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+rect -252 -113 -206 -101
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+rect -212 -235 -206 -201
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+rect 1350 -49 1396 -23
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+rect 1390 -235 1396 -49
+rect 2316 -92 2362 -80
+rect 2486 -92 2544 -86
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+rect 5126 -335 5160 -274
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+rect 5126 -369 5290 -335
+rect 5324 -369 5336 -335
+rect -252 -422 -206 -410
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+rect -4 -380 42 -375
+rect 1258 -378 1319 -375
+rect -252 -456 -246 -422
+rect -212 -456 -64 -422
+rect 1265 -419 1311 -378
+rect -252 -468 -206 -456
+rect 1265 -465 3699 -419
+rect 5048 -433 5094 -421
+rect -246 -501 -212 -468
+rect -252 -585 -206 -501
+rect 1344 -508 1399 -493
+rect 1344 -574 1356 -508
+rect 1390 -574 1399 -508
+rect 1344 -580 1399 -574
+rect -252 -619 -246 -585
+rect -212 -619 -206 -585
+rect -252 -631 -206 -619
+rect 1353 -605 1399 -580
+rect 3653 -605 3699 -465
+rect 4552 -470 4608 -458
+rect 5048 -467 5054 -433
+rect 5088 -467 5094 -433
+rect 5048 -470 5094 -467
+rect 4552 -504 4564 -470
+rect 4598 -479 5094 -470
+rect 4598 -504 5088 -479
+rect 5126 -501 5160 -369
+rect 5278 -375 5336 -369
+rect 5368 -334 5414 -322
+rect 5368 -368 5374 -334
+rect 5408 -368 5544 -334
+rect 5368 -380 5414 -368
+rect 4552 -512 4608 -504
+rect 5120 -585 5166 -501
+rect 1353 -611 3157 -605
+rect 1353 -645 2238 -611
+rect 2272 -645 3111 -611
+rect 3145 -645 3157 -611
+rect 1353 -651 3157 -645
+rect 3647 -611 4595 -605
+rect 3647 -645 3676 -611
+rect 3710 -645 4549 -611
+rect 4583 -645 4595 -611
+rect 5120 -619 5126 -585
+rect 5160 -619 5166 -585
+rect 5120 -631 5166 -619
+rect 3647 -651 4595 -645
+rect 3653 -660 3699 -651
+rect -382 -714 5544 -702
+rect -382 -748 -289 -714
+rect -27 -748 1331 -714
+rect 5345 -748 5544 -714
+rect -382 -760 5544 -748
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0
+timestamp 1647282796
+transform 1 0 -25 0 1 -227
+box -109 -86 461 314
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0
+timestamp 1647281419
+transform 1 0 -273 0 1 -422
+box -73 -199 161 103
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0
+timestamp 1647281041
+transform 1 0 -273 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0
+timestamp 1647276187
+transform 1 0 -25 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW4BNL sky130_fd_pr__nfet_01v8_PW4BNL_0
+timestamp 1647366004
+transform 1 0 562 0 1 -422
+box -73 -199 425 103
+use sky130_fd_pr__pfet_01v8_A4DS5R sky130_fd_pr__pfet_01v8_A4DS5R_0
+timestamp 1647366004
+transform 1 0 562 0 1 -227
+box -109 -133 637 314
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin
+timestamp 1647279940
+transform 1 0 1329 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin
+timestamp 1647276187
+transform 1 0 1329 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1
+timestamp 1647276187
+transform 1 0 1845 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1
+timestamp 1647279940
+transform 1 0 1845 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_B2DS5R sky130_fd_pr__pfet_01v8_B2DS5R_0
+timestamp 1647369436
+transform 1 0 2383 0 -1 1
+box -109 -86 637 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1
+timestamp 1647283104
+transform 1 0 2383 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2
+timestamp 1647279940
+transform 1 0 3277 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2
+timestamp 1647276187
+transform 1 0 3277 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_B2DS5R sky130_fd_pr__pfet_01v8_B2DS5R_1
+timestamp 1647369436
+transform 1 0 3821 0 -1 1
+box -109 -86 637 314
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2
+timestamp 1647283104
+transform 1 0 3821 0 -1 -580
+box -73 -199 689 50
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb
+timestamp 1647276187
+transform 1 0 4704 0 1 -422
+box -73 -199 249 103
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb
+timestamp 1647279940
+transform 1 0 4704 0 1 -227
+box -109 -133 373 314
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1
+timestamp 1647281016
+transform 1 0 5187 0 1 -227
+box -109 -133 109 314
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1
+timestamp 1647281419
+transform 1 0 5187 0 1 -422
+box -73 -199 73 103
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2
+timestamp 1647281041
+transform 1 0 5347 0 1 -227
+box -109 -133 197 314
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2
+timestamp 1647281419
+transform 1 0 5347 0 1 -422
+box -73 -199 161 103
+<< labels >>
+rlabel metal1 -382 -369 -357 -335 1 Clk_In
+port 1 n
+rlabel metal1 -95 -364 -56 -332 1 Clkb_int
+rlabel metal1 184 -760 218 -702 1 GND
+port 3 n
+rlabel metal1 156 95 190 153 1 VDD
+port 2 n
+rlabel locali 1938 -335 1963 -311 1 3
+rlabel locali 2416 -321 2441 -297 1 4
+rlabel locali 3309 -323 3334 -299 1 5
+rlabel locali 4735 -321 4760 -297 1 2
+rlabel locali 4568 -430 4592 -404 1 6
+rlabel metal1 5224 -363 5249 -339 1 7
+rlabel metal1 5510 -368 5544 -334 1 Clk_Out
+port 4 n
+rlabel metal1 1209 -365 1238 -342 1 Clkb_buf
+rlabel locali 1359 -328 1387 -296 1 Clk_In_buf
+rlabel metal1 416 -366 453 -336 1 dus
+<< properties >>
+string LEFsite unithddb1
+string LEFclass CORE
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_switch_p_-_seccopy_5-3-2022_10y41.mag b/mag/3-stage_cs-vco_dp9/old/vco_switch_p_-_seccopy_5-3-2022_10y41.mag
new file mode 100755
index 0000000..c16e059
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_switch_p_-_seccopy_5-3-2022_10y41.mag
@@ -0,0 +1,128 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646473152
+<< nwell >>
+rect 376 952 987 1215
+rect 376 845 932 952
+rect 934 845 987 952
+<< pwell >>
+rect 376 462 987 845
+<< psubdiff >>
+rect 412 508 436 542
+rect 630 508 654 542
+<< nsubdiff >>
+rect 414 1145 443 1179
+rect 661 1145 690 1179
+<< psubdiffcont >>
+rect 436 508 630 542
+<< nsubdiffcont >>
+rect 443 1145 661 1179
+<< poly >>
+rect 655 1073 721 1089
+rect 655 1039 671 1073
+rect 705 1069 721 1073
+rect 705 1039 727 1069
+rect 655 1033 727 1039
+rect 655 1023 721 1033
+<< polycont >>
+rect 671 1039 705 1073
+<< locali >>
+rect 427 1145 443 1179
+rect 661 1145 677 1179
+rect 488 1085 522 1145
+rect 671 1073 705 1089
+rect 671 1034 705 1039
+rect 410 833 444 994
+rect 891 988 973 1022
+rect 610 903 699 940
+rect 410 799 494 833
+rect 576 765 610 877
+rect 939 852 973 988
+rect 745 745 779 793
+rect 939 671 973 796
+rect 899 637 973 671
+rect 488 542 522 627
+rect 420 508 436 542
+rect 630 508 646 542
+<< viali >>
+rect 443 1145 661 1179
+rect 410 994 444 1028
+rect 671 994 705 1034
+rect 494 799 528 833
+rect 745 793 779 827
+rect 939 796 973 852
+rect 829 731 889 765
+rect 445 508 619 542
+<< metal1 >>
+rect 376 1179 897 1186
+rect 376 1145 443 1179
+rect 661 1145 897 1179
+rect 376 1097 897 1145
+rect 376 1080 414 1097
+rect 398 1028 450 1040
+rect 659 1034 717 1040
+rect 659 1028 671 1034
+rect 398 994 410 1028
+rect 444 994 671 1028
+rect 705 994 717 1034
+rect 398 982 450 994
+rect 659 988 717 994
+rect 376 896 598 911
+rect 376 876 889 896
+rect 570 861 889 876
+rect 478 833 538 839
+rect 478 799 494 833
+rect 528 827 791 833
+rect 528 799 745 827
+rect 478 793 538 799
+rect 733 793 745 799
+rect 779 793 791 827
+rect 733 787 791 793
+rect 834 777 889 861
+rect 927 852 985 865
+rect 927 796 939 852
+rect 973 796 985 852
+rect 927 784 985 796
+rect 819 765 899 777
+rect 817 731 829 765
+rect 889 764 899 765
+rect 889 731 901 764
+rect 817 725 901 731
+rect 376 542 690 632
+rect 376 508 445 542
+rect 619 508 690 542
+rect 817 508 901 534
+rect 376 462 901 508
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0
+timestamp 1646411492
+transform 0 -1 828 1 0 701
+box -76 -99 76 99
+use sky130_fd_pr__pfet_01v8_5YXW2B sky130_fd_pr__pfet_01v8_5YXW2B_0
+timestamp 1646470613
+transform 0 -1 825 1 0 1051
+box -112 -134 112 134
+use sky130_fd_pr__pfet_01v8_ACAZ2B_v2 sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0
+timestamp 1646472401
+transform 0 -1 789 1 0 957
+box -112 -170 112 136
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0
+timestamp 1646472163
+transform 1 0 549 0 1 981
+box -109 -136 109 162
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0
+timestamp 1646472401
+transform 1 0 549 0 1 727
+box -73 -122 73 122
+<< labels >>
+rlabel metal1 376 876 407 911 1 in
+port 0 n
+rlabel metal1 376 488 414 632 1 vss
+port 3 n
+rlabel nwell 376 1080 414 1176 1 vdd
+port 4 n
+rlabel metal1 927 784 985 865 1 out
+port 2 n
+rlabel metal1 478 793 520 839 1 sel
+port 1 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs.gds b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs.gds
new file mode 100644
index 0000000..61306e3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs.gds
Binary files differ
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_HACK_INVERTER_WIDTHS.spice b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_HACK_INVERTER_WIDTHS.spice
new file mode 100755
index 0000000..1a08512
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_HACK_INVERTER_WIDTHS.spice
@@ -0,0 +1,1087 @@
+* NGSPICE file created from vco_with_fdivs.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=6720000u l=150000u
+C0 a_n73_n115# a_15_n115# 0.11fF
+C1 a_15_n115# VSUBS 0.02fF
+C2 a_n73_n115# VSUBS 0.02fF
+C3 a_n118_22# VSUBS 0.15fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
++ VSUBS
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=6400000u l=150000u
+C0 a_15_n36# w_n109_n86# 0.08fF
+C1 w_n109_n86# a_n73_n36# 0.08fF
+C2 w_n109_n86# a_n15_n133# 0.05fF
+C3 a_15_n36# a_n73_n36# 0.09fF
+C4 a_15_n36# VSUBS -0.06fF
+C5 a_n73_n36# VSUBS -0.06fF
+C6 a_n15_n133# VSUBS 0.04fF
+C7 w_n109_n86# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_n73_n67# a_n73_37# a_15_n67# VSUBS
+X0 a_15_n67# a_n73_37# a_n73_n67# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=2800000u l=150000u
+C0 a_n73_37# a_n73_n67# 0.03fF
+C1 a_n73_n67# a_15_n67# 0.06fF
+C2 a_15_n67# VSUBS 0.03fF
+C3 a_n73_n67# VSUBS 0.03fF
+C4 a_n73_37# VSUBS 0.15fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
++ VSUBS
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=6720000u l=150000u
+C0 a_15_n78# w_n109_n140# 0.05fF
+C1 w_n109_n140# a_n73_n78# 0.05fF
+C2 w_n109_n140# a_n33_37# 0.14fF
+C3 a_15_n78# a_n73_n78# 0.06fF
+C4 a_15_n78# a_n33_37# 0.00fF
+C5 a_n33_37# a_n73_n78# 0.00fF
+C6 a_15_n78# VSUBS -0.03fF
+C7 a_n73_n78# VSUBS -0.03fF
+C8 a_n33_37# VSUBS -0.01fF
+C9 w_n109_n140# VSUBS 0.16fF
+.ends
+
+.subckt FD_v2 VDD GND Clk_Out 7 5 4 3 Clkb 6 Clk_In 2
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 GND Clk_In Clkb GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 7 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD GND sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD GND sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW5BNL
+C0 5 2 0.17fF
+C1 Clkb 4 0.12fF
+C2 Clk_Out 7 0.14fF
+C3 2 4 0.19fF
+C4 5 GND 0.18fF
+C5 5 Clk_In 0.11fF
+C6 3 5 0.03fF
+C7 7 2 0.10fF
+C8 GND 4 0.41fF
+C9 VDD 5 0.12fF
+C10 Clk_In 4 0.08fF
+C11 3 4 0.13fF
+C12 7 GND 0.13fF
+C13 VDD 4 0.10fF
+C14 7 Clk_In 0.00fF
+C15 5 6 0.19fF
+C16 VDD 7 0.26fF
+C17 6 4 0.00fF
+C18 6 7 0.42fF
+C19 Clk_Out 2 0.04fF
+C20 2 Clkb 0.60fF
+C21 Clk_Out GND 0.08fF
+C22 GND Clkb 0.08fF
+C23 Clk_In Clkb 1.01fF
+C24 Clk_Out VDD 0.08fF
+C25 3 Clkb 0.27fF
+C26 5 4 0.07fF
+C27 GND 2 0.20fF
+C28 VDD Clkb 1.06fF
+C29 Clk_In 2 0.85fF
+C30 3 2 0.12fF
+C31 VDD 2 0.28fF
+C32 Clk_Out 6 0.02fF
+C33 Clk_In GND 0.43fF
+C34 3 GND 0.22fF
+C35 6 Clkb 0.02fF
+C36 3 Clk_In 0.19fF
+C37 VDD GND 0.03fF
+C38 VDD Clk_In 1.11fF
+C39 3 VDD 0.15fF
+C40 6 2 0.60fF
+C41 6 GND 0.78fF
+C42 6 Clk_In 0.00fF
+C43 VDD 6 0.12fF
+C44 5 Clkb 0.08fF
+C45 Clkb 0 1.00fF
+C46 7 0 0.48fF
+C47 Clk_Out 0 0.13fF
+C48 5 0 0.13fF
+C49 GND 0 -0.17fF
+C50 Clk_In 0 0.96fF
+C51 3 0 0.03fF
+C52 2 0 0.93fF
+C53 VDD 0 1.90fF
+C54 6 0 0.83fF
+C55 4 0 0.09fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# w_n109_n340# 0.19fF
+C1 a_15_n240# a_n73_n240# 0.20fF
+C2 a_n33_n337# w_n109_n340# 0.11fF
+C3 a_15_n240# w_n109_n340# 0.17fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_18_n220# a_114_n220# w_n209_n320#
++ a_n129_n317# a_63_n317# a_n33_251# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n317# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n317# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_251# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 a_n78_n220# a_n129_n317# 0.00fF
+C1 a_n129_n317# a_n173_n220# 0.00fF
+C2 a_n129_n317# w_n209_n320# 0.14fF
+C3 a_114_n220# a_18_n220# 0.31fF
+C4 a_114_n220# a_n173_n220# 0.07fF
+C5 a_114_n220# a_n78_n220# 0.18fF
+C6 a_63_n317# a_n129_n317# 0.03fF
+C7 a_114_n220# w_n209_n320# 0.33fF
+C8 a_114_n220# a_63_n317# 0.00fF
+C9 a_18_n220# a_n33_251# 0.00fF
+C10 a_n78_n220# a_n33_251# 0.00fF
+C11 a_n33_251# w_n209_n320# 0.14fF
+C12 a_n78_n220# a_18_n220# 0.31fF
+C13 a_n173_n220# a_18_n220# 0.14fF
+C14 a_18_n220# w_n209_n320# 0.28fF
+C15 a_n78_n220# a_n173_n220# 0.31fF
+C16 a_63_n317# a_n33_251# 0.02fF
+C17 a_n78_n220# w_n209_n320# 0.33fF
+C18 a_n173_n220# w_n209_n320# 0.28fF
+C19 a_63_n317# a_18_n220# 0.00fF
+C20 a_63_n317# w_n209_n320# 0.14fF
+C21 a_n129_n317# a_n33_251# 0.02fF
+C22 a_114_n220# VSUBS -0.33fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.33fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n317# VSUBS -0.01fF
+C27 a_n129_n317# VSUBS -0.01fF
+C28 a_n33_251# VSUBS -0.01fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n33_95# w_n112_n198# 0.19fF
+C1 a_n33_95# a_18_n136# 0.00fF
+C2 a_n76_n136# w_n112_n198# 0.16fF
+C3 a_n76_n136# a_18_n136# 0.20fF
+C4 a_18_n136# w_n112_n198# 0.16fF
+C5 a_n33_95# a_n76_n136# 0.00fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_n33_142# 0.01fF
+C1 a_15_n120# a_n33_142# 0.00fF
+C2 a_n73_n120# a_15_n120# 0.15fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_n33_n217# 0.00fF
+C1 a_18_n129# a_n33_n217# 0.00fF
+C2 a_n76_n129# a_18_n129# 0.21fF
+C3 a_18_n129# VSUBS 0.00fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_n33_n157# 0.00fF
+C1 a_18_n69# a_n33_n157# 0.01fF
+C2 a_n76_n69# a_18_n69# 0.17fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+C0 a_n76_n29# a_n33_n117# 0.01fF
+C1 a_18_n29# a_n33_n117# 0.01fF
+C2 a_n76_n29# a_18_n29# 0.12fF
+C3 a_18_n29# VSUBS 0.00fF
+C4 a_n76_n29# VSUBS 0.00fF
+C5 a_n33_n117# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_n33_n297# 0.00fF
+C1 a_18_n209# a_n33_n297# 0.00fF
+C2 a_n76_n209# a_18_n209# 0.35fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
++ VSUBS
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n33_67# w_n112_n170# 0.19fF
+C1 a_n33_67# a_18_n108# 0.01fF
+C2 a_n76_n108# w_n112_n170# 0.15fF
+C3 a_n76_n108# a_18_n108# 0.22fF
+C4 a_18_n108# w_n112_n170# 0.15fF
+C5 a_n33_67# a_n76_n108# 0.01fF
+C6 a_18_n108# VSUBS -0.13fF
+C7 a_n76_n108# VSUBS -0.13fF
+C8 a_n33_67# VSUBS -0.07fF
+C9 w_n112_n170# VSUBS 0.21fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
++ VSUBS
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+C0 a_n15_n132# w_n109_n136# 0.05fF
+C1 a_n73_n100# w_n109_n136# 0.10fF
+C2 a_n73_n100# a_15_n100# 0.13fF
+C3 a_15_n100# w_n109_n136# 0.10fF
+C4 a_15_n100# VSUBS -0.08fF
+C5 a_n73_n100# VSUBS -0.08fF
+C6 a_n15_n132# VSUBS 0.00fF
+C7 w_n109_n136# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+C0 a_n73_n96# a_n73_56# 0.03fF
+C1 a_n73_n96# a_15_n96# 0.08fF
+C2 a_15_n96# VSUBS 0.02fF
+C3 a_n73_n96# VSUBS 0.02fF
+C4 a_n73_56# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+C0 a_18_n73# a_n18_n99# 0.03fF
+C1 a_n76_n73# a_18_n73# 0.05fF
+C2 a_18_n73# VSUBS 0.02fF
+C3 a_n76_n73# VSUBS 0.02fF
+C4 a_n18_n99# VSUBS 0.13fF
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd selb
+XXM25 vdd in out selb vss sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel vss sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+C0 in selb 0.25fF
+C1 sel selb 0.39fF
+C2 in vdd 0.30fF
+C3 sel vdd 0.09fF
+C4 in out 0.19fF
+C5 sel out 0.06fF
+C6 vdd selb 0.14fF
+C7 selb out 0.06fF
+C8 vdd out 0.11fF
+C9 sel in 0.55fF
+C10 sel vss 0.78fF
+C11 selb vss 0.81fF
+C12 vdd vss 0.57fF
+C13 out vss 0.16fF
+C14 in vss 0.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n276# w_n112_n338# 0.32fF
+C1 a_n33_235# w_n112_n338# 0.19fF
+C2 a_n76_n276# a_n33_235# 0.00fF
+C3 w_n112_n338# a_18_n276# 0.32fF
+C4 a_n76_n276# a_18_n276# 0.46fF
+C5 a_n33_235# a_18_n276# 0.00fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
++ VSUBS
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+C0 a_n73_n144# w_n109_n244# 0.13fF
+C1 a_n33_n241# w_n109_n244# 0.14fF
+C2 a_n73_n144# a_n33_n241# 0.00fF
+C3 w_n109_n244# a_15_n144# 0.13fF
+C4 a_n73_n144# a_15_n144# 0.15fF
+C5 a_n33_n241# a_15_n144# 0.00fF
+C6 a_15_n144# VSUBS -0.11fF
+C7 a_n73_n144# VSUBS -0.11fF
+C8 a_n33_n241# VSUBS -0.01fF
+C9 w_n109_n244# VSUBS 0.29fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n33_n297# 0.00fF
+C1 a_n76_n209# a_n33_n297# 0.00fF
+C2 a_18_n209# a_n76_n209# 0.47fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_15_n103# a_n33_63# 0.00fF
+C1 a_n73_n103# a_n33_63# 0.00fF
+C2 a_15_n103# a_n73_n103# 0.07fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+C0 a_n73_n64# w_n109_n164# 0.06fF
+C1 a_n33_n161# w_n109_n164# 0.14fF
+C2 a_n73_n64# a_n33_n161# 0.00fF
+C3 w_n109_n164# a_15_n64# 0.06fF
+C4 a_n73_n64# a_15_n64# 0.07fF
+C5 a_n33_n161# a_15_n64# 0.00fF
+C6 a_15_n64# VSUBS -0.06fF
+C7 a_n73_n64# VSUBS -0.06fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n96# a_n33_33# 0.00fF
+C1 a_n73_n96# a_n33_33# 0.00fF
+C2 a_15_n96# a_n73_n96# 0.06fF
+C3 a_15_n96# VSUBS 0.02fF
+C4 a_n73_n96# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+C0 a_n73_n236# w_n109_n298# 0.26fF
+C1 a_n33_395# w_n109_n298# 0.14fF
+C2 a_n73_n236# a_n33_395# 0.00fF
+C3 w_n109_n298# a_15_n236# 0.26fF
+C4 a_n73_n236# a_15_n236# 0.32fF
+C5 a_n33_395# a_15_n236# 0.00fF
+C6 a_15_n236# VSUBS -0.25fF
+C7 a_n73_n236# VSUBS -0.25fF
+C8 a_n33_395# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.50fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_15_n175# a_n33_135# 0.00fF
+C1 a_n73_n175# a_n33_135# 0.00fF
+C2 a_15_n175# a_n73_n175# 0.16fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+C0 a_18_n89# a_n33_n177# 0.01fF
+C1 a_n76_n89# a_n33_n177# 0.00fF
+C2 a_18_n89# a_n76_n89# 0.19fF
+C3 a_18_n89# VSUBS 0.00fF
+C4 a_n76_n89# VSUBS 0.00fF
+C5 a_n33_n177# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
++ VSUBS
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n76_n72# w_n112_n134# 0.15fF
+C1 a_n18_n98# w_n112_n134# 0.05fF
+C2 w_n112_n134# a_18_n72# 0.15fF
+C3 a_n76_n72# a_18_n72# 0.22fF
+C4 a_18_n72# VSUBS -0.13fF
+C5 a_n76_n72# VSUBS -0.13fF
+C6 a_n18_n98# VSUBS 0.00fF
+C7 w_n112_n134# VSUBS 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
++ VSUBS
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n76_n108# w_n112_n170# 0.15fF
+C1 a_n68_67# w_n112_n170# 0.16fF
+C2 a_n76_n108# a_n68_67# 0.03fF
+C3 w_n112_n170# a_18_n108# 0.15fF
+C4 a_n76_n108# a_18_n108# 0.22fF
+C5 a_18_n108# VSUBS -0.13fF
+C6 a_n76_n108# VSUBS -0.13fF
+C7 a_n68_67# VSUBS -0.01fF
+C8 w_n112_n170# VSUBS 0.21fF
+.ends
+
+.subckt vco_switch_p in sel vss vdd selb out
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out vss sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel vss sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out vss sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+C0 out sel 0.14fF
+C1 vdd vss 0.01fF
+C2 selb in 0.11fF
+C3 selb vss 0.11fF
+C4 vdd sel 0.91fF
+C5 vss in -0.04fF
+C6 vdd out -0.04fF
+C7 selb sel 0.35fF
+C8 in sel 0.75fF
+C9 out selb 0.05fF
+C10 vss sel 0.39fF
+C11 out in 0.19fF
+C12 out vss 0.04fF
+C13 vdd selb 0.06fF
+C14 vdd in 0.40fF
+C15 selb 0 -0.05fF
+C16 vss 0 -0.10fF
+C17 sel 0 0.36fF
+C18 out 0 0.11fF
+C19 in 0 0.06fF
+C20 vdd 0 0.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
++ VSUBS
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+C0 a_18_n96# a_n76_n96# 0.13fF
+C1 a_n33_55# a_n76_n96# 0.01fF
+C2 a_n76_n96# w_n112_n158# 0.11fF
+C3 a_18_n96# a_n33_55# 0.01fF
+C4 a_18_n96# w_n112_n158# 0.11fF
+C5 a_n33_55# w_n112_n158# 0.19fF
+C6 a_18_n96# VSUBS -0.11fF
+C7 a_n76_n96# VSUBS -0.11fF
+C8 a_n33_55# VSUBS -0.07fF
+C9 w_n112_n158# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
++ VSUBS
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+C0 a_18_n156# a_n76_n156# 0.24fF
+C1 a_n33_115# a_n76_n156# 0.00fF
+C2 a_n76_n156# w_n112_n218# 0.18fF
+C3 a_18_n156# a_n33_115# 0.00fF
+C4 a_18_n156# w_n112_n218# 0.18fF
+C5 a_n33_115# w_n112_n218# 0.19fF
+C6 a_18_n156# VSUBS -0.18fF
+C7 a_n76_n156# VSUBS -0.18fF
+C8 a_n33_115# VSUBS -0.07fF
+C9 w_n112_n218# VSUBS 0.27fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 a_15_n22# a_n72_n22# 0.09fF
+C1 a_n72_n22# w_n109_n58# 0.14fF
+C2 a_15_n22# w_n109_n58# 0.08fF
+C3 a_n15_n53# w_n109_n58# 0.05fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_n73_n68# a_15_n68# 0.04fF
+C1 a_15_n68# a_n33_33# 0.00fF
+C2 a_n73_n68# a_n33_33# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt x3-stage_cs-vco_dp9 vdd out vctrl sel0 sel1 sel2 sel3 ng3 vco_switch_n_v2_3/selb
++ vss
+XXM12 net7 vdd vdd net6 vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd vdd out vdd net7 net7 net7 out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM25 vdd vgp vdd vgp vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2_0/selb vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2_1/selb vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2_2/selb vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2_3/selb vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd vss sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 vss sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd vss sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 vss vdd vco_switch_p_0/selb pg0 vco_switch_p
+XXM11A vdd vdd pg0 net2 vss sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11B vdd net2 vdd pg1 vss sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_2 vgp sel2 vss vdd vco_switch_p_2/selb pg2 vco_switch_p
+Xvco_switch_p_1 vgp sel1 vss vdd vco_switch_p_1/selb pg1 vco_switch_p
+XXM21 vdd net6 vdd net5 vss sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 vss vdd vco_switch_p_3/selb pg3 vco_switch_p
+XXM11 vdd vdd vgp net2 vss sky130_fd_pr__pfet_01v8_4XEGTB
+XXM22 net5 vss net6 vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11C vdd vdd pg2 net2 vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 vco_switch_n_v2_3/selb ng2 0.06fF
+C1 vco_switch_n_v2_1/selb vdd 0.02fF
+C2 net8 ng0 0.16fF
+C3 vco_switch_p_3/selb pg2 0.05fF
+C4 vgp pg2 1.40fF
+C5 ng1 vdd 0.11fF
+C6 vco_switch_p_1/selb sel1 0.20fF
+C7 vco_switch_n_v2_1/selb vco_switch_n_v2_0/selb 0.00fF
+C8 vco_switch_n_v2_3/selb vctrl 0.01fF
+C9 vco_switch_p_3/selb vdd 0.00fF
+C10 vgp pg1 0.81fF
+C11 vgp vdd 7.37fF
+C12 sel3 sel2 7.17fF
+C13 net6 net4 0.00fF
+C14 ng0 sel1 0.10fF
+C15 pg0 pg2 0.02fF
+C16 net7 out 0.28fF
+C17 net2 net4 0.00fF
+C18 ng2 vdd 0.11fF
+C19 sel0 vgp 0.25fF
+C20 pg0 pg1 0.11fF
+C21 pg0 vdd 2.47fF
+C22 vco_switch_p_0/selb vco_switch_p_1/selb 0.00fF
+C23 sel3 vco_switch_n_v2_2/selb 0.01fF
+C24 sel3 vco_switch_p_2/selb 0.02fF
+C25 net5 net4 0.15fF
+C26 net3 vdd 0.28fF
+C27 vctrl vdd 0.66fF
+C28 vctrl vco_switch_n_v2_0/selb 0.09fF
+C29 sel3 vco_switch_n_v2_1/selb 0.01fF
+C30 net8 net2 0.04fF
+C31 sel3 ng1 0.02fF
+C32 sel0 pg0 0.06fF
+C33 sel2 sel1 6.56fF
+C34 vco_switch_n_v2_3/selb vdd 0.02fF
+C35 sel3 vco_switch_p_3/selb 0.22fF
+C36 sel3 vgp 3.29fF
+C37 net8 net5 0.16fF
+C38 sel0 vctrl 0.54fF
+C39 sel2 pg3 0.04fF
+C40 net8 vco_switch_n_v2_1/selb 0.01fF
+C41 ng1 net8 0.00fF
+C42 ng2 net4 0.00fF
+C43 sel3 ng2 0.05fF
+C44 net8 vgp 0.03fF
+C45 sel3 pg0 0.30fF
+C46 pg3 net2 0.06fF
+C47 pg2 pg1 0.07fF
+C48 ng3 sel2 0.02fF
+C49 pg2 vdd 1.69fF
+C50 sel2 vco_switch_p_0/selb 0.05fF
+C51 net3 net4 0.08fF
+C52 vco_switch_n_v2_1/selb sel1 0.33fF
+C53 vco_switch_p_2/selb pg3 0.01fF
+C54 pg1 vdd 0.84fF
+C55 sel3 vctrl 0.37fF
+C56 ng1 sel1 0.04fF
+C57 net6 out 0.01fF
+C58 vco_switch_n_v2_0/selb vdd 0.02fF
+C59 ng2 net8 0.02fF
+C60 vgp sel1 1.27fF
+C61 ng3 vco_switch_n_v2_2/selb 0.04fF
+C62 sel3 vco_switch_n_v2_3/selb 0.26fF
+C63 sel0 vdd 0.04fF
+C64 net3 net8 0.02fF
+C65 pg3 vgp 0.24fF
+C66 net8 vctrl 0.01fF
+C67 sel0 vco_switch_n_v2_0/selb 0.05fF
+C68 ng3 ng1 0.02fF
+C69 pg0 sel1 0.37fF
+C70 vco_switch_p_0/selb vgp 0.01fF
+C71 sel3 pg2 0.50fF
+C72 vctrl sel1 0.90fF
+C73 net6 net7 0.20fF
+C74 net4 vdd 0.19fF
+C75 sel3 pg1 0.10fF
+C76 sel3 vdd 5.08fF
+C77 sel2 vco_switch_p_1/selb 0.05fF
+C78 sel3 vco_switch_n_v2_0/selb 0.02fF
+C79 ng3 ng2 0.40fF
+C80 vco_switch_p_0/selb pg0 0.02fF
+C81 net7 net5 0.01fF
+C82 vco_switch_p_1/selb net2 0.00fF
+C83 sel3 sel0 0.84fF
+C84 ng3 vctrl 0.25fF
+C85 sel2 ng0 0.24fF
+C86 vco_switch_p_2/selb vco_switch_p_1/selb 0.00fF
+C87 vco_switch_n_v2_3/selb ng3 0.02fF
+C88 sel1 pg1 0.14fF
+C89 sel1 vdd 1.30fF
+C90 pg3 pg2 0.34fF
+C91 sel1 vco_switch_n_v2_0/selb 0.20fF
+C92 vco_switch_p_1/selb vgp 0.01fF
+C93 pg3 pg1 0.02fF
+C94 pg3 vdd 1.67fF
+C95 ng0 vco_switch_n_v2_1/selb 0.06fF
+C96 ng1 ng0 0.12fF
+C97 sel0 sel1 3.63fF
+C98 net8 net4 0.01fF
+C99 ng3 vdd 0.30fF
+C100 vco_switch_p_1/selb pg0 0.05fF
+C101 sel2 net2 0.00fF
+C102 vco_switch_p_0/selb vdd 0.02fF
+C103 out vdd 0.81fF
+C104 sel2 vco_switch_n_v2_2/selb 0.21fF
+C105 vco_switch_p_2/selb sel2 0.11fF
+C106 ng2 ng0 0.01fF
+C107 net6 net5 0.05fF
+C108 sel2 vco_switch_n_v2_1/selb 0.05fF
+C109 sel3 sel1 2.04fF
+C110 sel0 vco_switch_p_0/selb 0.03fF
+C111 sel2 ng1 0.27fF
+C112 net5 net2 0.18fF
+C113 net3 ng0 0.00fF
+C114 vctrl ng0 1.74fF
+C115 sel2 vgp 1.47fF
+C116 sel3 pg3 0.27fF
+C117 vco_switch_n_v2_2/selb vco_switch_n_v2_1/selb 0.00fF
+C118 ng1 vco_switch_n_v2_2/selb 0.06fF
+C119 ng3 net4 0.00fF
+C120 vgp net2 0.04fF
+C121 sel3 ng3 0.04fF
+C122 net7 vdd 0.84fF
+C123 sel2 ng2 0.06fF
+C124 sel3 vco_switch_p_0/selb 0.01fF
+C125 vco_switch_p_2/selb vco_switch_p_3/selb 0.00fF
+C126 sel2 pg0 0.43fF
+C127 vco_switch_p_2/selb vgp 0.01fF
+C128 ng1 vco_switch_n_v2_1/selb 0.03fF
+C129 net5 vgp 0.02fF
+C130 vco_switch_p_1/selb pg1 0.02fF
+C131 vco_switch_p_1/selb vdd 0.02fF
+C132 sel2 vctrl 0.41fF
+C133 net2 pg0 0.17fF
+C134 ng3 net8 0.05fF
+C135 ng2 vco_switch_n_v2_2/selb 0.03fF
+C136 vco_switch_p_3/selb vgp 0.01fF
+C137 net3 net2 0.02fF
+C138 ng0 vdd 0.11fF
+C139 ng0 vco_switch_n_v2_0/selb 0.03fF
+C140 vco_switch_n_v2_2/selb vctrl 0.08fF
+C141 ng2 ng1 0.08fF
+C142 net3 net5 0.17fF
+C143 vco_switch_p_0/selb sel1 0.17fF
+C144 sel0 ng0 0.04fF
+C145 vctrl vco_switch_n_v2_1/selb 0.09fF
+C146 vco_switch_n_v2_3/selb vco_switch_n_v2_2/selb 0.00fF
+C147 vgp pg0 2.03fF
+C148 ng1 vctrl 0.62fF
+C149 sel2 pg2 0.26fF
+C150 sel3 vco_switch_p_1/selb 0.01fF
+C151 vgp vctrl 0.00fF
+C152 sel2 pg1 0.51fF
+C153 sel2 vdd 2.00fF
+C154 net6 vdd 0.13fF
+C155 sel2 vco_switch_n_v2_0/selb 0.05fF
+C156 net2 pg2 0.02fF
+C157 sel3 ng0 0.02fF
+C158 net2 pg1 0.00fF
+C159 ng2 vctrl 1.22fF
+C160 vco_switch_p_2/selb pg2 0.02fF
+C161 net2 vdd 4.18fF
+C162 sel0 sel2 1.72fF
+C163 vco_switch_n_v2_2/selb vdd 0.02fF
+C164 vco_switch_p_2/selb pg1 0.05fF
+C165 vco_switch_p_2/selb vdd 0.02fF
+C166 net5 vdd 0.47fF
+C167 net6 vss 0.58fF
+C168 vco_switch_p_3/selb vss -0.05fF
+C169 pg3 vss 0.32fF
+C170 vco_switch_p_1/selb vss -0.05fF
+C171 sel1 vss 0.89fF
+C172 pg1 vss -0.19fF
+C173 vco_switch_p_2/selb vss -0.05fF
+C174 sel2 vss 1.03fF
+C175 pg2 vss -0.55fF
+C176 vco_switch_p_0/selb vss -0.05fF
+C177 sel0 vss 2.16fF
+C178 pg0 vss -0.94fF
+C179 net4 vss 0.55fF
+C180 net3 vss 0.32fF
+C181 net5 vss 1.96fF
+C182 net2 vss -1.31fF
+C183 sel3 vss 0.68fF
+C184 vco_switch_n_v2_3/selb vss 0.60fF
+C185 ng3 vss 2.57fF
+C186 vco_switch_n_v2_2/selb vss 0.66fF
+C187 ng2 vss 1.74fF
+C188 vco_switch_n_v2_1/selb vss 0.65fF
+C189 vdd vss 18.02fF
+C190 ng1 vss 1.14fF
+C191 vctrl vss 5.22fF
+C192 vco_switch_n_v2_0/selb vss 0.65fF
+C193 ng0 vss 2.03fF
+C194 net8 vss 5.56fF
+C195 vgp vss -1.62fF
+C196 out vss -0.22fF
+C197 net7 vss 0.55fF
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128 vdd vss vsel0 vsel1 vsel2 vsel3 out_div256
+XFD_v2_3 vdd vss FD_v2_4/Clk_In FD_v2_3/7 FD_v2_3/5 FD_v2_3/4 FD_v2_3/3 FD_v2_3/Clkb
++ FD_v2_3/6 FD_v2_3/Clk_In FD_v2_3/2 FD_v2
+XFD_v2_4 vdd vss FD_v2_5/Clk_In FD_v2_4/7 FD_v2_4/5 FD_v2_4/4 FD_v2_4/3 FD_v2_4/Clkb
++ FD_v2_4/6 FD_v2_4/Clk_In FD_v2_4/2 FD_v2
+XFD_v2_5 vdd vss FD_v2_6/Clk_In FD_v2_5/7 FD_v2_5/5 FD_v2_5/4 FD_v2_5/3 FD_v2_5/Clkb
++ FD_v2_5/6 FD_v2_5/Clk_In FD_v2_5/2 FD_v2
+XFD_v2_6 vdd vss out_div128 FD_v2_6/7 FD_v2_6/5 FD_v2_6/4 FD_v2_6/3 FD_v2_6/Clkb FD_v2_6/6
++ FD_v2_6/Clk_In FD_v2_6/2 FD_v2
+XFD_v2_7 vdd vss out_div256 FD_v2_7/7 FD_v2_7/5 FD_v2_7/4 FD_v2_7/3 FD_v2_7/Clkb FD_v2_7/6
++ out_div128 FD_v2_7/2 FD_v2
+X3-stage_cs-vco_dp9_0 vdd out vctrl vsel0 vsel1 vsel2 vsel3 3-stage_cs-vco_dp9_0/ng3
++ 3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb vss x3-stage_cs-vco_dp9
+XFD_v2_0 vdd vss FD_v2_1/Clk_In FD_v2_0/7 FD_v2_0/5 FD_v2_0/4 FD_v2_0/3 FD_v2_0/Clkb
++ FD_v2_0/6 out FD_v2_0/2 FD_v2
+XFD_v2_1 vdd vss FD_v2_2/Clk_In FD_v2_1/7 FD_v2_1/5 FD_v2_1/4 FD_v2_1/3 FD_v2_1/Clkb
++ FD_v2_1/6 FD_v2_1/Clk_In FD_v2_1/2 FD_v2
+XFD_v2_2 vdd vss FD_v2_3/Clk_In FD_v2_2/7 FD_v2_2/5 FD_v2_2/4 FD_v2_2/3 FD_v2_2/Clkb
++ FD_v2_2/6 FD_v2_2/Clk_In FD_v2_2/2 FD_v2
+C0 FD_v2_4/6 FD_v2_3/2 0.00fF
+C1 vdd FD_v2_0/7 -0.01fF
+C2 FD_v2_0/Clkb FD_v2_3/5 0.01fF
+C3 FD_v2_2/Clkb FD_v2_1/4 0.01fF
+C4 FD_v2_5/7 FD_v2_2/Clkb 0.04fF
+C5 FD_v2_3/7 FD_v2_4/Clkb 0.04fF
+C6 FD_v2_6/Clkb FD_v2_6/Clk_In 0.01fF
+C7 FD_v2_3/Clk_In FD_v2_4/5 0.01fF
+C8 FD_v2_7/4 FD_v2_4/Clkb 0.01fF
+C9 FD_v2_0/7 FD_v2_1/Clkb 0.00fF
+C10 vdd FD_v2_1/Clkb 0.08fF
+C11 FD_v2_6/6 FD_v2_5/Clk_In 0.02fF
+C12 FD_v2_5/3 FD_v2_2/2 0.00fF
+C13 FD_v2_5/Clk_In FD_v2_6/2 0.00fF
+C14 FD_v2_3/Clk_In FD_v2_4/Clk_In 0.01fF
+C15 FD_v2_4/7 FD_v2_5/Clkb 0.00fF
+C16 FD_v2_3/Clkb FD_v2_3/Clk_In 0.07fF
+C17 FD_v2_2/Clk_In FD_v2_1/7 0.06fF
+C18 FD_v2_1/2 FD_v2_2/Clkb 0.01fF
+C19 FD_v2_7/5 FD_v2_4/4 0.00fF
+C20 FD_v2_5/2 FD_v2_2/3 0.00fF
+C21 FD_v2_5/2 FD_v2_4/7 0.02fF
+C22 FD_v2_4/Clk_In FD_v2_3/5 0.01fF
+C23 FD_v2_1/Clkb FD_v2_2/6 0.04fF
+C24 FD_v2_0/2 FD_v2_3/7 0.01fF
+C25 FD_v2_3/Clkb FD_v2_0/4 0.01fF
+C26 FD_v2_1/Clkb FD_v2_2/4 0.01fF
+C27 FD_v2_7/Clkb FD_v2_4/5 0.01fF
+C28 FD_v2_1/Clk_In FD_v2_2/2 0.00fF
+C29 FD_v2_5/6 FD_v2_2/2 0.00fF
+C30 FD_v2_0/2 FD_v2_3/3 0.00fF
+C31 FD_v2_4/7 FD_v2_3/Clk_In 0.01fF
+C32 FD_v2_5/Clkb FD_v2_2/7 0.04fF
+C33 FD_v2_1/Clk_In FD_v2_3/Clk_In 0.01fF
+C34 FD_v2_6/6 FD_v2_5/3 0.00fF
+C35 FD_v2_5/3 FD_v2_6/2 0.00fF
+C36 FD_v2_4/2 FD_v2_3/Clk_In 0.01fF
+C37 FD_v2_1/Clkb FD_v2_2/5 0.01fF
+C38 FD_v2_5/2 FD_v2_2/Clk_In 0.01fF
+C39 FD_v2_2/Clk_In FD_v2_2/2 0.00fF
+C40 FD_v2_3/Clk_In FD_v2_3/2 0.01fF
+C41 FD_v2_3/Clk_In FD_v2_2/7 0.08fF
+C42 vdd out_div256 0.01fF
+C43 FD_v2_6/Clkb FD_v2_5/Clkb 0.02fF
+C44 FD_v2_5/6 FD_v2_6/3 0.00fF
+C45 FD_v2_2/4 FD_v2_1/5 0.00fF
+C46 FD_v2_6/7 FD_v2_5/Clkb 0.01fF
+C47 FD_v2_3/6 FD_v2_0/4 0.01fF
+C48 FD_v2_1/3 FD_v2_2/2 0.00fF
+C49 FD_v2_4/7 FD_v2_7/Clkb 0.01fF
+C50 out FD_v2_4/Clk_In 0.01fF
+C51 FD_v2_6/Clkb FD_v2_5/2 0.01fF
+C52 FD_v2_0/Clkb FD_v2_3/Clkb 0.02fF
+C53 FD_v2_6/6 out_div128 0.02fF
+C54 FD_v2_3/Clkb FD_v2_0/6 0.04fF
+C55 vdd FD_v2_1/7 0.00fF
+C56 FD_v2_6/7 FD_v2_5/2 0.01fF
+C57 FD_v2_6/4 FD_v2_5/Clkb 0.01fF
+C58 FD_v2_4/2 FD_v2_7/Clkb 0.01fF
+C59 out_div128 FD_v2_7/Clkb 0.07fF
+C60 FD_v2_5/7 FD_v2_2/Clk_In 0.01fF
+C61 FD_v2_5/3 FD_v2_5/Clk_In 0.03fF
+C62 FD_v2_2/Clk_In FD_v2_5/4 0.01fF
+C63 FD_v2_5/6 FD_v2_2/Clkb 0.01fF
+C64 FD_v2_2/3 FD_v2_1/2 0.00fF
+C65 vdd FD_v2_5/Clkb 0.04fF
+C66 FD_v2_4/6 FD_v2_7/4 0.01fF
+C67 FD_v2_1/Clk_In FD_v2_0/6 0.02fF
+C68 FD_v2_6/5 FD_v2_5/Clkb 0.01fF
+C69 FD_v2_1/Clk_In FD_v2_1/2 0.01fF
+C70 FD_v2_4/7 FD_v2_5/Clk_In 0.08fF
+C71 FD_v2_7/Clkb FD_v2_4/Clkb 0.02fF
+C72 FD_v2_5/7 FD_v2_6/Clkb 0.01fF
+C73 FD_v2_0/2 FD_v2_3/Clk_In 0.00fF
+C74 FD_v2_0/Clkb FD_v2_3/2 0.01fF
+C75 FD_v2_3/Clk_In FD_v2_0/7 0.04fF
+C76 FD_v2_2/Clk_In FD_v2_2/Clkb 0.01fF
+C77 FD_v2_6/Clkb FD_v2_5/4 0.01fF
+C78 vdd FD_v2_3/Clk_In 0.07fF
+C79 FD_v2_3/Clkb FD_v2_0/5 0.01fF
+C80 FD_v2_0/Clkb FD_v2_3/6 0.04fF
+C81 out FD_v2_3/2 0.00fF
+C82 out_div128 FD_v2_5/Clk_In 0.01fF
+C83 FD_v2_1/2 FD_v2_2/7 0.01fF
+C84 FD_v2_2/Clk_In FD_v2_1/2 0.00fF
+C85 out FD_v2_3/6 0.02fF
+C86 FD_v2_5/Clkb FD_v2_2/6 0.01fF
+C87 FD_v2_6/7 FD_v2_7/Clkb 0.00fF
+C88 FD_v2_5/Clk_In FD_v2_2/7 0.01fF
+C89 FD_v2_1/Clkb FD_v2_2/2 0.01fF
+C90 FD_v2_2/Clkb FD_v2_1/6 0.04fF
+C91 FD_v2_2/Clk_In FD_v2_5/Clk_In 0.01fF
+C92 FD_v2_5/2 FD_v2_2/6 0.00fF
+C93 FD_v2_4/Clk_In FD_v2_7/6 0.02fF
+C94 FD_v2_3/Clk_In FD_v2_2/6 0.02fF
+C95 FD_v2_4/7 FD_v2_3/Clkb 0.04fF
+C96 FD_v2_5/2 FD_v2_6/Clk_In 0.00fF
+C97 FD_v2_6/5 FD_v2_5/4 0.00fF
+C98 vdd FD_v2_7/Clkb 0.04fF
+C99 FD_v2_3/2 FD_v2_4/Clk_In 0.01fF
+C100 FD_v2_6/7 FD_v2_5/Clk_In 0.04fF
+C101 FD_v2_3/Clkb FD_v2_4/2 0.02fF
+C102 FD_v2_2/6 FD_v2_1/4 0.01fF
+C103 FD_v2_7/2 FD_v2_4/Clk_In 0.00fF
+C104 FD_v2_3/Clkb FD_v2_2/7 0.00fF
+C105 FD_v2_7/3 FD_v2_4/2 0.00fF
+C106 FD_v2_7/3 out_div128 0.03fF
+C107 vdd FD_v2_0/Clkb -0.17fF
+C108 FD_v2_0/7 FD_v2_1/2 0.02fF
+C109 vdd FD_v2_0/6 -0.00fF
+C110 FD_v2_4/7 out_div128 0.04fF
+C111 FD_v2_3/3 FD_v2_3/Clk_In 0.03fF
+C112 vdd FD_v2_1/2 0.00fF
+C113 vdd out 0.07fF
+C114 FD_v2_2/Clk_In FD_v2_5/5 0.01fF
+C115 FD_v2_5/7 FD_v2_6/Clk_In 0.06fF
+C116 FD_v2_3/Clk_In FD_v2_4/4 0.01fF
+C117 FD_v2_2/5 FD_v2_1/4 0.00fF
+C118 out_div128 FD_v2_4/2 0.00fF
+C119 vdd FD_v2_5/Clk_In 0.07fF
+C120 FD_v2_1/Clkb FD_v2_2/Clkb 0.02fF
+C121 FD_v2_1/Clk_In FD_v2_2/7 0.04fF
+C122 FD_v2_7/2 FD_v2_4/7 0.01fF
+C123 FD_v2_6/Clk_In FD_v2_6/2 0.00fF
+C124 FD_v2_4/Clkb FD_v2_7/6 0.04fF
+C125 FD_v2_2/3 FD_v2_1/6 0.00fF
+C126 FD_v2_3/6 FD_v2_4/2 0.00fF
+C127 FD_v2_0/3 FD_v2_3/2 0.00fF
+C128 FD_v2_7/2 out_div128 0.01fF
+C129 FD_v2_6/Clkb FD_v2_5/5 0.01fF
+C130 FD_v2_3/2 FD_v2_2/7 0.02fF
+C131 FD_v2_1/7 FD_v2_2/2 0.01fF
+C132 FD_v2_3/6 FD_v2_0/3 0.00fF
+C133 FD_v2_1/Clk_In FD_v2_1/3 0.03fF
+C134 FD_v2_4/6 FD_v2_7/Clkb 0.04fF
+C135 FD_v2_6/Clkb FD_v2_5/6 0.04fF
+C136 FD_v2_3/2 FD_v2_4/Clkb 0.02fF
+C137 FD_v2_5/Clk_In FD_v2_2/4 0.01fF
+C138 vdd FD_v2_4/Clk_In 0.20fF
+C139 FD_v2_6/4 FD_v2_5/5 0.00fF
+C140 FD_v2_0/2 FD_v2_3/Clkb 0.01fF
+C141 FD_v2_7/Clkb FD_v2_4/4 0.01fF
+C142 FD_v2_3/6 FD_v2_4/Clkb 0.01fF
+C143 FD_v2_5/Clkb FD_v2_2/2 0.02fF
+C144 FD_v2_3/Clkb FD_v2_0/7 0.01fF
+C145 FD_v2_7/2 FD_v2_4/Clkb 0.01fF
+C146 FD_v2_0/Clkb FD_v2_3/7 0.01fF
+C147 FD_v2_2/Clkb FD_v2_1/5 0.01fF
+C148 FD_v2_2/Clk_In FD_v2_1/6 0.02fF
+C149 FD_v2_6/7 out_div128 0.08fF
+C150 vdd FD_v2_3/Clkb 0.04fF
+C151 FD_v2_7/7 FD_v2_4/Clk_In 0.04fF
+C152 FD_v2_3/7 out 0.04fF
+C153 FD_v2_7/6 FD_v2_4/3 0.00fF
+C154 FD_v2_6/4 FD_v2_5/6 0.01fF
+C155 FD_v2_3/3 FD_v2_0/6 0.00fF
+C156 FD_v2_5/Clk_In FD_v2_2/5 0.01fF
+C157 FD_v2_6/7 FD_v2_7/2 0.02fF
+C158 FD_v2_0/Clkb FD_v2_3/4 0.01fF
+C159 vdd FD_v2_4/7 0.01fF
+C160 FD_v2_1/Clk_In FD_v2_0/7 0.08fF
+C161 FD_v2_4/6 FD_v2_5/Clk_In 0.02fF
+C162 FD_v2_3/4 FD_v2_0/6 0.01fF
+C163 vdd FD_v2_1/Clk_In 0.08fF
+C164 FD_v2_7/5 FD_v2_4/Clkb 0.01fF
+C165 FD_v2_3/2 FD_v2_4/3 0.00fF
+C166 vdd out_div128 0.07fF
+C167 FD_v2_0/7 FD_v2_3/2 0.01fF
+C168 FD_v2_6/6 FD_v2_5/Clkb 0.04fF
+C169 FD_v2_4/5 FD_v2_7/4 0.00fF
+C170 FD_v2_6/2 FD_v2_5/Clkb 0.01fF
+C171 FD_v2_7/2 FD_v2_4/3 0.00fF
+C172 FD_v2_2/Clkb FD_v2_1/7 0.01fF
+C173 vdd FD_v2_2/7 0.01fF
+C174 FD_v2_4/2 FD_v2_7/7 0.01fF
+C175 FD_v2_5/2 FD_v2_6/3 0.00fF
+C176 FD_v2_1/Clk_In FD_v2_1/Clkb 0.07fF
+C177 vdd FD_v2_2/Clk_In -0.00fF
+C178 FD_v2_3/7 FD_v2_4/Clk_In 0.01fF
+C179 FD_v2_1/Clk_In FD_v2_2/6 0.02fF
+C180 FD_v2_0/4 FD_v2_3/5 0.00fF
+C181 FD_v2_1/Clkb FD_v2_2/7 0.01fF
+C182 vdd FD_v2_1/6 0.00fF
+C183 FD_v2_3/4 FD_v2_0/5 0.00fF
+C184 FD_v2_4/6 FD_v2_3/Clkb 0.01fF
+C185 FD_v2_7/7 FD_v2_4/Clkb 0.01fF
+C186 FD_v2_4/Clk_In FD_v2_3/4 0.01fF
+C187 FD_v2_6/Clk_In FD_v2_5/6 0.02fF
+C188 FD_v2_5/2 FD_v2_2/Clkb 0.02fF
+C189 FD_v2_4/Clk_In out_div256 0.01fF
+C190 FD_v2_4/6 FD_v2_7/3 0.00fF
+C191 FD_v2_6/7 vdd 0.01fF
+C192 FD_v2_5/Clk_In FD_v2_5/Clkb 0.07fF
+C193 FD_v2_5/7 FD_v2_6/2 0.01fF
+C194 FD_v2_3/Clk_In FD_v2_0/6 0.02fF
+C195 FD_v2_7/6 FD_v2_4/4 0.01fF
+C196 FD_v2_6/6 FD_v2_5/4 0.01fF
+C197 FD_v2_5/2 FD_v2_5/Clk_In 0.01fF
+C198 FD_v2_2/4 FD_v2_1/6 0.01fF
+C199 FD_v2_1/3 FD_v2_2/6 0.00fF
+C200 FD_v2_4/6 out_div128 0.02fF
+C201 FD_v2_5/Clk_In FD_v2_2/2 0.01fF
+C202 FD_v2_3/3 FD_v2_4/2 0.00fF
+C203 FD_v2_0/2 vdd -0.09fF
+C204 FD_v2_2/Clkb vss 1.00fF
+C205 FD_v2_2/7 vss 0.50fF
+C206 FD_v2_2/5 vss 0.13fF
+C207 FD_v2_2/Clk_In vss 1.46fF
+C208 FD_v2_2/3 vss 0.03fF
+C209 FD_v2_2/2 vss 0.93fF
+C210 FD_v2_2/6 vss 0.83fF
+C211 FD_v2_2/4 vss 0.09fF
+C212 FD_v2_1/Clkb vss 1.02fF
+C213 FD_v2_1/7 vss 0.48fF
+C214 FD_v2_1/5 vss 0.13fF
+C215 FD_v2_1/Clk_In vss 1.11fF
+C216 FD_v2_1/3 vss 0.03fF
+C217 FD_v2_1/2 vss 0.93fF
+C218 FD_v2_1/6 vss 0.83fF
+C219 FD_v2_1/4 vss 0.09fF
+C220 FD_v2_0/Clkb vss 1.00fF
+C221 FD_v2_0/7 vss 0.50fF
+C222 FD_v2_0/5 vss 0.13fF
+C223 out vss 0.79fF
+C224 FD_v2_0/3 vss 0.03fF
+C225 FD_v2_0/2 vss 0.93fF
+C226 FD_v2_0/6 vss 0.83fF
+C227 FD_v2_0/4 vss 0.09fF
+C228 3-stage_cs-vco_dp9_0/net6 vss 0.15fF
+C229 3-stage_cs-vco_dp9_0/vco_switch_p_3/selb vss -0.05fF
+C230 3-stage_cs-vco_dp9_0/pg3 vss 0.36fF
+C231 3-stage_cs-vco_dp9_0/vco_switch_p_1/selb vss -0.05fF
+C232 vsel1 vss 1.04fF
+C233 3-stage_cs-vco_dp9_0/pg1 vss -0.14fF
+C234 3-stage_cs-vco_dp9_0/vco_switch_p_2/selb vss -0.05fF
+C235 vsel2 vss 1.17fF
+C236 3-stage_cs-vco_dp9_0/pg2 vss -0.51fF
+C237 3-stage_cs-vco_dp9_0/vco_switch_p_0/selb vss -0.05fF
+C238 vsel0 vss 2.33fF
+C239 3-stage_cs-vco_dp9_0/pg0 vss -0.91fF
+C240 3-stage_cs-vco_dp9_0/net4 vss 0.31fF
+C241 3-stage_cs-vco_dp9_0/net3 vss -0.06fF
+C242 3-stage_cs-vco_dp9_0/net5 vss 1.34fF
+C243 3-stage_cs-vco_dp9_0/net2 vss -1.31fF
+C244 vsel3 vss 0.79fF
+C245 3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb vss 0.60fF
+C246 3-stage_cs-vco_dp9_0/ng3 vss 2.39fF
+C247 3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb vss 0.60fF
+C248 3-stage_cs-vco_dp9_0/ng2 vss 1.48fF
+C249 3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb vss 0.60fF
+C250 vdd vss 36.98fF
+C251 3-stage_cs-vco_dp9_0/ng1 vss 0.82fF
+C252 vctrl vss 2.99fF
+C253 3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb vss 0.60fF
+C254 3-stage_cs-vco_dp9_0/ng0 vss 1.67fF
+C255 3-stage_cs-vco_dp9_0/net8 vss 3.38fF
+C256 3-stage_cs-vco_dp9_0/vgp vss -2.11fF
+C257 3-stage_cs-vco_dp9_0/net7 vss 0.02fF
+C258 FD_v2_7/Clkb vss 1.02fF
+C259 FD_v2_7/7 vss 0.48fF
+C260 out_div256 vss 0.18fF
+C261 FD_v2_7/5 vss 0.13fF
+C262 out_div128 vss 1.13fF
+C263 FD_v2_7/3 vss 0.03fF
+C264 FD_v2_7/2 vss 0.93fF
+C265 FD_v2_7/6 vss 0.83fF
+C266 FD_v2_7/4 vss 0.09fF
+C267 FD_v2_6/Clkb vss 1.00fF
+C268 FD_v2_6/7 vss 0.50fF
+C269 FD_v2_6/5 vss 0.13fF
+C270 FD_v2_6/Clk_In vss 1.46fF
+C271 FD_v2_6/3 vss 0.03fF
+C272 FD_v2_6/2 vss 0.93fF
+C273 FD_v2_6/6 vss 0.83fF
+C274 FD_v2_6/4 vss 0.09fF
+C275 FD_v2_5/Clkb vss 1.02fF
+C276 FD_v2_5/7 vss 0.48fF
+C277 FD_v2_5/5 vss 0.13fF
+C278 FD_v2_5/Clk_In vss 1.12fF
+C279 FD_v2_5/3 vss 0.03fF
+C280 FD_v2_5/2 vss 0.93fF
+C281 FD_v2_5/6 vss 0.83fF
+C282 FD_v2_5/4 vss 0.09fF
+C283 FD_v2_4/Clkb vss 1.00fF
+C284 FD_v2_4/7 vss 0.50fF
+C285 FD_v2_4/5 vss 0.13fF
+C286 FD_v2_4/Clk_In vss 1.94fF
+C287 FD_v2_4/3 vss 0.03fF
+C288 FD_v2_4/2 vss 0.93fF
+C289 FD_v2_4/6 vss 0.83fF
+C290 FD_v2_4/4 vss 0.09fF
+C291 FD_v2_3/Clkb vss 1.02fF
+C292 FD_v2_3/7 vss 0.48fF
+C293 FD_v2_3/5 vss 0.13fF
+C294 FD_v2_3/Clk_In vss 1.13fF
+C295 FD_v2_3/3 vss 0.03fF
+C296 FD_v2_3/2 vss 0.93fF
+C297 FD_v2_3/6 vss 0.83fF
+C298 FD_v2_3/4 vss 0.09fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.ext b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.ext
new file mode 100755
index 0000000..aad1822
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.ext
@@ -0,0 +1,531 @@
+timestamp 1647369436
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use FD_v2 FD_v2_8 -1 0 5933 0 -1 -1307
+use FD_v2 FD_v2_9 -1 0 4118 0 -1 -1307
+use FD_v2 FD_v2_4 1 0 2167 0 1 11
+use FD_v2 FD_v2_5 1 0 3982 0 1 11
+use FD_v2 FD_v2_2 -1 0 5933 0 -1 -29
+use FD_v2 FD_v2_3 -1 0 4118 0 -1 -29
+use FD_v2 FD_v2_7 -1 0 7748 0 -1 -1307
+use FD_v2 FD_v2_6 1 0 5797 0 1 11
+use FD_v2 FD_v2_1 -1 0 7748 0 -1 -29
+use FD_v5_lasttry FD_v5_lasttry_0 1 0 2617 0 1 1451
+use 3-stage_cs-vco_dp9 3-stage_cs-vco_dp9_0 1 0 25 0 1 226
+port "out_div256" 9 5865 -968 5891 -947 m1
+port "vctrl" 1 -1702 -522 -1659 -476 m1
+port "out_div128" 2 7700 -966 7726 -949 m1
+port "vsel3" 8 -1161 1449 -1138 1475 m1
+port "vsel2" 7 -1248 1534 -1225 1560 m1
+port "vsel1" 6 -1330 1605 -1307 1631 m1
+port "vsel0" 5 -1407 1757 -1384 1783 m1
+port "vss" 4 1994 2427 2051 2461 m1
+port "vdd" 3 1732 2426 1789 2460 m1
+node "m1_1702_n1381#" 6 2973.88 1702 -1381 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 726882 12202 0 0 0 0 0 0 0 0 0 0
+node "out_div256" 0 46.3475 5865 -968 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2550 218 0 0 0 0 0 0 0 0 0 0
+node "m1_1968_n677#" 1 175.146 1968 -677 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22824 782 0 0 0 0 0 0 0 0 0 0
+node "vctrl" 0 60.2106 -1702 -522 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4324 280 0 0 0 0 0 0 0 0 0 0
+node "out_div128" 3 331.101 7700 -966 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24956 1536 0 0 0 0 0 0 0 0 0 0
+node "m1_1729_n38#" 1 287.448 1729 -38 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29348 1128 6084 312 4900 280 0 0 0 0 0 0
+node "m1_2161_286#" 2 407.61 2161 286 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12280 656 10008 568 44956 1614 0 0 0 0 0 0
+node "m1_1989_595#" 1 176.155 1989 595 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 632 6084 312 4900 280 0 0 0 0 0 0
+node "m1_2235_659#" 19 2171 2235 659 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 167869 10058 0 0 0 0 0 0 0 0 0 0
+node "m1_7680_300#" 4 641.318 7680 300 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65090 2922 0 0 0 0 0 0 0 0 0 0
+node "vsel3" 0 25.6106 -1161 1449 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "m1_1704_1531#" 4 2865.5 1704 1531 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 941130 10994 0 0 0 0 0 0 0 0 0 0
+node "vsel2" 0 25.6106 -1248 1534 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel1" 0 25.6106 -1330 1605 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel0" 0 24.3208 -1407 1757 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 832 116 0 0 0 0 0 0 0 0 0 0
+node "vss" 0 46.009 1994 2427 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2660 216 0 0 0 0 0 0 0 0 0 0
+node "vdd" 0 46.009 1732 2426 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2660 216 0 0 0 0 0 0 0 0 0 0
+node "out" 216 332.429 1728 1040 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28280 1494 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "w_7680_300#" 0 0 7680 300 pw 2116 184 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_2161_286#" "m1_1968_n677#" 11.6298
+cap "out_div256" "m1_1702_n1381#" 11.8421
+cap "m1_2161_286#" "m1_2235_659#" 6.15635
+cap "m1_2161_286#" "m1_1989_595#" 13.7037
+cap "m1_1729_n38#" "m1_2161_286#" 86.0176
+cap "vss" "vdd" 8.39378
+cap "m1_2235_659#" "m1_1989_595#" 1.53409
+cap "FD_v2_4/Clk_In" "FD_v2_9/Clk_Out" 5.56034
+cap "FD_v2_4/Clk_In" "FD_v2_9/GND" 283.398
+cap "FD_v2_9/VDD" "FD_v2_9/GND" 150.42
+cap "FD_v2_4/Clk_In" "FD_v2_9/7" 17.6172
+cap "FD_v2_3/7" "FD_v2_4/Clkb" 7.83799
+cap "FD_v2_4/Clk_In" "FD_v2_9/VDD" 45.6595
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "FD_v2_9/GND" -1.13687e-13
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/out" "FD_v2_9/GND" -4.26326e-13
+cap "FD_v2_9/GND" "FD_v2_4/Clkb" 0.967742
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "FD_v2_9/GND" -2.84217e-14
+cap "FD_v2_3/7" "FD_v2_4/Clk_In" 2.36301
+cap "FD_v2_8/GND" "FD_v2_8/Clk_Out" 6.24324
+cap "FD_v2_4/6" "FD_v2_9/3" 0.225256
+cap "FD_v2_4/Clk_Out" "FD_v2_4/7" 20.9464
+cap "FD_v2_4/6" "FD_v2_3/2" 1.85484
+cap "FD_v2_4/Clkb" "FD_v2_3/6" 5.7415
+cap "FD_v2_4/2" "FD_v2_2/Clk_Out" 2.70235
+cap "FD_v2_9/Clkb" "FD_v2_4/2" 5.83099
+cap "FD_v2_4/Clkb" "FD_v2_9/Clkb" 22.4636
+cap "FD_v2_9/7" "FD_v2_4/Clkb" 7.75281
+cap "FD_v2_9/7" "FD_v2_4/2" 5.39062
+cap "FD_v2_8/Clk_Out" "FD_v2_4/2" 0.509915
+cap "FD_v2_9/6" "FD_v2_4/Clk_In" 23.9259
+cap "FD_v2_4/5" "FD_v2_9/Clkb" 7.25201
+cap "FD_v2_4/Clk_In" "FD_v2_3/5" 4.74368
+cap "FD_v2_3/2" "FD_v2_4/3" 1.74022
+cap "FD_v2_4/5" "FD_v2_2/Clk_Out" 4.74368
+cap "FD_v2_9/2" "FD_v2_4/6" 3.48485
+cap "FD_v2_4/Clkb" "FD_v2_8/GND" 0.344388
+cap "FD_v2_4/2" "FD_v2_3/3" 1.74022
+cap "FD_v2_9/2" "FD_v2_4/7" 5.39062
+cap "FD_v2_2/Clk_Out" "FD_v2_4/4" 5.3023
+cap "FD_v2_9/Clkb" "FD_v2_4/4" 7.72024
+cap "FD_v2_9/2" "FD_v2_4/3" 0.935223
+cap "FD_v2_4/6" "FD_v2_9/Clkb" 40.7705
+cap "FD_v2_4/6" "FD_v2_8/Clk_Out" 23.9259
+cap "FD_v2_4/Clkb" "FD_v2_9/5" 7.25201
+cap "FD_v2_4/Clkb" "FD_v2_9/6" 40.7705
+cap "FD_v2_9/6" "FD_v2_4/2" 3.48485
+cap "FD_v2_4/7" "FD_v2_9/Clkb" 7.75281
+cap "FD_v2_4/7" "FD_v2_2/Clk_Out" 3.28571
+cap "FD_v2_4/7" "FD_v2_8/Clk_Out" 27.0396
+cap "FD_v2_8/VDD" "FD_v2_8/Clk_Out" 8.47297
+cap "FD_v2_3/7" "FD_v2_4/Clk_In" 3.28571
+cap "FD_v2_3/4" "FD_v2_4/Clk_In" 5.3023
+cap "FD_v2_4/7" "FD_v2_8/GND" 6.90698
+cap "FD_v2_9/5" "FD_v2_4/4" 2.68702
+cap "FD_v2_8/Clk_Out" "FD_v2_9/3" 17.1875
+cap "FD_v2_9/6" "FD_v2_4/4" 5.70992
+cap "FD_v2_4/Clk_In" "FD_v2_3/2" 2.70235
+cap "FD_v2_4/Clkb" "FD_v2_9/4" 7.72024
+cap "FD_v2_4/7" "FD_v2_4/VDD" 7.2907
+cap "FD_v2_3/Clkb" "FD_v2_4/2" 7.89894
+cap "FD_v2_3/7" "FD_v2_4/Clkb" 10.7367
+cap "FD_v2_4/5" "FD_v2_9/4" 2.68702
+cap "FD_v2_9/2" "FD_v2_4/Clk_In" 0.509915
+cap "FD_v2_4/2" "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n15_n133#" 1.85484
+cap "FD_v2_9/2" "FD_v2_8/Clk_Out" 2.94658
+cap "FD_v2_9/6" "FD_v2_4/3" 0.225256
+cap "FD_v2_5/Clkb" "FD_v2_8/GND" 5.37209
+cap "FD_v2_4/2" "FD_v2_9/3" 0.935223
+cap "FD_v2_4/Clkb" "FD_v2_3/2" 7.89894
+cap "FD_v2_4/6" "FD_v2_9/4" 5.70992
+cap "FD_v2_4/Clk_In" "FD_v2_2/Clk_Out" 7.13793
+cap "FD_v2_9/2" "FD_v2_8/7" 11.2469
+cap "FD_v2_9/7" "FD_v2_4/Clk_In" 19.6441
+cap "FD_v2_4/6" "FD_v2_3/Clkb" 5.7415
+cap "FD_v2_5/Clkb" "FD_v2_4/VDD" 8.34593
+cap "FD_v2_4/Clk_Out" "FD_v2_4/6" 9.37221
+cap "FD_v2_9/2" "FD_v2_4/Clkb" 5.83099
+cap "FD_v2_4/7" "FD_v2_3/Clkb" 14.2118
+cap "FD_v2_4/Clk_In" "FD_v2_8/GND" 2.64031
+cap "FD_v2_4/Clk_Out" "FD_v2_8/2" 0.509915
+cap "FD_v2_2/2" "FD_v2_5/3" 1.74022
+cap "FD_v2_8/GND" "FD_v2_9/Clkb" 24.3324
+cap "FD_v2_2/7" "FD_v2_4/Clk_Out" 5.64873
+cap "FD_v2_8/GND" "FD_v2_4/7" 6.90698
+cap "FD_v2_4/Clk_Out" "FD_v2_5/Clkb" 71.7391
+cap "FD_v2_5/2" "FD_v2_4/7" 22.4939
+cap "FD_v2_4/Clk_Out" "FD_v2_4/sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" 9.37221
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_4/Clk_Out" 7.13793
+cap "FD_v2_4/Clk_Out" "FD_v2_8/Clk_Out" 11.1207
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_5/4" 5.3023
+cap "FD_v2_5/Clkb" "FD_v2_8/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 22.4636
+cap "FD_v2_2/Clk_Out" "FD_v2_4/VDD" -8.88178e-16
+cap "FD_v2_5/5" "FD_v2_8/4" 2.68702
+cap "FD_v2_8/5" "FD_v2_5/Clkb" 7.25201
+cap "FD_v2_4/Clk_Out" "FD_v2_2/4" 5.3023
+cap "FD_v2_4/VDD" "FD_v2_5/Clkb" 29.4562
+cap "FD_v2_2/Clk_Out" "FD_v2_4/7" 2.36301
+cap "FD_v2_8/7" "FD_v2_8/GND" 13.814
+cap "FD_v2_8/VDD" "FD_v2_8/Clk_Out" 60.723
+cap "FD_v2_5/4" "FD_v2_8/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 7.72024
+cap "FD_v2_5/2" "FD_v2_8/7" 5.39062
+cap "FD_v2_8/5" "FD_v2_5/4" 2.68702
+cap "FD_v2_5/Clkb" "FD_v2_4/7" 4.45238
+cap "FD_v2_4/Clk_Out" "FD_v2_4/VDD" 69.1959
+cap "FD_v2_3/Clkb" "FD_v2_4/7" 4.36285
+cap "FD_v2_8/6" "FD_v2_5/3" 0.225256
+cap "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_8/7" 11.2469
+cap "FD_v2_8/Clk_Out" "FD_v2_9/Clkb" 71.7391
+cap "FD_v2_2/2" "FD_v2_5/Clkb" 7.89894
+cap "FD_v2_8/Clk_Out" "FD_v2_4/7" 10.2216
+cap "FD_v2_8/2" "FD_v2_5/3" 0.935223
+cap "FD_v2_4/Clk_Out" "FD_v2_4/7" 61.1363
+cap "FD_v2_4/Clk_Out" "FD_v2_2/2" 2.70235
+cap "FD_v2_8/4" "FD_v2_5/Clkb" 7.72024
+cap "FD_v2_5/Clkb" "FD_v2_8/7" 7.75281
+cap "FD_v2_8/Clk_Out" "FD_v2_9/3" 17.1875
+cap "FD_v2_8/6" "FD_v2_5/2" 3.48485
+cap "FD_v2_8/VDD" "FD_v2_9/Clkb" 37.8022
+cap "FD_v2_5/6" "FD_v2_8/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 8.54829
+cap "FD_v2_8/Clk_Out" "FD_v2_8/7" 80.363
+cap "FD_v2_2/6" "FD_v2_5/Clkb" 5.7415
+cap "FD_v2_4/VDD" "FD_v2_4/7" 7.2907
+cap "FD_v2_4/Clk_Out" "FD_v2_2/5" 4.74368
+cap "FD_v2_4/Clk_Out" "FD_v2_5/3" 34.375
+cap "FD_v2_5/Clkb" "FD_v2_8/GND" 18.9603
+cap "FD_v2_4/Clk_Out" "FD_v2_8/7" 37.2612
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_5/5" 4.74368
+cap "FD_v2_8/Clk_Out" "FD_v2_8/GND" 49.6632
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_5/2" 2.70235
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n15_n133#" "FD_v2_5/2" 1.85484
+cap "FD_v2_8/6" "FD_v2_5/Clkb" 40.7705
+cap "FD_v2_4/Clk_Out" "FD_v2_8/GND" 55.9065
+cap "FD_v2_8/VDD" "FD_v2_8/7" 14.5814
+cap "FD_v2_4/Clk_Out" "FD_v2_5/2" 5.89315
+cap "FD_v2_5/5" "FD_v2_8/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 7.25201
+cap "FD_v2_8/6" "FD_v2_8/Clk_Out" 18.7444
+cap "FD_v2_8/2" "FD_v2_5/Clkb" 5.83099
+cap "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_8/Clk_Out" 2.94658
+cap "FD_v2_4/Clk_Out" "FD_v2_8/6" 23.9259
+cap "FD_v2_8/7" "FD_v2_9/Clkb" 4.45238
+cap "FD_v2_8/6" "FD_v2_5/4" 5.70992
+cap "FD_v2_5/2" "FD_v2_8/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 5.83099
+cap "FD_v2_2/7" "FD_v2_5/Clkb" 18.5747
+cap "FD_v2_8/4" "FD_v2_5/6" 2.85496
+cap "FD_v2_8/Clk_In" "FD_v2_8/Clkb" 71.7391
+cap "FD_v2_8/GND" "FD_v2_6/Clkb" 24.3324
+cap "FD_v2_5/7" "FD_v2_8/Clkb" 7.75281
+cap "FD_v2_5/Clk_Out" "FD_v2_1/7" 5.64873
+cap "FD_v2_1/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_6/4" 5.3023
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_5/Clk_Out" 5.89315
+cap "FD_v2_5/6" "FD_v2_8/3" 0.225256
+cap "FD_v2_5/VDD" "FD_v2_2/Clk_In" -4.44089e-16
+cap "FD_v2_5/VDD" "FD_v2_5/Clk_Out" 69.1959
+cap "FD_v2_5/7" "FD_v2_2/Clkb" 18.5747
+cap "FD_v2_8/Clk_In" "FD_v2_8/VDD" 57.3538
+cap "FD_v2_7/7" "FD_v2_6/Clkb" 7.75281
+cap "FD_v2_7/5" "FD_v2_6/4" 2.68702
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_5/7" 22.4939
+cap "FD_v2_8/GND" "FD_v2_8/Clkb" 24.3324
+cap "FD_v2_5/Clk_Out" "FD_v2_7/2" 0.509915
+cap "FD_v2_5/6" "FD_v2_8/Clkb" 32.2222
+cap "FD_v2_6/4" "FD_v2_7/6" 5.70992
+cap "FD_v2_5/VDD" "FD_v2_5/7" 14.5814
+cap "FD_v2_1/2" "FD_v2_6/Clkb" 7.89894
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_7/6" 3.48485
+cap "FD_v2_6/3" "FD_v2_7/2" 0.935223
+cap "FD_v2_8/Clk_In" "FD_v2_8/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.89315
+cap "FD_v2_6/3" "FD_v2_5/Clk_Out" 34.375
+cap "FD_v2_5/7" "FD_v2_8/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.39062
+cap "FD_v2_8/Clkb" "FD_v2_7/7" 4.45238
+cap "FD_v2_5/6" "FD_v2_2/Clkb" 5.7415
+cap "FD_v2_8/Clk_In" "FD_v2_5/Clk_Out" 11.1207
+cap "FD_v2_5/6" "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 1.85484
+cap "FD_v2_5/2" "FD_v2_8/3" 0.935223
+cap "FD_v2_5/6" "FD_v2_8/4" 2.85496
+cap "FD_v2_5/7" "FD_v2_2/Clk_In" 5.64873
+cap "FD_v2_5/7" "FD_v2_5/Clk_Out" 80.363
+cap "FD_v2_7/7" "FD_v2_8/VDD" 14.5814
+cap "FD_v2_5/Clk_Out" "FD_v2_7/6" 23.9259
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_7/7" 5.39062
+cap "FD_v2_5/7" "FD_v2_8/Clk_In" 37.2612
+cap "FD_v2_6/3" "FD_v2_7/6" 0.225256
+cap "FD_v2_5/6" "FD_v2_8/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 3.48485
+cap "FD_v2_1/7" "FD_v2_6/Clkb" 18.5747
+cap "FD_v2_1/6" "FD_v2_6/Clkb" 5.7415
+cap "FD_v2_8/Clk_In" "FD_v2_7/6" 18.7444
+cap "FD_v2_5/Clk_Out" "FD_v2_8/GND" 55.9065
+cap "FD_v2_5/VDD" "FD_v2_6/Clkb" 37.8022
+cap "FD_v2_5/6" "FD_v2_5/Clk_Out" 18.7444
+cap "FD_v2_8/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_7/7" 22.4939
+cap "FD_v2_5/2" "FD_v2_2/Clkb" 7.89894
+cap "FD_v2_8/Clk_In" "FD_v2_8/GND" 55.9065
+cap "FD_v2_5/Clk_Out" "FD_v2_7/7" 37.2612
+cap "FD_v2_8/Clkb" "FD_v2_8/VDD" 37.8022
+cap "FD_v2_8/Clk_In" "FD_v2_5/6" 23.9259
+cap "FD_v2_5/7" "FD_v2_8/GND" 13.814
+cap "FD_v2_5/Clk_Out" "FD_v2_6/Clkb" 71.7391
+cap "FD_v2_7/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v2_6/4" 5.34524
+cap "FD_v2_8/Clk_In" "FD_v2_7/7" 80.363
+cap "FD_v2_5/2" "FD_v2_2/3" 1.74022
+cap "FD_v2_6/3" "FD_v2_1/2" 1.74022
+cap "FD_v2_5/7" "FD_v2_6/Clkb" 4.45238
+cap "FD_v2_8/Clk_In" "FD_v2_8/3" 34.375
+cap "FD_v2_7/6" "FD_v2_6/Clkb" 40.7705
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_1/sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n15_n133#" 1.85484
+cap "FD_v2_8/Clk_In" "FD_v2_5/2" 0.509915
+cap "FD_v2_8/GND" "FD_v2_7/7" 13.814
+cap "FD_v2_6/5" "FD_v2_1/Clk_In" 4.74368
+cap "FD_v2_6/5" "FD_v2_7/4" 2.68702
+cap "FD_v2_7/4" "FD_v2_6/6" 5.70992
+cap "FD_v2_6/7" "FD_v2_7/2" 5.39062
+cap "FD_v2_7/Clk_In" "FD_v2_7/2" 1.13309
+cap "FD_v2_7/3" "FD_v2_6/6" 0.225256
+cap "FD_v2_7/2" "FD_v2_6/a_971_n597#" 5.83099
+cap "FD_v2_7/Clk_In" "FD_v2_7/GND" 62.1429
+cap "FD_v2_7/2" "FD_v2_6/6" 3.48485
+cap "FD_v2_1/Clk_In" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 7.13793
+cap "FD_v2_7/Clkb" "FD_v2_6/2" 5.83099
+cap "FD_v2_1/Clkb" "FD_v2_6/2" 7.89894
+cap "FD_v2_6/4" "FD_v2_7/Clkb" 2.375
+cap "FD_v2_7/Clk_In" "FD_v2_6/2" 0.509915
+cap "FD_v2_6/7" "FD_v2_7/Clkb" 7.75281
+cap "FD_v2_1/Clkb" "FD_v2_6/7" 18.5747
+cap "FD_v2_1/2" "FD_v2_6/6" 1.85484
+cap "FD_v2_7/Clkb" "FD_v2_7/Clk_In" 12.4699
+cap "FD_v2_1/Clk_In" "FD_v2_6/2" 2.70235
+cap "FD_v2_6/7" "FD_v2_7/Clk_In" 64.6411
+cap "FD_v2_7/Clkb" "FD_v2_6/a_971_n597#" 22.4636
+cap "FD_v2_7/Clkb" "FD_v2_6/6" 40.7705
+cap "FD_v2_6/5" "FD_v2_7/Clkb" 7.25201
+cap "FD_v2_1/Clkb" "FD_v2_6/6" 5.7415
+cap "FD_v2_7/3" "FD_v2_6/2" 0.935223
+cap "FD_v2_1/3" "FD_v2_6/2" 1.74022
+cap "FD_v2_1/4" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 5.3023
+cap "FD_v2_1/5" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 4.74368
+cap "FD_v2_7/Clk_In" "FD_v2_6/6" 23.9259
+cap "FD_v2_1/2" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 2.70235
+cap "FD_v2_6/7" "FD_v2_1/Clk_In" 5.64873
+cap "FD_v2_6/a_971_n597#" "FD_v2_7/5" 7.25201
+cap "FD_v2_7/4" "FD_v2_6/a_971_n597#" 7.72024
+cap "FD_v2_4/Clk_In" "FD_v2_4/VDD" 46.1823
+cap "3-stage_cs-vco_dp9_0/vdd" "FD_v2_4/VDD" -0.984
+cap "FD_v2_4/Clkb" "FD_v2_3/7" 7.83799
+cap "3-stage_cs-vco_dp9_0/XM24/a_n76_n129#" "FD_v2_4/VDD" 4.18883
+cap "FD_v2_4/Clk_In" "FD_v2_3/7" 3.45234
+cap "FD_v5_lasttry_0/sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "FD_v5_lasttry_0/Clk_In" 0.438053
+cap "3-stage_cs-vco_dp9_0/XM23/a_n33_310#" "FD_v5_lasttry_0/Clk_In" 0.456221
+cap "FD_v2_4/VDD" "FD_v5_lasttry_0/Clk_In" 22.0188
+cap "FD_v2_4/VDD" "FD_v2_3/GND" 165.031
+cap "3-stage_cs-vco_dp9_0/vdd" "FD_v5_lasttry_0/Clk_In" 31.583
+cap "FD_v2_4/Clk_In" "FD_v2_3/GND" 261.398
+cap "FD_v5_lasttry_0/Clkb_int" "FD_v5_lasttry_0/Clk_In" 1.03321
+cap "FD_v5_lasttry_0/Clkb_int" "FD_v2_3/GND" 6.06486
+cap "FD_v2_3/7" "FD_v5_lasttry_0/Clk_In" 2.14286
+cap "FD_v2_3/7" "FD_v2_3/GND" 6
+cap "FD_v2_3/GND" "FD_v5_lasttry_0/Clk_In" 49.3099
+cap "FD_v2_4/3" "FD_v2_3/2" 1.74022
+cap "FD_v2_3/7" "FD_v2_4/Clk_In" 4.37504
+cap "FD_v2_2/GND" "FD_v5_lasttry_0/Clkb_buf" 16.4195
+cap "FD_v2_2/Clk_Out" "FD_v2_4/5" 4.74368
+cap "FD_v2_2/GND" "FD_v2_3/3" 11.5455
+cap "FD_v2_2/GND" "FD_v2_3/4" 26.0114
+cap "FD_v2_3/6" "FD_v5_lasttry_0/dus" 1.60108
+cap "FD_v2_2/Clk_Out" "FD_v2_2/GND" 20.9595
+cap "FD_v2_4/Clkb" "FD_v2_3/2" 7.89894
+cap "FD_v2_4/7" "FD_v2_2/Clk_Out" 3.28571
+cap "FD_v2_2/GND" "FD_v2_3/7" 6.06486
+cap "FD_v2_3/Clkb" "FD_v2_4/2" 7.89894
+cap "FD_v2_3/Clkb" "FD_v2_4/6" 5.7415
+cap "FD_v2_4/sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" "FD_v2_3/2" 1.85484
+cap "FD_v2_3/6" "FD_v2_2/GND" 37.7137
+cap "FD_v2_3/3" "FD_v2_4/2" 1.74022
+cap "FD_v2_2/Clk_Out" "FD_v2_4/2" 2.70235
+cap "FD_v2_4/Clkb" "FD_v2_3/7" 10.7367
+cap "FD_v2_4/Clk_In" "FD_v2_3/2" 2.70235
+cap "FD_v5_lasttry_0/Clkb_buf" "FD_v2_3/5" 0.540984
+cap "FD_v2_2/Clk_Out" "FD_v2_3/2" 2.94658
+cap "FD_v2_3/5" "FD_v2_4/Clk_In" 4.74368
+cap "FD_v5_lasttry_0/dus" "FD_v2_3/4" 0.142857
+cap "FD_v5_lasttry_0/dus" "FD_v2_2/Clk_Out" 2.63359
+cap "FD_v2_2/Clk_Out" "FD_v2_4/4" 5.3023
+cap "FD_v2_2/GND" "FD_v2_3/2" 11.4432
+cap "FD_v5_lasttry_0/Clkb_buf" "FD_v2_3/3" 2.64
+cap "FD_v2_3/6" "FD_v2_4/Clkb" 5.7415
+cap "FD_v2_2/GND" "FD_v2_3/Clkb" 13.9615
+cap "FD_v2_2/GND" "FD_v2_3/5" 23.9658
+cap "FD_v2_4/VDD" "FD_v2_2/Clk_Out" 8.47297
+cap "FD_v2_3/4" "FD_v2_4/Clk_In" 5.3023
+cap "FD_v5_lasttry_0/dus" "FD_v2_2/GND" 10.9463
+cap "FD_v2_4/7" "FD_v2_3/Clkb" 14.2118
+cap "FD_v2_2/Clk_Out" "FD_v2_4/Clk_In" 7.13793
+cap "FD_v2_2/Clk_Out" "FD_v2_3/3" 17.1875
+cap "FD_v2_2/7" "FD_v2_3/2" 11.2469
+cap "FD_v5_lasttry_0/dus" "FD_v5_lasttry_0/Clk_In" 0.438053
+cap "FD_v2_3/6" "FD_v2_4/2" 1.85484
+cap "FD_v2_4/Clk_Out" "FD_v2_2/7" 5.64873
+cap "FD_v2_2/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v5_lasttry_0/3" 3.34177
+cap "FD_v5_lasttry_0/3" "FD_v2_2/6" 2.18833
+cap "FD_v2_5/Clkb" "FD_v2_2/6" 5.7415
+cap "FD_v5_lasttry_0/3" "FD_v2_2/GND" 91.158
+cap "FD_v2_5/3" "FD_v2_2/2" 1.74022
+cap "FD_v2_3/Clkb" "FD_v2_4/7" 4.36285
+cap "FD_v2_2/5" "FD_v2_2/GND" 23.9658
+cap "FD_v2_2/Clk_Out" "FD_v2_4/7" 2.36301
+cap "FD_v2_5/2" "FD_v2_2/6" 1.85484
+cap "FD_v5_lasttry_0/Clk_In_buf" "FD_v2_2/5" 2.01075
+cap "FD_v2_2/2" "FD_v5_lasttry_0/3" 3.06557
+cap "FD_v2_2/2" "FD_v2_5/Clkb" 7.89894
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_5/5" 4.74368
+cap "FD_v2_2/7" "FD_v2_5/Clkb" 18.5747
+cap "FD_v2_2/Clk_Out" "FD_v2_3/3" 17.1875
+cap "FD_v2_4/VDD" "FD_v2_3/Clkb" 37.8022
+cap "FD_v2_4/VDD" "FD_v2_2/7" 14.5814
+cap "FD_v2_2/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v2_2/GND" 13.9615
+cap "FD_v2_2/6" "FD_v2_2/GND" 37.7137
+cap "FD_v2_4/VDD" "FD_v2_2/Clk_Out" 60.723
+cap "FD_v2_4/Clk_Out" "FD_v2_2/5" 4.74368
+cap "FD_v2_4/Clk_Out" "FD_v2_4/VDD" -2.66454e-15
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_5/2" 2.70235
+cap "FD_v2_2/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v5_lasttry_0/Clk_In_buf" 64.4968
+cap "FD_v5_lasttry_0/Clk_In_buf" "FD_v2_2/6" 40.3918
+cap "FD_v5_lasttry_0/Clk_In_buf" "FD_v2_2/GND" 24.6445
+cap "FD_v2_2/Clk_Out" "FD_v5_lasttry_0/Clkb_buf" 1.78571
+cap "FD_v2_2/4" "FD_v2_2/GND" 19.1818
+cap "FD_v2_2/2" "FD_v2_2/GND" 5.44323
+cap "FD_v2_2/Clk_Out" "FD_v2_2/6" 18.7444
+cap "FD_v2_3/Clkb" "FD_v2_2/GND" 29.5029
+cap "FD_v5_lasttry_0/Clk_In_buf" "FD_v2_2/4" 2.20447
+cap "FD_v2_2/7" "FD_v2_2/GND" 25.8788
+cap "FD_v2_2/Clk_Out" "FD_v2_2/GND" 60.8338
+cap "FD_v2_2/5" "FD_v5_lasttry_0/3" 3.7651
+cap "FD_v2_2/7" "FD_v5_lasttry_0/Clk_In_buf" 7.66667
+cap "FD_v2_2/Clk_Out" "FD_v5_lasttry_0/Clk_In_buf" 7.89641
+cap "FD_v5_lasttry_0/4" "FD_v2_2/GND" 10.9463
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_5/4" 5.3023
+cap "FD_v2_2/6" "FD_v5_lasttry_0/MNinv1/a_n73_37#" 2.14286
+cap "FD_v2_4/Clk_Out" "FD_v2_2/4" 5.3023
+cap "FD_v2_2/7" "FD_v2_3/Clkb" 4.45238
+cap "FD_v2_4/Clk_Out" "FD_v2_2/2" 2.70235
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_2/7" 11.2469
+cap "FD_v2_2/Clk_Out" "FD_v2_3/Clkb" 71.7391
+cap "FD_v2_2/Clk_Out" "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 2.94658
+cap "FD_v2_2/Clk_Out" "FD_v2_2/7" 80.363
+cap "FD_v2_4/Clk_Out" "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 7.13793
+cap "FD_v2_2/GND" "FD_v5_lasttry_0/Clkb_buf" 13.6981
+cap "FD_v5_lasttry_0/MNTgate2/a_15_n163#" "FD_v2_1/6" 2.45093
+cap "FD_v2_2/GND" "FD_v2_1/6" 37.7137
+cap "FD_v2_2/4" "FD_v5_lasttry_0/MNTgate1/a_n73_n163#" 4.36576
+cap "FD_v5_lasttry_0/MNTgate2/a_15_n163#" "FD_v2_1/5" 3.04615
+cap "FD_v5_lasttry_0/Clkb_buf" "FD_v2_1/6" 37.7139
+cap "FD_v2_2/GND" "FD_v2_1/5" 6.46566
+cap "FD_v2_2/GND" "FD_v2_2/Clkb" 29.5029
+cap "FD_v2_2/GND" "FD_v2_2/4" 6.82955
+cap "FD_v2_6/3" "FD_v2_1/2" 1.74022
+cap "FD_v2_2/Clkb" "FD_v2_5/VDD" 37.8022
+cap "FD_v2_2/Clkb" "FD_v2_5/6" 5.7415
+cap "FD_v5_lasttry_0/Clkb_buf" "FD_v2_1/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 7
+cap "FD_v2_6/Clkb" "FD_v2_1/7" 18.5747
+cap "FD_v2_2/Clk_In" "FD_v5_lasttry_0/MNTgate1/a_n73_n163#" 9.51092
+cap "FD_v2_2/Clk_In" "FD_v5_lasttry_0/5" 2.34426
+cap "FD_v2_2/Clk_In" "FD_v2_2/3" 34.375
+cap "FD_v2_2/GND" "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 6
+cap "FD_v2_6/Clkb" "FD_v2_1/2" 7.89894
+cap "FD_v5_lasttry_0/4" "FD_v2_1/7" 1.57143
+cap "FD_v2_2/Clkb" "FD_v2_5/7" 18.5747
+cap "FD_v2_5/2" "FD_v2_2/3" 1.74022
+cap "FD_v2_2/GND" "FD_v5_lasttry_0/a_2222_n669#" 13.6981
+cap "FD_v2_2/Clk_In" "FD_v2_2/GND" 81.7932
+cap "FD_v2_2/GND" "FD_v2_1/7" 25.8788
+cap "FD_v2_2/Clk_In" "FD_v2_1/6" 18.7444
+cap "FD_v2_2/GND" "FD_v2_1/2" 5.44323
+cap "FD_v2_2/Clk_In" "FD_v2_2/Clkb" 71.7391
+cap "FD_v2_2/Clk_In" "FD_v2_5/VDD" 69.1959
+cap "FD_v2_2/Clkb" "FD_v5_lasttry_0/a_2222_n669#" 64.3792
+cap "FD_v5_lasttry_0/Clkb_buf" "FD_v2_1/2" 3.50625
+cap "FD_v2_2/Clkb" "FD_v2_1/7" 4.45238
+cap "FD_v2_1/7" "FD_v2_5/VDD" 14.5814
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_1/6" 1.85484
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 1.85484
+cap "FD_v2_5/2" "FD_v2_2/Clkb" 7.89894
+cap "FD_v2_2/Clk_In" "FD_v2_5/7" 5.64873
+cap "FD_v5_lasttry_0/a_2222_n669#" "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 2.20447
+cap "FD_v2_2/Clk_In" "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.89315
+cap "FD_v5_lasttry_0/MNTgate1/a_n73_n163#" "FD_v2_2/3" 8.13086
+cap "FD_v2_1/7" "FD_v2_2/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 22.4939
+cap "FD_v5_lasttry_0/4" "FD_v2_2/3" 2.03077
+cap "FD_v2_2/Clk_In" "FD_v5_lasttry_0/a_2222_n669#" 81.9701
+cap "FD_v2_2/GND" "FD_v5_lasttry_0/MNTgate1/a_n73_n163#" 97.5547
+cap "FD_v2_2/GND" "FD_v5_lasttry_0/5" 82.0047
+cap "FD_v2_2/GND" "FD_v2_2/3" 11.5455
+cap "FD_v2_2/Clk_In" "FD_v2_1/7" 80.363
+cap "FD_v2_6/Clkb" "FD_v2_1/6" 5.7415
+cap "FD_v2_5/Clk_Out" "FD_v2_1/7" 5.64873
+cap "FD_v2_2/GND" "FD_v5_lasttry_0/4" 10.9463
+cap "FD_v2_1/6" "FD_v5_lasttry_0/5" 7.99683
+cap "FD_v2_1/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_6/4" 5.3023
+cap "FD_v5_lasttry_0/MNTgate2/a_15_n163#" "FD_v2_2/GND" 10.4634
+cap "FD_v2_1/5" "FD_v5_lasttry_0/5" 4.36576
+cap "FD_v2_6/2" "FD_v2_1/3" 1.74022
+cap "FD_v5_lasttry_0/6" "FD_v2_1/5" 2.2541
+cap "FD_v2_1/Clkb" "FD_v5_lasttry_0/Clkb_buf" 77.4225
+cap "FD_v5_lasttry_0/MNTgate2/a_n73_n163#" "FD_v2_1/5" 3.7651
+cap "FD_v2_1/GND" "FD_v2_1/5" 17.5002
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" "FD_v2_1/2" 1.85484
+cap "FD_v2_6/6" "FD_v2_1/Clkb" 5.7415
+cap "FD_v5_lasttry_0/6" "FD_v2_1/GND" 95.6304
+cap "FD_v2_1/3" "FD_v5_lasttry_0/Clkb_buf" 4.02151
+cap "FD_v2_1/GND" "FD_v5_lasttry_0/MNTgate2/a_n73_n163#" 106.708
+cap "FD_v2_1/GND" "FD_v5_lasttry_0/2" 10.9463
+cap "FD_v2_6/7" "FD_v2_1/Clkb" 18.5747
+cap "FD_v2_1/4" "FD_v5_lasttry_0/MNTgate2/a_n73_n163#" 2.95331
+cap "FD_v2_1/2" "FD_v2_1/GND" 41.3478
+cap "FD_v2_1/4" "FD_v2_1/GND" 26.0114
+cap "FD_v5_lasttry_0/6" "FD_v2_1/Clk_In" 45.3525
+cap "FD_v2_1/5" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 4.74368
+cap "FD_v5_lasttry_0/7" "FD_v2_1/Clk_In" 1.94261
+cap "FD_v2_1/GND" "FD_v2_1/Clk_In" 225.424
+cap "FD_v2_1/GND" "FD_v5_lasttry_0/Clkb_buf" 26.1449
+cap "FD_v2_6/2" "FD_v2_1/Clk_In" 2.70235
+cap "FD_v2_1/4" "FD_v5_lasttry_0/Clkb_buf" 2.20447
+cap "FD_v2_1/2" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 2.70235
+cap "FD_v2_6/5" "FD_v2_1/Clk_In" 4.74368
+cap "FD_v2_1/4" "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 5.3023
+cap "FD_v2_1/Clk_In" "FD_v5_lasttry_0/Clkb_buf" 8.29184
+cap "FD_v2_6/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_1/Clk_In" 7.13793
+cap "FD_v5_lasttry_0/MNTgate2/a_n73_n163#" "FD_v2_1/Clkb" 9.18987
+cap "FD_v2_1/GND" "FD_v2_1/Clkb" 94.7242
+cap "FD_v5_lasttry_0/2" "FD_v2_1/Clkb" 1.80328
+cap "FD_v2_1/GND" "FD_v2_1/3" 11.5455
+cap "FD_v2_6/2" "FD_v2_1/Clkb" 7.89894
+cap "FD_v2_6/7" "FD_v2_1/Clk_In" 5.64873
+cap "FD_v2_1/Clk_In" "FD_v5_lasttry_0/7" 1.94261
+cap "FD_v2_6/GND" "FD_v2_1/Clk_In" 63.1358
+cap "FD_v5_lasttry_0/VDD" "3-stage_cs-vco_dp9_0/vco_switch_p_3/sel" 0.114213
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_3/sky130_fd_pr__pfet_01v8_5YXW2B_0/a_18_n72#" "FD_v5_lasttry_0/VDD" 23.3411
+cap "FD_v5_lasttry_0/VDD" "3-stage_cs-vco_dp9_0/vss" 131.444
+cap "3-stage_cs-vco_dp9_0/vdd" "FD_v5_lasttry_0/VDD" 42.568
+merge "FD_v5_lasttry_0/GND" "vss" -4432.33 -1087554 -15742 0 0 0 0 0 0 0 0 -150586 -11366 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -150586 -11366 -201905 -32312 0 0 -4900 -280 0 0 0 0 0 0
+merge "vss" "FD_v2_1/GND"
+merge "FD_v2_1/GND" "m1_1989_595#"
+merge "m1_1989_595#" "m1_2235_659#"
+merge "m1_2235_659#" "FD_v2_6/GND"
+merge "FD_v2_6/GND" "FD_v2_7/GND"
+merge "FD_v2_7/GND" "FD_v2_2/GND"
+merge "FD_v2_2/GND" "FD_v2_5/GND"
+merge "FD_v2_5/GND" "FD_v2_8/GND"
+merge "FD_v2_8/GND" "FD_v2_3/GND"
+merge "FD_v2_3/GND" "FD_v2_4/GND"
+merge "FD_v2_4/GND" "FD_v2_9/GND"
+merge "FD_v2_9/GND" "m1_1968_n677#"
+merge "m1_1968_n677#" "3-stage_cs-vco_dp9_0/vss"
+merge "3-stage_cs-vco_dp9_0/vss" "w_7680_300#"
+merge "FD_v5_lasttry_0/Clk_Out" "FD_v2_1/Clk_In" -294.399 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -398676 -160 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_1/Clk_In" "m1_7680_300#"
+merge "FD_v2_6/Clk_In" "FD_v2_5/Clk_Out" -65.228 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -75120 -68 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_1/Clk_Out" "FD_v2_2/Clk_In" -67.0844 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -77976 -68 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_1/VDD" "vdd" -4678.18 0 0 0 0 -402762 -15270 0 0 -147696 -10386 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -149634 -11366 -455131 -33614 0 0 -6700 -280 0 0 0 0 0 0
+merge "vdd" "FD_v5_lasttry_0/VDD"
+merge "FD_v5_lasttry_0/VDD" "m1_1704_1531#"
+merge "m1_1704_1531#" "FD_v2_6/VDD"
+merge "FD_v2_6/VDD" "FD_v2_7/VDD"
+merge "FD_v2_7/VDD" "FD_v2_2/VDD"
+merge "FD_v2_2/VDD" "FD_v2_5/VDD"
+merge "FD_v2_5/VDD" "FD_v2_8/VDD"
+merge "FD_v2_8/VDD" "3-stage_cs-vco_dp9_0/vdd"
+merge "3-stage_cs-vco_dp9_0/vdd" "FD_v2_9/VDD"
+merge "FD_v2_9/VDD" "m1_1702_n1381#"
+merge "m1_1702_n1381#" "FD_v2_3/VDD"
+merge "FD_v2_3/VDD" "FD_v2_4/VDD"
+merge "FD_v2_4/VDD" "m1_1729_n38#"
+merge "3-stage_cs-vco_dp9_0/vctrl" "vctrl" -60.2106 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4324 -280 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_6/Clk_Out" "FD_v2_7/Clk_In" -89.032 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -94080 -136 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_7/Clk_In" "out_div128"
+merge "3-stage_cs-vco_dp9_0/sel0" "vsel0" -623.008 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -38812 -2916 0 0 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/sel1" "vsel1" -21.6612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5152 -122 0 0 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/sel2" "vsel2" -22.9534 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3164 -122 0 0 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/sel3" "vsel3" -24.464 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 840 -122 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_7/Clk_Out" "FD_v2_8/Clk_In" -62.7475 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2550 -286 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_8/Clk_In" "out_div256"
+merge "FD_v2_9/Clk_In" "FD_v2_8/Clk_Out" -12.4662 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6052 -68 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_5/Clk_In" "FD_v2_4/Clk_Out" -31.3656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -23024 -68 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_3/Clk_In" "FD_v2_2/Clk_Out" -62.862 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -71480 -68 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_3/Clk_Out" "FD_v2_4/Clk_In" -110.995 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -32759 -318 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_4/Clk_In" "m1_2161_286#"
+merge "3-stage_cs-vco_dp9_0/out" "FD_v5_lasttry_0/Clk_In" -517.656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -369064 -472 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FD_v5_lasttry_0/Clk_In" "out"
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.mag b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.mag
new file mode 100755
index 0000000..b1052fb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.mag
@@ -0,0 +1,173 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647369436
+<< error_s >>
+rect 5646 1468 5648 1502
+rect 896 335 926 347
+rect 896 251 926 263
+<< pwell >>
+rect 7680 300 7726 346
+<< locali >>
+rect 2131 1117 2393 1122
+rect 1728 1082 2393 1117
+rect 1728 1077 2171 1082
+rect 1728 1040 1768 1077
+<< metal1 >>
+rect 1726 2424 1796 2462
+rect 1989 2426 2059 2464
+rect -1409 1755 -1383 1787
+rect -1332 1602 -1304 1635
+rect -1251 1531 -1223 1564
+rect 1704 1546 7009 1723
+rect 1704 1531 1847 1546
+rect -1163 1448 -1135 1481
+rect 8161 1076 8263 1122
+rect 7006 691 7173 749
+rect 1989 659 2059 665
+rect 2235 659 7173 691
+rect 1989 601 1995 659
+rect 2053 601 2235 659
+rect 7006 658 7173 659
+rect 1989 595 2059 601
+rect 2161 352 2235 358
+rect 2161 292 2168 352
+rect 2228 292 2277 352
+rect 8217 346 8263 1076
+rect 7680 300 8263 346
+rect 2161 286 2235 292
+rect 1729 -38 1735 20
+rect 1793 -38 2235 20
+rect 2172 -315 2224 -309
+rect 2224 -364 2248 -318
+rect 7680 -357 7756 -323
+rect 2172 -373 2224 -367
+rect -1724 -522 -1630 -476
+rect 1968 -619 2080 -554
+rect 1968 -677 2236 -619
+rect 7722 -939 7756 -357
+rect 5860 -973 5935 -939
+rect 7680 -973 7756 -939
+rect 1868 -1304 7680 -1258
+rect 1799 -1312 7680 -1304
+rect 1702 -1381 7680 -1312
+<< via1 >>
+rect 1995 601 2053 659
+rect 2168 292 2228 352
+rect 1735 -38 1793 20
+rect 2172 -367 2224 -315
+<< metal2 >>
+rect 1985 660 2063 669
+rect 1985 600 1994 660
+rect 2054 600 2063 660
+rect 1985 591 2063 600
+rect 2161 352 2235 358
+rect 2161 292 2168 352
+rect 2228 292 2235 352
+rect 2161 286 2235 292
+rect 1725 21 1803 30
+rect 1725 -39 1734 21
+rect 1794 -39 1803 21
+rect 1725 -48 1803 -39
+rect 2159 -371 2168 -311
+rect 2228 -371 2237 -311
+<< via2 >>
+rect 1994 659 2054 660
+rect 1994 601 1995 659
+rect 1995 601 2053 659
+rect 2053 601 2054 659
+rect 1994 600 2054 601
+rect 2170 294 2226 350
+rect 1734 20 1794 21
+rect 1734 -38 1735 20
+rect 1735 -38 1793 20
+rect 1793 -38 1794 20
+rect 1734 -39 1794 -38
+rect 2168 -315 2228 -311
+rect 2168 -367 2172 -315
+rect 2172 -367 2224 -315
+rect 2224 -367 2228 -315
+rect 2168 -371 2228 -367
+<< metal3 >>
+rect 1989 660 2059 665
+rect 1989 600 1994 660
+rect 2054 600 2059 660
+rect 1989 595 2059 600
+rect 2165 350 2231 355
+rect 2165 294 2170 350
+rect 2226 294 2231 350
+rect 2165 289 2231 294
+rect 1729 21 1799 26
+rect 1729 -39 1734 21
+rect 1794 -39 1799 21
+rect 1729 -44 1799 -39
+rect 2168 -306 2228 289
+rect 2163 -311 2233 -306
+rect 2163 -371 2168 -311
+rect 2228 -371 2233 -311
+rect 2163 -376 2233 -371
+use FD_v2 FD_v2_8
+timestamp 1647347842
+transform -1 0 5933 0 -1 -1307
+box 68 -697 1883 34
+use FD_v2 FD_v2_9
+timestamp 1647347842
+transform -1 0 4118 0 -1 -1307
+box 68 -697 1883 34
+use FD_v2 FD_v2_4
+timestamp 1647347842
+transform 1 0 2167 0 1 11
+box 68 -697 1883 34
+use FD_v2 FD_v2_5
+timestamp 1647347842
+transform 1 0 3982 0 1 11
+box 68 -697 1883 34
+use FD_v2 FD_v2_2
+timestamp 1647347842
+transform -1 0 5933 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_3
+timestamp 1647347842
+transform -1 0 4118 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_7
+timestamp 1647347842
+transform -1 0 7748 0 -1 -1307
+box 68 -697 1883 34
+use FD_v2 FD_v2_6
+timestamp 1647347842
+transform 1 0 5797 0 1 11
+box 68 -697 1883 34
+use FD_v2 FD_v2_1
+timestamp 1647347842
+transform -1 0 7748 0 -1 -29
+box 68 -697 1883 34
+use FD_v5_lasttry FD_v5_lasttry_0
+timestamp 1647369436
+transform 1 0 2617 0 1 1451
+box -383 -769 5544 178
+use 3-stage_cs-vco_dp9 3-stage_cs-vco_dp9_0
+timestamp 1647352703
+transform 1 0 25 0 1 226
+box -1753 -1641 2093 2381
+<< labels >>
+rlabel metal1 1732 2426 1789 2460 1 vdd
+port 3 n
+rlabel metal1 1994 2427 2051 2461 1 vss
+port 4 n
+rlabel metal1 -1407 1757 -1384 1783 1 vsel0
+port 5 n
+rlabel metal1 -1330 1605 -1307 1631 1 vsel1
+port 6 n
+rlabel metal1 -1248 1534 -1225 1560 1 vsel2
+port 7 n
+rlabel metal1 -1161 1449 -1138 1475 1 vsel3
+port 8 n
+rlabel metal1 -1702 -522 -1659 -476 1 vctrl
+port 1 n
+rlabel metal1 5865 -968 5891 -947 1 out_div256
+port 9 n
+rlabel metal1 7700 -966 7726 -949 1 out_div128
+port 2 n
+rlabel locali 1902 1080 1947 1117 1 out
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.spice b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.spice
new file mode 100755
index 0000000..327bb0a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry.spice
@@ -0,0 +1,1568 @@
+* NGSPICE file created from vco_with_fdivs_lasttry.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+C0 a_15_n115# a_n73_n115# 0.11fF
+C1 a_15_n115# VSUBS 0.02fF
+C2 a_n73_n115# VSUBS 0.02fF
+C3 a_n118_22# VSUBS 0.15fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
++ VSUBS
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_n73_n36# a_15_n36# 0.09fF
+C1 w_n109_n86# a_n15_n133# 0.05fF
+C2 a_15_n36# w_n109_n86# 0.08fF
+C3 a_n73_n36# w_n109_n86# 0.08fF
+C4 a_15_n36# VSUBS -0.06fF
+C5 a_n73_n36# VSUBS -0.06fF
+C6 a_n15_n133# VSUBS 0.04fF
+C7 w_n109_n86# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+C0 a_n73_37# a_n73_n79# 0.03fF
+C1 a_15_n79# a_n73_n79# 0.07fF
+C2 a_15_n79# VSUBS 0.03fF
+C3 a_n73_n79# VSUBS 0.03fF
+C4 a_n73_37# VSUBS 0.15fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
++ VSUBS
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+C0 a_n73_n78# a_15_n78# 0.06fF
+C1 w_n109_n140# a_n33_37# 0.14fF
+C2 a_15_n78# a_n33_37# 0.00fF
+C3 a_15_n78# w_n109_n140# 0.05fF
+C4 a_n73_n78# a_n33_37# 0.00fF
+C5 a_n73_n78# w_n109_n140# 0.05fF
+C6 a_15_n78# VSUBS -0.03fF
+C7 a_n73_n78# VSUBS -0.03fF
+C8 a_n33_37# VSUBS -0.01fF
+C9 w_n109_n140# VSUBS 0.16fF
+.ends
+
+.subckt FD_v2 VDD GND Clk_Out 7 5 4 3 Clkb 6 Clk_In 2
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 GND sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD GND sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD GND sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+C0 4 GND 0.41fF
+C1 4 3 0.13fF
+C2 5 6 0.19fF
+C3 2 VDD 0.28fF
+C4 7 6 0.42fF
+C5 Clk_Out 6 0.02fF
+C6 VDD Clkb 1.06fF
+C7 Clk_In GND 0.43fF
+C8 7 Clk_Out 0.14fF
+C9 Clk_In 3 0.18fF
+C10 VDD 6 0.12fF
+C11 4 2 0.19fF
+C12 VDD 5 0.12fF
+C13 7 VDD 0.26fF
+C14 GND 3 0.23fF
+C15 VDD Clk_Out 0.08fF
+C16 4 Clkb 0.12fF
+C17 4 6 0.00fF
+C18 Clk_In 2 0.85fF
+C19 4 5 0.08fF
+C20 Clk_In Clkb 0.93fF
+C21 2 GND 0.21fF
+C22 2 3 0.12fF
+C23 Clk_In 6 0.00fF
+C24 Clk_In 5 0.11fF
+C25 4 VDD 0.10fF
+C26 GND Clkb 0.09fF
+C27 7 Clk_In 0.00fF
+C28 Clkb 3 0.28fF
+C29 6 GND 0.78fF
+C30 5 GND 0.19fF
+C31 5 3 0.03fF
+C32 7 GND 0.11fF
+C33 Clk_In VDD 1.11fF
+C34 Clk_Out GND 0.09fF
+C35 2 Clkb 0.60fF
+C36 VDD GND 0.03fF
+C37 VDD 3 0.15fF
+C38 2 6 0.61fF
+C39 2 5 0.17fF
+C40 4 Clk_In 0.08fF
+C41 7 2 0.11fF
+C42 2 Clk_Out 0.04fF
+C43 6 Clkb 0.02fF
+C44 5 Clkb 0.09fF
+C45 Clkb 0 0.93fF
+C46 7 0 0.47fF
+C47 Clk_Out 0 0.12fF
+C48 5 0 0.12fF
+C49 GND 0 -0.19fF
+C50 Clk_In 0 1.07fF
+C51 3 0 0.02fF
+C52 2 0 0.92fF
+C53 VDD 0 1.90fF
+C54 6 0 0.82fF
+C55 4 0 0.09fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+C0 a_n73_n163# a_n73_37# 0.03fF
+C1 a_n73_n163# a_15_n163# 0.12fF
+C2 a_n73_n163# a_103_n163# 0.05fF
+C3 a_103_n163# a_15_n163# 0.12fF
+C4 a_n73_n163# a_191_n163# 0.03fF
+C5 a_191_n163# a_15_n163# 0.05fF
+C6 a_191_n163# a_103_n163# 0.12fF
+C7 a_191_n163# VSUBS 0.03fF
+C8 a_103_n163# VSUBS 0.03fF
+C9 a_15_n163# VSUBS 0.03fF
+C10 a_n73_n163# VSUBS 0.03fF
+C11 a_n73_37# VSUBS 0.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133# VSUBS
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+C0 a_n15_n133# w_n109_n86# 0.35fF
+C1 a_279_n36# a_n73_n36# 0.03fF
+C2 a_n73_n36# w_n109_n86# 0.14fF
+C3 a_191_n36# a_n73_n36# 0.04fF
+C4 a_279_n36# a_15_n36# 0.04fF
+C5 a_15_n36# w_n109_n86# 0.14fF
+C6 a_191_n36# a_15_n36# 0.07fF
+C7 a_279_n36# a_103_n36# 0.07fF
+C8 a_15_n36# a_367_n36# 0.03fF
+C9 a_103_n36# w_n109_n86# 0.14fF
+C10 a_191_n36# a_103_n36# 0.18fF
+C11 a_455_n36# a_279_n36# 0.07fF
+C12 a_455_n36# a_543_n36# 0.18fF
+C13 a_103_n36# a_367_n36# 0.04fF
+C14 a_455_n36# w_n109_n86# 0.14fF
+C15 a_191_n36# a_455_n36# 0.04fF
+C16 a_15_n36# a_n73_n36# 0.18fF
+C17 a_455_n36# a_367_n36# 0.18fF
+C18 a_103_n36# a_n73_n36# 0.07fF
+C19 a_103_n36# a_15_n36# 0.18fF
+C20 a_455_n36# a_103_n36# 0.03fF
+C21 a_279_n36# a_543_n36# 0.04fF
+C22 a_279_n36# w_n109_n86# 0.14fF
+C23 a_543_n36# w_n109_n86# 0.14fF
+C24 a_191_n36# a_279_n36# 0.18fF
+C25 a_191_n36# a_543_n36# 0.03fF
+C26 a_191_n36# w_n109_n86# 0.14fF
+C27 a_279_n36# a_367_n36# 0.18fF
+C28 a_543_n36# a_367_n36# 0.07fF
+C29 a_367_n36# w_n109_n86# 0.14fF
+C30 a_191_n36# a_367_n36# 0.07fF
+C31 a_543_n36# VSUBS -0.12fF
+C32 a_455_n36# VSUBS -0.12fF
+C33 a_367_n36# VSUBS -0.12fF
+C34 a_279_n36# VSUBS -0.12fF
+C35 a_191_n36# VSUBS -0.12fF
+C36 a_103_n36# VSUBS -0.12fF
+C37 a_15_n36# VSUBS -0.12fF
+C38 a_n73_n36# VSUBS -0.12fF
+C39 a_n15_n133# VSUBS 0.43fF
+C40 w_n109_n86# VSUBS 0.90fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+C0 a_15_n163# a_n73_n163# 0.12fF
+C1 a_n73_37# a_n73_n163# 0.03fF
+C2 a_15_n163# VSUBS 0.03fF
+C3 a_n73_n163# VSUBS 0.03fF
+C4 a_n73_37# VSUBS 0.15fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+C0 a_15_n163# a_103_n163# 0.12fF
+C1 a_15_n163# a_n73_n163# 0.12fF
+C2 a_n73_37# a_n73_n163# 0.03fF
+C3 a_103_n163# a_n73_n163# 0.05fF
+C4 a_103_n163# VSUBS 0.03fF
+C5 a_15_n163# VSUBS 0.03fF
+C6 a_n73_n163# VSUBS 0.03fF
+C7 a_n73_37# VSUBS 0.26fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133# VSUBS
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+C0 a_279_n36# a_103_n36# 0.07fF
+C1 a_191_n36# a_279_n36# 0.18fF
+C2 a_n73_n36# a_103_n36# 0.07fF
+C3 a_191_n36# a_n73_n36# 0.04fF
+C4 a_279_n36# w_n109_n86# 0.14fF
+C5 a_279_n36# a_15_n36# 0.04fF
+C6 a_n73_n36# w_n109_n86# 0.14fF
+C7 a_n73_n36# a_15_n36# 0.18fF
+C8 a_191_n36# a_103_n36# 0.18fF
+C9 w_n109_n86# a_103_n36# 0.14fF
+C10 a_15_n36# a_103_n36# 0.18fF
+C11 a_191_n36# w_n109_n86# 0.14fF
+C12 a_191_n36# a_15_n36# 0.07fF
+C13 w_n109_n86# a_15_n36# 0.14fF
+C14 a_279_n36# a_n73_n36# 0.03fF
+C15 w_n109_n86# a_n15_n133# 0.20fF
+C16 a_279_n36# VSUBS -0.12fF
+C17 a_191_n36# VSUBS -0.12fF
+C18 a_103_n36# VSUBS -0.12fF
+C19 a_15_n36# VSUBS -0.12fF
+C20 a_n73_n36# VSUBS -0.12fF
+C21 a_n15_n133# VSUBS 0.24fF
+C22 w_n109_n86# VSUBS 0.58fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86# VSUBS
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+C0 a_191_n36# a_367_n36# 0.07fF
+C1 a_191_n36# a_15_n36# 0.07fF
+C2 a_103_n36# a_191_n36# 0.18fF
+C3 a_191_n36# a_279_n36# 0.18fF
+C4 a_191_n36# a_n73_n36# 0.04fF
+C5 a_191_n36# w_n109_n86# 0.14fF
+C6 a_367_n36# a_15_n36# 0.03fF
+C7 a_103_n36# a_367_n36# 0.04fF
+C8 a_n15_n81# w_n109_n86# 0.34fF
+C9 a_367_n36# a_279_n36# 0.18fF
+C10 a_103_n36# a_15_n36# 0.18fF
+C11 a_279_n36# a_15_n36# 0.04fF
+C12 a_103_n36# a_279_n36# 0.07fF
+C13 a_n73_n36# a_15_n36# 0.18fF
+C14 a_103_n36# a_n73_n36# 0.07fF
+C15 a_367_n36# w_n109_n86# 0.14fF
+C16 a_n73_n36# a_279_n36# 0.03fF
+C17 w_n109_n86# a_15_n36# 0.14fF
+C18 a_103_n36# w_n109_n86# 0.14fF
+C19 w_n109_n86# a_279_n36# 0.14fF
+C20 a_n73_n36# w_n109_n86# 0.14fF
+C21 a_367_n36# VSUBS -0.12fF
+C22 a_279_n36# VSUBS -0.12fF
+C23 a_191_n36# VSUBS -0.12fF
+C24 a_103_n36# VSUBS -0.12fF
+C25 a_15_n36# VSUBS -0.12fF
+C26 a_n73_n36# VSUBS -0.12fF
+C27 a_n15_n81# VSUBS 0.05fF
+C28 w_n109_n86# VSUBS 0.68fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133# VSUBS
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_n73_n36# a_15_n36# 0.18fF
+C1 a_15_n36# a_103_n36# 0.18fF
+C2 a_15_n36# w_n109_n86# 0.14fF
+C3 a_n73_n36# a_103_n36# 0.07fF
+C4 w_n109_n86# a_n15_n133# 0.10fF
+C5 a_n73_n36# w_n109_n86# 0.14fF
+C6 w_n109_n86# a_103_n36# 0.14fF
+C7 a_103_n36# VSUBS -0.12fF
+C8 a_15_n36# VSUBS -0.12fF
+C9 a_n73_n36# VSUBS -0.12fF
+C10 a_n15_n133# VSUBS 0.11fF
+C11 w_n109_n86# VSUBS 0.37fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_B2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n15_n81# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# VSUBS
+X0 a_543_n36# a_n15_n81# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n81# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+C0 a_455_n36# a_367_n36# 0.18fF
+C1 a_455_n36# w_n109_n86# 0.14fF
+C2 a_543_n36# a_279_n36# 0.04fF
+C3 a_455_n36# a_279_n36# 0.07fF
+C4 a_15_n36# a_191_n36# 0.07fF
+C5 a_455_n36# a_543_n36# 0.18fF
+C6 a_n73_n36# a_15_n36# 0.18fF
+C7 a_15_n36# a_103_n36# 0.18fF
+C8 a_15_n36# a_367_n36# 0.03fF
+C9 a_15_n36# w_n109_n86# 0.14fF
+C10 a_15_n36# a_279_n36# 0.04fF
+C11 a_n73_n36# a_191_n36# 0.04fF
+C12 a_191_n36# a_103_n36# 0.18fF
+C13 a_n73_n36# a_103_n36# 0.07fF
+C14 a_367_n36# a_191_n36# 0.07fF
+C15 a_191_n36# w_n109_n86# 0.14fF
+C16 w_n109_n86# a_n15_n81# 0.48fF
+C17 a_n73_n36# w_n109_n86# 0.14fF
+C18 a_367_n36# a_103_n36# 0.04fF
+C19 a_191_n36# a_279_n36# 0.18fF
+C20 w_n109_n86# a_103_n36# 0.14fF
+C21 a_191_n36# a_543_n36# 0.03fF
+C22 a_455_n36# a_191_n36# 0.04fF
+C23 a_n73_n36# a_279_n36# 0.03fF
+C24 a_279_n36# a_103_n36# 0.07fF
+C25 a_367_n36# w_n109_n86# 0.14fF
+C26 a_455_n36# a_103_n36# 0.03fF
+C27 a_367_n36# a_279_n36# 0.18fF
+C28 w_n109_n86# a_279_n36# 0.14fF
+C29 a_367_n36# a_543_n36# 0.07fF
+C30 w_n109_n86# a_543_n36# 0.14fF
+C31 a_543_n36# VSUBS -0.12fF
+C32 a_455_n36# VSUBS -0.12fF
+C33 a_367_n36# VSUBS -0.12fF
+C34 a_279_n36# VSUBS -0.12fF
+C35 a_191_n36# VSUBS -0.12fF
+C36 a_103_n36# VSUBS -0.12fF
+C37 a_15_n36# VSUBS -0.12fF
+C38 a_n73_n36# VSUBS -0.12fF
+C39 a_n15_n81# VSUBS 0.07fF
+C40 w_n109_n86# VSUBS 0.90fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_191_n163# a_103_n163# 0.12fF
+C1 a_191_n163# a_543_n163# 0.02fF
+C2 a_279_n163# a_15_n163# 0.03fF
+C3 a_191_n163# a_15_n163# 0.05fF
+C4 a_191_n163# a_279_n163# 0.12fF
+C5 a_455_n163# a_631_n163# 0.05fF
+C6 a_367_n163# a_455_n163# 0.12fF
+C7 a_455_n163# a_103_n163# 0.02fF
+C8 a_455_n163# a_543_n163# 0.12fF
+C9 a_455_n163# a_279_n163# 0.05fF
+C10 a_367_n163# a_631_n163# 0.03fF
+C11 a_191_n163# a_455_n163# 0.03fF
+C12 a_103_n163# a_n73_n163# 0.05fF
+C13 a_543_n163# a_631_n163# 0.12fF
+C14 a_367_n163# a_103_n163# 0.03fF
+C15 a_367_n163# a_543_n163# 0.05fF
+C16 a_n73_n163# a_15_n163# 0.12fF
+C17 a_n73_n163# a_279_n163# 0.02fF
+C18 a_191_n163# a_n73_n163# 0.03fF
+C19 a_367_n163# a_15_n163# 0.02fF
+C20 a_279_n163# a_631_n163# 0.02fF
+C21 a_367_n163# a_279_n163# 0.12fF
+C22 a_367_n163# a_191_n163# 0.05fF
+C23 a_103_n163# a_15_n163# 0.12fF
+C24 a_103_n163# a_279_n163# 0.05fF
+C25 a_543_n163# a_279_n163# 0.03fF
+C26 a_631_n163# VSUBS 0.03fF
+C27 a_543_n163# VSUBS 0.03fF
+C28 a_455_n163# VSUBS 0.03fF
+C29 a_367_n163# VSUBS 0.03fF
+C30 a_279_n163# VSUBS 0.03fF
+C31 a_191_n163# VSUBS 0.03fF
+C32 a_103_n163# VSUBS 0.03fF
+C33 a_15_n163# VSUBS 0.03fF
+C34 a_n73_n163# VSUBS 0.03fF
+C35 a_n15_n199# VSUBS 0.68fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
++ VSUBS
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 w_n109_n86# a_n15_n133# 0.05fF
+C1 a_n73_n36# a_15_n36# 0.18fF
+C2 w_n109_n86# a_15_n36# 0.14fF
+C3 a_n73_n36# w_n109_n86# 0.14fF
+C4 a_15_n36# VSUBS -0.12fF
+C5 a_n73_n36# VSUBS -0.12fF
+C6 a_n15_n133# VSUBS 0.04fF
+C7 w_n109_n86# VSUBS 0.26fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n73_37# a_n73_n163# 0.03fF
+C1 a_103_n163# a_279_n163# 0.05fF
+C2 a_15_n163# a_103_n163# 0.12fF
+C3 a_103_n163# a_191_n163# 0.12fF
+C4 a_103_n163# a_367_n163# 0.03fF
+C5 a_103_n163# a_n73_n163# 0.05fF
+C6 a_15_n163# a_279_n163# 0.03fF
+C7 a_191_n163# a_279_n163# 0.12fF
+C8 a_15_n163# a_191_n163# 0.05fF
+C9 a_367_n163# a_279_n163# 0.12fF
+C10 a_15_n163# a_367_n163# 0.02fF
+C11 a_n73_n163# a_279_n163# 0.02fF
+C12 a_15_n163# a_n73_n163# 0.12fF
+C13 a_191_n163# a_367_n163# 0.05fF
+C14 a_191_n163# a_n73_n163# 0.03fF
+C15 a_367_n163# VSUBS 0.03fF
+C16 a_279_n163# VSUBS 0.03fF
+C17 a_191_n163# VSUBS 0.03fF
+C18 a_103_n163# VSUBS 0.03fF
+C19 a_15_n163# VSUBS 0.03fF
+C20 a_n73_n163# VSUBS 0.03fF
+C21 a_n73_37# VSUBS 0.58fF
+.ends
+
+.subckt FD_v5_lasttry Clk_In VDD GND Clk_Out Clkb_buf dus 7 4 3 5 2 Clkb_int Clk_In_buf
++ 6
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus GND sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 GND sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD GND sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In GND sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 GND sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 GND sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf GND sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_B2DS5R_0 3 4 3 4 3 Clkb_buf 3 4 4 VDD GND sky130_fd_pr__pfet_01v8_B2DS5R
+Xsky130_fd_pr__pfet_01v8_B2DS5R_1 5 6 5 6 5 Clk_In_buf 5 6 6 VDD GND sky130_fd_pr__pfet_01v8_B2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 GND sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 GND sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+C0 5 6 0.76fF
+C1 5 VDD 0.85fF
+C2 5 4 0.27fF
+C3 2 Clkb_buf 2.51fF
+C4 5 Clk_In_buf 0.76fF
+C5 3 2 0.65fF
+C6 dus Clkb_int 0.54fF
+C7 6 2 1.12fF
+C8 2 VDD 0.17fF
+C9 4 2 0.61fF
+C10 2 7 0.14fF
+C11 3 Clkb_buf 1.20fF
+C12 2 Clk_In_buf 2.36fF
+C13 6 Clkb_buf 0.06fF
+C14 VDD Clkb_buf 4.34fF
+C15 4 Clkb_buf -0.09fF
+C16 VDD Clk_In 0.02fF
+C17 3 VDD 0.95fF
+C18 4 3 0.70fF
+C19 Clk_In_buf Clkb_buf 3.06fF
+C20 6 VDD 0.24fF
+C21 4 VDD 0.27fF
+C22 6 Clk_Out 0.02fF
+C23 VDD Clk_Out 0.17fF
+C24 5 2 0.47fF
+C25 3 Clk_In_buf 1.27fF
+C26 6 7 0.39fF
+C27 7 VDD 0.47fF
+C28 dus Clkb_buf 0.47fF
+C29 7 Clk_Out 0.29fF
+C30 6 Clk_In_buf 0.22fF
+C31 Clk_In_buf VDD 3.93fF
+C32 4 Clk_In_buf 0.05fF
+C33 Clk_In Clkb_int 0.37fF
+C34 dus Clk_In 0.02fF
+C35 5 Clkb_buf 0.82fF
+C36 VDD Clkb_int 0.34fF
+C37 dus VDD 0.44fF
+C38 5 3 0.03fF
+C39 6 GND 2.63fF
+C40 4 GND 1.43fF
+C41 Clk_In_buf GND 3.63fF
+C42 Clkb_buf GND 5.30fF
+C43 Clk_Out GND 0.12fF
+C44 7 GND 0.61fF
+C45 Clkb_int GND 0.81fF
+C46 Clk_In GND 0.54fF
+C47 5 GND 0.73fF
+C48 dus GND 1.61fF
+C49 VDD GND 6.82fF
+C50 3 GND 0.74fF
+C51 2 GND 2.37fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
++ VSUBS
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+C0 a_n73_n240# a_15_n240# 0.20fF
+C1 w_n109_n340# a_n33_n337# 0.11fF
+C2 w_n109_n340# a_15_n240# 0.17fF
+C3 w_n109_n340# a_n73_n240# 0.19fF
+C4 a_15_n240# VSUBS -0.16fF
+C5 a_n73_n240# VSUBS -0.18fF
+C6 a_n33_n337# VSUBS 0.02fF
+C7 w_n109_n340# VSUBS 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220# VSUBS
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+C0 w_n209_n320# a_18_n220# 0.28fF
+C1 a_n33_310# a_n129_n366# 0.02fF
+C2 w_n209_n320# a_n78_n220# 0.20fF
+C3 w_n209_n320# a_114_n220# 0.20fF
+C4 a_18_n220# a_n173_n220# 0.14fF
+C5 a_n129_n366# a_63_n366# 0.04fF
+C6 a_n173_n220# a_n78_n220# 0.24fF
+C7 w_n209_n320# a_n33_310# 0.09fF
+C8 a_n173_n220# a_114_n220# 0.06fF
+C9 w_n209_n320# a_63_n366# 0.10fF
+C10 a_18_n220# a_n78_n220# 0.24fF
+C11 a_18_n220# a_114_n220# 0.24fF
+C12 a_114_n220# a_n78_n220# 0.09fF
+C13 a_18_n220# a_n33_310# 0.00fF
+C14 a_n33_310# a_n78_n220# 0.00fF
+C15 a_18_n220# a_63_n366# 0.00fF
+C16 w_n209_n320# a_n129_n366# 0.10fF
+C17 a_114_n220# a_63_n366# 0.00fF
+C18 a_n129_n366# a_n173_n220# 0.00fF
+C19 a_n33_310# a_63_n366# 0.02fF
+C20 w_n209_n320# a_n173_n220# 0.28fF
+C21 a_n129_n366# a_n78_n220# 0.00fF
+C22 a_114_n220# VSUBS -0.18fF
+C23 a_18_n220# VSUBS -0.27fF
+C24 a_n78_n220# VSUBS -0.18fF
+C25 a_n173_n220# VSUBS -0.27fF
+C26 a_63_n366# VSUBS 0.06fF
+C27 a_n129_n366# VSUBS 0.06fF
+C28 a_n33_310# VSUBS 0.09fF
+C29 w_n209_n320# VSUBS 0.78fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
++ VSUBS
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n136# a_18_n136# 0.20fF
+C1 a_n33_95# a_n76_n136# 0.00fF
+C2 w_n112_n198# a_n76_n136# 0.16fF
+C3 a_n33_95# a_18_n136# 0.00fF
+C4 w_n112_n198# a_18_n136# 0.16fF
+C5 a_n33_95# w_n112_n198# 0.19fF
+C6 a_18_n136# VSUBS -0.15fF
+C7 a_n76_n136# VSUBS -0.15fF
+C8 a_n33_95# VSUBS -0.07fF
+C9 w_n112_n198# VSUBS 0.24fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+C0 a_n73_n120# a_15_n120# 0.15fF
+C1 a_n33_142# a_15_n120# 0.00fF
+C2 a_n73_n120# a_n33_142# 0.01fF
+C3 a_15_n120# VSUBS 0.01fF
+C4 a_n73_n120# VSUBS 0.01fF
+C5 a_n33_142# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+C0 a_n76_n129# a_18_n129# 0.15fF
+C1 a_n33_n217# a_18_n129# 0.00fF
+C2 a_n76_n129# a_n33_n217# 0.00fF
+C3 a_18_n129# VSUBS 0.02fF
+C4 a_n76_n129# VSUBS 0.00fF
+C5 a_n33_n217# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+C0 a_n76_n69# a_18_n69# 0.17fF
+C1 a_n33_n157# a_18_n69# 0.01fF
+C2 a_n76_n69# a_n33_n157# 0.00fF
+C3 a_18_n69# VSUBS 0.00fF
+C4 a_n76_n69# VSUBS 0.00fF
+C5 a_n33_n157# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+C0 a_n76_n29# a_18_n29# 0.12fF
+C1 a_n33_n117# a_18_n29# 0.01fF
+C2 a_n76_n29# a_n33_n117# 0.01fF
+C3 a_18_n29# VSUBS 0.00fF
+C4 a_n76_n29# VSUBS 0.00fF
+C5 a_n33_n117# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_n76_n209# a_18_n209# 0.35fF
+C1 a_n33_n297# a_18_n209# 0.00fF
+C2 a_n76_n209# a_n33_n297# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
++ VSUBS
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_n76_n108# a_18_n108# 0.22fF
+C1 a_n33_67# a_n76_n108# 0.01fF
+C2 w_n112_n170# a_n76_n108# 0.15fF
+C3 a_n33_67# a_18_n108# 0.01fF
+C4 w_n112_n170# a_18_n108# 0.15fF
+C5 a_n33_67# w_n112_n170# 0.19fF
+C6 a_18_n108# VSUBS -0.13fF
+C7 a_n76_n108# VSUBS -0.13fF
+C8 a_n33_67# VSUBS -0.07fF
+C9 w_n112_n170# VSUBS 0.21fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
++ VSUBS
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+C0 a_n73_n100# a_15_n100# 0.13fF
+C1 w_n109_n136# a_n73_n100# 0.10fF
+C2 w_n109_n136# a_15_n100# 0.10fF
+C3 a_n15_n132# w_n109_n136# 0.05fF
+C4 a_15_n100# VSUBS -0.08fF
+C5 a_n73_n100# VSUBS -0.08fF
+C6 a_n15_n132# VSUBS 0.00fF
+C7 w_n109_n136# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+C0 a_n73_n96# a_15_n96# 0.08fF
+C1 a_n73_n96# a_n73_56# 0.03fF
+C2 a_15_n96# VSUBS 0.02fF
+C3 a_n73_n96# VSUBS 0.02fF
+C4 a_n73_56# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+C0 a_n76_n73# a_18_n73# 0.05fF
+C1 a_n18_n99# a_18_n73# 0.03fF
+C2 a_18_n73# VSUBS 0.02fF
+C3 a_n76_n73# VSUBS 0.02fF
+C4 a_n18_n99# VSUBS 0.13fF
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd selb
+XXM25 vdd in out selb vss sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel vss sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+C0 vdd out 0.11fF
+C1 in selb 0.25fF
+C2 in sel 0.55fF
+C3 sel selb 0.39fF
+C4 in out 0.19fF
+C5 selb out 0.06fF
+C6 sel out 0.06fF
+C7 vdd in 0.30fF
+C8 vdd selb 0.14fF
+C9 vdd sel 0.09fF
+C10 sel vss 0.78fF
+C11 selb vss 0.81fF
+C12 vdd vss 0.57fF
+C13 out vss 0.16fF
+C14 in vss 0.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
++ VSUBS
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n276# a_n76_n276# 0.46fF
+C1 a_18_n276# w_n112_n338# 0.32fF
+C2 a_18_n276# a_n33_235# 0.00fF
+C3 a_n76_n276# w_n112_n338# 0.32fF
+C4 a_n76_n276# a_n33_235# 0.00fF
+C5 w_n112_n338# a_n33_235# 0.19fF
+C6 a_18_n276# VSUBS -0.31fF
+C7 a_n76_n276# VSUBS -0.31fF
+C8 a_n33_235# VSUBS -0.07fF
+C9 w_n112_n338# VSUBS 0.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
++ VSUBS
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+C0 a_15_n144# a_n73_n144# 0.15fF
+C1 a_15_n144# w_n109_n244# 0.13fF
+C2 a_15_n144# a_n33_n241# 0.00fF
+C3 a_n73_n144# w_n109_n244# 0.13fF
+C4 a_n73_n144# a_n33_n241# 0.00fF
+C5 w_n109_n244# a_n33_n241# 0.14fF
+C6 a_15_n144# VSUBS -0.11fF
+C7 a_n73_n144# VSUBS -0.11fF
+C8 a_n33_n241# VSUBS -0.01fF
+C9 w_n109_n244# VSUBS 0.29fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+C0 a_18_n209# a_n33_n297# 0.00fF
+C1 a_18_n209# a_n76_n209# 0.47fF
+C2 a_n33_n297# a_n76_n209# 0.00fF
+C3 a_18_n209# VSUBS 0.00fF
+C4 a_n76_n209# VSUBS 0.00fF
+C5 a_n33_n297# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+C0 a_15_n103# a_n33_63# 0.00fF
+C1 a_15_n103# a_n73_n103# 0.07fF
+C2 a_n33_63# a_n73_n103# 0.00fF
+C3 a_n33_63# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
++ VSUBS
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+C0 a_15_n64# a_n73_n64# 0.07fF
+C1 a_15_n64# w_n109_n164# 0.06fF
+C2 a_15_n64# a_n33_n161# 0.00fF
+C3 a_n73_n64# w_n109_n164# 0.06fF
+C4 a_n73_n64# a_n33_n161# 0.00fF
+C5 w_n109_n164# a_n33_n161# 0.14fF
+C6 a_15_n64# VSUBS -0.06fF
+C7 a_n73_n64# VSUBS -0.06fF
+C8 a_n33_n161# VSUBS -0.01fF
+C9 w_n109_n164# VSUBS 0.20fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+C0 a_15_n96# a_n33_33# 0.00fF
+C1 a_15_n96# a_n73_n96# 0.06fF
+C2 a_n33_33# a_n73_n96# 0.00fF
+C3 a_15_n96# VSUBS 0.02fF
+C4 a_n73_n96# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
++ VSUBS
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+C0 a_15_n236# a_n73_n236# 0.32fF
+C1 a_15_n236# w_n109_n298# 0.26fF
+C2 a_15_n236# a_n33_395# 0.00fF
+C3 a_n73_n236# w_n109_n298# 0.26fF
+C4 a_n73_n236# a_n33_395# 0.00fF
+C5 w_n109_n298# a_n33_395# 0.14fF
+C6 a_15_n236# VSUBS -0.25fF
+C7 a_n73_n236# VSUBS -0.25fF
+C8 a_n33_395# VSUBS -0.01fF
+C9 w_n109_n298# VSUBS 0.50fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+C0 a_15_n175# a_n33_135# 0.00fF
+C1 a_15_n175# a_n73_n175# 0.16fF
+C2 a_n33_135# a_n73_n175# 0.00fF
+C3 a_15_n175# VSUBS 0.02fF
+C4 a_n73_n175# VSUBS 0.02fF
+C5 a_n33_135# VSUBS 0.13fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+C0 a_18_n89# a_n33_n177# 0.01fF
+C1 a_18_n89# a_n76_n89# 0.19fF
+C2 a_n33_n177# a_n76_n89# 0.00fF
+C3 a_18_n89# VSUBS 0.00fF
+C4 a_n76_n89# VSUBS 0.00fF
+C5 a_n33_n177# VSUBS 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
++ VSUBS
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_18_n72# a_n76_n72# 0.22fF
+C1 a_18_n72# w_n112_n134# 0.15fF
+C2 a_n76_n72# w_n112_n134# 0.15fF
+C3 w_n112_n134# a_n18_n98# 0.05fF
+C4 a_18_n72# VSUBS -0.13fF
+C5 a_n76_n72# VSUBS -0.13fF
+C6 a_n18_n98# VSUBS 0.00fF
+C7 w_n112_n134# VSUBS 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
++ VSUBS
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+C0 a_18_n108# a_n76_n108# 0.22fF
+C1 a_18_n108# w_n112_n170# 0.15fF
+C2 a_n76_n108# w_n112_n170# 0.15fF
+C3 a_n76_n108# a_n68_67# 0.03fF
+C4 w_n112_n170# a_n68_67# 0.16fF
+C5 a_18_n108# VSUBS -0.13fF
+C6 a_n76_n108# VSUBS -0.13fF
+C7 a_n68_67# VSUBS -0.01fF
+C8 w_n112_n170# VSUBS 0.21fF
+.ends
+
+.subckt vco_switch_p in sel vss selb vdd out
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out vss sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel vss sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out vss sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+C0 in out 0.19fF
+C1 vdd vss 0.01fF
+C2 vdd selb 0.06fF
+C3 sel vss 0.39fF
+C4 in vdd 0.40fF
+C5 sel selb 0.35fF
+C6 in sel 0.75fF
+C7 out vdd -0.04fF
+C8 vss selb 0.11fF
+C9 sel out 0.14fF
+C10 in vss -0.04fF
+C11 in selb 0.11fF
+C12 sel vdd 0.91fF
+C13 out vss 0.04fF
+C14 out selb 0.05fF
+C15 selb 0 -0.05fF
+C16 vss 0 -0.10fF
+C17 sel 0 0.36fF
+C18 out 0 0.11fF
+C19 in 0 0.06fF
+C20 vdd 0 0.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
++ VSUBS
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+C0 a_n76_n96# a_n33_55# 0.01fF
+C1 w_n112_n158# a_n76_n96# 0.11fF
+C2 w_n112_n158# a_n33_55# 0.19fF
+C3 a_18_n96# a_n76_n96# 0.13fF
+C4 a_18_n96# a_n33_55# 0.01fF
+C5 a_18_n96# w_n112_n158# 0.11fF
+C6 a_18_n96# VSUBS -0.11fF
+C7 a_n76_n96# VSUBS -0.11fF
+C8 a_n33_55# VSUBS -0.07fF
+C9 w_n112_n158# VSUBS 0.19fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
++ VSUBS
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+C0 a_n76_n156# a_n33_115# 0.00fF
+C1 w_n112_n218# a_n76_n156# 0.18fF
+C2 w_n112_n218# a_n33_115# 0.19fF
+C3 a_18_n156# a_n76_n156# 0.24fF
+C4 a_18_n156# a_n33_115# 0.00fF
+C5 a_18_n156# w_n112_n218# 0.18fF
+C6 a_18_n156# VSUBS -0.18fF
+C7 a_n76_n156# VSUBS -0.18fF
+C8 a_n33_115# VSUBS -0.07fF
+C9 w_n112_n218# VSUBS 0.27fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
++ VSUBS
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+C0 w_n109_n58# a_n72_n22# 0.14fF
+C1 w_n109_n58# a_n15_n53# 0.05fF
+C2 a_15_n22# a_n72_n22# 0.09fF
+C3 a_15_n22# w_n109_n58# 0.08fF
+C4 a_15_n22# VSUBS -0.07fF
+C5 a_n72_n22# VSUBS -0.14fF
+C6 a_n15_n53# VSUBS 0.00fF
+C7 w_n109_n58# VSUBS 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS29AB a_n33_33# a_n73_n68# a_15_n68# VSUBS
+X0 a_15_n68# a_n33_33# a_n73_n68# VSUBS sky130_fd_pr__nfet_01v8 ad=1.044e+11p pd=1.3e+06u as=1.044e+11p ps=1.3e+06u w=360000u l=150000u
+C0 a_15_n68# a_n73_n68# 0.04fF
+C1 a_n33_33# a_15_n68# 0.00fF
+C2 a_n33_33# a_n73_n68# 0.00fF
+C3 a_15_n68# VSUBS 0.02fF
+C4 a_n73_n68# VSUBS 0.02fF
+C5 a_n33_33# VSUBS 0.14fF
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel2 net7 ng3 vco_switch_n_v2_3/selb
++ vss vdd sel3
+XXM12 net7 vdd vdd net6 vss sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd net7 net7 net7 vdd out vdd out vss sky130_fd_pr__pfet_01v8_UUCHZP
+XXM25 vdd vgp vdd vgp vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2_0/selb vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2_1/selb vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2_2/selb vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2_3/selb vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd vss sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 vss sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 vss sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd vss sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd vss sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 vss vco_switch_p_0/selb vdd pg0 vco_switch_p
+XXM11A vdd vdd pg0 net2 vss sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11B vdd net2 vdd pg1 vss sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_2 vgp sel2 vss vco_switch_p_2/selb vdd pg2 vco_switch_p
+Xvco_switch_p_1 vgp sel1 vss vco_switch_p_1/selb vdd pg1 vco_switch_p
+XXM21 vdd net6 vdd net5 vss sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 vss vco_switch_p_3/selb vdd pg3 vco_switch_p
+XXM11 vdd vdd vgp net2 vss sky130_fd_pr__pfet_01v8_4XEGTB
+XXM22 net5 vss net6 vss sky130_fd_pr__nfet_01v8_LS29AB
+XXM11C vdd vdd pg2 net2 vss sky130_fd_pr__pfet_01v8_TPJM7Z
+C0 pg2 sel3 0.50fF
+C1 ng0 sel2 0.24fF
+C2 vctrl ng1 0.62fF
+C3 net2 net8 0.04fF
+C4 vco_switch_p_3/selb vdd 0.00fF
+C5 net3 net4 0.08fF
+C6 vdd pg3 1.86fF
+C7 net4 net6 0.00fF
+C8 ng3 sel2 0.02fF
+C9 sel3 vco_switch_p_1/selb 0.01fF
+C10 vdd pg1 0.84fF
+C11 ng0 vco_switch_n_v2_0/selb 0.03fF
+C12 sel3 sel2 7.17fF
+C13 vdd sel1 1.30fF
+C14 vco_switch_n_v2_1/selb sel2 0.05fF
+C15 net3 net2 0.02fF
+C16 ng2 vdd 0.11fF
+C17 vco_switch_n_v2_0/selb sel3 0.02fF
+C18 sel1 sel0 3.63fF
+C19 net2 vgp 0.04fF
+C20 vco_switch_n_v2_0/selb vco_switch_n_v2_1/selb 0.00fF
+C21 ng3 vco_switch_n_v2_3/selb 0.02fF
+C22 ng2 net8 0.02fF
+C23 ng1 sel2 0.27fF
+C24 vctrl sel2 0.41fF
+C25 sel3 vco_switch_n_v2_3/selb 0.26fF
+C26 vco_switch_p_3/selb vgp 0.01fF
+C27 vdd vco_switch_n_v2_2/selb 0.02fF
+C28 pg3 vgp 0.24fF
+C29 vco_switch_p_2/selb vdd 0.02fF
+C30 vdd pg0 2.47fF
+C31 vco_switch_p_0/selb vco_switch_p_1/selb 0.00fF
+C32 net7 net5 0.01fF
+C33 pg1 vgp 0.81fF
+C34 vctrl vco_switch_n_v2_0/selb 0.09fF
+C35 ng3 net4 0.00fF
+C36 vco_switch_p_0/selb sel2 0.05fF
+C37 sel1 vgp 1.27fF
+C38 sel0 pg0 0.06fF
+C39 pg2 sel2 0.26fF
+C40 vdd net5 0.47fF
+C41 net7 vdd 0.96fF
+C42 vctrl vco_switch_n_v2_3/selb 0.01fF
+C43 vco_switch_p_1/selb sel2 0.05fF
+C44 net5 net8 0.16fF
+C45 vco_switch_p_2/selb vgp 0.01fF
+C46 pg0 vgp 2.03fF
+C47 vdd sel0 0.04fF
+C48 vco_switch_n_v2_0/selb sel2 0.05fF
+C49 net7 out 0.45fF
+C50 vco_switch_p_3/selb sel3 0.22fF
+C51 ng0 sel1 0.10fF
+C52 sel3 pg3 0.27fF
+C53 net3 net5 0.17fF
+C54 ng0 ng2 0.01fF
+C55 sel3 pg1 0.10fF
+C56 net5 net6 0.05fF
+C57 net7 net6 0.20fF
+C58 vdd out 0.86fF
+C59 net5 vgp 0.02fF
+C60 sel3 sel1 2.04fF
+C61 ng2 ng3 0.40fF
+C62 net3 vdd 0.28fF
+C63 ng2 sel3 0.05fF
+C64 sel1 vco_switch_n_v2_1/selb 0.33fF
+C65 vdd net6 0.13fF
+C66 vdd vgp 7.37fF
+C67 net3 net8 0.02fF
+C68 pg2 net2 0.02fF
+C69 sel0 vgp 0.25fF
+C70 vgp net8 0.03fF
+C71 ng3 vco_switch_n_v2_2/selb 0.04fF
+C72 sel1 ng1 0.04fF
+C73 vctrl sel1 0.90fF
+C74 vco_switch_n_v2_2/selb sel3 0.01fF
+C75 vco_switch_p_2/selb sel3 0.02fF
+C76 sel3 pg0 0.30fF
+C77 vco_switch_p_1/selb net2 0.00fF
+C78 vco_switch_p_3/selb pg2 0.05fF
+C79 ng2 ng1 0.08fF
+C80 ng2 vctrl 1.22fF
+C81 net6 out 0.01fF
+C82 net2 sel2 0.00fF
+C83 pg2 pg3 0.34fF
+C84 vco_switch_n_v2_2/selb vco_switch_n_v2_1/selb 0.00fF
+C85 vco_switch_p_0/selb sel1 0.17fF
+C86 pg2 pg1 0.07fF
+C87 ng0 vdd 0.11fF
+C88 pg3 sel2 0.04fF
+C89 vco_switch_n_v2_2/selb ng1 0.06fF
+C90 vctrl vco_switch_n_v2_2/selb 0.08fF
+C91 vco_switch_p_1/selb pg1 0.02fF
+C92 ng3 vdd 0.30fF
+C93 ng0 sel0 0.04fF
+C94 pg1 sel2 0.51fF
+C95 ng0 net8 0.16fF
+C96 vco_switch_p_1/selb sel1 0.20fF
+C97 vdd sel3 5.08fF
+C98 sel1 sel2 6.56fF
+C99 ng3 net8 0.05fF
+C100 vdd vco_switch_n_v2_1/selb 0.02fF
+C101 vco_switch_p_0/selb pg0 0.02fF
+C102 sel3 sel0 0.84fF
+C103 ng2 sel2 0.06fF
+C104 vco_switch_n_v2_0/selb sel1 0.20fF
+C105 vco_switch_p_2/selb pg2 0.02fF
+C106 pg2 pg0 0.02fF
+C107 net4 net2 0.00fF
+C108 net3 ng0 0.00fF
+C109 net8 vco_switch_n_v2_1/selb 0.01fF
+C110 vdd ng1 0.11fF
+C111 vctrl vdd 0.66fF
+C112 vco_switch_p_2/selb vco_switch_p_1/selb 0.00fF
+C113 vco_switch_p_1/selb pg0 0.05fF
+C114 vco_switch_n_v2_2/selb sel2 0.21fF
+C115 vco_switch_p_2/selb sel2 0.11fF
+C116 pg0 sel2 0.43fF
+C117 vctrl sel0 0.54fF
+C118 net8 ng1 0.00fF
+C119 vctrl net8 0.01fF
+C120 vco_switch_p_0/selb vdd 0.02fF
+C121 ng2 vco_switch_n_v2_3/selb 0.06fF
+C122 sel3 vgp 3.29fF
+C123 vdd pg2 1.69fF
+C124 vco_switch_p_0/selb sel0 0.03fF
+C125 ng2 net4 0.00fF
+C126 net2 pg3 0.06fF
+C127 vdd vco_switch_p_1/selb 0.02fF
+C128 vco_switch_n_v2_2/selb vco_switch_n_v2_3/selb 0.00fF
+C129 vdd sel2 2.00fF
+C130 net2 pg1 0.00fF
+C131 vctrl vgp 0.00fF
+C132 sel0 sel2 1.72fF
+C133 ng0 sel3 0.02fF
+C134 vdd vco_switch_n_v2_0/selb 0.02fF
+C135 pg1 pg3 0.02fF
+C136 vco_switch_p_0/selb vgp 0.01fF
+C137 ng0 vco_switch_n_v2_1/selb 0.06fF
+C138 ng3 sel3 0.04fF
+C139 vco_switch_n_v2_0/selb sel0 0.05fF
+C140 pg2 vgp 1.40fF
+C141 sel1 pg1 0.14fF
+C142 vdd vco_switch_n_v2_3/selb 0.02fF
+C143 net4 net5 0.15fF
+C144 net2 pg0 0.17fF
+C145 sel3 vco_switch_n_v2_1/selb 0.01fF
+C146 vco_switch_p_1/selb vgp 0.01fF
+C147 ng0 ng1 0.12fF
+C148 ng0 vctrl 1.74fF
+C149 vgp sel2 1.47fF
+C150 net4 vdd 0.19fF
+C151 vco_switch_p_2/selb vco_switch_p_3/selb 0.00fF
+C152 ng3 ng1 0.02fF
+C153 vctrl ng3 0.25fF
+C154 vco_switch_p_2/selb pg3 0.01fF
+C155 sel3 ng1 0.02fF
+C156 net5 net2 0.18fF
+C157 vctrl sel3 0.37fF
+C158 net4 net8 0.01fF
+C159 vco_switch_p_2/selb pg1 0.05fF
+C160 pg1 pg0 0.11fF
+C161 vco_switch_n_v2_1/selb ng1 0.03fF
+C162 vctrl vco_switch_n_v2_1/selb 0.09fF
+C163 sel1 pg0 0.37fF
+C164 vdd net2 4.18fF
+C165 vco_switch_p_0/selb sel3 0.01fF
+C166 ng2 vco_switch_n_v2_2/selb 0.03fF
+C167 net6 vss 0.58fF
+C168 vco_switch_p_3/selb vss -0.05fF
+C169 sel3 vss 0.68fF
+C170 pg3 vss 0.29fF
+C171 vco_switch_p_1/selb vss -0.05fF
+C172 sel1 vss 0.89fF
+C173 pg1 vss -0.19fF
+C174 vco_switch_p_2/selb vss -0.05fF
+C175 sel2 vss 1.03fF
+C176 pg2 vss -0.55fF
+C177 vco_switch_p_0/selb vss -0.05fF
+C178 sel0 vss 2.16fF
+C179 pg0 vss -0.94fF
+C180 net4 vss 0.55fF
+C181 net3 vss 0.32fF
+C182 net5 vss 1.96fF
+C183 net2 vss -1.31fF
+C184 vco_switch_n_v2_3/selb vss 0.60fF
+C185 ng3 vss 2.57fF
+C186 vco_switch_n_v2_2/selb vss 0.66fF
+C187 ng2 vss 1.74fF
+C188 vco_switch_n_v2_1/selb vss 0.65fF
+C189 vdd vss 18.26fF
+C190 ng1 vss 1.14fF
+C191 vctrl vss 5.22fF
+C192 vco_switch_n_v2_0/selb vss 0.65fF
+C193 ng0 vss 2.03fF
+C194 net8 vss 5.56fF
+C195 vgp vss -1.62fF
+C196 out vss 0.01fF
+C197 net7 vss 0.82fF
+.ends
+
+*.subckt vco_with_fdivs_lasttry vctrl out_div128 vdd vss vsel0 vsel1 vsel2 vsel3 out_div256
+.subckt vco_with_fdivs vctrl out_div128 vdd vss vsel0 vsel1 vsel2 vsel3 out_div256
+XFD_v2_3 vdd vss FD_v2_4/Clk_In FD_v2_3/7 FD_v2_3/5 FD_v2_3/4 FD_v2_3/3 FD_v2_3/Clkb
++ FD_v2_3/6 FD_v2_3/Clk_In FD_v2_3/2 FD_v2
+XFD_v2_4 vdd vss FD_v2_5/Clk_In FD_v2_4/7 FD_v2_4/5 FD_v2_4/4 FD_v2_4/3 FD_v2_4/Clkb
++ FD_v2_4/6 FD_v2_4/Clk_In FD_v2_4/2 FD_v2
+XFD_v2_5 vdd vss FD_v2_6/Clk_In FD_v2_5/7 FD_v2_5/5 FD_v2_5/4 FD_v2_5/3 FD_v2_5/Clkb
++ FD_v2_5/6 FD_v2_5/Clk_In FD_v2_5/2 FD_v2
+XFD_v2_6 vdd vss out_div128 FD_v2_6/7 FD_v2_6/5 FD_v2_6/4 FD_v2_6/3 FD_v2_6/Clkb FD_v2_6/6
++ FD_v2_6/Clk_In FD_v2_6/2 FD_v2
+XFD_v2_7 vdd vss out_div256 FD_v2_7/7 FD_v2_7/5 FD_v2_7/4 FD_v2_7/3 FD_v2_7/Clkb FD_v2_7/6
++ out_div128 FD_v2_7/2 FD_v2
+XFD_v2_8 vdd vss FD_v2_9/Clk_In FD_v2_8/7 FD_v2_8/5 FD_v2_8/4 FD_v2_8/3 FD_v2_8/Clkb
++ FD_v2_8/6 out_div256 FD_v2_8/2 FD_v2
+XFD_v2_9 vdd vss FD_v2_9/Clk_Out FD_v2_9/7 FD_v2_9/5 FD_v2_9/4 FD_v2_9/3 FD_v2_9/Clkb
++ FD_v2_9/6 FD_v2_9/Clk_In FD_v2_9/2 FD_v2
+XFD_v5_lasttry_0 out vdd vss FD_v2_1/Clk_In FD_v5_lasttry_0/Clkb_buf FD_v5_lasttry_0/dus
++ FD_v5_lasttry_0/7 FD_v5_lasttry_0/4 FD_v5_lasttry_0/3 FD_v5_lasttry_0/5 FD_v5_lasttry_0/2
++ FD_v5_lasttry_0/Clkb_int FD_v5_lasttry_0/Clk_In_buf FD_v5_lasttry_0/6 FD_v5_lasttry
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel2 3-stage_cs-vco_dp9_0/net7 3-stage_cs-vco_dp9_0/ng3
++ 3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb vss vdd vsel3 x3-stage_cs-vco_dp9
+XFD_v2_1 vdd vss FD_v2_2/Clk_In FD_v2_1/7 FD_v2_1/5 FD_v2_1/4 FD_v2_1/3 FD_v2_1/Clkb
++ FD_v2_1/6 FD_v2_1/Clk_In FD_v2_1/2 FD_v2
+XFD_v2_2 vdd vss FD_v2_3/Clk_In FD_v2_2/7 FD_v2_2/5 FD_v2_2/4 FD_v2_2/3 FD_v2_2/Clkb
++ FD_v2_2/6 FD_v2_2/Clk_In FD_v2_2/2 FD_v2
+C0 FD_v2_2/6 FD_v5_lasttry_0/3 0.00fF
+C1 FD_v2_1/6 FD_v2_6/Clkb 0.01fF
+C2 FD_v2_2/2 FD_v2_5/6 0.00fF
+C3 FD_v5_lasttry_0/Clk_In_buf FD_v2_3/Clk_In 0.01fF
+C4 FD_v2_1/2 FD_v2_6/6 0.00fF
+C5 FD_v2_6/4 FD_v2_7/6 0.01fF
+C6 FD_v2_7/5 FD_v2_6/Clkb 0.01fF
+C7 FD_v2_3/2 FD_v2_4/Clk_In 0.01fF
+C8 FD_v2_9/6 FD_v2_4/Clk_In 0.02fF
+C9 FD_v2_6/6 FD_v2_7/3 0.00fF
+C10 FD_v2_2/7 FD_v2_3/2 0.02fF
+C11 FD_v2_4/3 FD_v2_9/2 0.00fF
+C12 FD_v2_6/6 FD_v2_1/Clkb 0.01fF
+C13 FD_v2_5/Clkb FD_v2_2/2 0.02fF
+C14 FD_v2_3/4 FD_v2_4/Clk_In 0.01fF
+C15 FD_v5_lasttry_0/4 FD_v2_2/3 0.00fF
+C16 vdd FD_v2_1/7 0.01fF
+C17 FD_v5_lasttry_0/Clkb_buf FD_v2_3/5 0.00fF
+C18 FD_v2_2/7 FD_v5_lasttry_0/Clk_In_buf 0.01fF
+C19 FD_v2_5/7 out_div256 0.04fF
+C20 FD_v2_2/4 FD_v2_5/Clk_In 0.01fF
+C21 FD_v2_8/4 FD_v2_5/6 0.01fF
+C22 FD_v2_9/3 FD_v2_9/Clk_In 0.03fF
+C23 FD_v2_3/6 FD_v2_4/Clkb 0.01fF
+C24 FD_v5_lasttry_0/dus FD_v2_3/4 0.00fF
+C25 vdd vsel3 0.00fF
+C26 vdd FD_v2_8/7 0.01fF
+C27 FD_v2_3/Clk_In FD_v2_4/Clk_In 0.01fF
+C28 FD_v2_5/2 FD_v2_8/6 0.00fF
+C29 FD_v2_9/Clk_In FD_v2_8/7 0.08fF
+C30 FD_v2_2/2 FD_v2_5/Clk_In 0.01fF
+C31 FD_v2_2/7 FD_v2_3/Clk_In 0.08fF
+C32 FD_v2_9/2 FD_v2_8/7 0.02fF
+C33 vdd FD_v2_4/7 0.01fF
+C34 FD_v2_8/Clkb FD_v2_5/2 0.01fF
+C35 FD_v2_2/Clkb FD_v2_1/7 0.00fF
+C36 FD_v2_9/Clkb vdd 0.04fF
+C37 FD_v2_2/Clk_In FD_v2_5/Clk_In 0.01fF
+C38 FD_v2_1/6 FD_v5_lasttry_0/Clkb_buf 0.04fF
+C39 FD_v2_9/Clkb FD_v2_4/5 0.01fF
+C40 FD_v2_9/Clk_In FD_v2_4/7 0.04fF
+C41 FD_v2_9/Clkb FD_v2_9/Clk_In 0.07fF
+C42 FD_v5_lasttry_0/Clkb_buf FD_v2_1/Clk_In 0.01fF
+C43 FD_v2_9/2 FD_v2_4/7 0.01fF
+C44 FD_v2_5/Clkb FD_v2_8/4 0.01fF
+C45 FD_v5_lasttry_0/dus FD_v2_3/Clk_In 0.00fF
+C46 vdd FD_v2_7/7 0.01fF
+C47 FD_v2_2/6 FD_v2_5/2 0.00fF
+C48 FD_v2_7/2 out_div128 0.00fF
+C49 FD_v2_5/7 FD_v2_6/2 0.02fF
+C50 vdd FD_v2_6/Clk_In 0.07fF
+C51 FD_v2_1/2 FD_v2_6/Clkb 0.02fF
+C52 FD_v2_4/4 FD_v2_9/5 0.00fF
+C53 FD_v2_8/Clkb FD_v2_5/6 0.04fF
+C54 FD_v2_5/3 FD_v2_2/2 0.00fF
+C55 FD_v5_lasttry_0/5 FD_v2_1/Clkb 0.01fF
+C56 FD_v2_6/6 FD_v2_7/4 0.01fF
+C57 FD_v2_1/7 FD_v2_2/2 0.02fF
+C58 FD_v2_4/6 FD_v2_3/Clkb 0.01fF
+C59 out_div128 FD_v2_7/Clkb 0.01fF
+C60 vdd FD_v2_3/Clk_In 0.07fF
+C61 FD_v2_2/Clk_In FD_v2_1/7 0.08fF
+C62 FD_v2_5/Clkb FD_v2_8/6 0.04fF
+C63 FD_v2_3/Clk_In FD_v2_4/5 0.01fF
+C64 FD_v2_2/Clkb FD_v5_lasttry_0/Clk_In_buf 0.13fF
+C65 FD_v2_1/7 FD_v2_6/Clkb 0.04fF
+C66 FD_v2_5/Clkb FD_v2_8/Clkb 0.02fF
+C67 FD_v2_2/5 FD_v2_5/Clk_In 0.01fF
+C68 FD_v5_lasttry_0/2 FD_v2_2/6 0.00fF
+C69 out_div256 FD_v2_5/2 0.00fF
+C70 out_div256 FD_v2_8/Clkb 0.07fF
+C71 FD_v2_9/Clkb FD_v2_4/Clkb 0.02fF
+C72 FD_v2_3/2 FD_v2_4/Clkb 0.02fF
+C73 FD_v2_9/6 FD_v2_4/Clkb 0.04fF
+C74 FD_v2_5/7 FD_v2_8/2 0.01fF
+C75 FD_v2_5/Clkb FD_v2_2/6 0.01fF
+C76 vdd FD_v2_4/Clk_In 0.18fF
+C77 FD_v2_6/2 FD_v2_7/Clkb 0.01fF
+C78 FD_v2_4/6 FD_v2_5/Clk_In 0.02fF
+C79 FD_v2_1/2 FD_v2_6/3 0.00fF
+C80 FD_v2_2/7 vdd 0.01fF
+C81 FD_v2_2/4 FD_v5_lasttry_0/Clk_In_buf 0.00fF
+C82 FD_v2_8/6 FD_v2_5/Clk_In 0.02fF
+C83 FD_v5_lasttry_0/Clkb_buf FD_v2_1/3 0.00fF
+C84 FD_v2_9/2 FD_v2_4/Clk_In 0.00fF
+C85 FD_v2_7/4 FD_v2_6/5 0.00fF
+C86 FD_v2_4/Clk_In FD_v2_9/7 0.04fF
+C87 FD_v5_lasttry_0/Clkb_buf FD_v2_1/2 0.00fF
+C88 FD_v2_5/2 FD_v2_5/Clk_In 0.01fF
+C89 out_div256 FD_v2_5/6 0.02fF
+C90 FD_v5_lasttry_0/Clkb_buf FD_v2_3/3 0.00fF
+C91 FD_v5_lasttry_0/Clk_In_buf FD_v2_2/2 0.00fF
+C92 FD_v2_5/7 FD_v2_6/Clk_In 0.08fF
+C93 FD_v2_1/4 FD_v2_6/Clk_In 0.01fF
+C94 FD_v2_7/7 FD_v2_6/Clkb 0.01fF
+C95 FD_v2_3/7 FD_v2_4/Clk_In 0.01fF
+C96 FD_v5_lasttry_0/Clk_In_buf FD_v2_2/Clk_In 0.08fF
+C97 FD_v2_7/6 FD_v2_6/Clkb 0.04fF
+C98 FD_v2_6/Clk_In FD_v2_6/Clkb 0.07fF
+C99 FD_v2_5/Clkb FD_v2_8/5 0.01fF
+C100 FD_v5_lasttry_0/Clkb_buf FD_v2_1/Clkb 0.08fF
+C101 FD_v2_7/2 FD_v2_6/7 0.01fF
+C102 FD_v2_5/3 FD_v2_8/6 0.00fF
+C103 FD_v2_7/2 FD_v2_6/Clk_In 0.00fF
+C104 FD_v2_7/4 FD_v2_6/Clkb 0.01fF
+C105 FD_v2_8/3 FD_v2_5/2 0.00fF
+C106 FD_v2_1/6 FD_v2_6/2 0.00fF
+C107 FD_v2_1/Clk_In FD_v2_6/2 0.01fF
+C108 FD_v2_9/3 FD_v2_4/6 0.00fF
+C109 vdd FD_v2_9/Clk_In 0.07fF
+C110 FD_v2_4/2 FD_v2_3/Clkb 0.02fF
+C111 FD_v2_9/2 FD_v2_9/Clk_In 0.01fF
+C112 FD_v2_5/Clkb FD_v2_5/Clk_In 0.07fF
+C113 FD_v2_7/Clkb FD_v2_6/7 0.01fF
+C114 FD_v2_8/3 FD_v2_5/6 0.00fF
+C115 FD_v2_9/Clkb FD_v2_4/6 0.04fF
+C116 FD_v2_5/2 FD_v2_8/7 0.01fF
+C117 FD_v2_3/2 FD_v2_4/6 0.00fF
+C118 FD_v2_2/5 FD_v5_lasttry_0/Clk_In_buf 0.00fF
+C119 FD_v2_7/6 FD_v2_6/3 0.00fF
+C120 FD_v2_2/Clkb vdd 0.04fF
+C121 FD_v2_6/Clk_In FD_v2_6/3 0.03fF
+C122 FD_v2_1/5 FD_v5_lasttry_0/6 0.01fF
+C123 FD_v2_5/2 FD_v2_4/7 0.02fF
+C124 FD_v2_1/6 FD_v5_lasttry_0/6 0.00fF
+C125 FD_v5_lasttry_0/2 FD_v2_1/Clkb 0.00fF
+C126 FD_v2_4/2 FD_v2_3/6 0.00fF
+C127 FD_v5_lasttry_0/6 FD_v2_1/Clk_In 0.05fF
+C128 FD_v2_7/7 FD_v2_8/Clkb 0.00fF
+C129 out_div256 FD_v2_8/3 0.03fF
+C130 out_div128 FD_v2_6/2 0.00fF
+C131 FD_v2_8/2 FD_v2_5/6 0.00fF
+C132 out 3-stage_cs-vco_dp9_0/net7 0.00fF
+C133 FD_v2_4/2 FD_v2_3/3 0.00fF
+C134 FD_v2_6/4 FD_v2_7/Clkb 0.01fF
+C135 FD_v2_2/Clk_In FD_v2_2/3 0.03fF
+C136 FD_v2_1/5 FD_v2_6/Clk_In 0.01fF
+C137 FD_v2_9/Clk_Out FD_v2_4/Clk_In 0.01fF
+C138 FD_v5_lasttry_0/Clkb_buf FD_v2_3/Clk_In 0.00fF
+C139 FD_v2_9/2 FD_v2_4/Clkb 0.01fF
+C140 FD_v2_2/6 FD_v5_lasttry_0/Clk_In_buf 0.04fF
+C141 FD_v2_1/3 FD_v2_6/2 0.00fF
+C142 FD_v2_1/Clk_In FD_v2_6/7 0.01fF
+C143 FD_v2_4/Clkb FD_v2_9/7 0.01fF
+C144 FD_v2_1/Clk_In FD_v2_6/Clk_In 0.01fF
+C145 FD_v2_5/7 vdd 0.01fF
+C146 vdd FD_v2_2/Clk_In 0.07fF
+C147 FD_v2_9/4 FD_v2_4/5 0.00fF
+C148 FD_v5_lasttry_0/3 FD_v2_2/3 0.01fF
+C149 FD_v2_5/Clkb FD_v2_8/2 0.01fF
+C150 FD_v2_5/Clkb FD_v2_8/7 0.01fF
+C151 FD_v2_5/3 FD_v2_5/Clk_In 0.03fF
+C152 out_div256 FD_v2_8/2 0.01fF
+C153 vdd FD_v2_6/Clkb 0.04fF
+C154 FD_v2_6/Clk_In FD_v2_5/6 0.02fF
+C155 FD_v2_6/2 FD_v2_7/3 0.00fF
+C156 FD_v2_3/7 FD_v2_4/Clkb 0.04fF
+C157 FD_v2_3/Clkb FD_v2_4/7 0.04fF
+C158 FD_v2_5/Clkb FD_v2_4/7 0.00fF
+C159 FD_v2_3/5 FD_v2_4/Clk_In 0.01fF
+C160 FD_v2_2/6 FD_v2_3/Clk_In 0.02fF
+C161 FD_v2_4/2 FD_v2_9/3 0.00fF
+C162 FD_v2_6/2 FD_v2_1/Clkb 0.02fF
+C163 FD_v2_2/Clk_In FD_v2_5/4 0.01fF
+C164 FD_v2_7/2 FD_v2_6/6 0.00fF
+C165 FD_v2_2/Clkb FD_v2_5/7 0.04fF
+C166 FD_v2_2/Clkb FD_v2_2/Clk_In 0.07fF
+C167 out_div256 FD_v2_7/7 0.08fF
+C168 FD_v2_8/2 FD_v2_5/Clk_In 0.00fF
+C169 FD_v2_8/7 FD_v2_5/Clk_In 0.04fF
+C170 out_div256 FD_v2_7/6 0.02fF
+C171 FD_v2_1/Clk_In FD_v2_6/4 0.01fF
+C172 out_div256 FD_v2_6/Clk_In 0.01fF
+C173 FD_v5_lasttry_0/7 FD_v2_1/Clk_In 0.00fF
+C174 FD_v2_9/Clkb FD_v2_4/2 0.01fF
+C175 FD_v2_2/Clkb FD_v5_lasttry_0/3 0.00fF
+C176 FD_v2_7/5 FD_v2_6/4 0.00fF
+C177 FD_v2_4/2 FD_v2_9/6 0.00fF
+C178 FD_v2_5/5 FD_v2_2/Clk_In 0.01fF
+C179 FD_v2_5/Clk_In FD_v2_4/7 0.08fF
+C180 out_div128 FD_v2_6/7 0.06fF
+C181 FD_v2_9/Clkb FD_v2_4/4 0.01fF
+C182 FD_v2_4/4 FD_v2_9/6 0.01fF
+C183 FD_v2_9/4 FD_v2_4/Clkb 0.01fF
+C184 out FD_v5_lasttry_0/dus 0.00fF
+C185 FD_v2_6/6 FD_v2_7/Clkb 0.04fF
+C186 FD_v2_3/Clk_In FD_v2_3/Clkb 0.07fF
+C187 FD_v2_2/4 FD_v5_lasttry_0/3 0.00fF
+C188 FD_v5_lasttry_0/4 FD_v2_1/7 0.00fF
+C189 FD_v2_2/Clk_In FD_v2_2/2 0.01fF
+C190 FD_v2_8/2 FD_v2_5/3 0.00fF
+C191 FD_v2_7/7 FD_v2_6/2 0.01fF
+C192 FD_v2_3/2 FD_v2_4/3 0.00fF
+C193 FD_v2_4/3 FD_v2_9/6 0.00fF
+C194 FD_v2_2/Clk_In FD_v5_lasttry_0/5 0.00fF
+C195 FD_v2_5/7 FD_v2_2/Clk_In 0.01fF
+C196 FD_v2_1/2 FD_v2_6/Clk_In 0.01fF
+C197 FD_v2_4/Clkb FD_v2_9/5 0.01fF
+C198 FD_v2_5/2 FD_v2_2/3 0.00fF
+C199 FD_v2_1/4 FD_v5_lasttry_0/5 0.00fF
+C200 FD_v2_6/2 FD_v2_7/6 0.00fF
+C201 FD_v2_4/6 FD_v2_9/Clk_In 0.02fF
+C202 FD_v2_6/Clk_In FD_v2_6/2 0.01fF
+C203 FD_v5_lasttry_0/3 FD_v2_2/2 0.00fF
+C204 FD_v2_9/2 FD_v2_4/6 0.00fF
+C205 FD_v2_5/5 FD_v2_8/4 0.00fF
+C206 FD_v2_9/Clk_In FD_v2_8/6 0.02fF
+C207 FD_v2_5/7 FD_v2_6/Clkb 0.00fF
+C208 vdd FD_v2_8/Clkb 0.04fF
+C209 FD_v2_4/2 FD_v2_3/Clk_In 0.01fF
+C210 FD_v2_2/Clk_In FD_v5_lasttry_0/3 0.01fF
+C211 FD_v2_2/7 FD_v2_3/Clkb 0.00fF
+C212 FD_v2_2/7 FD_v2_5/Clkb 0.04fF
+C213 out vdd 0.05fF
+C214 FD_v2_1/Clkb FD_v2_6/7 0.04fF
+C215 FD_v2_4/4 FD_v2_3/Clk_In 0.01fF
+C216 FD_v2_6/5 FD_v2_7/Clkb 0.01fF
+C217 FD_v2_8/6 FD_v2_5/4 0.01fF
+C218 FD_v2_7/2 FD_v2_6/Clkb 0.01fF
+C219 FD_v2_6/Clk_In FD_v2_1/7 0.01fF
+C220 FD_v2_3/3 FD_v2_3/Clk_In 0.03fF
+C221 FD_v2_8/Clkb FD_v2_5/4 0.01fF
+C222 FD_v2_9/Clkb FD_v2_8/7 0.00fF
+C223 FD_v2_2/Clkb FD_v2_5/2 0.02fF
+C224 out FD_v2_3/7 0.00fF
+C225 FD_v2_7/7 FD_v2_8/2 0.02fF
+C226 FD_v2_2/7 FD_v2_5/Clk_In 0.01fF
+C227 FD_v2_9/Clkb FD_v2_4/7 0.01fF
+C228 FD_v2_5/5 FD_v2_8/Clkb 0.01fF
+C229 FD_v2_7/Clkb FD_v2_6/Clkb 0.02fF
+C230 FD_v2_3/6 FD_v5_lasttry_0/dus 0.00fF
+C231 vdd FD_v2_3/Clkb 0.04fF
+C232 FD_v2_5/Clkb vdd 0.04fF
+C233 FD_v2_2/5 FD_v5_lasttry_0/3 0.00fF
+C234 out FD_v5_lasttry_0/Clkb_int 0.00fF
+C235 vdd out_div256 0.07fF
+C236 FD_v2_2/Clkb FD_v2_5/6 0.01fF
+C237 FD_v2_9/4 FD_v2_4/6 0.01fF
+C238 FD_v2_1/4 FD_v5_lasttry_0/Clkb_buf 0.00fF
+C239 FD_v2_7/7 FD_v2_6/Clk_In 0.04fF
+C240 FD_v2_1/Clk_In FD_v2_6/5 0.01fF
+C241 FD_v2_6/Clk_In FD_v2_7/6 0.02fF
+C242 FD_v2_5/4 FD_v2_8/5 0.00fF
+C243 FD_v2_7/2 FD_v2_6/3 0.00fF
+C244 FD_v2_5/7 FD_v2_8/Clkb 0.01fF
+C245 FD_v2_2/Clk_In FD_v2_5/2 0.01fF
+C246 out_div128 FD_v2_6/6 0.02fF
+C247 FD_v2_3/Clk_In FD_v2_4/7 0.01fF
+C248 FD_v2_4/2 FD_v2_9/Clk_In 0.00fF
+C249 FD_v2_3/2 FD_v2_3/Clk_In 0.01fF
+C250 vdd FD_v2_5/Clk_In 0.07fF
+C251 FD_v2_1/5 FD_v5_lasttry_0/5 0.01fF
+C252 FD_v2_4/2 FD_v2_9/7 0.01fF
+C253 FD_v2_9/Clk_In FD_v2_5/Clk_In 0.01fF
+C254 FD_v2_1/6 FD_v2_2/Clk_In 0.02fF
+C255 FD_v2_1/6 FD_v5_lasttry_0/5 0.01fF
+C256 FD_v2_2/Clkb vss 0.98fF
+C257 FD_v2_2/7 vss 0.50fF
+C258 FD_v2_2/5 vss 0.15fF
+C259 FD_v2_2/Clk_In vss 1.21fF
+C260 FD_v2_2/3 vss 0.03fF
+C261 FD_v2_2/2 vss 0.93fF
+C262 FD_v2_2/6 vss 0.86fF
+C263 FD_v2_2/4 vss 0.12fF
+C264 FD_v2_1/Clkb vss 1.03fF
+C265 FD_v2_1/7 vss 0.50fF
+C266 FD_v2_1/5 vss 0.15fF
+C267 FD_v2_1/Clk_In vss 1.72fF
+C268 FD_v2_1/3 vss 0.03fF
+C269 FD_v2_1/2 vss 0.97fF
+C270 FD_v2_1/6 vss 0.86fF
+C271 FD_v2_1/4 vss 0.12fF
+C272 3-stage_cs-vco_dp9_0/net6 vss 0.15fF
+C273 3-stage_cs-vco_dp9_0/vco_switch_p_3/selb vss -0.05fF
+C274 vsel3 vss 0.79fF
+C275 3-stage_cs-vco_dp9_0/pg3 vss 0.33fF
+C276 3-stage_cs-vco_dp9_0/vco_switch_p_1/selb vss -0.05fF
+C277 vsel1 vss 1.03fF
+C278 3-stage_cs-vco_dp9_0/pg1 vss -0.14fF
+C279 3-stage_cs-vco_dp9_0/vco_switch_p_2/selb vss -0.05fF
+C280 vsel2 vss 1.17fF
+C281 3-stage_cs-vco_dp9_0/pg2 vss -0.51fF
+C282 3-stage_cs-vco_dp9_0/vco_switch_p_0/selb vss -0.05fF
+C283 vsel0 vss 1.73fF
+C284 3-stage_cs-vco_dp9_0/pg0 vss -0.91fF
+C285 3-stage_cs-vco_dp9_0/net4 vss 0.31fF
+C286 3-stage_cs-vco_dp9_0/net3 vss -0.06fF
+C287 3-stage_cs-vco_dp9_0/net5 vss 1.34fF
+C288 3-stage_cs-vco_dp9_0/net2 vss -1.31fF
+C289 3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb vss 0.60fF
+C290 3-stage_cs-vco_dp9_0/ng3 vss 2.39fF
+C291 3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb vss 0.60fF
+C292 3-stage_cs-vco_dp9_0/ng2 vss 1.48fF
+C293 3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb vss 0.60fF
+C294 vdd vss 43.96fF
+C295 3-stage_cs-vco_dp9_0/ng1 vss 0.82fF
+C296 vctrl vss 2.97fF
+C297 3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb vss 0.60fF
+C298 3-stage_cs-vco_dp9_0/ng0 vss 1.67fF
+C299 3-stage_cs-vco_dp9_0/net8 vss 3.38fF
+C300 3-stage_cs-vco_dp9_0/vgp vss -2.11fF
+C301 out vss 0.01fF
+C302 3-stage_cs-vco_dp9_0/net7 vss 0.21fF
+C303 FD_v5_lasttry_0/6 vss 1.27fF
+C304 FD_v5_lasttry_0/4 vss 0.37fF
+C305 FD_v5_lasttry_0/Clk_In_buf vss 2.77fF
+C306 FD_v5_lasttry_0/Clkb_buf vss 4.03fF
+C307 FD_v5_lasttry_0/7 vss 0.46fF
+C308 FD_v5_lasttry_0/Clkb_int vss 0.64fF
+C309 FD_v5_lasttry_0/5 vss 0.40fF
+C310 FD_v5_lasttry_0/dus vss 0.57fF
+C311 FD_v5_lasttry_0/3 vss 0.40fF
+C312 FD_v5_lasttry_0/2 vss 1.69fF
+C313 FD_v2_9/Clkb vss 0.96fF
+C314 FD_v2_9/7 vss 0.47fF
+C315 FD_v2_9/Clk_Out vss 0.12fF
+C316 FD_v2_9/5 vss 0.12fF
+C317 FD_v2_9/Clk_In vss 1.24fF
+C318 FD_v2_9/3 vss 0.02fF
+C319 FD_v2_9/2 vss 0.92fF
+C320 FD_v2_9/6 vss 0.82fF
+C321 FD_v2_9/4 vss 0.09fF
+C322 FD_v2_8/Clkb vss 0.96fF
+C323 FD_v2_8/7 vss 0.49fF
+C324 FD_v2_8/5 vss 0.12fF
+C325 out_div256 vss 1.23fF
+C326 FD_v2_8/3 vss 0.02fF
+C327 FD_v2_8/2 vss 0.92fF
+C328 FD_v2_8/6 vss 0.82fF
+C329 FD_v2_8/4 vss 0.09fF
+C330 FD_v2_7/Clkb vss 0.93fF
+C331 FD_v2_7/7 vss 0.49fF
+C332 FD_v2_7/5 vss 0.12fF
+C333 out_div128 vss 1.50fF
+C334 FD_v2_7/3 vss 0.02fF
+C335 FD_v2_7/2 vss 0.92fF
+C336 FD_v2_7/6 vss 0.82fF
+C337 FD_v2_7/4 vss 0.09fF
+C338 FD_v2_6/Clkb vss 0.96fF
+C339 FD_v2_6/7 vss 0.47fF
+C340 FD_v2_6/5 vss 0.12fF
+C341 FD_v2_6/Clk_In vss 1.19fF
+C342 FD_v2_6/3 vss 0.02fF
+C343 FD_v2_6/2 vss 0.92fF
+C344 FD_v2_6/6 vss 0.82fF
+C345 FD_v2_6/4 vss 0.09fF
+C346 FD_v2_5/Clkb vss 0.96fF
+C347 FD_v2_5/7 vss 0.49fF
+C348 FD_v2_5/5 vss 0.12fF
+C349 FD_v2_5/Clk_In vss 1.22fF
+C350 FD_v2_5/3 vss 0.02fF
+C351 FD_v2_5/2 vss 0.92fF
+C352 FD_v2_5/6 vss 0.82fF
+C353 FD_v2_5/4 vss 0.09fF
+C354 FD_v2_4/Clkb vss 0.94fF
+C355 FD_v2_4/7 vss 0.49fF
+C356 FD_v2_4/5 vss 0.12fF
+C357 FD_v2_4/Clk_In vss 2.07fF
+C358 FD_v2_4/3 vss 0.02fF
+C359 FD_v2_4/2 vss 0.92fF
+C360 FD_v2_4/6 vss 0.82fF
+C361 FD_v2_4/4 vss 0.09fF
+C362 FD_v2_3/Clkb vss 0.98fF
+C363 FD_v2_3/7 vss 0.48fF
+C364 FD_v2_3/5 vss 0.15fF
+C365 FD_v2_3/Clk_In vss 1.21fF
+C366 FD_v2_3/3 vss 0.03fF
+C367 FD_v2_3/2 vss 0.93fF
+C368 FD_v2_3/6 vss 0.86fF
+C369 FD_v2_3/4 vss 0.12fF
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry_POST_LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry_POST_LAYOUT_tb.log
new file mode 100755
index 0000000..e340274
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/old/vco_with_fdivs_lasttry_POST_LAYOUT_tb.log
@@ -0,0 +1,851 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 1.79999
+x1.fd_v2_3/clk_in 1.79999
+x1.fd_v2_3/3 1.79999
+x1.fd_v2_3/6 1.32618
+x1.fd_v2_3/clkb -1.6935e-05
+x1.fd_v2_3/5 -8.75197e-05
+net1 1.8
+x1.fd_v2_3/2 0.00127916
+x1.fd_v2_4/clk_in 1.8
+x1.fd_v2_3/7 0.00128433
+x1.fd_v2_4/4 0.000557742
+x1.fd_v2_4/3 0.00055798
+x1.fd_v2_4/6 0.83542
+x1.fd_v2_4/clkb 5.27838e-07
+x1.fd_v2_4/5 1.8
+x1.fd_v2_4/2 1.37878
+x1.fd_v2_5/clk_in 0.000558381
+x1.fd_v2_4/7 1.37878
+x1.fd_v2_5/4 0.837358
+x1.fd_v2_5/3 1.8
+x1.fd_v2_5/6 1.35609
+x1.fd_v2_5/clkb 1.8
+x1.fd_v2_5/5 1.35609
+x1.fd_v2_5/2 0.000803825
+x1.fd_v2_6/clk_in 1.80002
+x1.fd_v2_5/7 0.000805604
+x1.fd_v2_6/4 -2.66113e-05
+x1.fd_v2_6/3 -2.68612e-05
+x1.fd_v2_6/6 0.722901
+x1.fd_v2_6/clkb 3.62476e-07
+x1.fd_v2_6/5 1.79995
+x1.fd_v2_6/2 1.76471
+out_div128_buf 1.39707e-06
+x1.fd_v2_6/7 1.76463
+x1.fd_v2_7/4 1.79458
+x1.fd_v2_7/3 2.04891e-06
+x1.fd_v2_7/6 2.92659e-06
+x1.fd_v2_7/clkb 1.8
+x1.fd_v2_7/5 -3.87318e-06
+x1.fd_v2_7/2 1.8
+out_div256_buf 1.49349e-07
+x1.fd_v2_7/7 1.8
+x1.fd_v2_8/4 1.781
+x1.fd_v2_8/3 -5.55739e-07
+x1.fd_v2_8/6 1.04314e-05
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 -3.17817e-05
+x1.fd_v2_8/2 1.8
+x1.fd_v2_9/clk_in 1.12744e-06
+x1.fd_v2_8/7 1.8
+x1.fd_v2_9/4 0.0683538
+x1.fd_v2_9/3 1.8
+x1.fd_v2_9/6 1.8
+x1.fd_v2_9/clkb 1.8
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 9.79813e-07
+x1.fd_v2_9/clk_out 1.8
+x1.fd_v2_9/7 9.80637e-07
+x1.fd_v5_lasttry_0/4 0.34441
+x1.fd_v5_lasttry_0/5 1.78753
+x1.fd_v5_lasttry_0/2 -0.0213527
+x1.fd_v5_lasttry_0/3 1.781
+x1.fd_v5_lasttry_0/clkb_buf 1.79198
+x1.fd_v5_lasttry_0/clk_in_buf -0.00718786
+x1.fd_v5_lasttry_0/clkb_int 1.79818
+x1.fd_v5_lasttry_0/dus -0.0038805
+x1.fd_v5_lasttry_0/6 1.79645
+x1.fd_v5_lasttry_0/7 -0.0182771
+x1.fd_v2_1/clk_in 1.784
+x1.out -0.013312
+x1.3-stage_cs-vco_dp9_0/net7 1.79775
+x1.x3-stage_cs-vco_dp9_0.net6 0.00309879
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.57988
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.885302
+x1.3-stage_cs-vco_dp9_0/ng3 -1.14852e-06
+x1.x3-stage_cs-vco_dp9_0.ng0 -8.71187e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -3.77715e-08
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 -1.21395e-06
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -8.82755e-08
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 -1.49854e-06
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -9.73077e-08
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.10532e-07
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.885246
+x1.x3-stage_cs-vco_dp9_0.net5 1.79935
+x1.x3-stage_cs-vco_dp9_0.net2 1.59085
+x1.x3-stage_cs-vco_dp9_0.net4 0.531412
+x1.x3-stage_cs-vco_dp9_0.pg3 1.57988
+x1.x3-stage_cs-vco_dp9_0.pg0 1.57988
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -1.55882e-07
+x1.x3-stage_cs-vco_dp9_0.pg1 1.57988
+x1.x3-stage_cs-vco_dp9_0.pg2 1.57988
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -1.63701e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -1.12694e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -2.16435e-07
+x1.fd_v2_1/4 0.0200328
+x1.fd_v2_1/3 -0.00970607
+x1.fd_v2_1/6 0.295731
+x1.fd_v2_1/clkb -0.00853624
+x1.fd_v2_1/5 1.82503
+x1.fd_v2_1/2 1.79798
+x1.fd_v2_2/clk_in -8.87493e-05
+x1.fd_v2_1/7 1.79995
+x1.fd_v2_2/4 0.0755122
+x1.fd_v2_2/3 1.79997
+x1.fd_v2_2/6 1.79996
+x1.fd_v2_2/clkb 1.79987
+x1.fd_v2_2/5 1.79999
+x1.fd_v2_2/2 1.99606e-05
+x1.fd_v2_2/7 3.06187e-05
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 2.12695e-07
+buf2a_out 3.75336e-07
+buf4a_out 3.63569e-07
+buf8a_out 5.38495e-07
+pad_out_a 3.12233e-06
+buf1b_out -1.94724e-06
+buf2b_out 3.89029e-05
+buf4b_out -4.38834e-05
+buf8b_out 4.89518e-05
+pad_out_b -0.000160528
+v1#branch -7.49917e-10
+vsel3#branch 2.36773e-09
+vsel2#branch 1.69142e-09
+vsel1#branch 1.24083e-09
+vsel0#branch 7.1634e-10
+vmeas_current_gnd#branch 1.09472e-05
+vmeas_current_vdd#branch 2.65932e-05
+v2#branch -2.60565e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.527204e-10 targ= 1.516001e-08 trig= 1.490729e-08
+fvco_outside_while = 3.95694e+09
+tdiv128_outside_while= 4.867936e-08 targ= 6.043003e-08 trig= 1.175067e-08
+fdiv128_outside_while= 2.05426e+07
+supply_current_rms_outside_while= 2.00203e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.79084e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.800085e+00 at= 1.532500e-08
+vlow_outside_while = -1.657979e-02 at= 1.165500e-08
+peak_to_peak_outside_while= 1.81667e+00
+supply_current_rms = 1.98569e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 1.79999
+x1.fd_v2_3/clk_in 1.79999
+x1.fd_v2_3/3 1.79999
+x1.fd_v2_3/6 1.32618
+x1.fd_v2_3/clkb -1.6935e-05
+x1.fd_v2_3/5 -8.75197e-05
+net1 1.8
+x1.fd_v2_3/2 0.00127916
+x1.fd_v2_4/clk_in 1.8
+x1.fd_v2_3/7 0.00128433
+x1.fd_v2_4/4 0.000557742
+x1.fd_v2_4/3 0.00055798
+x1.fd_v2_4/6 0.83542
+x1.fd_v2_4/clkb 5.27838e-07
+x1.fd_v2_4/5 1.8
+x1.fd_v2_4/2 1.37878
+x1.fd_v2_5/clk_in 0.000558381
+x1.fd_v2_4/7 1.37878
+x1.fd_v2_5/4 0.837358
+x1.fd_v2_5/3 1.8
+x1.fd_v2_5/6 1.35609
+x1.fd_v2_5/clkb 1.8
+x1.fd_v2_5/5 1.35609
+x1.fd_v2_5/2 0.000803825
+x1.fd_v2_6/clk_in 1.80002
+x1.fd_v2_5/7 0.000805604
+x1.fd_v2_6/4 -2.66113e-05
+x1.fd_v2_6/3 -2.68612e-05
+x1.fd_v2_6/6 0.722901
+x1.fd_v2_6/clkb 3.62476e-07
+x1.fd_v2_6/5 1.79995
+x1.fd_v2_6/2 1.76471
+out_div128_buf 1.39707e-06
+x1.fd_v2_6/7 1.76463
+x1.fd_v2_7/4 1.79458
+x1.fd_v2_7/3 2.04891e-06
+x1.fd_v2_7/6 2.92659e-06
+x1.fd_v2_7/clkb 1.8
+x1.fd_v2_7/5 -3.87318e-06
+x1.fd_v2_7/2 1.8
+out_div256_buf 1.49349e-07
+x1.fd_v2_7/7 1.8
+x1.fd_v2_8/4 1.781
+x1.fd_v2_8/3 -5.55739e-07
+x1.fd_v2_8/6 1.04314e-05
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 -3.17817e-05
+x1.fd_v2_8/2 1.8
+x1.fd_v2_9/clk_in 1.12744e-06
+x1.fd_v2_8/7 1.8
+x1.fd_v2_9/4 0.0683538
+x1.fd_v2_9/3 1.8
+x1.fd_v2_9/6 1.8
+x1.fd_v2_9/clkb 1.8
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 9.79813e-07
+x1.fd_v2_9/clk_out 1.8
+x1.fd_v2_9/7 9.80637e-07
+x1.fd_v5_lasttry_0/4 0.34441
+x1.fd_v5_lasttry_0/5 1.78753
+x1.fd_v5_lasttry_0/2 -0.0213527
+x1.fd_v5_lasttry_0/3 1.781
+x1.fd_v5_lasttry_0/clkb_buf 1.79198
+x1.fd_v5_lasttry_0/clk_in_buf -0.00718786
+x1.fd_v5_lasttry_0/clkb_int 1.79818
+x1.fd_v5_lasttry_0/dus -0.0038805
+x1.fd_v5_lasttry_0/6 1.79645
+x1.fd_v5_lasttry_0/7 -0.0182771
+x1.fd_v2_1/clk_in 1.784
+x1.out -0.013312
+x1.3-stage_cs-vco_dp9_0/net7 1.79775
+x1.x3-stage_cs-vco_dp9_0.net6 0.00309879
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.57988
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.885302
+x1.3-stage_cs-vco_dp9_0/ng3 -1.14852e-06
+x1.x3-stage_cs-vco_dp9_0.ng0 -8.71187e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -3.77715e-08
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 -1.21395e-06
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -8.82755e-08
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 -1.49854e-06
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -9.73077e-08
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.10532e-07
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.885246
+x1.x3-stage_cs-vco_dp9_0.net5 1.79935
+x1.x3-stage_cs-vco_dp9_0.net2 1.59085
+x1.x3-stage_cs-vco_dp9_0.net4 0.531412
+x1.x3-stage_cs-vco_dp9_0.pg3 1.57988
+x1.x3-stage_cs-vco_dp9_0.pg0 1.57988
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -1.55882e-07
+x1.x3-stage_cs-vco_dp9_0.pg1 1.57988
+x1.x3-stage_cs-vco_dp9_0.pg2 1.57988
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -1.63701e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -1.12694e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -2.16435e-07
+x1.fd_v2_1/4 0.0200328
+x1.fd_v2_1/3 -0.00970607
+x1.fd_v2_1/6 0.295731
+x1.fd_v2_1/clkb -0.00853624
+x1.fd_v2_1/5 1.82503
+x1.fd_v2_1/2 1.79798
+x1.fd_v2_2/clk_in -8.87493e-05
+x1.fd_v2_1/7 1.79995
+x1.fd_v2_2/4 0.0755122
+x1.fd_v2_2/3 1.79997
+x1.fd_v2_2/6 1.79996
+x1.fd_v2_2/clkb 1.79987
+x1.fd_v2_2/5 1.79999
+x1.fd_v2_2/2 1.99606e-05
+x1.fd_v2_2/7 3.06187e-05
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 2.12695e-07
+buf2a_out 3.75336e-07
+buf4a_out 3.63569e-07
+buf8a_out 5.38495e-07
+pad_out_a 3.12233e-06
+buf1b_out -1.94724e-06
+buf2b_out 3.89029e-05
+buf4b_out -4.38834e-05
+buf8b_out 4.89518e-05
+pad_out_b -0.000160528
+v1#branch -7.49917e-10
+vsel3#branch 2.36773e-09
+vsel2#branch 1.69142e-09
+vsel1#branch 1.24083e-09
+vsel0#branch 7.1634e-10
+vmeas_current_gnd#branch 1.09472e-05
+vmeas_current_vdd#branch 2.65932e-05
+v2#branch -2.60565e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.451227e-10 targ= 1.462702e-08 trig= 1.438190e-08
+fvco_outside_while = 4.07959e+09
+tdiv128_outside_while= 4.714192e-08 targ= 5.853388e-08 trig= 1.139196e-08
+fdiv128_outside_while= 2.12125e+07
+supply_current_rms_outside_while= 2.13232e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.26634e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.800085e+00 at= 1.920500e-08
+vlow_outside_while = -1.657836e-02 at= 1.130500e-08
+peak_to_peak_outside_while= 1.81666e+00
+supply_current_rms = 2.11653e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net3 and x1.3-stage_cs-vco_dp9_0/net3
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 1.79999
+x1.fd_v2_3/clk_in 1.79999
+x1.fd_v2_3/3 1.79999
+x1.fd_v2_3/6 1.32618
+x1.fd_v2_3/clkb -1.6935e-05
+x1.fd_v2_3/5 -8.75197e-05
+net1 1.8
+x1.fd_v2_3/2 0.00127916
+x1.fd_v2_4/clk_in 1.8
+x1.fd_v2_3/7 0.00128433
+x1.fd_v2_4/4 0.000557742
+x1.fd_v2_4/3 0.00055798
+x1.fd_v2_4/6 0.83542
+x1.fd_v2_4/clkb 5.27838e-07
+x1.fd_v2_4/5 1.8
+x1.fd_v2_4/2 1.37878
+x1.fd_v2_5/clk_in 0.000558381
+x1.fd_v2_4/7 1.37878
+x1.fd_v2_5/4 0.837358
+x1.fd_v2_5/3 1.8
+x1.fd_v2_5/6 1.35609
+x1.fd_v2_5/clkb 1.8
+x1.fd_v2_5/5 1.35609
+x1.fd_v2_5/2 0.000803825
+x1.fd_v2_6/clk_in 1.80002
+x1.fd_v2_5/7 0.000805604
+x1.fd_v2_6/4 -2.66113e-05
+x1.fd_v2_6/3 -2.68612e-05
+x1.fd_v2_6/6 0.722901
+x1.fd_v2_6/clkb 3.62476e-07
+x1.fd_v2_6/5 1.79995
+x1.fd_v2_6/2 1.76471
+out_div128_buf 1.39707e-06
+x1.fd_v2_6/7 1.76463
+x1.fd_v2_7/4 1.79458
+x1.fd_v2_7/3 2.04891e-06
+x1.fd_v2_7/6 2.92659e-06
+x1.fd_v2_7/clkb 1.8
+x1.fd_v2_7/5 -3.87318e-06
+x1.fd_v2_7/2 1.8
+out_div256_buf 1.49349e-07
+x1.fd_v2_7/7 1.8
+x1.fd_v2_8/4 1.781
+x1.fd_v2_8/3 -5.55739e-07
+x1.fd_v2_8/6 1.04314e-05
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 -3.17817e-05
+x1.fd_v2_8/2 1.8
+x1.fd_v2_9/clk_in 1.12744e-06
+x1.fd_v2_8/7 1.8
+x1.fd_v2_9/4 0.0683538
+x1.fd_v2_9/3 1.8
+x1.fd_v2_9/6 1.8
+x1.fd_v2_9/clkb 1.8
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 9.79813e-07
+x1.fd_v2_9/clk_out 1.8
+x1.fd_v2_9/7 9.80637e-07
+x1.fd_v5_lasttry_0/4 0.34441
+x1.fd_v5_lasttry_0/5 1.78753
+x1.fd_v5_lasttry_0/2 -0.0213527
+x1.fd_v5_lasttry_0/3 1.781
+x1.fd_v5_lasttry_0/clkb_buf 1.79198
+x1.fd_v5_lasttry_0/clk_in_buf -0.00718786
+x1.fd_v5_lasttry_0/clkb_int 1.79818
+x1.fd_v5_lasttry_0/dus -0.0038805
+x1.fd_v5_lasttry_0/6 1.79645
+x1.fd_v5_lasttry_0/7 -0.0182771
+x1.fd_v2_1/clk_in 1.784
+x1.out -0.013312
+x1.3-stage_cs-vco_dp9_0/net7 1.79775
+x1.x3-stage_cs-vco_dp9_0.net6 0.00309879
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.57988
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.885302
+x1.3-stage_cs-vco_dp9_0/ng3 -1.14852e-06
+x1.x3-stage_cs-vco_dp9_0.ng0 -8.71187e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -3.77715e-08
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 -1.21395e-06
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -8.82755e-08
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 -1.49854e-06
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -9.73077e-08
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.10532e-07
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.885246
+x1.x3-stage_cs-vco_dp9_0.net5 1.79935
+x1.x3-stage_cs-vco_dp9_0.net2 1.59085
+x1.x3-stage_cs-vco_dp9_0.net4 0.531412
+x1.x3-stage_cs-vco_dp9_0.pg3 1.57988
+x1.x3-stage_cs-vco_dp9_0.pg0 1.57988
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -1.55882e-07
+x1.x3-stage_cs-vco_dp9_0.pg1 1.57988
+x1.x3-stage_cs-vco_dp9_0.pg2 1.57988
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -1.63701e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -1.12694e-07
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -2.16435e-07
+x1.fd_v2_1/4 0.0200328
+x1.fd_v2_1/3 -0.00970607
+x1.fd_v2_1/6 0.295731
+x1.fd_v2_1/clkb -0.00853624
+x1.fd_v2_1/5 1.82503
+x1.fd_v2_1/2 1.79798
+x1.fd_v2_2/clk_in -8.87493e-05
+x1.fd_v2_1/7 1.79995
+x1.fd_v2_2/4 0.0755122
+x1.fd_v2_2/3 1.79997
+x1.fd_v2_2/6 1.79996
+x1.fd_v2_2/clkb 1.79987
+x1.fd_v2_2/5 1.79999
+x1.fd_v2_2/2 1.99606e-05
+x1.fd_v2_2/7 3.06187e-05
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 2.12695e-07
+buf2a_out 3.75336e-07
+buf4a_out 3.63569e-07
+buf8a_out 5.38495e-07
+pad_out_a 3.12233e-06
+buf1b_out -1.94724e-06
+buf2b_out 3.89029e-05
+buf4b_out -4.38834e-05
+buf8b_out 4.89518e-05
+pad_out_b -0.000160528
+v1#branch -7.49917e-10
+vsel3#branch 2.36773e-09
+vsel2#branch 1.69142e-09
+vsel1#branch 1.24083e-09
+vsel0#branch 7.1634e-10
+vmeas_current_gnd#branch 1.09472e-05
+vmeas_current_vdd#branch 2.65932e-05
+v2#branch -2.60565e-05
+
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_26QSQN.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_26QSQN.ext
new file mode 100755
index 0000000..282674a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_26QSQN.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n209#" 1169 17.4716 18 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n209#" 1169 17.4716 -76 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n297#" 823 148.863 -33 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23364 1320 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n297#" "a_n76_n209#" 3.69031
+cap "a_n33_n297#" "a_18_n209#" 4.24313
+cap "a_18_n209#" "a_n76_n209#" 349.025
+device msubckt sky130_fd_pr__nfet_01v8 -18 -209 -17 -208 l=36 w=480 "VSUBS" "a_n33_n297#" 72 0 "a_n76_n209#" 480 0 "a_18_n209#" 480 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_26QSQN.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_26QSQN.mag
new file mode 100755
index 0000000..d09d413
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_26QSQN.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -209 -18 271
+rect 18 -209 76 271
+rect -29 -247 29 -241
+rect -29 -281 -17 -247
+rect -29 -287 29 -281
+<< nmos >>
+rect -18 -209 18 271
+<< ndiff >>
+rect -76 259 -18 271
+rect -76 -197 -64 259
+rect -30 -197 -18 259
+rect -76 -209 -18 -197
+rect 18 259 76 271
+rect 18 -197 30 259
+rect 64 -197 76 259
+rect 18 -209 76 -197
+<< ndiffc >>
+rect -64 -197 -30 259
+rect 30 -197 64 259
+<< poly >>
+rect -18 271 18 297
+rect -18 -231 18 -209
+rect -33 -247 33 -231
+rect -33 -281 -17 -247
+rect 17 -281 33 -247
+rect -33 -297 33 -281
+<< polycont >>
+rect -17 -281 17 -247
+<< locali >>
+rect -64 259 -30 275
+rect -64 -213 -30 -197
+rect 30 259 64 275
+rect 30 -213 64 -197
+rect -33 -281 -17 -247
+rect 17 -281 33 -247
+<< viali >>
+rect -64 60 -30 242
+rect 30 -60 64 122
+rect -17 -281 17 -247
+<< metal1 >>
+rect -70 242 -24 254
+rect -70 60 -64 242
+rect -30 60 -24 242
+rect -70 48 -24 60
+rect 24 122 70 134
+rect 24 -60 30 122
+rect 64 -60 70 122
+rect 24 -72 70 -60
+rect -29 -247 29 -241
+rect -29 -281 -17 -247
+rect 17 -281 29 -247
+rect -29 -287 29 -281
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2.4 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_44BYND.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_44BYND.ext
new file mode 100755
index 0000000..4644ebb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_44BYND.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n120#" 582 8.7358 15 -120 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8092 544 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n120#" 586 19.9316 -73 -120 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 10166 534 0 0 0 0 0 0 0 0 0 0
+node "a_n33_142#" 577 144.799 -33 142 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12996 840 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_142#" "a_n73_n120#" 5.82353
+cap "a_n33_142#" "a_15_n120#" 4.5
+cap "a_15_n120#" "a_n73_n120#" 145.444
+device msubckt sky130_fd_pr__nfet_01v8 -15 -120 -14 -119 l=30 w=240 "VSUBS" "a_n33_142#" 60 0 "a_n73_n120#" 240 0 "a_15_n120#" 240 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_44BYND.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_44BYND.mag
new file mode 100755
index 0000000..6b61ffa
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_44BYND.mag
@@ -0,0 +1,49 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -120 -15 120
+rect 15 -120 73 120
+<< nmos >>
+rect -15 -120 15 120
+<< ndiff >>
+rect -73 108 -15 120
+rect -73 -108 -61 108
+rect -27 -108 -15 108
+rect -73 -120 -15 -108
+rect 15 98 73 120
+rect 15 -107 27 98
+rect 61 -107 73 98
+rect 15 -120 73 -107
+<< ndiffc >>
+rect -61 -108 -27 108
+rect 27 -107 61 98
+<< poly >>
+rect -33 192 33 208
+rect -33 158 -17 192
+rect 17 158 33 192
+rect -33 142 33 158
+rect -15 120 15 142
+rect -15 -146 15 -120
+<< polycont >>
+rect -17 158 17 192
+<< locali >>
+rect -33 158 -17 192
+rect 17 158 33 192
+rect -61 108 -27 124
+rect -61 -124 -27 -108
+rect 27 98 61 114
+rect 27 -124 61 -107
+<< viali >>
+rect -61 -89 -27 108
+<< metal1 >>
+rect -67 108 -21 120
+rect -67 -89 -61 108
+rect -27 -89 -21 108
+rect -67 -101 -21 -89
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1.2 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_4BNSKG.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_4BNSKG.mag
new file mode 100755
index 0000000..4950ae9
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_4BNSKG.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646335097
+<< error_p >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect -29 74 29 80
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect -29 -120 29 -114
+<< pwell >>
+rect -214 -252 214 252
+<< nmos >>
+rect -18 -42 18 42
+<< ndiff >>
+rect -76 30 -18 42
+rect -76 -30 -64 30
+rect -30 -30 -18 30
+rect -76 -42 -18 -30
+rect 18 30 76 42
+rect 18 -30 30 30
+rect 64 -30 76 30
+rect 18 -42 76 -30
+<< ndiffc >>
+rect -64 -30 -30 30
+rect 30 -30 64 30
+<< psubdiff >>
+rect -178 182 -82 216
+rect 82 182 178 216
+rect -178 120 -144 182
+rect 144 120 178 182
+rect -178 -182 -144 -120
+rect 144 -182 178 -120
+rect -178 -216 -82 -182
+rect 82 -216 178 -182
+<< psubdiffcont >>
+rect -82 182 82 216
+rect -178 -120 -144 120
+rect 144 -120 178 120
+rect -82 -216 82 -182
+<< poly >>
+rect -33 114 33 130
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -33 64 33 80
+rect -18 42 18 64
+rect -18 -64 18 -42
+rect -33 -80 33 -64
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -33 -130 33 -114
+<< polycont >>
+rect -17 80 17 114
+rect -17 -114 17 -80
+<< locali >>
+rect -178 182 -82 216
+rect 82 182 178 216
+rect -178 120 -144 182
+rect 144 120 178 182
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -64 30 -30 46
+rect -64 -46 -30 -30
+rect 30 30 64 46
+rect 30 -46 64 -30
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -178 -182 -144 -120
+rect 144 -182 178 -120
+rect -178 -216 -82 -182
+rect 82 -216 178 -182
+<< viali >>
+rect -17 80 17 114
+rect -64 -30 -30 30
+rect 30 -30 64 30
+rect -17 -114 17 -80
+<< metal1 >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect 17 80 29 114
+rect -29 74 29 80
+rect -70 30 -24 42
+rect -70 -30 -64 30
+rect -30 -30 -24 30
+rect -70 -42 -24 -30
+rect 24 30 70 42
+rect 24 -30 30 30
+rect 64 -30 70 30
+rect 24 -42 70 -30
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect 17 -114 29 -80
+rect -29 -120 29 -114
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -161 -199 161 199
+string parameters w 0.42 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_86PVFD.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_86PVFD.ext
new file mode 100755
index 0000000..130d530
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_86PVFD.ext
@@ -0,0 +1,15 @@
+timestamp 1645123349
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n120#" 586 198.668 15 -120 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n120#" 586 196.646 -73 -120 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n208#" 734 512.486 -33 -208 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17232 1036 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+substrate "w_n211_n330#" 0 0 -211 -330 pw 278520 2164 0 0 0 0 0 0 0 0 59160 3480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59160 3480 11500 592 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n208#" "a_n73_n120#" 21.4768
+cap "a_n33_n208#" "a_15_n120#" 19.0697
+cap "a_n73_n120#" "a_15_n120#" 217.984
+device msubckt sky130_fd_pr__nfet_01v8 -15 -120 -14 -119 l=30 w=240 "w_n211_n330#" "a_n33_n208#" 60 0 "a_n73_n120#" 240 0 "a_15_n120#" 240 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_86PVFD.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_86PVFD.mag
new file mode 100755
index 0000000..a61d8c3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_86PVFD.mag
@@ -0,0 +1,104 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645123349
+<< error_p >>
+rect -29 192 29 198
+rect -29 158 -17 192
+rect -29 152 29 158
+rect -29 -158 29 -152
+rect -29 -192 -17 -158
+rect -29 -198 29 -192
+<< pwell >>
+rect -211 -330 211 330
+<< nmos >>
+rect -15 -120 15 120
+<< ndiff >>
+rect -73 108 -15 120
+rect -73 -108 -61 108
+rect -27 -108 -15 108
+rect -73 -120 -15 -108
+rect 15 108 73 120
+rect 15 -108 27 108
+rect 61 -108 73 108
+rect 15 -120 73 -108
+<< ndiffc >>
+rect -61 -108 -27 108
+rect 27 -108 61 108
+<< psubdiff >>
+rect -175 260 -79 294
+rect 79 260 175 294
+rect -175 198 -141 260
+rect -175 -260 -141 -198
+rect 141 -260 175 260
+rect -175 -294 -79 -260
+rect 79 -294 175 -260
+<< psubdiffcont >>
+rect -79 260 79 294
+rect -175 -198 -141 198
+rect -79 -294 79 -260
+<< poly >>
+rect -33 192 33 208
+rect -33 158 -17 192
+rect 17 158 33 192
+rect -33 142 33 158
+rect -15 120 15 142
+rect -15 -142 15 -120
+rect -33 -158 33 -142
+rect -33 -192 -17 -158
+rect 17 -192 33 -158
+rect -33 -208 33 -192
+<< polycont >>
+rect -17 158 17 192
+rect -17 -192 17 -158
+<< locali >>
+rect -175 260 -79 294
+rect 79 260 175 294
+rect -175 198 -141 260
+rect -33 158 -17 192
+rect 17 158 33 192
+rect -61 108 -27 124
+rect -61 -124 -27 -108
+rect 27 108 61 124
+rect 27 -124 61 -108
+rect -33 -192 -17 -158
+rect 17 -192 33 -158
+rect -175 -260 -141 -198
+rect 141 -260 175 260
+rect -175 -294 -113 -260
+rect 113 -294 175 -260
+<< viali >>
+rect -17 158 17 192
+rect -61 5 -27 91
+rect 27 -43 61 43
+rect -17 -192 17 -158
+rect -113 -294 -79 -260
+rect -79 -294 79 -260
+rect 79 -294 113 -260
+<< metal1 >>
+rect -29 192 29 198
+rect -29 158 -17 192
+rect 17 158 29 192
+rect -29 152 29 158
+rect -67 91 -21 103
+rect -67 5 -61 91
+rect -27 5 -21 91
+rect -67 -7 -21 5
+rect 21 43 67 55
+rect 21 -43 27 43
+rect 61 -43 67 43
+rect 21 -55 67 -43
+rect -29 -158 29 -152
+rect -29 -192 -17 -158
+rect 17 -192 29 -158
+rect -29 -198 29 -192
+rect -125 -260 125 -254
+rect -125 -294 -113 -260
+rect 113 -294 125 -260
+rect -125 -300 125 -294
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -277 158 277
+string parameters w 1.2 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_8T82FM.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_8T82FM.ext
new file mode 100755
index 0000000..a852a1d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_8T82FM.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n175#" 702 17.4716 15 -175 ndif 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n175#" 702 17.4716 -73 -175 ndif 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_135#" 655 144.799 -33 135 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14436 936 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_135#" "a_n73_n175#" 1.94118
+cap "a_n33_135#" "a_15_n175#" 1.94118
+cap "a_15_n175#" "a_n73_n175#" 157.548
+device msubckt sky130_fd_pr__nfet_01v8 -15 -175 -14 -174 l=30 w=288 "VSUBS" "a_n33_135#" 60 0 "a_n73_n175#" 288 0 "a_15_n175#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_8T82FM.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_8T82FM.mag
new file mode 100755
index 0000000..4e011ce
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_8T82FM.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -175 -15 113
+rect 15 -175 73 113
+<< nmos >>
+rect -15 -175 15 113
+<< ndiff >>
+rect -73 101 -15 113
+rect -73 -163 -65 101
+rect -31 -163 -15 101
+rect -73 -175 -15 -163
+rect 15 101 73 113
+rect 15 -163 31 101
+rect 65 -163 73 101
+rect 15 -175 73 -163
+<< ndiffc >>
+rect -65 -163 -31 101
+rect 31 -163 65 101
+<< poly >>
+rect -33 185 33 201
+rect -33 151 -17 185
+rect 17 151 33 185
+rect -33 135 33 151
+rect -15 113 15 135
+rect -15 -201 15 -175
+<< polycont >>
+rect -17 151 17 185
+<< locali >>
+rect -33 151 -17 185
+rect 17 151 33 185
+rect -65 101 -31 117
+rect -65 -179 -31 -163
+rect 31 101 65 117
+rect 31 -179 65 -163
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1.44 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_ALRCN6.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_ALRCN6.ext
new file mode 100755
index 0000000..9a0e4ab
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_ALRCN6.ext
@@ -0,0 +1,15 @@
+timestamp 1645180687
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n73#" 207 3.5316 15 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n73#" 207 3.5316 -73 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 324 114.359 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8316 528 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_33#" "a_n73_n73#" 13.8235
+cap "a_n73_n73#" "a_15_n73#" 114.079
+cap "a_n33_33#" "a_15_n73#" 13.1705
+device msubckt sky130_fd_pr__nfet_01v8 -15 -73 -14 -72 l=30 w=84 "VSUBS" "a_n33_33#" 60 0 "a_n73_n73#" 84 0 "a_15_n73#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_ALRCN6.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_ALRCN6.mag
new file mode 100755
index 0000000..d003c13
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_ALRCN6.mag
@@ -0,0 +1,87 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645271067
+<< error_p >>
+rect -29 77 29 83
+rect -29 43 -17 77
+rect -29 37 29 43
+rect -61 9 -45 15
+rect -43 9 -27 15
+rect -15 5 15 17
+rect 27 9 43 15
+rect 45 9 61 15
+rect -77 -14 -11 -1
+rect -77 -17 -61 -14
+rect -27 -17 -11 -14
+rect 11 -3 77 -1
+rect 11 -6 27 -3
+rect 61 -6 77 -3
+rect 11 -17 77 -6
+rect -67 -45 -61 -17
+rect 21 -18 67 -17
+rect 21 -45 27 -18
+rect -77 -48 -61 -45
+rect -27 -48 -11 -45
+rect -77 -61 -11 -48
+rect 11 -52 27 -45
+rect 61 -52 77 -45
+rect 11 -61 77 -52
+rect 21 -64 67 -61
+rect -61 -77 -45 -71
+rect -43 -77 -27 -71
+rect -15 -79 15 -67
+rect 27 -77 43 -71
+rect 45 -77 61 -71
+<< nmos >>
+rect -15 -67 15 5
+<< ndiff >>
+rect -73 -1 -15 5
+rect -73 -61 -61 -1
+rect -27 -61 -15 -1
+rect -73 -67 -15 -61
+rect 15 -1 73 5
+rect 15 -61 27 -1
+rect 61 -61 73 -1
+rect 15 -67 73 -61
+<< ndiffc >>
+rect -61 -61 -27 -1
+rect 27 -61 61 -1
+<< poly >>
+rect -33 77 33 93
+rect -33 43 -17 77
+rect 17 43 33 77
+rect -33 27 33 43
+rect -15 5 15 27
+rect -15 -93 15 -67
+<< polycont >>
+rect -17 43 17 77
+<< locali >>
+rect -33 43 -17 77
+rect 17 43 33 77
+rect -61 -1 -27 9
+rect -61 -71 -27 -61
+rect 27 -1 61 9
+rect 27 -71 61 -61
+<< viali >>
+rect -17 43 17 77
+rect -61 -48 -27 -14
+rect 27 -52 61 -18
+<< metal1 >>
+rect -29 77 29 83
+rect -29 43 -17 77
+rect 17 43 29 77
+rect -29 37 29 43
+rect -67 -14 -21 -2
+rect -67 -48 -61 -14
+rect -27 -48 -21 -14
+rect -67 -60 -21 -48
+rect 21 -18 67 -6
+rect 21 -52 27 -18
+rect 61 -52 67 -18
+rect 21 -64 67 -52
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_B87NCT.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_B87NCT.ext
new file mode 100755
index 0000000..e3c4705
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_B87NCT.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n69#" 489 17.4716 18 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n69#" 489 17.4716 -76 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n157#" 446 148.863 -33 -157 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13284 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n157#" "a_n76_n69#" 4.77127
+cap "a_n33_n157#" "a_18_n69#" 5.55882
+cap "a_18_n69#" "a_n76_n69#" 168.775
+device msubckt sky130_fd_pr__nfet_01v8 -18 -69 -17 -68 l=36 w=200 "VSUBS" "a_n33_n157#" 72 0 "a_n76_n69#" 200 0 "a_18_n69#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_B87NCT.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_B87NCT.mag
new file mode 100755
index 0000000..2851c9c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_B87NCT.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -69 -18 131
+rect 18 -69 76 131
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect -29 -147 29 -141
+<< nmos >>
+rect -18 -69 18 131
+<< ndiff >>
+rect -76 119 -18 131
+rect -76 -57 -64 119
+rect -30 -57 -18 119
+rect -76 -69 -18 -57
+rect 18 119 76 131
+rect 18 -57 30 119
+rect 64 -57 76 119
+rect 18 -69 76 -57
+<< ndiffc >>
+rect -64 -57 -30 119
+rect 30 -57 64 119
+<< poly >>
+rect -18 131 18 157
+rect -18 -91 18 -69
+rect -33 -107 33 -91
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+rect -33 -157 33 -141
+<< polycont >>
+rect -17 -141 17 -107
+<< locali >>
+rect -64 119 -30 135
+rect -64 -73 -30 -57
+rect 30 119 64 135
+rect 30 -73 64 -57
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+<< viali >>
+rect -64 32 -30 102
+rect 30 -4 64 66
+rect -17 -141 17 -107
+<< metal1 >>
+rect -70 102 -24 114
+rect -70 32 -64 102
+rect -30 32 -24 102
+rect -70 20 -24 32
+rect 24 66 70 78
+rect 24 -4 30 66
+rect 64 -4 70 66
+rect 24 -16 70 -4
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect 17 -141 29 -107
+rect -29 -147 29 -141
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_CJ56PH.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_CJ56PH.ext
new file mode 100755
index 0000000..27ed8c4
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_CJ56PH.ext
@@ -0,0 +1,15 @@
+timestamp 1645532764
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n100#" 489 3.5316 18 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n100#" 489 3.5316 -76 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n188#" 596 176.884 -33 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17496 944 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n100#" "a_n76_n100#" 168.775
+cap "a_n33_n188#" "a_n76_n100#" 12.2749
+cap "a_n33_n188#" "a_18_n100#" 11.1176
+device msubckt sky130_fd_pr__nfet_01v8 -18 -100 -17 -99 l=36 w=200 "VSUBS" "a_n33_n188#" 72 0 "a_n76_n100#" 200 0 "a_18_n100#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_CJ56PH.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_CJ56PH.mag
new file mode 100755
index 0000000..06915e5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_CJ56PH.mag
@@ -0,0 +1,75 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645532764
+<< error_p >>
+rect -29 172 29 178
+rect -29 138 -17 172
+rect -29 132 29 138
+rect -29 -138 29 -132
+rect -29 -172 -17 -138
+rect -29 -178 29 -172
+<< nmos >>
+rect -18 -100 18 100
+<< ndiff >>
+rect -76 88 -18 100
+rect -76 -88 -64 88
+rect -30 -88 -18 88
+rect -76 -100 -18 -88
+rect 18 88 76 100
+rect 18 -88 30 88
+rect 64 -88 76 88
+rect 18 -100 76 -88
+<< ndiffc >>
+rect -64 -88 -30 88
+rect 30 -88 64 88
+<< poly >>
+rect -33 172 33 188
+rect -33 138 -17 172
+rect 17 138 33 172
+rect -33 122 33 138
+rect -18 100 18 122
+rect -18 -122 18 -100
+rect -33 -138 33 -122
+rect -33 -172 -17 -138
+rect 17 -172 33 -138
+rect -33 -188 33 -172
+<< polycont >>
+rect -17 138 17 172
+rect -17 -172 17 -138
+<< locali >>
+rect -33 138 -17 172
+rect 17 138 33 172
+rect -64 88 -30 104
+rect -64 -104 -30 -88
+rect 30 88 64 104
+rect 30 -104 64 -88
+rect -33 -172 -17 -138
+rect 17 -172 33 -138
+<< viali >>
+rect -17 138 17 172
+rect -64 1 -30 71
+rect 30 -35 64 35
+rect -17 -172 17 -138
+<< metal1 >>
+rect -29 172 29 178
+rect -29 138 -17 172
+rect 17 138 29 172
+rect -29 132 29 138
+rect -70 71 -24 83
+rect -70 1 -64 71
+rect -30 1 -24 71
+rect -70 -11 -24 1
+rect 24 35 70 47
+rect 24 -35 30 35
+rect 64 -35 70 35
+rect 24 -47 70 -35
+rect -29 -138 29 -132
+rect -29 -172 -17 -138
+rect 17 -172 29 -138
+rect -29 -178 29 -172
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 1 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_D7TJRJ.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_D7TJRJ.ext
new file mode 100755
index 0000000..71c1f7a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_D7TJRJ.ext
@@ -0,0 +1,15 @@
+timestamp 1645134235
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n42#" 207 107.749 15 -42 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n42#" 207 107.355 -73 -42 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n130#" 484 539.552 -33 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12552 724 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+substrate "w_n211_n252#" 0 0 -211 -252 pw 212688 1852 0 0 0 0 0 0 0 0 48552 2856 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48552 2856 11500 592 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n130#" "a_15_n42#" 27.7745
+cap "a_n33_n130#" "a_n73_n42#" 27.6471
+cap "a_15_n42#" "a_n73_n42#" 114.079
+device msubckt sky130_fd_pr__nfet_01v8 -15 -42 -14 -41 l=30 w=84 "w_n211_n252#" "a_n33_n130#" 60 0 "a_n73_n42#" 84 0 "a_15_n42#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_D7TJRJ.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_D7TJRJ.mag
new file mode 100755
index 0000000..0ab112d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_D7TJRJ.mag
@@ -0,0 +1,110 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645134235
+<< error_p >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect -29 74 29 80
+rect -67 17 -21 29
+rect -67 -17 -61 17
+rect 21 13 67 25
+rect -67 -29 -21 -17
+rect 21 -21 27 13
+rect 21 -33 67 -21
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect -29 -120 29 -114
+<< pwell >>
+rect -211 -252 211 252
+<< nmos >>
+rect -15 -42 15 42
+<< ndiff >>
+rect -73 30 -15 42
+rect -73 -30 -61 30
+rect -27 -30 -15 30
+rect -73 -42 -15 -30
+rect 15 30 73 42
+rect 15 -30 27 30
+rect 61 -30 73 30
+rect 15 -42 73 -30
+<< ndiffc >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< psubdiff >>
+rect -175 182 -79 216
+rect 79 182 175 216
+rect -175 120 -141 182
+rect -175 -182 -141 -120
+rect 141 -182 175 182
+rect -175 -216 -79 -182
+rect 79 -216 175 -182
+<< psubdiffcont >>
+rect -79 182 79 216
+rect -175 -120 -141 120
+rect -79 -216 79 -182
+<< poly >>
+rect -33 114 33 130
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -33 64 33 80
+rect -15 42 15 64
+rect -15 -64 15 -42
+rect -33 -80 33 -64
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -33 -130 33 -114
+<< polycont >>
+rect -17 80 17 114
+rect -17 -114 17 -80
+<< locali >>
+rect -175 182 -79 216
+rect 79 182 175 216
+rect -175 120 -141 182
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -61 30 -27 46
+rect -61 -46 -27 -30
+rect 27 30 61 46
+rect 27 -46 61 -30
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -175 -182 -141 -120
+rect 141 -182 175 182
+rect -175 -216 -113 -182
+rect 113 -216 175 -182
+<< viali >>
+rect -17 80 17 114
+rect -61 -17 -27 17
+rect 27 -21 61 13
+rect -17 -114 17 -80
+rect -113 -216 -79 -182
+rect -79 -216 79 -182
+rect 79 -216 113 -182
+<< metal1 >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect 17 80 29 114
+rect -29 74 29 80
+rect -67 17 -21 29
+rect -67 -17 -61 17
+rect -27 -17 -21 17
+rect -67 -29 -21 -17
+rect 21 13 67 25
+rect 21 -21 27 13
+rect 61 -21 67 13
+rect 21 -33 67 -21
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect 17 -114 29 -80
+rect -29 -120 29 -114
+rect -125 -182 125 -176
+rect -125 -216 -113 -182
+rect 113 -216 125 -182
+rect -125 -222 125 -216
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -199 158 199
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EDB9KC.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EDB9KC.mag
new file mode 100755
index 0000000..dbe6417
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EDB9KC.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647120585
+<< error_p >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect -29 74 29 80
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect -29 -120 29 -114
+<< pwell >>
+rect -211 -252 211 252
+<< nmos >>
+rect -15 -42 15 42
+<< ndiff >>
+rect -73 30 -15 42
+rect -73 -30 -61 30
+rect -27 -30 -15 30
+rect -73 -42 -15 -30
+rect 15 30 73 42
+rect 15 -30 27 30
+rect 61 -30 73 30
+rect 15 -42 73 -30
+<< ndiffc >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< psubdiff >>
+rect -175 182 -79 216
+rect 79 182 175 216
+rect -175 120 -141 182
+rect 141 120 175 182
+rect -175 -182 -141 -120
+rect 141 -182 175 -120
+rect -175 -216 -79 -182
+rect 79 -216 175 -182
+<< psubdiffcont >>
+rect -79 182 79 216
+rect -175 -120 -141 120
+rect 141 -120 175 120
+rect -79 -216 79 -182
+<< poly >>
+rect -33 114 33 130
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -33 64 33 80
+rect -15 42 15 64
+rect -15 -64 15 -42
+rect -33 -80 33 -64
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -33 -130 33 -114
+<< polycont >>
+rect -17 80 17 114
+rect -17 -114 17 -80
+<< locali >>
+rect -175 182 -79 216
+rect 79 182 175 216
+rect -175 120 -141 182
+rect 141 120 175 182
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -61 30 -27 46
+rect -61 -46 -27 -30
+rect 27 30 61 46
+rect 27 -46 61 -30
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -175 -182 -141 -120
+rect 141 -182 175 -120
+rect -175 -216 -79 -182
+rect 79 -216 175 -182
+<< viali >>
+rect -17 80 17 114
+rect -61 -30 -27 30
+rect 27 -30 61 30
+rect -17 -114 17 -80
+<< metal1 >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect 17 80 29 114
+rect -29 74 29 80
+rect -67 30 -21 42
+rect -67 -30 -61 30
+rect -27 -30 -21 30
+rect -67 -42 -21 -30
+rect 21 30 67 42
+rect 21 -30 27 30
+rect 61 -30 67 30
+rect 21 -42 67 -30
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect 17 -114 29 -80
+rect -29 -120 29 -114
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -199 158 199
+string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EMZ8SC.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EMZ8SC.ext
new file mode 100755
index 0000000..13c0219
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EMZ8SC.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n103#" 348 0 15 -103 ndif 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4760 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n103#" 348 0 -73 -103 ndif 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4760 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_63#" 422 144.799 -33 63 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10116 648 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_63#" "a_n73_n103#" 1.65
+cap "a_n33_63#" "a_15_n103#" 1.65
+cap "a_15_n103#" "a_n73_n103#" 74.5161
+device msubckt sky130_fd_pr__nfet_01v8 -15 -103 -14 -102 l=30 w=144 "VSUBS" "a_n33_63#" 60 0 "a_n73_n103#" 144 0 "a_15_n103#" 144 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EMZ8SC.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EMZ8SC.mag
new file mode 100755
index 0000000..2d4c77b
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EMZ8SC.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -103 -15 41
+rect 15 -103 73 41
+<< nmos >>
+rect -15 -103 15 41
+<< ndiff >>
+rect -73 23 -15 41
+rect -73 -85 -65 23
+rect -31 -85 -15 23
+rect -73 -103 -15 -85
+rect 15 23 73 41
+rect 15 -85 31 23
+rect 65 -85 73 23
+rect 15 -103 73 -85
+<< ndiffc >>
+rect -65 -85 -31 23
+rect 31 -85 65 23
+<< poly >>
+rect -33 113 33 129
+rect -33 79 -17 113
+rect 17 79 33 113
+rect -33 63 33 79
+rect -15 41 15 63
+rect -15 -129 15 -103
+<< polycont >>
+rect -17 79 17 113
+<< locali >>
+rect -33 79 -17 113
+rect 17 79 33 113
+rect -65 23 -31 39
+rect -65 -101 -31 -85
+rect 31 23 65 39
+rect 31 -101 65 -85
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.72 l 0.150 m 1 nf 1 diffcov 90 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EN37S3.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EN37S3.mag
new file mode 100755
index 0000000..7b32a87
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_EN37S3.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647116822
+<< error_p >>
+rect -29 131 29 137
+rect -29 97 -17 131
+rect -29 91 29 97
+rect -29 -97 29 -91
+rect -29 -131 -17 -97
+rect -29 -137 29 -131
+<< pwell >>
+rect -211 -269 211 269
+<< nmos >>
+rect -15 -59 15 59
+<< ndiff >>
+rect -73 47 -15 59
+rect -73 -47 -61 47
+rect -27 -47 -15 47
+rect -73 -59 -15 -47
+rect 15 47 73 59
+rect 15 -47 27 47
+rect 61 -47 73 47
+rect 15 -59 73 -47
+<< ndiffc >>
+rect -61 -47 -27 47
+rect 27 -47 61 47
+<< psubdiff >>
+rect -175 199 -79 233
+rect 79 199 175 233
+rect -175 137 -141 199
+rect 141 137 175 199
+rect -175 -199 -141 -137
+rect 141 -199 175 -137
+rect -175 -233 -79 -199
+rect 79 -233 175 -199
+<< psubdiffcont >>
+rect -79 199 79 233
+rect -175 -137 -141 137
+rect 141 -137 175 137
+rect -79 -233 79 -199
+<< poly >>
+rect -33 131 33 147
+rect -33 97 -17 131
+rect 17 97 33 131
+rect -33 81 33 97
+rect -15 59 15 81
+rect -15 -81 15 -59
+rect -33 -97 33 -81
+rect -33 -131 -17 -97
+rect 17 -131 33 -97
+rect -33 -147 33 -131
+<< polycont >>
+rect -17 97 17 131
+rect -17 -131 17 -97
+<< locali >>
+rect -175 199 -79 233
+rect 79 199 175 233
+rect -175 137 -141 199
+rect 141 137 175 199
+rect -33 97 -17 131
+rect 17 97 33 131
+rect -61 47 -27 63
+rect -61 -63 -27 -47
+rect 27 47 61 63
+rect 27 -63 61 -47
+rect -33 -131 -17 -97
+rect 17 -131 33 -97
+rect -175 -199 -141 -137
+rect 141 -199 175 -137
+rect -175 -233 -79 -199
+rect 79 -233 175 -199
+<< viali >>
+rect -17 97 17 131
+rect -61 -47 -27 47
+rect 27 -47 61 47
+rect -17 -131 17 -97
+<< metal1 >>
+rect -29 131 29 137
+rect -29 97 -17 131
+rect 17 97 29 131
+rect -29 91 29 97
+rect -67 47 -21 59
+rect -67 -47 -61 47
+rect -27 -47 -21 47
+rect -67 -59 -21 -47
+rect 21 47 67 59
+rect 21 -47 27 47
+rect 61 -47 67 47
+rect 21 -59 67 -47
+rect -29 -97 29 -91
+rect -29 -131 -17 -97
+rect 17 -131 29 -97
+rect -29 -137 29 -131
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -216 158 216
+string parameters w 0.59 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE.ext
new file mode 100755
index 0000000..3f8548d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE.ext
@@ -0,0 +1,14 @@
+timestamp 1646396437
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n73#" 207 22.3916 18 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 3864 260 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n73#" 207 22.3916 -76 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 3864 260 0 0 0 0 0 0 0 0 0 0
+node "a_n18_n99#" 287 115.123 -18 -99 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9108 528 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n18_n99#" "a_18_n73#" 45.5956
+cap "a_18_n73#" "a_n76_n73#" 129.35
+device msubckt sky130_fd_pr__nfet_01v8 -18 -73 -17 -72 l=36 w=84 "VSUBS" "a_n18_n99#" 72 0 "a_n76_n73#" 84 0 "a_18_n73#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE.mag
new file mode 100755
index 0000000..1368a2a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646396437
+<< error_p >>
+rect -14 83 44 89
+rect -14 49 -2 83
+rect -14 43 44 49
+<< nmos >>
+rect -18 -73 18 11
+<< ndiff >>
+rect -76 -1 -18 11
+rect -76 -61 -64 -1
+rect -30 -61 -18 -1
+rect -76 -73 -18 -61
+rect 18 -1 76 11
+rect 18 -61 30 -1
+rect 64 -61 76 -1
+rect 18 -73 76 -61
+<< ndiffc >>
+rect -64 -61 -30 -1
+rect 30 -61 64 -1
+<< poly >>
+rect -18 83 48 99
+rect -18 49 -2 83
+rect 32 49 48 83
+rect -18 33 48 49
+rect -18 11 18 33
+rect -18 -99 18 -73
+<< polycont >>
+rect -2 49 32 83
+<< locali >>
+rect -18 49 -2 83
+rect 32 49 48 83
+rect -64 -1 -30 15
+rect -64 -77 -30 -61
+rect 30 -1 64 15
+rect 30 -77 64 -61
+<< viali >>
+rect -2 49 32 83
+rect -64 -61 -30 -1
+rect 30 -61 64 -1
+<< metal1 >>
+rect -14 83 44 89
+rect -14 49 -2 83
+rect 32 49 44 83
+rect -14 43 44 49
+rect -70 -1 -24 11
+rect -70 -61 -64 -1
+rect -30 -61 -24 -1
+rect -70 -73 -24 -61
+rect 24 -1 70 11
+rect 24 -61 30 -1
+rect 64 -61 70 -1
+rect 24 -73 70 -61
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.42 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext
new file mode 100755
index 0000000..fb9e46a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n73#" 207 17.4716 18 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n73#" 207 17.4716 -76 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n18_n99#" 293 153.77 -18 -99 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10824 580 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n18_n99#" "a_18_n73#" 30.0882
+cap "a_18_n73#" "a_n76_n73#" 50.6
+device msubckt sky130_fd_pr__nfet_01v8 -18 -73 -17 -72 l=36 w=84 "VSUBS" "a_n18_n99#" 72 0 "a_n76_n73#" 84 0 "a_18_n73#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE_v2.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE_v2.mag
new file mode 100755
index 0000000..4d64915
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_HGTGXE_v2.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -73 -18 11
+rect 18 -73 76 11
+<< nmos >>
+rect -18 -73 18 11
+<< ndiff >>
+rect -76 -1 -18 11
+rect -76 -61 -64 -1
+rect -30 -61 -18 -1
+rect -76 -73 -18 -61
+rect 18 -1 76 11
+rect 18 -61 30 -1
+rect 64 -61 76 -1
+rect 18 -73 76 -61
+<< ndiffc >>
+rect -64 -61 -30 -1
+rect 30 -61 64 -1
+<< poly >>
+rect -18 83 74 99
+rect -18 49 11 83
+rect 45 49 74 83
+rect -18 33 74 49
+rect -18 11 18 33
+rect -18 -99 18 -73
+<< polycont >>
+rect 11 49 45 83
+<< locali >>
+rect -5 49 11 83
+rect 45 49 61 83
+rect -64 -1 -30 15
+rect -64 -77 -30 -61
+rect 30 -1 64 15
+rect 30 -77 64 -61
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.42 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_JS3BNU.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_JS3BNU.ext
new file mode 100755
index 0000000..04b1fb5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_JS3BNU.ext
@@ -0,0 +1,14 @@
+timestamp 1646399090
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n96#" 319 22.3916 15 -96 ndif 0 0 0 0 0 0 0 0 7540 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 5980 352 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n96#" 319 22.3916 -73 -96 ndif 0 0 0 0 0 0 0 0 7540 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 5980 352 0 0 0 0 0 0 0 0 0 0
+node "a_n57_56#" 398 111.739 -57 56 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10092 632 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n96#" "a_15_n96#" 223.619
+cap "a_n57_56#" "a_n73_n96#" 74.1176
+device msubckt sky130_fd_pr__nfet_01v8 -15 -96 -14 -95 l=30 w=130 "VSUBS" "a_n57_56#" 60 0 "a_n73_n96#" 130 0 "a_15_n96#" 130 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_JS3BNU.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_JS3BNU.mag
new file mode 100755
index 0000000..548a625
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_JS3BNU.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646399090
+<< error_p >>
+rect -53 106 5 112
+rect -53 72 -41 106
+rect -53 66 5 72
+<< nmos >>
+rect -15 -96 15 34
+<< ndiff >>
+rect -73 22 -15 34
+rect -73 -84 -61 22
+rect -27 -84 -15 22
+rect -73 -96 -15 -84
+rect 15 22 73 34
+rect 15 -84 27 22
+rect 61 -84 73 22
+rect 15 -96 73 -84
+<< ndiffc >>
+rect -61 -84 -27 22
+rect 27 -84 61 22
+<< poly >>
+rect -57 106 15 122
+rect -57 72 -41 106
+rect -7 72 15 106
+rect -57 56 15 72
+rect -15 34 15 56
+rect -15 -122 15 -96
+<< polycont >>
+rect -41 72 -7 106
+<< locali >>
+rect -57 72 -41 106
+rect -7 72 9 106
+rect -61 22 -27 38
+rect -61 -100 -27 -84
+rect 27 22 61 38
+rect 27 -100 61 -84
+<< viali >>
+rect -41 72 -7 106
+rect -61 -84 -27 22
+rect 27 -84 61 22
+<< metal1 >>
+rect -53 106 5 112
+rect -53 72 -41 106
+rect -7 72 5 106
+rect -53 66 5 72
+rect -67 22 -21 34
+rect -67 -84 -61 22
+rect -27 -84 -21 22
+rect -67 -96 -21 -84
+rect 21 22 67 34
+rect 21 -84 27 22
+rect 61 -84 67 22
+rect 21 -96 67 -84
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.650 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS29AB.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS29AB.ext
new file mode 100755
index 0000000..53a29da
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS29AB.ext
@@ -0,0 +1,15 @@
+timestamp 1645537996
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n68#" 176 15.7058 15 -68 ndif 0 0 0 0 0 0 0 0 4176 260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2584 220 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n68#" 176 15.7058 -73 -68 ndif 0 0 0 0 0 0 0 0 4176 260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2584 220 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 323 135.853 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8316 528 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_33#" "a_n73_n68#" 1.53488
+cap "a_15_n68#" "a_n33_33#" 1.53488
+cap "a_15_n68#" "a_n73_n68#" 40.4516
+device msubckt sky130_fd_pr__nfet_01v8 -15 -68 -14 -67 l=30 w=72 "VSUBS" "a_n33_33#" 60 0 "a_n73_n68#" 72 0 "a_15_n68#" 72 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS29AB.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS29AB.mag
new file mode 100755
index 0000000..bdfea54
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS29AB.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645537996
+<< error_p >>
+rect -15 4 15 16
+rect -15 -80 15 -68
+<< nmos >>
+rect -15 -68 15 4
+<< ndiff >>
+rect -73 -10 -15 4
+rect -73 -54 -65 -10
+rect -31 -54 -15 -10
+rect -73 -68 -15 -54
+rect 15 -10 73 4
+rect 15 -54 31 -10
+rect 65 -54 73 -10
+rect 15 -68 73 -54
+<< ndiffc >>
+rect -65 -54 -31 -10
+rect 31 -54 65 -10
+<< poly >>
+rect -33 83 33 99
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -33 33 33 49
+rect -15 4 15 33
+rect -15 -99 15 -68
+<< polycont >>
+rect -17 49 17 83
+<< locali >>
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -65 -10 -31 6
+rect -65 -70 -31 -54
+rect 31 -10 65 6
+rect 31 -70 65 -54
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 90 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS30AB.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS30AB.ext
new file mode 100755
index 0000000..0d87f2a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS30AB.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n80#" 205 15.7058 15 -80 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2992 244 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n80#" 205 15.7058 -73 -80 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2992 244 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 343 152.353 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8676 552 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_33#" "a_n73_n80#" 1.53488
+cap "a_n33_33#" "a_15_n80#" 1.53488
+cap "a_15_n80#" "a_n73_n80#" 46.8387
+device msubckt sky130_fd_pr__nfet_01v8 -15 -80 -14 -79 l=30 w=84 "VSUBS" "a_n33_33#" 60 0 "a_n73_n80#" 84 0 "a_15_n80#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS30AB.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS30AB.mag
new file mode 100755
index 0000000..9d3007a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_LS30AB.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -80 -15 4
+rect 15 -80 73 4
+<< nmos >>
+rect -15 -80 15 4
+<< ndiff >>
+rect -73 -10 -15 4
+rect -73 -66 -65 -10
+rect -31 -66 -15 -10
+rect -73 -80 -15 -66
+rect 15 -10 73 4
+rect 15 -66 31 -10
+rect 65 -66 73 -10
+rect 15 -80 73 -66
+<< ndiffc >>
+rect -65 -66 -31 -10
+rect 31 -66 65 -10
+<< poly >>
+rect -33 83 33 99
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -33 33 33 49
+rect -15 4 15 33
+rect -15 -111 15 -80
+<< polycont >>
+rect -17 49 17 83
+<< locali >>
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -65 -10 -31 6
+rect -65 -82 -31 -66
+rect 31 -10 65 6
+rect 31 -82 65 -66
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 90 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_M34CP3.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_M34CP3.ext
new file mode 100755
index 0000000..e6e37a4
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_M34CP3.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n96#" 318 17.4716 15 -96 ndif 0 0 0 0 0 0 0 0 7540 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n96#" 318 17.4716 -73 -96 ndif 0 0 0 0 0 0 0 0 7540 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_56#" 398 153.777 -73 56 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11148 664 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_56#" "a_n73_n96#" 33
+cap "a_15_n96#" "a_n73_n96#" 84.3333
+device msubckt sky130_fd_pr__nfet_01v8 -15 -96 -14 -95 l=30 w=130 "VSUBS" "a_n73_56#" 60 0 "a_n73_n96#" 130 0 "a_15_n96#" 130 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_M34CP3.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_M34CP3.mag
new file mode 100755
index 0000000..cac8f35
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_M34CP3.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -96 -15 34
+rect 15 -96 73 34
+<< nmos >>
+rect -15 -96 15 34
+<< ndiff >>
+rect -73 22 -15 34
+rect -73 -84 -61 22
+rect -27 -84 -15 22
+rect -73 -96 -15 -84
+rect 15 22 73 34
+rect 15 -84 27 22
+rect 61 -84 73 22
+rect 15 -96 73 -84
+<< ndiffc >>
+rect -61 -84 -27 22
+rect 27 -84 61 22
+<< poly >>
+rect -73 106 15 122
+rect -73 72 -57 106
+rect -23 72 15 106
+rect -73 56 15 72
+rect -15 34 15 56
+rect -15 -122 15 -96
+<< polycont >>
+rect -57 72 -23 106
+<< locali >>
+rect -73 72 -57 106
+rect -23 72 -7 106
+rect -61 22 -27 38
+rect -61 -100 -27 -84
+rect 27 22 61 38
+rect 27 -100 61 -84
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.650 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 0 viadrn 0 viagate 0 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MP0P50.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MP0P50.ext
new file mode 100755
index 0000000..7f69ae1
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MP0P50.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n96#" 244 15.7058 15 -96 ndif 0 0 0 0 0 0 0 0 5800 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n96#" 244 15.7058 -73 -96 ndif 0 0 0 0 0 0 0 0 5800 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 369 152.353 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9156 584 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_33#" "a_n73_n96#" 1.53488
+cap "a_n33_33#" "a_15_n96#" 1.53488
+cap "a_15_n96#" "a_n73_n96#" 55.3548
+device msubckt sky130_fd_pr__nfet_01v8 -15 -96 -14 -95 l=30 w=100 "VSUBS" "a_n33_33#" 60 0 "a_n73_n96#" 100 0 "a_15_n96#" 100 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MP0P50.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MP0P50.mag
new file mode 100755
index 0000000..10cc724
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MP0P50.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -96 -15 4
+rect 15 -96 73 4
+<< nmos >>
+rect -15 -96 15 4
+<< ndiff >>
+rect -73 -10 -15 4
+rect -73 -82 -65 -10
+rect -31 -82 -15 -10
+rect -73 -96 -15 -82
+rect 15 -10 73 4
+rect 15 -82 31 -10
+rect 65 -82 73 -10
+rect 15 -96 73 -82
+<< ndiffc >>
+rect -65 -82 -31 -10
+rect 31 -82 65 -10
+<< poly >>
+rect -33 83 33 99
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -33 33 33 49
+rect -15 4 15 33
+rect -15 -127 15 -96
+<< polycont >>
+rect -17 49 17 83
+<< locali >>
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -65 -10 -31 6
+rect -65 -98 -31 -82
+rect 31 -10 65 6
+rect 31 -98 65 -82
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 90 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MV8TJR.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MV8TJR.ext
new file mode 100755
index 0000000..2290012
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MV8TJR.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n89#" 586 17.4716 18 -89 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n89#" 586 17.4716 -76 -89 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n177#" 500 148.863 -33 -177 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14724 840 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n177#" "a_n76_n89#" 4.46349
+cap "a_n33_n177#" "a_18_n89#" 5.23135
+cap "a_18_n89#" "a_n76_n89#" 194.525
+device msubckt sky130_fd_pr__nfet_01v8 -18 -89 -17 -88 l=36 w=240 "VSUBS" "a_n33_n177#" 72 0 "a_n76_n89#" 240 0 "a_18_n89#" 240 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MV8TJR.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MV8TJR.mag
new file mode 100755
index 0000000..88ddb2f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_MV8TJR.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -89 -18 151
+rect 18 -89 76 151
+rect -29 -127 29 -121
+rect -29 -161 -17 -127
+rect -29 -167 29 -161
+<< nmos >>
+rect -18 -89 18 151
+<< ndiff >>
+rect -76 139 -18 151
+rect -76 -77 -64 139
+rect -30 -77 -18 139
+rect -76 -89 -18 -77
+rect 18 139 76 151
+rect 18 -77 30 139
+rect 64 -77 76 139
+rect 18 -89 76 -77
+<< ndiffc >>
+rect -64 -77 -30 139
+rect 30 -77 64 139
+<< poly >>
+rect -18 151 18 177
+rect -18 -111 18 -89
+rect -33 -127 33 -111
+rect -33 -161 -17 -127
+rect 17 -161 33 -127
+rect -33 -177 33 -161
+<< polycont >>
+rect -17 -161 17 -127
+<< locali >>
+rect -64 139 -30 155
+rect -64 -93 -30 -77
+rect 30 139 64 155
+rect 30 -93 64 -77
+rect -33 -161 -17 -127
+rect 17 -161 33 -127
+<< viali >>
+rect -64 36 -30 122
+rect 30 -12 64 74
+rect -17 -161 17 -127
+<< metal1 >>
+rect -70 122 -24 134
+rect -70 36 -64 122
+rect -30 36 -24 122
+rect -70 24 -24 36
+rect 24 74 70 86
+rect 24 -12 30 74
+rect 64 -12 70 74
+rect 24 -24 70 -12
+rect -29 -127 29 -121
+rect -29 -161 -17 -127
+rect 17 -161 29 -127
+rect -29 -167 29 -161
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1.2 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_N32XHY.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_N32XHY.ext
new file mode 100755
index 0000000..9a0e4ab
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_N32XHY.ext
@@ -0,0 +1,15 @@
+timestamp 1645180687
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n73#" 207 3.5316 15 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n73#" 207 3.5316 -73 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 324 114.359 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8316 528 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_33#" "a_n73_n73#" 13.8235
+cap "a_n73_n73#" "a_15_n73#" 114.079
+cap "a_n33_33#" "a_15_n73#" 13.1705
+device msubckt sky130_fd_pr__nfet_01v8 -15 -73 -14 -72 l=30 w=84 "VSUBS" "a_n33_33#" 60 0 "a_n73_n73#" 84 0 "a_15_n73#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_N32XHY.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_N32XHY.mag
new file mode 100755
index 0000000..c759f2f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_N32XHY.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645180687
+<< error_p >>
+rect -29 83 29 89
+rect -29 49 -17 83
+rect -29 43 29 49
+rect -67 -14 -21 -2
+rect -67 -48 -61 -14
+rect 21 -18 67 -6
+rect -67 -60 -21 -48
+rect 21 -52 27 -18
+rect 21 -64 67 -52
+<< nmos >>
+rect -15 -73 15 11
+<< ndiff >>
+rect -73 -1 -15 11
+rect -73 -61 -61 -1
+rect -27 -61 -15 -1
+rect -73 -73 -15 -61
+rect 15 -1 73 11
+rect 15 -61 27 -1
+rect 61 -61 73 -1
+rect 15 -73 73 -61
+<< ndiffc >>
+rect -61 -61 -27 -1
+rect 27 -61 61 -1
+<< poly >>
+rect -33 83 33 99
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -33 33 33 49
+rect -15 11 15 33
+rect -15 -99 15 -73
+<< polycont >>
+rect -17 49 17 83
+<< locali >>
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -61 -1 -27 15
+rect -61 -77 -27 -61
+rect 27 -1 61 15
+rect 27 -77 61 -61
+<< viali >>
+rect -17 49 17 83
+rect -61 -48 -27 -14
+rect 27 -52 61 -18
+<< metal1 >>
+rect -29 83 29 89
+rect -29 49 -17 83
+rect 17 49 29 83
+rect -29 43 29 49
+rect -67 -14 -21 -2
+rect -67 -48 -61 -14
+rect -27 -48 -21 -14
+rect -67 -60 -21 -48
+rect 21 -18 67 -6
+rect 21 -52 27 -18
+rect 61 -52 67 -18
+rect 21 -64 67 -52
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.42 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NDE37H.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NDE37H.ext
new file mode 100755
index 0000000..4212cb0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NDE37H.ext
@@ -0,0 +1,13 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n115#" 411 17.4716 15 -115 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n115#" 411 17.4716 -73 -115 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n118_22#" 623 171.49 -118 22 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11640 836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n115#" "a_15_n115#" 107.556
+device msubckt sky130_fd_pr__nfet_01v8 -15 -115 -14 -114 l=30 w=168 "VSUBS" "a_n118_22#" 60 0 "a_n73_n115#" 168 0 "a_15_n115#" 168 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NDE37H.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NDE37H.mag
new file mode 100755
index 0000000..809a6a5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NDE37H.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -115 -15 53
+rect 15 -115 73 53
+<< nmos >>
+rect -15 -115 15 53
+<< ndiff >>
+rect -73 41 -15 53
+rect -73 -103 -61 41
+rect -27 -103 -15 41
+rect -73 -115 -15 -103
+rect 15 41 73 53
+rect 15 -103 27 41
+rect 61 -103 73 41
+rect 15 -115 73 -103
+<< ndiffc >>
+rect -61 -103 -27 41
+rect 27 -103 61 41
+<< poly >>
+rect -118 68 15 98
+rect -118 22 -88 68
+rect -15 53 15 68
+rect -15 -141 15 -115
+<< locali >>
+rect -61 41 -27 57
+rect -61 -119 -27 -103
+rect 27 41 61 57
+rect 27 -119 61 -103
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.84 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NNRSEG.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NNRSEG.ext
new file mode 100755
index 0000000..5b59be4
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NNRSEG.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n29#" 294 17.4716 18 -29 ndif 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n29#" 294 17.4716 -76 -29 ndif 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n117#" 337 148.863 -33 -117 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10404 600 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n117#" "a_n76_n29#" 5.99396
+cap "a_n33_n117#" "a_18_n29#" 6.60029
+cap "a_18_n29#" "a_n76_n29#" 117.275
+device msubckt sky130_fd_pr__nfet_01v8 -18 -29 -17 -28 l=36 w=120 "VSUBS" "a_n33_n117#" 72 0 "a_n76_n29#" 120 0 "a_18_n29#" 120 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NNRSEG.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NNRSEG.mag
new file mode 100755
index 0000000..8ffffc4
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_NNRSEG.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -29 -18 91
+rect 18 -29 76 91
+rect -29 -67 29 -61
+rect -29 -101 -17 -67
+rect -29 -107 29 -101
+<< nmos >>
+rect -18 -29 18 91
+<< ndiff >>
+rect -76 79 -18 91
+rect -76 -17 -64 79
+rect -30 -17 -18 79
+rect -76 -29 -18 -17
+rect 18 79 76 91
+rect 18 -17 30 79
+rect 64 -17 76 79
+rect 18 -29 76 -17
+<< ndiffc >>
+rect -64 -17 -30 79
+rect 30 -17 64 79
+<< poly >>
+rect -18 91 18 117
+rect -18 -51 18 -29
+rect -33 -67 33 -51
+rect -33 -101 -17 -67
+rect 17 -101 33 -67
+rect -33 -117 33 -101
+<< polycont >>
+rect -17 -101 17 -67
+<< locali >>
+rect -64 79 -30 95
+rect -64 -33 -30 -17
+rect 30 79 64 95
+rect 30 -33 64 -17
+rect -33 -101 -17 -67
+rect 17 -101 33 -67
+<< viali >>
+rect -64 24 -30 62
+rect 30 12 64 50
+rect -17 -101 17 -67
+<< metal1 >>
+rect -70 62 -24 74
+rect -70 24 -64 62
+rect -30 24 -24 62
+rect -70 12 -24 24
+rect 24 50 70 62
+rect 24 12 30 50
+rect 64 12 70 50
+rect 24 0 70 12
+rect -29 -67 29 -61
+rect -29 -101 -17 -67
+rect 17 -101 29 -67
+rect -29 -107 29 -101
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.6 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW4BNL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW4BNL.ext
new file mode 100755
index 0000000..aee1917
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW4BNL.ext
@@ -0,0 +1,35 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_367_n163#" 418 26.3006 367 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n163#" 418 26.3006 279 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n163#" 418 26.3006 191 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 2052 658.756 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64440 3372 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n163#" "a_103_n163#" 119.778
+cap "a_n73_n163#" "a_191_n163#" 28.1217
+cap "a_367_n163#" "a_103_n163#" 28.1217
+cap "a_n73_37#" "a_n73_n163#" 33
+cap "a_15_n163#" "a_191_n163#" 45.5493
+cap "a_n73_n163#" "a_279_n163#" 20.3396
+cap "a_367_n163#" "a_191_n163#" 45.5493
+cap "a_103_n163#" "a_191_n163#" 119.778
+cap "a_15_n163#" "a_279_n163#" 28.1217
+cap "a_367_n163#" "a_279_n163#" 119.778
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_103_n163#" "a_279_n163#" 45.5493
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+cap "a_367_n163#" "a_15_n163#" 20.3396
+cap "a_191_n163#" "a_279_n163#" 119.778
+device msubckt sky130_fd_pr__nfet_01v8 337 -163 338 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_279_n163#" 168 0 "a_367_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 249 -163 250 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_191_n163#" 168 0 "a_279_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 161 -163 162 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_103_n163#" 168 0 "a_191_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW4BNL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW4BNL.mag
new file mode 100755
index 0000000..6dd1dec
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW4BNL.mag
@@ -0,0 +1,86 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -163 -15 5
+rect 15 -163 73 5
+rect 103 -163 161 5
+rect 191 -163 249 5
+rect 279 -163 337 5
+rect 367 -163 425 5
+<< nmos >>
+rect -15 -163 15 5
+rect 73 -163 103 5
+rect 161 -163 191 5
+rect 249 -163 279 5
+rect 337 -163 367 5
+<< ndiff >>
+rect -73 -7 -15 5
+rect -73 -151 -61 -7
+rect -27 -151 -15 -7
+rect -73 -163 -15 -151
+rect 15 -7 73 5
+rect 15 -151 27 -7
+rect 61 -151 73 -7
+rect 15 -163 73 -151
+rect 103 -7 161 5
+rect 103 -151 115 -7
+rect 149 -151 161 -7
+rect 103 -163 161 -151
+rect 191 -7 249 5
+rect 191 -151 203 -7
+rect 237 -151 249 -7
+rect 191 -163 249 -151
+rect 279 -7 337 5
+rect 279 -151 291 -7
+rect 325 -151 337 -7
+rect 279 -163 337 -151
+rect 367 -7 425 5
+rect 367 -151 379 -7
+rect 413 -151 425 -7
+rect 367 -163 425 -151
+<< ndiffc >>
+rect -61 -151 -27 -7
+rect 27 -151 61 -7
+rect 115 -151 149 -7
+rect 203 -151 237 -7
+rect 291 -151 325 -7
+rect 379 -151 413 -7
+<< poly >>
+rect -73 87 367 103
+rect -73 53 -57 87
+rect -23 53 367 87
+rect -73 37 367 53
+rect -15 5 15 37
+rect 73 5 103 37
+rect 161 5 191 37
+rect 249 5 279 37
+rect 337 5 367 37
+rect -15 -199 15 -163
+rect 73 -199 103 -163
+rect 161 -199 191 -163
+rect 249 -199 279 -163
+rect 337 -199 367 -163
+<< polycont >>
+rect -57 53 -23 87
+<< locali >>
+rect -73 53 -57 87
+rect -23 53 -7 87
+rect -61 -7 -27 19
+rect -61 -177 -27 -151
+rect 27 -7 61 19
+rect 27 -177 61 -151
+rect 115 -7 149 19
+rect 115 -177 149 -151
+rect 203 -7 237 19
+rect 203 -177 237 -151
+rect 291 -7 325 19
+rect 291 -177 325 -151
+rect 379 -7 413 19
+rect 379 -177 413 -151
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.460 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW5BNL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW5BNL.ext
new file mode 100755
index 0000000..a5bc26f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW5BNL.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n79#" 214 26.3006 15 -79 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n79#" 214 26.3006 -73 -79 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 356 166.367 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10368 612 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n79#" "a_15_n79#" 68.4444
+cap "a_n73_n79#" "a_n73_37#" 33
+device msubckt sky130_fd_pr__nfet_01v8 -15 -79 -14 -78 l=30 w=84 "VSUBS" "a_n73_37#" 60 0 "a_n73_n79#" 84 0 "a_15_n79#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW5BNL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW5BNL.mag
new file mode 100755
index 0000000..215176b
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW5BNL.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -79 -15 5
+rect 15 -79 73 5
+<< nmos >>
+rect -15 -79 15 5
+<< ndiff >>
+rect -73 -7 -15 5
+rect -73 -67 -61 -7
+rect -27 -67 -15 -7
+rect -73 -79 -15 -67
+rect 15 -7 73 5
+rect 15 -67 27 -7
+rect 61 -67 73 -7
+rect 15 -79 73 -67
+<< ndiffc >>
+rect -61 -67 -27 -7
+rect 27 -67 61 -7
+<< poly >>
+rect -73 87 15 103
+rect -73 53 -57 87
+rect -23 53 15 87
+rect -73 37 15 53
+rect -15 5 15 37
+rect -15 -115 15 -79
+<< polycont >>
+rect -57 53 -23 87
+<< locali >>
+rect -73 53 -57 87
+rect -23 53 -7 87
+rect -61 -7 -27 19
+rect -61 -93 -27 -67
+rect 27 -7 61 19
+rect 27 -93 61 -67
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.460 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW6BNL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW6BNL.ext
new file mode 100755
index 0000000..f7c27e6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW6BNL.ext
@@ -0,0 +1,23 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_191_n163#" 418 26.3006 191 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 1269 412.562 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38664 2076 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n163#" "a_103_n163#" 119.778
+cap "a_n73_n163#" "a_191_n163#" 28.1217
+cap "a_n73_37#" "a_n73_n163#" 33
+cap "a_15_n163#" "a_191_n163#" 45.5493
+cap "a_103_n163#" "a_191_n163#" 119.778
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+device msubckt sky130_fd_pr__nfet_01v8 161 -163 162 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_103_n163#" 168 0 "a_191_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW6BNL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW6BNL.mag
new file mode 100755
index 0000000..0189480
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW6BNL.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -163 -15 5
+rect 15 -163 73 5
+rect 103 -163 161 5
+rect 191 -163 249 5
+<< nmos >>
+rect -15 -163 15 5
+rect 73 -163 103 5
+rect 161 -163 191 5
+<< ndiff >>
+rect -73 -7 -15 5
+rect -73 -151 -61 -7
+rect -27 -151 -15 -7
+rect -73 -163 -15 -151
+rect 15 -7 73 5
+rect 15 -151 27 -7
+rect 61 -151 73 -7
+rect 15 -163 73 -151
+rect 103 -7 161 5
+rect 103 -151 115 -7
+rect 149 -151 161 -7
+rect 103 -163 161 -151
+rect 191 -7 249 5
+rect 191 -151 203 -7
+rect 237 -151 249 -7
+rect 191 -163 249 -151
+<< ndiffc >>
+rect -61 -151 -27 -7
+rect 27 -151 61 -7
+rect 115 -151 149 -7
+rect 203 -151 237 -7
+<< poly >>
+rect -73 87 191 103
+rect -73 53 -57 87
+rect -23 53 191 87
+rect -73 37 191 53
+rect -15 5 15 37
+rect 73 5 103 37
+rect 161 5 191 37
+rect -15 -199 15 -163
+rect 73 -199 103 -163
+rect 161 -199 191 -163
+<< polycont >>
+rect -57 53 -23 87
+<< locali >>
+rect -73 53 -57 87
+rect -23 53 -7 87
+rect -61 -7 -27 19
+rect -61 -177 -27 -151
+rect 27 -7 61 19
+rect 27 -177 61 -151
+rect 115 -7 149 19
+rect 115 -177 149 -151
+rect 203 -7 237 19
+rect 203 -177 237 -151
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.460 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW7BNL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW7BNL.ext
new file mode 100755
index 0000000..98445d5
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW7BNL.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 491 166.367 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12888 780 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_n73_37#" "a_n73_n163#" 33
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW7BNL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW7BNL.mag
new file mode 100755
index 0000000..c1b39db
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW7BNL.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -163 -15 5
+rect 15 -163 73 5
+<< nmos >>
+rect -15 -163 15 5
+<< ndiff >>
+rect -73 -7 -15 5
+rect -73 -151 -61 -7
+rect -27 -151 -15 -7
+rect -73 -163 -15 -151
+rect 15 -7 73 5
+rect 15 -151 27 -7
+rect 61 -151 73 -7
+rect 15 -163 73 -151
+<< ndiffc >>
+rect -61 -151 -27 -7
+rect 27 -151 61 -7
+<< poly >>
+rect -73 87 15 103
+rect -73 53 -57 87
+rect -23 53 15 87
+rect -73 37 15 53
+rect -15 5 15 37
+rect -15 -199 15 -163
+<< polycont >>
+rect -57 53 -23 87
+<< locali >>
+rect -73 53 -57 87
+rect -23 53 -7 87
+rect -61 -7 -27 19
+rect -61 -177 -27 -151
+rect 27 -7 61 19
+rect 27 -177 61 -151
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.460 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW8BNL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW8BNL.ext
new file mode 100755
index 0000000..6c04ce7
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW8BNL.ext
@@ -0,0 +1,18 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 878 289.464 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25776 1428 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n163#" "a_103_n163#" 119.778
+cap "a_n73_37#" "a_n73_n163#" 33
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW8BNL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW8BNL.mag
new file mode 100755
index 0000000..a4d36ec
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW8BNL.mag
@@ -0,0 +1,53 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -163 -15 5
+rect 15 -163 73 5
+rect 103 -163 161 5
+<< nmos >>
+rect -15 -163 15 5
+rect 73 -163 103 5
+<< ndiff >>
+rect -73 -7 -15 5
+rect -73 -151 -61 -7
+rect -27 -151 -15 -7
+rect -73 -163 -15 -151
+rect 15 -7 73 5
+rect 15 -151 27 -7
+rect 61 -151 73 -7
+rect 15 -163 73 -151
+rect 103 -7 161 5
+rect 103 -151 115 -7
+rect 149 -151 161 -7
+rect 103 -163 161 -151
+<< ndiffc >>
+rect -61 -151 -27 -7
+rect 27 -151 61 -7
+rect 115 -151 149 -7
+<< poly >>
+rect -73 87 103 103
+rect -73 53 -57 87
+rect -23 53 103 87
+rect -73 37 103 53
+rect -15 5 15 37
+rect 73 5 103 37
+rect -15 -199 15 -163
+rect 73 -199 103 -163
+<< polycont >>
+rect -57 53 -23 87
+<< locali >>
+rect -73 53 -57 87
+rect -23 53 -7 87
+rect -61 -7 -27 19
+rect -61 -177 -27 -151
+rect 27 -7 61 19
+rect 27 -177 61 -151
+rect 115 -7 149 19
+rect 115 -177 149 -151
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.460 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW9BNL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW9BNL.ext
new file mode 100755
index 0000000..46a2082
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW9BNL.ext
@@ -0,0 +1,52 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_631_n163#" 418 26.3006 631 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_543_n163#" 418 26.3006 543 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_455_n163#" 418 26.3006 455 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_367_n163#" 418 26.3006 367 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n163#" 418 26.3006 279 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n163#" 418 26.3006 191 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n199#" 3853 811.993 -15 -199 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71940 4856 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_103_n163#" "a_367_n163#" 28.1217
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_191_n163#" "a_n73_n163#" 28.1217
+cap "a_191_n163#" "a_455_n163#" 28.1217
+cap "a_n73_n163#" "a_279_n163#" 20.3396
+cap "a_191_n163#" "a_15_n163#" 45.5493
+cap "a_455_n163#" "a_279_n163#" 45.5493
+cap "a_455_n163#" "a_631_n163#" 45.5493
+cap "a_367_n163#" "a_455_n163#" 119.778
+cap "a_15_n163#" "a_279_n163#" 28.1217
+cap "a_15_n163#" "a_367_n163#" 20.3396
+cap "a_191_n163#" "a_279_n163#" 119.778
+cap "a_191_n163#" "a_367_n163#" 45.5493
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+cap "a_455_n163#" "a_543_n163#" 119.778
+cap "a_279_n163#" "a_631_n163#" 20.3396
+cap "a_103_n163#" "a_455_n163#" 20.3396
+cap "a_367_n163#" "a_279_n163#" 119.778
+cap "a_367_n163#" "a_631_n163#" 28.1217
+cap "a_191_n163#" "a_543_n163#" 20.3396
+cap "a_103_n163#" "a_15_n163#" 119.778
+cap "a_191_n163#" "a_103_n163#" 119.778
+cap "a_279_n163#" "a_543_n163#" 28.1217
+cap "a_543_n163#" "a_631_n163#" 119.778
+cap "a_367_n163#" "a_543_n163#" 45.5493
+cap "a_103_n163#" "a_279_n163#" 45.5493
+device msubckt sky130_fd_pr__nfet_01v8 601 -163 602 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_543_n163#" 168 0 "a_631_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 513 -163 514 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_455_n163#" 168 0 "a_543_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 425 -163 426 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_367_n163#" 168 0 "a_455_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 337 -163 338 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_279_n163#" 168 0 "a_367_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 249 -163 250 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_191_n163#" 168 0 "a_279_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 161 -163 162 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_103_n163#" 168 0 "a_191_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW9BNL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW9BNL.mag
new file mode 100755
index 0000000..e3b00d7
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_PW9BNL.mag
@@ -0,0 +1,112 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -73 -163 -15 5
+rect 15 -163 73 5
+rect 103 -163 161 5
+rect 191 -163 249 5
+rect 279 -163 337 5
+rect 367 -163 425 5
+rect 455 -163 513 5
+rect 543 -163 601 5
+rect 631 -163 689 5
+<< nmos >>
+rect -15 -163 15 5
+rect 73 -163 103 5
+rect 161 -163 191 5
+rect 249 -163 279 5
+rect 337 -163 367 5
+rect 425 -163 455 5
+rect 513 -163 543 5
+rect 601 -163 631 5
+<< ndiff >>
+rect -73 -7 -15 5
+rect -73 -151 -61 -7
+rect -27 -151 -15 -7
+rect -73 -163 -15 -151
+rect 15 -7 73 5
+rect 15 -151 27 -7
+rect 61 -151 73 -7
+rect 15 -163 73 -151
+rect 103 -7 161 5
+rect 103 -151 115 -7
+rect 149 -151 161 -7
+rect 103 -163 161 -151
+rect 191 -7 249 5
+rect 191 -151 203 -7
+rect 237 -151 249 -7
+rect 191 -163 249 -151
+rect 279 -7 337 5
+rect 279 -151 291 -7
+rect 325 -151 337 -7
+rect 279 -163 337 -151
+rect 367 -7 425 5
+rect 367 -151 379 -7
+rect 413 -151 425 -7
+rect 367 -163 425 -151
+rect 455 -7 513 5
+rect 455 -151 467 -7
+rect 501 -151 513 -7
+rect 455 -163 513 -151
+rect 543 -7 601 5
+rect 543 -151 555 -7
+rect 589 -151 601 -7
+rect 543 -163 601 -151
+rect 631 -7 689 5
+rect 631 -151 643 -7
+rect 677 -151 689 -7
+rect 631 -163 689 -151
+<< ndiffc >>
+rect -61 -151 -27 -7
+rect 27 -151 61 -7
+rect 115 -151 149 -7
+rect 203 -151 237 -7
+rect 291 -151 325 -7
+rect 379 -151 413 -7
+rect 467 -151 501 -7
+rect 555 -151 589 -7
+rect 643 -151 677 -7
+<< poly >>
+rect -15 20 631 50
+rect -15 5 15 20
+rect 73 5 103 20
+rect 161 5 191 20
+rect 249 5 279 20
+rect 337 5 367 20
+rect 425 5 455 20
+rect 513 5 543 20
+rect 601 5 631 20
+rect -15 -199 15 -163
+rect 73 -199 103 -163
+rect 161 -199 191 -163
+rect 249 -199 279 -163
+rect 337 -199 367 -163
+rect 425 -199 455 -163
+rect 513 -199 543 -163
+rect 601 -199 631 -163
+<< locali >>
+rect -61 -7 -27 19
+rect -61 -177 -27 -151
+rect 27 -7 61 19
+rect 27 -177 61 -151
+rect 115 -7 149 19
+rect 115 -177 149 -151
+rect 203 -7 237 19
+rect 203 -177 237 -151
+rect 291 -7 325 19
+rect 291 -177 325 -151
+rect 379 -7 413 19
+rect 379 -177 413 -151
+rect 467 -7 501 19
+rect 467 -177 501 -151
+rect 555 -7 589 19
+rect 555 -177 589 -151
+rect 643 -7 677 19
+rect 643 -177 677 -151
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.460 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_Q665WF.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_Q665WF.ext
new file mode 100755
index 0000000..72e4ca2
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_Q665WF.ext
@@ -0,0 +1,15 @@
+timestamp 1645106608
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n129#" 630 205.479 18 -129 ndif 0 0 0 0 0 0 0 0 14964 632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 5428 328 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n129#" 630 207.572 -76 -129 ndif 0 0 0 0 0 0 0 0 14964 632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 5428 328 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n217#" 674 505.463 -33 -217 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19584 1060 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+substrate "w_n214_n339#" 0 0 -214 -339 pw 290184 2212 0 0 0 0 0 0 0 0 60792 3576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60792 3576 14352 716 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n217#" "a_n76_n129#" 10.2353
+cap "a_n33_n217#" "a_18_n129#" 11.867
+cap "a_n76_n129#" "a_18_n129#" 207.238
+device msubckt sky130_fd_pr__nfet_01v8 -18 -129 -17 -128 l=36 w=258 "w_n214_n339#" "a_n33_n217#" 72 0 "a_n76_n129#" 258 0 "a_18_n129#" 258 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_Q665WF.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_Q665WF.mag
new file mode 100755
index 0000000..c320528
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_Q665WF.mag
@@ -0,0 +1,105 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645106608
+<< error_p >>
+rect -29 201 29 207
+rect -29 167 -17 201
+rect -29 161 29 167
+rect -29 -167 29 -161
+rect -29 -201 -17 -167
+rect -29 -207 29 -201
+<< pwell >>
+rect -214 -339 214 339
+<< nmos >>
+rect -18 -129 18 129
+<< ndiff >>
+rect -76 117 -18 129
+rect -76 -117 -64 117
+rect -30 -117 -18 117
+rect -76 -129 -18 -117
+rect 18 117 76 129
+rect 18 -117 30 117
+rect 64 -117 76 117
+rect 18 -129 76 -117
+<< ndiffc >>
+rect -64 -117 -30 117
+rect 30 -117 64 117
+<< psubdiff >>
+rect -178 269 -82 303
+rect 82 269 178 303
+rect -178 207 -144 269
+rect 144 207 178 269
+rect -178 -269 -144 -207
+rect 144 -269 178 -207
+rect -178 -303 -82 -269
+rect 82 -303 178 -269
+<< psubdiffcont >>
+rect -82 269 82 303
+rect -178 -207 -144 207
+rect 144 -207 178 207
+rect -82 -303 82 -269
+<< poly >>
+rect -33 201 33 217
+rect -33 167 -17 201
+rect 17 167 33 201
+rect -33 151 33 167
+rect -18 129 18 151
+rect -18 -151 18 -129
+rect -33 -167 33 -151
+rect -33 -201 -17 -167
+rect 17 -201 33 -167
+rect -33 -217 33 -201
+<< polycont >>
+rect -17 167 17 201
+rect -17 -201 17 -167
+<< locali >>
+rect -178 269 -82 303
+rect 82 269 178 303
+rect -178 207 -144 269
+rect 144 207 178 269
+rect -33 167 -17 201
+rect 17 167 33 201
+rect -64 117 -30 133
+rect -64 -133 -30 -117
+rect 30 117 64 133
+rect 30 -133 64 -117
+rect -33 -201 -17 -167
+rect 17 -201 33 -167
+rect -178 -303 -144 -207
+rect 144 -303 178 -207
+<< viali >>
+rect -17 167 17 201
+rect -64 -47 -30 47
+rect 30 6 64 100
+rect -17 -201 17 -167
+rect -144 -303 -82 -269
+rect -82 -303 82 -269
+rect 82 -303 144 -269
+<< metal1 >>
+rect -29 201 29 207
+rect -29 167 -17 201
+rect 17 167 29 201
+rect -29 161 29 167
+rect 24 100 70 112
+rect -70 47 -24 59
+rect -70 -47 -64 47
+rect -30 -47 -24 47
+rect 24 6 30 100
+rect 64 6 70 100
+rect 24 -6 70 6
+rect -70 -59 -24 -47
+rect -29 -167 29 -161
+rect -29 -201 -17 -167
+rect 17 -201 29 -167
+rect -29 -207 29 -201
+rect -156 -269 156 -263
+rect -156 -303 -144 -269
+rect 144 -303 156 -269
+rect -156 -309 156 -303
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -161 -286 161 286
+string parameters w 1.29 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc -40 viadrn 40 viagate 100 viagb 100 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TUVSF7.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TUVSF7.ext
new file mode 100755
index 0000000..d9dee1f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TUVSF7.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n129#" 629 17.4716 18 -129 ndif 0 0 0 0 0 0 0 0 14964 632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n129#" 630 17.4716 -76 -129 ndif 0 0 0 0 0 0 0 0 14964 632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 5428 328 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n217#" 615 210.624 -33 -217 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19584 1060 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n217#" "a_n76_n129#" 2.91176
+cap "a_n33_n217#" "a_18_n129#" 2.91176
+cap "a_18_n129#" "a_n76_n129#" 146.3
+device msubckt sky130_fd_pr__nfet_01v8 -18 -129 -17 -128 l=36 w=258 "VSUBS" "a_n33_n217#" 72 0 "a_n76_n129#" 258 0 "a_18_n129#" 258 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TUVSF7.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TUVSF7.mag
new file mode 100755
index 0000000..f246b60
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TUVSF7.mag
@@ -0,0 +1,50 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -129 -18 129
+rect 18 -129 76 129
+<< nmos >>
+rect -18 -129 18 129
+<< ndiff >>
+rect -76 117 -18 129
+rect -76 -117 -64 117
+rect -30 -117 -18 117
+rect -76 -129 -18 -117
+rect 18 117 76 129
+rect 18 -117 30 117
+rect 64 -117 76 117
+rect 18 -129 76 -117
+<< ndiffc >>
+rect -64 -117 -30 117
+rect 30 -117 64 117
+<< poly >>
+rect -33 151 33 217
+rect -18 129 18 151
+rect -18 -151 18 -129
+rect -33 -167 33 -151
+rect -33 -201 -17 -167
+rect 17 -201 33 -167
+rect -33 -217 33 -201
+<< polycont >>
+rect -17 -201 17 -167
+<< locali >>
+rect -64 117 -30 133
+rect -64 -133 -30 -117
+rect 30 117 64 133
+rect 30 -133 64 -117
+rect -33 -201 -17 -167
+rect 17 -201 33 -167
+<< viali >>
+rect -64 -47 -30 47
+<< metal1 >>
+rect -70 47 -24 59
+rect -70 -47 -64 47
+rect -30 -47 -24 47
+rect -70 -59 -24 -47
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1.29 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc -40 viadrn 40 viagate 100 viagb 100 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TWMWTA.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TWMWTA.ext
new file mode 100755
index 0000000..8b861b3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TWMWTA.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n209#" 1169 17.4716 18 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9660 512 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n209#" 1169 17.4716 -76 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 11776 604 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n297#" 823 148.863 -33 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23364 1320 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n297#" "a_n76_n209#" 4.47426
+cap "a_n33_n297#" "a_18_n209#" 4.25907
+cap "a_18_n209#" "a_n76_n209#" 465.275
+device msubckt sky130_fd_pr__nfet_01v8 -18 -209 -17 -208 l=36 w=480 "VSUBS" "a_n33_n297#" 72 0 "a_n76_n209#" 480 0 "a_18_n209#" 480 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TWMWTA.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TWMWTA.mag
new file mode 100755
index 0000000..c0ba8b0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_TWMWTA.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -76 -209 -18 271
+rect 18 -209 76 271
+rect -29 -247 29 -241
+rect -29 -281 -17 -247
+rect -29 -287 29 -281
+<< nmos >>
+rect -18 -209 18 271
+<< ndiff >>
+rect -76 259 -18 271
+rect -76 -197 -64 259
+rect -30 -197 -18 259
+rect -76 -209 -18 -197
+rect 18 259 76 271
+rect 18 -197 30 259
+rect 64 -197 76 259
+rect 18 -209 76 -197
+<< ndiffc >>
+rect -64 -197 -30 259
+rect 30 -197 64 259
+<< poly >>
+rect -18 271 18 297
+rect -18 -231 18 -209
+rect -33 -247 33 -231
+rect -33 -281 -17 -247
+rect 17 -281 33 -247
+rect -33 -297 33 -281
+<< polycont >>
+rect -17 -281 17 -247
+<< locali >>
+rect -64 259 -30 275
+rect -64 -213 -30 -197
+rect 30 259 64 275
+rect 30 -213 64 -197
+rect -33 -281 -17 -247
+rect 17 -281 33 -247
+<< viali >>
+rect -64 -85 -30 147
+rect 30 -62 64 124
+rect -17 -281 17 -247
+<< metal1 >>
+rect -70 147 -24 159
+rect -70 -85 -64 147
+rect -30 -85 -24 147
+rect 24 124 70 136
+rect 24 -62 30 124
+rect 64 -62 70 124
+rect 24 -74 70 -62
+rect -70 -97 -24 -85
+rect -29 -247 29 -241
+rect -29 -281 -17 -247
+rect 17 -281 29 -247
+rect -29 -287 29 -281
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2.4 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 41 viadrn 51 viagate 100 viagb 80 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_VT9X6R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_VT9X6R.mag
new file mode 100755
index 0000000..eebe487
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__nfet_01v8_VT9X6R.mag
@@ -0,0 +1,75 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646335127
+<< error_p >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect -29 74 29 80
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect -29 -120 29 -114
+<< nmos >>
+rect -18 -42 18 42
+<< ndiff >>
+rect -76 30 -18 42
+rect -76 -30 -64 30
+rect -30 -30 -18 30
+rect -76 -42 -18 -30
+rect 18 30 76 42
+rect 18 -30 30 30
+rect 64 -30 76 30
+rect 18 -42 76 -30
+<< ndiffc >>
+rect -64 -30 -30 30
+rect 30 -30 64 30
+<< poly >>
+rect -33 114 33 130
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -33 64 33 80
+rect -18 42 18 64
+rect -18 -64 18 -42
+rect -33 -80 33 -64
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -33 -130 33 -114
+<< polycont >>
+rect -17 80 17 114
+rect -17 -114 17 -80
+<< locali >>
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -64 30 -30 46
+rect -64 -46 -30 -30
+rect 30 30 64 46
+rect 30 -46 64 -30
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+<< viali >>
+rect -17 80 17 114
+rect -64 -30 -30 30
+rect 30 -30 64 30
+rect -17 -114 17 -80
+<< metal1 >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect 17 80 29 114
+rect -29 74 29 80
+rect -70 30 -24 42
+rect -70 -30 -64 30
+rect -30 -30 -24 30
+rect -70 -42 -24 -30
+rect 24 30 70 42
+rect 24 -30 30 30
+rect 64 -30 70 30
+rect 24 -42 70 -30
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect 17 -114 29 -80
+rect -29 -120 29 -114
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string parameters w 0.42 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_4XEGTB.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_4XEGTB.ext
new file mode 100755
index 0000000..5d06b26
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_4XEGTB.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n96#" 454 0 18 -96 pdif 0 0 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n96#" 454 0 -76 -96 pdif 0 0 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n33_55#" 349 16.9812 -33 55 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 618 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n158#" 2140 189.504 -112 -158 nw 0 0 0 0 63168 1012 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n96#" "a_n76_n96#" 128.525
+cap "w_n112_n158#" "a_n33_55#" 137.69
+cap "w_n112_n158#" "a_18_n96#" 17.4716
+cap "a_18_n96#" "a_n33_55#" 5.51661
+cap "w_n112_n158#" "a_n76_n96#" 17.4716
+cap "a_n76_n96#" "a_n33_55#" 5.51661
+device msubckt sky130_fd_pr__pfet_01v8 -18 -96 -17 -95 l=36 w=120 "w_n112_n158#" "a_n33_55#" 72 0 "a_n76_n96#" 120 0 "a_18_n96#" 120 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_4XEGTB.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_4XEGTB.mag
new file mode 100755
index 0000000..3f8d71f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_4XEGTB.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -112 -158 112 124
+<< nwell >>
+rect -112 -158 112 124
+<< pmos >>
+rect -18 -96 18 24
+<< pdiff >>
+rect -76 12 -18 24
+rect -76 -84 -64 12
+rect -30 -84 -18 12
+rect -76 -96 -18 -84
+rect 18 12 76 24
+rect 18 -84 30 12
+rect 64 -84 76 12
+rect 18 -96 76 -84
+<< pdiffc >>
+rect -64 -84 -30 12
+rect 30 -84 64 12
+<< poly >>
+rect -33 105 33 121
+rect -33 71 -17 105
+rect 17 71 33 105
+rect -33 55 33 71
+rect -18 24 18 55
+rect -18 -122 18 -96
+<< polycont >>
+rect -17 71 17 105
+<< locali >>
+rect -33 71 -17 105
+rect 17 71 33 105
+rect -64 12 -30 28
+rect -64 -100 -30 -84
+rect 30 12 64 28
+rect 30 -100 64 -84
+<< viali >>
+rect -17 71 17 105
+rect -64 -55 -30 -17
+rect 30 -55 64 -17
+<< metal1 >>
+rect -29 105 29 111
+rect -29 71 -17 105
+rect 17 71 29 105
+rect -29 65 29 71
+rect -70 -17 -24 -5
+rect -70 -55 -64 -17
+rect -30 -55 -24 -17
+rect -70 -67 -24 -55
+rect 24 -17 70 -5
+rect 24 -55 30 -17
+rect 64 -55 70 -17
+rect 24 -67 70 -55
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.6 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_5YXW2B.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_5YXW2B.ext
new file mode 100755
index 0000000..717fe1d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_5YXW2B.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n72#" 544 0 18 -72 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n72#" 544 0 -76 -72 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n18_n98#" 262 4.9608 -18 -98 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7056 464 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n134#" 2034 180.096 -112 -134 nw 0 0 0 0 60032 984 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n112_n134#" "a_n76_n72#" 22.3916
+cap "w_n112_n134#" "a_18_n72#" 22.3916
+cap "a_n76_n72#" "a_18_n72#" 218.6
+cap "a_n18_n98#" "w_n112_n134#" 68.2
+device msubckt sky130_fd_pr__pfet_01v8 -18 -72 -17 -71 l=36 w=144 "w_n112_n134#" "a_n18_n98#" 72 0 "a_n76_n72#" 144 0 "a_18_n72#" 144 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_5YXW2B.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_5YXW2B.mag
new file mode 100755
index 0000000..71575ff
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_5YXW2B.mag
@@ -0,0 +1,46 @@
+magic
+tech sky130A
+timestamp 1647613837
+<< error_p >>
+rect -56 -67 56 67
+<< nwell >>
+rect -56 -67 56 67
+<< pmos >>
+rect -9 -36 9 36
+<< pdiff >>
+rect -38 30 -9 36
+rect -38 -30 -32 30
+rect -15 -30 -9 30
+rect -38 -36 -9 -30
+rect 9 30 38 36
+rect 9 -30 15 30
+rect 32 -30 38 30
+rect 9 -36 38 -30
+<< pdiffc >>
+rect -32 -30 -15 30
+rect 15 -30 32 30
+<< poly >>
+rect -9 36 9 49
+rect -9 -49 9 -36
+<< locali >>
+rect -32 30 -15 38
+rect -32 -38 -15 -30
+rect 15 30 32 38
+rect 15 -38 32 -30
+<< viali >>
+rect -32 -30 -15 30
+rect 15 -30 32 30
+<< metal1 >>
+rect -35 30 -12 36
+rect -35 -30 -32 30
+rect -15 -30 -12 30
+rect -35 -36 -12 -30
+rect 12 30 35 36
+rect 12 -30 15 30
+rect 32 -30 35 30
+rect 12 -36 35 -30
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_9P8X3X.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_9P8X3X.ext
new file mode 100755
index 0000000..b72674b
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_9P8X3X.ext
@@ -0,0 +1,41 @@
+timestamp 1645106328
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_114_n220#" 1631 -325.54 114 -220 pdif 0 0 0 0 0 0 0 0 0 0 25960 998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 12604 640 0 0 0 0 0 0 0 0 0 0
+node "a_18_n220#" 1606 -274.29 18 -220 pdif 0 0 0 0 0 0 0 0 0 0 26400 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 6854 390 0 0 0 0 0 0 0 0 0 0
+node "a_n78_n220#" 1606 -325.54 -78 -220 pdif 0 0 0 0 0 0 0 0 0 0 26400 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 12604 640 0 0 0 0 0 0 0 0 0 0
+node "a_n173_n220#" 1630 -274.29 -173 -220 pdif 0 0 0 0 0 0 0 0 0 0 25960 998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 6854 390 0 0 0 0 0 0 0 0 0 0
+node "a_63_n317#" 782 -66.6588 63 -317 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22248 1258 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n317#" 782 -66.6588 -129 -317 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22248 1258 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n33_251#" 782 -66.6588 -33 251 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22248 1258 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n311_n439#" 12151 1595.71 -311 -439 nw 0 0 0 0 546116 3000 0 0 87584 5152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87584 5152 23276 1104 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_114_n220#" "a_n78_n220#" 178.022
+cap "a_63_n317#" "a_n33_251#" 19.9333
+cap "a_63_n317#" "w_n311_n439#" 233.328
+cap "a_18_n220#" "a_63_n317#" 2.10631
+cap "a_n33_251#" "w_n311_n439#" 277.015
+cap "a_18_n220#" "a_n33_251#" 4.63833
+cap "a_n173_n220#" "w_n311_n439#" 531.209
+cap "a_18_n220#" "a_n173_n220#" 139.494
+cap "a_63_n317#" "a_n129_n317#" 44.804
+cap "a_n129_n317#" "a_n33_251#" 19.9333
+cap "a_18_n220#" "w_n311_n439#" 444.588
+cap "a_n78_n220#" "a_n33_251#" 2.9865
+cap "a_n129_n317#" "a_n173_n220#" 2.10631
+cap "a_n173_n220#" "a_n78_n220#" 313.152
+cap "a_114_n220#" "a_63_n317#" 2.9865
+cap "a_n129_n317#" "w_n311_n439#" 233.328
+cap "a_n78_n220#" "w_n311_n439#" 492.06
+cap "a_18_n220#" "a_n78_n220#" 313.152
+cap "a_114_n220#" "a_n173_n220#" 73.6386
+cap "a_114_n220#" "w_n311_n439#" 578.681
+cap "a_n129_n317#" "a_n78_n220#" 2.9865
+cap "a_114_n220#" "a_18_n220#" 313.152
+device msubckt sky130_fd_pr__pfet_01v8 78 -220 79 -219 l=36 w=440 "w_n311_n439#" "a_63_n317#" 72 0 "a_18_n220#" 440 0 "a_114_n220#" 440 0
+device msubckt sky130_fd_pr__pfet_01v8 -18 -220 -17 -219 l=36 w=440 "w_n311_n439#" "a_n33_251#" 72 0 "a_n78_n220#" 440 0 "a_18_n220#" 440 0
+device msubckt sky130_fd_pr__pfet_01v8 -114 -220 -113 -219 l=36 w=440 "w_n311_n439#" "a_n129_n317#" 72 0 "a_n173_n220#" 440 0 "a_n78_n220#" 440 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_9P8X3X.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_9P8X3X.mag
new file mode 100755
index 0000000..aa11a67
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_9P8X3X.mag
@@ -0,0 +1,150 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645106328
+<< error_p >>
+rect -29 301 29 307
+rect -29 267 -17 301
+rect -29 261 29 267
+rect -125 -267 -67 -261
+rect 67 -267 125 -261
+rect -125 -301 -113 -267
+rect 67 -301 79 -267
+rect -125 -307 -67 -301
+rect 67 -307 125 -301
+<< nwell >>
+rect -311 -439 311 439
+<< pmos >>
+rect -114 -220 -78 220
+rect -18 -220 18 220
+rect 78 -220 114 220
+<< pdiff >>
+rect -173 208 -114 220
+rect -173 -208 -161 208
+rect -127 -208 -114 208
+rect -173 -220 -114 -208
+rect -78 208 -18 220
+rect -78 -208 -65 208
+rect -31 -208 -18 208
+rect -78 -220 -18 -208
+rect 18 208 78 220
+rect 18 -208 31 208
+rect 65 -208 78 208
+rect 18 -220 78 -208
+rect 114 208 173 220
+rect 114 -208 127 208
+rect 161 -208 173 208
+rect 114 -220 173 -208
+<< pdiffc >>
+rect -161 -208 -127 208
+rect -65 -208 -31 208
+rect 31 -208 65 208
+rect 127 -208 161 208
+<< nsubdiff >>
+rect -275 369 -179 403
+rect 179 369 275 403
+rect -275 307 -241 369
+rect 241 307 275 369
+rect -275 -369 -241 -307
+rect 241 -369 275 -307
+rect -275 -403 -179 -369
+rect 179 -403 275 -369
+<< nsubdiffcont >>
+rect -179 369 179 403
+rect -275 -307 -241 307
+rect 241 -307 275 307
+rect -179 -403 179 -369
+<< poly >>
+rect -33 301 33 317
+rect -33 267 -17 301
+rect 17 267 33 301
+rect -33 251 33 267
+rect -114 220 -78 246
+rect -18 220 18 251
+rect 78 220 114 246
+rect -114 -251 -78 -220
+rect -18 -246 18 -220
+rect 78 -251 114 -220
+rect -129 -267 -63 -251
+rect -129 -301 -113 -267
+rect -79 -301 -63 -267
+rect -129 -317 -63 -301
+rect 63 -267 129 -251
+rect 63 -301 79 -267
+rect 113 -301 129 -267
+rect 63 -317 129 -301
+<< polycont >>
+rect -17 267 17 301
+rect -113 -301 -79 -267
+rect 79 -301 113 -267
+<< locali >>
+rect -275 307 -241 403
+rect 241 307 275 403
+rect -33 267 -17 301
+rect 17 267 33 301
+rect -161 208 -127 224
+rect -161 -224 -127 -208
+rect -65 208 -31 224
+rect -65 -224 -31 -208
+rect 31 208 65 224
+rect 31 -224 65 -208
+rect 127 208 161 224
+rect 127 -224 161 -208
+rect -129 -301 -113 -267
+rect -79 -301 -63 -267
+rect 63 -301 79 -267
+rect 113 -301 129 -267
+rect -275 -369 -241 -307
+rect 241 -369 275 -307
+rect -275 -403 -179 -369
+rect 179 -403 275 -369
+<< viali >>
+rect -241 369 -179 403
+rect -179 369 179 403
+rect 179 369 241 403
+rect -17 267 17 301
+rect -161 66 -127 191
+rect -65 -125 -31 125
+rect 31 66 65 191
+rect 127 -125 161 125
+rect -113 -301 -79 -267
+rect 79 -301 113 -267
+<< metal1 >>
+rect -253 403 253 409
+rect -253 369 -241 403
+rect 241 369 253 403
+rect -253 363 253 369
+rect -29 301 29 307
+rect -29 267 -17 301
+rect 17 267 29 301
+rect -29 261 29 267
+rect -167 191 -121 203
+rect -167 66 -161 191
+rect -127 66 -121 191
+rect 25 191 71 203
+rect -167 54 -121 66
+rect -71 125 -25 137
+rect -71 -125 -65 125
+rect -31 -125 -25 125
+rect 25 66 31 191
+rect 65 66 71 191
+rect 25 54 71 66
+rect 121 125 167 137
+rect -71 -137 -25 -125
+rect 121 -125 127 125
+rect 161 -125 167 125
+rect 121 -137 167 -125
+rect -125 -267 -67 -261
+rect -125 -301 -113 -267
+rect -79 -301 -67 -267
+rect -125 -307 -67 -301
+rect 67 -267 125 -261
+rect 67 -301 79 -267
+rect 113 -301 125 -267
+rect 67 -307 125 -301
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -386 258 386
+string parameters w 2.1999999999999997 l 0.18 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 60 viadrn -30 viagate 100 viagb 0 viagr 0 viagl 0 viagt 100
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A1DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A1DS5R.ext
new file mode 100755
index 0000000..3f049eb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A1DS5R.ext
@@ -0,0 +1,22 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 1407 107.372 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26458 1818 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 2222 367.2 -109 -86 nw 0 0 0 0 122400 1412 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "w_n109_n86#" "a_n15_n133#" 133.1
+cap "a_n73_n36#" "a_103_n36#" 68.7887
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_15_n36#" "a_103_n36#" 180.889
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+cap "w_n109_n86#" "a_103_n36#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A1DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A1DS5R.mag
new file mode 100755
index 0000000..b3f9fa9
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A1DS5R.mag
@@ -0,0 +1,46 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -86 197 314
+<< nwell >>
+rect -109 -86 197 314
+<< pmos >>
+rect -15 -36 15 252
+rect 73 -36 103 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+rect 103 240 161 252
+rect 103 -24 115 240
+rect 149 -24 161 240
+rect 103 -36 161 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+rect 115 -24 149 240
+<< poly >>
+rect -15 252 15 278
+rect 73 252 103 278
+rect -15 -102 15 -36
+rect 73 -102 103 -36
+rect -15 -133 103 -102
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+rect 115 240 149 256
+rect 115 -40 149 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A2DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A2DS5R.ext
new file mode 100755
index 0000000..7332e14
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A2DS5R.ext
@@ -0,0 +1,42 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_367_n36#" 1084 0 367 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n36#" 1084 0 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 0 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n81#" 3257 46.6665 -15 -81 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60810 4114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 2423 684 -109 -86 nw 0 0 0 0 228000 1940 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_279_n36#" "a_191_n36#" 180.889
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+cap "a_191_n36#" "a_367_n36#" 68.7887
+cap "a_15_n36#" "a_191_n36#" 68.7887
+cap "w_n109_n86#" "a_103_n36#" 17.4716
+cap "a_279_n36#" "a_n73_n36#" 30.717
+cap "a_103_n36#" "a_191_n36#" 180.889
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "w_n109_n86#" "a_191_n36#" 17.4716
+cap "a_279_n36#" "a_367_n36#" 180.889
+cap "a_279_n36#" "a_15_n36#" 42.4696
+cap "w_n109_n86#" "a_n15_n81#" 421.85
+cap "a_15_n36#" "a_367_n36#" 30.717
+cap "a_n73_n36#" "a_103_n36#" 68.7887
+cap "a_279_n36#" "a_103_n36#" 68.7887
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_103_n36#" "a_367_n36#" 42.4696
+cap "a_279_n36#" "w_n109_n86#" 17.4716
+cap "a_15_n36#" "a_103_n36#" 180.889
+cap "a_n73_n36#" "a_191_n36#" 42.4696
+cap "w_n109_n86#" "a_367_n36#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 337 -36 338 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_279_n36#" 288 0 "a_367_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A2DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A2DS5R.mag
new file mode 100755
index 0000000..4d7ddb1
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A2DS5R.mag
@@ -0,0 +1,76 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -86 461 314
+<< nwell >>
+rect -109 -86 461 314
+<< pmos >>
+rect -15 -36 15 252
+rect 73 -36 103 252
+rect 161 -36 191 252
+rect 249 -36 279 252
+rect 337 -36 367 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+rect 103 240 161 252
+rect 103 -24 115 240
+rect 149 -24 161 240
+rect 103 -36 161 -24
+rect 191 240 249 252
+rect 191 -24 203 240
+rect 237 -24 249 240
+rect 191 -36 249 -24
+rect 279 240 337 252
+rect 279 -24 291 240
+rect 325 -24 337 240
+rect 279 -36 337 -24
+rect 367 240 425 252
+rect 367 -24 379 240
+rect 413 -24 425 240
+rect 367 -36 425 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+rect 115 -24 149 240
+rect 203 -24 237 240
+rect 291 -24 325 240
+rect 379 -24 413 240
+<< poly >>
+rect -15 252 15 278
+rect 73 252 103 278
+rect 161 252 191 278
+rect 249 252 279 278
+rect 337 252 367 278
+rect -15 -51 15 -36
+rect 73 -51 103 -36
+rect 161 -51 191 -36
+rect 249 -51 279 -36
+rect 337 -51 367 -36
+rect -15 -81 367 -51
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+rect 115 240 149 256
+rect 115 -40 149 -24
+rect 203 240 237 256
+rect 203 -40 237 -24
+rect 291 240 325 256
+rect 291 -40 325 -24
+rect 379 240 413 256
+rect 379 -40 413 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A3DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A3DS5R.mag
new file mode 100755
index 0000000..46ca62e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A3DS5R.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647345772
+<< nwell >>
+rect -109 -86 285 314
+<< pmos >>
+rect -15 -36 15 252
+rect 73 -36 103 252
+rect 161 -36 191 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+rect 103 240 161 252
+rect 103 -24 115 240
+rect 149 -24 161 240
+rect 103 -36 161 -24
+rect 191 240 249 252
+rect 191 -24 203 240
+rect 237 -24 249 240
+rect 191 -36 249 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+rect 115 -24 149 240
+rect 203 -24 237 240
+<< poly >>
+rect -15 252 15 278
+rect 73 252 103 278
+rect 161 252 191 278
+rect -15 -102 15 -36
+rect 73 -102 103 -36
+rect 161 -102 191 -36
+rect -15 -133 191 -102
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+rect 115 240 149 256
+rect 115 -40 149 -24
+rect 203 240 237 256
+rect 203 -40 237 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A4DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A4DS5R.ext
new file mode 100755
index 0000000..977a023
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A4DS5R.ext
@@ -0,0 +1,56 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_543_n36#" 1084 0 543 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_455_n36#" 1084 0 455 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_367_n36#" 1084 0 367 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n36#" 1084 0 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 0 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 5182 427.215 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96750 6510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 3171 895.2 -109 -86 nw 0 0 0 0 298400 2292 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_367_n36#" "a_279_n36#" 180.889
+cap "a_279_n36#" "w_n109_n86#" 17.4716
+cap "a_455_n36#" "a_543_n36#" 180.889
+cap "a_455_n36#" "a_103_n36#" 30.717
+cap "a_455_n36#" "a_191_n36#" 42.4696
+cap "a_367_n36#" "a_15_n36#" 30.717
+cap "a_455_n36#" "a_279_n36#" 68.7887
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+cap "a_543_n36#" "a_191_n36#" 30.717
+cap "a_191_n36#" "a_103_n36#" 180.889
+cap "a_n73_n36#" "a_103_n36#" 68.7887
+cap "a_n73_n36#" "a_191_n36#" 42.4696
+cap "a_543_n36#" "a_279_n36#" 42.4696
+cap "a_367_n36#" "w_n109_n86#" 17.4716
+cap "a_279_n36#" "a_103_n36#" 68.7887
+cap "a_279_n36#" "a_191_n36#" 180.889
+cap "a_279_n36#" "a_n73_n36#" 30.717
+cap "a_367_n36#" "a_455_n36#" 180.889
+cap "a_15_n36#" "a_103_n36#" 180.889
+cap "a_15_n36#" "a_191_n36#" 68.7887
+cap "a_455_n36#" "w_n109_n86#" 17.4716
+cap "w_n109_n86#" "a_n15_n133#" 465.85
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "a_279_n36#" "a_15_n36#" 42.4696
+cap "a_367_n36#" "a_543_n36#" 68.7887
+cap "a_367_n36#" "a_103_n36#" 42.4696
+cap "a_367_n36#" "a_191_n36#" 68.7887
+cap "a_543_n36#" "w_n109_n86#" 17.4716
+cap "w_n109_n86#" "a_103_n36#" 17.4716
+cap "w_n109_n86#" "a_191_n36#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 513 -36 514 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_455_n36#" 288 0 "a_543_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 425 -36 426 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_367_n36#" 288 0 "a_455_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 337 -36 338 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_279_n36#" 288 0 "a_367_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A4DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A4DS5R.mag
new file mode 100755
index 0000000..15986ad
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A4DS5R.mag
@@ -0,0 +1,96 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -86 637 314
+<< nwell >>
+rect -109 -86 637 314
+<< pmos >>
+rect -15 -36 15 252
+rect 73 -36 103 252
+rect 161 -36 191 252
+rect 249 -36 279 252
+rect 337 -36 367 252
+rect 425 -36 455 252
+rect 513 -36 543 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+rect 103 240 161 252
+rect 103 -24 115 240
+rect 149 -24 161 240
+rect 103 -36 161 -24
+rect 191 240 249 252
+rect 191 -24 203 240
+rect 237 -24 249 240
+rect 191 -36 249 -24
+rect 279 240 337 252
+rect 279 -24 291 240
+rect 325 -24 337 240
+rect 279 -36 337 -24
+rect 367 240 425 252
+rect 367 -24 379 240
+rect 413 -24 425 240
+rect 367 -36 425 -24
+rect 455 240 513 252
+rect 455 -24 467 240
+rect 501 -24 513 240
+rect 455 -36 513 -24
+rect 543 240 601 252
+rect 543 -24 555 240
+rect 589 -24 601 240
+rect 543 -36 601 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+rect 115 -24 149 240
+rect 203 -24 237 240
+rect 291 -24 325 240
+rect 379 -24 413 240
+rect 467 -24 501 240
+rect 555 -24 589 240
+<< poly >>
+rect -15 252 15 278
+rect 73 252 103 278
+rect 161 252 191 278
+rect 249 252 279 278
+rect 337 252 367 278
+rect 425 252 455 278
+rect 513 252 543 278
+rect -15 -103 15 -36
+rect 73 -103 103 -36
+rect 161 -103 191 -36
+rect 249 -103 279 -36
+rect 337 -103 367 -36
+rect 425 -103 455 -36
+rect 513 -103 543 -36
+rect -15 -133 543 -103
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+rect 115 240 149 256
+rect 115 -40 149 -24
+rect 203 240 237 256
+rect 203 -40 237 -24
+rect 291 240 325 256
+rect 291 -40 325 -24
+rect 379 240 413 256
+rect 379 -40 413 -24
+rect 467 240 501 256
+rect 467 -40 501 -24
+rect 555 240 589 256
+rect 555 -40 589 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A7DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A7DS5R.ext
new file mode 100755
index 0000000..4d2640a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A7DS5R.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n36#" 544 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 544 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 429 43.8785 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8010 594 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 1996 167.424 -109 -86 nw 0 0 0 0 55808 948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n36#" "a_n73_n36#" 92.8889
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_n15_n133#" "w_n109_n86#" 66.55
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=144 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 144 0 "a_15_n36#" 144 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A7DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A7DS5R.mag
new file mode 100755
index 0000000..923af47
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A7DS5R.mag
@@ -0,0 +1,35 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -86 109 170
+<< nwell >>
+rect -109 -86 109 170
+<< pmos >>
+rect -15 -36 15 108
+<< pdiff >>
+rect -73 96 -15 108
+rect -73 -24 -61 96
+rect -27 -24 -15 96
+rect -73 -36 -15 -24
+rect 15 96 73 108
+rect 15 -24 27 96
+rect 61 -24 73 96
+rect 15 -36 73 -24
+<< pdiffc >>
+rect -61 -24 -27 96
+rect 27 -24 61 96
+<< poly >>
+rect -15 108 15 134
+rect -15 -133 15 -36
+<< locali >>
+rect -61 96 -27 112
+rect -61 -40 -27 -24
+rect 27 96 61 112
+rect 27 -40 61 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A8DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A8DS5R.ext
new file mode 100755
index 0000000..d385141
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A8DS5R.ext
@@ -0,0 +1,35 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_279_n36#" 1084 0 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 0 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 2921 235.547 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54540 3696 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 2049 578.4 -109 -86 nw 0 0 0 0 192800 1764 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n36#" "a_103_n36#" 68.7887
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+cap "a_279_n36#" "a_191_n36#" 180.889
+cap "a_103_n36#" "a_191_n36#" 180.889
+cap "a_n73_n36#" "w_n109_n86#" 17.4716
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "a_103_n36#" "a_279_n36#" 68.7887
+cap "w_n109_n86#" "a_191_n36#" 17.4716
+cap "a_191_n36#" "a_15_n36#" 68.7887
+cap "w_n109_n86#" "a_279_n36#" 17.4716
+cap "a_n73_n36#" "a_191_n36#" 42.4696
+cap "a_103_n36#" "w_n109_n86#" 17.4716
+cap "a_279_n36#" "a_15_n36#" 42.4696
+cap "a_103_n36#" "a_15_n36#" 180.889
+cap "w_n109_n86#" "a_n15_n133#" 266.2
+cap "a_n73_n36#" "a_279_n36#" 30.717
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A8DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A8DS5R.mag
new file mode 100755
index 0000000..5a4a1cd
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A8DS5R.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -86 373 314
+<< nwell >>
+rect -109 -86 373 314
+<< pmos >>
+rect -15 -36 15 252
+rect 73 -36 103 252
+rect 161 -36 191 252
+rect 249 -36 279 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+rect 103 240 161 252
+rect 103 -24 115 240
+rect 149 -24 161 240
+rect 103 -36 161 -24
+rect 191 240 249 252
+rect 191 -24 203 240
+rect 237 -24 249 240
+rect 191 -36 249 -24
+rect 279 240 337 252
+rect 279 -24 291 240
+rect 325 -24 337 240
+rect 279 -36 337 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+rect 115 -24 149 240
+rect 203 -24 237 240
+rect 291 -24 325 240
+<< poly >>
+rect -15 252 15 278
+rect 73 252 103 278
+rect 161 252 191 278
+rect 249 252 279 278
+rect -15 -103 15 -36
+rect 73 -103 103 -36
+rect 161 -103 191 -36
+rect 249 -103 279 -36
+rect -15 -133 279 -103
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+rect 115 240 149 256
+rect 115 -40 149 -24
+rect 203 240 237 256
+rect 203 -40 237 -24
+rect 291 240 325 256
+rect 291 -40 325 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A9DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A9DS5R.ext
new file mode 100755
index 0000000..1230232
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A9DS5R.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 660 43.8785 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12330 882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 3119 261.6 -109 -86 nw 0 0 0 0 87200 1236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n109_n86#" "a_n15_n133#" 66.55
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_15_n36#" "a_n73_n36#" 180.889
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A9DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A9DS5R.mag
new file mode 100755
index 0000000..5835334
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_A9DS5R.mag
@@ -0,0 +1,35 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -86 109 314
+<< nwell >>
+rect -109 -86 109 314
+<< pmos >>
+rect -15 -36 15 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+<< poly >>
+rect -15 252 15 278
+rect -15 -133 15 -36
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B.ext
new file mode 100755
index 0000000..46efb28
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n108#" 544 0 18 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n108#" 544 0 -76 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n33_67#" 382 16.9812 -33 67 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11592 666 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n170#" 2322 205.632 -112 -170 nw 0 0 0 0 68544 1060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n108#" "a_n76_n108#" 218.6
+cap "w_n112_n170#" "a_n33_67#" 137.69
+cap "w_n112_n170#" "a_18_n108#" 22.3916
+cap "a_18_n108#" "a_n33_67#" 7.79013
+cap "w_n112_n170#" "a_n76_n108#" 22.3916
+cap "a_n76_n108#" "a_n33_67#" 7.79013
+device msubckt sky130_fd_pr__pfet_01v8 -18 -108 -17 -107 l=36 w=144 "w_n112_n170#" "a_n33_67#" 72 0 "a_n76_n108#" 144 0 "a_18_n108#" 144 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B.mag
new file mode 100755
index 0000000..e0a44d0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -112 -170 112 136
+<< nwell >>
+rect -112 -170 112 136
+<< pmos >>
+rect -18 -108 18 36
+<< pdiff >>
+rect -76 24 -18 36
+rect -76 -96 -64 24
+rect -30 -96 -18 24
+rect -76 -108 -18 -96
+rect 18 24 76 36
+rect 18 -96 30 24
+rect 64 -96 76 24
+rect 18 -108 76 -96
+<< pdiffc >>
+rect -64 -96 -30 24
+rect 30 -96 64 24
+<< poly >>
+rect -33 117 33 133
+rect -33 83 -17 117
+rect 17 83 33 117
+rect -33 67 33 83
+rect -18 36 18 67
+rect -18 -134 18 -108
+<< polycont >>
+rect -17 83 17 117
+<< locali >>
+rect -33 83 -17 117
+rect 17 83 33 117
+rect -64 24 -30 40
+rect -64 -112 -30 -96
+rect 30 24 64 40
+rect 30 -112 64 -96
+<< viali >>
+rect -17 83 17 117
+rect -64 -96 -30 24
+rect 30 -96 64 24
+<< metal1 >>
+rect -29 117 29 123
+rect -29 83 -17 117
+rect 17 83 29 117
+rect -29 77 29 83
+rect -70 24 -24 36
+rect -70 -96 -64 24
+rect -30 -96 -24 24
+rect -70 -108 -24 -96
+rect 24 24 70 36
+rect 24 -96 30 24
+rect 64 -96 70 24
+rect 24 -108 70 -96
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.ext
new file mode 100755
index 0000000..c3f97d3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.ext
@@ -0,0 +1,18 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n108#" 544 0 18 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n108#" 544 0 -76 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n68_67#" 386 20.4792 -68 67 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12912 706 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n170#" 2322 205.632 -112 -170 nw 0 0 0 0 68544 1060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n112_n170#" "a_n76_n108#" 22.3916
+cap "w_n112_n170#" "a_18_n108#" 22.3916
+cap "a_n76_n108#" "a_18_n108#" 218.6
+cap "a_n68_67#" "w_n112_n170#" 141.72
+cap "a_n68_67#" "a_n76_n108#" 26.093
+device msubckt sky130_fd_pr__pfet_01v8 -18 -108 -17 -107 l=36 w=144 "w_n112_n170#" "a_n68_67#" 72 0 "a_n76_n108#" 144 0 "a_18_n108#" 144 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.mag
new file mode 100755
index 0000000..09bbde6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.mag
@@ -0,0 +1,55 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -112 -170 112 136
+<< nwell >>
+rect -112 -170 112 136
+<< pmos >>
+rect -18 -108 18 36
+<< pdiff >>
+rect -76 24 -18 36
+rect -76 -96 -64 24
+rect -30 -96 -18 24
+rect -76 -108 -18 -96
+rect 18 24 76 36
+rect 18 -96 30 24
+rect 64 -96 76 24
+rect 18 -108 76 -96
+<< pdiffc >>
+rect -64 -96 -30 24
+rect 30 -96 64 24
+<< poly >>
+rect -68 117 18 133
+rect -68 83 -52 117
+rect -18 83 18 117
+rect -68 67 18 83
+rect -18 36 18 67
+rect -18 -134 18 -108
+<< polycont >>
+rect -52 83 -18 117
+<< locali >>
+rect -68 83 -52 117
+rect -18 83 -2 117
+rect -64 24 -30 40
+rect -64 -112 -30 -96
+rect 30 24 64 40
+rect 30 -112 64 -96
+<< viali >>
+rect -64 -96 -30 24
+rect 30 -96 64 24
+<< metal1 >>
+rect -70 24 -24 36
+rect -70 -96 -64 24
+rect -30 -96 -24 24
+rect -70 -108 -24 -96
+rect 24 24 70 36
+rect 24 -96 30 24
+rect 64 -96 70 24
+rect 24 -108 70 -96
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.72 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPH4B.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPH4B.mag
new file mode 100755
index 0000000..99c1051
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPH4B.mag
@@ -0,0 +1,40 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646470613
+<< nwell >>
+rect -112 -140 112 106
+<< pmos >>
+rect -18 -78 18 6
+<< pdiff >>
+rect -76 -6 -18 6
+rect -76 -66 -64 -6
+rect -30 -66 -18 -6
+rect -76 -78 -18 -66
+rect 18 -6 76 6
+rect 18 -66 30 -6
+rect 64 -66 76 -6
+rect 18 -78 76 -66
+<< pdiffc >>
+rect -64 -66 -30 -6
+rect 30 -66 64 -6
+<< poly >>
+rect -18 6 18 37
+rect -18 -104 18 -78
+<< locali >>
+rect -64 -6 -30 10
+rect -64 -82 -30 -66
+rect 30 -6 64 10
+rect 30 -82 64 -66
+<< viali >>
+rect 30 -66 64 -6
+<< metal1 >>
+rect 24 -6 70 6
+rect 24 -66 30 -6
+rect 64 -66 70 -6
+rect 24 -78 70 -66
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.42 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPHKB.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPHKB.ext
new file mode 100755
index 0000000..4b45f37
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPHKB.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n78#" 318 0 15 -78 pdif 0 0 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n78#" 318 0 -73 -78 pdif 0 0 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_37#" 338 16.0749 -33 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8586 546 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n140#" 1918 160.884 -109 -140 nw 0 0 0 0 53628 928 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n78#" "a_n73_n78#" 56.2222
+cap "w_n109_n140#" "a_15_n78#" 17.4716
+cap "w_n109_n140#" "a_n73_n78#" 17.4716
+cap "a_n33_37#" "a_15_n78#" 4.60465
+cap "a_n33_37#" "a_n73_n78#" 4.60465
+cap "a_n33_37#" "w_n109_n140#" 134.39
+device msubckt sky130_fd_pr__pfet_01v8 -15 -78 -14 -77 l=30 w=84 "w_n109_n140#" "a_n33_37#" 60 0 "a_n73_n78#" 84 0 "a_15_n78#" 84 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPHKB.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPHKB.mag
new file mode 100755
index 0000000..3b6f1df
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_ACPHKB.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -140 109 106
+<< nwell >>
+rect -109 -140 109 106
+<< pmos >>
+rect -15 -78 15 6
+<< pdiff >>
+rect -73 -6 -15 6
+rect -73 -66 -61 -6
+rect -27 -66 -15 -6
+rect -73 -78 -15 -66
+rect 15 -6 73 6
+rect 15 -66 27 -6
+rect 61 -66 73 -6
+rect 15 -78 73 -66
+<< pdiffc >>
+rect -61 -66 -27 -6
+rect 27 -66 61 -6
+<< poly >>
+rect -33 87 33 103
+rect -33 53 -17 87
+rect 17 53 33 87
+rect -33 37 33 53
+rect -15 6 15 37
+rect -15 -104 15 -78
+<< polycont >>
+rect -17 53 17 87
+<< locali >>
+rect -33 53 -17 87
+rect 17 53 33 87
+rect -61 -6 -27 10
+rect -61 -82 -27 -66
+rect 27 -6 61 10
+rect 27 -82 61 -66
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_AZHELG.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_AZHELG.ext
new file mode 100755
index 0000000..0e95239
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_AZHELG.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n22#" 604 0 15 -22 pdif 0 0 0 0 0 0 0 0 0 0 9280 436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5712 404 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n72_n22#" 614 0 -72 -22 pdif 0 0 0 0 0 0 0 0 0 0 9120 434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5712 404 4830 302 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n53#" 349 4.5315 -15 -53 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6510 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n58#" 2012 168.732 -109 -58 nw 0 0 0 0 56244 952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n22#" "a_n72_n22#" 90.8852
+cap "w_n109_n58#" "a_n15_n53#" 64.35
+cap "w_n109_n58#" "a_15_n22#" 17.4716
+cap "w_n109_n58#" "a_n72_n22#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 -15 -22 -14 -21 l=30 w=160 "w_n109_n58#" "a_n15_n53#" 60 0 "a_n72_n22#" 160 0 "a_15_n22#" 160 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_AZHELG.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_AZHELG.mag
new file mode 100755
index 0000000..fd1bf3c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_AZHELG.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -58 109 200
+<< nwell >>
+rect -109 -58 109 200
+<< pmos >>
+rect -15 -22 15 138
+<< pdiff >>
+rect -72 126 -15 138
+rect -72 -10 -64 126
+rect -30 -10 -15 126
+rect -72 -22 -15 -10
+rect 15 126 73 138
+rect 15 -10 31 126
+rect 65 -10 73 126
+rect 15 -22 73 -10
+<< pdiffc >>
+rect -64 -10 -30 126
+rect 31 -10 65 126
+<< poly >>
+rect -15 138 15 164
+rect -15 -53 15 -22
+<< locali >>
+rect -64 126 -30 142
+rect -64 -26 -30 -10
+rect 31 126 65 142
+rect 31 -26 65 -10
+<< viali >>
+rect -64 28 -30 109
+<< metal1 >>
+rect -70 109 -24 121
+rect -70 28 -64 109
+rect -30 28 -24 109
+rect -70 16 -24 28
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.58 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_B2DS5R.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_B2DS5R.ext
new file mode 100755
index 0000000..fe04786
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_B2DS5R.ext
@@ -0,0 +1,56 @@
+timestamp 1647369436
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_543_n36#" 1084 -118.08 543 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_455_n36#" 1084 -118.08 455 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_367_n36#" 1084 -118.08 367 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n36#" 1084 -118.08 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 -118.08 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 -118.08 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 -118.08 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 -118.08 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n81#" 4597 67.1775 -15 -81 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85830 5782 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 3171 895.2 -109 -86 nw 0 0 0 0 298400 2292 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_367_n36#" "a_15_n36#" 30.717
+cap "a_367_n36#" "a_103_n36#" 42.4696
+cap "a_15_n36#" "a_103_n36#" 180.889
+cap "a_367_n36#" "a_191_n36#" 68.7887
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "a_367_n36#" "a_455_n36#" 180.889
+cap "a_n73_n36#" "a_103_n36#" 68.7887
+cap "a_15_n36#" "a_191_n36#" 68.7887
+cap "a_103_n36#" "a_191_n36#" 180.889
+cap "a_367_n36#" "a_543_n36#" 68.7887
+cap "a_367_n36#" "a_279_n36#" 180.889
+cap "a_103_n36#" "a_455_n36#" 30.717
+cap "a_367_n36#" "w_n109_n86#" 135.552
+cap "a_n73_n36#" "a_191_n36#" 42.4696
+cap "a_279_n36#" "a_15_n36#" 42.4696
+cap "a_15_n36#" "w_n109_n86#" 135.552
+cap "a_279_n36#" "a_103_n36#" 68.7887
+cap "w_n109_n86#" "a_n15_n81#" 481.25
+cap "w_n109_n86#" "a_103_n36#" 135.552
+cap "a_191_n36#" "a_455_n36#" 42.4696
+cap "a_n73_n36#" "a_279_n36#" 30.717
+cap "a_191_n36#" "a_543_n36#" 30.717
+cap "a_n73_n36#" "w_n109_n86#" 135.552
+cap "a_279_n36#" "a_191_n36#" 180.889
+cap "w_n109_n86#" "a_191_n36#" 135.552
+cap "a_543_n36#" "a_455_n36#" 180.889
+cap "a_279_n36#" "a_455_n36#" 68.7887
+cap "w_n109_n86#" "a_455_n36#" 135.552
+cap "a_279_n36#" "a_543_n36#" 42.4696
+cap "w_n109_n86#" "a_543_n36#" 135.552
+cap "a_279_n36#" "w_n109_n86#" 135.552
+device msubckt sky130_fd_pr__pfet_01v8 513 -36 514 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_455_n36#" 288 0 "a_543_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 425 -36 426 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_367_n36#" 288 0 "a_455_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 337 -36 338 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_279_n36#" 288 0 "a_367_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_B2DS5R.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_B2DS5R.mag
new file mode 100755
index 0000000..081fb14
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_B2DS5R.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647369436
+<< nwell >>
+rect -109 -86 637 314
+<< pmos >>
+rect -15 -36 15 252
+rect 73 -36 103 252
+rect 161 -36 191 252
+rect 249 -36 279 252
+rect 337 -36 367 252
+rect 425 -36 455 252
+rect 513 -36 543 252
+<< pdiff >>
+rect -73 240 -15 252
+rect -73 -24 -61 240
+rect -27 -24 -15 240
+rect -73 -36 -15 -24
+rect 15 240 73 252
+rect 15 -24 27 240
+rect 61 -24 73 240
+rect 15 -36 73 -24
+rect 103 240 161 252
+rect 103 -24 115 240
+rect 149 -24 161 240
+rect 103 -36 161 -24
+rect 191 240 249 252
+rect 191 -24 203 240
+rect 237 -24 249 240
+rect 191 -36 249 -24
+rect 279 240 337 252
+rect 279 -24 291 240
+rect 325 -24 337 240
+rect 279 -36 337 -24
+rect 367 240 425 252
+rect 367 -24 379 240
+rect 413 -24 425 240
+rect 367 -36 425 -24
+rect 455 240 513 252
+rect 455 -24 467 240
+rect 501 -24 513 240
+rect 455 -36 513 -24
+rect 543 240 601 252
+rect 543 -24 555 240
+rect 589 -24 601 240
+rect 543 -36 601 -24
+<< pdiffc >>
+rect -61 -24 -27 240
+rect 27 -24 61 240
+rect 115 -24 149 240
+rect 203 -24 237 240
+rect 291 -24 325 240
+rect 379 -24 413 240
+rect 467 -24 501 240
+rect 555 -24 589 240
+<< poly >>
+rect -15 252 15 278
+rect 73 252 103 278
+rect 161 252 191 278
+rect 249 252 279 278
+rect 337 252 367 278
+rect 425 252 455 278
+rect 513 252 543 278
+rect -15 -51 15 -36
+rect 73 -51 103 -36
+rect 161 -51 191 -36
+rect 249 -51 279 -36
+rect 337 -51 367 -36
+rect 425 -51 455 -36
+rect 513 -51 543 -36
+rect -15 -81 543 -51
+<< locali >>
+rect -61 240 -27 256
+rect -61 -40 -27 -24
+rect 27 240 61 256
+rect 27 -40 61 -24
+rect 115 240 149 256
+rect 115 -40 149 -24
+rect 203 240 237 256
+rect 203 -40 237 -24
+rect 291 240 325 256
+rect 291 -40 325 -24
+rect 379 240 413 256
+rect 379 -40 413 -24
+rect 467 240 501 256
+rect 467 -40 501 -24
+rect 555 240 589 256
+rect 555 -40 589 -24
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.72 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BKC9WK.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BKC9WK.ext
new file mode 100755
index 0000000..d5ebd28
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BKC9WK.ext
@@ -0,0 +1,19 @@
+timestamp 1645537996
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n14#" 363 -41 15 -14 pdif 0 0 0 0 0 0 0 0 0 0 5800 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n14#" 363 -41 -73 -14 pdif 0 0 0 0 0 0 0 0 0 0 5800 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n111#" 365 -10.9851 -33 -111 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9066 578 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n114#" 2043 171.348 -109 -114 nw 0 0 0 0 57116 960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n111#" "w_n109_n114#" 144.95
+cap "a_15_n14#" "w_n109_n114#" 41
+cap "w_n109_n114#" "a_n73_n14#" 41
+cap "a_n33_n111#" "a_15_n14#" 3.04615
+cap "a_n33_n111#" "a_n73_n14#" 3.04615
+cap "a_15_n14#" "a_n73_n14#" 40.3333
+device msubckt sky130_fd_pr__pfet_01v8 -15 -14 -14 -13 l=30 w=100 "w_n109_n114#" "a_n33_n111#" 60 0 "a_n73_n14#" 100 0 "a_15_n14#" 100 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BKC9WK.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BKC9WK.mag
new file mode 100755
index 0000000..2f9b0df
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BKC9WK.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645537996
+<< nwell >>
+rect -109 -114 109 148
+<< pmos >>
+rect -15 -14 15 86
+<< pdiff >>
+rect -73 54 -15 86
+rect -73 20 -61 54
+rect -27 20 -15 54
+rect -73 -14 -15 20
+rect 15 54 73 86
+rect 15 20 27 54
+rect 61 20 73 54
+rect 15 -14 73 20
+<< pdiffc >>
+rect -61 20 -27 54
+rect 27 20 61 54
+<< poly >>
+rect -15 86 15 112
+rect -15 -45 15 -14
+rect -33 -61 33 -45
+rect -33 -95 -17 -61
+rect 17 -95 33 -61
+rect -33 -111 33 -95
+<< polycont >>
+rect -17 -95 17 -61
+<< locali >>
+rect -61 54 -27 70
+rect -61 4 -27 20
+rect 27 54 61 70
+rect 27 4 61 20
+rect -33 -95 -17 -61
+rect 17 -95 33 -61
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.5 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BT7HXK.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BT7HXK.ext
new file mode 100755
index 0000000..d2f7ce0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BT7HXK.ext
@@ -0,0 +1,19 @@
+timestamp 1645723234
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n64#" 754 -82 15 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n64#" 754 -82 -73 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n161#" 527 -10.9851 -33 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12066 778 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n164#" 2823 236.748 -109 -164 nw 0 0 0 0 78916 1160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n161#" "w_n109_n164#" 144.95
+cap "a_15_n64#" "w_n109_n164#" 99.4716
+cap "w_n109_n164#" "a_n73_n64#" 99.4716
+cap "a_n33_n161#" "a_15_n64#" 1.53488
+cap "a_n33_n161#" "a_n73_n64#" 1.53488
+cap "a_15_n64#" "a_n73_n64#" 110.71
+device msubckt sky130_fd_pr__pfet_01v8 -15 -64 -14 -63 l=30 w=200 "w_n109_n164#" "a_n33_n161#" 60 0 "a_n73_n64#" 200 0 "a_15_n64#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BT7HXK.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BT7HXK.mag
new file mode 100755
index 0000000..0c963f8
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_BT7HXK.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645723234
+<< nwell >>
+rect -109 -164 109 198
+<< pmos >>
+rect -15 -64 15 136
+<< pdiff >>
+rect -73 124 -15 136
+rect -73 -52 -65 124
+rect -31 -52 -15 124
+rect -73 -64 -15 -52
+rect 15 124 73 136
+rect 15 -52 31 124
+rect 65 -52 73 124
+rect 15 -64 73 -52
+<< pdiffc >>
+rect -65 -52 -31 124
+rect 31 -52 65 124
+<< poly >>
+rect -15 136 15 162
+rect -15 -95 15 -64
+rect -33 -111 33 -95
+rect -33 -145 -17 -111
+rect 17 -145 33 -111
+rect -33 -161 33 -145
+<< polycont >>
+rect -17 -145 17 -111
+<< locali >>
+rect -65 124 -31 140
+rect -65 -68 -31 -52
+rect 31 124 65 140
+rect 31 -68 65 -52
+rect -33 -145 -17 -111
+rect 17 -145 33 -111
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_FYZURS.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_FYZURS.ext
new file mode 100755
index 0000000..619b6f9
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_FYZURS.ext
@@ -0,0 +1,19 @@
+timestamp 1645722298
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n236#" 1505 -164 15 -236 pdif 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n236#" 1505 -164 -73 -236 pdif 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_195#" 850 -10.9851 -33 195 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18066 1178 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n298#" 4383 367.548 -109 -298 nw 0 0 0 0 122516 1560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_195#" "w_n109_n298#" 144.95
+cap "a_15_n236#" "w_n109_n298#" 181.472
+cap "w_n109_n298#" "a_n73_n236#" 181.472
+cap "a_n33_195#" "a_15_n236#" 1.53488
+cap "a_n33_195#" "a_n73_n236#" 1.53488
+cap "a_15_n236#" "a_n73_n236#" 217.161
+device msubckt sky130_fd_pr__pfet_01v8 -15 -236 -14 -235 l=30 w=400 "w_n109_n298#" "a_n33_195#" 60 0 "a_n73_n236#" 400 0 "a_15_n236#" 400 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_FYZURS.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_FYZURS.mag
new file mode 100755
index 0000000..7661ed0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_FYZURS.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645722298
+<< nwell >>
+rect -109 -298 109 264
+<< pmos >>
+rect -15 -236 15 164
+<< pdiff >>
+rect -73 152 -15 164
+rect -73 -224 -65 152
+rect -31 -224 -15 152
+rect -73 -236 -15 -224
+rect 15 152 73 164
+rect 15 -224 31 152
+rect 65 -224 73 152
+rect 15 -236 73 -224
+<< pdiffc >>
+rect -65 -224 -31 152
+rect 31 -224 65 152
+<< poly >>
+rect -33 245 33 261
+rect -33 211 -17 245
+rect 17 211 33 245
+rect -33 195 33 211
+rect -15 164 15 195
+rect -15 -262 15 -236
+<< polycont >>
+rect -17 211 17 245
+<< locali >>
+rect -33 211 -17 245
+rect 17 211 33 245
+rect -65 152 -31 168
+rect -65 -240 -31 -224
+rect 31 152 65 168
+rect 31 -240 65 -224
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 2 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_KQRM7Z.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_KQRM7Z.ext
new file mode 100755
index 0000000..8a7de0c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_KQRM7Z.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n156#" 904 0 18 -156 pdif 0 0 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n156#" 904 0 -76 -156 pdif 0 0 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n33_115#" 512 16.9812 -33 115 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15048 858 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n218#" 3051 270.144 -112 -218 nw 0 0 0 0 90048 1252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n112_n218#" "a_n76_n156#" 17.4716
+cap "w_n112_n218#" "a_18_n156#" 17.4716
+cap "a_n76_n156#" "a_18_n156#" 239.525
+cap "a_n33_115#" "w_n112_n218#" 137.69
+cap "a_n33_115#" "a_n76_n156#" 4.42497
+cap "a_n33_115#" "a_18_n156#" 4.42497
+device msubckt sky130_fd_pr__pfet_01v8 -18 -156 -17 -155 l=36 w=240 "w_n112_n218#" "a_n33_115#" 72 0 "a_n76_n156#" 240 0 "a_18_n156#" 240 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_KQRM7Z.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_KQRM7Z.mag
new file mode 100755
index 0000000..c650ee4
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_KQRM7Z.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -112 -218 112 184
+<< nwell >>
+rect -112 -218 112 184
+<< pmos >>
+rect -18 -156 18 84
+<< pdiff >>
+rect -76 72 -18 84
+rect -76 -144 -64 72
+rect -30 -144 -18 72
+rect -76 -156 -18 -144
+rect 18 72 76 84
+rect 18 -144 30 72
+rect 64 -144 76 72
+rect 18 -156 76 -144
+<< pdiffc >>
+rect -64 -144 -30 72
+rect 30 -144 64 72
+<< poly >>
+rect -33 165 33 181
+rect -33 131 -17 165
+rect 17 131 33 165
+rect -33 115 33 131
+rect -18 84 18 115
+rect -18 -182 18 -156
+<< polycont >>
+rect -17 131 17 165
+<< locali >>
+rect -33 131 -17 165
+rect 17 131 33 165
+rect -64 72 -30 88
+rect -64 -160 -30 -144
+rect 30 72 64 88
+rect 30 -160 64 -144
+<< viali >>
+rect -17 131 17 165
+rect -64 -79 -30 7
+rect 30 -79 64 7
+<< metal1 >>
+rect -29 165 29 171
+rect -29 131 -17 165
+rect 17 131 29 165
+rect -29 125 29 131
+rect -70 7 -24 19
+rect -70 -79 -64 7
+rect -30 -79 -24 7
+rect -70 -91 -24 -79
+rect 24 7 70 19
+rect 24 -79 30 7
+rect 64 -79 70 7
+rect 24 -91 70 -79
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1.2 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP0P75.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP0P75.ext
new file mode 100755
index 0000000..6466f0a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP0P75.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n64#" 551 0 15 -64 pdif 0 0 0 0 0 0 0 0 0 0 8700 416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3944 300 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n64#" 551 0 -73 -64 pdif 0 0 0 0 0 0 0 0 0 0 8700 416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3944 300 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n161#" 446 16.0749 -33 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10566 678 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n164#" 2433 204.048 -109 -164 nw 0 0 0 0 68016 1060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n64#" "a_n73_n64#" 70.8889
+cap "w_n109_n164#" "a_n33_n161#" 134.39
+cap "a_15_n64#" "a_n33_n161#" 3.04615
+cap "a_n73_n64#" "a_n33_n161#" 3.04615
+device msubckt sky130_fd_pr__pfet_01v8 -15 -64 -14 -63 l=30 w=150 "w_n109_n164#" "a_n33_n161#" 60 0 "a_n73_n64#" 150 0 "a_15_n64#" 150 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP0P75.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP0P75.mag
new file mode 100755
index 0000000..655235a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP0P75.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -164 109 148
+<< nwell >>
+rect -109 -164 109 148
+<< pmos >>
+rect -15 -64 15 86
+<< pdiff >>
+rect -73 54 -15 86
+rect -73 -30 -61 54
+rect -27 -30 -15 54
+rect -73 -64 -15 -30
+rect 15 54 73 86
+rect 15 -30 27 54
+rect 61 -30 73 54
+rect 15 -64 73 -30
+<< pdiffc >>
+rect -61 -30 -27 54
+rect 27 -30 61 54
+<< poly >>
+rect -15 86 15 112
+rect -15 -95 15 -64
+rect -33 -111 33 -95
+rect -33 -145 -17 -111
+rect 17 -145 33 -111
+rect -33 -161 33 -145
+<< polycont >>
+rect -17 -145 17 -111
+<< locali >>
+rect -61 54 -27 70
+rect -61 -46 -27 -30
+rect 27 54 61 70
+rect 27 -46 61 -30
+rect -33 -145 -17 -111
+rect 17 -145 33 -111
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 0.5 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP1P4U.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP1P4U.ext
new file mode 100755
index 0000000..535ba05
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP1P4U.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n144#" 1054 0 15 -144 pdif 0 0 0 0 0 0 0 0 0 0 16240 676 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9792 644 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n144#" 1054 0 -73 -144 pdif 0 0 0 0 0 0 0 0 0 0 16240 676 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9792 644 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n241#" 657 16.0749 -33 -241 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14466 938 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n244#" 3447 289.068 -109 -244 nw 0 0 0 0 96356 1320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n144#" "a_n73_n144#" 153.29
+cap "w_n109_n244#" "a_n33_n241#" 134.39
+cap "w_n109_n244#" "a_15_n144#" 17.4716
+cap "a_15_n144#" "a_n33_n241#" 1.53488
+cap "w_n109_n244#" "a_n73_n144#" 17.4716
+cap "a_n73_n144#" "a_n33_n241#" 1.53488
+device msubckt sky130_fd_pr__pfet_01v8 -15 -144 -14 -143 l=30 w=280 "w_n109_n244#" "a_n33_n241#" 60 0 "a_n73_n144#" 280 0 "a_15_n144#" 280 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP1P4U.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP1P4U.mag
new file mode 100755
index 0000000..3806d17
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP1P4U.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -244 109 198
+<< nwell >>
+rect -109 -244 109 198
+<< pmos >>
+rect -15 -144 15 136
+<< pdiff >>
+rect -73 124 -15 136
+rect -73 -132 -65 124
+rect -31 -132 -15 124
+rect -73 -144 -15 -132
+rect 15 124 73 136
+rect 15 -132 31 124
+rect 65 -132 73 124
+rect 15 -144 73 -132
+<< pdiffc >>
+rect -65 -132 -31 124
+rect 31 -132 65 124
+<< poly >>
+rect -15 136 15 162
+rect -15 -175 15 -144
+rect -33 -191 33 -175
+rect -33 -225 -17 -191
+rect 17 -225 33 -191
+rect -33 -241 33 -225
+<< polycont >>
+rect -17 -225 17 -191
+<< locali >>
+rect -65 124 -31 140
+rect -65 -148 -31 -132
+rect 31 124 65 140
+rect 31 -148 65 -132
+rect -33 -225 -17 -191
+rect 17 -225 33 -191
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP3P0U.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP3P0U.ext
new file mode 100755
index 0000000..d615bfb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP3P0U.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n236#" 2256 0 15 -236 pdif 0 0 0 0 0 0 0 0 0 0 34800 1316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20672 1284 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n236#" 2256 0 -73 -236 pdif 0 0 0 0 0 0 0 0 0 0 34800 1316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20672 1284 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_395#" 1172 16.0749 -33 395 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24066 1578 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n298#" 5942 498.348 -109 -298 nw 0 0 0 0 166116 1960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n236#" "a_n73_n236#" 323.613
+cap "w_n109_n298#" "a_n33_395#" 134.39
+cap "w_n109_n298#" "a_15_n236#" 17.4716
+cap "a_15_n236#" "a_n33_395#" 1.53488
+cap "w_n109_n298#" "a_n73_n236#" 17.4716
+cap "a_n73_n236#" "a_n33_395#" 1.53488
+device msubckt sky130_fd_pr__pfet_01v8 -15 -236 -14 -235 l=30 w=600 "w_n109_n298#" "a_n33_395#" 60 0 "a_n73_n236#" 600 0 "a_15_n236#" 600 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP3P0U.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP3P0U.mag
new file mode 100755
index 0000000..91f7f03
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MP3P0U.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -298 109 464
+<< nwell >>
+rect -109 -298 109 464
+<< pmos >>
+rect -15 -236 15 364
+<< pdiff >>
+rect -73 352 -15 364
+rect -73 -224 -65 352
+rect -31 -224 -15 352
+rect -73 -236 -15 -224
+rect 15 352 73 364
+rect 15 -224 31 352
+rect 65 -224 73 352
+rect 15 -236 73 -224
+<< pdiffc >>
+rect -65 -224 -31 352
+rect 31 -224 65 352
+<< poly >>
+rect -33 445 33 461
+rect -33 411 -17 445
+rect 17 411 33 445
+rect -33 395 33 411
+rect -15 364 15 395
+rect -15 -262 15 -236
+<< polycont >>
+rect -17 411 17 445
+<< locali >>
+rect -33 411 -17 445
+rect 17 411 33 445
+rect -65 352 -31 368
+rect -65 -240 -31 -224
+rect 31 352 65 368
+rect 31 -240 65 -224
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MS69BZ.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MS69BZ.mag
new file mode 100755
index 0000000..00c63f6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_MS69BZ.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647120727
+<< error_p >>
+rect -29 130 29 136
+rect -29 96 -17 130
+rect -29 90 29 96
+rect -29 -96 29 -90
+rect -29 -130 -17 -96
+rect -29 -136 29 -130
+<< nwell >>
+rect -211 -268 211 268
+<< pmos >>
+rect -15 -49 15 49
+<< pdiff >>
+rect -73 37 -15 49
+rect -73 -37 -61 37
+rect -27 -37 -15 37
+rect -73 -49 -15 -37
+rect 15 37 73 49
+rect 15 -37 27 37
+rect 61 -37 73 37
+rect 15 -49 73 -37
+<< pdiffc >>
+rect -61 -37 -27 37
+rect 27 -37 61 37
+<< nsubdiff >>
+rect -175 198 -79 232
+rect 79 198 175 232
+rect -175 136 -141 198
+rect 141 136 175 198
+rect -175 -198 -141 -136
+rect 141 -198 175 -136
+rect -175 -232 -79 -198
+rect 79 -232 175 -198
+<< nsubdiffcont >>
+rect -79 198 79 232
+rect -175 -136 -141 136
+rect 141 -136 175 136
+rect -79 -232 79 -198
+<< poly >>
+rect -33 130 33 146
+rect -33 96 -17 130
+rect 17 96 33 130
+rect -33 80 33 96
+rect -15 49 15 80
+rect -15 -80 15 -49
+rect -33 -96 33 -80
+rect -33 -130 -17 -96
+rect 17 -130 33 -96
+rect -33 -146 33 -130
+<< polycont >>
+rect -17 96 17 130
+rect -17 -130 17 -96
+<< locali >>
+rect -175 198 -79 232
+rect 79 198 175 232
+rect -175 136 -141 198
+rect 141 136 175 198
+rect -33 96 -17 130
+rect 17 96 33 130
+rect -61 37 -27 53
+rect -61 -53 -27 -37
+rect 27 37 61 53
+rect 27 -53 61 -37
+rect -33 -130 -17 -96
+rect 17 -130 33 -96
+rect -175 -198 -141 -136
+rect 141 -198 175 -136
+rect -175 -232 -79 -198
+rect 79 -232 175 -198
+<< viali >>
+rect -17 96 17 130
+rect -61 -37 -27 37
+rect 27 -37 61 37
+rect -17 -130 17 -96
+<< metal1 >>
+rect -29 130 29 136
+rect -29 96 -17 130
+rect 17 96 29 130
+rect -29 90 29 96
+rect -67 37 -21 49
+rect -67 -37 -61 37
+rect -27 -37 -21 37
+rect -67 -49 -21 -37
+rect 21 37 67 49
+rect 21 -37 27 37
+rect 61 -37 67 37
+rect 21 -49 67 -37
+rect -29 -96 29 -90
+rect -29 -130 -17 -96
+rect 17 -130 29 -96
+rect -29 -136 29 -130
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -215 158 215
+string parameters w 0.49 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NC2CGG.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NC2CGG.ext
new file mode 100755
index 0000000..b838f58
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NC2CGG.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n240#" 1765 0 15 -240 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12716 816 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n240#" 1787 0 -73 -240 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14824 940 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n337#" 962 16.3929 -33 -337 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20586 1346 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n340#" 5303 444.72 -109 -340 nw 0 0 0 0 148240 1796 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n240#" "a_n73_n240#" 196.778
+cap "w_n109_n340#" "a_n33_n337#" 122.65
+cap "w_n109_n340#" "a_15_n240#" 8.7358
+cap "w_n109_n340#" "a_n73_n240#" 8.7358
+device msubckt sky130_fd_pr__pfet_01v8 -15 -240 -14 -239 l=30 w=480 "w_n109_n340#" "a_n33_n337#" 60 0 "a_n73_n240#" 480 0 "a_15_n240#" 480 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NC2CGG.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NC2CGG.mag
new file mode 100755
index 0000000..f018d6e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NC2CGG.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -340 109 340
+<< nwell >>
+rect -109 -340 109 340
+<< pmos >>
+rect -15 -240 15 240
+<< pdiff >>
+rect -73 228 -15 240
+rect -73 -176 -61 228
+rect -27 -176 -15 228
+rect -73 -240 -15 -176
+rect 15 114 73 240
+rect 15 -228 27 114
+rect 61 -228 73 114
+rect 15 -240 73 -228
+<< pdiffc >>
+rect -61 -176 -27 228
+rect 27 -228 61 114
+<< poly >>
+rect -15 240 15 270
+rect -15 -271 15 -240
+rect -33 -337 33 -271
+<< locali >>
+rect -61 228 -27 244
+rect -61 -192 -27 -176
+rect 27 114 61 130
+rect 27 -244 61 -228
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2.4 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NCD769.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NCD769.ext
new file mode 100755
index 0000000..49f477c
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NCD769.ext
@@ -0,0 +1,19 @@
+timestamp 1645133562
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n58#" 439 -104.96 15 -58 pdif 0 0 0 0 0 0 0 0 0 0 6728 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4216 316 2760 212 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n58#" 439 -105.37 -73 -58 pdif 0 0 0 0 0 0 0 0 0 0 6728 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4216 316 2806 214 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n155#" 564 -139.264 -33 -155 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14052 824 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+node "w_n211_n277#" 7906 673.484 -211 -277 nw 0 0 0 0 233788 1952 0 0 51952 3056 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51952 3056 11500 592 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n211_n277#" "a_15_n58#" 211.58
+cap "w_n211_n277#" "a_n73_n58#" 212.822
+cap "w_n211_n277#" "a_n33_n155#" 504.963
+cap "a_n73_n58#" "a_15_n58#" 129.349
+cap "a_n33_n155#" "a_15_n58#" 19.6441
+cap "a_n73_n58#" "a_n33_n155#" 19.9732
+device msubckt sky130_fd_pr__pfet_01v8 -15 -58 -14 -57 l=30 w=116 "w_n211_n277#" "a_n33_n155#" 60 0 "a_n73_n58#" 116 0 "a_15_n58#" 116 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NCD769.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NCD769.mag
new file mode 100755
index 0000000..c72d170
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_NCD769.mag
@@ -0,0 +1,110 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645133562
+<< error_p >>
+rect -29 139 29 145
+rect -29 105 -17 139
+rect -29 99 29 105
+rect -67 29 -21 41
+rect -67 -8 -61 29
+rect 21 18 67 30
+rect -67 -20 -21 -8
+rect 21 -18 27 18
+rect 21 -30 67 -18
+rect -29 -105 29 -99
+rect -29 -139 -17 -105
+rect -29 -145 29 -139
+<< nwell >>
+rect -211 -277 211 277
+<< pmos >>
+rect -15 -58 15 58
+<< pdiff >>
+rect -73 46 -15 58
+rect -73 -46 -61 46
+rect -27 -46 -15 46
+rect -73 -58 -15 -46
+rect 15 46 73 58
+rect 15 -46 27 46
+rect 61 -46 73 46
+rect 15 -58 73 -46
+<< pdiffc >>
+rect -61 -46 -27 46
+rect 27 -46 61 46
+<< nsubdiff >>
+rect -175 207 -79 241
+rect 79 207 175 241
+rect -175 145 -141 207
+rect -175 -207 -141 -145
+rect 141 -207 175 207
+rect -175 -241 -79 -207
+rect 79 -241 175 -207
+<< nsubdiffcont >>
+rect -79 207 79 241
+rect -175 -145 -141 145
+rect -79 -241 79 -207
+<< poly >>
+rect -33 139 33 155
+rect -33 105 -17 139
+rect 17 105 33 139
+rect -33 89 33 105
+rect -15 58 15 89
+rect -15 -89 15 -58
+rect -33 -105 33 -89
+rect -33 -139 -17 -105
+rect 17 -139 33 -105
+rect -33 -155 33 -139
+<< polycont >>
+rect -17 105 17 139
+rect -17 -139 17 -105
+<< locali >>
+rect -175 207 -113 241
+rect 113 207 175 241
+rect -175 145 -141 207
+rect -33 105 -17 139
+rect 17 105 33 139
+rect -61 46 -27 62
+rect -61 -62 -27 -46
+rect 27 46 61 62
+rect 27 -62 61 -46
+rect -33 -139 -17 -105
+rect 17 -139 33 -105
+rect -175 -207 -141 -145
+rect 141 -207 175 207
+rect -175 -241 -79 -207
+rect 79 -241 175 -207
+<< viali >>
+rect -113 207 -79 241
+rect -79 207 79 241
+rect 79 207 113 241
+rect -17 105 17 139
+rect -61 -8 -27 29
+rect 27 -18 61 18
+rect -17 -139 17 -105
+<< metal1 >>
+rect -125 241 125 247
+rect -125 207 -113 241
+rect 113 207 125 241
+rect -125 201 125 207
+rect -29 139 29 145
+rect -29 105 -17 139
+rect 17 105 29 139
+rect -29 99 29 105
+rect -67 29 -21 41
+rect -67 -8 -61 29
+rect -27 -8 -21 29
+rect -67 -20 -21 -8
+rect 21 18 67 30
+rect 21 -18 27 18
+rect 61 -18 67 18
+rect 21 -30 67 -18
+rect -29 -105 29 -99
+rect -29 -139 -17 -105
+rect 17 -139 29 -105
+rect -29 -145 29 -139
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -224 158 224
+string parameters w 0.58 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_TPJM7Z.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_TPJM7Z.ext
new file mode 100755
index 0000000..e6362cd
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_TPJM7Z.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n276#" 1806 0 18 -276 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n276#" 1806 0 -76 -276 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n33_235#" 835 16.9812 -33 235 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23688 1338 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n338#" 4872 431.424 -112 -338 nw 0 0 0 0 143808 1732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n276#" "a_n76_n276#" 461.525
+cap "w_n112_n338#" "a_n33_235#" 137.69
+cap "w_n112_n338#" "a_18_n276#" 17.4716
+cap "a_18_n276#" "a_n33_235#" 3.56637
+cap "w_n112_n338#" "a_n76_n276#" 17.4716
+cap "a_n76_n276#" "a_n33_235#" 3.56637
+device msubckt sky130_fd_pr__pfet_01v8 -18 -276 -17 -275 l=36 w=480 "w_n112_n338#" "a_n33_235#" 72 0 "a_n76_n276#" 480 0 "a_18_n276#" 480 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_TPJM7Z.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_TPJM7Z.mag
new file mode 100755
index 0000000..aebde7e
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_TPJM7Z.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -112 -338 112 304
+<< nwell >>
+rect -112 -338 112 304
+<< pmos >>
+rect -18 -276 18 204
+<< pdiff >>
+rect -76 192 -18 204
+rect -76 -264 -64 192
+rect -30 -264 -18 192
+rect -76 -276 -18 -264
+rect 18 192 76 204
+rect 18 -264 30 192
+rect 64 -264 76 192
+rect 18 -276 76 -264
+<< pdiffc >>
+rect -64 -264 -30 192
+rect 30 -264 64 192
+<< poly >>
+rect -33 285 33 301
+rect -33 251 -17 285
+rect 17 251 33 285
+rect -33 235 33 251
+rect -18 204 18 235
+rect -18 -302 18 -276
+<< polycont >>
+rect -17 251 17 285
+<< locali >>
+rect -33 251 -17 285
+rect 17 251 33 285
+rect -64 192 -30 208
+rect -64 -280 -30 -264
+rect 30 192 64 208
+rect 30 -280 64 -264
+<< viali >>
+rect -17 251 17 285
+rect -64 -127 -30 55
+rect 30 -127 64 55
+<< metal1 >>
+rect -29 285 29 291
+rect -29 251 -17 285
+rect 17 251 29 285
+rect -29 245 29 251
+rect -70 55 -24 67
+rect -70 -127 -64 55
+rect -30 -127 -24 55
+rect -70 -139 -24 -127
+rect 24 55 70 67
+rect 24 -127 30 55
+rect 64 -127 70 55
+rect 24 -139 70 -127
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2.4 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_UUCHZP.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_UUCHZP.ext
new file mode 100755
index 0000000..7f6f326
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_UUCHZP.ext
@@ -0,0 +1,41 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_114_n220#" 1630 0 114 -220 pdif 0 0 0 0 0 0 0 0 0 0 25960 998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_18_n220#" 1606 0 18 -220 pdif 0 0 0 0 0 0 0 0 0 0 26400 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 6854 390 0 0 0 0 0 0 0 0 0 0
+node "a_n78_n220#" 1605 0 -78 -220 pdif 0 0 0 0 0 0 0 0 0 0 26400 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n173_n220#" 1630 0 -173 -220 pdif 0 0 0 0 0 0 0 0 0 0 25960 998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 6854 390 0 0 0 0 0 0 0 0 0 0
+node "a_63_n366#" 847 77.4058 63 -366 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24012 1356 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n366#" 847 77.4058 -129 -366 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24012 1356 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_310#" 861 85.4998 -33 310 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24372 1376 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n209_n320#" 2924 780.672 -209 -320 nw 0 0 0 0 260224 2116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n78_n220#" "a_n129_n366#" 0.717391
+cap "a_n33_310#" "a_n78_n220#" 0.647059
+cap "a_n173_n220#" "w_n209_n320#" 17.4716
+cap "a_n173_n220#" "a_114_n220#" 58.2047
+cap "a_n173_n220#" "a_18_n220#" 139.494
+cap "a_114_n220#" "w_n209_n320#" 17.4716
+cap "a_n173_n220#" "a_n129_n366#" 0.717391
+cap "w_n209_n320#" "a_18_n220#" 17.4716
+cap "w_n209_n320#" "a_n129_n366#" 108.89
+cap "a_63_n366#" "w_n209_n320#" 108.89
+cap "a_n33_310#" "w_n209_n320#" 107.25
+cap "a_n173_n220#" "a_n78_n220#" 238.452
+cap "w_n209_n320#" "a_n78_n220#" 17.4716
+cap "a_114_n220#" "a_18_n220#" 238.452
+cap "a_63_n366#" "a_114_n220#" 0.717391
+cap "a_63_n366#" "a_18_n220#" 0.717391
+cap "a_n33_310#" "a_18_n220#" 0.647059
+cap "a_63_n366#" "a_n129_n366#" 36.5806
+cap "a_114_n220#" "a_n78_n220#" 93.5696
+cap "a_n33_310#" "a_n129_n366#" 19.9333
+cap "a_63_n366#" "a_n33_310#" 19.9333
+cap "a_n78_n220#" "a_18_n220#" 238.452
+device msubckt sky130_fd_pr__pfet_01v8 78 -220 79 -219 l=36 w=440 "w_n209_n320#" "a_63_n366#" 72 0 "a_18_n220#" 440 0 "a_114_n220#" 440 0
+device msubckt sky130_fd_pr__pfet_01v8 -18 -220 -17 -219 l=36 w=440 "w_n209_n320#" "a_n33_310#" 72 0 "a_n78_n220#" 440 0 "a_18_n220#" 440 0
+device msubckt sky130_fd_pr__pfet_01v8 -114 -220 -113 -219 l=36 w=440 "w_n209_n320#" "a_n129_n366#" 72 0 "a_n173_n220#" 440 0 "a_n78_n220#" 440 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_UUCHZP.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_UUCHZP.mag
new file mode 100755
index 0000000..c41fbc8
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_UUCHZP.mag
@@ -0,0 +1,91 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -113 282 113 320
+rect -209 -320 209 282
+<< nwell >>
+rect -113 282 113 320
+rect -209 -320 209 282
+<< pmos >>
+rect -114 -220 -78 220
+rect -18 -220 18 220
+rect 78 -220 114 220
+<< pdiff >>
+rect -173 208 -114 220
+rect -173 -208 -161 208
+rect -127 -208 -114 208
+rect -173 -220 -114 -208
+rect -78 208 -18 220
+rect -78 -208 -65 208
+rect -31 -208 -18 208
+rect -78 -220 -18 -208
+rect 18 208 78 220
+rect 18 -208 31 208
+rect 65 -208 78 208
+rect 18 -220 78 -208
+rect 114 208 173 220
+rect 114 -208 127 208
+rect 161 -208 173 208
+rect 114 -220 173 -208
+<< pdiffc >>
+rect -161 -208 -127 208
+rect -65 -208 -31 208
+rect 31 -208 65 208
+rect 127 -208 161 208
+<< poly >>
+rect -33 360 33 376
+rect -33 326 -17 360
+rect 17 326 33 360
+rect -33 310 33 326
+rect -114 220 -78 246
+rect -18 220 18 310
+rect 78 220 114 246
+rect -114 -300 -78 -220
+rect -18 -246 18 -220
+rect 78 -300 114 -220
+rect -129 -316 -63 -300
+rect -129 -350 -113 -316
+rect -79 -350 -63 -316
+rect -129 -366 -63 -350
+rect 63 -316 129 -300
+rect 63 -350 79 -316
+rect 113 -350 129 -316
+rect 63 -366 129 -350
+<< polycont >>
+rect -17 326 17 360
+rect -113 -350 -79 -316
+rect 79 -350 113 -316
+<< locali >>
+rect -33 326 -17 360
+rect 17 326 33 360
+rect -161 208 -127 224
+rect -161 -224 -127 -208
+rect -65 208 -31 224
+rect -65 -224 -31 -208
+rect 31 208 65 224
+rect 31 -224 65 -208
+rect 127 208 161 224
+rect 127 -224 161 -208
+rect -129 -350 -113 -316
+rect -79 -350 -63 -316
+rect 63 -350 79 -316
+rect 113 -350 129 -316
+<< viali >>
+rect -161 66 -127 191
+rect 31 66 65 191
+<< metal1 >>
+rect -167 191 -121 203
+rect -167 66 -161 191
+rect -127 66 -121 191
+rect -167 54 -121 66
+rect 25 191 71 203
+rect 25 66 31 191
+rect 65 66 71 191
+rect 25 54 71 66
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2.1999999999999997 l 0.18 m 1 nf 3 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 60 viadrn -30 viagate 100 viagb 0 viagr 0 viagl 0 viagt 100
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_V5LP55.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_V5LP55.ext
new file mode 100755
index 0000000..01ae33a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_V5LP55.ext
@@ -0,0 +1,19 @@
+timestamp 1645134758
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n240#" 1806 -314.06 15 -240 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n240#" 1806 -314.06 -73 -240 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n337#" 1147 -139.264 -33 -337 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24972 1552 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+node "w_n211_n459#" 12204 1134.31 -211 -459 nw 0 0 0 0 387396 2680 0 0 76704 4512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76704 4512 11500 592 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n211_n459#" "a_n33_n337#" 482.302
+cap "a_n73_n240#" "a_15_n240#" 518.937
+cap "w_n211_n459#" "a_15_n240#" 637.617
+cap "w_n211_n459#" "a_n73_n240#" 637.617
+cap "a_n33_n337#" "a_15_n240#" 13.2542
+cap "a_n33_n337#" "a_n73_n240#" 13.2542
+device msubckt sky130_fd_pr__pfet_01v8 -15 -240 -14 -239 l=30 w=480 "w_n211_n459#" "a_n33_n337#" 60 0 "a_n73_n240#" 480 0 "a_15_n240#" 480 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_V5LP55.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_V5LP55.mag
new file mode 100755
index 0000000..60cd3dc
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_V5LP55.mag
@@ -0,0 +1,104 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645134758
+<< error_p >>
+rect -29 321 29 327
+rect -29 287 -17 321
+rect -29 281 29 287
+rect -29 -287 29 -281
+rect -29 -321 -17 -287
+rect -29 -327 29 -321
+<< nwell >>
+rect -211 -459 211 459
+<< pmos >>
+rect -15 -240 15 240
+<< pdiff >>
+rect -73 228 -15 240
+rect -73 -228 -61 228
+rect -27 -228 -15 228
+rect -73 -240 -15 -228
+rect 15 228 73 240
+rect 15 -228 27 228
+rect 61 -228 73 228
+rect 15 -240 73 -228
+<< pdiffc >>
+rect -61 -228 -27 228
+rect 27 -228 61 228
+<< nsubdiff >>
+rect -175 389 -79 423
+rect 79 389 175 423
+rect -175 327 -141 389
+rect -175 -389 -141 -327
+rect 141 -389 175 389
+rect -175 -423 -79 -389
+rect 79 -423 175 -389
+<< nsubdiffcont >>
+rect -79 389 79 423
+rect -175 -327 -141 327
+rect -79 -423 79 -389
+<< poly >>
+rect -33 321 33 337
+rect -33 287 -17 321
+rect 17 287 33 321
+rect -33 271 33 287
+rect -15 240 15 271
+rect -15 -271 15 -240
+rect -33 -287 33 -271
+rect -33 -321 -17 -287
+rect 17 -321 33 -287
+rect -33 -337 33 -321
+<< polycont >>
+rect -17 287 17 321
+rect -17 -321 17 -287
+<< locali >>
+rect -175 389 -113 423
+rect 113 389 175 423
+rect -175 327 -141 389
+rect -33 287 -17 321
+rect 17 287 33 321
+rect -61 228 -27 244
+rect -61 -244 -27 -228
+rect 27 228 61 244
+rect 27 -244 61 -228
+rect -33 -321 -17 -287
+rect 17 -321 33 -287
+rect -175 -389 -141 -327
+rect 141 -389 175 389
+rect -175 -423 -79 -389
+rect 79 -423 175 -389
+<< viali >>
+rect -113 389 -79 423
+rect -79 389 79 423
+rect 79 389 113 423
+rect -17 287 17 321
+rect -61 -91 -27 91
+rect 27 -91 61 91
+rect -17 -321 17 -287
+<< metal1 >>
+rect -125 423 125 429
+rect -125 389 -113 423
+rect 113 389 125 423
+rect -125 383 125 389
+rect -29 321 29 327
+rect -29 287 -17 321
+rect 17 287 29 321
+rect -29 281 29 287
+rect -67 91 -21 103
+rect -67 -91 -61 91
+rect -27 -91 -21 91
+rect -67 -103 -21 -91
+rect 21 91 67 103
+rect 21 -91 27 91
+rect 61 -91 67 91
+rect 21 -103 67 -91
+rect -29 -287 29 -281
+rect -29 -321 -17 -287
+rect 17 -321 29 -287
+rect -29 -327 29 -321
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -406 158 406
+string parameters w 2.4 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_VP7S29.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_VP7S29.mag
new file mode 100755
index 0000000..c9c02b0
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_VP7S29.mag
@@ -0,0 +1,77 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646335198
+<< error_p >>
+rect -29 153 29 159
+rect -29 119 -17 153
+rect -29 113 29 119
+rect -29 -119 29 -113
+rect -29 -153 -17 -119
+rect -29 -159 29 -153
+<< nwell >>
+rect -112 -172 112 172
+<< pmos >>
+rect -18 -72 18 72
+<< pdiff >>
+rect -76 60 -18 72
+rect -76 -60 -64 60
+rect -30 -60 -18 60
+rect -76 -72 -18 -60
+rect 18 60 76 72
+rect 18 -60 30 60
+rect 64 -60 76 60
+rect 18 -72 76 -60
+<< pdiffc >>
+rect -64 -60 -30 60
+rect 30 -60 64 60
+<< poly >>
+rect -33 153 33 169
+rect -33 119 -17 153
+rect 17 119 33 153
+rect -33 103 33 119
+rect -18 72 18 103
+rect -18 -103 18 -72
+rect -33 -119 33 -103
+rect -33 -153 -17 -119
+rect 17 -153 33 -119
+rect -33 -169 33 -153
+<< polycont >>
+rect -17 119 17 153
+rect -17 -153 17 -119
+<< locali >>
+rect -33 119 -17 153
+rect 17 119 33 153
+rect -64 60 -30 76
+rect -64 -76 -30 -60
+rect 30 60 64 76
+rect 30 -76 64 -60
+rect -33 -153 -17 -119
+rect 17 -153 33 -119
+<< viali >>
+rect -17 119 17 153
+rect -64 -60 -30 60
+rect 30 -60 64 60
+rect -17 -153 17 -119
+<< metal1 >>
+rect -29 153 29 159
+rect -29 119 -17 153
+rect 17 119 29 153
+rect -29 113 29 119
+rect -70 60 -24 72
+rect -70 -60 -64 60
+rect -30 -60 -24 60
+rect -70 -72 -24 -60
+rect 24 60 70 72
+rect 24 -60 30 60
+rect 64 -60 70 60
+rect 24 -72 70 -60
+rect -29 -119 29 -113
+rect -29 -153 -17 -119
+rect 17 -153 29 -119
+rect -29 -159 29 -153
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 0.72 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_X4438S.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_X4438S.mag
new file mode 100755
index 0000000..b54dd10
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_X4438S.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646335097
+<< error_p >>
+rect -29 153 29 159
+rect -29 119 -17 153
+rect -29 113 29 119
+rect -29 -119 29 -113
+rect -29 -153 -17 -119
+rect -29 -159 29 -153
+<< nwell >>
+rect -214 -291 214 291
+<< pmos >>
+rect -18 -72 18 72
+<< pdiff >>
+rect -76 60 -18 72
+rect -76 -60 -64 60
+rect -30 -60 -18 60
+rect -76 -72 -18 -60
+rect 18 60 76 72
+rect 18 -60 30 60
+rect 64 -60 76 60
+rect 18 -72 76 -60
+<< pdiffc >>
+rect -64 -60 -30 60
+rect 30 -60 64 60
+<< nsubdiff >>
+rect -178 221 -82 255
+rect 82 221 178 255
+rect -178 159 -144 221
+rect 144 159 178 221
+rect -178 -221 -144 -159
+rect 144 -221 178 -159
+rect -178 -255 -82 -221
+rect 82 -255 178 -221
+<< nsubdiffcont >>
+rect -82 221 82 255
+rect -178 -159 -144 159
+rect 144 -159 178 159
+rect -82 -255 82 -221
+<< poly >>
+rect -33 153 33 169
+rect -33 119 -17 153
+rect 17 119 33 153
+rect -33 103 33 119
+rect -18 72 18 103
+rect -18 -103 18 -72
+rect -33 -119 33 -103
+rect -33 -153 -17 -119
+rect 17 -153 33 -119
+rect -33 -169 33 -153
+<< polycont >>
+rect -17 119 17 153
+rect -17 -153 17 -119
+<< locali >>
+rect -178 221 -82 255
+rect 82 221 178 255
+rect -178 159 -144 221
+rect 144 159 178 221
+rect -33 119 -17 153
+rect 17 119 33 153
+rect -64 60 -30 76
+rect -64 -76 -30 -60
+rect 30 60 64 76
+rect 30 -76 64 -60
+rect -33 -153 -17 -119
+rect 17 -153 33 -119
+rect -178 -221 -144 -159
+rect 144 -221 178 -159
+rect -178 -255 -82 -221
+rect 82 -255 178 -221
+<< viali >>
+rect -17 119 17 153
+rect -64 -60 -30 60
+rect 30 -60 64 60
+rect -17 -153 17 -119
+<< metal1 >>
+rect -29 153 29 159
+rect -29 119 -17 153
+rect 17 119 29 153
+rect -29 113 29 119
+rect -70 60 -24 72
+rect -70 -60 -64 60
+rect -30 -60 -24 60
+rect -70 -72 -24 -60
+rect 24 60 70 72
+rect 24 -60 30 60
+rect 64 -60 70 60
+rect 24 -72 70 -60
+rect -29 -119 29 -113
+rect -29 -153 -17 -119
+rect 17 -153 29 -119
+rect -29 -159 29 -153
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -161 -238 161 238
+string parameters w 0.72 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_XZZ25Z.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_XZZ25Z.ext
new file mode 100755
index 0000000..d3a8a30
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_XZZ25Z.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n136#" 754 0 18 -136 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n136#" 754 0 -76 -136 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n33_95#" 458 16.9812 -33 95 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13608 778 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n198#" 2747 243.264 -112 -198 nw 0 0 0 0 81088 1172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n112_n198#" "a_n76_n136#" 17.4716
+cap "a_18_n136#" "w_n112_n198#" 17.4716
+cap "a_n33_95#" "w_n112_n198#" 137.69
+cap "a_18_n136#" "a_n76_n136#" 202.525
+cap "a_n33_95#" "a_n76_n136#" 4.69594
+cap "a_18_n136#" "a_n33_95#" 4.69594
+device msubckt sky130_fd_pr__pfet_01v8 -18 -136 -17 -135 l=36 w=200 "w_n112_n198#" "a_n33_95#" 72 0 "a_n76_n136#" 200 0 "a_18_n136#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_XZZ25Z.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_XZZ25Z.mag
new file mode 100755
index 0000000..e708850
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_XZZ25Z.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -112 -198 112 164
+<< nwell >>
+rect -112 -198 112 164
+<< pmos >>
+rect -18 -136 18 64
+<< pdiff >>
+rect -76 52 -18 64
+rect -76 -124 -64 52
+rect -30 -124 -18 52
+rect -76 -136 -18 -124
+rect 18 52 76 64
+rect 18 -124 30 52
+rect 64 -124 76 52
+rect 18 -136 76 -124
+<< pdiffc >>
+rect -64 -124 -30 52
+rect 30 -124 64 52
+<< poly >>
+rect -33 145 33 161
+rect -33 111 -17 145
+rect 17 111 33 145
+rect -33 95 33 111
+rect -18 64 18 95
+rect -18 -162 18 -136
+<< polycont >>
+rect -17 111 17 145
+<< locali >>
+rect -33 111 -17 145
+rect 17 111 33 145
+rect -64 52 -30 68
+rect -64 -140 -30 -124
+rect 30 52 64 68
+rect 30 -140 64 -124
+<< viali >>
+rect -17 111 17 145
+rect -64 -71 -30 -1
+rect 30 -71 64 -1
+<< metal1 >>
+rect -29 145 29 151
+rect -29 111 -17 145
+rect 17 111 29 145
+rect -29 105 29 111
+rect -70 -1 -24 11
+rect -70 -71 -64 -1
+rect -30 -71 -24 -1
+rect -70 -83 -24 -71
+rect 24 -1 70 11
+rect 24 -71 30 -1
+rect 64 -71 70 -1
+rect 24 -83 70 -71
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.18 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 40 viadrn 40 viagate 100 viagb 0 viagr 0 viagl 0 viagt 80
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_BZS9EC.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_BZS9EC.ext
new file mode 100755
index 0000000..80d61a6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_BZS9EC.ext
@@ -0,0 +1,18 @@
+timestamp 1646398638
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n64#" 754 -177.94 15 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n64#" 754 -177.94 -73 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n54_n161#" 527 -74.0104 -54 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12264 784 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n164#" 2823 236.748 -109 -164 nw 0 0 0 0 78916 1160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n64#" "a_n73_n64#" 341.397
+cap "w_n109_n164#" "a_15_n64#" 200.332
+cap "a_n54_n161#" "a_n73_n64#" 52.5502
+cap "w_n109_n164#" "a_n54_n161#" 189.24
+cap "w_n109_n164#" "a_n73_n64#" 200.332
+device msubckt sky130_fd_pr__pfet_01v8_hvt -15 -64 -14 -63 l=30 w=200 "w_n109_n164#" "a_n54_n161#" 60 0 "a_n73_n64#" 200 0 "a_15_n64#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_BZS9EC.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_BZS9EC.mag
new file mode 100755
index 0000000..8ee0548
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_BZS9EC.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646398638
+<< error_p >>
+rect -50 -111 8 -105
+rect -50 -145 -38 -111
+rect -50 -151 8 -145
+<< nwell >>
+rect -109 -164 109 198
+<< pmoshvt >>
+rect -15 -64 15 136
+<< pdiff >>
+rect -73 124 -15 136
+rect -73 -52 -61 124
+rect -27 -52 -15 124
+rect -73 -64 -15 -52
+rect 15 124 73 136
+rect 15 -52 27 124
+rect 61 -52 73 124
+rect 15 -64 73 -52
+<< pdiffc >>
+rect -61 -52 -27 124
+rect 27 -52 61 124
+<< poly >>
+rect -15 136 15 162
+rect -15 -95 15 -64
+rect -54 -111 15 -95
+rect -54 -145 -38 -111
+rect -4 -145 15 -111
+rect -54 -161 15 -145
+<< polycont >>
+rect -38 -145 -4 -111
+<< locali >>
+rect -61 124 -27 140
+rect -61 -68 -27 -52
+rect 27 124 61 140
+rect 27 -68 61 -52
+rect -54 -145 -38 -111
+rect -4 -145 12 -111
+<< viali >>
+rect -61 -52 -27 124
+rect 27 -52 61 124
+rect -38 -145 -4 -111
+<< metal1 >>
+rect -67 124 -21 136
+rect -67 -52 -61 124
+rect -27 -52 -21 124
+rect -67 -64 -21 -52
+rect 21 124 67 136
+rect 21 -52 27 124
+rect 61 -52 67 124
+rect 21 -64 67 -52
+rect -50 -111 8 -105
+rect -50 -145 -38 -111
+rect -4 -145 8 -111
+rect -50 -151 8 -145
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8_hvt
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_N83GLL.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_N83GLL.ext
new file mode 100755
index 0000000..72894e6
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_N83GLL.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 754 0 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 754 0 -73 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n132#" 415 4.611 -15 -132 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7740 576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n136#" 2324 194.892 -109 -136 nw 0 0 0 0 64964 1032 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n100#" "a_n73_n100#" 127.111
+cap "w_n109_n136#" "a_n15_n132#" 64.9
+cap "w_n109_n136#" "a_15_n100#" 17.4716
+cap "w_n109_n136#" "a_n73_n100#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8_hvt -15 -100 -14 -99 l=30 w=200 "w_n109_n136#" "a_n15_n132#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_N83GLL.mag b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_N83GLL.mag
new file mode 100755
index 0000000..d17f088
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_pr__pfet_01v8_hvt_N83GLL.mag
@@ -0,0 +1,35 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< error_p >>
+rect -109 -136 109 162
+<< nwell >>
+rect -109 -136 109 162
+<< pmoshvt >>
+rect -15 -100 15 100
+<< pdiff >>
+rect -73 88 -15 100
+rect -73 -88 -61 88
+rect -27 -88 -15 88
+rect -73 -100 -15 -88
+rect 15 88 73 100
+rect 15 -88 27 88
+rect 61 -88 73 88
+rect 15 -100 73 -88
+<< pdiffc >>
+rect -61 -88 -27 88
+rect 27 -88 61 88
+<< poly >>
+rect -15 100 15 126
+rect -15 -132 15 -100
+<< locali >>
+rect -61 88 -27 104
+rect -61 -104 -27 -88
+rect 27 88 61 104
+rect 27 -104 61 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8_hvt
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 0 viadrn 0 viagate 0 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_16.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_16.ext
new file mode 100644
index 0000000..1e9b656
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_16.ext
@@ -0,0 +1,86 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 1840 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 1685 153 1719 187 li
+port "X" 6 1593 153 1627 187 li
+port "X" 6 1593 221 1627 255 li
+port "X" 6 1685 221 1719 255 li
+port "X" 6 1685 289 1719 323 li
+port "X" 6 1593 289 1627 323 li
+port "VPWR" 5 0 496 1840 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 29 221 63 255 li
+port "A" 1 29 153 63 187 li
+port "VPB" 4 46 544 46 544 nw
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 46 0 46 0 pw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_16" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 6141 1371.06 29 -17 m1 0 0 0 0 0 0 0 0 51156 3066 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119810 5922 176640 3872 0 0 0 0 0 0 0 0 0 0
+node "X" 13624 358.952 1593 289 li 0 0 0 0 0 0 0 0 37632 2240 89600 4096 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 236801 9112 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 13355 393.26 29 527 m1 0 0 0 0 0 0 0 0 0 0 121800 5618 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 149441 7044 176640 3872 0 0 0 0 0 0 0 0 0 0
+node "a_110_47#" 13806 1916.4 110 47 ndif 0 0 0 0 0 0 0 0 9408 560 22400 1024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 303885 16452 0 0 109922 4506 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 2351 538.585 29 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83394 4098 0 0 7056 350 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 10147 1845.11 29 527 nw 0 0 0 0 615036 4474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "A" "VPWR" 89.8988
+cap "VGND" "VPWR" 72.4031
+cap "VPWR" "VPB" 1000.66
+cap "A" "X" 2.45745
+cap "VGND" "X" 2233
+cap "A" "a_110_47#" 544.488
+cap "X" "VPB" 31.1615
+cap "a_110_47#" "VGND" 990.729
+cap "X" "VPWR" 3419.81
+cap "a_110_47#" "VPB" 1313.11
+cap "a_110_47#" "VPWR" 1186.85
+cap "A" "VGND" 129.616
+cap "a_110_47#" "X" 3326.02
+cap "A" "VPB" 264.83
+device msubckt sky130_fd_pr__nfet_01v8 1713 47 1714 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1627 47 1628 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1541 47 1542 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1455 47 1456 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1369 47 1370 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1283 47 1284 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1197 47 1198 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1111 47 1112 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1026 47 1027 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 940 47 941 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 854 47 855 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 768 47 769 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 682 47 683 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 596 47 597 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 510 47 511 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 424 47 425 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 338 47 339 48 l=30 w=84 "VNB" "A" 60 0 "a_110_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 252 47 253 48 l=30 w=84 "VNB" "A" 60 0 "VGND" 84 0 "a_110_47#" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 166 47 167 48 l=30 w=84 "VNB" "A" 60 0 "a_110_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "VGND" 84 0 "a_110_47#" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1713 297 1714 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1627 297 1628 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1541 297 1542 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1455 297 1456 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1369 297 1370 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1283 297 1284 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1197 297 1198 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1111 297 1112 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1026 297 1027 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 940 297 941 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 854 297 855 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 768 297 769 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 682 297 683 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 596 297 597 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 510 297 511 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 424 297 425 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 338 297 339 298 l=30 w=200 "VPB" "A" 60 0 "a_110_47#" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 252 297 253 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "a_110_47#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 166 297 167 298 l=30 w=200 "VPB" "A" 60 0 "a_110_47#" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "a_110_47#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_2.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_2.ext
new file mode 100644
index 0000000..b2f5331
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_2.ext
@@ -0,0 +1,50 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 368 48 m1
+port "VGND" 2 46 0 46 0 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 305 357 339 391 li
+port "X" 6 305 289 339 323 li
+port "X" 6 305 153 339 187 li
+port "X" 6 305 221 339 255 li
+port "VPWR" 5 0 496 368 592 m1
+port "VPWR" 5 46 544 46 544 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 121 221 155 255 li
+port "A" 1 121 153 155 187 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_2" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 883 321.253 29 -17 m1 0 0 0 0 0 0 0 0 9828 570 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23152 1156 35328 928 0 0 0 0 0 0 0 0 0 0
+node "X" 1059 38.7431 305 221 li 0 0 0 0 0 0 0 0 4536 276 10800 508 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29598 1276 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 1987 81.932 29 527 m1 0 0 0 0 0 0 0 0 0 0 23400 1034 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28503 1286 35328 928 0 0 0 0 0 0 0 0 0 0
+node "a_27_47#" 2319 304.193 27 47 ndif 0 0 0 0 0 0 0 0 4452 274 10600 506 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37140 1976 0 0 30620 1560 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 766 181.455 121 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18261 1132 0 0 8352 376 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 2351 427.572 29 527 nw 0 0 0 0 142524 1530 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "X" "a_27_47#" 425.353
+cap "X" "VGND" 230.998
+cap "a_27_47#" "VGND" 203.464
+cap "X" "A" 37.8529
+cap "X" "VPB" 32.8131
+cap "X" "VPWR" 266.971
+cap "a_27_47#" "A" 370.873
+cap "a_27_47#" "VPB" 185.622
+cap "a_27_47#" "VPWR" 337.736
+cap "VGND" "A" 66.1479
+cap "VGND" "VPWR" 14.469
+cap "A" "VPB" 74.0288
+cap "A" "VPWR" 78.9081
+cap "VPWR" "VPB" 232.858
+device msubckt sky130_fd_pr__nfet_01v8 259 47 260 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 175 47 176 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "a_27_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 259 297 260 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 175 297 176 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "a_27_47#" 200 0 "VPWR" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_4.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_4.ext
new file mode 100644
index 0000000..b5caccf
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_4.ext
@@ -0,0 +1,51 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 552 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 489 221 523 255 li
+port "X" 6 489 153 523 187 li
+port "X" 6 397 289 431 323 li
+port "VPWR" 5 0 496 552 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 121 221 155 255 li
+port "A" 1 121 153 155 187 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_4" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 1475 459.565 29 -17 m1 0 0 0 0 0 0 0 0 15204 866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34320 1748 52992 1296 0 0 0 0 0 0 0 0 0 0
+node "X" 2919 108.035 397 289 li 0 0 0 0 0 0 0 0 9408 560 22400 1024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53058 2332 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 3167 120.848 29 527 m1 0 0 0 0 0 0 0 0 0 0 36400 1564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43298 2024 52992 1296 0 0 0 0 0 0 0 0 0 0
+node "a_27_47#" 4266 615.301 27 47 ndif 0 0 0 0 0 0 0 0 4452 274 10600 506 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69507 4264 0 0 36524 1904 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 814 176.642 121 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17040 1124 0 0 7980 368 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 3326 604.764 29 527 nw 0 0 0 0 201588 1898 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_27_47#" "VPB" 303.281
+cap "VPWR" "VGND" 20.7593
+cap "a_27_47#" "VPWR" 413.347
+cap "a_27_47#" "VGND" 279.339
+cap "A" "X" 30.4287
+cap "A" "VPB" 77.2412
+cap "VPB" "X" 29.9537
+cap "A" "VPWR" 34.5962
+cap "A" "VGND" 62.0948
+cap "a_27_47#" "A" 381.986
+cap "VPWR" "X" 712.669
+cap "X" "VGND" 433.51
+cap "VPB" "VPWR" 352.927
+cap "a_27_47#" "X" 659.675
+device msubckt sky130_fd_pr__nfet_01v8 435 47 436 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 349 47 350 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 263 47 264 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 177 47 178 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "a_27_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 434 297 435 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 348 297 349 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 262 297 263 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 176 297 177 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "a_27_47#" 200 0 "VPWR" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_8.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_8.ext
new file mode 100644
index 0000000..984c579
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__clkbuf_8.ext
@@ -0,0 +1,64 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 1012 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 857 221 891 255 li
+port "X" 6 765 221 799 255 li
+port "X" 6 857 289 891 323 li
+port "X" 6 857 153 891 187 li
+port "X" 6 765 153 799 187 li
+port "X" 6 765 289 799 323 li
+port "VPWR" 5 0 496 1012 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 29 221 63 255 li
+port "A" 1 29 153 63 187 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_8" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 3237 788.777 29 -17 m1 0 0 0 0 0 0 0 0 27804 1670 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65112 3254 97152 2216 0 0 0 0 0 0 0 0 0 0
+node "X" 6434 196.116 765 289 li 0 0 0 0 0 0 0 0 18816 1120 44800 2048 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126264 4548 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 7144 218.138 29 527 m1 0 0 0 0 0 0 0 0 0 0 66000 3060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90440 4148 97152 2216 0 0 0 0 0 0 0 0 0 0
+node "a_110_47#" 6496 971.627 110 47 ndif 0 0 0 0 0 0 0 0 4704 280 11200 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 149880 8246 0 0 49650 2086 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 1261 313.482 29 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41850 2154 0 0 7686 370 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 5762 1047.74 29 527 nw 0 0 0 0 349248 2818 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VPB" "X" 30.647
+cap "A" "a_110_47#" 386.172
+cap "VPWR" "a_110_47#" 702.148
+cap "VGND" "a_110_47#" 449.413
+cap "VPB" "a_110_47#" 640.361
+cap "VPWR" "A" 84.1413
+cap "A" "VGND" 86.188
+cap "VPWR" "VGND" 45.2468
+cap "A" "VPB" 139.43
+cap "a_110_47#" "X" 1396.49
+cap "VPWR" "VPB" 620.47
+cap "A" "X" 6.49812
+cap "VPWR" "X" 1768.14
+cap "VGND" "X" 1096.83
+device msubckt sky130_fd_pr__nfet_01v8 854 47 855 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 768 47 769 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 682 47 683 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 596 47 597 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 510 47 511 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 424 47 425 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 338 47 339 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 252 47 253 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 166 47 167 48 l=30 w=84 "VNB" "A" 60 0 "a_110_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "VGND" 84 0 "a_110_47#" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 854 297 855 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 768 297 769 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 682 297 683 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 596 297 597 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 510 297 511 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 424 297 425 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 338 297 339 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 252 297 253 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 166 297 167 298 l=30 w=200 "VPB" "A" 60 0 "a_110_47#" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "a_110_47#" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__inv_1.ext b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__inv_1.ext
new file mode 100755
index 0000000..96f9e8a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/sky130_fd_sc_hd__inv_1.ext
@@ -0,0 +1,35 @@
+timestamp 1642674852
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 276 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "Y" 6 164 221 198 255 li
+port "Y" 6 164 289 198 323 li
+port "VPWR" 5 0 496 276 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 72 221 106 255 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "inv_1" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 437 366.072 29 -17 m1 0 0 0 0 0 0 0 0 6760 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16928 948 26496 744 0 0 0 0 0 0 0 0 0 0
+node "Y" 1159 56.9866 164 289 li 0 0 0 0 0 0 0 0 6760 364 10400 504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26772 1056 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 919 -22.806 29 527 m1 0 0 0 0 0 0 0 0 0 0 10400 504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18960 1076 26496 744 0 0 0 0 0 0 0 0 0 0
+node "A" 806 147.108 72 221 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18756 1176 0 0 3168 228 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 1864 338.976 29 527 nw 0 0 0 0 112992 1346 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 35092 838 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VGND" "VPWR" 12.1273
+cap "VGND" "Y" 201.848
+cap "VPWR" "A" 56.4312
+cap "Y" "A" 141.088
+cap "VPWR" "VPB" 330.181
+cap "Y" "VPB" 115.732
+cap "VGND" "A" 62.9116
+cap "A" "VPB" 72.1
+cap "VPWR" "Y" 264.932
+device msubckt sky130_fd_pr__nfet_01v8 120 47 121 48 l=30 w=130 "VNB" "A" 60 0 "VGND" 130 0 "Y" 130 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 120 297 121 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "Y" 200 0
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n.ext b/mag/3-stage_cs-vco_dp9/vco_switch_n.ext
new file mode 100755
index 0000000..9fb2c89
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n.ext
@@ -0,0 +1,88 @@
+timestamp 1646474908
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_sc_hd__inv_1 x1 1 0 414 0 1 584
+use sky130_fd_pr__pfet_01v8_ACAZ2B XM25 0 -1 789 1 0 957
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 0 -1 828 1 0 701
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_1 0 -1 828 -1 0 607
+port "vdd" 4 376 1080 414 1176 m1
+port "vss" 3 376 488 414 632 m1
+port "in" 0 376 876 407 911 m1
+port "sel" 1 478 793 520 839 m1
+port "out" 2 927 784 985 865 m1
+node "m1_656_924#" 0 -7.585 656 924 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3960 252 0 0 0 0 0 0 0 0 0 0
+node "vdd" 0 21.73 376 1080 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33284 840 0 0 0 0 0 0 0 0 0 0
+node "vss" 34 670.986 376 488 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 47942 1542 0 0 0 0 0 0 0 0 0 0
+node "li_560_674#" 73 466.603 560 674 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2871 304 13978 808 0 0 0 0 0 0 0 0 0 0
+node "in" 24 234.784 376 876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2040 188 27313 1456 0 0 0 0 0 0 0 0 0 0
+node "sel" 82 463.619 478 793 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4216 384 12058 742 0 0 0 0 0 0 0 0 0 0
+node "li_616_937#" 27 2.40811 616 937 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3034 238 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 170 279.377 927 784 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16082 1014 4698 278 0 0 0 0 0 0 0 0 0 0
+node "w_376_845#" 5999 663.628 376 845 nw 0 0 0 0 225856 2176 0 0 9384 620 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8820 608 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "w_376_462#" 0 0 376 462 pw 234013 1988 0 0 0 0 0 0 0 0 8680 566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7595 504 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_376_845#" "in" 231.456
+cap "in" "li_560_674#" 69.4985
+cap "out" "in" 118.361
+cap "vdd" "m1_656_924#" 17
+cap "sel" "vdd" 38.8956
+cap "w_376_845#" "li_616_937#" 63.5602
+cap "w_376_845#" "out" 126.262
+cap "out" "li_560_674#" 3.5
+cap "out" "li_616_937#" 5.06639
+cap "in" "vdd" 81.6124
+cap "m1_656_924#" "vss" 4.13514
+cap "sel" "m1_656_924#" 29.6703
+cap "w_376_845#" "vdd" 297.909
+cap "li_560_674#" "vdd" 15.6432
+cap "sel" "vss" 55.2198
+cap "in" "m1_656_924#" 96.4286
+cap "in" "vss" 105.016
+cap "in" "sel" 524.804
+cap "w_376_845#" "m1_656_924#" 53.2239
+cap "li_560_674#" "m1_656_924#" 12.5581
+cap "li_616_937#" "m1_656_924#" 36.5189
+cap "li_560_674#" "vss" 169.247
+cap "out" "vss" 3.3
+cap "w_376_845#" "sel" 4.44231
+cap "sel" "li_560_674#" 129.263
+cap "out" "sel" 33.5213
+cap "x1/VPB" "XM25/a_18_n108#" -12.4282
+cap "x1/Y" "XM25/a_18_n108#" 58.5311
+cap "XM25/a_n76_n108#" "x1/VPB" -15.2069
+cap "XM25/a_n76_n108#" "x1/Y" 100.622
+cap "x1/A" "x1/VNB" 282.649
+cap "x1/A" "XM25/a_18_n108#" 31.8579
+cap "x1/VNB" "XM25/a_18_n108#" 45.7933
+cap "x1/Y" "x1/VPB" -79.2215
+cap "XM25/a_n76_n108#" "x1/VNB" -14.1382
+cap "XM25/a_n76_n108#" "x1/A" 20.6405
+cap "XM25/a_n76_n108#" "XM25/a_18_n108#" 72.3306
+cap "x1/A" "x1/VPB" -4.44231
+cap "x1/A" "x1/Y" 194.777
+cap "x1/VNB" "x1/Y" 322.934
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" -70.2292 0 0 0 0 0 0 0 0 -4872 -284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3662 -418 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" "XM25/a_18_n108#"
+merge "XM25/a_18_n108#" "out"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "XM25/a_n76_n108#" -134.322 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2040 -188 -1224 -290 0 0 0 0 0 0 0 0 0 0
+merge "XM25/a_n76_n108#" "in"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "XM25/a_n33_67#" -274.608 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4129 -520 -2668 -208 0 0 0 0 0 0 0 0 0 0
+merge "XM25/a_n33_67#" "m1_656_924#"
+merge "m1_656_924#" "x1/Y"
+merge "x1/Y" "li_616_937#"
+merge "li_616_937#" "li_560_674#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_18_n73#" -224.174 -35092 -838 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3128 -686 -4968 -744 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_18_n73#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" "XM25/VSUBS"
+merge "XM25/VSUBS" "x1/VGND"
+merge "x1/VGND" "vss"
+merge "vss" "x1/VNB"
+merge "x1/VNB" "w_376_462#"
+merge "XM25/w_n112_n170#" "x1/VPWR" -611.77 0 0 0 0 -181322 -2620 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -320 -540 -26496 -744 0 0 0 0 0 0 0 0 0 0
+merge "x1/VPWR" "vdd"
+merge "vdd" "x1/VPB"
+merge "x1/VPB" "w_376_845#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "x1/A" -330.428 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2006 -254 0 0 0 0 0 0 0 0 0 0 0 0
+merge "x1/A" "sel"
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n.mag b/mag/3-stage_cs-vco_dp9/vco_switch_n.mag
new file mode 100755
index 0000000..23ac0d1
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n.mag
@@ -0,0 +1,111 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646474908
+<< nwell >>
+rect 376 952 987 1215
+rect 376 845 932 952
+rect 934 845 987 952
+<< pwell >>
+rect 376 462 987 845
+<< psubdiff >>
+rect 414 532 443 567
+rect 627 532 662 567
+<< nsubdiff >>
+rect 414 1145 443 1179
+rect 661 1145 690 1179
+<< psubdiffcont >>
+rect 443 532 627 567
+<< nsubdiffcont >>
+rect 443 1145 661 1179
+<< locali >>
+rect 427 1135 443 1179
+rect 661 1135 677 1179
+rect 891 988 973 1022
+rect 616 937 698 974
+rect 939 852 973 988
+rect 486 799 494 833
+rect 745 745 779 793
+rect 560 674 574 709
+rect 939 671 973 796
+rect 899 637 973 671
+rect 426 532 443 567
+rect 627 532 643 567
+rect 813 543 829 577
+rect 889 543 905 577
+<< viali >>
+rect 494 799 528 833
+rect 745 793 779 827
+rect 939 796 973 852
+rect 829 731 889 765
+rect 574 674 609 709
+rect 745 575 779 609
+rect 829 543 889 577
+<< metal1 >>
+rect 376 1080 690 1186
+rect 656 924 716 990
+rect 376 896 598 911
+rect 376 876 889 896
+rect 570 861 889 876
+rect 478 833 538 839
+rect 478 799 494 833
+rect 528 827 791 833
+rect 528 799 745 827
+rect 478 793 538 799
+rect 733 793 745 799
+rect 779 793 791 827
+rect 733 787 791 793
+rect 834 777 889 861
+rect 927 852 985 865
+rect 927 796 939 852
+rect 973 796 985 852
+rect 927 784 985 796
+rect 819 765 899 777
+rect 817 731 829 765
+rect 889 764 899 765
+rect 889 731 901 764
+rect 817 725 901 731
+rect 562 709 621 715
+rect 562 674 574 709
+rect 609 674 779 709
+rect 562 668 621 674
+rect 376 554 414 632
+rect 744 625 779 674
+rect 729 609 789 625
+rect 729 575 745 609
+rect 779 575 789 609
+rect 729 559 789 575
+rect 817 577 901 584
+rect 376 508 690 554
+rect 817 543 829 577
+rect 889 543 901 577
+rect 817 508 901 543
+rect 376 462 901 508
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_1
+timestamp 1646411492
+transform 0 -1 828 -1 0 607
+box -76 -99 76 99
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0
+timestamp 1646411492
+transform 0 -1 828 1 0 701
+box -76 -99 76 99
+use sky130_fd_pr__pfet_01v8_ACAZ2B XM25
+timestamp 1646336843
+transform 0 -1 789 1 0 957
+box -112 -170 112 136
+use sky130_fd_sc_hd__inv_1 x1 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1642674852
+transform 1 0 414 0 1 584
+box -38 -48 314 592
+<< labels >>
+rlabel metal1 376 876 407 911 1 in
+port 0 n
+rlabel metal1 376 488 414 632 1 vss
+port 3 n
+rlabel metal1 376 1080 414 1176 1 vdd
+port 4 n
+rlabel metal1 927 784 985 865 1 out
+port 2 n
+rlabel metal1 478 793 520 839 1 sel
+port 1 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n.spice b/mag/3-stage_cs-vco_dp9/vco_switch_n.spice
new file mode 100755
index 0000000..17742c3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n.spice
@@ -0,0 +1,22 @@
+* NGSPICE file created from vco_switch_n.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_sc_hd__inv_1 A VGND VPWR Y VNB VPB
+X0 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=1.69e+11p pd=1.82e+06u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u
+X1 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.6e+11p pd=2.52e+06u as=2.6e+11p ps=2.52e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n in sel out vss vdd
+XXM25 vdd in out x1/Y sky130_fd_pr__pfet_01v8_ACAZ2B
+Xx1 sel vss vdd x1/Y vss vdd sky130_fd_sc_hd__inv_1
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss x1/Y out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n_v2.ext b/mag/3-stage_cs-vco_dp9/vco_switch_n_v2.ext
new file mode 100755
index 0000000..a9fc00d
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n_v2.ext
@@ -0,0 +1,87 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0 1 0 549 0 1 981
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0 1 0 549 0 1 727
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_1 0 -1 828 -1 0 607
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 0 -1 828 1 0 701
+use sky130_fd_pr__pfet_01v8_ACAZ2B XM25 0 -1 789 1 0 957
+port "in" 0 376 876 407 911 m1
+port "sel" 1 478 793 520 839 m1
+port "out" 2 927 784 985 865 m1
+port "vdd" 4 376 1080 414 1176 m1
+port "vss" 3 376 488 414 632 m1
+node "m1_656_924#" 0 5.23973 656 924 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3960 252 0 0 0 0 0 0 0 0 0 0
+node "li_560_674#" 73 595.795 560 674 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2871 304 13978 808 0 0 0 0 0 0 0 0 0 0
+node "in" 24 241.855 376 876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2040 188 27313 1456 0 0 0 0 0 0 0 0 0 0
+node "selb" 40 48.5894 576 765 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "sel" 82 300.595 478 793 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4216 384 12058 742 0 0 0 0 0 0 0 0 0 0
+node "li_610_937#" 29 3.11143 610 937 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3256 250 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 170 151.067 927 784 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16082 1014 4698 278 0 0 0 0 0 0 0 0 0 0
+node "vdd" 5970 699.298 376 1080 m1 0 0 0 0 225856 2176 0 0 9384 620 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14659 690 33284 840 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 376 488 m1 0 0 0 0 0 0 0 0 0 0 8680 566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16423 876 69470 1542 0 0 0 0 0 0 0 0 0 0
+cap "li_560_674#" "in" 69.4985
+cap "sel" "in" 524.804
+cap "out" "selb" 11.234
+cap "vdd" "selb" 25.6024
+cap "vdd" "m1_656_924#" 62.6389
+cap "li_560_674#" "selb" 19.4464
+cap "sel" "selb" 73.7852
+cap "vdd" "out" 119.292
+cap "li_560_674#" "m1_656_924#" 12.5581
+cap "sel" "m1_656_924#" 29.6703
+cap "vdd" "li_560_674#" 15.6432
+cap "li_560_674#" "out" 3.5
+cap "in" "selb" 23.1304
+cap "vdd" "sel" 44.249
+cap "sel" "out" 33.5213
+cap "li_610_937#" "m1_656_924#" 36.5189
+cap "in" "m1_656_924#" 96.4286
+cap "sel" "li_560_674#" 129.263
+cap "vdd" "li_610_937#" 68.7837
+cap "li_610_937#" "out" 5.06639
+cap "vdd" "in" 305.745
+cap "in" "out" 118.361
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 9.62368
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" 72.3306
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" -15.68
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 21.0908
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 137.365
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" -12.8826
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" 30.674
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 10.0179
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" -34.8758
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 24.9046
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" 23.393
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" 51.1319
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 44.7292
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 49.2705
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 48.4129
+merge "XM25/a_n33_67#" "m1_656_924#" -153.269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3273 -608 -2668 -208 0 0 0 0 0 0 0 0 0 0
+merge "m1_656_924#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_15_n96#"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_15_n96#" "li_560_674#"
+merge "li_560_674#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "selb"
+merge "selb" "li_610_937#"
+merge "XM25/a_18_n108#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" -34.4963 0 0 0 0 0 0 0 0 -4872 -284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3662 -418 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "out"
+merge "XM25/a_n76_n108#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" -78.8077 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2040 -188 -1224 -290 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "in"
+merge "XM25/w_n112_n170#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#" -399.882 0 0 0 0 -133294 -2306 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "vdd"
+merge "XM25/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" -117.459 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3128 -320 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_18_n73#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_18_n73#" "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS" "vss"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" -127.685 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 -2006 -254 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" "sel"
+merge "sel" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#"
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n_v2.mag b/mag/3-stage_cs-vco_dp9/vco_switch_n_v2.mag
new file mode 100755
index 0000000..a2fff1a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n_v2.mag
@@ -0,0 +1,132 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< nwell >>
+rect 376 952 987 1215
+rect 376 845 932 952
+rect 934 845 987 952
+<< pwell >>
+rect 376 462 987 845
+<< psubdiff >>
+rect 414 532 443 567
+rect 627 532 662 567
+<< nsubdiff >>
+rect 414 1145 443 1179
+rect 661 1145 690 1179
+<< psubdiffcont >>
+rect 443 532 627 567
+<< nsubdiffcont >>
+rect 443 1145 661 1179
+<< locali >>
+rect 427 1160 443 1179
+rect 426 1136 443 1160
+rect 661 1145 677 1179
+rect 661 1136 676 1145
+rect 426 1126 676 1136
+rect 488 1085 522 1126
+rect 891 988 973 1022
+rect 610 937 698 974
+rect 486 799 494 833
+rect 576 765 610 877
+rect 939 852 973 988
+rect 745 745 779 793
+rect 560 674 574 709
+rect 939 671 973 796
+rect 899 637 973 671
+rect 488 587 522 627
+rect 426 576 643 587
+rect 426 532 443 576
+rect 627 532 643 576
+rect 813 543 829 577
+rect 889 543 905 577
+<< viali >>
+rect 443 1145 661 1170
+rect 443 1136 661 1145
+rect 494 799 528 833
+rect 745 793 779 827
+rect 939 796 973 852
+rect 829 731 889 765
+rect 574 674 609 709
+rect 443 567 627 576
+rect 443 541 627 567
+rect 745 575 779 609
+rect 829 543 889 577
+<< metal1 >>
+rect 376 1170 690 1186
+rect 376 1136 443 1170
+rect 661 1136 690 1170
+rect 376 1080 690 1136
+rect 656 924 716 990
+rect 376 896 598 911
+rect 376 876 889 896
+rect 570 861 889 876
+rect 478 833 538 839
+rect 478 799 494 833
+rect 528 827 791 833
+rect 528 799 745 827
+rect 478 793 538 799
+rect 733 793 745 799
+rect 779 793 791 827
+rect 733 787 791 793
+rect 834 777 889 861
+rect 927 852 985 865
+rect 927 796 939 852
+rect 973 796 985 852
+rect 927 784 985 796
+rect 819 765 899 777
+rect 817 731 829 765
+rect 889 764 899 765
+rect 889 731 901 764
+rect 817 725 901 731
+rect 562 709 621 715
+rect 562 674 574 709
+rect 609 674 779 709
+rect 562 668 621 674
+rect 376 576 690 632
+rect 744 625 779 674
+rect 376 541 443 576
+rect 627 541 690 576
+rect 729 609 789 625
+rect 729 575 745 609
+rect 779 575 789 609
+rect 729 559 789 575
+rect 817 577 901 584
+rect 376 508 690 541
+rect 817 543 829 577
+rect 889 543 901 577
+rect 817 508 901 543
+rect 376 462 901 508
+use sky130_fd_pr__pfet_01v8_ACAZ2B XM25
+timestamp 1647613837
+transform 0 -1 789 1 0 957
+box -112 -170 112 136
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 0 -1 828 1 0 701
+box -76 -99 76 99
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_1
+timestamp 1647613837
+transform 0 -1 828 -1 0 607
+box -76 -99 76 99
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 1 0 549 0 1 727
+box -73 -122 73 122
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 1 0 549 0 1 981
+box -109 -136 109 162
+<< labels >>
+rlabel metal1 376 876 407 911 1 in
+port 0 n
+rlabel metal1 376 488 414 632 1 vss
+port 3 n
+rlabel metal1 376 1080 414 1176 1 vdd
+port 4 n
+rlabel metal1 927 784 985 865 1 out
+port 2 n
+rlabel metal1 478 793 520 839 1 sel
+port 1 n
+rlabel locali 578 834 608 858 1 selb
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.ext b/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.ext
new file mode 100755
index 0000000..1c1df8a
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.ext
@@ -0,0 +1,79 @@
+timestamp 1646403372
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 XMNTGATE -1 0 -74 0 -1 512
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 XMNCLAMP 1 0 -74 0 1 93
+use sky130_fd_pr__nfet_01v8_JS3BNU XMNINV1 1 0 -91 0 1 357
+use sky130_fd_pr__pfet_01v8_hvt_BZS9EC XMPINV1 1 0 -74 0 1 1159
+use sky130_fd_pr__pfet_01v8_ACAZ2B_v2 XMPTGATE 1 0 -74 0 1 823
+port "sel" 2 -187 429 -162 463 m1
+port "in" 1 -197 613 -151 686 m1
+port "out" 3 4 620 62 678 m1
+port "vdd" 5 -186 1323 -164 1357 m1
+port "vss" 4 -186 -82 -164 -48 pw
+node "sel" 0 90.962 -187 429 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2142 194 0 0 0 0 0 0 0 0 0 0
+node "m1_n123_463#" 2 147.646 -123 463 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19890 1238 0 0 0 0 0 0 0 0 0 0
+node "li_n44_142#" 91 249.202 -44 142 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8602 574 0 0 0 0 0 0 0 0 0 0 0 0
+node "in" 63 129.406 -197 613 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5950 418 3358 238 0 0 0 0 0 0 0 0 0 0
+node "li_n41_906#" 21 363.28 -41 906 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1666 166 37012 2200 0 0 0 0 0 0 0 0 0 0
+node "out" 334 862.733 4 620 m1 0 0 0 0 0 0 0 0 4368 272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10268 740 26384 1548 0 0 0 0 0 0 0 0 0 0
+node "vdd" 6407 533.054 -186 1323 m1 0 0 0 0 171808 1982 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 27736 1058 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 -186 -82 pw 169120 1958 0 0 0 0 0 0 0 0 7616 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8874 658 27134 1436 0 0 0 0 0 0 0 0 0 0
+cap "m1_n123_463#" "in" 187.918
+cap "out" "in" 85.971
+cap "out" "li_n44_142#" 35.6912
+cap "in" "li_n41_906#" 35.3226
+cap "li_n44_142#" "li_n41_906#" 80.018
+cap "vdd" "in" 54.7213
+cap "out" "m1_n123_463#" 104.032
+cap "sel" "in" 10.8
+cap "m1_n123_463#" "li_n41_906#" 794.545
+cap "vdd" "m1_n123_463#" 204.724
+cap "out" "li_n41_906#" 774.943
+cap "vdd" "out" 61.5155
+cap "out" "sel" 11.9531
+cap "vdd" "li_n41_906#" 548.598
+cap "sel" "li_n41_906#" 23.1818
+cap "XMNCLAMP/a_n18_n99#" "XMNTGATE/a_18_n73#" -7.10543e-15
+cap "XMPINV1/w_n109_n164#" "XMNTGATE/a_18_n73#" -9.45316
+cap "XMNCLAMP/a_n76_n73#" "XMNTGATE/a_18_n73#" 53.9748
+cap "XMNCLAMP/a_n18_n99#" "XMNTGATE/a_n18_n99#" 306.896
+cap "XMNCLAMP/a_n18_n99#" "XMNTGATE/a_n76_n73#" 157.983
+cap "XMPINV1/w_n109_n164#" "XMNTGATE/a_n18_n99#" -56.8774
+cap "XMPINV1/w_n109_n164#" "XMNTGATE/a_n76_n73#" -22.769
+cap "XMNCLAMP/a_n76_n73#" "XMNTGATE/a_n18_n99#" 319.604
+cap "XMNCLAMP/a_n76_n73#" "XMNTGATE/a_n76_n73#" -6.2113
+cap "XMNTGATE/a_n76_n73#" "XMNTGATE/a_18_n73#" 1.13687e-13
+cap "XMNTGATE/a_18_n73#" "XMNTGATE/a_n18_n99#" 183.609
+cap "XMNTGATE/a_n76_n73#" "XMNTGATE/a_n18_n99#" 8.14365
+cap "XMPINV1/w_n109_n164#" "XMNCLAMP/a_n18_n99#" -250.662
+cap "XMNCLAMP/a_n18_n99#" "XMNCLAMP/a_n76_n73#" 57.082
+cap "XMPINV1/a_n54_n161#" "XMPINV1/w_n109_n164#" 3.0207
+cap "XMPINV1/w_n109_n164#" "XMPINV1/a_15_n64#" 34.0536
+merge "XMPINV1/a_n54_n161#" "XMNINV1/a_n57_56#" -511.658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4752 -276 0 0 -2244 -200 -3604 -336 0 0 0 0 0 0 0 0 0 0
+merge "XMNINV1/a_n57_56#" "sel"
+merge "sel" "m1_n123_463#"
+merge "m1_n123_463#" "XMNTGATE/a_n18_n99#"
+merge "XMPTGATE/a_18_n108#" "XMNCLAMP/a_18_n73#" -76.9682 0 0 0 0 0 0 0 0 -4368 -272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4080 -444 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XMNCLAMP/a_18_n73#" "XMNTGATE/a_n76_n73#"
+merge "XMNTGATE/a_n76_n73#" "out"
+merge "XMPTGATE/a_n76_n108#" "XMNTGATE/a_18_n73#" -51.9116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XMNTGATE/a_18_n73#" "in"
+merge "XMPTGATE/a_n33_67#" "XMPINV1/a_15_n64#" -478.734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3088 -508 -18047 -790 0 0 0 0 0 0 0 0 0 0
+merge "XMPINV1/a_15_n64#" "XMNINV1/a_15_n96#"
+merge "XMNINV1/a_15_n96#" "li_n41_906#"
+merge "li_n41_906#" "XMNCLAMP/a_n18_n99#"
+merge "XMNCLAMP/a_n18_n99#" "li_n44_142#"
+merge "XMPTGATE/w_n112_n170#" "XMPINV1/a_n73_n64#" -198.082 0 0 0 0 -71524 -2220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9062 -492 0 0 0 0 0 0 0 0 0 0
+merge "XMPINV1/a_n73_n64#" "XMPINV1/w_n109_n164#"
+merge "XMPINV1/w_n109_n164#" "vdd"
+merge "XMPTGATE/VSUBS" "XMPINV1/VSUBS" -231.743 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2040 -188 -3380 -312 0 0 0 0 0 0 0 0 0 0
+merge "XMPINV1/VSUBS" "XMNINV1/VSUBS"
+merge "XMNINV1/VSUBS" "XMNINV1/a_n73_n96#"
+merge "XMNINV1/a_n73_n96#" "XMNCLAMP/VSUBS"
+merge "XMNCLAMP/VSUBS" "XMNCLAMP/a_n76_n73#"
+merge "XMNCLAMP/a_n76_n73#" "XMNTGATE/VSUBS"
+merge "XMNTGATE/VSUBS" "vss"
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.mag b/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.mag
new file mode 100755
index 0000000..8227816
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.mag
@@ -0,0 +1,121 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646411492
+<< error_s >>
+rect -132 429 -85 463
+<< nwell >>
+rect -186 653 38 1420
+<< pwell >>
+rect -186 -102 38 653
+<< ndiff >>
+rect -53 92 -1 104
+rect -53 32 -44 92
+rect -10 32 -1 92
+rect -53 20 -1 32
+<< ndiffc >>
+rect -44 32 -10 92
+<< psubdiff >>
+rect -186 -82 -155 -48
+rect 14 -82 38 -48
+<< nsubdiff >>
+rect -150 1350 -126 1384
+rect -22 1350 2 1384
+<< psubdiffcont >>
+rect -155 -82 14 -48
+<< nsubdiffcont >>
+rect -126 1350 -22 1384
+<< locali >>
+rect -142 1350 -126 1384
+rect -22 1350 -6 1384
+rect -41 906 -32 940
+rect 2 906 8 940
+rect -138 666 -104 711
+rect -157 632 -104 666
+rect -138 589 -104 632
+rect -44 666 -10 731
+rect -44 632 16 666
+rect -44 577 -10 632
+rect -44 142 -10 395
+rect -44 92 -10 104
+rect -44 16 -10 32
+rect -171 -82 -155 -48
+rect 14 -82 30 -48
+<< viali >>
+rect -126 1350 -22 1384
+rect -32 906 2 940
+rect -191 632 -157 666
+rect 16 632 50 666
+rect -138 32 -104 92
+rect -44 32 -10 92
+rect -155 -82 14 -48
+<< metal1 >>
+rect -186 1384 38 1400
+rect -186 1350 -126 1384
+rect -22 1350 38 1384
+rect -186 1323 38 1350
+rect -141 1095 -95 1323
+rect -197 666 -151 686
+rect -197 632 -191 666
+rect -157 632 -151 666
+rect -197 613 -151 632
+rect -123 463 -89 1048
+rect -38 952 -4 1295
+rect -58 940 8 952
+rect -58 906 -32 940
+rect 2 906 8 940
+rect -58 894 8 906
+rect -187 429 -124 463
+rect -138 104 -104 391
+rect -58 261 -24 894
+rect 4 666 62 678
+rect 4 632 16 666
+rect 50 632 62 666
+rect 4 620 62 632
+rect 4 104 38 620
+rect -144 92 -98 104
+rect -144 32 -138 92
+rect -104 32 -98 92
+rect -144 16 -98 32
+rect -50 92 38 104
+rect -50 32 -44 92
+rect -10 70 38 92
+rect -10 32 -4 70
+rect -50 16 -4 32
+rect -138 -40 -104 16
+rect -186 -48 38 -40
+rect -186 -82 -155 -48
+rect 14 -82 38 -48
+rect -186 -91 38 -82
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 XMNTGATE
+timestamp 1646411492
+transform -1 0 -74 0 -1 512
+box -76 -99 76 99
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 XMNCLAMP
+timestamp 1646411492
+transform 1 0 -74 0 1 93
+box -76 -99 76 99
+use sky130_fd_pr__pfet_01v8_ACAZ2B_v2 XMPTGATE
+timestamp 1646398074
+transform 1 0 -74 0 1 823
+box -112 -170 112 136
+use sky130_fd_pr__pfet_01v8_hvt_BZS9EC XMPINV1
+timestamp 1646398638
+transform 1 0 -74 0 1 1159
+box -109 -164 109 198
+use sky130_fd_pr__nfet_01v8_JS3BNU XMNINV1
+timestamp 1646399090
+transform 1 0 -91 0 1 357
+box -73 -122 73 122
+<< labels >>
+rlabel metal1 -197 613 -151 686 1 in
+port 1 n
+rlabel metal1 -187 429 -162 463 1 sel
+port 2 n
+rlabel metal1 4 620 62 678 1 out
+port 3 n
+rlabel pwell -186 -82 -164 -48 1 vss
+port 4 n
+rlabel metal1 -186 1323 -164 1357 1 vdd
+port 5 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.spice b/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.spice
new file mode 100755
index 0000000..b97520b
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_n_vert.spice
@@ -0,0 +1,26 @@
+* NGSPICE file created from vco_switch_n_vert.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_JS3BNU a_n57_56# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n57_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_BZS9EC a_n73_n64# w_n109_n164# a_15_n64# a_n54_n161#
+X0 a_15_n64# a_n54_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt vco_switch_n_vert in sel out vss vdd
+XXMNTGATE in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+XXMNINV1 sel li_n44_142# vss vss sky130_fd_pr__nfet_01v8_JS3BNU
+XXMPTGATE vdd in out li_n44_142# sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+XXMNCLAMP out li_n44_142# vss vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+XXMPINV1 vdd vdd li_n44_142# sel sky130_fd_pr__pfet_01v8_hvt_BZS9EC
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_p.ext b/mag/3-stage_cs-vco_dp9/vco_switch_p.ext
new file mode 100755
index 0000000..b926c83
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_p.ext
@@ -0,0 +1,75 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0 1 0 549 0 1 981
+use sky130_fd_pr__pfet_01v8_ACAZ2B_v2 sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 0 -1 789 1 0 957
+use sky130_fd_pr__pfet_01v8_5YXW2B sky130_fd_pr__pfet_01v8_5YXW2B_0 0 -1 825 1 0 1051
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0 1 0 549 0 1 727
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 0 -1 828 1 0 701
+port "in" 0 376 876 407 911 m1
+port "out" 2 927 784 985 865 m1
+port "sel" 1 478 793 520 839 m1
+port "vdd" 4 376 1080 414 1176 nw
+port "vss" 3 376 488 414 632 m1
+node "in" 24 221.558 376 876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2040 188 27313 1456 0 0 0 0 0 0 0 0 0 0
+node "selb" 40 48.2225 576 765 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_610_903#" 29 3.63303 610 903 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3293 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 170 147.767 927 784 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16082 1014 4698 278 0 0 0 0 0 0 0 0 0 0
+node "sel" 306 383.732 478 793 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4572 276 0 0 16660 1184 25196 1532 0 0 0 0 0 0 0 0 0 0
+node "vdd" 6009 699.298 376 1080 nw 0 0 0 0 225856 2176 0 0 9384 620 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10540 688 47015 1254 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 376 488 m1 0 0 0 0 0 0 0 0 0 0 8228 552 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9418 622 65270 1442 0 0 0 0 0 0 0 0 0 0
+cap "vdd" "out" 119.292
+cap "selb" "in" 23.1304
+cap "vdd" "li_610_903#" 65.4914
+cap "out" "li_610_903#" 5.0875
+cap "selb" "vdd" 25.283
+cap "sel" "in" 730.084
+cap "selb" "out" 11.234
+cap "sel" "vdd" 634.013
+cap "sel" "out" 38.489
+cap "sel" "li_610_903#" 24.4665
+cap "sel" "selb" 84.7852
+cap "vdd" "in" 332.708
+cap "out" "in" 118.361
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 39.2136
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 3.85567
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 34.8277
+cap "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 23.2405
+cap "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 227.173
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" 100.345
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" 8.49929
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 4.8755
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 67.4141
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 72.3306
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" 10.0179
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" 27.0717
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" -35.181
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" -31.6358
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" 150.695
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" -78.8077 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2040 -188 -1224 -290 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "in"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n76_n72#" -17.0247 0 0 0 0 0 0 0 0 0 0 -8352 -404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5702 -538 -6624 -380 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n76_n72#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#"
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "out"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_15_n96#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -999 -338 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "selb"
+merge "selb" "li_610_903#"
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_18_n72#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/w_n112_n134#" -579.978 0 0 0 0 -193326 -3290 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 -3456 -336 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/w_n112_n134#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/w_n112_n170#"
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/w_n112_n170#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "vdd"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" -124.952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -132 0 0 -2346 -274 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#"
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sel"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS" -44.6487 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/VSUBS" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/VSUBS" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS" "vss"
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_p.mag b/mag/3-stage_cs-vco_dp9/vco_switch_p.mag
new file mode 100755
index 0000000..c431a31
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_p.mag
@@ -0,0 +1,130 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647613837
+<< nwell >>
+rect 376 952 987 1215
+rect 376 845 932 952
+rect 934 845 987 952
+<< pwell >>
+rect 376 462 987 845
+<< psubdiff >>
+rect 412 542 436 576
+rect 630 542 654 576
+<< nsubdiff >>
+rect 414 1145 443 1179
+rect 661 1145 690 1179
+<< psubdiffcont >>
+rect 436 542 630 576
+<< nsubdiffcont >>
+rect 443 1145 661 1179
+<< poly >>
+rect 655 1073 721 1089
+rect 655 1039 671 1073
+rect 705 1069 721 1073
+rect 705 1039 727 1069
+rect 655 1033 727 1039
+rect 655 1023 721 1033
+<< polycont >>
+rect 671 1039 705 1073
+<< locali >>
+rect 427 1145 443 1179
+rect 661 1145 677 1179
+rect 488 1085 522 1145
+rect 671 1073 705 1089
+rect 671 1034 705 1039
+rect 410 833 444 994
+rect 891 988 973 1022
+rect 610 903 699 940
+rect 410 799 494 833
+rect 576 765 610 877
+rect 939 852 973 988
+rect 745 745 779 793
+rect 939 671 973 796
+rect 899 637 973 671
+rect 488 576 522 627
+rect 420 542 436 576
+rect 630 542 646 576
+<< viali >>
+rect 443 1145 661 1179
+rect 410 994 444 1028
+rect 671 994 705 1034
+rect 494 799 528 833
+rect 745 793 779 827
+rect 939 796 973 852
+rect 829 731 889 765
+rect 445 542 619 576
+<< metal1 >>
+rect 376 1179 897 1186
+rect 376 1145 443 1179
+rect 661 1145 897 1179
+rect 376 1097 897 1145
+rect 376 1080 414 1097
+rect 398 1028 450 1040
+rect 659 1034 717 1040
+rect 659 1028 671 1034
+rect 398 994 410 1028
+rect 444 994 671 1028
+rect 705 994 717 1034
+rect 398 982 450 994
+rect 659 988 717 994
+rect 376 896 598 911
+rect 376 876 889 896
+rect 570 861 889 876
+rect 478 833 538 839
+rect 478 799 494 833
+rect 528 827 791 833
+rect 528 799 745 827
+rect 478 793 538 799
+rect 733 793 745 799
+rect 779 793 791 827
+rect 733 787 791 793
+rect 834 777 889 861
+rect 927 852 985 865
+rect 927 796 939 852
+rect 973 796 985 852
+rect 927 784 985 796
+rect 819 765 899 777
+rect 817 731 829 765
+rect 889 764 899 765
+rect 889 731 901 764
+rect 817 725 901 731
+rect 376 576 690 632
+rect 376 542 445 576
+rect 619 542 690 576
+rect 376 508 690 542
+rect 817 508 901 534
+rect 376 462 901 508
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 0 -1 828 1 0 701
+box -76 -99 76 99
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 1 0 549 0 1 727
+box -73 -122 73 122
+use sky130_fd_pr__pfet_01v8_5YXW2B sky130_fd_pr__pfet_01v8_5YXW2B_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 0 -1 825 1 0 1051
+box -112 -134 112 134
+use sky130_fd_pr__pfet_01v8_ACAZ2B_v2 sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0
+timestamp 1647613837
+transform 0 -1 789 1 0 957
+box -112 -170 112 136
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0 3-stage_cs-vco_dp9
+timestamp 1647613837
+transform 1 0 549 0 1 981
+box -109 -136 109 162
+<< labels >>
+rlabel metal1 376 876 407 911 1 in
+port 0 n
+rlabel metal1 376 488 414 632 1 vss
+port 3 n
+rlabel nwell 376 1080 414 1176 1 vdd
+port 4 n
+rlabel metal1 927 784 985 865 1 out
+port 2 n
+rlabel metal1 478 793 520 839 1 sel
+port 1 n
+rlabel locali 578 834 608 858 1 selb
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/vco_switch_p.spice b/mag/3-stage_cs-vco_dp9/vco_switch_p.spice
new file mode 100755
index 0000000..6ff17bb
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_switch_p.spice
@@ -0,0 +1,30 @@
+* NGSPICE file created from vco_switch_p.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd li_610_903# vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 li_610_903# sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd li_610_903# in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/vco_with_fdivs.ext b/mag/3-stage_cs-vco_dp9/vco_with_fdivs.ext
new file mode 100755
index 0000000..34490f3
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_with_fdivs.ext
@@ -0,0 +1,874 @@
+timestamp 1647616692
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use 3-stage_cs-vco_dp9 3-stage_cs-vco_dp9_0 1 0 25 0 1 226
+use FD_v2 FD_v2_2 -1 0 5933 0 -1 -29
+use FD_v2 FD_v2_3 -1 0 4118 0 -1 -29
+use FD_v2 FD_v2_4 1 0 2167 0 1 -83
+use FD_v2 FD_v2_5 1 0 3982 0 1 -83
+use FD_v2 FD_v2_8 -1 0 5933 0 -1 -1491
+use FD_v2 FD_v2_9 -1 0 4118 0 -1 -1491
+use FD_v5 FD_v5_0 1 0 2617 0 1 1451
+use FD_v2 FD_v2_7 -1 0 7748 0 -1 -1491
+use FD_v2 FD_v2_6 1 0 5797 0 1 -83
+use FD_v2 FD_v2_1 -1 0 7748 0 -1 -29
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_3 1 0 8560 0 -1 687
+use sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_8_1 1 0 9408 0 1 -657
+use sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_8_0 1 0 9408 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_4_1 1 0 8856 0 1 -657
+use sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_4_0 1 0 8856 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_2_1 1 0 8488 0 1 -657
+use sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_2_0 1 0 8488 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_0 1 0 10400 0 1 -657
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_1 1 0 10400 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_2 -1 0 12240 0 -1 687
+port "vctrl" 1 -1702 -522 -1659 -476 m1
+port "vsel3" 8 -1161 1449 -1138 1475 m1
+port "vsel2" 7 -1248 1534 -1225 1560 m1
+port "vsel1" 6 -1330 1605 -1307 1631 m1
+port "vsel0" 5 -1407 1757 -1384 1783 m1
+port "vdd" 3 1732 2426 1789 2460 m1
+port "vss" 4 1994 2687 2051 2721 m1
+port "out_div256_buf" 9 12793 -1239 12853 -1185 m2
+port "out_div128_buf" 2 12803 879 12857 931 m2
+node "m2_n2159_1638#" 3 519.697 -2159 1638 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43240 2242 0 0 0 0 0 0 0 0
+node "m2_n2159_1718#" 3 486.537 -2159 1718 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40400 2100 0 0 0 0 0 0 0 0
+node "m2_n2159_1798#" 3 456.177 -2159 1798 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36840 1922 0 0 0 0 0 0 0 0
+node "m2_n2159_1958#" 3 511.013 -2159 1958 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33440 1752 0 0 0 0 0 0 0 0
+node "vctrl" 0 134.133 -1702 -522 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4324 280 0 0 0 0 0 0 0 0 0 0
+node "m1_n2159_n461#" 1 295.61 -2159 -461 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30520 1012 0 0 0 0 0 0 0 0 0 0
+node "m1_2161_286#" 2 493.837 2161 286 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12280 656 10008 568 50596 1802 0 0 0 0 0 0
+node "m1_7680_300#" 4 740.571 7680 300 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65090 2922 0 0 0 0 0 0 0 0 0 0
+node "m1_n889_1476#" 0 84.687 -889 1476 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 384 0 0 0 0 0 0 0 0 0 0
+node "vsel3" 0 25.6106 -1161 1449 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel2" 0 25.6106 -1248 1534 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel1" 0 25.6106 -1330 1605 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel0" 0 24.3208 -1407 1757 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 832 116 0 0 0 0 0 0 0 0 0 0
+node "vdd" 0 46.009 1732 2426 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2660 216 0 0 0 0 0 0 0 0 0 0
+node "vss" 0 86.9735 1994 2687 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2660 216 0 0 0 0 0 0 0 0 0 0
+node "out_div256_buf" 14 489.358 12793 -1239 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7134 338 12099 440 73021 1908 0 0 0 0 0 0 0 0
+node "li_10187_n1210#" 122 145.666 10187 -1210 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 12220 736 0 0 0 0 0 0 0 0 0 0
+node "li_9326_n1210#" 72 88.6247 9326 -1210 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 7656 476 0 0 0 0 0 0 0 0 0 0
+node "li_8782_n1210#" 72 108.473 8782 -1210 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 9144 572 0 0 0 0 0 0 0 0 0 0
+node "li_8588_n1221#" 21 1383.2 8588 -1221 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2304 192 11450 630 180493 6358 74372 2710 0 0 0 0 0 0
+node "li_10185_n451#" 122 311.164 10185 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 12356 744 0 0 0 0 0 0 0 0 0 0
+node "li_9325_n451#" 72 194.218 9325 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 7240 460 0 0 0 0 0 0 0 0 0 0
+node "li_8789_n451#" 72 221.635 8789 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 8770 550 0 0 0 0 0 0 0 0 0 0
+node "li_8577_n451#" 18 1004.68 8577 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 58190 3474 0 0 0 0 0 0 0 0 0 0
+node "li_8587_462#" 239 809.308 8587 462 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6902 746 86706 4372 172163 8076 0 0 0 0 0 0 0 0
+node "out_div128_buf" 37 2826.11 12803 879 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22222 670 26208 648 238352 5886 62624 1534 0 0 0 0 0 0
+node "out" 216 332.429 1728 1040 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28280 1494 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_7680_n1770#" 59765 55333 7680 -1770 nw 0 0 0 0 5874215 21806 0 0 250240 14856 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 246908 14660 3225826 57614 4184598 94244 1114300 25460 0 0 0 0 0 0
+substrate "a_8547_n771#" 0 0 8547 -771 ppd 0 0 0 0 0 0 0 0 0 0 247316 14684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243712 14472 1651869 44136 3629178 82228 978840 22452 0 0 0 0 0 0
+cap "m1_n2159_n461#" "w_7680_n1770#" 68.3125
+cap "li_8789_n451#" "w_7680_n1770#" 27.9986
+cap "w_7680_n1770#" "m2_n2159_1718#" 300.375
+cap "w_7680_n1770#" "li_8577_n451#" 64.3486
+cap "m2_n2159_1798#" "m2_n2159_1718#" 1151.25
+cap "w_7680_n1770#" "li_8587_462#" 7142.79
+cap "m2_n2159_1958#" "m2_n2159_1718#" 209
+cap "vsel3" "m1_n889_1476#" 0.914634
+cap "vsel3" "w_7680_n1770#" 46.3848
+cap "m2_n2159_1638#" "m2_n2159_1718#" 1262.5
+cap "li_8588_n1221#" "w_7680_n1770#" 2063.08
+cap "w_7680_n1770#" "m1_n889_1476#" 44.1
+cap "w_7680_n1770#" "m2_n2159_1798#" 219.814
+cap "m2_n2159_1958#" "w_7680_n1770#" 75.34
+cap "li_9325_n451#" "li_8789_n451#" 9.76017
+cap "li_8782_n1210#" "li_8588_n1221#" 29.2195
+cap "li_8782_n1210#" "w_7680_n1770#" 146.832
+cap "w_7680_n1770#" "li_9326_n1210#" 128.186
+cap "li_8587_462#" "out_div128_buf" 30.4924
+cap "m2_n2159_1638#" "w_7680_n1770#" 481.971
+cap "m1_2161_286#" "w_7680_n1770#" 150.819
+cap "m2_n2159_1958#" "m2_n2159_1798#" 348.333
+cap "li_10187_n1210#" "w_7680_n1770#" 202.557
+cap "w_7680_n1770#" "out_div256_buf" 464.121
+cap "m1_n2159_n461#" "vctrl" 3
+cap "li_8789_n451#" "li_8577_n451#" 24.7995
+cap "m2_n2159_1638#" "m2_n2159_1798#" 383.75
+cap "vsel2" "m1_n889_1476#" 4.44611
+cap "w_7680_n1770#" "out_div128_buf" 177.017
+cap "m2_n2159_1638#" "m2_n2159_1958#" 149.286
+cap "li_8782_n1210#" "li_9326_n1210#" 9.85063
+cap "li_10185_n451#" "w_7680_n1770#" 40.6135
+cap "li_9325_n451#" "w_7680_n1770#" 22.2458
+cap "m1_7680_300#" "li_8587_462#" 78.0189
+cap "vsel0" "m2_n2159_1718#" 16.6513
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "3-stage_cs-vco_dp9_0/vctrl" 1386.29
+cap "3-stage_cs-vco_dp9_0/sel1" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" 60.8111
+cap "3-stage_cs-vco_dp9_0/vctrl" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 11.6418
+cap "3-stage_cs-vco_dp9_0/sel1" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 112.371
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" 60.8249
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 140.584
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "3-stage_cs-vco_dp9_0/sel3" 60.8646
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 205.873
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/sel" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" 159.615
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/in" 23.2836
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "3-stage_cs-vco_dp9_0/sel3" -1.74933
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/sel3" 666.667
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/sel" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 379.429
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/sel" 144.539
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" 19.4813
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/in" 11.6418
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "FD_v2_4/Clk_In" 8.96197
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/sel" 2.85714
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sel" 314.227
+cap "FD_v2_4/Clk_In" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" 34.7407
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" "3-stage_cs-vco_dp9_0/ng3" 7.44363
+cap "FD_v2_4/GND" "FD_v2_9/4" 17.7273
+cap "FD_v2_3/VDD" "FD_v2_4/5" 5.78133
+cap "FD_v2_4/GND" "FD_v2_4/5" 23.9658
+cap "FD_v2_4/GND" "FD_v2_9/Clk_Out" 5.17315
+cap "FD_v2_4/3" "FD_v2_3/VDD" 4.60465
+cap "FD_v2_4/GND" "FD_v2_4/3" 11.5455
+cap "FD_v2_4/2" "FD_v2_3/VDD" 2.77806
+cap "FD_v2_4/GND" "FD_v2_4/2" 6
+cap "FD_v2_4/Clkb" "FD_v2_9/4" 2.51825
+cap "FD_v2_4/3" "FD_v2_9/2" 0.68546
+cap "FD_v2_4/GND" "FD_v2_3/VDD" 2.55831
+cap "FD_v2_9/6" "FD_v2_4/Clk_In" 15.4867
+cap "FD_v2_4/GND" "FD_v2_9/7" 12.0649
+cap "FD_v2_4/4" "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 2.51825
+cap "FD_v2_4/GND" "FD_v2_9/5" 23.9658
+cap "FD_v2_4/GND" "FD_v2_9/2" 5.44323
+cap "FD_v2_4/5" "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 2.60252
+cap "FD_v2_4/Clkb" "FD_v2_9/7" 5.79832
+cap "FD_v2_4/Clkb" "FD_v2_9/5" 2.60252
+cap "FD_v2_4/GND" "FD_v2_4/Clkb" 26.5514
+cap "FD_v2_3/VDD" "FD_v2_4/Clk_In" 10.7368
+cap "FD_v2_4/GND" "FD_v2_4/Clk_In" 133.008
+cap "FD_v2_9/7" "FD_v2_4/Clk_In" 10.0581
+cap "FD_v2_4/GND" "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 13.9615
+cap "FD_v2_4/6" "FD_v2_3/VDD" 3.15689
+cap "FD_v2_4/GND" "FD_v2_4/6" 14.8618
+cap "FD_v2_4/3" "FD_v2_9/6" 0.172324
+cap "FD_v2_4/Clkb" "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 15.0072
+cap "FD_v2_4/4" "FD_v2_3/VDD" 9.09184
+cap "FD_v2_4/GND" "FD_v2_9/6" 37.7137
+cap "FD_v2_4/4" "FD_v2_4/GND" 26.0114
+cap "FD_v2_9/Clkb" "FD_v2_8/VDD" 37.8022
+cap "FD_v2_8/7" "FD_v2_4/GND" 25.8788
+cap "FD_v2_9/3" "FD_v2_4/GND" 11.5455
+cap "FD_v2_5/3" "FD_v2_4/Clk_Out" 19.5938
+cap "FD_v2_5/3" "FD_v2_8/2" 0.68546
+cap "FD_v2_5/Clkb" "FD_v2_4/Clk_Out" 40.8913
+cap "FD_v2_4/6" "FD_v2_4/Clk_Out" 15.4398
+cap "FD_v2_8/Clk_Out" "FD_v2_4/GND" 76.8732
+cap "FD_v2_8/Clk_Out" "FD_v2_4/7" 10.0581
+cap "FD_v2_8/Clk_Out" "FD_v2_8/6" 18.7444
+cap "FD_v2_2/VDD" "FD_v2_4/7" 2.77806
+cap "FD_v2_2/VDD" "FD_v2_5/4" 8.54464
+cap "FD_v2_8/7" "FD_v2_9/Clkb" 4.45238
+cap "FD_v2_4/GND" "FD_v2_4/7" 25.8788
+cap "FD_v2_4/GND" "FD_v2_5/4" 24.8295
+cap "FD_v2_9/4" "FD_v2_4/GND" 8.28409
+cap "FD_v2_8/7" "FD_v2_4/Clk_Out" 10.0581
+cap "FD_v2_8/6" "FD_v2_4/GND" 37.7137
+cap "FD_v2_8/7" "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 22.4939
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_9/Clkb" "FD_v2_8/Clk_Out" 71.7391
+cap "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_8/Clk_Out" 5.89315
+cap "FD_v2_2/VDD" "FD_v2_4/Clk_Out" 2.77806
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_4/GND" 6
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_4/7" 19.5299
+cap "FD_v2_9/Clkb" "FD_v2_4/GND" 29.5029
+cap "FD_v2_4/GND" "FD_v2_8/2" 5.44323
+cap "FD_v2_9/Clkb" "FD_v2_4/7" 5.79832
+cap "FD_v2_4/GND" "FD_v2_4/Clk_Out" 76.8732
+cap "FD_v2_4/7" "FD_v2_4/Clk_Out" 67.426
+cap "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_4/GND" 6
+cap "FD_v2_8/6" "FD_v2_4/Clk_Out" 15.4867
+cap "FD_v2_4/GND" "FD_v2_8/5" 3.5625
+cap "FD_v2_8/7" "FD_v2_8/VDD" 14.5814
+cap "FD_v2_8/Clk_Out" "FD_v2_8/VDD" 69.1959
+cap "FD_v2_5/Clkb" "FD_v2_8/7" 5.79832
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_4/Clk_Out" 5.89315
+cap "FD_v2_9/3" "FD_v2_4/6" 0.172324
+cap "FD_v2_9/3" "FD_v2_4/2" 0.68546
+cap "FD_v2_8/Clk_Out" "FD_v2_4/6" 15.4867
+cap "FD_v2_2/VDD" "FD_v2_5/3" 4.60465
+cap "FD_v2_4/6" "FD_v2_2/VDD" 9.59694
+cap "FD_v2_4/2" "FD_v2_2/VDD" 0.126276
+cap "FD_v2_4/GND" "FD_v2_5/3" 11.5455
+cap "FD_v2_5/Clkb" "FD_v2_4/GND" 29.5029
+cap "FD_v2_5/Clkb" "FD_v2_4/7" 4.45238
+cap "FD_v2_4/6" "FD_v2_4/GND" 22.8519
+cap "FD_v2_8/6" "FD_v2_5/3" 0.172324
+cap "FD_v2_8/7" "FD_v2_8/Clk_Out" 80.363
+cap "FD_v2_4/2" "FD_v2_4/GND" 5.44323
+cap "FD_v2_9/3" "FD_v2_8/Clk_Out" 34.375
+cap "FD_v2_5/7" "FD_v2_6/Clkb" 4.45238
+cap "FD_v2_5/GND" "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 6
+cap "FD_v2_7/7" "FD_v2_8/Clkb" 4.45238
+cap "FD_v2_8/Clk_In" "FD_v2_5/7" 10.0581
+cap "FD_v2_8/4" "FD_v2_5/a_971_n597#" 2.51825
+cap "FD_v2_2/VDD" "FD_v2_5/2" 0.126276
+cap "FD_v2_7/7" "FD_v2_6/Clkb" 5.79832
+cap "FD_v2_5/GND" "FD_v2_8/3" 11.5455
+cap "FD_v2_7/7" "FD_v2_8/Clk_In" 72.6071
+cap "FD_v2_5/GND" "FD_v2_5/a_971_n597#" 13.9615
+cap "FD_v2_8/VDD" "FD_v2_7/7" 14.5814
+cap "FD_v2_5/Clk_Out" "FD_v2_5/7" 67.426
+cap "FD_v2_2/VDD" "FD_v2_5/7" 2.77806
+cap "FD_v2_8/Clkb" "FD_v2_5/5" 2.60252
+cap "FD_v2_5/GND" "FD_v2_8/2" 6
+cap "FD_v2_5/GND" "FD_v2_5/2" 5.44323
+cap "FD_v2_8/Clk_In" "FD_v2_8/Clkb" 71.7391
+cap "FD_v2_8/VDD" "FD_v2_8/Clkb" 37.8022
+cap "FD_v2_7/7" "FD_v2_5/Clk_Out" 10.0581
+cap "FD_v2_5/Clk_Out" "FD_v2_6/3" 19.5938
+cap "FD_v2_2/VDD" "FD_v2_6/3" 0.287791
+cap "FD_v2_5/6" "FD_v2_8/Clk_In" 15.4867
+cap "FD_v2_7/6" "FD_v2_6/3" 0.172324
+cap "FD_v2_8/VDD" "FD_v2_8/Clk_In" 176.155
+cap "FD_v2_5/GND" "FD_v2_5/7" 25.8788
+cap "FD_v2_8/3" "FD_v2_5/2" 0.68546
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_5/7" 19.5299
+cap "FD_v2_5/6" "FD_v2_5/Clk_Out" 15.4398
+cap "FD_v2_5/6" "FD_v2_2/VDD" 12.7538
+cap "FD_v2_2/VDD" "FD_v2_5/5" 5.78133
+cap "FD_v2_5/Clk_Out" "FD_v2_6/Clkb" 40.8913
+cap "FD_v2_5/GND" "FD_v2_8/5" 20.4033
+cap "FD_v2_5/GND" "FD_v2_7/7" 25.8788
+cap "FD_v2_5/GND" "FD_v2_6/3" 5.17051
+cap "FD_v2_7/6" "FD_v2_8/Clk_In" 18.7444
+cap "FD_v2_8/Clkb" "FD_v2_5/4" 2.51825
+cap "FD_v2_5/GND" "FD_v2_8/Clkb" 43.4645
+cap "FD_v2_8/5" "FD_v2_5/a_971_n597#" 2.60252
+cap "FD_v2_2/VDD" "FD_v2_5/Clk_Out" 2.77806
+cap "FD_v2_5/GND" "FD_v2_5/5" 23.9658
+cap "FD_v2_5/GND" "FD_v2_5/6" 37.7137
+cap "FD_v2_5/GND" "FD_v2_6/Clkb" 29.5029
+cap "FD_v2_7/6" "FD_v2_5/Clk_Out" 2.78372
+cap "FD_v2_5/GND" "FD_v2_8/Clk_In" 57.3743
+cap "FD_v2_7/7" "FD_v2_8/2" 22.4939
+cap "FD_v2_8/Clkb" "FD_v2_5/a_971_n597#" 15.0072
+cap "FD_v2_5/6" "FD_v2_8/3" 0.172324
+cap "FD_v2_8/Clk_In" "FD_v2_8/3" 34.375
+cap "FD_v2_5/GND" "FD_v2_5/Clk_Out" 64.3867
+cap "FD_v2_2/VDD" "FD_v2_5/4" 0.547194
+cap "FD_v2_5/Clk_Out" "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 5.89315
+cap "FD_v2_2/VDD" "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 2.77806
+cap "FD_v2_5/GND" "FD_v2_7/6" 9.55283
+cap "FD_v2_5/GND" "FD_v2_8/4" 26.0114
+cap "FD_v2_8/2" "FD_v2_8/Clk_In" 3.9507
+cap "FD_v2_8/Clkb" "FD_v2_5/7" 5.79832
+cap "FD_v2_5/GND" "FD_v2_5/4" 1.18182
+cap "FD_v2_6/Clkb" "FD_v2_7/Clkb" 15.0072
+cap "FD_v2_5/GND" "FD_v2_7/3" 11.5455
+cap "FD_v2_6/7" "FD_v2_7/Clkb" 5.79832
+cap "FD_v2_5/GND" "FD_v2_7/Clk_In" 39.3068
+cap "FD_v2_5/GND" "FD_v2_7/6" 28.1609
+cap "FD_v2_2/VDD" "FD_v2_6/5" 5.78133
+cap "FD_v2_5/GND" "FD_v2_6/3" 6.375
+cap "FD_v2_5/GND" "FD_v2_7/Clkb" 19.132
+cap "FD_v2_7/3" "FD_v2_6/6" 0.172324
+cap "FD_v2_7/Clk_In" "FD_v2_6/6" 15.4867
+cap "FD_v2_5/GND" "FD_v2_6/Clkb" 13.9615
+cap "FD_v2_6/4" "FD_v2_7/Clkb" 2.51825
+cap "FD_v2_5/GND" "FD_v2_6/7" 12.0649
+cap "FD_v2_6/2" "FD_v2_5/GND" 5.44323
+cap "FD_v2_7/2" "FD_v2_7/Clk_In" 0.566547
+cap "FD_v2_6/3" "FD_v2_2/VDD" 4.31686
+cap "FD_v2_7/6" "FD_v2_5/Clk_Out" 12.703
+cap "FD_v2_7/2" "FD_v2_6/3" 0.68546
+cap "FD_v2_6/4" "FD_v2_5/GND" 26.0114
+cap "FD_v2_6/2" "FD_v2_2/VDD" 0.126276
+cap "FD_v2_7/4" "FD_v2_6/Clkb" 2.51825
+cap "FD_v2_6/7" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_6/5" "FD_v2_7/Clkb" 2.60252
+cap "FD_v2_7/5" "FD_v2_6/Clkb" 2.60252
+cap "FD_v2_5/GND" "FD_v2_6/6" 37.7137
+cap "FD_v2_6/2" "FD_v2_5/Clk_Out" -5.68434e-14
+cap "FD_v2_5/GND" "FD_v2_7/4" 26.0114
+cap "FD_v2_7/Clk_In" "FD_v2_7/Clkb" 6.23494
+cap "FD_v2_6/4" "FD_v2_2/VDD" 9.09184
+cap "FD_v2_7/2" "FD_v2_5/GND" 11.4432
+cap "FD_v2_5/GND" "FD_v2_7/5" 23.9658
+cap "FD_v2_6/2" "FD_v2_7/3" 0.68546
+cap "FD_v2_5/GND" "FD_v2_6/5" 23.9658
+cap "FD_v2_5/GND" "FD_v2_5/Clk_Out" 12.4865
+cap "FD_v2_7/Clk_In" "FD_v2_6/7" 23.7481
+cap "FD_v2_6/6" "FD_v2_2/VDD" 12.7538
+cap "FD_v2_7/Clk_In" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 16.7895
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" -130.115
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 70.4965
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 2.01546
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 72.0941
+cap "FD_v2_7/Clk_In" "FD_v2_7/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 0.566547
+cap "FD_v2_7/VDD" "FD_v2_7/Clk_In" 5.81161
+cap "FD_v2_6/7" "FD_v2_7/Clk_In" 13.6899
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 2.01546
+cap "sky130_fd_sc_hd__clkbuf_4_0/A" "sky130_fd_sc_hd__clkbuf_4_1/A" 1.98847
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_4_1/A" 64.549
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_8_0/A" 5.81607
+cap "sky130_fd_sc_hd__clkbuf_2_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 16.7895
+cap "sky130_fd_sc_hd__clkbuf_4_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 307.734
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 66.7364
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 3.97695
+cap "FD_v2_7/Clk_In" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 35.2546
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 79.5029
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_2_0/A" -34.3099
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_4_0/A" 5.78465
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_8_1/A" 3.25789
+cap "FD_v2_7/GND" "FD_v2_7/VDD" -5.8028
+cap "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/A" 50.9448
+cap "sky130_fd_sc_hd__clkbuf_2_0/A" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 30.778
+cap "FD_v2_7/Clk_In" "sky130_fd_sc_hd__clkbuf_2_0/A" 1.98847
+cap "FD_v2_7/Clk_In" "FD_v2_7/Clkb" 6.23494
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 9.29272
+cap "FD_v2_7/GND" "FD_v2_7/Clk_In" 205.119
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 56.1057
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 188.97
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/A" 12.052
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_8_0/A" 3.25789
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 0.530259
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_4_1/A" 8.38944
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/A" 5.21801
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 48.4715
+cap "sky130_fd_sc_hd__clkbuf_2_0/A" "sky130_fd_sc_hd__clkbuf_4_0/A" 16.9745
+cap "FD_v2_7/Clk_In" "sky130_fd_sc_hd__clkbuf_4_1/A" 16.1276
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_4_0/A" 58.4298
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_2_0/A" 13.9379
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 42.3299
+cap "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 107.689
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" -106.4
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/A" 12.052
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/A" 3.69079
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/A" 115.663
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_8_1/A" 5.21801
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 91.4874
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 95.6317
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 15.9078
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 16.8441
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 23.4765
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_0/X" 5.64474
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 31.6347
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 99.2513
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 49.6879
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 12.0812
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_0/VPB" 107.515
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" -75.8408
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 22.1814
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 19.2794
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 7.42363
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 5.60377
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/X" 209.582
+cap "sky130_fd_sc_hd__clkbuf_4_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 8.28293
+cap "sky130_fd_sc_hd__clkbuf_8_1/VPB" "sky130_fd_sc_hd__clkbuf_8_1/A" 7.0036
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/X" 58.3619
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" -101.52
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/VPB" 128.924
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_0/X" 150.457
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 7.10543e-15
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" -21.0416
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 24.3112
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 17.7031
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_8_1/VPB" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 8.16582
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 12.0812
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 4.75714
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_0/X" 100.606
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_1/A" 3.97695
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 6.84435
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/X" 43.1172
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 45.5248
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 79.3129
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 22.4136
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/A" 77.6983
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/X" -87.58
+cap "sky130_fd_sc_hd__clkbuf_8_1/VGND" "sky130_fd_sc_hd__clkbuf_8_0/X" 14.3373
+cap "sky130_fd_sc_hd__clkbuf_8_1/VGND" "sky130_fd_sc_hd__clkbuf_8_1/X" 14.1026
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/X" 43.4105
+cap "sky130_fd_sc_hd__clkbuf_8_0/X" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 36.3246
+cap "sky130_fd_sc_hd__clkbuf_8_1/VGND" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 183.828
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 23.8617
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/VPB" 175.349
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 35.2832
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 27.6506
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" -140.43
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 2.52354
+cap "sky130_fd_sc_hd__clkbuf_8_1/VGND" "sky130_fd_sc_hd__clkbuf_16_0/X" 246.935
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_0/X" 7.95389
+cap "sky130_fd_sc_hd__clkbuf_8_1/VPB" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 53.8883
+cap "sky130_fd_sc_hd__clkbuf_16_1/X" "sky130_fd_sc_hd__clkbuf_8_0/VPB" 159.063
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_0/X" 6.81728
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 24.8218
+cap "sky130_fd_sc_hd__clkbuf_16_1/X" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 137.717
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" 1.13687e-13
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 21.3163
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 7.95389
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 10.8508
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 4.25665
+cap "sky130_fd_sc_hd__clkbuf_16_1/X" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 50.8858
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 88.6816
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/X" -52.2788
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/X" -102.92
+cap "FD_v2_3/Clk_Out" "FD_v2_3/GND" 180.219
+cap "FD_v2_3/Clk_Out" "FD_v2_3/VDD" 58.4053
+cap "FD_v2_3/VDD" "FD_v2_3/GND" 52.0237
+cap "FD_v2_3/GND" "FD_v2_3/7" 12.0649
+cap "FD_v2_4/3" "FD_v2_3/2" 0.695783
+cap "FD_v2_3/VDD" "FD_v2_3/6" 30.6077
+cap "FD_v2_4/5" "FD_v2_3/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 4.4
+cap "FD_v2_3/VDD" "FD_v2_3/4" 16.4158
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_3/Clk_Out" 10.7812
+cap "FD_v2_3/6" "FD_v2_3/GND" 37.7137
+cap "FD_v5_0/Clkb_buf" "FD_v2_3/GND" 10.9463
+cap "FD_v2_3/VDD" "FD_v2_4/3" 21.0238
+cap "FD_v2_3/VDD" "FD_v2_4/2" 2.77806
+cap "FD_v2_3/5" "FD_v2_3/Clk_Out" 4.4
+cap "FD_v2_3/4" "FD_v2_3/GND" 17.7273
+cap "3-stage_cs-vco_dp9_0/out" "FD_v2_3/7" 2.14286
+cap "3-stage_cs-vco_dp9_0/out" "FD_v2_3/GND" 1.72174
+cap "FD_v2_3/VDD" "FD_v2_4/Clkb" 22.7108
+cap "FD_v2_3/VDD" "FD_v2_4/5" 17.4046
+cap "FD_v2_4/4" "FD_v2_3/VDD" 14.1918
+cap "FD_v2_3/VDD" "FD_v2_3/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 43.6154
+cap "FD_v2_3/7" "FD_v2_4/Clkb" 9.47414
+cap "FD_v2_3/5" "FD_v2_3/VDD" 23.1859
+cap "FD_v2_3/VDD" "FD_v2_3/Clk_Out" 104.475
+cap "FD_v2_3/GND" "FD_v5_0/Clkb_int" 6.06486
+cap "FD_v5_0/dus" "FD_v2_3/GND" 10.9463
+cap "FD_v2_3/7" "FD_v2_3/Clk_Out" 5.05366
+cap "FD_v2_3/5" "FD_v2_3/GND" 23.9658
+cap "FD_v2_3/VDD" "FD_v2_3/2" 6.77581
+cap "FD_v2_3/GND" "FD_v2_3/Clk_Out" 486.292
+cap "FD_v2_3/6" "FD_v2_4/Clkb" 2.22581
+cap "FD_v2_3/VDD" "FD_v2_4/6" 8.25689
+cap "FD_v2_3/6" "FD_v5_0/dus" 1.60108
+cap "FD_v2_3/GND" "FD_v2_3/2" 5.44323
+cap "FD_v2_3/5" "FD_v5_0/Clkb_buf" 0.540984
+cap "FD_v2_3/4" "FD_v5_0/dus" 0.142857
+cap "FD_v2_3/VDD" "FD_v2_3/7" 12.0794
+cap "FD_v2_3/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v2_3/GND" 13.9615
+cap "FD_v2_3/VDD" "FD_v2_3/GND" -187.542
+cap "FD_v2_2/6" "FD_v2_2/GND" 37.7137
+cap "FD_v2_3/3" "FD_v2_2/GND" 11.5455
+cap "FD_v2_4/Clk_Out" "FD_v2_2/7" 2.875
+cap "FD_v2_2/5" "FD_v5_0/Clk_In_buf" 0.236559
+cap "FD_v2_2/GND" "FD_v2_2/7" 25.8788
+cap "FD_v2_3/3" "FD_v2_4/2" 0.695783
+cap "FD_v2_2/GND" "FD_v2_2/Clk_Out" 76.8732
+cap "FD_v2_4/2" "FD_v2_2/VDD" 6.64953
+cap "FD_v2_4/Clk_Out" "FD_v2_5/3" 14.7812
+cap "FD_v2_2/GND" "FD_v5_0/Clk_In_buf" 11.3614
+cap "FD_v5_0/Clkb_buf" "FD_v2_2/GND" 5.47317
+cap "FD_v2_2/6" "FD_v2_2/VDD" 30.6077
+cap "FD_v2_4/Clk_Out" "FD_v2_4/6" 3.3046
+cap "FD_v2_3/3" "FD_v2_2/VDD" 21.0238
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_2/GND" 6
+cap "FD_v2_2/6" "FD_v2_2/Clk_Out" 18.7444
+cap "FD_v2_2/VDD" "FD_v2_4/7" 23.8827
+cap "FD_v2_3/3" "FD_v2_2/Clk_Out" 34.375
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/VDD" 18.2308
+cap "FD_v2_2/Clk_Out" "FD_v2_2/VDD" 81.2753
+cap "FD_v2_2/VDD" "FD_v2_2/7" 26.6608
+cap "FD_v2_2/Clk_Out" "FD_v2_4/7" 2.875
+cap "FD_v2_2/GND" "FD_v2_2/2" 5.44323
+cap "FD_v2_2/6" "FD_v5_0/Clk_In_buf" 40.3918
+cap "FD_v2_4/Clk_Out" "FD_v2_5/Clkb" 30.8478
+cap "FD_v2_3/3" "FD_v5_0/Clkb_buf" 2.64
+cap "FD_v5_0/3" "FD_v2_2/GND" 10.9463
+cap "FD_v2_2/Clk_Out" "FD_v2_2/7" 80.363
+cap "FD_v2_3/4" "FD_v2_2/GND" 8.28409
+cap "FD_v2_2/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v5_0/Clk_In_buf" 0.214953
+cap "FD_v5_0/MNinv1/a_n73_37#" "FD_v2_2/6" 2.14286
+cap "FD_v5_0/Clk_In_buf" "FD_v2_2/7" 7.66667
+cap "FD_v2_3/Clkb" "FD_v2_2/GND" 29.5029
+cap "FD_v2_2/Clk_Out" "FD_v5_0/Clk_In_buf" 7.89641
+cap "FD_v5_0/Clkb_buf" "FD_v2_2/Clk_Out" 1.78571
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_2/VDD" 5.55612
+cap "FD_v2_2/Clk_Out" "FD_v5_0/dus" 2.63359
+cap "FD_v2_5/3" "FD_v2_2/VDD" 21.0238
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_2/7" 22.4939
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_2/Clk_Out" 5.89315
+cap "FD_v2_4/6" "FD_v2_2/VDD" 9.59694
+cap "FD_v5_0/3" "FD_v2_2/6" 2.18833
+cap "FD_v2_2/VDD" "FD_v2_2/2" 6.77581
+cap "FD_v2_2/6" "FD_v2_5/Clkb" 2.22581
+cap "FD_v2_3/4" "FD_v2_2/VDD" 6.86786
+cap "FD_v2_2/VDD" "FD_v2_5/Clkb" 60.5129
+cap "FD_v2_3/Clkb" "FD_v2_2/VDD" 60.5129
+cap "FD_v2_3/Clkb" "FD_v2_4/7" 9.47414
+cap "FD_v2_2/7" "FD_v2_5/Clkb" 9.47414
+cap "FD_v2_3/Clkb" "FD_v2_2/7" 4.45238
+cap "FD_v2_3/Clkb" "FD_v2_2/Clk_Out" 71.7391
+cap "FD_v2_5/4" "FD_v2_2/VDD" 13.6446
+cap "FD_v2_5/3" "FD_v2_2/2" 0.695783
+cap "FD_v2_2/GND" "FD_v2_2/5" 3.5625
+cap "FD_v5_0/3" "FD_v2_2/2" 3.06557
+cap "FD_v2_4/6" "FD_v2_3/Clkb" 2.22581
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_4/7" 2.96392
+cap "FD_v2_2/5" "FD_v2_2/VDD" 2.85
+cap "FD_v2_4/Clk_Out" "FD_v2_2/VDD" 78.4973
+cap "FD_v2_4/Clk_Out" "FD_v2_4/7" 12.937
+cap "FD_v2_2/3" "FD_v5_0/4" 2.03077
+cap "FD_v2_2/Clk_In" "FD_v2_2/Clkb" 71.7391
+cap "FD_v2_1/7" "FD_v2_2/VDD" 26.6608
+cap "FD_v2_2/Clk_In" "FD_v5_0/a_2222_n669#" 81.9701
+cap "FD_v2_2/4" "FD_v2_2/GND" 26.0114
+cap "FD_v2_2/GND" "FD_v5_0/4" 21.8927
+cap "FD_v2_2/Clk_In" "FD_v2_2/VDD" 106.66
+cap "FD_v2_1/6" "FD_v2_2/GND" 9.55283
+cap "FD_v2_1/7" "FD_v2_5/Clk_Out" 2.875
+cap "FD_v2_6/Clkb" "FD_v2_1/7" 9.47414
+cap "FD_v5_0/3" "FD_v2_2/5" 3.7651
+cap "FD_v2_5/7" "FD_v2_2/Clkb" 9.47414
+cap "FD_v2_5/6" "FD_v2_2/Clkb" 2.22581
+cap "FD_v2_2/GND" "FD_v5_0/5" 10.9463
+cap "FD_v2_2/GND" "FD_v2_1/7" 25.8788
+cap "FD_v2_2/Clk_In" "FD_v2_2/3" 34.375
+cap "FD_v2_2/2" "FD_v2_1/7" 22.4939
+cap "FD_v2_2/Clk_In" "FD_v2_5/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 10.7812
+cap "FD_v5_0/3" "FD_v2_2/Clkb" 3.34177
+cap "FD_v2_5/7" "FD_v2_2/VDD" 23.8827
+cap "FD_v2_5/6" "FD_v2_2/VDD" 17.8538
+cap "FD_v2_2/Clk_In" "FD_v2_2/GND" 76.8732
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/5" 1.77419
+cap "FD_v2_2/Clk_In" "FD_v2_2/2" 5.89315
+cap "FD_v2_2/VDD" "FD_v2_2/5" 20.3359
+cap "FD_v2_1/7" "FD_v5_0/4" 1.57143
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/Clkb" 128.661
+cap "FD_v2_2/VDD" "FD_v2_2/Clkb" 60.5129
+cap "FD_v2_5/7" "FD_v2_5/Clk_Out" 12.937
+cap "FD_v2_5/6" "FD_v2_5/Clk_Out" 3.3046
+cap "FD_v2_6/3" "FD_v2_2/VDD" 7.11079
+cap "FD_v2_1/6" "FD_v2_2/Clk_In" 18.7444
+cap "FD_v2_5/4" "FD_v2_2/VDD" 0.547194
+cap "FD_v2_2/Clk_In" "FD_v2_5/5" 4.4
+cap "FD_v5_0/3" "FD_v2_2/3" 8.13086
+cap "FD_v2_5/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/5" 4.4
+cap "FD_v2_2/VDD" "FD_v2_5/2" 6.64953
+cap "FD_v5_0/3" "FD_v2_2/GND" 177.766
+cap "FD_v2_2/GND" "FD_v2_2/5" 20.4033
+cap "FD_v2_6/3" "FD_v2_5/Clk_Out" 14.7812
+cap "FD_v2_2/Clk_In" "FD_v2_1/7" 80.363
+cap "FD_v2_2/Clk_In" "FD_v5_0/5" 2.34426
+cap "FD_v2_5/7" "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 2.96392
+cap "FD_v2_2/3" "FD_v2_2/VDD" 21.0238
+cap "FD_v2_2/GND" "FD_v2_2/Clkb" 43.4645
+cap "FD_v2_2/VDD" "FD_v2_5/Clk_Out" 78.4973
+cap "FD_v2_2/3" "FD_v2_5/2" 0.695783
+cap "FD_v2_5/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/VDD" 43.6154
+cap "FD_v5_0/3" "FD_v2_2/4" 4.36576
+cap "FD_v2_2/GND" "FD_v5_0/a_2222_n669#" 26.9811
+cap "FD_v2_6/Clkb" "FD_v2_2/VDD" 45.2822
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/2" 2.20447
+cap "FD_v2_2/2" "FD_v2_2/VDD" 5.55612
+cap "FD_v2_2/4" "FD_v5_0/a_2222_n669#" 2.20447
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_2/4" "FD_v2_2/VDD" 23.2837
+cap "FD_v2_6/Clkb" "FD_v2_5/Clk_Out" 30.8478
+cap "FD_v2_2/GND" "FD_v2_2/3" 11.5455
+cap "FD_v2_1/6" "FD_v2_2/VDD" 8.41837
+cap "FD_v2_5/7" "FD_v2_2/Clk_In" 2.875
+cap "FD_v2_2/VDD" "FD_v2_5/5" 17.4046
+cap "FD_v2_1/7" "FD_v2_2/Clkb" 4.45238
+cap "FD_v5_0/3" "FD_v2_2/Clk_In" 9.51092
+cap "FD_v2_2/GND" "FD_v2_2/2" 6
+cap "FD_v2_1/6" "FD_v2_2/VDD" 22.1893
+cap "FD_v2_1/6" "FD_v2_5/GND" 28.1609
+cap "FD_v5_0/6" "FD_v2_1/Clk_In" 45.3525
+cap "FD_v2_1/Clkb" "FD_v2_6/6" 2.22581
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/2" 3.50625
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/Clk_In" 8.29184
+cap "FD_v2_6/5" "FD_v2_2/VDD" 17.4046
+cap "FD_v2_6/Clk_Out" "FD_v2_2/VDD" 6.52326
+cap "FD_v2_1/Clkb" "FD_v5_0/2" 1.80328
+cap "FD_v2_5/Clk_Out" "FD_v2_2/VDD" 43.6154
+cap "FD_v2_2/VDD" "FD_v2_6/6" 17.8538
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/3" 4.02151
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/4" 2.20447
+cap "FD_v2_6/Clkb" "FD_v2_2/VDD" 15.2308
+cap "FD_v2_1/5" "FD_v2_5/Clk_Out" 4.4
+cap "FD_v2_6/7" "FD_v2_1/Clk_In" 2.875
+cap "FD_v2_5/GND" "FD_v5_0/2" 10.9463
+cap "FD_v2_6/3" "FD_v2_1/2" 0.695783
+cap "FD_v2_1/Clkb" "FD_v5_0/Clkb_buf" 84.4225
+cap "FD_v5_0/6" "FD_v2_5/GND" 25.6327
+cap "FD_v5_0/Clkb_buf" "FD_v2_5/GND" 27.3962
+cap "FD_v2_1/5" "FD_v5_0/6" 5.30025
+cap "FD_v2_1/2" "FD_v2_2/VDD" 12.3319
+cap "FD_v2_1/Clkb" "FD_v2_6/7" 9.47414
+cap "FD_v2_1/Clk_In" "FD_v2_2/VDD" 48.919
+cap "FD_v2_5/GND" "FD_v2_1/2" 11.4432
+cap "FD_v2_5/GND" "FD_v2_1/Clk_In" 20.4435
+cap "FD_v2_6/4" "FD_v2_2/VDD" 14.1918
+cap "FD_v2_6/2" "FD_v2_1/3" 0.695783
+cap "FD_v5_0/5" "FD_v2_1/4" 2.95331
+cap "FD_v2_6/Clkb" "FD_v2_1/6" 2.22581
+cap "FD_v2_6/7" "FD_v2_2/VDD" 9.30132
+cap "FD_v2_1/3" "FD_v2_2/VDD" 21.0238
+cap "FD_v2_5/GND" "FD_v2_1/3" 11.5455
+cap "FD_v2_2/VDD" "FD_v2_1/4" 23.2837
+cap "FD_v2_5/GND" "FD_v2_1/4" 26.0114
+cap "FD_v2_6/3" "FD_v2_2/VDD" 13.9131
+cap "FD_v2_1/Clkb" "FD_v5_0/5" 9.18987
+cap "FD_v2_1/Clkb" "FD_v2_2/VDD" 22.7108
+cap "FD_v2_1/Clkb" "FD_v2_5/GND" 19.132
+cap "FD_v5_0/6" "FD_v2_1/6" 2.45093
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/6" 37.7139
+cap "FD_v2_6/2" "FD_v2_2/VDD" 6.64953
+cap "FD_v2_5/GND" "FD_v5_0/5" 177.766
+cap "FD_v2_1/5" "FD_v5_0/5" 8.13086
+cap "FD_v2_1/5" "FD_v2_2/VDD" 23.1859
+cap "FD_v2_1/5" "FD_v2_5/GND" 23.9658
+cap "FD_v2_6/5" "FD_v2_1/Clk_In" 4.4
+cap "FD_v2_5/Clk_Out" "FD_v2_1/Clk_In" 10.7812
+cap "FD_v2_1/6" "FD_v5_0/5" 7.99683
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 35.5947
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_16_3/A" 1.2349
+cap "FD_v2_6/VDD" "FD_v2_6/Clk_Out" 5.81161
+cap "FD_v5_0/GND" "FD_v2_6/VDD" 45.6124
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "FD_v2_6/VDD" 29.7555
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "FD_v2_6/VDD" 1.96107
+cap "FD_v2_6/VDD" "FD_v5_0/Clk_Out" 0.252551
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "FD_v2_6/VDD" 24
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 118.763
+cap "FD_v5_0/GND" "FD_v2_6/Clk_Out" 74.6465
+cap "FD_v5_0/GND" "FD_v5_0/MNbuf1/a_n73_37#" 1.0102
+cap "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 100.884
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "FD_v2_6/VDD" 63.3118
+cap "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_16_3/X" 2.19415
+cap "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 56.7732
+cap "FD_v5_0/GND" "FD_v5_0/Clk_Out" 124.164
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/A" 6.8484
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "FD_v5_0/GND" 11.3904
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "FD_v2_6/VDD" 100.332
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "FD_v2_6/Clk_Out" 2.4497
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 2.08516
+cap "FD_v2_6/VDD" "sky130_fd_sc_hd__clkbuf_16_3/A" 7.23176
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 8.61495
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "FD_v2_6/VDD" 5.81607
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "FD_v5_0/GND" 5.83377
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 2.11421
+cap "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_16_3/A" 60.8993
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 22.4136
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_8_1/A" 0.551532
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 2.43529
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 11.7315
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_8_1/A" 3.14714
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/X" 15.5833
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_8_1/A" 6.8484
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_8_1/A" 166.966
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 38.1486
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 20.3747
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 16.3188
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 2.77852
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/VPWR" 187.38
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "li_8587_462#" -87.955
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/X" 550.297
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_3/X" 374.019
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 32.1735
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 4.75714
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 8.67403
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 18.5887
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 0.174142
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 207.187
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 5.77345
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" -86.6276
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" -1.81899e-12
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 2.67915
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/A" 1.95395
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/X" 3.66667
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/X" 173.899
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 79.236
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 38.1486
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 12.349
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/X" 453.974
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/VPB" -2.4869e-14
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 8.67403
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/VPB" 16.8595
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" -4.54747e-13
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPB" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" -2.04636e-12
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_0/X" 42.8826
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 6.70188
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPB" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 109.547
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPB" "sky130_fd_sc_hd__clkbuf_16_3/X" 112.952
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_3/X" 18.7
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_3/VPB" 180.023
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 221.213
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 4.01342
+cap "li_8587_462#" "sky130_fd_sc_hd__clkbuf_16_3/VPB" -87.955
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 18.5887
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" 6.70188
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 1.13687e-13
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 85.5178
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" 4.01342
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 29.7555
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 4.25665
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 20.6392
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/X" 180.381
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/sel1" 21.9036
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel3" 103.016
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/sel2" 18.1536
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel2" 130.64
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/sel0" 99.539
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" 245.05
+cap "3-stage_cs-vco_dp9_0/sel0" "3-stage_cs-vco_dp9_0/sel1" 36.6895
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/sel0" 71.7863
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel0" 81.739
+cap "3-stage_cs-vco_dp9_0/sel0" "3-stage_cs-vco_dp9_0/sel2" 43.8795
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/sel1" 70.8562
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 11.0169
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel1" 133.343
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/sel" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 18.377
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg0" 7.61076
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" 4.54747e-13
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/pg0" 28.773
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg1" 7.37105
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" -1.3874
+cap "3-stage_cs-vco_dp9_0/pg1" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 28.3946
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 22.0339
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_1/sel" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 14.0684
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_2/sel" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 12.5
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_2/sel" 1.51515
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/pg3" 20.7447
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vdd" 111.872
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/pg2" 20.9677
+cap "3-stage_cs-vco_dp9_0/XM12/a_15_n240#" "3-stage_cs-vco_dp9_0/out" 0.456221
+cap "3-stage_cs-vco_dp9_0/pg3" "3-stage_cs-vco_dp9_0/vdd" 5.28455
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/pg2" 5.31335
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_3/sel" 13.1673
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_p_3/sel" 0.114213
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_2/in" 11.0169
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/out" -10.163
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/out" 52.005
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vdd" -275.329
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/out" -146.715
+cap "FD_v5_0/dus" "3-stage_cs-vco_dp9_0/out" 0.876106
+cap "3-stage_cs-vco_dp9_0/out" "3-stage_cs-vco_dp9_0/vdd" 1.59677
+cap "FD_v5_0/Clkb_int" "3-stage_cs-vco_dp9_0/out" 1.03321
+cap "FD_v5_0/Clk_Out" "FD_v5_0/7" 3.88522
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg1" 7.37105
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg0" 7.61076
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/pg2" 5.31335
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/pg3" 5.28455
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/vss" 70.3896
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vdd" 29.7491
+merge "FD_v5_0/VDD" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" -13951.4 0 0 0 0 -999772 -47606 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -278714 -964 1959366 -74764 125300 -6284 -157760 -3748 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "vdd"
+merge "vdd" "m1_n889_1476#"
+merge "m1_n889_1476#" "sky130_fd_sc_hd__clkbuf_16_2/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VPWR" "sky130_fd_sc_hd__clkbuf_16_2/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VPB" "sky130_fd_sc_hd__clkbuf_16_3/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_3/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VPB" "sky130_fd_sc_hd__clkbuf_16_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VPWR" "sky130_fd_sc_hd__clkbuf_16_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VPB" "sky130_fd_sc_hd__clkbuf_16_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VPWR" "sky130_fd_sc_hd__clkbuf_16_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_2_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VPWR" "sky130_fd_sc_hd__clkbuf_2_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VPB" "sky130_fd_sc_hd__clkbuf_2_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VPWR" "sky130_fd_sc_hd__clkbuf_2_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VPB" "sky130_fd_sc_hd__clkbuf_4_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VPWR" "sky130_fd_sc_hd__clkbuf_4_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VPB" "sky130_fd_sc_hd__clkbuf_4_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VPWR" "sky130_fd_sc_hd__clkbuf_4_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VPB" "sky130_fd_sc_hd__clkbuf_8_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VPWR" "sky130_fd_sc_hd__clkbuf_8_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VPWR" "sky130_fd_sc_hd__clkbuf_8_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VPB" "FD_v2_1/VDD"
+merge "FD_v2_1/VDD" "FD_v2_6/VDD"
+merge "FD_v2_6/VDD" "FD_v2_7/VDD"
+merge "FD_v2_7/VDD" "FD_v2_8/VDD"
+merge "FD_v2_8/VDD" "FD_v2_5/VDD"
+merge "FD_v2_5/VDD" "FD_v2_2/VDD"
+merge "FD_v2_2/VDD" "3-stage_cs-vco_dp9_0/vdd"
+merge "3-stage_cs-vco_dp9_0/vdd" "FD_v2_9/VDD"
+merge "FD_v2_9/VDD" "FD_v2_4/VDD"
+merge "FD_v2_4/VDD" "FD_v2_3/VDD"
+merge "FD_v2_3/VDD" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "w_7680_n1770#"
+merge "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "vss" -17638.1 0 0 0 0 0 0 0 0 0 0 -239136 -408 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -362814 -964 3373368 -73630 311932 -3614 35550 -280 0 0 0 0 0 0
+merge "vss" "sky130_fd_sc_hd__clkbuf_16_2/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VNB" "sky130_fd_sc_hd__clkbuf_16_2/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VGND" "sky130_fd_sc_hd__clkbuf_16_3/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VNB" "sky130_fd_sc_hd__clkbuf_16_3/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VGND" "FD_v5_0/GND"
+merge "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_16_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VNB" "sky130_fd_sc_hd__clkbuf_16_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VGND" "sky130_fd_sc_hd__clkbuf_16_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VNB" "sky130_fd_sc_hd__clkbuf_16_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VGND" "sky130_fd_sc_hd__clkbuf_2_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VNB" "sky130_fd_sc_hd__clkbuf_2_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VGND" "sky130_fd_sc_hd__clkbuf_2_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VNB" "sky130_fd_sc_hd__clkbuf_2_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VGND" "sky130_fd_sc_hd__clkbuf_4_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VNB" "sky130_fd_sc_hd__clkbuf_4_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VGND" "sky130_fd_sc_hd__clkbuf_4_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VNB" "sky130_fd_sc_hd__clkbuf_4_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VGND" "sky130_fd_sc_hd__clkbuf_8_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VNB" "sky130_fd_sc_hd__clkbuf_8_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VGND" "sky130_fd_sc_hd__clkbuf_8_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VGND" "FD_v2_1/GND"
+merge "FD_v2_1/GND" "FD_v2_6/GND"
+merge "FD_v2_6/GND" "FD_v2_7/GND"
+merge "FD_v2_7/GND" "FD_v2_8/GND"
+merge "FD_v2_8/GND" "FD_v2_5/GND"
+merge "FD_v2_5/GND" "FD_v2_2/GND"
+merge "FD_v2_2/GND" "FD_v2_9/GND"
+merge "FD_v2_9/GND" "FD_v2_4/GND"
+merge "FD_v2_4/GND" "FD_v2_3/GND"
+merge "FD_v2_3/GND" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" "3-stage_cs-vco_dp9_0/vss"
+merge "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "a_8547_n771#"
+merge "3-stage_cs-vco_dp9_0/vco_switch_p_2/sel" "3-stage_cs-vco_dp9_0/sel2" -103.843 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -924 -122 10800 -320 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/sel2" "vsel2"
+merge "vsel2" "m2_n2159_1718#"
+merge "sky130_fd_sc_hd__clkbuf_16_2/X" "sky130_fd_sc_hd__clkbuf_16_3/X" -412.327 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10134 -924 0 0 120594 -2116 39240 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_3/X" "out_div128_buf"
+merge "FD_v5_0/Clk_Out" "FD_v2_1/Clk_In" -40.9159 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12486 -160 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_1/Clk_In" "m1_7680_300#"
+merge "FD_v2_6/Clk_In" "FD_v2_5/Clk_Out" -1.239 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19540 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_2_0/X" "sky130_fd_sc_hd__clkbuf_4_0/A" -114.439 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14144 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_4_0/A" "li_8782_n1210#"
+merge "FD_v2_1/Clk_Out" "FD_v2_2/Clk_In" -5.6304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12784 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_2/A" "sky130_fd_sc_hd__clkbuf_16_3/A" -619.566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -26456 -746 0 0 -120400 -5600 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_3/A" "sky130_fd_sc_hd__clkbuf_16_0/X"
+merge "sky130_fd_sc_hd__clkbuf_16_0/X" "li_8587_462#"
+merge "3-stage_cs-vco_dp9_0/vctrl" "vctrl" -110.952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14444 -430 0 0 0 0 0 0 0 0 0 0
+merge "vctrl" "m1_n2159_n461#"
+merge "sky130_fd_sc_hd__clkbuf_2_1/A" "FD_v2_6/Clk_Out" -93.6667 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4252 -136 819 -136 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_6/Clk_Out" "FD_v2_7/Clk_In"
+merge "FD_v2_7/Clk_In" "li_8577_n451#"
+merge "sky130_fd_sc_hd__clkbuf_4_1/X" "sky130_fd_sc_hd__clkbuf_8_1/A" -71.3998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71217 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_1/A" "li_9325_n451#"
+merge "3-stage_cs-vco_dp9_0/sel0" "vsel0" -81.2058 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -832 -116 -4200 -290 0 0 0 0 0 0 0 0
+merge "vsel0" "m2_n2159_1958#"
+merge "sky130_fd_sc_hd__clkbuf_2_0/A" "FD_v2_7/Clk_Out" -244.308 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2304 -192 58310 -482 47520 0 0 0 0 0 0 0 0 0
+merge "FD_v2_7/Clk_Out" "FD_v2_8/Clk_In"
+merge "FD_v2_8/Clk_In" "li_8588_n1221#"
+merge "3-stage_cs-vco_dp9_0/sel1" "vsel1" -98.7726 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -924 -122 -4480 -304 0 0 0 0 0 0 0 0
+merge "vsel1" "m2_n2159_1798#"
+merge "3-stage_cs-vco_dp9_0/sel3" "vsel3" -109.501 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11484 -122 8560 -290 0 0 0 0 0 0 0 0
+merge "vsel3" "m2_n2159_1638#"
+merge "FD_v2_9/Clk_In" "FD_v2_8/Clk_Out" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_4_0/X" "sky130_fd_sc_hd__clkbuf_8_0/A" -106.451 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13158 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_0/A" "li_9326_n1210#"
+merge "FD_v2_5/Clk_In" "FD_v2_4/Clk_Out" -22.3913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13002 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_1/X" "out_div256_buf" -132.952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30832 -338 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_3/Clk_In" "FD_v2_2/Clk_Out" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_2_1/X" "sky130_fd_sc_hd__clkbuf_4_1/A" -115.438 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32143 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_4_1/A" "li_8789_n451#"
+merge "FD_v2_3/Clk_Out" "FD_v2_4/Clk_In" -59.5376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8696 -318 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_4/Clk_In" "m1_2161_286#"
+merge "sky130_fd_sc_hd__clkbuf_16_1/A" "sky130_fd_sc_hd__clkbuf_8_0/X" -74.8368 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18292 -408 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_0/X" "li_10187_n1210#"
+merge "sky130_fd_sc_hd__clkbuf_16_0/A" "sky130_fd_sc_hd__clkbuf_8_1/X" -175.416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -11590 -408 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_1/X" "li_10185_n451#"
+merge "FD_v5_0/Clk_In" "3-stage_cs-vco_dp9_0/out" -155.652 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -89099 -472 0 0 0 0 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/out" "out"
diff --git a/mag/3-stage_cs-vco_dp9/vco_with_fdivs.mag b/mag/3-stage_cs-vco_dp9/vco_with_fdivs.mag
new file mode 100644
index 0000000..80e1091
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_with_fdivs.mag
@@ -0,0 +1,879 @@
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+rect 5840 -1732 7937 -1730
+rect 7997 -1732 8006 -1672
+rect 7925 -1742 8006 -1732
+<< via2 >>
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+rect -2043 2463 -1953 2553
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+<< metal3 >>
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+rect -1830 2723 -1825 2813
+rect -1735 2723 -1730 2813
+rect -1830 2718 -1730 2723
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+rect 7932 -1672 8002 -1667
+rect 7932 -1732 7937 -1672
+rect 7997 -1732 8002 -1672
+rect 7932 -1737 8002 -1732
+use 3-stage_cs-vco_dp9 3-stage_cs-vco_dp9_0
+timestamp 1647616625
+transform 1 0 25 0 1 226
+box -1753 -1641 2093 2641
+use FD_v2 FD_v2_1
+timestamp 1647613837
+transform -1 0 7748 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_2
+timestamp 1647613837
+transform -1 0 5933 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_3
+timestamp 1647613837
+transform -1 0 4118 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_4
+timestamp 1647613837
+transform 1 0 2167 0 1 -83
+box 68 -697 1883 34
+use FD_v2 FD_v2_5
+timestamp 1647613837
+transform 1 0 3982 0 1 -83
+box 68 -697 1883 34
+use FD_v2 FD_v2_6
+timestamp 1647613837
+transform 1 0 5797 0 1 -83
+box 68 -697 1883 34
+use FD_v2 FD_v2_7
+timestamp 1647613837
+transform -1 0 7748 0 -1 -1491
+box 68 -697 1883 34
+use FD_v2 FD_v2_8
+timestamp 1647613837
+transform -1 0 5933 0 -1 -1491
+box 68 -697 1883 34
+use FD_v2 FD_v2_9
+timestamp 1647613837
+transform -1 0 4118 0 -1 -1491
+box 68 -697 1883 34
+use FD_v5 FD_v5_0
+timestamp 1647613837
+transform 1 0 2617 0 1 1451
+box -383 -769 5544 178
+use sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_2_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1646908997
+transform 1 0 8488 0 -1 -962
+box -38 -48 406 592
+use sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_2_1
+timestamp 1646908997
+transform 1 0 8488 0 1 -657
+box -38 -48 406 592
+use sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_4_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1646908997
+transform 1 0 8856 0 -1 -962
+box -38 -48 590 592
+use sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_4_1
+timestamp 1646908997
+transform 1 0 8856 0 1 -657
+box -38 -48 590 592
+use sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1646908997
+transform 1 0 9408 0 -1 -962
+box -38 -48 1050 592
+use sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_8_1
+timestamp 1646908997
+transform 1 0 9408 0 1 -657
+box -38 -48 1050 592
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1646908997
+transform 1 0 10400 0 1 -657
+box -38 -48 1878 592
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_1
+timestamp 1646908997
+transform 1 0 10400 0 -1 -962
+box -38 -48 1878 592
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_2
+timestamp 1646908997
+transform -1 0 12240 0 -1 687
+box -38 -48 1878 592
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_3
+timestamp 1646908997
+transform 1 0 8560 0 -1 687
+box -38 -48 1878 592
+<< labels >>
+rlabel metal1 1732 2426 1789 2460 1 vdd
+port 3 n
+rlabel metal1 -1407 1757 -1384 1783 1 vsel0
+port 5 n
+rlabel metal1 -1330 1605 -1307 1631 1 vsel1
+port 6 n
+rlabel metal1 -1248 1534 -1225 1560 1 vsel2
+port 7 n
+rlabel metal1 -1161 1449 -1138 1475 1 vsel3
+port 8 n
+rlabel metal1 -1702 -522 -1659 -476 1 vctrl
+port 1 n
+rlabel locali 1902 1080 1947 1117 1 out
+rlabel metal1 1994 2687 2051 2721 1 vss
+port 4 n
+rlabel metal2 12803 879 12857 931 1 out_div128_buf
+port 2 n
+rlabel metal2 12793 -1239 12853 -1185 1 out_div256_buf
+port 9 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/vco_with_fdivs.spice b/mag/3-stage_cs-vco_dp9/vco_with_fdivs.spice
new file mode 100755
index 0000000..6185f72
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_with_fdivs.spice
@@ -0,0 +1,433 @@
+* NGSPICE file created from vco_with_fdivs.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hd__clkbuf_8 A VGND VPWR X VNB VPB
+X0 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.65e+12p pd=1.53e+07u as=2.8e+11p ps=2.56e+06u w=1e+06u l=150000u
+X1 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=1.12e+12p ps=1.024e+07u w=1e+06u l=150000u
+X2 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=4.704e+11p pd=5.6e+06u as=6.951e+11p ps=8.35e+06u w=420000u l=150000u
+X5 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.176e+11p ps=1.4e+06u w=420000u l=150000u
+X9 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X17 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X19 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_4 A VGND VPWR X VNB VPB
+X0 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=9.1e+11p pd=7.82e+06u as=2.65e+11p ps=2.53e+06u w=1e+06u l=150000u
+X1 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=3.801e+11p pd=4.33e+06u as=2.352e+11p ps=2.8e+06u w=420000u l=150000u
+X2 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=5.6e+11p pd=5.12e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=150000u
+X6 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VPWR X VNB VPB
+X0 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=5.85e+11p pd=5.17e+06u as=2.65e+11p ps=2.53e+06u w=1e+06u l=150000u
+X1 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X2 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=2.457e+11p pd=2.85e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.134e+11p pd=1.38e+06u as=0p ps=0u w=420000u l=150000u
+X5 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt FD_v5 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb_buf 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPTgate2 5 6 5 6 Clk_In_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VPWR X VNB VPB
+X0 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=3.045e+12p pd=2.809e+07u as=5.6e+11p ps=5.12e+06u w=1e+06u l=150000u
+X1 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.24e+12p ps=2.048e+07u w=1e+06u l=150000u
+X2 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=2.352e+11p pd=2.8e+06u as=1.2789e+12p ps=1.533e+07u w=420000u l=150000u
+X8 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=9.408e+11p ps=1.12e+07u w=420000u l=150000u
+X9 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X17 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X18 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X20 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X22 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X26 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X28 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X29 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X30 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X33 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X36 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X37 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X38 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X39 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel3 sel2 vss vdd
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128_buf vdd vss vsel0 vsel1 vsel2 vsel3 out_div256_buf
+Xsky130_fd_sc_hd__clkbuf_8_1 sky130_fd_sc_hd__clkbuf_8_1/A vss vdd sky130_fd_sc_hd__clkbuf_8_1/X
++ vss vdd sky130_fd_sc_hd__clkbuf_8
+XFD_v2_3 FD_v2_3/Clk_In vdd vss FD_v2_4/Clk_In FD_v2
+XFD_v2_4 FD_v2_4/Clk_In vdd vss FD_v2_5/Clk_In FD_v2
+XFD_v2_5 FD_v2_5/Clk_In vdd vss FD_v2_6/Clk_In FD_v2
+XFD_v2_6 FD_v2_6/Clk_In vdd vss FD_v2_7/Clk_In FD_v2
+XFD_v2_7 FD_v2_7/Clk_In vdd vss FD_v2_8/Clk_In FD_v2
+XFD_v2_8 FD_v2_8/Clk_In vdd vss FD_v2_9/Clk_In FD_v2
+Xsky130_fd_sc_hd__clkbuf_4_0 sky130_fd_sc_hd__clkbuf_4_0/A vss vdd sky130_fd_sc_hd__clkbuf_8_0/A
++ vss vdd sky130_fd_sc_hd__clkbuf_4
+XFD_v2_9 FD_v2_9/Clk_In vdd vss FD_v2_9/Clk_Out FD_v2
+Xsky130_fd_sc_hd__clkbuf_4_1 sky130_fd_sc_hd__clkbuf_4_1/A vss vdd sky130_fd_sc_hd__clkbuf_8_1/A
++ vss vdd sky130_fd_sc_hd__clkbuf_4
+Xsky130_fd_sc_hd__clkbuf_2_0 FD_v2_8/Clk_In vss vdd sky130_fd_sc_hd__clkbuf_4_0/A
++ vss vdd sky130_fd_sc_hd__clkbuf_2
+Xsky130_fd_sc_hd__clkbuf_2_1 FD_v2_7/Clk_In vss vdd sky130_fd_sc_hd__clkbuf_4_1/A
++ vss vdd sky130_fd_sc_hd__clkbuf_2
+XFD_v5_0 out vdd vss FD_v2_1/Clk_In FD_v5
+Xsky130_fd_sc_hd__clkbuf_16_0 sky130_fd_sc_hd__clkbuf_8_1/X vss vdd sky130_fd_sc_hd__clkbuf_16_3/A
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_1 sky130_fd_sc_hd__clkbuf_8_0/X vss vdd out_div256_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_2 sky130_fd_sc_hd__clkbuf_16_3/A vss vdd out_div128_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_3 sky130_fd_sc_hd__clkbuf_16_3/A vss vdd out_div128_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel3 vsel2 vss vdd x3-stage_cs-vco_dp9
+XFD_v2_1 FD_v2_1/Clk_In vdd vss FD_v2_2/Clk_In FD_v2
+Xsky130_fd_sc_hd__clkbuf_8_0 sky130_fd_sc_hd__clkbuf_8_0/A vss vdd sky130_fd_sc_hd__clkbuf_8_0/X
++ vss vdd sky130_fd_sc_hd__clkbuf_8
+XFD_v2_2 FD_v2_2/Clk_In vdd vss FD_v2_3/Clk_In FD_v2
+.ends
+
diff --git a/mag/3-stage_cs-vco_dp9/vco_with_fdivs_-_before_adding_BB.mag b/mag/3-stage_cs-vco_dp9/vco_with_fdivs_-_before_adding_BB.mag
new file mode 100755
index 0000000..47f6bcc
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_with_fdivs_-_before_adding_BB.mag
@@ -0,0 +1,469 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647518745
+<< pwell >>
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+<< locali >>
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+rect 4075 -1555 5888 -1465
+rect 5978 -1555 7584 -1465
+rect 7674 -1555 7680 -1465
+rect 1703 -1565 7680 -1555
+<< via1 >>
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+rect -96 2282 -6 2372
+rect 987 2282 1077 2372
+rect 2233 1596 2323 1686
+rect 3977 1596 4067 1686
+rect 5786 1596 5876 1686
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+<< metal2 >>
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+rect -1820 2372 -1740 2376
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+rect -1825 2287 -1820 2367
+rect -1740 2287 -1047 2367
+rect -1825 2282 -1047 2287
+rect -957 2282 -96 2372
+rect -6 2282 987 2372
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+rect -1820 2278 -1740 2282
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+rect -2159 1798 -1238 1838
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+<< via2 >>
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+<< metal3 >>
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+use 3-stage_cs-vco_dp9 3-stage_cs-vco_dp9_0
+timestamp 1647518745
+transform 1 0 25 0 1 226
+box -1753 -1641 2093 2641
+use FD_v2 FD_v2_1
+timestamp 1647518745
+transform -1 0 7748 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_2
+timestamp 1647518745
+transform -1 0 5933 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_3
+timestamp 1647518745
+transform -1 0 4118 0 -1 -29
+box 68 -697 1883 34
+use FD_v2 FD_v2_4
+timestamp 1647518745
+transform 1 0 2167 0 1 -83
+box 68 -697 1883 34
+use FD_v2 FD_v2_5
+timestamp 1647518745
+transform 1 0 3982 0 1 -83
+box 68 -697 1883 34
+use FD_v2 FD_v2_6
+timestamp 1647518745
+transform 1 0 5797 0 1 -83
+box 68 -697 1883 34
+use FD_v2 FD_v2_7
+timestamp 1647518745
+transform -1 0 7748 0 -1 -1491
+box 68 -697 1883 34
+use FD_v2 FD_v2_8
+timestamp 1647518745
+transform -1 0 5933 0 -1 -1491
+box 68 -697 1883 34
+use FD_v2 FD_v2_9
+timestamp 1647518745
+transform -1 0 4118 0 -1 -1491
+box 68 -697 1883 34
+use FD_v5 FD_v5_0
+timestamp 1647518745
+transform 1 0 2617 0 1 1451
+box -383 -769 5544 178
+<< labels >>
+rlabel metal1 1732 2426 1789 2460 1 vdd
+port 3 n
+rlabel metal1 -1407 1757 -1384 1783 1 vsel0
+port 5 n
+rlabel metal1 -1330 1605 -1307 1631 1 vsel1
+port 6 n
+rlabel metal1 -1248 1534 -1225 1560 1 vsel2
+port 7 n
+rlabel metal1 -1161 1449 -1138 1475 1 vsel3
+port 8 n
+rlabel metal1 -1702 -522 -1659 -476 1 vctrl
+port 1 n
+rlabel locali 1902 1080 1947 1117 1 out
+rlabel metal1 7700 -1150 7726 -1133 1 out_div128
+port 2 n
+rlabel via1 5865 -1152 5891 -1131 1 out_div256
+port 9 n
+rlabel metal1 1994 2687 2051 2721 1 vss
+port 4 n
+<< end >>
diff --git a/mag/3-stage_cs-vco_dp9/vco_with_fdivs_POST_LAYOUT_tb.log b/mag/3-stage_cs-vco_dp9/vco_with_fdivs_POST_LAYOUT_tb.log
new file mode 100755
index 0000000..f527e4f
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_with_fdivs_POST_LAYOUT_tb.log
@@ -0,0 +1,1481 @@
+
+Compatibility modes selected: hs a
+
+Warning: m=xx on .subckt line will override multiplier m hierarchy!
+
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 -6.57436e-06
+x1.fd_v2_3/clk_in 1.79996
+x1.fd_v2_3/3 -1.30231e-05
+x1.fd_v2_3/6 0.792592
+x1.fd_v2_3/clkb -1.39191e-05
+x1.fd_v2_3/5 1.79999
+net1 1.8
+x1.fd_v2_3/2 1.66508
+x1.fd_v2_4/clk_in 6.92777e-06
+x1.fd_v2_3/7 1.66509
+x1.fd_v2_4/4 0.81231
+x1.fd_v2_4/3 1.8
+x1.fd_v2_4/6 1.58948
+x1.fd_v2_4/clkb 1.8
+x1.fd_v2_4/5 1.58948
+x1.fd_v2_4/2 2.08479e-05
+x1.fd_v2_5/clk_in 1.80004
+x1.fd_v2_4/7 1.01381e-05
+x1.fd_v2_5/4 -3.45216e-06
+x1.fd_v2_5/3 -1.00752e-05
+x1.fd_v2_5/6 0.794419
+x1.fd_v2_5/clkb -3.70911e-05
+x1.fd_v2_5/5 1.79999
+x1.fd_v2_5/2 1.66028
+x1.fd_v2_6/clk_in -4.25264e-06
+x1.fd_v2_5/7 1.66051
+x1.fd_v2_6/4 0.808828
+x1.fd_v2_6/3 1.8
+x1.fd_v2_6/6 1.60655
+x1.fd_v2_6/clkb 1.80012
+x1.fd_v2_6/5 1.60641
+x1.fd_v2_6/2 -5.8657e-05
+out_div128_buf 1.8
+x1.fd_v2_6/7 -6.09207e-05
+x1.fd_v2_7/4 1.26016e-05
+x1.fd_v2_7/3 4.71267e-06
+x1.fd_v2_7/6 0.79495
+x1.fd_v2_7/clkb 2.0188e-06
+x1.fd_v2_7/5 1.8
+x1.fd_v2_7/2 1.65837
+out_div256_buf 7.70075e-06
+x1.fd_v2_7/7 1.65837
+x1.fd_v2_8/4 0.810461
+x1.fd_v2_8/3 1.8
+x1.fd_v2_8/6 1.59917
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 1.59917
+x1.fd_v2_8/2 1.81705e-05
+x1.fd_v2_9/clk_in 1.8
+x1.fd_v2_8/7 1.55651e-05
+x1.fd_v2_9/4 1.11543e-05
+x1.fd_v2_9/3 3.14149e-06
+x1.fd_v2_9/6 0.79617
+x1.fd_v2_9/clkb -8.87153e-08
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 1.65471
+x1.fd_v2_9/clk_out -2.67459e-05
+x1.fd_v2_9/7 1.65471
+x1.fd_v5_0/4 1.71492
+x1.fd_v5_0/5 -0.0174329
+x1.fd_v5_0/2 1.79636
+x1.fd_v5_0/3 -0.00543058
+x1.fd_v5_0/clkb_buf 1.79505
+x1.fd_v5_0/clk_in_buf 0.00351015
+x1.fd_v5_0/clkb_int 1.79665
+x1.fd_v5_0/dus -0.00627537
+x1.fd_v5_0/6 0.00535738
+x1.fd_v5_0/7 1.79267
+x1.fd_v2_1/clk_in -0.040032
+x1.out -0.0161395
+x1.3-stage_cs-vco_dp9_0/net7 1.79442
+x1.x3-stage_cs-vco_dp9_0.net6 -0.00315382
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.70271
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.982534
+x1.3-stage_cs-vco_dp9_0/ng3 2.69135e-05
+x1.x3-stage_cs-vco_dp9_0.ng0 1.50189e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -2.46251e-05
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 2.05503e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -2.27226e-05
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 2.75821e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -2.21318e-05
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.69716e-05
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.983204
+x1.x3-stage_cs-vco_dp9_0.net5 1.8048
+x1.x3-stage_cs-vco_dp9_0.net2 1.03367
+x1.x3-stage_cs-vco_dp9_0.net4 0.0707445
+x1.x3-stage_cs-vco_dp9_0.pg3 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg0 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -6.50028e-05
+x1.x3-stage_cs-vco_dp9_0.pg1 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg2 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -6.51181e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -6.44664e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -6.31688e-05
+x1.fd_v2_1/4 -0.0548854
+x1.fd_v2_1/3 1.79947
+x1.fd_v2_1/6 1.79922
+x1.fd_v2_1/clkb 1.78983
+x1.fd_v2_1/5 1.79472
+x1.fd_v2_1/2 -0.00524352
+x1.fd_v2_2/clk_in 1.80761
+x1.fd_v2_1/7 0.0210799
+x1.fd_v2_2/4 1.80609
+x1.fd_v2_2/3 1.81536
+x1.fd_v2_2/6 1.54268
+x1.fd_v2_2/clkb 0.031251
+x1.fd_v2_2/5 0.0428536
+x1.fd_v2_2/2 0.000697906
+x1.fd_v2_2/7 -0.000309931
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 1.79998
+buf2a_out 1.79999
+buf4a_out 1.8
+buf8a_out 1.8
+pad_out_a 1.8
+buf1b_out -3.84638e-05
+buf2b_out -4.29694e-05
+buf4b_out -4.55334e-05
+buf8b_out -4.40379e-05
+pad_out_b -2.21527e-05
+v1#branch 5.53124e-08
+vsel3#branch 5.70942e-09
+vsel2#branch 1.5568e-08
+vsel1#branch 1.96122e-08
+vsel0#branch 2.00558e-08
+vmeas_current_gnd#branch -2.14417e-05
+vmeas_current_vdd#branch -5.47662e-05
+v2#branch 5.48476e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.528939e-10 targ= 1.539824e-08 trig= 1.514535e-08
+fvco_outside_while = 3.95423e+09
+tdiv128_outside_while= 3.237513e-08 targ= 6.527883e-08 trig= 3.290371e-08
+fdiv128_outside_while= 3.08879e+07
+supply_current_rms_outside_while= 2.17800e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 4.83096e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 9.000000e-01 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.837548e+00 at= 1.659500e-08
+vlow_outside_while = -8.147867e-05 at= 1.969500e-08
+peak_to_peak_outside_while= 1.83763e+00
+supply_current_rms = 2.14811e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 -6.57436e-06
+x1.fd_v2_3/clk_in 1.79996
+x1.fd_v2_3/3 -1.30231e-05
+x1.fd_v2_3/6 0.792592
+x1.fd_v2_3/clkb -1.39191e-05
+x1.fd_v2_3/5 1.79999
+net1 1.8
+x1.fd_v2_3/2 1.66508
+x1.fd_v2_4/clk_in 6.92777e-06
+x1.fd_v2_3/7 1.66509
+x1.fd_v2_4/4 0.81231
+x1.fd_v2_4/3 1.8
+x1.fd_v2_4/6 1.58948
+x1.fd_v2_4/clkb 1.8
+x1.fd_v2_4/5 1.58948
+x1.fd_v2_4/2 2.08479e-05
+x1.fd_v2_5/clk_in 1.80004
+x1.fd_v2_4/7 1.01381e-05
+x1.fd_v2_5/4 -3.45216e-06
+x1.fd_v2_5/3 -1.00752e-05
+x1.fd_v2_5/6 0.794419
+x1.fd_v2_5/clkb -3.70911e-05
+x1.fd_v2_5/5 1.79999
+x1.fd_v2_5/2 1.66028
+x1.fd_v2_6/clk_in -4.25264e-06
+x1.fd_v2_5/7 1.66051
+x1.fd_v2_6/4 0.808828
+x1.fd_v2_6/3 1.8
+x1.fd_v2_6/6 1.60655
+x1.fd_v2_6/clkb 1.80012
+x1.fd_v2_6/5 1.60641
+x1.fd_v2_6/2 -5.8657e-05
+out_div128_buf 1.8
+x1.fd_v2_6/7 -6.09207e-05
+x1.fd_v2_7/4 1.26016e-05
+x1.fd_v2_7/3 4.71267e-06
+x1.fd_v2_7/6 0.79495
+x1.fd_v2_7/clkb 2.0188e-06
+x1.fd_v2_7/5 1.8
+x1.fd_v2_7/2 1.65837
+out_div256_buf 7.70075e-06
+x1.fd_v2_7/7 1.65837
+x1.fd_v2_8/4 0.810461
+x1.fd_v2_8/3 1.8
+x1.fd_v2_8/6 1.59917
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 1.59917
+x1.fd_v2_8/2 1.81705e-05
+x1.fd_v2_9/clk_in 1.8
+x1.fd_v2_8/7 1.55651e-05
+x1.fd_v2_9/4 1.11543e-05
+x1.fd_v2_9/3 3.14149e-06
+x1.fd_v2_9/6 0.79617
+x1.fd_v2_9/clkb -8.87153e-08
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 1.65471
+x1.fd_v2_9/clk_out -2.67459e-05
+x1.fd_v2_9/7 1.65471
+x1.fd_v5_0/4 1.71492
+x1.fd_v5_0/5 -0.0174329
+x1.fd_v5_0/2 1.79636
+x1.fd_v5_0/3 -0.00543058
+x1.fd_v5_0/clkb_buf 1.79505
+x1.fd_v5_0/clk_in_buf 0.00351015
+x1.fd_v5_0/clkb_int 1.79665
+x1.fd_v5_0/dus -0.00627537
+x1.fd_v5_0/6 0.00535738
+x1.fd_v5_0/7 1.79267
+x1.fd_v2_1/clk_in -0.040032
+x1.out -0.0161395
+x1.3-stage_cs-vco_dp9_0/net7 1.79442
+x1.x3-stage_cs-vco_dp9_0.net6 -0.00315382
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.70271
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.982534
+x1.3-stage_cs-vco_dp9_0/ng3 2.69135e-05
+x1.x3-stage_cs-vco_dp9_0.ng0 1.50189e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -2.46251e-05
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 2.05503e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -2.27226e-05
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 2.75821e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -2.21318e-05
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.69716e-05
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.983204
+x1.x3-stage_cs-vco_dp9_0.net5 1.8048
+x1.x3-stage_cs-vco_dp9_0.net2 1.03367
+x1.x3-stage_cs-vco_dp9_0.net4 0.0707445
+x1.x3-stage_cs-vco_dp9_0.pg3 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg0 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -6.50028e-05
+x1.x3-stage_cs-vco_dp9_0.pg1 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg2 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -6.51181e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -6.44664e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -6.31688e-05
+x1.fd_v2_1/4 -0.0548854
+x1.fd_v2_1/3 1.79947
+x1.fd_v2_1/6 1.79922
+x1.fd_v2_1/clkb 1.78983
+x1.fd_v2_1/5 1.79472
+x1.fd_v2_1/2 -0.00524352
+x1.fd_v2_2/clk_in 1.80761
+x1.fd_v2_1/7 0.0210799
+x1.fd_v2_2/4 1.80609
+x1.fd_v2_2/3 1.81536
+x1.fd_v2_2/6 1.54268
+x1.fd_v2_2/clkb 0.031251
+x1.fd_v2_2/5 0.0428536
+x1.fd_v2_2/2 0.000697906
+x1.fd_v2_2/7 -0.000309931
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 1.79998
+buf2a_out 1.79999
+buf4a_out 1.8
+buf8a_out 1.8
+pad_out_a 1.8
+buf1b_out -3.84638e-05
+buf2b_out -4.29694e-05
+buf4b_out -4.55334e-05
+buf8b_out -4.40379e-05
+pad_out_b -2.21527e-05
+v1#branch 5.53124e-08
+vsel3#branch 5.70942e-09
+vsel2#branch 1.5568e-08
+vsel1#branch 1.96122e-08
+vsel0#branch 2.00558e-08
+vmeas_current_gnd#branch -2.14417e-05
+vmeas_current_vdd#branch -5.47662e-05
+v2#branch 5.48476e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.451055e-10 targ= 1.471577e-08 trig= 1.447066e-08
+fvco_outside_while = 4.07988e+09
+tdiv128_outside_while= 4.702415e-08 targ= 9.069466e-08 trig= 4.367051e-08
+fdiv128_outside_while= 2.12657e+07
+supply_current_rms_outside_while= 2.10806e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.27561e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.100000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.807033e+00 at= 1.999500e-08
+vlow_outside_while = 1.798545e+00 at= 1.995500e-08
+peak_to_peak_outside_while= 8.48762e-03
+supply_current_rms = 2.07875e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 -6.57436e-06
+x1.fd_v2_3/clk_in 1.79996
+x1.fd_v2_3/3 -1.30231e-05
+x1.fd_v2_3/6 0.792592
+x1.fd_v2_3/clkb -1.39191e-05
+x1.fd_v2_3/5 1.79999
+net1 1.8
+x1.fd_v2_3/2 1.66508
+x1.fd_v2_4/clk_in 6.92777e-06
+x1.fd_v2_3/7 1.66509
+x1.fd_v2_4/4 0.81231
+x1.fd_v2_4/3 1.8
+x1.fd_v2_4/6 1.58948
+x1.fd_v2_4/clkb 1.8
+x1.fd_v2_4/5 1.58948
+x1.fd_v2_4/2 2.08479e-05
+x1.fd_v2_5/clk_in 1.80004
+x1.fd_v2_4/7 1.01381e-05
+x1.fd_v2_5/4 -3.45216e-06
+x1.fd_v2_5/3 -1.00752e-05
+x1.fd_v2_5/6 0.794419
+x1.fd_v2_5/clkb -3.70911e-05
+x1.fd_v2_5/5 1.79999
+x1.fd_v2_5/2 1.66028
+x1.fd_v2_6/clk_in -4.25264e-06
+x1.fd_v2_5/7 1.66051
+x1.fd_v2_6/4 0.808828
+x1.fd_v2_6/3 1.8
+x1.fd_v2_6/6 1.60655
+x1.fd_v2_6/clkb 1.80012
+x1.fd_v2_6/5 1.60641
+x1.fd_v2_6/2 -5.8657e-05
+out_div128_buf 1.8
+x1.fd_v2_6/7 -6.09207e-05
+x1.fd_v2_7/4 1.26016e-05
+x1.fd_v2_7/3 4.71267e-06
+x1.fd_v2_7/6 0.79495
+x1.fd_v2_7/clkb 2.0188e-06
+x1.fd_v2_7/5 1.8
+x1.fd_v2_7/2 1.65837
+out_div256_buf 7.70075e-06
+x1.fd_v2_7/7 1.65837
+x1.fd_v2_8/4 0.810461
+x1.fd_v2_8/3 1.8
+x1.fd_v2_8/6 1.59917
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 1.59917
+x1.fd_v2_8/2 1.81705e-05
+x1.fd_v2_9/clk_in 1.8
+x1.fd_v2_8/7 1.55651e-05
+x1.fd_v2_9/4 1.11543e-05
+x1.fd_v2_9/3 3.14149e-06
+x1.fd_v2_9/6 0.79617
+x1.fd_v2_9/clkb -8.87153e-08
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 1.65471
+x1.fd_v2_9/clk_out -2.67459e-05
+x1.fd_v2_9/7 1.65471
+x1.fd_v5_0/4 1.71492
+x1.fd_v5_0/5 -0.0174329
+x1.fd_v5_0/2 1.79636
+x1.fd_v5_0/3 -0.00543058
+x1.fd_v5_0/clkb_buf 1.79505
+x1.fd_v5_0/clk_in_buf 0.00351015
+x1.fd_v5_0/clkb_int 1.79665
+x1.fd_v5_0/dus -0.00627537
+x1.fd_v5_0/6 0.00535738
+x1.fd_v5_0/7 1.79267
+x1.fd_v2_1/clk_in -0.040032
+x1.out -0.0161395
+x1.3-stage_cs-vco_dp9_0/net7 1.79442
+x1.x3-stage_cs-vco_dp9_0.net6 -0.00315382
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.70271
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.982534
+x1.3-stage_cs-vco_dp9_0/ng3 2.69135e-05
+x1.x3-stage_cs-vco_dp9_0.ng0 1.50189e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -2.46251e-05
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 2.05503e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -2.27226e-05
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 2.75821e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -2.21318e-05
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.69716e-05
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.983204
+x1.x3-stage_cs-vco_dp9_0.net5 1.8048
+x1.x3-stage_cs-vco_dp9_0.net2 1.03367
+x1.x3-stage_cs-vco_dp9_0.net4 0.0707445
+x1.x3-stage_cs-vco_dp9_0.pg3 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg0 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -6.50028e-05
+x1.x3-stage_cs-vco_dp9_0.pg1 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg2 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -6.51181e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -6.44664e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -6.31688e-05
+x1.fd_v2_1/4 -0.0548854
+x1.fd_v2_1/3 1.79947
+x1.fd_v2_1/6 1.79922
+x1.fd_v2_1/clkb 1.78983
+x1.fd_v2_1/5 1.79472
+x1.fd_v2_1/2 -0.00524352
+x1.fd_v2_2/clk_in 1.80761
+x1.fd_v2_1/7 0.0210799
+x1.fd_v2_2/4 1.80609
+x1.fd_v2_2/3 1.81536
+x1.fd_v2_2/6 1.54268
+x1.fd_v2_2/clkb 0.031251
+x1.fd_v2_2/5 0.0428536
+x1.fd_v2_2/2 0.000697906
+x1.fd_v2_2/7 -0.000309931
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 1.79998
+buf2a_out 1.79999
+buf4a_out 1.8
+buf8a_out 1.8
+pad_out_a 1.8
+buf1b_out -3.84638e-05
+buf2b_out -4.29694e-05
+buf4b_out -4.55334e-05
+buf8b_out -4.40379e-05
+pad_out_b -2.21527e-05
+v1#branch 5.53124e-08
+vsel3#branch 5.70942e-09
+vsel2#branch 1.5568e-08
+vsel1#branch 1.96122e-08
+vsel0#branch 2.00558e-08
+vmeas_current_gnd#branch -2.14417e-05
+vmeas_current_vdd#branch -5.47662e-05
+v2#branch 5.48476e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.430863e-10 targ= 1.452454e-08 trig= 1.428145e-08
+fvco_outside_while = 4.11377e+09
+tdiv128_outside_while= 4.666034e-08 targ= 8.993770e-08 trig= 4.327735e-08
+fdiv128_outside_while= 2.14315e+07
+supply_current_rms_outside_while= 2.15040e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.59051e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.300000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.837946e+00 at= 1.982500e-08
+vlow_outside_while = 1.719673e-01 at= 1.999500e-08
+peak_to_peak_outside_while= 1.66598e+00
+supply_current_rms = 2.12370e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 -6.57436e-06
+x1.fd_v2_3/clk_in 1.79996
+x1.fd_v2_3/3 -1.30231e-05
+x1.fd_v2_3/6 0.792592
+x1.fd_v2_3/clkb -1.39191e-05
+x1.fd_v2_3/5 1.79999
+net1 1.8
+x1.fd_v2_3/2 1.66508
+x1.fd_v2_4/clk_in 6.92777e-06
+x1.fd_v2_3/7 1.66509
+x1.fd_v2_4/4 0.81231
+x1.fd_v2_4/3 1.8
+x1.fd_v2_4/6 1.58948
+x1.fd_v2_4/clkb 1.8
+x1.fd_v2_4/5 1.58948
+x1.fd_v2_4/2 2.08479e-05
+x1.fd_v2_5/clk_in 1.80004
+x1.fd_v2_4/7 1.01381e-05
+x1.fd_v2_5/4 -3.45216e-06
+x1.fd_v2_5/3 -1.00752e-05
+x1.fd_v2_5/6 0.794419
+x1.fd_v2_5/clkb -3.70911e-05
+x1.fd_v2_5/5 1.79999
+x1.fd_v2_5/2 1.66028
+x1.fd_v2_6/clk_in -4.25264e-06
+x1.fd_v2_5/7 1.66051
+x1.fd_v2_6/4 0.808828
+x1.fd_v2_6/3 1.8
+x1.fd_v2_6/6 1.60655
+x1.fd_v2_6/clkb 1.80012
+x1.fd_v2_6/5 1.60641
+x1.fd_v2_6/2 -5.8657e-05
+out_div128_buf 1.8
+x1.fd_v2_6/7 -6.09207e-05
+x1.fd_v2_7/4 1.26016e-05
+x1.fd_v2_7/3 4.71267e-06
+x1.fd_v2_7/6 0.79495
+x1.fd_v2_7/clkb 2.0188e-06
+x1.fd_v2_7/5 1.8
+x1.fd_v2_7/2 1.65837
+out_div256_buf 7.70075e-06
+x1.fd_v2_7/7 1.65837
+x1.fd_v2_8/4 0.810461
+x1.fd_v2_8/3 1.8
+x1.fd_v2_8/6 1.59917
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 1.59917
+x1.fd_v2_8/2 1.81705e-05
+x1.fd_v2_9/clk_in 1.8
+x1.fd_v2_8/7 1.55651e-05
+x1.fd_v2_9/4 1.11543e-05
+x1.fd_v2_9/3 3.14149e-06
+x1.fd_v2_9/6 0.79617
+x1.fd_v2_9/clkb -8.87153e-08
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 1.65471
+x1.fd_v2_9/clk_out -2.67459e-05
+x1.fd_v2_9/7 1.65471
+x1.fd_v5_0/4 1.71492
+x1.fd_v5_0/5 -0.0174329
+x1.fd_v5_0/2 1.79636
+x1.fd_v5_0/3 -0.00543058
+x1.fd_v5_0/clkb_buf 1.79505
+x1.fd_v5_0/clk_in_buf 0.00351015
+x1.fd_v5_0/clkb_int 1.79665
+x1.fd_v5_0/dus -0.00627537
+x1.fd_v5_0/6 0.00535738
+x1.fd_v5_0/7 1.79267
+x1.fd_v2_1/clk_in -0.040032
+x1.out -0.0161395
+x1.3-stage_cs-vco_dp9_0/net7 1.79442
+x1.x3-stage_cs-vco_dp9_0.net6 -0.00315382
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.70271
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.982534
+x1.3-stage_cs-vco_dp9_0/ng3 2.69135e-05
+x1.x3-stage_cs-vco_dp9_0.ng0 1.50189e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -2.46251e-05
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 2.05503e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -2.27226e-05
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 2.75821e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -2.21318e-05
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.69716e-05
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.983204
+x1.x3-stage_cs-vco_dp9_0.net5 1.8048
+x1.x3-stage_cs-vco_dp9_0.net2 1.03367
+x1.x3-stage_cs-vco_dp9_0.net4 0.0707445
+x1.x3-stage_cs-vco_dp9_0.pg3 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg0 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -6.50028e-05
+x1.x3-stage_cs-vco_dp9_0.pg1 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg2 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -6.51181e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -6.44664e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -6.31688e-05
+x1.fd_v2_1/4 -0.0548854
+x1.fd_v2_1/3 1.79947
+x1.fd_v2_1/6 1.79922
+x1.fd_v2_1/clkb 1.78983
+x1.fd_v2_1/5 1.79472
+x1.fd_v2_1/2 -0.00524352
+x1.fd_v2_2/clk_in 1.80761
+x1.fd_v2_1/7 0.0210799
+x1.fd_v2_2/4 1.80609
+x1.fd_v2_2/3 1.81536
+x1.fd_v2_2/6 1.54268
+x1.fd_v2_2/clkb 0.031251
+x1.fd_v2_2/5 0.0428536
+x1.fd_v2_2/2 0.000697906
+x1.fd_v2_2/7 -0.000309931
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 1.79998
+buf2a_out 1.79999
+buf4a_out 1.8
+buf8a_out 1.8
+pad_out_a 1.8
+buf1b_out -3.84638e-05
+buf2b_out -4.29694e-05
+buf4b_out -4.55334e-05
+buf8b_out -4.40379e-05
+pad_out_b -2.21527e-05
+v1#branch 5.53124e-08
+vsel3#branch 5.70942e-09
+vsel2#branch 1.5568e-08
+vsel1#branch 1.96122e-08
+vsel0#branch 2.00558e-08
+vmeas_current_gnd#branch -2.14417e-05
+vmeas_current_vdd#branch -5.47662e-05
+v2#branch 5.48476e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.423694e-10 targ= 1.444727e-08 trig= 1.420490e-08
+fvco_outside_while = 4.12593e+09
+tdiv128_outside_while= 4.653588e-08 targ= 8.966459e-08 trig= 4.312871e-08
+fdiv128_outside_while= 2.14888e+07
+supply_current_rms_outside_while= 2.16392e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.70654e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.500000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.837605e+00 at= 1.973500e-08
+vlow_outside_while = 1.797416e-02 at= 1.999500e-08
+peak_to_peak_outside_while= 1.81963e+00
+supply_current_rms = 2.13753e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Reset re-loads circuit ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+Circuit: ** sch_path: /home/darunix/gitsandboxes/vco/vco/xschem/vco_with_fdivs_tb.sch
+
+option SCALE: Scale is set to 1e-06 for instance and model parameters
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/net2 and x1.3-stage_cs-vco_dp9_0/net2
+
+Note: Starting dynamic gmin stepping
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Warning: Further gmin increment
+Trying gmin = 5.6234E-11 Warning: Further gmin increment
+Trying gmin = 8.6596E-11 Note: One successful gmin step
+Trying gmin = 6.9783E-11 Note: One successful gmin step
+Trying gmin = 5.0481E-11 Note: One successful gmin step
+Trying gmin = 3.1059E-11 Note: One successful gmin step
+Trying gmin = 1.4989E-11 Note: One successful gmin step
+Trying gmin = 5.0254E-12 Warning: Further gmin increment
+Trying gmin = 1.1406E-11 Note: One successful gmin step
+Trying gmin = 7.5710E-12 Note: One successful gmin step
+Trying gmin = 4.0943E-12 Warning: Further gmin increment
+Trying gmin = 6.4924E-12 Note: One successful gmin step
+Trying gmin = 5.1558E-12 Warning: Further gmin increment
+Trying gmin = 6.1289E-12 Warning: Further gmin increment
+Trying gmin = 6.3996E-12 Note: One successful gmin step
+Trying gmin = 6.2628E-12 Warning: Further gmin increment
+Trying gmin = 6.3651E-12 Note: One successful gmin step
+Trying gmin = 6.3137E-12 Note: One successful gmin step
+Trying gmin = 6.2374E-12 Note: One successful gmin step
+Trying gmin = 6.1247E-12 Note: One successful gmin step
+Trying gmin = 5.9595E-12 Note: One successful gmin step
+Trying gmin = 5.7199E-12 Note: One successful gmin step
+Trying gmin = 5.3785E-12 Note: One successful gmin step
+Trying gmin = 4.9043E-12 Note: One successful gmin step
+Trying gmin = 4.2701E-12 Note: One successful gmin step
+Trying gmin = 3.4692E-12 Note: One successful gmin step
+Trying gmin = 2.5406E-12 Note: One successful gmin step
+Trying gmin = 1.5921E-12 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Dynamic gmin stepping failed
+Note: Starting true gmin stepping
+Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Further gmin increment
+Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: Last gmin step failed
+Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: True gmin stepping failed
+Note: Starting source stepping
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+
+Trying gmin = 1.0000E-02 Note: One successful gmin step
+Trying gmin = 1.0000E-03 Note: One successful gmin step
+Trying gmin = 1.0000E-04 Note: One successful gmin step
+Trying gmin = 1.0000E-05 Note: One successful gmin step
+Trying gmin = 1.0000E-06 Note: One successful gmin step
+Trying gmin = 1.0000E-07 Note: One successful gmin step
+Trying gmin = 1.0000E-08 Note: One successful gmin step
+Trying gmin = 1.0000E-09 Note: One successful gmin step
+Trying gmin = 1.0000E-10 Note: One successful gmin step
+Trying gmin = 1.0000E-11 Note: One successful gmin step
+Trying gmin = 1.0000E-12 Note: One successful gmin step
+Note: One successful source step
+Supplies reduced to 0.1000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Supplies reduced to 0.0000% Warning: singular matrix: check nodes x1.3-stage_cs-vco_dp9_0/pg1 and x1.3-stage_cs-vco_dp9_0/pg1
+
+Warning: source stepping failed
+Note: Transient op started
+Note: Transient op finished successfully
+
+Initial Transient Solution
+--------------------------
+
+Node Voltage
+---- -------
+x1.fd_v2_3/4 -6.57436e-06
+x1.fd_v2_3/clk_in 1.79996
+x1.fd_v2_3/3 -1.30231e-05
+x1.fd_v2_3/6 0.792592
+x1.fd_v2_3/clkb -1.39191e-05
+x1.fd_v2_3/5 1.79999
+net1 1.8
+x1.fd_v2_3/2 1.66508
+x1.fd_v2_4/clk_in 6.92777e-06
+x1.fd_v2_3/7 1.66509
+x1.fd_v2_4/4 0.81231
+x1.fd_v2_4/3 1.8
+x1.fd_v2_4/6 1.58948
+x1.fd_v2_4/clkb 1.8
+x1.fd_v2_4/5 1.58948
+x1.fd_v2_4/2 2.08479e-05
+x1.fd_v2_5/clk_in 1.80004
+x1.fd_v2_4/7 1.01381e-05
+x1.fd_v2_5/4 -3.45216e-06
+x1.fd_v2_5/3 -1.00752e-05
+x1.fd_v2_5/6 0.794419
+x1.fd_v2_5/clkb -3.70911e-05
+x1.fd_v2_5/5 1.79999
+x1.fd_v2_5/2 1.66028
+x1.fd_v2_6/clk_in -4.25264e-06
+x1.fd_v2_5/7 1.66051
+x1.fd_v2_6/4 0.808828
+x1.fd_v2_6/3 1.8
+x1.fd_v2_6/6 1.60655
+x1.fd_v2_6/clkb 1.80012
+x1.fd_v2_6/5 1.60641
+x1.fd_v2_6/2 -5.8657e-05
+out_div128_buf 1.8
+x1.fd_v2_6/7 -6.09207e-05
+x1.fd_v2_7/4 1.26016e-05
+x1.fd_v2_7/3 4.71267e-06
+x1.fd_v2_7/6 0.79495
+x1.fd_v2_7/clkb 2.0188e-06
+x1.fd_v2_7/5 1.8
+x1.fd_v2_7/2 1.65837
+out_div256_buf 7.70075e-06
+x1.fd_v2_7/7 1.65837
+x1.fd_v2_8/4 0.810461
+x1.fd_v2_8/3 1.8
+x1.fd_v2_8/6 1.59917
+x1.fd_v2_8/clkb 1.8
+x1.fd_v2_8/5 1.59917
+x1.fd_v2_8/2 1.81705e-05
+x1.fd_v2_9/clk_in 1.8
+x1.fd_v2_8/7 1.55651e-05
+x1.fd_v2_9/4 1.11543e-05
+x1.fd_v2_9/3 3.14149e-06
+x1.fd_v2_9/6 0.79617
+x1.fd_v2_9/clkb -8.87153e-08
+x1.fd_v2_9/5 1.8
+x1.fd_v2_9/2 1.65471
+x1.fd_v2_9/clk_out -2.67459e-05
+x1.fd_v2_9/7 1.65471
+x1.fd_v5_0/4 1.71492
+x1.fd_v5_0/5 -0.0174329
+x1.fd_v5_0/2 1.79636
+x1.fd_v5_0/3 -0.00543058
+x1.fd_v5_0/clkb_buf 1.79505
+x1.fd_v5_0/clk_in_buf 0.00351015
+x1.fd_v5_0/clkb_int 1.79665
+x1.fd_v5_0/dus -0.00627537
+x1.fd_v5_0/6 0.00535738
+x1.fd_v5_0/7 1.79267
+x1.fd_v2_1/clk_in -0.040032
+x1.out -0.0161395
+x1.3-stage_cs-vco_dp9_0/net7 1.79442
+x1.x3-stage_cs-vco_dp9_0.net6 -0.00315382
+net2 0
+x1.x3-stage_cs-vco_dp9_0.vgp 1.70271
+vctrl 0
+x1.x3-stage_cs-vco_dp9_0.net8 0.982534
+x1.3-stage_cs-vco_dp9_0/ng3 2.69135e-05
+x1.x3-stage_cs-vco_dp9_0.ng0 1.50189e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_0/selb -2.46251e-05
+vsel0 1.8
+x1.x3-stage_cs-vco_dp9_0.ng1 2.05503e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_1/selb -2.27226e-05
+vsel1 1.8
+x1.x3-stage_cs-vco_dp9_0.ng2 2.75821e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_n_v2_2/selb -2.21318e-05
+vsel2 1.8
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/selb -1.69716e-05
+vsel3 1.8
+x1.x3-stage_cs-vco_dp9_0.net3 0.983204
+x1.x3-stage_cs-vco_dp9_0.net5 1.8048
+x1.x3-stage_cs-vco_dp9_0.net2 1.03367
+x1.x3-stage_cs-vco_dp9_0.net4 0.0707445
+x1.x3-stage_cs-vco_dp9_0.pg3 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg0 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_0/selb -6.50028e-05
+x1.x3-stage_cs-vco_dp9_0.pg1 1.70271
+x1.x3-stage_cs-vco_dp9_0.pg2 1.70271
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_2/selb -6.51181e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_1/selb -6.44664e-05
+x1.x3-stage_cs-vco_dp9_0.vco_switch_p_3/selb -6.31688e-05
+x1.fd_v2_1/4 -0.0548854
+x1.fd_v2_1/3 1.79947
+x1.fd_v2_1/6 1.79922
+x1.fd_v2_1/clkb 1.78983
+x1.fd_v2_1/5 1.79472
+x1.fd_v2_1/2 -0.00524352
+x1.fd_v2_2/clk_in 1.80761
+x1.fd_v2_1/7 0.0210799
+x1.fd_v2_2/4 1.80609
+x1.fd_v2_2/3 1.81536
+x1.fd_v2_2/6 1.54268
+x1.fd_v2_2/clkb 0.031251
+x1.fd_v2_2/5 0.0428536
+x1.fd_v2_2/2 0.000697906
+x1.fd_v2_2/7 -0.000309931
+x1.3-stage_cs-vco_dp9_0/net6 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_3/selb 0
+x1.3-stage_cs-vco_dp9_0/pg3 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_1/selb 0
+x1.3-stage_cs-vco_dp9_0/pg1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_2/selb 0
+x1.3-stage_cs-vco_dp9_0/pg2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_p_0/selb 0
+x1.3-stage_cs-vco_dp9_0/pg0 0
+x1.3-stage_cs-vco_dp9_0/net4 0
+x1.3-stage_cs-vco_dp9_0/net3 0
+x1.3-stage_cs-vco_dp9_0/net5 0
+x1.3-stage_cs-vco_dp9_0/net2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/selb 0
+x1.3-stage_cs-vco_dp9_0/ng2 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/selb 0
+x1.3-stage_cs-vco_dp9_0/ng1 0
+x1.3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/selb 0
+x1.3-stage_cs-vco_dp9_0/ng0 0
+x1.3-stage_cs-vco_dp9_0/net8 0
+x1.3-stage_cs-vco_dp9_0/vgp 0
+vdd 1.8
+buf1a_out 1.79998
+buf2a_out 1.79999
+buf4a_out 1.8
+buf8a_out 1.8
+pad_out_a 1.8
+buf1b_out -3.84638e-05
+buf2b_out -4.29694e-05
+buf4b_out -4.55334e-05
+buf8b_out -4.40379e-05
+pad_out_b -2.21527e-05
+v1#branch 5.53124e-08
+vsel3#branch 5.70942e-09
+vsel2#branch 1.5568e-08
+vsel1#branch 1.96122e-08
+vsel0#branch 2.00558e-08
+vmeas_current_gnd#branch -2.14417e-05
+vmeas_current_vdd#branch -5.47662e-05
+v2#branch 5.48476e-05
+
+
+No. of Data Rows : 20020
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.421232e-10 targ= 1.440559e-08 trig= 1.416347e-08
+fvco_outside_while = 4.13013e+09
+tdiv128_outside_while= 4.647070e-08 targ= 8.952035e-08 trig= 4.304965e-08
+fdiv128_outside_while= 2.15189e+07
+supply_current_rms_outside_while= 2.17283e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.76522e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.836673e+00 at= 1.969500e-08
+vlow_outside_while = 3.926997e-03 at= 1.999500e-08
+peak_to_peak_outside_while= 1.83275e+00
+supply_current_rms = 2.14517e-03 from= 0.00000e+00 to= 2.00000e-07
+
+binary raw file "vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw"
+Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
+
+Warning: v1: no DC value, transient time 0 value used
+
+ Measurements for Transient Analysis
+
+tvco_outside_while = 2.421232e-10 targ= 1.440559e-08 trig= 1.416347e-08
+Original line no.: 0, new internal line no.: 12457:
+insertnumber: fails.
+ s = ".meas tran fvco_outside_while param= 4.130128851579692e+09 " u=" 4.130128851579692e+09 " id=0
+fvco_outside_while = 4.13013e+09
+tdiv128_outside_while= 4.647070e-08 targ= 8.952035e-08 trig= 4.304965e-08
+Original line no.: 0, new internal line no.: 12459:
+insertnumber: fails.
+ s = ".meas tran fdiv128_outside_while param= 2.151893575271838e+07 " u=" 2.151893575271838e+07 " id=0
+fdiv128_outside_while= 2.15189e+07
+supply_current_rms_outside_while= 2.17283e-03 from= 1.00000e-08 to= 4.00000e-08
+ground_current_rms_outside_while= 5.76522e-04 from= 1.00000e-08 to= 4.00000e-08
+vctrl_avg_outside_while= 1.700000e+00 from= 1.000000e-08 to= 2.000500e-08
+vhigh_outside_while = 1.836673e+00 at= 1.969500e-08
+vlow_outside_while = 3.926997e-03 at= 1.999500e-08
+Original line no.: 0, new internal line no.: 12465:
+insertnumber: fails.
+ s = ".meas tran peak_to_peak_outside_while param= 1.832746057572564e+00 " u=" 1.832746057572564e+00 " id=0
+peak_to_peak_outside_while= 1.83275e+00
+supply_current_rms = 2.14517e-03 from= 0.00000e+00 to= 2.00000e-07
+
+
+Total analysis time (seconds) = 122.954
+
+Total CPU time (seconds) = 624.725
+
+Total DRAM available = 7952.234 MB.
+DRAM currently available = 593.336 MB.
+Maximum ngspice program size = 1254.906 MB.
+Current ngspice program size = 1237.535 MB.
+
+Shared ngspice pages = 10.227 MB.
+Text (code) pages = 7.879 MB.
+Stack = 0 bytes.
+Library pages = 1227.422 MB.
+
diff --git a/mag/3-stage_cs-vco_dp9/vco_with_fdivs_POST_LAYOUT_tb.spice b/mag/3-stage_cs-vco_dp9/vco_with_fdivs_POST_LAYOUT_tb.spice
new file mode 100755
index 0000000..c5d6a53
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/vco_with_fdivs_POST_LAYOUT_tb.spice
@@ -0,0 +1,206 @@
+** sch_path: /home/darunix/GitSandboxes/VCO/vco/xschem/vco_with_fdivs_tb.sch
+**.subckt vco_with_fdivs_tb vctrl out_div128_buf pad_out_a out_div256_buf pad_out_b
+*.iopin vctrl
+*.iopin out_div128_buf
+*.iopin pad_out_a
+*.iopin out_div256_buf
+*.iopin pad_out_b
+
+
+
+*POST-LAYOUT DUT:
+x1 vctrl out_div128_buf net1 net2 vsel0 vsel1 vsel2 vsel3 out_div256_buf vco_with_fdivs
+
+*This is the SCH DUT:
+*x1 net1 vctrl vsel0 vsel1 vsel2 vsel3 net2 out_div128_buf out_div256_buf vco_with_fdivs
+
+
+
+
+V2 vdd GND 1.8
+Vmeas_current_vdd vdd net1 0
+Vmeas_current_gnd net2 GND 0
+xbuf1a out_div128_buf GND GND vdd vdd buf1a_out sky130_fd_sc_hd__clkbuf_1
+xbuf2a buf1a_out GND GND vdd vdd buf2a_out sky130_fd_sc_hd__clkbuf_2
+xbuf4a buf2a_out GND GND vdd vdd buf4a_out sky130_fd_sc_hd__clkbuf_4
+xbuf8a buf4a_out GND GND vdd vdd buf8a_out sky130_fd_sc_hd__clkbuf_8
+xbuf16a buf8a_out GND GND vdd vdd pad_out_a sky130_fd_sc_hd__clkbuf_16
+Vsel0 vsel0 GND {p_sel0}
+Vsel1 vsel1 GND {p_sel1}
+Vsel2 vsel2 GND {p_sel2}
+Vsel3 vsel3 GND {p_sel3}
+xbuf1b out_div256_buf GND GND vdd vdd buf1b_out sky130_fd_sc_hd__clkbuf_1
+xbuf2b buf1b_out GND GND vdd vdd buf2b_out sky130_fd_sc_hd__clkbuf_2
+xbuf4b buf2b_out GND GND vdd vdd buf4b_out sky130_fd_sc_hd__clkbuf_4
+xbuf8b buf4b_out GND GND vdd vdd buf8b_out sky130_fd_sc_hd__clkbuf_8
+xbuf16b buf8b_out GND GND vdd vdd pad_out_b sky130_fd_sc_hd__clkbuf_16
+**** begin user architecture code
+
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+
+*V1 vctrl GND 0.9
+V1 vctrl GND pwl(0, 0, 1n, 0, 1.1n, 0.9, 2n, 0.9, 2.1n, {vcontrol_par})
+
+*.options savecurrents
+
+*Trying to get the syntax right for probing M26 and M7 current:
+*Current probes:
+ *DP9:
+ *.probe tran all m.x1.out
+ *.probe tran all @m.x1.xm26.msky130_fd_pr__nfet_01v8[id]
+ *.save tran all @m.x1.xm26.msky130_fd_pr__nfet_01v8[id]
+ *.probe tran all @m.x1.xm16a.msky130_fd_pr__nfet_01v8[id]
+ *.save tran all @m.x1.xm16a.msky130_fd_pr__nfet_01v8[id]
+
+
+
+.control
+
+
+let do_vctrl_sweep = 1
+*let do_dimensions_sweep = 0
+*let do_2dimensions_sweep = 0
+*let do_paracap_sweep = 0
+
+
+.param vcontrol_par = 0.9
+*.param paracap = 2.93f
+
+*---------
+*VCO current mirror select controls:
+.param p_sel0 = 1.8
+.param p_sel1 = 1.8
+.param p_sel2 = 1.8
+.param p_sel3 = 1.8
+*---------
+
+
+
+
+
+*This is to parameterize transient step/stop/start times
+*using variables:
+set t_start = 0
+set t_step = 10p
+let expected_frequency_vec = 1G
+let nperiods_vec = 200
+let t_stop_vec = nperiods_vec / expected_frequency_vec
+set t_stop = $&t_stop_vec
+
+*-----------------------
+*SEE IF THIS DOESN'T BREAK IT:
+*Trying to sync the params with the variables:
+*Just for the measure statements:
+.param t_start_par = 0
+.param t_step_par = 10p
+.param t_stop_par = 100n
+alterparam t_start_par = $t_start
+alterparam t_step_par = $t_step
+alterparam t_stop_par = $t_stop
+reset
+*-----------------------
+
+
+
+
+if do_vctrl_sweep = 1
+ *-------- WHILE LOOP FOR VCTRL SWEEP-----------------
+ let start_vctrl = 0.9
+ let stop_vctrl = 1.81
+ let increment = 0.2
+ let vctrl_next = start_vctrl
+
+ let debug_1 = 1234
+ let debug_2 = 5678
+
+ let iteration = 1
+
+ while vctrl_next le stop_vctrl
+
+ *alter V1 dc = vctrl_next
+ set vctrl_next_var = $&vctrl_next
+ alterparam vcontrol_par = $vctrl_next_var
+ reset
+
+
+ *This is using the (set) variables:
+ tran $t_step $t_stop $t_start
+
+
+ let vctrl_next = vctrl_next + increment
+ let iteration = iteration + 1
+
+
+ set appendwrite true
+ write vco_with_fdivs_POST_LAYOUT_tb_WITH_APPENDWRITE.raw all
+
+
+ end
+*-------- END WHILE LOOP FOR VCTRL SWEEP-----------------
+end $end the if do_vctrl_sweep = 1
+
+
+
+
+.endc
+
+
+
+
+
+*THESE WORK:
+*.meas tran Tvco_OUTSIDE_WHILE TRIG v(m.x1.out) VAL=0.5*1.8 RISE=50 TARG v(m.x1.out) VAL=0.5*1.8 RISE=51
+*.meas tran Tvco_OUTSIDE_WHILE TRIG v(x1.x3-stage_cs-vco_dp9.out) VAL=0.5*1.8 RISE=50 TARG v(x1.x3-stage_cs-vco_dp9.out) VAL=0.5*1.8 RISE=51
+.meas tran Tvco_OUTSIDE_WHILE TRIG v(x1.out) VAL=0.5*1.8 RISE=50 TARG v(x1.out) VAL=0.5*1.8 RISE=51
+.meas tran fvco_OUTSIDE_WHILE PARAM='1/Tvco_OUTSIDE_WHILE'
+.meas tran Tdiv128_OUTSIDE_WHILE TRIG v(out_div128_buf) VAL=0.5*1.8 RISE=1 TARG v(out_div128_buf) VAL=0.5*1.8 RISE=2
+.meas tran fdiv128_OUTSIDE_WHILE PARAM='1/Tdiv128_OUTSIDE_WHILE'
+.meas tran Supply_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_vdd) FROM=10e-9 TO=40e-9
+.meas tran Ground_current_rms_OUTSIDE_WHILE RMS i(vmeas_current_gnd) FROM=10e-9 TO=40e-9
+.meas tran vctrl_avg_OUTSIDE_WHILE AVG v(vctrl) FROM=10e-9 TO=20e-9
+.meas tran vhigh_OUTSIDE_WHILE MAX v(out_div128_buf) FROM=10e-9 TO=20e-9
+.meas tran vlow_OUTSIDE_WHILE MIN v(out_div128_buf) FROM=10e-9 TO=20e-9
+.meas tran peak_to_peak_OUTSIDE_WHILE PARAM='vhigh_OUTSIDE_WHILE-vlow_OUTSIDE_WHILE'
+
+.meas tran supply_current_rms RMS i(vmeas_current_vdd) FROM='t_start_par' TO='t_stop_par'
+
+*IF NORMAL circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+ *.meas tran m7_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8[id] FROM='t_stop_par/2' TO='t_stop_par'
+*IF LVT circuit: (couldn't wrap this inside an if)
+ *.meas tran m26_lvt_current_rms RMS @m.x1.xm26.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2' TO='t_stop_par'
+ *.meas tran m7_lvt_current_rms RMS @m.x1.xm7.msky130_fd_pr__nfet_01v8_lvt[id] FROM='t_stop_par/2' TO='t_stop_par'
+
+
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: vco_with_fdivs.sym # of pins=9
+
+
+*------------------------------------------------------------------
+*EXTRACTED NETLIST FOR VCO_WITH_FDIVS POST-LAYOUT 0
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp9/vco_with_fdivs.spice
+
+
+*This is the netlist HACKED where I have made the Fdiv Inverters 2x Wider, to try to fix the Fdiv issue
+*.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp9/vco_with_fdivs_HACK_INVERTER_WIDTHS.spice
+
+*This is last try, layout I tried with slightly wider Pmos on TGATEs to see if making them
+*less resistive would help a bit (even though they will add more cap)
+.include /home/darunix/GitSandboxes/VCO/vco/mag/3-stage_cs-vco_dp9/vco_with_fdivs_lasttry.spice
+
+
+*------------------------------------------------------------------
+
+
+
+
+
+.GLOBAL GND
+.end
diff --git a/mag/3-stage_cs-vco_dp9/zzz_carmen.mag b/mag/3-stage_cs-vco_dp9/zzz_carmen.mag
new file mode 100755
index 0000000..d886b77
--- /dev/null
+++ b/mag/3-stage_cs-vco_dp9/zzz_carmen.mag
@@ -0,0 +1,444 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645793411
+<< error_s >>
+rect 67 86 79 116
+rect 151 86 163 116
+rect 871 109 901 121
+rect 871 25 901 37
+<< nwell >>
+rect -570 243 1795 1347
+rect -570 242 -278 243
+rect -218 242 1795 243
+<< pwell >>
+rect -570 241 -278 242
+rect -218 241 1795 242
+rect -570 -835 1795 241
+<< psubdiff >>
+rect -529 -28 -495 216
+rect 894 -62 1023 -28
+rect -529 -136 -495 -62
+rect 989 -411 1023 -62
+rect -529 -747 -495 -647
+rect 989 -747 1023 -663
+rect -529 -781 -492 -747
+rect 894 -781 1023 -747
+<< nsubdiff >>
+rect -531 1252 -458 1286
+rect 930 1252 1023 1286
+rect -531 1226 -497 1252
+rect -531 565 -497 572
+rect 989 565 1023 1252
+rect -531 531 -458 565
+rect 930 531 1023 565
+rect -531 278 -497 531
+<< psubdiffcont >>
+rect -529 -62 894 -28
+rect -529 -647 -495 -136
+rect 989 -663 1023 -411
+rect -492 -781 894 -747
+<< nsubdiffcont >>
+rect -458 1252 930 1286
+rect -531 572 -497 1226
+rect -458 531 930 565
+<< poly >>
+rect 289 1133 317 1199
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+rect 590 -694 618 -628
+<< locali >>
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+rect -529 -747 -495 -647
+rect 223 -678 383 -644
+rect 528 -678 680 -644
+rect 989 -747 1023 -663
+rect 894 -781 1023 -747
+<< viali >>
+rect -458 1252 930 1286
+rect -267 410 -128 444
+rect 137 412 171 446
+rect 364 416 741 450
+rect 1091 406 1125 810
+rect -360 207 -326 241
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+rect 989 -663 1023 -411
+rect -529 -781 -492 -747
+rect -492 -781 894 -747
+<< metal1 >>
+rect 1172 1443 1372 1742
+rect -510 1442 1372 1443
+rect -510 1286 1713 1442
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+rect 930 1252 1713 1286
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+rect 578 1193 630 1199
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+rect 578 1135 630 1141
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+rect -457 -288 -411 729
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+rect 82 44 192 52
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+rect -120 -79 -74 -25
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+rect 161 -50 751 -19
+rect -120 -125 627 -79
+rect 280 -153 326 -125
+rect 581 -152 627 -125
+rect -457 -334 -181 -288
+rect -227 -423 -181 -334
+rect -826 -635 -626 -552
+rect -826 -687 -762 -635
+rect -710 -687 -626 -635
+rect -826 -752 -626 -687
+rect -430 -724 -390 -457
+rect -336 -724 -296 -457
+rect -130 -553 -49 -457
+rect -194 -635 -114 -623
+rect -194 -687 -183 -635
+rect -131 -687 -114 -635
+rect -194 -691 -114 -687
+rect -183 -693 -131 -691
+rect -86 -724 -49 -553
+rect -16 -724 24 -191
+rect 76 -724 116 -191
+rect 158 -610 227 -169
+rect 158 -724 198 -610
+rect 278 -635 330 -629
+rect 227 -684 278 -638
+rect 330 -684 379 -638
+rect 278 -693 330 -687
+rect 418 -724 487 -263
+rect 681 -602 751 -50
+rect 822 -55 862 0
+rect 1426 -10 1743 30
+rect 578 -635 630 -629
+rect 528 -684 578 -638
+rect 630 -684 680 -638
+rect 578 -693 630 -687
+rect 711 -724 751 -602
+rect 786 -94 930 -55
+rect 786 -632 826 -94
+rect 890 -632 930 -94
+rect 1086 -342 1128 -47
+rect 1288 -342 1328 -63
+rect 1086 -344 1652 -342
+rect 786 -678 930 -632
+rect 786 -724 826 -678
+rect 890 -724 930 -678
+rect 973 -411 1652 -344
+rect 973 -663 989 -411
+rect 1023 -663 1652 -411
+rect 973 -724 1652 -663
+rect -569 -747 1755 -724
+rect -569 -781 -529 -747
+rect 894 -781 1755 -747
+rect -569 -872 1755 -781
+rect 1202 -1174 1402 -872
+<< via1 >>
+rect -186 1141 -134 1193
+rect 277 1141 329 1193
+rect 578 1141 630 1193
+rect -762 -687 -710 -635
+rect -183 -687 -131 -635
+rect 278 -687 330 -635
+rect 578 -687 630 -635
+<< metal2 >>
+rect -192 1141 -186 1193
+rect -134 1187 -128 1193
+rect 271 1187 277 1193
+rect -134 1147 277 1187
+rect -134 1141 -128 1147
+rect 271 1141 277 1147
+rect 329 1187 335 1193
+rect 572 1187 578 1193
+rect 329 1147 578 1187
+rect 329 1141 335 1147
+rect 572 1141 578 1147
+rect 630 1141 636 1193
+rect -768 -687 -762 -635
+rect -710 -641 -704 -635
+rect -189 -641 -183 -635
+rect -710 -681 -183 -641
+rect -710 -687 -704 -681
+rect -189 -687 -183 -681
+rect -131 -641 -125 -635
+rect 272 -641 278 -635
+rect -131 -681 278 -641
+rect -131 -687 -125 -681
+rect 272 -687 278 -681
+rect 330 -641 336 -635
+rect 572 -641 578 -635
+rect 330 -681 578 -641
+rect 330 -687 336 -681
+rect 572 -687 578 -681
+rect 630 -687 636 -635
+use sky130_fd_pr__nfet_01v8_B87NCT XMDUM26
+timestamp 1645190808
+transform 1 0 -363 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_B87NCT XM26
+timestamp 1645190808
+transform 1 0 -157 0 1 -537
+box -76 -157 76 157
+use sky130_fd_pr__nfet_01v8_TWMWTA XMDUM16
+timestamp 1645726643
+transform 1 0 50 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B_1
+timestamp 1645187587
+transform 1 0 651 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16B
+timestamp 1645187587
+transform -1 0 557 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16_1
+timestamp 1645187587
+transform 1 0 350 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_26QSQN XM16
+timestamp 1645187587
+transform -1 0 256 0 1 -397
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_44BYND XM13
+timestamp 1645792670
+transform 1 0 1152 0 1 54
+box -73 -146 73 208
+use sky130_fd_pr__nfet_01v8_26QSQN XMDUM16B
+timestamp 1645187587
+transform 1 0 858 0 1 -391
+box -76 -297 76 297
+use sky130_fd_pr__nfet_01v8_TUVSF7 XM24
+timestamp 1645550202
+transform 1 0 1356 0 1 -4
+box -76 -217 76 217
+use sky130_fd_pr__nfet_01v8_EMZ8SC XM2
+timestamp 1645723234
+transform 0 -1 -187 1 0 101
+box -73 -129 73 129
+use sky130_fd_pr__pfet_01v8_BT7HXK XM1
+timestamp 1645723234
+transform 0 1 -215 -1 0 351
+box -109 -164 109 198
+use sky130_fd_pr__nfet_01v8_LS29AB XM4
+timestamp 1645537996
+transform 0 -1 83 1 0 101
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_BKC9WK XM3
+timestamp 1645537996
+transform 0 1 101 -1 0 351
+box -109 -114 109 148
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11
+timestamp 1645187069
+transform 1 0 49 0 1 899
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B_1
+timestamp 1645187069
+transform 1 0 650 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11B
+timestamp 1645187069
+transform 1 0 556 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11
+timestamp 1645187069
+transform 1 0 256 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__pfet_01v8_TPJM7Z XM11_1
+timestamp 1645187069
+transform 1 0 350 0 1 898
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_8T82FM XM6
+timestamp 1645719837
+transform 0 -1 466 1 0 101
+box -73 -201 73 201
+use sky130_fd_pr__pfet_01v8_FYZURS XM5
+timestamp 1645722298
+transform 0 -1 517 1 0 351
+box -109 -298 109 264
+use sky130_fd_pr__pfet_01v8_NC2CGG XM12
+timestamp 1645792198
+transform 1 0 1152 0 1 582
+box -109 -340 109 340
+use sky130_fd_pr__pfet_01v8_TPJM7Z XMDUM11B
+timestamp 1645187069
+transform 1 0 858 0 1 897
+box -112 -338 112 304
+use sky130_fd_pr__nfet_01v8_LS29AB XM22
+timestamp 1645537996
+transform 1 0 886 0 1 105
+box -73 -99 73 99
+use sky130_fd_pr__pfet_01v8_AZHELG XM21
+timestamp 1645791712
+transform 1 0 894 0 1 381
+box -109 -122 109 156
+use sky130_fd_pr__pfet_01v8_UUCHZP XM23
+timestamp 1645550202
+transform 1 0 1453 0 1 597
+box -209 -320 209 320
+use sky130_fd_pr__pfet_01v8_XZZ25Z XMDUM25
+timestamp 1645268775
+transform 1 0 -366 0 1 1039
+box -112 -198 112 164
+use sky130_fd_pr__pfet_01v8_XZZ25Z XM25
+timestamp 1645268775
+transform 1 0 -160 0 1 1039
+box -112 -198 112 164
+<< labels >>
+rlabel metal1 -826 -752 -626 -552 1 vctrl
+port 3 n
+flabel metal1 1202 -1174 1402 -974 0 FreeSans 256 0 0 0 vss
+port 1 nsew
+flabel metal1 1172 1542 1372 1742 0 FreeSans 256 0 0 0 vdd
+port 0 nsew
+flabel metal1 1849 118 2049 318 0 FreeSans 256 0 0 0 out
+port 2 nsew
+<< end >>
diff --git a/mag/FD_v2.ext b/mag/FD_v2.ext
new file mode 100644
index 0000000..88d612d
--- /dev/null
+++ b/mag/FD_v2.ext
@@ -0,0 +1,231 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_0 1 0 177 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_0 1 0 177 0 1 -227
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_1 1 0 377 0 1 -227
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_0 1 0 595 0 -1 -499
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_1 1 0 377 0 1 -422
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_0 1 0 595 0 1 -173
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_2 1 0 879 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_2 1 0 879 0 1 -227
+use sky130_fd_pr__nfet_01v8_NDE37H sky130_fd_pr__nfet_01v8_NDE37H_1 1 0 1138 0 -1 -499
+use sky130_fd_pr__pfet_01v8_ACPHKB sky130_fd_pr__pfet_01v8_ACPHKB_1 1 0 1138 0 1 -173
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_3 1 0 1383 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_3 1 0 1383 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_4 1 0 1614 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_4 1 0 1614 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW5BNL sky130_fd_pr__nfet_01v8_PW5BNL_5 1 0 1774 0 1 -422
+use sky130_fd_pr__pfet_01v8_A7DS5R sky130_fd_pr__pfet_01v8_A7DS5R_5 1 0 1774 0 1 -227
+port "Clk_Out" 4 1849 -368 1883 -334 m1
+port "Clk_In" 1 68 -375 92 -329 m1
+port "VDD" 2 68 -49 102 9 m1
+port "GND" 3 96 -688 130 -630 m1
+node "li_1553_n470#" 12 35.4726 1553 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1556_n369#" 12 33.0592 1556 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 70 114.189 1849 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6596 456 4096 292 0 0 0 0 0 0 0 0 0 0
+node "6" 258 562.288 1165 -380 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21794 1418 13308 794 0 0 0 0 0 0 0 0 0 0
+node "5" 194 163.065 906 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18394 1150 0 0 0 0 0 0 0 0 0 0 0 0
+node "4" 125 127.428 622 -380 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11832 764 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 116 700.949 320 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7854 598 53130 2402 0 0 0 0 0 0 0 0 0 0
+node "3" 162 121.242 404 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15368 972 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb" 49 51.3951 204 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 0 0 0 0 0 0 0 0 0 0 0 0
+node "7" 175 415.97 1553 -547 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5848 616 23728 1396 0 0 0 0 0 0 0 0 0 0
+node "li_204_n127#" 72 0 204 -127 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 20148 968 0 0 0 0 0 0 0 0 0 0
+node "a_971_n597#" 128 915.599 971 -597 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6004 310 0 0 3400 336 42780 1952 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 209 1097.67 68 -375 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5092 286 0 0 8794 710 82524 3680 0 0 0 0 0 0 0 0 0 0
+node "a_1687_n501#" 720 0 1687 -501 ndif 0 0 0 0 0 0 0 0 1176 196 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_1687_n263#" 2026 0 1687 -263 pdif 0 0 0 0 0 0 0 0 0 0 2016 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 15744 1945.75 68 -49 m1 0 0 0 0 629805 4324 0 0 57800 3468 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80342 4794 105270 3746 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 96 -688 m1 0 0 0 0 0 0 0 0 0 0 61710 3698 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92684 5520 105270 3746 0 0 0 0 0 0 0 0 0 0
+cap "5" "4" 29.8951
+cap "Clk_Out" "6" 8.23846
+cap "7" "li_1553_n470#" 186.069
+cap "VDD" "3" 136.674
+cap "li_204_n127#" "a_971_n597#" 64.8276
+cap "7" "Clk_Out" 97.5628
+cap "Clk_In" "Clkb" 68.1857
+cap "li_1556_n369#" "2" 10.2936
+cap "Clk_In" "2" 772.197
+cap "3" "Clkb" 35.8436
+cap "li_1556_n369#" "6" 79.361
+cap "3" "2" 109.908
+cap "5" "Clk_In" 72.7032
+cap "5" "3" 16.6953
+cap "li_1556_n369#" "li_1553_n470#" 15.2687
+cap "Clk_In" "a_971_n597#" 563.519
+cap "7" "li_1556_n369#" 64.3828
+cap "li_204_n127#" "Clk_In" 197.189
+cap "Clk_In" "4" 40.6174
+cap "Clk_Out" "li_1556_n369#" 5.31754
+cap "3" "4" 130.479
+cap "VDD" "Clkb" 32.155
+cap "VDD" "2" 250.304
+cap "VDD" "6" 95.0651
+cap "VDD" "5" 144.699
+cap "VDD" "li_1553_n470#" 2.81203
+cap "3" "Clk_In" 143.21
+cap "Clkb" "2" 13.6829
+cap "VDD" "a_971_n597#" 94.534
+cap "VDD" "7" 241.737
+cap "li_204_n127#" "VDD" 882.312
+cap "2" "6" 313.227
+cap "VDD" "4" 87.618
+cap "5" "2" 151.309
+cap "VDD" "Clk_Out" 73.6181
+cap "5" "6" 154.27
+cap "6" "li_1553_n470#" 33.5915
+cap "Clkb" "a_971_n597#" 22.898
+cap "2" "a_971_n597#" 457.606
+cap "7" "2" 38.6655
+cap "li_204_n127#" "Clkb" 8.01429
+cap "li_204_n127#" "2" 73.4694
+cap "6" "a_971_n597#" 12.7317
+cap "4" "Clkb" 9.71094
+cap "7" "6" 157.372
+cap "4" "2" 113.627
+cap "5" "a_971_n597#" 12.5172
+cap "4" "6" 3.16056
+cap "Clk_Out" "2" 24.1201
+cap "VDD" "li_1556_n369#" 3.7651
+cap "VDD" "Clk_In" 849.512
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 29.3333
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" 2.94263
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" 76.2931
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 15.8854
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 12.731
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 213.62
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 55.1837
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 8.20812
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 188.888
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" -29.567
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" 36.5315
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 11.1681
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 101.363
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 68.6513
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 21.3754
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" 10.378
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" 19.6289
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 84.3136
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" -48.0139
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 27.7803
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" 61.8779
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 102.424
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" 14.9692
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.47232
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 9.52101
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" 0.668788
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 14.6086
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 97.9663
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 9.31816
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" 25.3679
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 45.2419
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 63.8225
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 75.7818
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 236.191
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 34.9474
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 18.1003
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" 17.6716
+cap "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" 20.7091
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 0.215969
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" 4.53321
+cap "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" 100.03
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" 10.1789
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 124.772
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" 42.5694
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 46.0273
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" 9.52101
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 0.663184
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" 16.2506
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" 22.0544
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" -67.2997
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 0.770619
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" 34.9474
+cap "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" 0.215969
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 8.49674
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 56.1379
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" 33.4734
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" 3.54362
+cap "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n73_n115#" 5.03919
+cap "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" 8.12678
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_5/VSUBS" -136.753 0 0 0 0 0 0 0 0 37968 -336 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8624 -706 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_n79#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_4/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_15_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_15_n79#" "a_1687_n501#"
+merge "a_1687_n501#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_3/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_n79#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/VSUBS" "sky130_fd_pr__nfet_01v8_NDE37H_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/VSUBS" "sky130_fd_pr__pfet_01v8_A7DS5R_2/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_2/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_n79#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/VSUBS" "sky130_fd_pr__pfet_01v8_A7DS5R_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/VSUBS" "sky130_fd_pr__pfet_01v8_A7DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_n79#" "GND"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_5/w_n109_n86#" -975.658 0 0 0 0 -327834 -7544 0 0 0 0 65088 -576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5760 -568 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_15_n36#" "a_1687_n263#"
+merge "a_1687_n263#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/w_n109_n86#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/w_n109_n140#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/w_n109_n140#" "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_2/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/w_n109_n86#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/w_n109_n140#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/w_n109_n140#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/w_n109_n86#" "VDD"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" -212.168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1230 -142 0 0 -1736 -388 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_15_n79#" "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "2"
+merge "2" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_37#" -195.578 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10701 -142 0 0 14450 -688 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_n73_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n73_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_n79#" "7"
+merge "7" "li_1553_n470#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n73_n78#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n73_n115#" -7.31553 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25483 -558 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n73_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_15_n79#" "5"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_n73_n78#" "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_15_n79#" -27.88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3230 -462 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_1/a_15_n79#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n73_n115#"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n73_n115#" "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_1/a_15_n36#" "3"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_5/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" 3.92545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17342 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_5/a_15_n79#" "Clk_Out"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_4/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" -152.465 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5781 -284 0 0 25905 -546 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_4/a_n73_37#" "li_1556_n369#"
+merge "li_1556_n369#" "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_3/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_3/a_n73_37#" "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_15_n78#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_15_n78#" "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/a_15_n115#" "6"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n118_22#" -185.194 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3054 -342 0 0 10506 -224 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/a_n118_22#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n15_n133#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_n73_37#" "Clk_In"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_n33_37#" -319.74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2280 -212 0 0 -2482 -486 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_n33_37#" "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_0/a_15_n36#" "li_204_n127#"
+merge "li_204_n127#" "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#"
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_0/a_15_n79#" "Clkb"
+merge "Clkb" "a_971_n597#"
+merge "sky130_fd_pr__pfet_01v8_A7DS5R_2/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_37#" -71.9553 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1230 -142 0 0 -2482 -350 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW5BNL_2/a_n73_37#" "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_15_n78#"
+merge "sky130_fd_pr__pfet_01v8_ACPHKB_0/a_15_n78#" "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#"
+merge "sky130_fd_pr__nfet_01v8_NDE37H_0/a_15_n115#" "4"
diff --git a/mag/FD_v5.ext b/mag/FD_v5.ext
new file mode 100644
index 0000000..9529468
--- /dev/null
+++ b/mag/FD_v5.ext
@@ -0,0 +1,453 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_PW6BNL sky130_fd_pr__nfet_01v8_PW6BNL_0 1 0 -25 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW8BNL sky130_fd_pr__nfet_01v8_PW8BNL_0 1 0 -273 0 1 -422
+use sky130_fd_pr__pfet_01v8_A1DS5R sky130_fd_pr__pfet_01v8_A1DS5R_0 1 0 -273 0 1 -227
+use sky130_fd_pr__pfet_01v8_A2DS5R sky130_fd_pr__pfet_01v8_A2DS5R_0 1 0 -25 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW4BNL sky130_fd_pr__nfet_01v8_PW4BNL_0 1 0 562 0 1 -422
+use sky130_fd_pr__pfet_01v8_A4DS5R sky130_fd_pr__pfet_01v8_A4DS5R_0 1 0 562 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW6BNL MNClkin 1 0 1329 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv1 1 0 1845 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPClkin 1 0 1329 0 1 -227
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv1 1 0 1845 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate1 1 0 2383 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate1 1 0 2383 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNinv2 1 0 3277 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPinv2 1 0 3277 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW9BNL MNTgate2 1 0 3821 0 -1 -580
+use sky130_fd_pr__pfet_01v8_A2DS5R MPTgate2 1 0 3821 0 -1 1
+use sky130_fd_pr__nfet_01v8_PW6BNL MNfb 1 0 4704 0 1 -422
+use sky130_fd_pr__pfet_01v8_A8DS5R MPfb 1 0 4704 0 1 -227
+use sky130_fd_pr__nfet_01v8_PW7BNL MNbuf1 1 0 5187 0 1 -422
+use sky130_fd_pr__nfet_01v8_PW8BNL MNbuf2 1 0 5347 0 1 -422
+use sky130_fd_pr__pfet_01v8_A9DS5R MPbuf1 1 0 5187 0 1 -227
+use sky130_fd_pr__pfet_01v8_A1DS5R MPbuf2 1 0 5347 0 1 -227
+port "Clk_Out" 4 5510 -368 5544 -334 m1
+port "Clk_In" 1 -382 -369 -357 -335 m1
+port "VDD" 2 156 95 190 153 m1
+port "GND" 3 184 -760 218 -702 m1
+node "li_5126_n470#" 12 33.5477 5126 -470 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3760_n667#" 354 984.836 3760 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2322_n667#" 354 982.926 2322 -667 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33524 2040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5129_n369#" 12 32.2015 5129 -369 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5462_n270#" 22 5.19444 5462 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_Out" 49 159.577 5510 -368 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 340 7088 468 0 0 0 0 0 0 0 0 0 0
+node "5" 363 274.157 3304 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34442 2094 0 0 0 0 0 0 0 0 0 0 0 0
+node "2" 217 1546.63 1788 -369 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17204 1148 138368 6108 0 0 0 0 0 0 0 0 0 0
+node "3" 350 272.852 1872 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33150 2018 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In_buf" 164 179.781 1356 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15504 980 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clk_In" 50 218.18 -382 -369 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 7224 476 0 0 0 0 0 0 0 0 0 0
+node "6" 713 1109.97 3848 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64496 3944 21652 1290 0 0 0 0 0 0 0 0 0 0
+node "4" 571 529.467 2410 -415 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53582 3234 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3760_n126#" 122 0 3760 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_2322_n126#" 122 0 2322 -126 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 16232 972 0 0 0 0 0 0 0 0 0 0
+node "li_4024_n83#" 15 0 4024 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3848_n92#" 31 0 3848 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2586_n83#" 15 0 2586 -83 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1394 150 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2410_n92#" 31 0 2410 -92 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1430 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_90_n270#" 22 5.19444 90 -270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2074 190 0 0 0 0 0 0 0 0 0 0 0 0
+node "dus" 225 534.77 2 -403 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26540 1472 27052 1224 0 0 0 0 0 0 0 0 0 0
+node "7" 190 550.562 5126 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8296 760 31936 1828 0 0 0 0 0 0 0 0 0 0
+node "li_1356_17#" 12 0 1356 17 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0
+node "Clkb_int" 247 661.691 -246 -619 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10846 978 33290 1872 0 0 0 0 0 0 0 0 0 0
+node "a_2222_n669#" 682 2777.76 2222 -669 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14984 892 0 0 6732 600 88919 3942 0 0 0 0 0 0 0 0 0 0
+node "a_5260_n585#" 1440 0 5260 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n585#" 1440 0 -112 -585 ndif 0 0 0 0 0 0 0 0 2352 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n40_n319#" 903 65.9549 -40 -319 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2266 434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_5260_n263#" 4053 0 5260 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n112_n263#" 4053 0 -112 -263 pdif 0 0 0 0 0 0 0 0 0 0 4032 604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_3651_1#" 772 43.4388 3651 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 968 0 0 10812 840 161874 7130 0 0 0 0 0 0 0 0 0 0
+node "Clkb_buf" 1844 3803.45 2213 1 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31376 1860 0 0 43860 2988 289445 12672 0 0 0 0 0 0 0 0 0 0
+node "VDD" 40269 8766.5 156 95 m1 0 0 0 0 2909902 12836 0 0 158814 9478 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 284716 16816 343766 11970 0 0 0 0 0 0 0 0 0 0
+substrate "GND" 0 0 184 -760 m1 0 0 0 0 0 0 0 0 0 0 201484 11920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 339320 20028 343708 11968 0 0 0 0 0 0 0 0 0 0
+cap "5" "a_3651_1#" 84.9256
+cap "li_3760_n126#" "5" 14.7632
+cap "a_2222_n669#" "a_3651_1#" 259.483
+cap "Clk_Out" "li_5129_n369#" 5.31754
+cap "li_2322_n667#" "4" 88.9945
+cap "3" "a_3651_1#" 121.852
+cap "li_2410_n92#" "VDD" 43.293
+cap "li_1356_17#" "a_3651_1#" 17
+cap "5" "2" 307.459
+cap "VDD" "li_90_n270#" 45.9225
+cap "a_2222_n669#" "2" 270.978
+cap "Clk_Out" "VDD" 30.2767
+cap "3" "2" 331.614
+cap "li_2322_n126#" "4" 12.6168
+cap "a_n112_n263#" "Clkb_int" 2.9155
+cap "Clkb_buf" "4" 3.33929
+cap "Clkb_int" "a_n112_n585#" 7.0744
+cap "6" "li_3760_n667#" 88.9945
+cap "6" "li_5129_n369#" 74.8
+cap "Clkb_buf" "li_3760_n667#" 602.691
+cap "7" "li_5129_n369#" 61.6231
+cap "li_3848_n92#" "VDD" 43.293
+cap "4" "li_2586_n83#" 22
+cap "6" "VDD" 275.264
+cap "li_2322_n126#" "VDD" 408.583
+cap "Clk_In_buf" "VDD" 70.9841
+cap "a_2222_n669#" "3" 7.94891
+cap "Clkb_buf" "VDD" 3417.21
+cap "li_5462_n270#" "VDD" 45.9225
+cap "7" "VDD" 269.598
+cap "li_2410_n92#" "li_2322_n126#" 1.88
+cap "4" "a_3651_1#" 121.852
+cap "li_2586_n83#" "VDD" 39.5697
+cap "6" "Clk_Out" 8.23846
+cap "7" "Clk_Out" 92.3198
+cap "li_5462_n270#" "Clk_Out" 1.83333
+cap "4" "2" 415.856
+cap "Clkb_int" "VDD" 280.253
+cap "li_2410_n92#" "li_2586_n83#" 9.52817
+cap "VDD" "a_3651_1#" 2978.55
+cap "li_5129_n369#" "2" 5.96809
+cap "li_3848_n92#" "6" 23.2941
+cap "li_3760_n126#" "VDD" 408.583
+cap "Clkb_int" "li_90_n270#" 5.79139
+cap "Clkb_buf" "li_2322_n126#" 245.012
+cap "Clkb_buf" "6" 35.6561
+cap "2" "VDD" 92.652
+cap "a_n40_n319#" "VDD" 59.4
+cap "6" "7" 146.867
+cap "Clk_In" "VDD" 5.1
+cap "Clkb_buf" "Clk_In_buf" 74.1789
+cap "5" "4" 18.9494
+cap "a_2222_n669#" "4" 9
+cap "dus" "VDD" 98.7105
+cap "4" "3" 170.035
+cap "7" "li_5462_n270#" 3.71523
+cap "5" "li_3760_n667#" 6.03226
+cap "dus" "li_90_n270#" 26.2851
+cap "5" "VDD" 254.495
+cap "li_3848_n92#" "li_3760_n126#" 1.88
+cap "3" "VDD" 238.741
+cap "li_5129_n369#" "li_5126_n470#" 15.2687
+cap "6" "a_3651_1#" 3.33929
+cap "li_2322_n126#" "a_3651_1#" 170.315
+cap "6" "li_3760_n126#" 12.6168
+cap "li_1356_17#" "VDD" 101.091
+cap "Clk_In_buf" "a_3651_1#" 87.5799
+cap "Clkb_buf" "a_3651_1#" 1409.52
+cap "li_2322_n126#" "2" 90.9805
+cap "6" "2" 578.272
+cap "Clk_In_buf" "2" 5.13697
+cap "Clkb_buf" "2" 2298.82
+cap "7" "2" 12.3056
+cap "li_4024_n83#" "VDD" 39.5697
+cap "Clkb_buf" "dus" 97.1345
+cap "a_2222_n669#" "li_2322_n667#" 602.691
+cap "li_2322_n667#" "3" 6.03226
+cap "6" "5" 171.334
+cap "li_3760_n126#" "a_3651_1#" 235.31
+cap "li_2322_n126#" "3" 14.7632
+cap "a_2222_n669#" "Clk_In_buf" 10.6857
+cap "Clkb_buf" "5" 28.3979
+cap "Clk_In" "Clkb_int" 235.533
+cap "Clkb_buf" "a_2222_n669#" 653.464
+cap "Clk_In_buf" "3" 16.3922
+cap "dus" "Clkb_int" 96.2735
+cap "Clkb_buf" "3" 24.1398
+cap "4" "VDD" 275.264
+cap "2" "a_3651_1#" 1934.53
+cap "Clk_In_buf" "li_1356_17#" 3.9507
+cap "li_3760_n126#" "2" 90.9805
+cap "Clkb_buf" "li_1356_17#" 27.0946
+cap "6" "li_5126_n470#" 29.5263
+cap "li_3848_n92#" "li_4024_n83#" 9.52817
+cap "li_2410_n92#" "4" 23.2941
+cap "7" "li_5126_n470#" 181.929
+cap "6" "li_4024_n83#" 22
+cap "a_n40_n319#" "dus" 15.0989
+cap "Clk_In" "dus" 18.3829
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" -9.58974
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 374.693
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 529.086
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "MNClkin/a_15_n163#" 21.3071
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" 135.963
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" 46.6931
+cap "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" -138.428
+cap "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 288.302
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" 145.425
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" -30.7228
+cap "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 61.2575
+cap "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 75.8306
+cap "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" 11.4
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 217.334
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "MNClkin/a_15_n163#" 4.00786
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 33
+cap "MNinv1/a_191_n163#" "MNClkin/a_15_n163#" 67.1697
+cap "MNTgate1/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 17.5757
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 82.8018
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "MNTgate1/a_15_n163#" 1.23612
+cap "MNinv1/a_n73_37#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 195.054
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "MNinv1/a_n73_37#" -6.48841
+cap "MNTgate1/a_15_n163#" "MNinv1/a_191_n163#" 14.2405
+cap "MNinv1/a_n73_37#" "MNinv1/a_191_n163#" 187.723
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" -213.068
+cap "MNClkin/a_15_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" -151.945
+cap "MNTgate1/a_15_n163#" "MNClkin/a_15_n163#" -6.873
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 217.945
+cap "MNTgate1/a_15_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 1.8255
+cap "MNinv1/a_n73_37#" "MNClkin/a_15_n163#" 135.831
+cap "MNinv1/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 275.689
+cap "MNinv1/a_n73_37#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" 13.7802
+cap "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "MNinv1/a_191_n163#" 53.3624
+cap "MNClkin/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" 522.162
+cap "MNinv2/a_n73_n163#" "MNTgate2/a_n15_n199#" 102.35
+cap "MPTgate1/a_n15_n81#" "MNinv1/a_191_n163#" 150.312
+cap "MPinv1/a_279_n36#" "MNTgate1/a_15_n163#" -163.785
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_15_n163#" 6.53314
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_n15_n199#" 2.43269
+cap "MPinv1/a_279_n36#" "MPTgate1/a_n15_n81#" -215.618
+cap "MNTgate1/a_n15_n199#" "MNTgate2/a_n15_n199#" 109.567
+cap "MPinv1/a_279_n36#" "MNinv1/a_191_n163#" -167.423
+cap "MNTgate2/a_15_n163#" "MNinv2/a_191_n163#" -2.92226
+cap "MNTgate2/a_n15_n199#" "MNinv2/a_191_n163#" 81.901
+cap "MNinv2/a_n73_n163#" "MNinv2/a_191_n163#" 37.1757
+cap "MNinv1/a_n73_37#" "MNTgate1/a_n15_n199#" 0.332021
+cap "MPTgate2/a_n15_n81#" "MNinv2/a_191_n163#" 85.0149
+cap "MNTgate1/a_15_n163#" "MNTgate2/a_n15_n199#" -159.294
+cap "MNTgate1/a_15_n163#" "MNinv2/a_n73_n163#" 52.0859
+cap "MPTgate2/a_n15_n81#" "MNTgate1/a_15_n163#" -166.446
+cap "MNTgate2/a_n15_n199#" "MNinv1/a_191_n163#" 204.7
+cap "MPTgate2/a_n15_n81#" "MPTgate1/a_n15_n81#" 71.815
+cap "MNinv1/a_n73_37#" "MPTgate1/a_n15_n81#" 0.96988
+cap "MNinv2/a_n73_n163#" "MNinv1/a_191_n163#" 69.7567
+cap "MPinv1/a_279_n36#" "MNTgate2/a_15_n163#" 20.6585
+cap "MNTgate1/a_15_n163#" "MNTgate1/a_n15_n199#" 24.0588
+cap "MPTgate2/a_n15_n81#" "MNinv1/a_191_n163#" 59.2502
+cap "MPinv1/a_279_n36#" "MNinv2/a_n73_n163#" 16.5
+cap "MNTgate1/a_15_n163#" "MNinv2/a_191_n163#" 218.748
+cap "MPTgate1/a_n15_n81#" "MNTgate1/a_n15_n199#" 27.0803
+cap "MPinv1/a_279_n36#" "MPTgate2/a_n15_n81#" 12.7582
+cap "2" "MNinv2/a_191_n163#" -1.42109e-14
+cap "MNTgate1/a_n15_n199#" "MNinv1/a_191_n163#" 79.491
+cap "MNinv1/a_191_n163#" "MNinv2/a_191_n163#" 26.5082
+cap "MPinv1/a_279_n36#" "MNinv2/a_191_n163#" -14.6416
+cap "MNTgate1/a_15_n163#" "MPTgate1/a_n15_n81#" -75.8445
+cap "2" "MNTgate1/a_15_n163#" 123.703
+cap "MNTgate1/a_15_n163#" "MNinv1/a_191_n163#" 307.928
+cap "MNbuf2/a_15_n163#" "MNTgate2/a_15_n163#" 4.24837
+cap "MNinv2/a_191_n163#" "MNTgate2/a_n15_n199#" 79.491
+cap "MPinv2/a_279_n36#" "MNfb/a_15_n163#" 31.9471
+cap "MPinv2/a_279_n36#" "MPTgate2/a_n15_n81#" -235.15
+cap "MPinv2/a_n15_n133#" "MPTgate2/a_n15_n81#" 3.10902
+cap "MNfb/a_n73_n163#" "MNbuf1/a_n73_n163#" -46.4039
+cap "MNTgate2/a_15_n163#" "MNfb/a_15_n163#" 440.45
+cap "MPTgate2/a_n15_n81#" "MNTgate2/a_15_n163#" 140.389
+cap "MPinv2/a_n15_n133#" "MNTgate2/a_n15_n199#" 2.04298
+cap "MNfb/a_n73_n163#" "MNinv2/a_191_n163#" 73.6429
+cap "MNTgate2/a_n15_n199#" "MNTgate2/a_15_n163#" 25.6357
+cap "MNTgate2/a_n15_n199#" "MPTgate2/a_n15_n81#" 31.2823
+cap "MNfb/a_n73_n163#" "MNbuf2/a_15_n163#" 20.5987
+cap "MNfb/a_n73_n163#" "MPinv2/a_279_n36#" 17.2279
+cap "MNfb/a_n73_n163#" "MNTgate2/a_15_n163#" 258.11
+cap "MNbuf2/a_15_n163#" "MNbuf1/a_n73_n163#" 37.9346
+cap "MPinv2/a_279_n36#" "MNbuf1/a_n73_n163#" -4.98108
+cap "MNfb/a_n73_n163#" "MNfb/a_15_n163#" 69.8638
+cap "MNinv2/a_191_n163#" "MPinv2/a_279_n36#" -182.47
+cap "MNbuf1/a_n73_n163#" "MNTgate2/a_15_n163#" 97.3094
+cap "MNbuf2/a_15_n163#" "MPinv2/a_279_n36#" 45.2648
+cap "MNinv2/a_191_n163#" "MNTgate2/a_15_n163#" 388.409
+cap "MNbuf1/a_n73_n163#" "MNfb/a_15_n163#" 129.706
+cap "MNinv2/a_191_n163#" "MPTgate2/a_n15_n81#" 159.969
+cap "MNinv2/a_191_n163#" "MNfb/a_15_n163#" 27.7597
+cap "MPinv2/a_279_n36#" "MNTgate2/a_15_n163#" -214.066
+cap "MNfb/a_103_n163#" "MNbuf1/a_n73_n163#" -23.09
+cap "MNbuf2/a_15_n163#" "MPfb/a_103_n36#" 89.1249
+cap "MNfb/a_191_n163#" "MPfb/a_103_n36#" 31.8522
+cap "MNbuf1/a_n73_n163#" "MPfb/a_n15_n133#" 5.41463
+cap "MNfb/a_103_n163#" "MNbuf1/a_n73_37#" 21.1947
+cap "MNbuf1/a_n73_n163#" "MNbuf1/a_n73_37#" 30.087
+cap "MNfb/a_103_n163#" "MPfb/a_103_n36#" 19.0137
+cap "MNfb/a_103_n163#" "MNbuf2/a_15_n163#" 57.4821
+cap "MNbuf1/a_n73_n163#" "MPfb/a_103_n36#" 66.7316
+cap "MNfb/a_103_n163#" "MNfb/a_191_n163#" 21.0913
+cap "MNbuf2/a_15_n163#" "MNbuf1/a_n73_n163#" 143.468
+cap "MNfb/a_191_n163#" "MNbuf1/a_n73_n163#" 0.0772348
+cap "MNbuf2/a_15_n163#" "MNbuf1/a_n73_37#" 4.24837
+merge "MPbuf2/a_103_n36#" "li_5462_n270#" -5338.22 0 0 0 0 -1793600 -19228 0 0 0 0 28800 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27738 -3248 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_5462_n270#" "MPbuf2/a_n73_n36#"
+merge "MPbuf2/a_n73_n36#" "MPbuf2/w_n109_n86#"
+merge "MPbuf2/w_n109_n86#" "MPbuf1/a_15_n36#"
+merge "MPbuf1/a_15_n36#" "a_5260_n263#"
+merge "a_5260_n263#" "MPbuf1/w_n109_n86#"
+merge "MPbuf1/w_n109_n86#" "MPfb/a_279_n36#"
+merge "MPfb/a_279_n36#" "MPfb/a_103_n36#"
+merge "MPfb/a_103_n36#" "MPfb/a_n73_n36#"
+merge "MPfb/a_n73_n36#" "MPfb/w_n109_n86#"
+merge "MPfb/w_n109_n86#" "MPTgate2/w_n109_n86#"
+merge "MPTgate2/w_n109_n86#" "MPinv2/a_279_n36#"
+merge "MPinv2/a_279_n36#" "MPinv2/a_103_n36#"
+merge "MPinv2/a_103_n36#" "MPinv2/a_n73_n36#"
+merge "MPinv2/a_n73_n36#" "MPinv2/w_n109_n86#"
+merge "MPinv2/w_n109_n86#" "MPTgate1/w_n109_n86#"
+merge "MPTgate1/w_n109_n86#" "MPinv1/a_n73_n36#"
+merge "MPinv1/a_n73_n36#" "MPinv1/a_279_n36#"
+merge "MPinv1/a_279_n36#" "MPinv1/a_103_n36#"
+merge "MPinv1/a_103_n36#" "MPinv1/w_n109_n86#"
+merge "MPinv1/w_n109_n86#" "MPClkin/a_279_n36#"
+merge "MPClkin/a_279_n36#" "MPClkin/a_103_n36#"
+merge "MPClkin/a_103_n36#" "MPClkin/a_n73_n36#"
+merge "MPClkin/a_n73_n36#" "MPClkin/w_n109_n86#"
+merge "MPClkin/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_455_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_455_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_103_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_279_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_103_n36#" "li_90_n270#"
+merge "li_90_n270#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/w_n109_n86#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_103_n36#" "a_n112_n263#"
+merge "a_n112_n263#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n73_n36#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/w_n109_n86#" "VDD"
+merge "MNTgate2/a_n15_n199#" "MPTgate1/a_n15_n81#" -547.99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21032 -778 0 0 15354 -724 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPTgate1/a_n15_n81#" "MPClkin/a_n15_n133#"
+merge "MPClkin/a_n15_n133#" "MNClkin/a_n73_37#"
+merge "MNClkin/a_n73_37#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_543_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_543_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_15_n36#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_191_n36#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_367_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_367_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_191_n163#" "Clkb_buf"
+merge "MPbuf2/VSUBS" "MPbuf1/VSUBS" -952.932 0 0 0 0 0 0 0 0 16800 -1344 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120463 -5192 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf1/VSUBS" "MNbuf2/VSUBS"
+merge "MNbuf2/VSUBS" "MNbuf2/a_103_n163#"
+merge "MNbuf2/a_103_n163#" "MNbuf2/a_n73_n163#"
+merge "MNbuf2/a_n73_n163#" "MNbuf1/VSUBS"
+merge "MNbuf1/VSUBS" "MNbuf1/a_15_n163#"
+merge "MNbuf1/a_15_n163#" "a_5260_n585#"
+merge "a_5260_n585#" "MPfb/VSUBS"
+merge "MPfb/VSUBS" "MNfb/VSUBS"
+merge "MNfb/VSUBS" "MNfb/a_103_n163#"
+merge "MNfb/a_103_n163#" "MNfb/a_n73_n163#"
+merge "MNfb/a_n73_n163#" "MPTgate2/VSUBS"
+merge "MPTgate2/VSUBS" "MNTgate2/VSUBS"
+merge "MNTgate2/VSUBS" "MPinv2/VSUBS"
+merge "MPinv2/VSUBS" "MNinv2/VSUBS"
+merge "MNinv2/VSUBS" "MNinv2/a_103_n163#"
+merge "MNinv2/a_103_n163#" "MNinv2/a_n73_n163#"
+merge "MNinv2/a_n73_n163#" "MPTgate1/VSUBS"
+merge "MPTgate1/VSUBS" "MNTgate1/VSUBS"
+merge "MNTgate1/VSUBS" "MPinv1/VSUBS"
+merge "MPinv1/VSUBS" "MNinv1/VSUBS"
+merge "MNinv1/VSUBS" "MNinv1/a_103_n163#"
+merge "MNinv1/a_103_n163#" "MNinv1/a_n73_n163#"
+merge "MNinv1/a_n73_n163#" "MNClkin/a_103_n163#"
+merge "MNClkin/a_103_n163#" "MPClkin/VSUBS"
+merge "MPClkin/VSUBS" "MNClkin/VSUBS"
+merge "MNClkin/VSUBS" "MNClkin/a_n73_n163#"
+merge "MNClkin/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A4DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW4BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_279_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_279_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_n163#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/VSUBS" "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/VSUBS" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_103_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_n163#" "GND"
+merge "GND" "a_n112_n585#"
+merge "MPinv2/a_n15_n133#" "MNinv2/a_n73_37#" -156.783 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7139 -538 0 0 59406 -1688 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNinv2/a_n73_37#" "MNTgate1/a_543_n163#"
+merge "MNTgate1/a_543_n163#" "MPTgate1/a_367_n36#"
+merge "MPTgate1/a_367_n36#" "MPTgate1/a_191_n36#"
+merge "MPTgate1/a_191_n36#" "li_2586_n83#"
+merge "li_2586_n83#" "MPTgate1/a_15_n36#"
+merge "MPTgate1/a_15_n36#" "li_2410_n92#"
+merge "li_2410_n92#" "MNTgate1/a_367_n163#"
+merge "MNTgate1/a_367_n163#" "MNTgate1/a_191_n163#"
+merge "MNTgate1/a_191_n163#" "MNTgate1/a_15_n163#"
+merge "MNTgate1/a_15_n163#" "4"
+merge "MPfb/a_191_n36#" "MPfb/a_15_n36#" -1112.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7170 -538 0 0 -3128 -524 -64400 -2800 0 0 0 0 0 0 0 0 0 0
+merge "MPfb/a_15_n36#" "MNfb/a_191_n163#"
+merge "MNfb/a_191_n163#" "MNfb/a_15_n163#"
+merge "MNfb/a_15_n163#" "MPinv1/a_n15_n133#"
+merge "MPinv1/a_n15_n133#" "MNinv1/a_n73_37#"
+merge "MNinv1/a_n73_37#" "2"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_n15_n81#" "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#" -406.518 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -824 0 0 -10166 -938 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_15_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_n73_37#" "Clkb_int"
+merge "Clkb_int" "a_n40_n319#"
+merge "MPTgate2/a_n15_n81#" "MNTgate1/a_n15_n199#" 82.773 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12930 -240 0 0 79092 -1088 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_n15_n199#" "MPClkin/a_191_n36#"
+merge "MPClkin/a_191_n36#" "MNClkin/a_191_n163#"
+merge "MNClkin/a_191_n163#" "MPClkin/a_15_n36#"
+merge "MPClkin/a_15_n36#" "li_1356_17#"
+merge "li_1356_17#" "a_3651_1#"
+merge "a_3651_1#" "MNClkin/a_15_n163#"
+merge "MNClkin/a_15_n163#" "Clk_In_buf"
+merge "Clk_In_buf" "a_2222_n669#"
+merge "MPbuf2/a_n15_n133#" "MPbuf1/a_n73_n36#" -348.154 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2487 -338 0 0 6478 -856 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MPbuf1/a_n73_n36#" "MNbuf2/a_n73_37#"
+merge "MNbuf2/a_n73_37#" "MNbuf1/a_n73_n163#"
+merge "MNbuf1/a_n73_n163#" "7"
+merge "7" "li_5126_n470#"
+merge "MNTgate2/a_631_n163#" "MNTgate2/a_455_n163#" -232.712 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36339 -1722 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate2/a_455_n163#" "MPTgate2/a_279_n36#"
+merge "MPTgate2/a_279_n36#" "MPTgate2/a_103_n36#"
+merge "MPTgate2/a_103_n36#" "MPTgate2/a_n73_n36#"
+merge "MPTgate2/a_n73_n36#" "li_3760_n126#"
+merge "li_3760_n126#" "MNTgate2/a_103_n163#"
+merge "MNTgate2/a_103_n163#" "MNTgate2/a_n73_n163#"
+merge "MNTgate2/a_n73_n163#" "MNTgate2/a_279_n163#"
+merge "MNTgate2/a_279_n163#" "li_3760_n667#"
+merge "li_3760_n667#" "MPinv2/a_191_n36#"
+merge "MPinv2/a_191_n36#" "MPinv2/a_15_n36#"
+merge "MPinv2/a_15_n36#" "MNinv2/a_15_n163#"
+merge "MNinv2/a_15_n163#" "MNinv2/a_191_n163#"
+merge "MNinv2/a_191_n163#" "5"
+merge "MNTgate1/a_631_n163#" "MNTgate1/a_455_n163#" -235.078 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34869 -1658 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNTgate1/a_455_n163#" "MPTgate1/a_279_n36#"
+merge "MPTgate1/a_279_n36#" "MPTgate1/a_103_n36#"
+merge "MPTgate1/a_103_n36#" "MPTgate1/a_n73_n36#"
+merge "MPTgate1/a_n73_n36#" "li_2322_n126#"
+merge "li_2322_n126#" "MNTgate1/a_103_n163#"
+merge "MNTgate1/a_103_n163#" "MNTgate1/a_n73_n163#"
+merge "MNTgate1/a_n73_n163#" "MNTgate1/a_279_n163#"
+merge "MNTgate1/a_279_n163#" "li_2322_n667#"
+merge "li_2322_n667#" "MPinv1/a_191_n36#"
+merge "MPinv1/a_191_n36#" "MPinv1/a_15_n36#"
+merge "MPinv1/a_15_n36#" "MNinv1/a_15_n163#"
+merge "MNinv1/a_15_n163#" "MNinv1/a_191_n163#"
+merge "MNinv1/a_191_n163#" "3"
+merge "MPbuf1/a_n15_n133#" "MNbuf1/a_n73_37#" -335.515 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5417 -680 0 0 81336 -1884 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf1/a_n73_37#" "li_5129_n369#"
+merge "li_5129_n369#" "MPfb/a_n15_n133#"
+merge "MPfb/a_n15_n133#" "MNfb/a_n73_37#"
+merge "MNfb/a_n73_37#" "MNTgate2/a_543_n163#"
+merge "MNTgate2/a_543_n163#" "MPTgate2/a_367_n36#"
+merge "MPTgate2/a_367_n36#" "MPTgate2/a_191_n36#"
+merge "MPTgate2/a_191_n36#" "li_4024_n83#"
+merge "li_4024_n83#" "MPTgate2/a_15_n36#"
+merge "MPTgate2/a_15_n36#" "li_3848_n92#"
+merge "li_3848_n92#" "MNTgate2/a_367_n163#"
+merge "MNTgate2/a_367_n163#" "MNTgate2/a_191_n163#"
+merge "MNTgate2/a_191_n163#" "MNTgate2/a_15_n163#"
+merge "MNTgate2/a_15_n163#" "6"
+merge "sky130_fd_pr__pfet_01v8_A1DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" -255.794 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4258 -338 0 0 -2244 -200 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW8BNL_0/a_n73_37#" "Clk_In"
+merge "sky130_fd_pr__pfet_01v8_A4DS5R_0/a_n15_n133#" "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_37#" -474.404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -790 -934 0 0 -1190 -478 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_PW4BNL_0/a_n73_37#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_367_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_191_n36#" "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#"
+merge "sky130_fd_pr__pfet_01v8_A2DS5R_0/a_15_n36#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_191_n163#" "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#"
+merge "sky130_fd_pr__nfet_01v8_PW6BNL_0/a_15_n163#" "dus"
+merge "MPbuf2/a_15_n36#" "MNbuf2/a_15_n163#" -80.8137 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "MNbuf2/a_15_n163#" "Clk_Out"
diff --git a/mag/pins.spice b/mag/pins.spice
new file mode 100644
index 0000000..d03f6d9
--- /dev/null
+++ b/mag/pins.spice
@@ -0,0 +1,26 @@
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
+.ends
+
diff --git a/mag/sky130_fd_pr__nfet_01v8_26QSQN.ext b/mag/sky130_fd_pr__nfet_01v8_26QSQN.ext
new file mode 100644
index 0000000..5abb5f3
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_26QSQN.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n209#" 1169 17.4716 18 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n209#" 1169 17.4716 -76 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n297#" 823 148.863 -33 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23364 1320 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n209#" "a_n76_n209#" 349.025
+cap "a_n33_n297#" "a_n76_n209#" 3.69031
+cap "a_n33_n297#" "a_18_n209#" 4.24313
+device msubckt sky130_fd_pr__nfet_01v8 -18 -209 -17 -208 l=36 w=480 "VSUBS" "a_n33_n297#" 72 0 "a_n76_n209#" 480 0 "a_18_n209#" 480 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_44BYND.ext b/mag/sky130_fd_pr__nfet_01v8_44BYND.ext
new file mode 100644
index 0000000..1092637
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_44BYND.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n120#" 582 8.7358 15 -120 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8092 544 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n120#" 586 19.9316 -73 -120 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 10166 534 0 0 0 0 0 0 0 0 0 0
+node "a_n33_142#" 577 144.799 -33 142 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12996 840 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n120#" "a_n73_n120#" 145.444
+cap "a_n33_142#" "a_n73_n120#" 5.82353
+cap "a_n33_142#" "a_15_n120#" 4.5
+device msubckt sky130_fd_pr__nfet_01v8 -15 -120 -14 -119 l=30 w=240 "VSUBS" "a_n33_142#" 60 0 "a_n73_n120#" 240 0 "a_15_n120#" 240 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_8T82FM.ext b/mag/sky130_fd_pr__nfet_01v8_8T82FM.ext
new file mode 100644
index 0000000..2140dfb
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_8T82FM.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n175#" 702 17.4716 15 -175 ndif 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n175#" 702 17.4716 -73 -175 ndif 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_135#" 655 144.799 -33 135 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14436 936 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n175#" "a_n73_n175#" 157.548
+cap "a_n33_135#" "a_n73_n175#" 1.94118
+cap "a_n33_135#" "a_15_n175#" 1.94118
+device msubckt sky130_fd_pr__nfet_01v8 -15 -175 -14 -174 l=30 w=288 "VSUBS" "a_n33_135#" 60 0 "a_n73_n175#" 288 0 "a_15_n175#" 288 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_B87NCT.ext b/mag/sky130_fd_pr__nfet_01v8_B87NCT.ext
new file mode 100644
index 0000000..e4dd77b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_B87NCT.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n69#" 489 17.4716 18 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n69#" 489 17.4716 -76 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n157#" 446 148.863 -33 -157 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13284 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n69#" "a_n76_n69#" 168.775
+cap "a_n33_n157#" "a_n76_n69#" 4.77127
+cap "a_n33_n157#" "a_18_n69#" 5.55882
+device msubckt sky130_fd_pr__nfet_01v8 -18 -69 -17 -68 l=36 w=200 "VSUBS" "a_n33_n157#" 72 0 "a_n76_n69#" 200 0 "a_18_n69#" 200 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_EMZ8SC.ext b/mag/sky130_fd_pr__nfet_01v8_EMZ8SC.ext
new file mode 100644
index 0000000..15875c5
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_EMZ8SC.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n103#" 348 0 15 -103 ndif 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4760 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n103#" 348 0 -73 -103 ndif 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4760 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_63#" 422 144.799 -33 63 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10116 648 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n103#" "a_n73_n103#" 74.5161
+cap "a_n33_63#" "a_n73_n103#" 1.65
+cap "a_n33_63#" "a_15_n103#" 1.65
+device msubckt sky130_fd_pr__nfet_01v8 -15 -103 -14 -102 l=30 w=144 "VSUBS" "a_n33_63#" 60 0 "a_n73_n103#" 144 0 "a_15_n103#" 144 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext b/mag/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext
new file mode 100644
index 0000000..f8833d3
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n73#" 207 17.4716 18 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n73#" 207 17.4716 -76 -73 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n18_n99#" 293 153.77 -18 -99 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10824 580 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n73#" "a_n76_n73#" 50.6
+cap "a_n18_n99#" "a_18_n73#" 30.0882
+device msubckt sky130_fd_pr__nfet_01v8 -18 -73 -17 -72 l=36 w=84 "VSUBS" "a_n18_n99#" 72 0 "a_n76_n73#" 84 0 "a_18_n73#" 84 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_LS30AB.ext b/mag/sky130_fd_pr__nfet_01v8_LS30AB.ext
new file mode 100644
index 0000000..7588c84
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_LS30AB.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n80#" 205 15.7058 15 -80 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2992 244 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n80#" 205 15.7058 -73 -80 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2992 244 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 343 152.353 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8676 552 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n80#" "a_n73_n80#" 46.8387
+cap "a_n33_33#" "a_n73_n80#" 1.53488
+cap "a_n33_33#" "a_15_n80#" 1.53488
+device msubckt sky130_fd_pr__nfet_01v8 -15 -80 -14 -79 l=30 w=84 "VSUBS" "a_n33_33#" 60 0 "a_n73_n80#" 84 0 "a_15_n80#" 84 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_M34CP3.ext b/mag/sky130_fd_pr__nfet_01v8_M34CP3.ext
new file mode 100644
index 0000000..3a1c16c
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_M34CP3.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n96#" 318 17.4716 15 -96 ndif 0 0 0 0 0 0 0 0 7540 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n96#" 318 17.4716 -73 -96 ndif 0 0 0 0 0 0 0 0 7540 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4692 344 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_56#" 398 153.777 -73 56 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11148 664 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n96#" "a_n73_n96#" 84.3333
+cap "a_n73_56#" "a_n73_n96#" 33
+device msubckt sky130_fd_pr__nfet_01v8 -15 -96 -14 -95 l=30 w=130 "VSUBS" "a_n73_56#" 60 0 "a_n73_n96#" 130 0 "a_15_n96#" 130 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_MP0P50.ext b/mag/sky130_fd_pr__nfet_01v8_MP0P50.ext
new file mode 100644
index 0000000..d14bca0
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_MP0P50.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n96#" 244 15.7058 15 -96 ndif 0 0 0 0 0 0 0 0 5800 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n96#" 244 15.7058 -73 -96 ndif 0 0 0 0 0 0 0 0 5800 316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3536 276 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_33#" 369 152.353 -33 33 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9156 584 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n96#" "a_n73_n96#" 55.3548
+cap "a_n33_33#" "a_n73_n96#" 1.53488
+cap "a_n33_33#" "a_15_n96#" 1.53488
+device msubckt sky130_fd_pr__nfet_01v8 -15 -96 -14 -95 l=30 w=100 "VSUBS" "a_n33_33#" 60 0 "a_n73_n96#" 100 0 "a_15_n96#" 100 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_MV8TJR.ext b/mag/sky130_fd_pr__nfet_01v8_MV8TJR.ext
new file mode 100644
index 0000000..e641cd0
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_MV8TJR.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n89#" 586 17.4716 18 -89 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n89#" 586 17.4716 -76 -89 ndif 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n177#" 500 148.863 -33 -177 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14724 840 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n89#" "a_n76_n89#" 194.525
+cap "a_n33_n177#" "a_n76_n89#" 4.46349
+cap "a_n33_n177#" "a_18_n89#" 5.23135
+device msubckt sky130_fd_pr__nfet_01v8 -18 -89 -17 -88 l=36 w=240 "VSUBS" "a_n33_n177#" 72 0 "a_n76_n89#" 240 0 "a_18_n89#" 240 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_NDE37H.ext b/mag/sky130_fd_pr__nfet_01v8_NDE37H.ext
new file mode 100644
index 0000000..45d9d7d
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_NDE37H.ext
@@ -0,0 +1,13 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n115#" 411 17.4716 15 -115 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n115#" 411 17.4716 -73 -115 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n118_22#" 623 171.49 -118 22 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11640 836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n115#" "a_n73_n115#" 107.556
+device msubckt sky130_fd_pr__nfet_01v8 -15 -115 -14 -114 l=30 w=168 "VSUBS" "a_n118_22#" 60 0 "a_n73_n115#" 168 0 "a_15_n115#" 168 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_NNRSEG.ext b/mag/sky130_fd_pr__nfet_01v8_NNRSEG.ext
new file mode 100644
index 0000000..8b109c3
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_NNRSEG.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n29#" 294 17.4716 18 -29 ndif 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n29#" 294 17.4716 -76 -29 ndif 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n117#" 337 148.863 -33 -117 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10404 600 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n29#" "a_n76_n29#" 117.275
+cap "a_n33_n117#" "a_n76_n29#" 5.99396
+cap "a_n33_n117#" "a_18_n29#" 6.60029
+device msubckt sky130_fd_pr__nfet_01v8 -18 -29 -17 -28 l=36 w=120 "VSUBS" "a_n33_n117#" 72 0 "a_n76_n29#" 120 0 "a_18_n29#" 120 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_PW4BNL.ext b/mag/sky130_fd_pr__nfet_01v8_PW4BNL.ext
new file mode 100644
index 0000000..b165926
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PW4BNL.ext
@@ -0,0 +1,35 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_367_n163#" 418 26.3006 367 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n163#" 418 26.3006 279 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n163#" 418 26.3006 191 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 2052 658.756 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64440 3372 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n163#" "a_n73_n163#" 119.778
+cap "a_279_n163#" "a_n73_n163#" 20.3396
+cap "a_279_n163#" "a_15_n163#" 28.1217
+cap "a_n73_n163#" "a_n73_37#" 33
+cap "a_15_n163#" "a_367_n163#" 20.3396
+cap "a_279_n163#" "a_367_n163#" 119.778
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+cap "a_15_n163#" "a_103_n163#" 119.778
+cap "a_279_n163#" "a_103_n163#" 45.5493
+cap "a_367_n163#" "a_103_n163#" 28.1217
+cap "a_191_n163#" "a_n73_n163#" 28.1217
+cap "a_15_n163#" "a_191_n163#" 45.5493
+cap "a_279_n163#" "a_191_n163#" 119.778
+cap "a_191_n163#" "a_367_n163#" 45.5493
+cap "a_191_n163#" "a_103_n163#" 119.778
+device msubckt sky130_fd_pr__nfet_01v8 337 -163 338 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_279_n163#" 168 0 "a_367_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 249 -163 250 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_191_n163#" 168 0 "a_279_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 161 -163 162 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_103_n163#" 168 0 "a_191_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_PW5BNL.ext b/mag/sky130_fd_pr__nfet_01v8_PW5BNL.ext
new file mode 100644
index 0000000..a3714d7
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PW5BNL.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n79#" 214 26.3006 15 -79 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n79#" 214 26.3006 -73 -79 ndif 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 356 166.367 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10368 612 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_37#" "a_n73_n79#" 33
+cap "a_15_n79#" "a_n73_n79#" 68.4444
+device msubckt sky130_fd_pr__nfet_01v8 -15 -79 -14 -78 l=30 w=84 "VSUBS" "a_n73_37#" 60 0 "a_n73_n79#" 84 0 "a_15_n79#" 84 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_PW6BNL.ext b/mag/sky130_fd_pr__nfet_01v8_PW6BNL.ext
new file mode 100644
index 0000000..6000ca7
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PW6BNL.ext
@@ -0,0 +1,23 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_191_n163#" 418 26.3006 191 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
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+node "a_n73_37#" 1269 412.562 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38664 2076 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_103_n163#" "a_15_n163#" 119.778
+cap "a_191_n163#" "a_n73_n163#" 28.1217
+cap "a_n73_n163#" "a_n73_37#" 33
+cap "a_191_n163#" "a_15_n163#" 45.5493
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_191_n163#" "a_103_n163#" 119.778
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+device msubckt sky130_fd_pr__nfet_01v8 161 -163 162 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_103_n163#" 168 0 "a_191_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_PW7BNL.ext b/mag/sky130_fd_pr__nfet_01v8_PW7BNL.ext
new file mode 100644
index 0000000..f022100
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PW7BNL.ext
@@ -0,0 +1,14 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 491 166.367 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12888 780 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n163#" "a_n73_n163#" 119.778
+cap "a_n73_n163#" "a_n73_37#" 33
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_PW8BNL.ext b/mag/sky130_fd_pr__nfet_01v8_PW8BNL.ext
new file mode 100644
index 0000000..7710aaf
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PW8BNL.ext
@@ -0,0 +1,18 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_37#" 878 289.464 -73 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25776 1428 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_103_n163#" "a_15_n163#" 119.778
+cap "a_n73_n163#" "a_n73_37#" 33
+cap "a_n73_n163#" "a_15_n163#" 119.778
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n73_37#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_PW9BNL.ext b/mag/sky130_fd_pr__nfet_01v8_PW9BNL.ext
new file mode 100644
index 0000000..0657570
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_PW9BNL.ext
@@ -0,0 +1,52 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_631_n163#" 418 26.3006 631 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_543_n163#" 418 26.3006 543 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_455_n163#" 418 26.3006 455 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_367_n163#" 418 26.3006 367 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n163#" 418 26.3006 279 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n163#" 418 26.3006 191 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n163#" 418 26.3006 103 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n163#" 418 26.3006 15 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n163#" 418 26.3006 -73 -163 ndif 0 0 0 0 0 0 0 0 9744 452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6664 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n199#" 3853 811.993 -15 -199 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71940 4856 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_455_n163#" "a_191_n163#" 28.1217
+cap "a_543_n163#" "a_367_n163#" 45.5493
+cap "a_15_n163#" "a_367_n163#" 20.3396
+cap "a_279_n163#" "a_367_n163#" 119.778
+cap "a_103_n163#" "a_191_n163#" 119.778
+cap "a_543_n163#" "a_455_n163#" 119.778
+cap "a_455_n163#" "a_279_n163#" 45.5493
+cap "a_631_n163#" "a_367_n163#" 28.1217
+cap "a_n73_n163#" "a_103_n163#" 45.5493
+cap "a_15_n163#" "a_103_n163#" 119.778
+cap "a_631_n163#" "a_455_n163#" 45.5493
+cap "a_103_n163#" "a_279_n163#" 45.5493
+cap "a_n73_n163#" "a_191_n163#" 28.1217
+cap "a_543_n163#" "a_191_n163#" 20.3396
+cap "a_15_n163#" "a_191_n163#" 45.5493
+cap "a_455_n163#" "a_367_n163#" 119.778
+cap "a_279_n163#" "a_191_n163#" 119.778
+cap "a_15_n163#" "a_n73_n163#" 119.778
+cap "a_n73_n163#" "a_279_n163#" 20.3396
+cap "a_103_n163#" "a_367_n163#" 28.1217
+cap "a_543_n163#" "a_279_n163#" 28.1217
+cap "a_15_n163#" "a_279_n163#" 28.1217
+cap "a_455_n163#" "a_103_n163#" 20.3396
+cap "a_543_n163#" "a_631_n163#" 119.778
+cap "a_191_n163#" "a_367_n163#" 45.5493
+cap "a_631_n163#" "a_279_n163#" 20.3396
+device msubckt sky130_fd_pr__nfet_01v8 601 -163 602 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_543_n163#" 168 0 "a_631_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 513 -163 514 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_455_n163#" 168 0 "a_543_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 425 -163 426 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_367_n163#" 168 0 "a_455_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 337 -163 338 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_279_n163#" 168 0 "a_367_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 249 -163 250 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_191_n163#" 168 0 "a_279_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 161 -163 162 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_103_n163#" 168 0 "a_191_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 73 -163 74 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_15_n163#" 168 0 "a_103_n163#" 168 0
+device msubckt sky130_fd_pr__nfet_01v8 -15 -163 -14 -162 l=30 w=168 "VSUBS" "a_n15_n199#" 60 0 "a_n73_n163#" 168 0 "a_15_n163#" 168 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_TUVSF7.ext b/mag/sky130_fd_pr__nfet_01v8_TUVSF7.ext
new file mode 100644
index 0000000..7bbc554
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_TUVSF7.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n129#" 629 17.4716 18 -129 ndif 0 0 0 0 0 0 0 0 14964 632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n129#" 630 17.4716 -76 -129 ndif 0 0 0 0 0 0 0 0 14964 632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 600 5428 328 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n217#" 615 210.624 -33 -217 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19584 1060 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n129#" "a_n76_n129#" 146.3
+cap "a_n33_n217#" "a_n76_n129#" 2.91176
+cap "a_n33_n217#" "a_18_n129#" 2.91176
+device msubckt sky130_fd_pr__nfet_01v8 -18 -129 -17 -128 l=36 w=258 "VSUBS" "a_n33_n217#" 72 0 "a_n76_n129#" 258 0 "a_18_n129#" 258 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_TWMWTA.ext b/mag/sky130_fd_pr__nfet_01v8_TWMWTA.ext
new file mode 100644
index 0000000..054bec4
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_TWMWTA.ext
@@ -0,0 +1,15 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n209#" 1169 17.4716 18 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9660 512 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n209#" 1169 17.4716 -76 -209 ndif 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 11776 604 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n297#" 823 148.863 -33 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23364 1320 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_18_n209#" "a_n76_n209#" 465.275
+cap "a_n33_n297#" "a_n76_n209#" 4.47426
+cap "a_n33_n297#" "a_18_n209#" 4.25907
+device msubckt sky130_fd_pr__nfet_01v8 -18 -209 -17 -208 l=36 w=480 "VSUBS" "a_n33_n297#" 72 0 "a_n76_n209#" 480 0 "a_18_n209#" 480 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_4XEGTB.ext b/mag/sky130_fd_pr__pfet_01v8_4XEGTB.ext
new file mode 100644
index 0000000..cfd9691
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4XEGTB.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n96#" 454 0 18 -96 pdif 0 0 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n96#" 454 0 -76 -96 pdif 0 0 0 0 0 0 0 0 0 0 6960 356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352 324 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n33_55#" 349 16.9812 -33 55 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 618 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n158#" 2140 189.504 -112 -158 nw 0 0 0 0 63168 1012 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n76_n96#" "a_n33_55#" 5.51661
+cap "a_18_n96#" "a_n76_n96#" 128.525
+cap "w_n112_n158#" "a_n33_55#" 137.69
+cap "a_18_n96#" "w_n112_n158#" 17.4716
+cap "w_n112_n158#" "a_n76_n96#" 17.4716
+cap "a_18_n96#" "a_n33_55#" 5.51661
+device msubckt sky130_fd_pr__pfet_01v8 -18 -96 -17 -95 l=36 w=120 "w_n112_n158#" "a_n33_55#" 72 0 "a_n76_n96#" 120 0 "a_18_n96#" 120 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_5YXW2B.ext b/mag/sky130_fd_pr__pfet_01v8_5YXW2B.ext
new file mode 100644
index 0000000..ef62770
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_5YXW2B.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n72#" 544 0 18 -72 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n72#" 544 0 -76 -72 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n18_n98#" 262 4.9608 -18 -98 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7056 464 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n134#" 2034 180.096 -112 -134 nw 0 0 0 0 60032 984 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n76_n72#" "a_18_n72#" 218.6
+cap "w_n112_n134#" "a_n76_n72#" 22.3916
+cap "w_n112_n134#" "a_18_n72#" 22.3916
+cap "w_n112_n134#" "a_n18_n98#" 68.2
+device msubckt sky130_fd_pr__pfet_01v8 -18 -72 -17 -71 l=36 w=144 "w_n112_n134#" "a_n18_n98#" 72 0 "a_n76_n72#" 144 0 "a_18_n72#" 144 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_A1DS5R.ext b/mag/sky130_fd_pr__pfet_01v8_A1DS5R.ext
new file mode 100644
index 0000000..1122f2f
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_A1DS5R.ext
@@ -0,0 +1,22 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 1407 107.372 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26458 1818 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 2222 367.2 -109 -86 nw 0 0 0 0 122400 1412 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n36#" "a_n73_n36#" 180.889
+cap "a_n15_n133#" "w_n109_n86#" 133.1
+cap "a_103_n36#" "a_n73_n36#" 68.7887
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_103_n36#" "a_15_n36#" 180.889
+cap "a_15_n36#" "w_n109_n86#" 17.4716
+cap "a_103_n36#" "w_n109_n86#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_A2DS5R.ext b/mag/sky130_fd_pr__pfet_01v8_A2DS5R.ext
new file mode 100644
index 0000000..e4116c0
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_A2DS5R.ext
@@ -0,0 +1,42 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_367_n36#" 1084 0 367 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n36#" 1084 0 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 0 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n81#" 3257 46.6665 -15 -81 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60810 4114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 2423 684 -109 -86 nw 0 0 0 0 228000 1940 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_367_n36#" "a_279_n36#" 180.889
+cap "a_367_n36#" "a_15_n36#" 30.717
+cap "a_367_n36#" "a_103_n36#" 42.4696
+cap "a_n73_n36#" "w_n109_n86#" 17.4716
+cap "a_279_n36#" "w_n109_n86#" 17.4716
+cap "a_15_n36#" "w_n109_n86#" 17.4716
+cap "a_103_n36#" "w_n109_n86#" 17.4716
+cap "a_367_n36#" "a_191_n36#" 68.7887
+cap "a_191_n36#" "w_n109_n86#" 17.4716
+cap "a_279_n36#" "a_n73_n36#" 30.717
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "a_103_n36#" "a_n73_n36#" 68.7887
+cap "a_n15_n81#" "w_n109_n86#" 421.85
+cap "a_279_n36#" "a_15_n36#" 42.4696
+cap "a_103_n36#" "a_279_n36#" 68.7887
+cap "a_103_n36#" "a_15_n36#" 180.889
+cap "a_n73_n36#" "a_191_n36#" 42.4696
+cap "a_367_n36#" "w_n109_n86#" 17.4716
+cap "a_279_n36#" "a_191_n36#" 180.889
+cap "a_191_n36#" "a_15_n36#" 68.7887
+cap "a_103_n36#" "a_191_n36#" 180.889
+device msubckt sky130_fd_pr__pfet_01v8 337 -36 338 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_279_n36#" 288 0 "a_367_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n81#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_A4DS5R.ext b/mag/sky130_fd_pr__pfet_01v8_A4DS5R.ext
new file mode 100644
index 0000000..65ebea2
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_A4DS5R.ext
@@ -0,0 +1,56 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_543_n36#" 1084 0 543 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_455_n36#" 1084 0 455 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_367_n36#" 1084 0 367 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_279_n36#" 1084 0 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 0 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 5182 427.215 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96750 6510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 3171 895.2 -109 -86 nw 0 0 0 0 298400 2292 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_191_n36#" "a_543_n36#" 30.717
+cap "a_279_n36#" "a_15_n36#" 42.4696
+cap "w_n109_n86#" "a_543_n36#" 17.4716
+cap "a_103_n36#" "a_455_n36#" 30.717
+cap "a_191_n36#" "a_455_n36#" 42.4696
+cap "w_n109_n86#" "a_455_n36#" 17.4716
+cap "a_367_n36#" "a_103_n36#" 42.4696
+cap "a_15_n36#" "a_103_n36#" 180.889
+cap "a_191_n36#" "a_367_n36#" 68.7887
+cap "w_n109_n86#" "a_367_n36#" 17.4716
+cap "a_279_n36#" "a_103_n36#" 68.7887
+cap "a_191_n36#" "a_15_n36#" 68.7887
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+cap "a_543_n36#" "a_455_n36#" 180.889
+cap "a_191_n36#" "a_279_n36#" 180.889
+cap "a_15_n36#" "a_n73_n36#" 180.889
+cap "w_n109_n86#" "a_279_n36#" 17.4716
+cap "a_543_n36#" "a_367_n36#" 68.7887
+cap "a_279_n36#" "a_n73_n36#" 30.717
+cap "a_191_n36#" "a_103_n36#" 180.889
+cap "a_279_n36#" "a_543_n36#" 42.4696
+cap "w_n109_n86#" "a_103_n36#" 17.4716
+cap "a_n15_n133#" "w_n109_n86#" 465.85
+cap "a_367_n36#" "a_455_n36#" 180.889
+cap "a_n73_n36#" "a_103_n36#" 68.7887
+cap "a_191_n36#" "w_n109_n86#" 17.4716
+cap "a_279_n36#" "a_455_n36#" 68.7887
+cap "a_191_n36#" "a_n73_n36#" 42.4696
+cap "a_367_n36#" "a_15_n36#" 30.717
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_279_n36#" "a_367_n36#" 180.889
+device msubckt sky130_fd_pr__pfet_01v8 513 -36 514 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_455_n36#" 288 0 "a_543_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 425 -36 426 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_367_n36#" 288 0 "a_455_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 337 -36 338 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_279_n36#" 288 0 "a_367_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_A7DS5R.ext b/mag/sky130_fd_pr__pfet_01v8_A7DS5R.ext
new file mode 100644
index 0000000..5d3f5d1
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_A7DS5R.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n36#" 544 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 544 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 429 43.8785 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8010 594 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 1996 167.424 -109 -86 nw 0 0 0 0 55808 948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n36#" "a_15_n36#" 92.8889
+cap "w_n109_n86#" "a_n15_n133#" 66.55
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "w_n109_n86#" "a_15_n36#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=144 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 144 0 "a_15_n36#" 144 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_A8DS5R.ext b/mag/sky130_fd_pr__pfet_01v8_A8DS5R.ext
new file mode 100644
index 0000000..3efd99a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_A8DS5R.ext
@@ -0,0 +1,35 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_279_n36#" 1084 0 279 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_191_n36#" 1084 0 191 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_103_n36#" 1084 0 103 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 2921 235.547 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54540 3696 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 2049 578.4 -109 -86 nw 0 0 0 0 192800 1764 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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+cap "a_103_n36#" "a_15_n36#" 180.889
+cap "a_n73_n36#" "a_279_n36#" 30.717
+cap "a_191_n36#" "a_n73_n36#" 42.4696
+cap "a_15_n36#" "a_n73_n36#" 180.889
+cap "a_191_n36#" "a_279_n36#" 180.889
+cap "a_15_n36#" "a_279_n36#" 42.4696
+cap "a_103_n36#" "w_n109_n86#" 17.4716
+cap "a_15_n36#" "a_191_n36#" 68.7887
+cap "w_n109_n86#" "a_n15_n133#" 266.2
+cap "w_n109_n86#" "a_n73_n36#" 17.4716
+cap "a_103_n36#" "a_n73_n36#" 68.7887
+cap "w_n109_n86#" "a_279_n36#" 17.4716
+cap "a_103_n36#" "a_279_n36#" 68.7887
+device msubckt sky130_fd_pr__pfet_01v8 249 -36 250 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_191_n36#" 288 0 "a_279_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 161 -36 162 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_103_n36#" 288 0 "a_191_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 73 -36 74 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_15_n36#" 288 0 "a_103_n36#" 288 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_A9DS5R.ext b/mag/sky130_fd_pr__pfet_01v8_A9DS5R.ext
new file mode 100644
index 0000000..9f5860b
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_A9DS5R.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n36#" 1084 0 15 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n36#" 1084 0 -73 -36 pdif 0 0 0 0 0 0 0 0 0 0 16704 692 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10064 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n133#" 660 43.8785 -15 -133 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12330 882 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n86#" 3119 261.6 -109 -86 nw 0 0 0 0 87200 1236 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n36#" "a_15_n36#" 180.889
+cap "a_15_n36#" "w_n109_n86#" 17.4716
+cap "a_n15_n133#" "w_n109_n86#" 66.55
+cap "a_n73_n36#" "w_n109_n86#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 -15 -36 -14 -35 l=30 w=288 "w_n109_n86#" "a_n15_n133#" 60 0 "a_n73_n36#" 288 0 "a_15_n36#" 288 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_ACAZ2B.ext b/mag/sky130_fd_pr__pfet_01v8_ACAZ2B.ext
new file mode 100644
index 0000000..bf04f66
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ACAZ2B.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n108#" 544 0 18 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n108#" 544 0 -76 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n33_67#" 382 16.9812 -33 67 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11592 666 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n170#" 2322 205.632 -112 -170 nw 0 0 0 0 68544 1060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n76_n108#" "a_n33_67#" 7.79013
+cap "a_18_n108#" "a_n76_n108#" 218.6
+cap "w_n112_n170#" "a_n33_67#" 137.69
+cap "a_18_n108#" "w_n112_n170#" 22.3916
+cap "w_n112_n170#" "a_n76_n108#" 22.3916
+cap "a_18_n108#" "a_n33_67#" 7.79013
+device msubckt sky130_fd_pr__pfet_01v8 -18 -108 -17 -107 l=36 w=144 "w_n112_n170#" "a_n33_67#" 72 0 "a_n76_n108#" 144 0 "a_18_n108#" 144 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.ext b/mag/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.ext
new file mode 100644
index 0000000..fef7bcf
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ACAZ2B_v2.ext
@@ -0,0 +1,18 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n108#" 544 0 18 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n108#" 544 0 -76 -108 pdif 0 0 0 0 0 0 0 0 0 0 8352 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5168 372 6624 380 0 0 0 0 0 0 0 0 0 0
+node "a_n68_67#" 386 20.4792 -68 67 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12912 706 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n170#" 2322 205.632 -112 -170 nw 0 0 0 0 68544 1060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n76_n108#" "a_18_n108#" 218.6
+cap "w_n112_n170#" "a_n76_n108#" 22.3916
+cap "a_n76_n108#" "a_n68_67#" 26.093
+cap "w_n112_n170#" "a_18_n108#" 22.3916
+cap "w_n112_n170#" "a_n68_67#" 141.72
+device msubckt sky130_fd_pr__pfet_01v8 -18 -108 -17 -107 l=36 w=144 "w_n112_n170#" "a_n68_67#" 72 0 "a_n76_n108#" 144 0 "a_18_n108#" 144 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_ACPHKB.ext b/mag/sky130_fd_pr__pfet_01v8_ACPHKB.ext
new file mode 100644
index 0000000..e597ad3
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ACPHKB.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n78#" 318 0 15 -78 pdif 0 0 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n78#" 318 0 -73 -78 pdif 0 0 0 0 0 0 0 0 0 0 4872 284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3128 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_37#" 338 16.0749 -33 37 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8586 546 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n140#" 1918 160.884 -109 -140 nw 0 0 0 0 53628 928 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n78#" "a_n33_37#" 4.60465
+cap "a_n73_n78#" "a_15_n78#" 56.2222
+cap "w_n109_n140#" "a_n33_37#" 134.39
+cap "w_n109_n140#" "a_n73_n78#" 17.4716
+cap "a_n73_n78#" "a_n33_37#" 4.60465
+cap "w_n109_n140#" "a_15_n78#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 -15 -78 -14 -77 l=30 w=84 "w_n109_n140#" "a_n33_37#" 60 0 "a_n73_n78#" 84 0 "a_15_n78#" 84 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_AZHELG.ext b/mag/sky130_fd_pr__pfet_01v8_AZHELG.ext
new file mode 100644
index 0000000..1394d23
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_AZHELG.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n22#" 604 0 15 -22 pdif 0 0 0 0 0 0 0 0 0 0 9280 436 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5712 404 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n72_n22#" 614 0 -72 -22 pdif 0 0 0 0 0 0 0 0 0 0 9120 434 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5712 404 4830 302 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n53#" 349 4.5315 -15 -53 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6510 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n58#" 2012 168.732 -109 -58 nw 0 0 0 0 56244 952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n22#" "a_n72_n22#" 90.8852
+cap "w_n109_n58#" "a_n15_n53#" 64.35
+cap "a_15_n22#" "w_n109_n58#" 17.4716
+cap "w_n109_n58#" "a_n72_n22#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8 -15 -22 -14 -21 l=30 w=160 "w_n109_n58#" "a_n15_n53#" 60 0 "a_n72_n22#" 160 0 "a_15_n22#" 160 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_KQRM7Z.ext b/mag/sky130_fd_pr__pfet_01v8_KQRM7Z.ext
new file mode 100644
index 0000000..925e0e8
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_KQRM7Z.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n156#" 904 0 18 -156 pdif 0 0 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n156#" 904 0 -76 -156 pdif 0 0 0 0 0 0 0 0 0 0 13920 596 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8432 564 5060 312 0 0 0 0 0 0 0 0 0 0
+node "a_n33_115#" 512 16.9812 -33 115 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15048 858 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n218#" 3051 270.144 -112 -218 nw 0 0 0 0 90048 1252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n76_n156#" "a_18_n156#" 239.525
+cap "w_n112_n218#" "a_n76_n156#" 17.4716
+cap "a_n76_n156#" "a_n33_115#" 4.42497
+cap "w_n112_n218#" "a_18_n156#" 17.4716
+cap "a_n33_115#" "a_18_n156#" 4.42497
+cap "w_n112_n218#" "a_n33_115#" 137.69
+device msubckt sky130_fd_pr__pfet_01v8 -18 -156 -17 -155 l=36 w=240 "w_n112_n218#" "a_n33_115#" 72 0 "a_n76_n156#" 240 0 "a_18_n156#" 240 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_MP0P75.ext b/mag/sky130_fd_pr__pfet_01v8_MP0P75.ext
new file mode 100644
index 0000000..05467e8
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MP0P75.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n64#" 551 0 15 -64 pdif 0 0 0 0 0 0 0 0 0 0 8700 416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3944 300 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n64#" 551 0 -73 -64 pdif 0 0 0 0 0 0 0 0 0 0 8700 416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3944 300 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n161#" 446 16.0749 -33 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10566 678 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n164#" 2433 204.048 -109 -164 nw 0 0 0 0 68016 1060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n64#" "a_n33_n161#" 3.04615
+cap "a_15_n64#" "a_n73_n64#" 70.8889
+cap "w_n109_n164#" "a_n33_n161#" 134.39
+cap "a_15_n64#" "a_n33_n161#" 3.04615
+device msubckt sky130_fd_pr__pfet_01v8 -15 -64 -14 -63 l=30 w=150 "w_n109_n164#" "a_n33_n161#" 60 0 "a_n73_n64#" 150 0 "a_15_n64#" 150 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_MP1P4U.ext b/mag/sky130_fd_pr__pfet_01v8_MP1P4U.ext
new file mode 100644
index 0000000..8e8097d
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MP1P4U.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n144#" 1054 0 15 -144 pdif 0 0 0 0 0 0 0 0 0 0 16240 676 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9792 644 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n144#" 1054 0 -73 -144 pdif 0 0 0 0 0 0 0 0 0 0 16240 676 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9792 644 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n241#" 657 16.0749 -33 -241 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14466 938 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n244#" 3447 289.068 -109 -244 nw 0 0 0 0 96356 1320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n144#" "a_n33_n241#" 1.53488
+cap "a_15_n144#" "a_n73_n144#" 153.29
+cap "w_n109_n244#" "a_n33_n241#" 134.39
+cap "a_15_n144#" "w_n109_n244#" 17.4716
+cap "w_n109_n244#" "a_n73_n144#" 17.4716
+cap "a_15_n144#" "a_n33_n241#" 1.53488
+device msubckt sky130_fd_pr__pfet_01v8 -15 -144 -14 -143 l=30 w=280 "w_n109_n244#" "a_n33_n241#" 60 0 "a_n73_n144#" 280 0 "a_15_n144#" 280 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_MP3P0U.ext b/mag/sky130_fd_pr__pfet_01v8_MP3P0U.ext
new file mode 100644
index 0000000..50fd655
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MP3P0U.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n236#" 2256 0 15 -236 pdif 0 0 0 0 0 0 0 0 0 0 34800 1316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20672 1284 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n236#" 2256 0 -73 -236 pdif 0 0 0 0 0 0 0 0 0 0 34800 1316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20672 1284 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_395#" 1172 16.0749 -33 395 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24066 1578 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n298#" 5942 498.348 -109 -298 nw 0 0 0 0 166116 1960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n236#" "a_n33_395#" 1.53488
+cap "a_15_n236#" "a_n73_n236#" 323.613
+cap "w_n109_n298#" "a_n33_395#" 134.39
+cap "a_15_n236#" "w_n109_n298#" 17.4716
+cap "w_n109_n298#" "a_n73_n236#" 17.4716
+cap "a_15_n236#" "a_n33_395#" 1.53488
+device msubckt sky130_fd_pr__pfet_01v8 -15 -236 -14 -235 l=30 w=600 "w_n109_n298#" "a_n33_395#" 60 0 "a_n73_n236#" 600 0 "a_15_n236#" 600 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_NC2CGG.ext b/mag/sky130_fd_pr__pfet_01v8_NC2CGG.ext
new file mode 100644
index 0000000..eec0f8e
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_NC2CGG.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n240#" 1765 0 15 -240 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12716 816 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n240#" 1787 0 -73 -240 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14824 940 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n337#" 962 16.3929 -33 -337 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20586 1346 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n240#" "a_n73_n240#" 196.778
+cap "w_n109_n340#" "a_n33_n337#" 122.65
+cap "a_15_n240#" "w_n109_n340#" 8.7358
+cap "w_n109_n340#" "a_n73_n240#" 8.7358
+device msubckt sky130_fd_pr__pfet_01v8 -15 -240 -14 -239 l=30 w=480 "w_n109_n340#" "a_n33_n337#" 60 0 "a_n73_n240#" 480 0 "a_15_n240#" 480 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_TPJM7Z.ext b/mag/sky130_fd_pr__pfet_01v8_TPJM7Z.ext
new file mode 100644
index 0000000..70eddc2
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_TPJM7Z.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n276#" 1806 0 18 -276 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n276#" 1806 0 -76 -276 pdif 0 0 0 0 0 0 0 0 0 0 27840 1076 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16592 1044 9476 504 0 0 0 0 0 0 0 0 0 0
+node "a_n33_235#" 835 16.9812 -33 235 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23688 1338 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n338#" 4872 431.424 -112 -338 nw 0 0 0 0 143808 1732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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+cap "a_n76_n276#" "a_n33_235#" 3.56637
+cap "a_18_n276#" "a_n76_n276#" 461.525
+cap "w_n112_n338#" "a_n33_235#" 137.69
+cap "a_18_n276#" "w_n112_n338#" 17.4716
+cap "w_n112_n338#" "a_n76_n276#" 17.4716
+cap "a_18_n276#" "a_n33_235#" 3.56637
+device msubckt sky130_fd_pr__pfet_01v8 -18 -276 -17 -275 l=36 w=480 "w_n112_n338#" "a_n33_235#" 72 0 "a_n76_n276#" 480 0 "a_18_n276#" 480 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_UUCHZP.ext b/mag/sky130_fd_pr__pfet_01v8_UUCHZP.ext
new file mode 100644
index 0000000..cd7d401
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_UUCHZP.ext
@@ -0,0 +1,41 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_114_n220#" 1630 0 114 -220 pdif 0 0 0 0 0 0 0 0 0 0 25960 998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_18_n220#" 1606 0 18 -220 pdif 0 0 0 0 0 0 0 0 0 0 26400 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 6854 390 0 0 0 0 0 0 0 0 0 0
+node "a_n78_n220#" 1605 0 -78 -220 pdif 0 0 0 0 0 0 0 0 0 0 26400 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n173_n220#" 1630 0 -173 -220 pdif 0 0 0 0 0 0 0 0 0 0 25960 998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15232 964 6854 390 0 0 0 0 0 0 0 0 0 0
+node "a_63_n366#" 847 77.4058 63 -366 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24012 1356 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n366#" 847 77.4058 -129 -366 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24012 1356 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n33_310#" 861 85.4998 -33 310 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24372 1376 0 0 2244 200 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n209_n320#" 2924 780.672 -209 -320 nw 0 0 0 0 260224 2116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n173_n220#" "w_n209_n320#" 17.4716
+cap "a_18_n220#" "a_n33_310#" 0.647059
+cap "a_n78_n220#" "a_18_n220#" 238.452
+cap "a_63_n366#" "a_18_n220#" 0.717391
+cap "a_n33_310#" "w_n209_n320#" 107.25
+cap "a_n78_n220#" "w_n209_n320#" 17.4716
+cap "a_63_n366#" "w_n209_n320#" 108.89
+cap "a_n78_n220#" "a_n173_n220#" 238.452
+cap "a_n129_n366#" "w_n209_n320#" 108.89
+cap "a_18_n220#" "a_114_n220#" 238.452
+cap "a_n78_n220#" "a_n33_310#" 0.647059
+cap "a_63_n366#" "a_n33_310#" 19.9333
+cap "a_114_n220#" "w_n209_n320#" 17.4716
+cap "a_n129_n366#" "a_n173_n220#" 0.717391
+cap "a_18_n220#" "w_n209_n320#" 17.4716
+cap "a_n129_n366#" "a_n33_310#" 19.9333
+cap "a_n78_n220#" "a_n129_n366#" 0.717391
+cap "a_63_n366#" "a_n129_n366#" 36.5806
+cap "a_n173_n220#" "a_114_n220#" 58.2047
+cap "a_n78_n220#" "a_114_n220#" 93.5696
+cap "a_63_n366#" "a_114_n220#" 0.717391
+cap "a_18_n220#" "a_n173_n220#" 139.494
+device msubckt sky130_fd_pr__pfet_01v8 78 -220 79 -219 l=36 w=440 "w_n209_n320#" "a_63_n366#" 72 0 "a_18_n220#" 440 0 "a_114_n220#" 440 0
+device msubckt sky130_fd_pr__pfet_01v8 -18 -220 -17 -219 l=36 w=440 "w_n209_n320#" "a_n33_310#" 72 0 "a_n78_n220#" 440 0 "a_18_n220#" 440 0
+device msubckt sky130_fd_pr__pfet_01v8 -114 -220 -113 -219 l=36 w=440 "w_n209_n320#" "a_n129_n366#" 72 0 "a_n173_n220#" 440 0 "a_n78_n220#" 440 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_XZZ25Z.ext b/mag/sky130_fd_pr__pfet_01v8_XZZ25Z.ext
new file mode 100644
index 0000000..43e06b0
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_XZZ25Z.ext
@@ -0,0 +1,19 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_18_n136#" 754 0 18 -136 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n76_n136#" 754 0 -76 -136 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 4324 280 0 0 0 0 0 0 0 0 0 0
+node "a_n33_95#" 458 16.9812 -33 95 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13608 778 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n112_n198#" 2747 243.264 -112 -198 nw 0 0 0 0 81088 1172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_95#" "w_n112_n198#" 137.69
+cap "a_18_n136#" "w_n112_n198#" 17.4716
+cap "a_n76_n136#" "w_n112_n198#" 17.4716
+cap "a_18_n136#" "a_n33_95#" 4.69594
+cap "a_n76_n136#" "a_n33_95#" 4.69594
+cap "a_18_n136#" "a_n76_n136#" 202.525
+device msubckt sky130_fd_pr__pfet_01v8 -18 -136 -17 -135 l=36 w=200 "w_n112_n198#" "a_n33_95#" 72 0 "a_n76_n136#" 200 0 "a_18_n136#" 200 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_hvt_N83GLL.ext b/mag/sky130_fd_pr__pfet_01v8_hvt_N83GLL.ext
new file mode 100644
index 0000000..7f34e82
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_hvt_N83GLL.ext
@@ -0,0 +1,17 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 754 0 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 754 0 -73 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n132#" 415 4.611 -15 -132 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7740 576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n136#" 2324 194.892 -109 -136 nw 0 0 0 0 64964 1032 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n100#" "a_n73_n100#" 127.111
+cap "w_n109_n136#" "a_n15_n132#" 64.9
+cap "a_15_n100#" "w_n109_n136#" 17.4716
+cap "w_n109_n136#" "a_n73_n100#" 17.4716
+device msubckt sky130_fd_pr__pfet_01v8_hvt -15 -100 -14 -99 l=30 w=200 "w_n109_n136#" "a_n15_n132#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git a/mag/sky130_fd_sc_hd__clkbuf_16.ext b/mag/sky130_fd_sc_hd__clkbuf_16.ext
new file mode 100644
index 0000000..4a61fce
--- /dev/null
+++ b/mag/sky130_fd_sc_hd__clkbuf_16.ext
@@ -0,0 +1,86 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 1840 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 1685 153 1719 187 li
+port "X" 6 1593 153 1627 187 li
+port "X" 6 1593 221 1627 255 li
+port "X" 6 1685 221 1719 255 li
+port "X" 6 1685 289 1719 323 li
+port "X" 6 1593 289 1627 323 li
+port "VPWR" 5 0 496 1840 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 29 221 63 255 li
+port "A" 1 29 153 63 187 li
+port "VPB" 4 46 544 46 544 nw
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 46 0 46 0 pw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_16" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 6141 1371.06 29 -17 m1 0 0 0 0 0 0 0 0 51156 3066 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119810 5922 176640 3872 0 0 0 0 0 0 0 0 0 0
+node "X" 13624 358.952 1593 289 li 0 0 0 0 0 0 0 0 37632 2240 89600 4096 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 236801 9112 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 13355 393.26 29 527 m1 0 0 0 0 0 0 0 0 0 0 121800 5618 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 149441 7044 176640 3872 0 0 0 0 0 0 0 0 0 0
+node "a_110_47#" 13806 1916.4 110 47 ndif 0 0 0 0 0 0 0 0 9408 560 22400 1024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 303885 16452 0 0 109922 4506 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 2351 538.585 29 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83394 4098 0 0 7056 350 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 10147 1845.11 29 527 nw 0 0 0 0 615036 4474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_110_47#" "VPWR" 1186.85
+cap "VGND" "X" 2233
+cap "VGND" "A" 129.616
+cap "X" "VPB" 31.1615
+cap "VPB" "A" 264.83
+cap "VGND" "a_110_47#" 990.729
+cap "VGND" "VPWR" 72.4031
+cap "X" "A" 2.45745
+cap "a_110_47#" "VPB" 1313.11
+cap "VPWR" "VPB" 1000.66
+cap "a_110_47#" "X" 3326.02
+cap "VPWR" "X" 3419.81
+cap "a_110_47#" "A" 544.488
+cap "VPWR" "A" 89.8988
+device msubckt sky130_fd_pr__nfet_01v8 1713 47 1714 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1627 47 1628 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1541 47 1542 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1455 47 1456 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1369 47 1370 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1283 47 1284 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1197 47 1198 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1111 47 1112 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 1026 47 1027 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 940 47 941 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 854 47 855 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 768 47 769 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 682 47 683 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 596 47 597 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 510 47 511 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 424 47 425 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 338 47 339 48 l=30 w=84 "VNB" "A" 60 0 "a_110_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 252 47 253 48 l=30 w=84 "VNB" "A" 60 0 "VGND" 84 0 "a_110_47#" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 166 47 167 48 l=30 w=84 "VNB" "A" 60 0 "a_110_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "VGND" 84 0 "a_110_47#" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1713 297 1714 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1627 297 1628 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1541 297 1542 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1455 297 1456 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1369 297 1370 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1283 297 1284 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1197 297 1198 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1111 297 1112 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 1026 297 1027 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 940 297 941 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 854 297 855 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 768 297 769 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 682 297 683 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 596 297 597 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 510 297 511 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 424 297 425 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 338 297 339 298 l=30 w=200 "VPB" "A" 60 0 "a_110_47#" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 252 297 253 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "a_110_47#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 166 297 167 298 l=30 w=200 "VPB" "A" 60 0 "a_110_47#" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "a_110_47#" 200 0
diff --git a/mag/sky130_fd_sc_hd__clkbuf_2.ext b/mag/sky130_fd_sc_hd__clkbuf_2.ext
new file mode 100644
index 0000000..56e8fda
--- /dev/null
+++ b/mag/sky130_fd_sc_hd__clkbuf_2.ext
@@ -0,0 +1,50 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 368 48 m1
+port "VGND" 2 46 0 46 0 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 305 357 339 391 li
+port "X" 6 305 289 339 323 li
+port "X" 6 305 153 339 187 li
+port "X" 6 305 221 339 255 li
+port "VPWR" 5 0 496 368 592 m1
+port "VPWR" 5 46 544 46 544 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 121 221 155 255 li
+port "A" 1 121 153 155 187 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_2" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 883 321.253 29 -17 m1 0 0 0 0 0 0 0 0 9828 570 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23152 1156 35328 928 0 0 0 0 0 0 0 0 0 0
+node "X" 1059 38.7431 305 221 li 0 0 0 0 0 0 0 0 4536 276 10800 508 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29598 1276 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 1987 81.932 29 527 m1 0 0 0 0 0 0 0 0 0 0 23400 1034 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28503 1286 35328 928 0 0 0 0 0 0 0 0 0 0
+node "a_27_47#" 2319 304.193 27 47 ndif 0 0 0 0 0 0 0 0 4452 274 10600 506 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37140 1976 0 0 30620 1560 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 766 181.455 121 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18261 1132 0 0 8352 376 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 2351 427.572 29 527 nw 0 0 0 0 142524 1530 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "X" "VGND" 230.998
+cap "X" "VPB" 32.8131
+cap "A" "a_27_47#" 370.873
+cap "a_27_47#" "VPWR" 337.736
+cap "A" "VPWR" 78.9081
+cap "a_27_47#" "VGND" 203.464
+cap "A" "VGND" 66.1479
+cap "X" "a_27_47#" 425.353
+cap "VGND" "VPWR" 14.469
+cap "X" "A" 37.8529
+cap "X" "VPWR" 266.971
+cap "a_27_47#" "VPB" 185.622
+cap "A" "VPB" 74.0288
+cap "VPB" "VPWR" 232.858
+device msubckt sky130_fd_pr__nfet_01v8 259 47 260 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 175 47 176 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "a_27_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 259 297 260 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 175 297 176 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "a_27_47#" 200 0 "VPWR" 200 0
diff --git a/mag/sky130_fd_sc_hd__clkbuf_4.ext b/mag/sky130_fd_sc_hd__clkbuf_4.ext
new file mode 100644
index 0000000..f44aa7f
--- /dev/null
+++ b/mag/sky130_fd_sc_hd__clkbuf_4.ext
@@ -0,0 +1,51 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 552 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 489 221 523 255 li
+port "X" 6 489 153 523 187 li
+port "X" 6 397 289 431 323 li
+port "VPWR" 5 0 496 552 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 121 221 155 255 li
+port "A" 1 121 153 155 187 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_4" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 1475 459.565 29 -17 m1 0 0 0 0 0 0 0 0 15204 866 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34320 1748 52992 1296 0 0 0 0 0 0 0 0 0 0
+node "X" 2919 108.035 397 289 li 0 0 0 0 0 0 0 0 9408 560 22400 1024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53058 2332 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 3167 120.848 29 527 m1 0 0 0 0 0 0 0 0 0 0 36400 1564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43298 2024 52992 1296 0 0 0 0 0 0 0 0 0 0
+node "a_27_47#" 4266 615.301 27 47 ndif 0 0 0 0 0 0 0 0 4452 274 10600 506 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69507 4264 0 0 36524 1904 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 814 176.642 121 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17040 1124 0 0 7980 368 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 3326 604.764 29 527 nw 0 0 0 0 201588 1898 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "A" "VGND" 62.0948
+cap "a_27_47#" "VPWR" 413.347
+cap "VPB" "A" 77.2412
+cap "VPWR" "X" 712.669
+cap "VPWR" "VGND" 20.7593
+cap "VPB" "VPWR" 352.927
+cap "A" "VPWR" 34.5962
+cap "a_27_47#" "X" 659.675
+cap "a_27_47#" "VGND" 279.339
+cap "VPB" "a_27_47#" 303.281
+cap "X" "VGND" 433.51
+cap "VPB" "X" 29.9537
+cap "A" "a_27_47#" 381.986
+cap "A" "X" 30.4287
+device msubckt sky130_fd_pr__nfet_01v8 435 47 436 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 349 47 350 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 263 47 264 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 177 47 178 48 l=30 w=84 "VNB" "a_27_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "a_27_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 434 297 435 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 348 297 349 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 262 297 263 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 176 297 177 298 l=30 w=200 "VPB" "a_27_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "a_27_47#" 200 0 "VPWR" 200 0
diff --git a/mag/sky130_fd_sc_hd__clkbuf_8.ext b/mag/sky130_fd_sc_hd__clkbuf_8.ext
new file mode 100644
index 0000000..e7e1df9
--- /dev/null
+++ b/mag/sky130_fd_sc_hd__clkbuf_8.ext
@@ -0,0 +1,64 @@
+timestamp 1646908997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8_hvt l=l w=w a1=as p1=ps a2=ad p2=pd
+port "VGND" 2 0 -48 1012 48 m1
+port "VGND" 2 29 -17 63 17 m1
+port "X" 6 857 221 891 255 li
+port "X" 6 765 221 799 255 li
+port "X" 6 857 289 891 323 li
+port "X" 6 857 153 891 187 li
+port "X" 6 765 153 799 187 li
+port "X" 6 765 289 799 323 li
+port "VPWR" 5 0 496 1012 592 m1
+port "VPWR" 5 29 527 63 561 m1
+port "A" 1 29 221 63 255 li
+port "A" 1 29 153 63 187 li
+port "VPB" 4 29 527 63 561 nw
+port "VNB" 3 29 -17 63 17 pw
+node "clkbuf_8" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 3237 788.777 29 -17 m1 0 0 0 0 0 0 0 0 27804 1670 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65112 3254 97152 2216 0 0 0 0 0 0 0 0 0 0
+node "X" 6434 196.116 765 289 li 0 0 0 0 0 0 0 0 18816 1120 44800 2048 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126264 4548 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 7144 218.138 29 527 m1 0 0 0 0 0 0 0 0 0 0 66000 3060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90440 4148 97152 2216 0 0 0 0 0 0 0 0 0 0
+node "a_110_47#" 6496 971.627 110 47 ndif 0 0 0 0 0 0 0 0 4704 280 11200 512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 149880 8246 0 0 49650 2086 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 1261 313.482 29 153 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41850 2154 0 0 7686 370 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 5762 1047.74 29 527 nw 0 0 0 0 349248 2818 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 29 -17 pw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_110_47#" "X" 1396.49
+cap "VPWR" "VGND" 45.2468
+cap "a_110_47#" "A" 386.172
+cap "A" "X" 6.49812
+cap "a_110_47#" "VPB" 640.361
+cap "VPWR" "a_110_47#" 702.148
+cap "VPB" "X" 30.647
+cap "VPB" "A" 139.43
+cap "VPWR" "X" 1768.14
+cap "VPWR" "A" 84.1413
+cap "VPWR" "VPB" 620.47
+cap "a_110_47#" "VGND" 449.413
+cap "VGND" "X" 1096.83
+cap "A" "VGND" 86.188
+device msubckt sky130_fd_pr__nfet_01v8 854 47 855 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 768 47 769 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 682 47 683 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 596 47 597 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 510 47 511 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 424 47 425 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 338 47 339 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "X" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 252 47 253 48 l=30 w=84 "VNB" "a_110_47#" 60 0 "VGND" 84 0 "X" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 166 47 167 48 l=30 w=84 "VNB" "A" 60 0 "a_110_47#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_01v8 80 47 81 48 l=30 w=84 "VNB" "A" 60 0 "VGND" 84 0 "a_110_47#" 84 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 854 297 855 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 768 297 769 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 682 297 683 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 596 297 597 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 510 297 511 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 424 297 425 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 338 297 339 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "X" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 252 297 253 298 l=30 w=200 "VPB" "a_110_47#" 60 0 "VPWR" 200 0 "X" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 166 297 167 298 l=30 w=200 "VPB" "A" 60 0 "a_110_47#" 200 0 "VPWR" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_hvt 80 297 81 298 l=30 w=200 "VPB" "A" 60 0 "VPWR" 200 0 "a_110_47#" 200 0
diff --git a/mag/unused/example_por.ext b/mag/unused/example_por.ext
new file mode 100644
index 0000000..253748b
--- /dev/null
+++ b/mag/unused/example_por.ext
@@ -0,0 +1,941 @@
+timestamp 1620310959
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 1 0 408 0 1 7841
+use sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 1 0 1657 0 1 7841
+use sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 -1 0 371 0 1 6769
+use sky130_fd_pr__nfet_g5v0d10v5_TGFUGS sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 1 0 1515 0 1 6769
+use sky130_fd_pr__pfet_g5v0d10v5_YEUEBV sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 1 0 5018 0 1 7841
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 1 0 3878 0 1 7841
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 1 0 3392 0 1 7841
+use sky130_fd_pr__pfet_g5v0d10v5_YUHPBG sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 1 0 2906 0 1 7841
+use sky130_fd_pr__nfet_g5v0d10v5_PKVMTM sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 1 0 2660 0 1 6770
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 1 0 6644 0 1 7841
+use sky130_fd_pr__pfet_g5v0d10v5_YUHPXE sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 1 0 6158 0 1 7841
+use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_1 1 0 7477 0 1 7438
+use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_0 1 0 8523 0 1 6404
+use sky130_fd_sc_hvl__schmittbuf_1 sky130_fd_sc_hvl__schmittbuf_1_0 1 0 7467 0 1 6404
+use sky130_fd_sc_hvl__inv_8 sky130_fd_sc_hvl__inv_8_0 1 0 9397 0 1 7438
+use sky130_fd_sc_hvl__fill_4 sky130_fd_sc_hvl__fill_4_0 1 0 10443 0 1 6404
+use sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 1 0 5446 0 1 3098
+use sky130_fd_pr__cap_mim_m3_2_W5U4AW sky130_fd_pr__cap_mim_m3_2_W5U4AW_0 1 0 7970 0 1 3151
+use sky130_fd_pr__cap_mim_m3_1_WRT4AW sky130_fd_pr__cap_mim_m3_1_WRT4AW_0 -1 0 7027 0 1 3151
+port "vdd1v8" 1 10974 7962 11180 8291 m4
+port "porb_h" 3 10969 6765 11342 6834 m3
+port "vss" 2 38 7255 232 7655 m4
+port "por_l" 4 11189 7491 11344 7551 m3
+port "porb_l" 5 11188 7856 11343 7916 m3
+port "vdd3v3" 0 38 7965 73 8283 m4
+node "m4_4101_51#" 0 1437.67 4101 51 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4290400 13784 0 0 0 0
+node "m1_6249_7690#" 1 239.251 6249 7690 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44282 1254 0 0 0 0 0 0 0 0 0 0
+node "m1_4109_7872#" 2 1075.75 4109 7872 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 315882 4246 0 0 0 0 0 0 0 0 0 0
+node "m1_3966_7645#" 7 696.51 3966 7645 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 440096 10316 0 0 0 0 0 0 0 0 0 0
+node "m1_4283_8081#" 4 660.15 4283 8081 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64416 3016 0 0 0 0 0 0 0 0 0 0
+node "m1_721_6815#" 16 3255.62 721 6815 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 582299 16418 37291 1466 0 0 0 0 0 0 0 0
+node "m1_2756_6573#" 13 864.581 2756 6573 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 402235 12910 0 0 0 0 0 0 0 0 0 0
+node "m1_2993_7658#" 0 68.4209 2993 7658 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44822 906 0 0 0 0 0 0 0 0 0 0
+node "m1_627_7892#" 2 1149.25 627 7892 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 298384 4660 0 0 0 0 0 0 0 0 0 0
+node "m1_502_7653#" 14 1220.58 502 7653 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 525113 14858 38984 1456 0 0 0 0 0 0 0 0
+node "m1_185_6573#" 12 884.33 185 6573 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 376744 12172 0 0 0 0 0 0 0 0 0 0
+node "vdd1v8" 7 6498.93 10974 7962 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 544221 7420 544221 7420 544221 7420 1295931 8536 0 0 0 0
+node "li_10655_165#" 15 198.324 10655 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38880 792 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_9883_165#" 22 324.553 9883 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_9111_165#" 22 324.553 9111 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_8339_165#" 22 324.553 8339 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7567_165#" 22 324.553 7567 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6795_165#" 22 324.553 6795 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6023_165#" 22 324.553 6023 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5251_165#" 22 324.553 5251 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4479_165#" 22 324.553 4479 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3707_165#" 22 324.553 3707 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2935_165#" 22 324.553 2935 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_2163_165#" 22 324.553 2163 165 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83592 1206 0 0 0 0 0 0 0 0 0 0 0 0
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+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -231.926
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 3737.49
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" 46.8043
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -9.1
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -328.82
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_510_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 266.893
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 0.1375
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -255.54
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -110.025
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_510_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" -18.4286
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 122.431
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -110.275
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3737.49
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 948.59
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 97.465
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -0.4
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_n2932#" 86.6503
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -16.8
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 266.893
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" -164.41
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 0.220724
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 55.5374
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" -170.65
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" 39.8461
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -73.0333
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_n2932#" -18.4286
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -110.275
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" -18.4286
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -328.82
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -110.025
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -261.905
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 86.6503
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 86.4296
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" -170.61
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" -9.21429
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -430.46
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -335.05
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -110.025
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_n2932#" 266.893
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -104.709
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -110.275
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_n2932#" -18.4286
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 848.765
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3659.44
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -246.04
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_n2932#" -110.275
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_n2932#" -9.21429
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 206.596
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_n2932#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -68.884
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -328.82
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 70.6324
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_n2932#" 168.184
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 861.238
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_n2932#" 68.2218
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -842.105
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "vss" -21.0305
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -167.115
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 46.9545
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 235.455
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -48.8985
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 198.565
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" 1912.61
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "vss" -336.02
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 1058.86
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -164.41
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 948.59
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 88.29
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3887.43
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 88.29
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3887.43
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -164.41
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 948.59
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -215.23
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3809.38
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 848.765
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -11.535
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 204.586
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1139.65
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 278.849
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -164.41
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -220.55
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -842.105
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 202.819
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "vss" -121.88
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 230.215
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -146.084
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -159.288
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -201.276
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 877.565
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 41.58
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 995.165
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1912.61
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 41.58
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -6.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -6.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -26.275
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 3887.43
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 767.29
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -26.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 884.89
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -164.41
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -26.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -6.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -6.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -164.41
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 3887.43
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 767.29
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 884.89
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -26.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -26.275
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3809.38
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 667.465
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -26.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 785.065
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -6.295
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -215.23
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -6.295
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 444.23
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" 459.825
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -164.41
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -162.59
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1139.65
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "vss" -45.2345
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -167.115
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" -842.105
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 74.3505
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" 10.7949
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 235.455
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 1058.86
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 316.165
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "vss" -336.02
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "vss" -90.8865
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -4.32
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -5.6685
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -5.4
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" 10.7949
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1912.61
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" 21.5898
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -165.547
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -163.605
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 948.59
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -164.41
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -110.275
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 21.5898
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 205.89
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -110.275
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -157.89
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 3887.43
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "vss" -118.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" 21.5898
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" -0.4
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" -0.5
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -164.41
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "vss" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 205.89
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 3887.43
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" 19.9293
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 948.59
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" 10.7949
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 106.065
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -118.295
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "vss" 848.765
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "vss" -110.275
+cap "vss" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -110.275
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -162.79
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 3809.38
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -191.144
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" 21.5898
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -167.525
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -215.23
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -220.55
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -164.41
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 261.478
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 10.7949
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4756_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 17.2805
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 301.464
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1139.65
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4756_2500#" 3.55271e-15
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" 5.04545
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_80_n200#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" -93.9733
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" 409.383
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4508_2500#" 35.4925
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4508_2500#" -50.141
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" -0.401664
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_80_n200#" 1.68976
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" 12.9375
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" "vdd3v3" 3.37952
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" 341.936
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4508_2500#" -9.25714
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" 63.1257
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" 309.947
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_80_n200#" 17.1429
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4122_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_2500#" -9.25714
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" 1.69486
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#" -11.1313
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#" 6.21745
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_2500#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#" -27.6552
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" -60.272
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" 3.37952
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" 59.9626
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4122_2500#" -156.958
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#" 1414.8
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_2500#" 83.4
+cap "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" -88.3111
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#" -16.5239
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#" -322.809
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2192_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" -18.5143
+cap "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#" -12.9168
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2192_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#" -18.5143
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2192_2500#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#" -27.6552
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" -42.3152
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#" 91.1991
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 19.8825
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" 13.8
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -25.1088
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" -18.5143
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -9.3
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" -9.25714
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 1003.79
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 244.655
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 146.776
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 1685.37
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 13.8
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -145.59
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n262_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -9.25714
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "li_7870_6775#" 75.2751
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -339.682
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -16.6152
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" -181.42
+cap "li_7870_6775#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 120.994
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 265.63
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" 37.4027
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" -9.25714
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -222.665
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -18.5143
+cap "sky130_fd_sc_hvl__buf_8_0/VGND" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 195.05
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_64_207#" "sky130_fd_sc_hvl__buf_8_0/VGND" 19.014
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/a_217_207#" 51.3644
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__buf_8_0/VGND" 8.84916
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" -18.5143
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" 11.04
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1685.37
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 11.4031
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/a_64_207#" 121.653
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/VGND" 5.32907e-15
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_sc_hvl__buf_8_0/VGND" 5.315
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 228.873
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/A" 7.10543e-15
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__buf_8_0/VGND" 67.7492
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -328.82
+cap "sky130_fd_sc_hvl__buf_8_0/VGND" "sky130_fd_sc_hvl__schmittbuf_1_0/a_78_463#" 2.1877
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__buf_8_0/A" -3.13023
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" "sky130_fd_sc_hvl__buf_8_0/VGND" -21.8317
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_sc_hvl__buf_8_0/VGND" -176.44
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/A" 6.01147
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 275.882
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__buf_8_0/VPWR" -165.301
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" -9.25714
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" -9.25714
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_231_463#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -7.10543e-15
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 12.8
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" 265.63
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 9.62293
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/a_78_463#" 125.451
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/VGND" 0.01575
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/a_231_463#" 37.8014
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/A" -51.327
+cap "sky130_fd_sc_hvl__buf_8_0/VGND" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" -24.6048
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_217_207#" "sky130_fd_sc_hvl__buf_8_0/VGND" 1.42109e-14
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -1.42109e-13
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" 10.24
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" 13.8
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" 312.971
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/X" -2.84217e-14
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/X" 111.089
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/X" 5.68434e-13
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" 5.52
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" 6.9
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -49.975
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 11.4031
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 266.96
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" 11.04
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 383.444
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" 86.1851
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 13.8
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 3.56716
+cap "li_7870_6775#" "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" -881.083
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -165.647
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" 0.08775
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" -5.90498
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "sky130_fd_sc_hvl__buf_8_0/VNB" -22.2014
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" -9.25714
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" 161.262
+cap "li_7870_6775#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 275.882
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" 17.9602
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -176.44
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 5.315
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 265.63
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_0/VPWR" -105.28
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 162.371
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" -172.245
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" -168.69
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_0/VNB" 11.9662
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/A" 195.921
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/VNB" 236.342
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__schmittbuf_1_0/A" -3.13023
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" -18.5143
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/X" 4.54747e-13
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -430.46
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 1607.32
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/X" 140.629
+cap "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 179.082
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" 10.1329
+cap "sky130_fd_sc_hvl__buf_8_0/X" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -25.5049
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -22.4858
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" 1.6439
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" -16.6662
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -382.483
+cap "sky130_fd_sc_hvl__buf_8_0/X" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 70.7926
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 38.715
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -328.82
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 3.24
+cap "sky130_fd_sc_hvl__buf_8_0/X" "sky130_fd_sc_hvl__buf_8_0/VPWR" 94.4332
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 1.25725
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" -176.44
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/X" -4.37464
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" -165.098
+cap "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/VPWR" 9.91296
+cap "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -73.3
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -346.662
+cap "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" -76.685
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" 94.5846
+cap "vss" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_80_n200#" 50.6485
+cap "vdd3v3" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_80_n200#" 618.689
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "vdd3v3" 20
+cap "vss" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#" 44.4396
+cap "vdd3v3" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#" 414.614
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" 338.902
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" 10.0331
+cap "vss" "vdd3v3" -71.4685
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" 3.37952
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" -4.08078
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#" 47.1265
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_80_n200#" 50.0237
+cap "vdd3v3" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" 60
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" 8.21128
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" 13.3039
+cap "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_80_n200#" 40.7087
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" 373.722
+cap "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" 157.593
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" 109.246
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" -10
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "m1_185_6573#" 51.879
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n247_n200#" 71.6655
+cap "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n625_n297#" 70.1803
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "vss" -379.118
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n625_n297#" -3117.86
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n247_n200#" "vss" 10.5624
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n247_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n625_n297#" 449.146
+cap "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" 25.6193
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n625_n297#" "vss" -762.24
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" 1.69486
+cap "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" 3.08786
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" 277.089
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 59.5742
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" 30.2912
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" -79.5505
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 141.949
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" 121.436
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" 0.121294
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" 3.8312
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" 217.781
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 33.0826
+cap "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 142.482
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 0.0355032
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" 2.8819
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" -145.342
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" -33.5647
+cap "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" -766.513
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" 16.9374
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 29.3354
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" 47.2921
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" 25.6095
+cap "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" -286.892
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" 135.614
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" 264.539
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" 40.8918
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" 10.695
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" "vss" -226.035
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/w_n992_n497#" "m1_2756_6573#" -89.7481
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/w_n992_n497#" "vss" -303.902
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/w_n992_n497#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" 409.809
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" "vss" 52.1706
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_298_n200#" "vss" 4.0968
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" "vss" -303.372
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" "vss" 40.8918
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" "vss" 8.7515
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#" "vss" -632.599
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_298_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" 0.573248
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" 53.5822
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" 277.276
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_298_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" 47.8787
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" 128.808
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" 120.945
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#" 24.3186
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_298_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#" -74.882
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" 202.364
+cap "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#" -3587.86
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#" 106.763
+cap "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" -30.3488
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_64_207#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" 14.9548
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_64_207#" "sky130_fd_sc_hvl__buf_8_1/VNB" 27.7382
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/VNB" 19.7764
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/VNB" 7.10543e-15
+cap "sky130_fd_sc_hvl__buf_8_1/VPWR" "sky130_fd_sc_hvl__buf_8_0/VPWR" 3.27114
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" 17.9123
+cap "sky130_fd_sc_hvl__buf_8_1/VPWR" "sky130_fd_sc_hvl__buf_8_1/A" 16.008
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_64_207#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 12.2571
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_0/VPWR" 5.00361
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_231_463#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" 90.1302
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" -72.9824
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_231_463#" "sky130_fd_sc_hvl__buf_8_1/VNB" 31.2321
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/A" 75.5765
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_1/VNB" 482.135
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -8.085
+cap "sky130_fd_sc_hvl__buf_8_1/VNB" "sky130_fd_sc_hvl__buf_8_1/A" 43.9546
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_1/VPWR" 184.239
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_78_463#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" 4.9422
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_231_463#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -5.68434e-14
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_1/A" 1.42109e-14
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_1/VNB" 79.4487
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/A" 1.32889
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_1/a_45_443#" 1.15
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" 0.861744
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 9.76178
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/VPWR" 64.4936
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 61.5313
+cap "sky130_fd_sc_hvl__buf_8_1/VPWR" "sky130_fd_sc_hvl__buf_8_1/VNB" -2.84217e-14
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_1/A" 186.447
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__inv_8_0/Y" -2.84217e-14
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -50.831
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_1/VPWR" 39.7082
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_1/VPWR" 116.467
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 79.8378
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_0/VPWR" -45.7006
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/A" 28.5955
+cap "sky130_fd_sc_hvl__buf_8_0/X" "sky130_fd_sc_hvl__buf_8_1/VNB" 13.2805
+cap "sky130_fd_sc_hvl__inv_8_0/Y" "sky130_fd_sc_hvl__buf_8_1/VNB" 1.77636e-15
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/VNB" 115.809
+cap "sky130_fd_sc_hvl__inv_8_0/Y" "sky130_fd_sc_hvl__buf_8_0/VPWR" 16.4116
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__buf_8_1/VNB" 15.1385
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/A" 4.73873
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_1/a_45_443#" 1.51316
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_1/VNB" 137.591
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_1/VNB" 140.289
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/VPWR" -78.2706
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__inv_8_0/Y" 86.4916
+cap "sky130_fd_sc_hvl__inv_8_0/Y" "sky130_fd_sc_hvl__buf_8_1/VNB" 38.4789
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_1/X" 443.566
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/a_45_443#" -30.3285
+cap "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" "sky130_fd_sc_hvl__buf_8_0/VPWR" 183.25
+cap "li_7870_6775#" "sky130_fd_sc_hvl__schmittbuf_1_0/a_117_181#" -68.0585
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_1/VNB" 968.176
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 61.8263
+cap "sky130_fd_sc_hvl__buf_8_1/a_45_443#" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" 3.26842
+cap "sky130_fd_sc_hvl__buf_8_0/A" "sky130_fd_sc_hvl__buf_8_1/a_45_443#" 392.315
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__inv_8_0/Y" 10.7295
+cap "sky130_fd_sc_hvl__inv_8_0/Y" "sky130_fd_sc_hvl__buf_8_1/VPWR" 84.0364
+cap "sky130_fd_sc_hvl__buf_8_0/X" "sky130_fd_sc_hvl__buf_8_0/VPWR" 2.34479e-13
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_1/VPWR" 469.333
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/X" 44.1304
+cap "sky130_fd_sc_hvl__buf_8_1/X" "sky130_fd_sc_hvl__buf_8_0/VPWR" 24.7798
+cap "porb_l" "vdd1v8" 166.68
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/X" 40.8084
+cap "sky130_fd_sc_hvl__inv_8_0/Y" "vdd1v8" 213.545
+cap "porb_l" "sky130_fd_sc_hvl__inv_8_0/A" 94.4158
+cap "sky130_fd_sc_hvl__buf_8_0/a_45_443#" "sky130_fd_sc_hvl__inv_8_0/A" 9.92632
+cap "porb_l" "sky130_fd_sc_hvl__inv_8_0/Y" 312.292
+cap "sky130_fd_sc_hvl__inv_8_0/Y" "sky130_fd_sc_hvl__inv_8_0/A" 26.8102
+cap "sky130_fd_sc_hvl__inv_8_0/VNB" "sky130_fd_sc_hvl__buf_8_0/X" 19.7868
+cap "li_7870_6775#" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" -54.923
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/a_45_443#" -295.38
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__inv_8_0/Y" 97.2577
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "li_7870_6775#" -280.909
+cap "sky130_fd_sc_hvl__inv_8_0/VNB" "sky130_fd_sc_hvl__inv_8_0/A" 184.88
+cap "sky130_fd_sc_hvl__inv_8_0/VNB" "sky130_fd_sc_hvl__inv_8_0/Y" 147.288
+cap "sky130_fd_sc_hvl__inv_8_0/VNB" "li_7870_6775#" 2.4869e-14
+cap "sky130_fd_sc_hvl__buf_8_0/X" "li_7870_6775#" 34.8754
+cap "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__inv_8_0/VNB" 667.424
+cap "vdd1v8" "sky130_fd_sc_hvl__inv_8_0/A" -823.728
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_625_n200#" -38.3037 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12627 -9326 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_625_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_189_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_189_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_683_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_683_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_465_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_465_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_247_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_247_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n247_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n247_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n683_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n683_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_29_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_29_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n189_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n189_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n407_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n407_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n625_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n625_n297#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n843_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n843_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_80_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_80_n200#" "m1_502_7653#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_734_n200#" 129.658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91002 -8670 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_734_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_298_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_298_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n138_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_574_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_574_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_356_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_138_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_138_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n80_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n298_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n298_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_80_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n516_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n516_n297#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n574_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n574_n200#" "m1_3966_7645#"
+merge "m1_3966_7645#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n734_n297#" "m1_4283_8081#"
+merge "sky130_fd_sc_hvl__buf_8_0/X" "porb_h" -216.077 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1356 -414 0 0 -55581 0 -122177 -353 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n138_n200#" -495.223 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 122034 -5926 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/a_n80_n297#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_80_n200#" "m1_2756_6573#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_80_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n80_n288#" -2110.71 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -76365 -8576 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_516_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_516_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_574_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_574_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_356_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_356_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_80_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_80_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n356_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n356_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n792_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_138_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_138_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n80_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n80_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n298_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n298_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n516_n288#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n734_n288#" "m1_721_6815#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" -262.922 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -32035 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_n2932#" "li_8339_165#"
+merge "sky130_fd_sc_hvl__inv_8_0/VGND" "sky130_fd_sc_hvl__buf_8_1/VGND" -57403.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -523034 -10580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 623613 -45332 -22372874 -169333 629978 0 237505 -2214 416224 -22772 270492 -2404 0 0
+merge "sky130_fd_sc_hvl__buf_8_1/VGND" "sky130_fd_sc_hvl__fill_4_0/VGND"
+merge "sky130_fd_sc_hvl__fill_4_0/VGND" "sky130_fd_sc_hvl__fill_4_0/VNB"
+merge "sky130_fd_sc_hvl__fill_4_0/VNB" "sky130_fd_sc_hvl__inv_8_0/VNB"
+merge "sky130_fd_sc_hvl__inv_8_0/VNB" "sky130_fd_sc_hvl__schmittbuf_1_0/VGND"
+merge "sky130_fd_sc_hvl__schmittbuf_1_0/VGND" "sky130_fd_sc_hvl__schmittbuf_1_0/VNB"
+merge "sky130_fd_sc_hvl__schmittbuf_1_0/VNB" "sky130_fd_sc_hvl__buf_8_0/VGND"
+merge "sky130_fd_sc_hvl__buf_8_0/VGND" "sky130_fd_sc_hvl__buf_8_0/VNB"
+merge "sky130_fd_sc_hvl__buf_8_0/VNB" "sky130_fd_sc_hvl__buf_8_1/VNB"
+merge "sky130_fd_sc_hvl__buf_8_1/VNB" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/VSUBS" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#"
+merge "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/c2_n3079_n3000#" "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/VSUBS" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/VSUBS" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/VSUBS" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n138_n200#" "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0/a_n272_n422#" "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/VSUBS" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/VSUBS" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_734_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_734_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_298_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_298_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n138_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n574_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n574_n200#" "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n926_n422#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0/a_n926_n422#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n138_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n138_n200#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n272_n422#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/VSUBS" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/VSUBS"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/VSUBS" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4894_2500#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4894_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_2500#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_2500#" "li_10656_5813#"
+merge "li_10656_5813#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5280_2500#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5280_2500#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/VSUBS"
+merge "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/VSUBS" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_n2932#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_5142_n2932#" "li_10655_165#"
+merge "li_10655_165#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/VSUBS"
+merge "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/VSUBS" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#"
+merge "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/m3_n3136_n3100#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5280_n2932#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5280_n2932#" "a_7438_7387#"
+merge "a_7438_7387#" "vss"
+merge "vss" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n5410_n3062#" "li_51_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3350_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_2500#" -233.447 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 717 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_2500#" "li_1778_5813#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n80_n297#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n138_n200#" -480.217 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -113478 -5712 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/a_n80_n297#" "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_80_n200#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_80_n200#" "m1_185_6573#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" -6530.52 0 0 0 0 -5410931 -41238 0 0 0 0 0 0 1861553 -19804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1023980 -37080 857468 -32962 -94101 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_516_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_80_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n356_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n356_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n792_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/a_n792_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n138_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_n138_n200#" "m1_4109_7872#"
+merge "m1_4109_7872#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_843_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_407_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_407_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n29_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n29_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n465_n200#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n901_n200#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/a_n901_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/w_n338_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/w_n338_n497#" "m1_627_7892#"
+merge "m1_627_7892#" "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/w_n338_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/w_n338_n497#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/w_n338_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1/w_n338_n497#" "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/w_n992_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0/w_n992_n497#" "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/w_n338_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/w_n338_n497#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/w_n338_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/w_n338_n497#" "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/w_n1101_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0/w_n1101_n497#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/w_n338_n497#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3/w_n338_n497#" "w_70_7344#"
+merge "w_70_7344#" "sky130_fd_sc_hvl__fill_4_0/VPWR"
+merge "sky130_fd_sc_hvl__fill_4_0/VPWR" "sky130_fd_sc_hvl__fill_4_0/VPB"
+merge "sky130_fd_sc_hvl__fill_4_0/VPB" "sky130_fd_sc_hvl__schmittbuf_1_0/VPWR"
+merge "sky130_fd_sc_hvl__schmittbuf_1_0/VPWR" "sky130_fd_sc_hvl__schmittbuf_1_0/VPB"
+merge "sky130_fd_sc_hvl__schmittbuf_1_0/VPB" "sky130_fd_sc_hvl__buf_8_0/VPWR"
+merge "sky130_fd_sc_hvl__buf_8_0/VPWR" "sky130_fd_sc_hvl__buf_8_0/VPB"
+merge "sky130_fd_sc_hvl__buf_8_0/VPB" "w_7401_6799#"
+merge "w_7401_6799#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4756_2500#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4756_2500#" "vdd3v3"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2192_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2578_n2932#" -275.054 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -45150 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2578_n2932#" "li_2935_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4122_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4508_2500#" -219.107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -624 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4508_2500#" "li_1006_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_510_n2932#" -260.934 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29885 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_510_n2932#" "li_6023_165#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0/a_80_n200#" "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" -239.251 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12092 -1100 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_n138_n200#" "m1_6249_7690#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" -234.496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -417 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_2500#" "li_9498_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" -260.934 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29885 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_n2932#" "li_6795_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n262_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" -233.533 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 624 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_2500#" "li_4866_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n262_n2932#" -266.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -36335 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n262_n2932#" "li_5251_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1806_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2192_2500#" -234.496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -417 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2192_2500#" "li_3322_5813#"
+merge "sky130_fd_sc_hvl__buf_8_1/X" "porb_l" -1198.77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9476 -504 -25688 -1058 -12160 -464 -83471 -2856 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0/a_n138_n200#" "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_80_n200#" -50.1052 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -754 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0/a_80_n200#" "m1_2993_7658#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3350_n2932#" -274.457 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44505 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3350_n2932#" "li_2163_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3984_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_n2932#" -274.457 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44505 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_n2932#" "li_9111_165#"
+merge "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2/a_80_n200#" "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" -3341.96 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2324 0 80000 -848 0 0 0 0 -6978171 -25768 165561 -2538 0 0
+merge "sky130_fd_pr__cap_mim_m3_2_W5U4AW_0/m4_n3179_n3100#" "sky130_fd_sc_hvl__schmittbuf_1_0/A"
+merge "sky130_fd_sc_hvl__schmittbuf_1_0/A" "li_7870_6775#"
+merge "li_7870_6775#" "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#"
+merge "sky130_fd_pr__cap_mim_m3_1_WRT4AW_0/c1_n3036_n3000#" "m4_4101_51#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1806_n2932#" -274.457 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44505 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1806_n2932#" "li_3707_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n3736_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4122_n2932#" -273.264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -43215 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4122_n2932#" "li_1391_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_n2932#" -260.934 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29885 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_n2932#" "li_7567_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1282_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" -234.687 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -624 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_896_2500#" "li_6410_5813#"
+merge "sky130_fd_sc_hvl__inv_8_0/VPWR" "sky130_fd_sc_hvl__inv_8_0/VPB" 4707.47 0 0 0 0 106600 -1304 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 -354068 -13920 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hvl__inv_8_0/VPB" "sky130_fd_sc_hvl__buf_8_1/VPWR"
+merge "sky130_fd_sc_hvl__buf_8_1/VPWR" "sky130_fd_sc_hvl__buf_8_1/VPB"
+merge "sky130_fd_sc_hvl__buf_8_1/VPB" "vdd1v8"
+merge "sky130_fd_sc_hvl__inv_8_0/A" "sky130_fd_sc_hvl__buf_8_1/A" -1166.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22391 -2290 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hvl__buf_8_1/A" "sky130_fd_sc_hvl__schmittbuf_1_0/X"
+merge "sky130_fd_sc_hvl__schmittbuf_1_0/X" "sky130_fd_sc_hvl__buf_8_0/A"
+merge "sky130_fd_sc_hvl__buf_8_0/A" "li_7604_7754#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n648_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1034_n2932#" -275.054 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -45150 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1034_n2932#" "li_4479_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2826_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" -208.447 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -624 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2440_2500#" "li_7954_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3598_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" -234.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -627 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_3212_2500#" "li_8726_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_2054_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" -234.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -627 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_1668_2500#" "li_7182_5813#"
+merge "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1/a_n80_n288#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2578_2500#" -486.706 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31414 -1142 -4212 -372 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2578_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n2964_2500#" "li_2550_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4756_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" -275.054 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -45150 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_4370_n2932#" "li_9883_165#"
+merge "sky130_fd_sc_hvl__inv_8_0/Y" "por_l" -161.603 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68012 -460 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4508_n2932#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4894_n2932#" -182.212 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55219 -1138 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n4894_n2932#" "li_619_165#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_510_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" -234.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -627 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_124_2500#" "li_5638_5813#"
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1034_2500#" "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" -234.496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -417 -1142 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/a_n1420_2500#" "li_4094_5813#"
diff --git a/mag/example_por.mag b/mag/unused/example_por.mag
similarity index 100%
rename from mag/example_por.mag
rename to mag/unused/example_por.mag
diff --git a/mag/unused/sky130_fd_pr__cap_mim_m3_1_WRT4AW.ext b/mag/unused/sky130_fd_pr__cap_mim_m3_1_WRT4AW.ext
new file mode 100644
index 0000000..fd0ff98
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__cap_mim_m3_1_WRT4AW.ext
@@ -0,0 +1,12 @@
+timestamp 1606502073
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l
+node "c1_n3036_n3000#" 0 0 -3036 -3000 mim 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3517668 13032 0 0 0 0
+node "m3_n3136_n3100#" 3 16779.4 -3136 -3100 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38886400 24944 592896 12544 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "c1_n3036_n3000#" "m3_n3136_n3100#" 15588
+device csubckt sky130_fd_pr__cap_mim_m3_1 -3036 -3000 -3035 -2999 w=6000 l=6000 "None" "c1_n3036_n3000#" 13024 0 "m3_n3136_n3100#" 138 0
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag b/mag/unused/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
similarity index 100%
rename from mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
rename to mag/unused/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
diff --git a/mag/unused/sky130_fd_pr__cap_mim_m3_2_W5U4AW.ext b/mag/unused/sky130_fd_pr__cap_mim_m3_2_W5U4AW.ext
new file mode 100644
index 0000000..e278c96
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__cap_mim_m3_2_W5U4AW.ext
@@ -0,0 +1,12 @@
+timestamp 1606502073
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_2 w=w l=l
+node "c2_n3079_n3000#" 0 0 -3079 -3000 mim2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32083968 22688 0 0
+node "m4_n3179_n3100#" 1 13885.5 -3179 -3100 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39419600 25116 1984640 13044 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "c2_n3079_n3000#" "m4_n3179_n3100#" 63958.3
+device csubckt sky130_fd_pr__cap_mim_m3_2 -3079 -3000 -3078 -2999 w=6000 l=6000 "None" "c2_n3079_n3000#" 22496 0 "m4_n3179_n3100#" 138 0
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag b/mag/unused/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
similarity index 100%
rename from mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
rename to mag/unused/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
diff --git a/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.ext b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.ext
new file mode 100644
index 0000000..f5a4a4b
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.ext
@@ -0,0 +1,14 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_80_n200#" 934 238.006 80 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 934 301.395 -138 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n288#" 318 521.957 -80 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+substrate "a_n272_n422#" 0 0 -272 -422 mvppd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 147552 5088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86496 5088 16652 816 0 0 0 0 0 0 0 0 0 0
+cap "a_80_n200#" "a_n138_n200#" 177.825
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "a_n272_n422#" "a_n80_n288#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
rename to mag/unused/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
diff --git a/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.ext b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.ext
new file mode 100644
index 0000000..6649a26
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.ext
@@ -0,0 +1,55 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_734_n200#" 933 165.158 734 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_516_n200#" 933 72.8577 516 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_298_n200#" 933 30.5181 298 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_80_n200#" 933 30.5181 80 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 933 30.5181 -138 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n356_n200#" 933 30.5181 -356 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n574_n200#" 933 98.446 -574 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n792_n200#" 933 254.135 -792 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_574_n288#" 318 492.212 574 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_356_n288#" 318 483.007 356 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_138_n288#" 318 476.842 138 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n288#" 318 476.842 -80 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n298_n288#" 318 476.842 -298 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n516_n288#" 318 493.698 -516 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n734_n288#" 318 519.087 -734 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+substrate "a_n926_n422#" 0 0 -926 -422 mvppd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 299280 10320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 175440 10320 25300 1192 0 0 0 0 0 0 0 0 0 0
+cap "a_n298_n288#" "a_n734_n288#" 37.3746
+cap "a_298_n200#" "a_80_n200#" 73.1739
+cap "a_734_n200#" "a_516_n200#" 73.1739
+cap "a_298_n200#" "a_n138_n200#" 20.0769
+cap "a_80_n200#" "a_n138_n200#" 73.1739
+cap "a_n298_n288#" "a_n516_n288#" 171.21
+cap "a_n356_n200#" "a_80_n200#" 20.0769
+cap "a_n356_n200#" "a_n138_n200#" 73.1739
+cap "a_n792_n200#" "a_n356_n200#" 20.0769
+cap "a_n516_n288#" "a_n80_n288#" 37.3746
+cap "a_298_n200#" "a_516_n200#" 73.1739
+cap "a_n574_n200#" "a_n138_n200#" 20.0769
+cap "a_n574_n200#" "a_n356_n200#" 73.1739
+cap "a_80_n200#" "a_516_n200#" 20.0769
+cap "a_356_n288#" "a_n80_n288#" 37.3746
+cap "a_n298_n288#" "a_n80_n288#" 171.21
+cap "a_n574_n200#" "a_n792_n200#" 73.1739
+cap "a_356_n288#" "a_138_n288#" 171.21
+cap "a_n298_n288#" "a_138_n288#" 37.3746
+cap "a_356_n288#" "a_574_n288#" 171.21
+cap "a_138_n288#" "a_n80_n288#" 171.21
+cap "a_734_n200#" "a_298_n200#" 20.0769
+cap "a_574_n288#" "a_138_n288#" 37.3746
+cap "a_n734_n288#" "a_n516_n288#" 171.21
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 574 -200 575 -199 l=160 w=400 "a_n926_n422#" "a_574_n288#" 320 0 "a_516_n200#" 400 0 "a_734_n200#" 400 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 356 -200 357 -199 l=160 w=400 "a_n926_n422#" "a_356_n288#" 320 0 "a_298_n200#" 400 0 "a_516_n200#" 400 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 138 -200 139 -199 l=160 w=400 "a_n926_n422#" "a_138_n288#" 320 0 "a_80_n200#" 400 0 "a_298_n200#" 400 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "a_n926_n422#" "a_n80_n288#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 -298 -200 -297 -199 l=160 w=400 "a_n926_n422#" "a_n298_n288#" 320 0 "a_n356_n200#" 400 0 "a_n138_n200#" 400 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 -516 -200 -515 -199 l=160 w=400 "a_n926_n422#" "a_n516_n288#" 320 0 "a_n574_n200#" 400 0 "a_n356_n200#" 400 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 -734 -200 -733 -199 l=160 w=400 "a_n926_n422#" "a_n734_n288#" 320 0 "a_n792_n200#" 400 0 "a_n574_n200#" 400 0
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
rename to mag/unused/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
diff --git a/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.ext b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.ext
new file mode 100644
index 0000000..6b0a6b9
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.ext
@@ -0,0 +1,14 @@
+timestamp 1605994897
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_80_n200#" 934 212.418 80 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 934 212.418 -138 -200 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n288#" 318 507.582 -80 -288 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92160 1472 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+substrate "a_n272_n422#" 0 0 -272 -422 mvppd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 147552 5088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86496 5088 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_80_n200#" "a_n138_n200#" 177.825
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "a_n272_n422#" "a_n80_n288#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/unused/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
rename to mag/unused/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
diff --git a/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.ext b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.ext
new file mode 100644
index 0000000..e721afe
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.ext
@@ -0,0 +1,18 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_80_n200#" 1465 0 80 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 1465 0 -138 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n297#" 323 82.256 -80 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "w_n338_n497#" 8242 2015.83 -338 -497 nw 0 0 0 0 671944 3340 0 0 0 0 0 0 149640 5160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87720 5160 17756 864 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_80_n200#" "w_n338_n497#" 223.333
+cap "a_n138_n200#" "w_n338_n497#" 223.333
+cap "a_n138_n200#" "a_80_n200#" 177.825
+cap "a_n80_n297#" "w_n338_n497#" 517.206
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "w_n338_n497#" "a_n80_n297#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
rename to mag/unused/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
diff --git a/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.ext b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.ext
new file mode 100644
index 0000000..14452c0
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.ext
@@ -0,0 +1,71 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_734_n200#" 1464 0 734 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_516_n200#" 1464 0 516 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_298_n200#" 1464 0 298 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_80_n200#" 1464 0 80 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 1464 0 -138 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n356_n200#" 1464 0 -356 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n574_n200#" 1464 0 -574 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n792_n200#" 1464 0 -792 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_574_n297#" 323 82.256 574 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_356_n297#" 323 82.256 356 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_138_n297#" 323 82.256 138 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n297#" 323 82.256 -80 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n298_n297#" 323 82.256 -298 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n516_n297#" 323 82.256 -516 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n734_n297#" 323 82.256 -734 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "w_n992_n497#" 15222 5916.29 -992 -497 nw 0 0 0 0 1972096 5956 0 0 0 0 0 0 301368 10392 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 176664 10392 91034 4142 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n992_n497#" "a_n138_n200#" 35.2044
+cap "a_n734_n297#" "a_n298_n297#" 38.8746
+cap "w_n992_n497#" "a_n734_n297#" 516.211
+cap "a_734_n200#" "a_298_n200#" 20.0769
+cap "a_n356_n200#" "w_n992_n497#" 40.4306
+cap "a_n80_n297#" "a_n298_n297#" 178.348
+cap "w_n992_n497#" "a_n80_n297#" 486.466
+cap "a_n356_n200#" "a_n792_n200#" 20.0769
+cap "a_298_n200#" "a_80_n200#" 73.1739
+cap "w_n992_n497#" "a_574_n297#" 501.836
+cap "w_n992_n497#" "a_n574_n200#" 77.5441
+cap "a_138_n297#" "a_n298_n297#" 38.8746
+cap "a_298_n200#" "a_516_n200#" 73.1739
+cap "a_n356_n200#" "a_n138_n200#" 73.1739
+cap "a_138_n297#" "w_n992_n497#" 486.466
+cap "a_n792_n200#" "a_n574_n200#" 73.1739
+cap "w_n992_n497#" "a_298_n200#" 35.2044
+cap "w_n992_n497#" "a_356_n297#" 492.631
+cap "a_n516_n297#" "a_n298_n297#" 178.348
+cap "a_734_n200#" "a_516_n200#" 73.1739
+cap "w_n992_n497#" "a_n516_n297#" 498.349
+cap "w_n992_n497#" "a_734_n200#" 169.844
+cap "a_516_n200#" "a_80_n200#" 20.0769
+cap "w_n992_n497#" "a_80_n200#" 40.4306
+cap "a_n574_n200#" "a_n138_n200#" 20.0769
+cap "a_298_n200#" "a_n138_n200#" 20.0769
+cap "a_n356_n200#" "a_n574_n200#" 73.1739
+cap "a_138_n297#" "a_n80_n297#" 178.348
+cap "a_n80_n297#" "a_356_n297#" 38.8746
+cap "a_138_n297#" "a_574_n297#" 38.8746
+cap "a_356_n297#" "a_574_n297#" 178.348
+cap "a_n516_n297#" "a_n734_n297#" 178.348
+cap "w_n992_n497#" "a_516_n200#" 82.7702
+cap "w_n992_n497#" "a_n298_n297#" 486.466
+cap "a_n516_n297#" "a_n80_n297#" 38.8746
+cap "a_n138_n200#" "a_80_n200#" 73.1739
+cap "w_n992_n497#" "a_n792_n200#" 255.355
+cap "a_n356_n200#" "a_80_n200#" 20.0769
+cap "a_138_n297#" "a_356_n297#" 178.348
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 574 -200 575 -199 l=160 w=400 "w_n992_n497#" "a_574_n297#" 320 0 "a_516_n200#" 400 0 "a_734_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 356 -200 357 -199 l=160 w=400 "w_n992_n497#" "a_356_n297#" 320 0 "a_298_n200#" 400 0 "a_516_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 138 -200 139 -199 l=160 w=400 "w_n992_n497#" "a_138_n297#" 320 0 "a_80_n200#" 400 0 "a_298_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "w_n992_n497#" "a_n80_n297#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -298 -200 -297 -199 l=160 w=400 "w_n992_n497#" "a_n298_n297#" 320 0 "a_n356_n200#" 400 0 "a_n138_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -516 -200 -515 -199 l=160 w=400 "w_n992_n497#" "a_n516_n297#" 320 0 "a_n574_n200#" 400 0 "a_n356_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -734 -200 -733 -199 l=160 w=400 "w_n992_n497#" "a_n734_n297#" 320 0 "a_n792_n200#" 400 0 "a_n574_n200#" 400 0
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
rename to mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
diff --git a/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.ext b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.ext
new file mode 100644
index 0000000..1b58688
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.ext
@@ -0,0 +1,18 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_80_n200#" 1465 0 80 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 1465 0 -138 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n297#" 323 82.256 -80 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "w_n338_n497#" 8244 2015.83 -338 -497 nw 0 0 0 0 671944 3340 0 0 0 0 0 0 149640 5160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87720 5160 36570 1774 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n338_n497#" "a_n80_n297#" 531.581
+cap "a_n138_n200#" "a_80_n200#" 177.825
+cap "w_n338_n497#" "a_n138_n200#" 331.742
+cap "w_n338_n497#" "a_80_n200#" 254.51
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "w_n338_n497#" "a_n80_n297#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
rename to mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
diff --git a/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.ext b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.ext
new file mode 100644
index 0000000..9c89974
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.ext
@@ -0,0 +1,18 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_80_n200#" 1465 0 80 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n138_n200#" 1465 0 -138 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n80_n297#" 323 82.256 -80 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "w_n338_n497#" 8244 2015.83 -338 -497 nw 0 0 0 0 671944 3340 0 0 0 0 0 0 149640 5160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87720 5160 34822 1698 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_80_n200#" "w_n338_n497#" 248.921
+cap "a_n138_n200#" "w_n338_n497#" 312.311
+cap "a_n138_n200#" "a_80_n200#" 177.825
+cap "a_n80_n297#" "w_n338_n497#" 531.581
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -80 -200 -79 -199 l=160 w=400 "w_n338_n497#" "a_n80_n297#" 320 0 "a_n138_n200#" 400 0 "a_80_n200#" 400 0
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
rename to mag/unused/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
diff --git a/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.ext b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.ext
new file mode 100644
index 0000000..d36cda6
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.ext
@@ -0,0 +1,80 @@
+timestamp 1606063140
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+node "a_843_n200#" 1464 0 843 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_625_n200#" 1464 0 625 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_407_n200#" 1464 0 407 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_189_n200#" 1464 0 189 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n29_n200#" 1464 0 -29 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n247_n200#" 1464 0 -247 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n465_n200#" 1464 0 -465 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n683_n200#" 1464 0 -683 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_n901_n200#" 1464 0 -901 -200 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23200 916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 8004 440 0 0 0 0 0 0 0 0 0 0
+node "a_683_n297#" 323 82.256 683 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_465_n297#" 323 82.256 465 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_247_n297#" 323 82.256 247 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_29_n297#" 323 82.256 29 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n189_n297#" 323 82.256 -189 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n407_n297#" 323 82.256 -407 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n625_n297#" 323 82.256 -625 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "a_n843_n297#" 323 82.256 -843 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95040 1508 0 0 10880 776 13984 792 0 0 0 0 0 0 0 0 0 0
+node "w_n1101_n497#" 16609 6566.36 -1101 -497 nw 0 0 0 0 2188788 6392 0 0 0 0 0 0 326656 11264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 191488 11264 101798 4610 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n189_n297#" "a_247_n297#" 38.8746
+cap "a_625_n200#" "a_843_n200#" 73.1739
+cap "a_465_n297#" "a_247_n297#" 178.348
+cap "a_n247_n200#" "a_n29_n200#" 73.1739
+cap "w_n1101_n497#" "a_n901_n200#" 264.048
+cap "a_n189_n297#" "w_n1101_n497#" 486.466
+cap "a_n625_n297#" "a_n407_n297#" 178.348
+cap "w_n1101_n497#" "a_465_n297#" 492.631
+cap "a_189_n200#" "a_n247_n200#" 20.0769
+cap "a_n683_n200#" "a_n901_n200#" 73.1739
+cap "w_n1101_n497#" "a_n29_n200#" 40.4306
+cap "a_n189_n297#" "a_29_n297#" 178.348
+cap "a_465_n297#" "a_29_n297#" 38.8746
+cap "a_465_n297#" "a_683_n297#" 178.348
+cap "a_189_n200#" "w_n1101_n497#" 35.2044
+cap "a_625_n200#" "w_n1101_n497#" 77.5441
+cap "a_407_n200#" "a_n29_n200#" 20.0769
+cap "a_n625_n297#" "a_n843_n297#" 178.348
+cap "a_189_n200#" "a_407_n200#" 73.1739
+cap "a_n625_n297#" "w_n1101_n497#" 498.349
+cap "a_625_n200#" "a_407_n200#" 73.1739
+cap "a_n843_n297#" "a_n407_n297#" 38.8746
+cap "w_n1101_n497#" "a_n407_n297#" 486.466
+cap "a_n247_n200#" "a_n465_n200#" 73.1739
+cap "a_843_n200#" "w_n1101_n497#" 175.071
+cap "w_n1101_n497#" "a_n465_n200#" 40.4306
+cap "a_n407_n297#" "a_29_n297#" 38.8746
+cap "a_189_n200#" "a_n29_n200#" 73.1739
+cap "a_n683_n200#" "a_n465_n200#" 73.1739
+cap "a_407_n200#" "a_843_n200#" 20.0769
+cap "a_n625_n297#" "a_n189_n297#" 38.8746
+cap "a_n247_n200#" "w_n1101_n497#" 35.2044
+cap "w_n1101_n497#" "a_247_n297#" 486.466
+cap "a_189_n200#" "a_625_n200#" 20.0769
+cap "a_n843_n297#" "w_n1101_n497#" 516.211
+cap "a_n247_n200#" "a_n683_n200#" 20.0769
+cap "a_n189_n297#" "a_n407_n297#" 178.348
+cap "a_683_n297#" "a_247_n297#" 38.8746
+cap "a_29_n297#" "a_247_n297#" 178.348
+cap "a_n683_n200#" "w_n1101_n497#" 77.9852
+cap "a_n465_n200#" "a_n901_n200#" 20.0769
+cap "w_n1101_n497#" "a_29_n297#" 486.466
+cap "w_n1101_n497#" "a_683_n297#" 501.836
+cap "a_407_n200#" "w_n1101_n497#" 40.4306
+cap "a_n465_n200#" "a_n29_n200#" 20.0769
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 683 -200 684 -199 l=160 w=400 "w_n1101_n497#" "a_683_n297#" 320 0 "a_625_n200#" 400 0 "a_843_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 465 -200 466 -199 l=160 w=400 "w_n1101_n497#" "a_465_n297#" 320 0 "a_407_n200#" 400 0 "a_625_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 247 -200 248 -199 l=160 w=400 "w_n1101_n497#" "a_247_n297#" 320 0 "a_189_n200#" 400 0 "a_407_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 29 -200 30 -199 l=160 w=400 "w_n1101_n497#" "a_29_n297#" 320 0 "a_n29_n200#" 400 0 "a_189_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -189 -200 -188 -199 l=160 w=400 "w_n1101_n497#" "a_n189_n297#" 320 0 "a_n247_n200#" 400 0 "a_n29_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -407 -200 -406 -199 l=160 w=400 "w_n1101_n497#" "a_n407_n297#" 320 0 "a_n465_n200#" 400 0 "a_n247_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -625 -200 -624 -199 l=160 w=400 "w_n1101_n497#" "a_n625_n297#" 320 0 "a_n683_n200#" 400 0 "a_n465_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 -843 -200 -842 -199 l=160 w=400 "w_n1101_n497#" "a_n843_n297#" 320 0 "a_n901_n200#" 400 0 "a_n683_n200#" 400 0
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/unused/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
rename to mag/unused/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
diff --git a/mag/unused/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.ext b/mag/unused/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.ext
new file mode 100644
index 0000000..42840d0
--- /dev/null
+++ b/mag/unused/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.ext
@@ -0,0 +1,179 @@
+timestamp 1606074388
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__res_xhigh_po l=l w=w
+parameters sky130_fd_pr__res_xhigh_po_5p73 l=l
+parameters sky130_fd_pr__res_xhigh_po_2p85 l=l
+parameters sky130_fd_pr__res_xhigh_po_1p41 l=l
+parameters sky130_fd_pr__res_xhigh_po_0p69 l=l
+parameters sky130_fd_pr__res_xhigh_po_0p35 l=l
+node "a_5142_n2932#" 107 788.161 5142 -2932 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119232 2280 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_5142_n2500#" 72464 0 5142 -2500 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 690000 10276 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_5142_2500#" 107 788.161 5142 2500 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119232 2280 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4756_n2932#" 107 565.411 4756 -2932 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119232 2280 0 0 0 0 0 0 0 0 0 0 0 0
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+node "a_4756_2500#" 107 565.411 4756 2500 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119232 2280 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4370_n2932#" 107 565.411 4370 -2932 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119232 2280 0 0 0 0 0 0 0 0 0 0 0 0
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+cap "a_4756_2500#" "a_4370_2500#" 114.968
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+cap "a_n1420_n2932#" "a_n1034_n2932#" 114.968
+cap "a_n3736_n2932#" "a_n3350_n2932#" 114.968
+cap "a_3984_2500#" "a_3598_2500#" 114.968
+cap "a_3984_n2932#" "a_4370_n2932#" 114.968
+cap "a_2054_2500#" "a_1668_2500#" 114.968
+cap "a_n262_2500#" "a_124_2500#" 114.968
+cap "a_n1806_2500#" "a_n1420_2500#" 114.968
+cap "a_2826_n2932#" "a_3212_n2932#" 114.968
+cap "a_n4508_n2932#" "a_n4894_n2932#" 114.968
+cap "a_124_2500#" "a_510_2500#" 114.968
+cap "a_1668_n2932#" "a_2054_n2932#" 114.968
+cap "a_n4508_n2932#" "a_n4122_n2932#" 114.968
+cap "a_2440_n2932#" "a_2826_n2932#" 114.968
+cap "a_2826_2500#" "a_2440_2500#" 114.968
+cap "a_4370_2500#" "a_3984_2500#" 114.968
+cap "a_n1034_n2932#" "a_n648_n2932#" 114.968
+cap "a_1668_2500#" "a_1282_2500#" 114.968
+cap "a_510_n2932#" "a_896_n2932#" 114.968
+cap "a_n648_n2932#" "a_n262_n2932#" 114.968
+cap "a_n4894_2500#" "a_n5280_2500#" 114.968
+cap "a_n1806_2500#" "a_n2192_2500#" 114.968
+cap "a_3212_2500#" "a_3598_2500#" 114.968
+cap "a_n2192_n2932#" "a_n1806_n2932#" 114.968
+cap "a_1668_n2932#" "a_1282_n2932#" 114.968
+cap "a_510_n2932#" "a_124_n2932#" 114.968
+cap "a_n262_n2932#" "a_124_n2932#" 114.968
+cap "a_n2964_n2932#" "a_n2578_n2932#" 114.968
+cap "a_3212_2500#" "a_2826_2500#" 114.968
+cap "a_n648_2500#" "a_n1034_2500#" 114.968
+cap "a_3598_n2932#" "a_3212_n2932#" 114.968
+cap "a_n1034_2500#" "a_n1420_2500#" 114.968
+cap "a_n4508_2500#" "a_n4894_2500#" 114.968
+cap "a_2054_2500#" "a_2440_2500#" 114.968
+cap "a_5142_n2932#" "a_4756_n2932#" 114.968
+cap "a_896_n2932#" "a_1282_n2932#" 114.968
+cap "a_n4508_2500#" "a_n4122_2500#" 114.968
+cap "a_n3736_n2932#" "a_n4122_n2932#" 114.968
+cap "a_n2192_n2932#" "a_n2578_n2932#" 114.968
+cap "a_n2964_n2932#" "a_n3350_n2932#" 114.968
+cap "a_n4122_2500#" "a_n3736_2500#" 114.968
+cap "a_896_2500#" "a_510_2500#" 114.968
+cap "a_896_2500#" "a_1282_2500#" 114.968
+cap "a_4756_n2932#" "a_4370_n2932#" 114.968
+cap "a_n2578_2500#" "a_n2964_2500#" 114.968
+cap "a_n3350_2500#" "a_n3736_2500#" 114.968
+cap "a_n2578_2500#" "a_n2192_2500#" 114.968
+cap "a_n1420_n2932#" "a_n1806_n2932#" 114.968
+cap "a_3598_n2932#" "a_3984_n2932#" 114.968
+cap "a_4756_2500#" "a_5142_2500#" 114.968
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 5142 -2500 5143 -2499 l=5000 "a_n5410_n3062#" "a_5142_n2500#" 0 0 "a_5142_n2932#" 138 0 "a_5142_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 4756 -2500 4757 -2499 l=5000 "a_n5410_n3062#" "a_4756_n2500#" 0 0 "a_4756_n2932#" 138 0 "a_4756_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 4370 -2500 4371 -2499 l=5000 "a_n5410_n3062#" "a_4370_n2500#" 0 0 "a_4370_n2932#" 138 0 "a_4370_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 3984 -2500 3985 -2499 l=5000 "a_n5410_n3062#" "a_3984_n2500#" 0 0 "a_3984_n2932#" 138 0 "a_3984_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 3598 -2500 3599 -2499 l=5000 "a_n5410_n3062#" "a_3598_n2500#" 0 0 "a_3598_n2932#" 138 0 "a_3598_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 3212 -2500 3213 -2499 l=5000 "a_n5410_n3062#" "a_3212_n2500#" 0 0 "a_3212_n2932#" 138 0 "a_3212_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 2826 -2500 2827 -2499 l=5000 "a_n5410_n3062#" "a_2826_n2500#" 0 0 "a_2826_n2932#" 138 0 "a_2826_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 2440 -2500 2441 -2499 l=5000 "a_n5410_n3062#" "a_2440_n2500#" 0 0 "a_2440_n2932#" 138 0 "a_2440_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 2054 -2500 2055 -2499 l=5000 "a_n5410_n3062#" "a_2054_n2500#" 0 0 "a_2054_n2932#" 138 0 "a_2054_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 1668 -2500 1669 -2499 l=5000 "a_n5410_n3062#" "a_1668_n2500#" 0 0 "a_1668_n2932#" 138 0 "a_1668_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 1282 -2500 1283 -2499 l=5000 "a_n5410_n3062#" "a_1282_n2500#" 0 0 "a_1282_n2932#" 138 0 "a_1282_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 896 -2500 897 -2499 l=5000 "a_n5410_n3062#" "a_896_n2500#" 0 0 "a_896_n2932#" 138 0 "a_896_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 510 -2500 511 -2499 l=5000 "a_n5410_n3062#" "a_510_n2500#" 0 0 "a_510_n2932#" 138 0 "a_510_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 124 -2500 125 -2499 l=5000 "a_n5410_n3062#" "a_124_n2500#" 0 0 "a_124_n2932#" 138 0 "a_124_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -262 -2500 -261 -2499 l=5000 "a_n5410_n3062#" "a_n262_n2500#" 0 0 "a_n262_n2932#" 138 0 "a_n262_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -648 -2500 -647 -2499 l=5000 "a_n5410_n3062#" "a_n648_n2500#" 0 0 "a_n648_n2932#" 138 0 "a_n648_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -1034 -2500 -1033 -2499 l=5000 "a_n5410_n3062#" "a_n1034_n2500#" 0 0 "a_n1034_n2932#" 138 0 "a_n1034_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -1420 -2500 -1419 -2499 l=5000 "a_n5410_n3062#" "a_n1420_n2500#" 0 0 "a_n1420_n2932#" 138 0 "a_n1420_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -1806 -2500 -1805 -2499 l=5000 "a_n5410_n3062#" "a_n1806_n2500#" 0 0 "a_n1806_n2932#" 138 0 "a_n1806_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -2192 -2500 -2191 -2499 l=5000 "a_n5410_n3062#" "a_n2192_n2500#" 0 0 "a_n2192_n2932#" 138 0 "a_n2192_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -2578 -2500 -2577 -2499 l=5000 "a_n5410_n3062#" "a_n2578_n2500#" 0 0 "a_n2578_n2932#" 138 0 "a_n2578_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -2964 -2500 -2963 -2499 l=5000 "a_n5410_n3062#" "a_n2964_n2500#" 0 0 "a_n2964_n2932#" 138 0 "a_n2964_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -3350 -2500 -3349 -2499 l=5000 "a_n5410_n3062#" "a_n3350_n2500#" 0 0 "a_n3350_n2932#" 138 0 "a_n3350_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -3736 -2500 -3735 -2499 l=5000 "a_n5410_n3062#" "a_n3736_n2500#" 0 0 "a_n3736_n2932#" 138 0 "a_n3736_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -4122 -2500 -4121 -2499 l=5000 "a_n5410_n3062#" "a_n4122_n2500#" 0 0 "a_n4122_n2932#" 138 0 "a_n4122_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -4508 -2500 -4507 -2499 l=5000 "a_n5410_n3062#" "a_n4508_n2500#" 0 0 "a_n4508_n2932#" 138 0 "a_n4508_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -4894 -2500 -4893 -2499 l=5000 "a_n5410_n3062#" "a_n4894_n2500#" 0 0 "a_n4894_n2932#" 138 0 "a_n4894_2500#" 138 0
+device rsubckt sky130_fd_pr__res_xhigh_po_0p69 -5280 -2500 -5279 -2499 l=5000 "a_n5410_n3062#" "a_n5280_n2500#" 0 0 "a_n5280_n2932#" 138 0 "a_n5280_2500#" 138 0
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/unused/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
similarity index 100%
rename from mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
rename to mag/unused/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
diff --git a/mag/unused/sky130_fd_sc_hvl__buf_8.ext b/mag/unused/sky130_fd_sc_hvl__buf_8.ext
new file mode 100644
index 0000000..d0d372b
--- /dev/null
+++ b/mag/unused/sky130_fd_sc_hvl__buf_8.ext
@@ -0,0 +1,71 @@
+timestamp 1646909064
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+port "VGND" 2 0 51 1920 125 m1
+port "X" 6 1759 612 1793 646 li
+port "X" 6 1759 538 1793 572 li
+port "X" 6 1759 464 1793 498 li
+port "X" 6 1759 390 1793 424 li
+port "X" 6 1759 316 1793 350 li
+port "X" 6 1759 242 1793 276 li
+port "X" 6 1759 168 1793 202 li
+port "VPWR" 5 0 689 1920 763 m1
+port "A" 1 415 316 449 350 li
+port "A" 1 319 316 353 350 li
+port "A" 1 223 316 257 350 li
+port "A" 1 127 316 161 350 li
+port "VPB" 4 960 802 960 802 m1
+port "VPB" 4 0 791 1920 814 m1
+port "VNB" 3 960 11 960 11 m1
+port "VNB" 3 0 0 1920 23 m1
+node "buf_8" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 3390 5260.02 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 58350 2578 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251312 5724 142080 3988 0 0 0 0 0 0 0 0 0 0
+node "X" 8451 284.755 1759 168 li 0 0 0 0 0 0 0 0 0 0 0 0 33600 1648 67200 2848 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 190646 8028 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 7867 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116700 4378 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 304848 6576 142080 3988 0 0 0 0 0 0 0 0 0 0
+node "a_45_443#" 6501 1706.56 45 443 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 16950 826 33900 1426 0 0 0 0 0 0 0 0 0 0 0 0 0 0 562400 11448 0 0 84628 3504 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 1110 650.338 127 316 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 213000 4460 0 0 15134 738 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 13840 3201.12 0 791 m1 0 0 0 0 1067040 5144 0 0 0 0 0 0 65280 3908 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65280 3908 88320 3932 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 0 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65280 3908 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65280 3908 88320 3932 0 0 0 0 0 0 0 0 0 0
+cap "A" "VGND" 560.88
+cap "VGND" "VPWR" 167.292
+cap "a_45_443#" "VGND" 1462.07
+cap "A" "VPWR" 671.182
+cap "a_45_443#" "A" 906.847
+cap "VGND" "X" 2085.08
+cap "a_45_443#" "VPWR" 2726.76
+cap "A" "X" 4.99648
+cap "X" "VPWR" 2921.29
+cap "a_45_443#" "X" 2064.22
+cap "VPB" "A" 405.9
+cap "VPB" "VPWR" 5071.95
+cap "VPB" "a_45_443#" 1160.19
+cap "VPB" "X" 208.569
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1718 141 1719 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "X" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1562 141 1563 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "VGND" 150 0 "X" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1406 141 1407 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "X" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1250 141 1251 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "VGND" 150 0 "X" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1094 141 1095 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "X" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 938 141 939 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "VGND" 150 0 "X" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 782 141 783 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "X" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 626 141 627 142 l=100 w=150 "VNB" "a_45_443#" 200 0 "VGND" 150 0 "X" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 470 141 471 142 l=100 w=150 "VNB" "A" 200 0 "a_45_443#" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 314 141 315 142 l=100 w=150 "VNB" "A" 200 0 "VGND" 150 0 "a_45_443#" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 106 141 107 142 l=100 w=150 "VNB" "A" 200 0 "a_45_443#" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1718 443 1719 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "X" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1562 443 1563 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "VPWR" 300 0 "X" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1406 443 1407 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "X" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1250 443 1251 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "VPWR" 300 0 "X" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1094 443 1095 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "X" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 938 443 939 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "VPWR" 300 0 "X" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 782 443 783 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "X" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 626 443 627 444 l=100 w=300 "VPB" "a_45_443#" 200 0 "VPWR" 300 0 "X" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 470 443 471 444 l=100 w=300 "VPB" "A" 200 0 "a_45_443#" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 314 443 315 444 l=100 w=300 "VPB" "A" 200 0 "VPWR" 300 0 "a_45_443#" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 102 443 103 444 l=100 w=300 "VPB" "A" 200 0 "a_45_443#" 300 0 "VPWR" 300 0
diff --git a/mag/unused/sky130_fd_sc_hvl__fill_4.ext b/mag/unused/sky130_fd_sc_hvl__fill_4.ext
new file mode 100644
index 0000000..70f250e
--- /dev/null
+++ b/mag/unused/sky130_fd_sc_hvl__fill_4.ext
@@ -0,0 +1,18 @@
+timestamp 1646909064
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+port "VGND" 1 0 51 384 125 m1
+port "VPWR" 4 0 689 384 763 m1
+port "VPB" 3 192 802 192 802 m1
+port "VPB" 3 0 791 384 814 m1
+port "VNB" 2 192 11 192 11 m1
+port "VNB" 2 0 0 384 23 m1
+node "fill_4" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 1 823.393 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28416 916 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 1 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28416 916 0 0 0 0 0 0 0 0 0 0
+node "VPB" 3140 804.96 0 791 m1 0 0 0 0 268320 2072 0 0 0 0 0 0 13056 836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13056 836 17664 860 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 0 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13056 836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13056 836 17664 860 0 0 0 0 0 0 0 0 0 0
+cap "VPWR" "VPB" 823.393
diff --git a/mag/unused/sky130_fd_sc_hvl__inv_8.ext b/mag/unused/sky130_fd_sc_hvl__inv_8.ext
new file mode 100644
index 0000000..a6f902e
--- /dev/null
+++ b/mag/unused/sky130_fd_sc_hvl__inv_8.ext
@@ -0,0 +1,57 @@
+timestamp 1646909064
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+port "VGND" 2 0 51 1440 125 m1
+port "Y" 6 1279 168 1313 202 li
+port "Y" 6 1183 168 1217 202 li
+port "VPWR" 5 0 689 1440 763 m1
+port "A" 1 895 316 929 350 li
+port "A" 1 799 316 833 350 li
+port "A" 1 703 316 737 350 li
+port "A" 1 607 316 641 350 li
+port "A" 1 511 316 545 350 li
+port "A" 1 415 316 449 350 li
+port "A" 1 319 316 353 350 li
+port "VPB" 4 720 802 720 802 m1
+port "VPB" 4 0 791 1440 814 m1
+port "VNB" 3 720 11 720 11 m1
+port "VNB" 3 0 0 1440 23 m1
+node "inv_8" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 2857 4060.26 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 45600 2108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 145506 3998 106560 3028 0 0 0 0 0 0 0 0 0 0
+node "Y" 8481 346.12 1183 168 li 0 0 0 0 0 0 0 0 0 0 0 0 33600 1648 67200 2848 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 175256 7808 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 7245 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82200 3548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 249836 5296 106560 3028 0 0 0 0 0 0 0 0 0 0
+node "A" 3093 1765.12 319 316 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 572200 11644 0 0 60630 2674 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 10488 2452.32 0 791 m1 0 0 0 0 817440 4184 0 0 0 0 0 0 48960 2948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48960 2948 66240 2972 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 0 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48960 2948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48960 2948 66240 2972 0 0 0 0 0 0 0 0 0 0
+cap "A" "VGND" 1107.42
+cap "A" "VPWR" 1932.87
+cap "VPWR" "VPB" 3975.33
+cap "VGND" "Y" 1743.97
+cap "VPWR" "Y" 2821.33
+cap "A" "VPB" 1060.95
+cap "VPWR" "VGND" 104.31
+cap "A" "Y" 3559.97
+cap "Y" "VPB" 253.524
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1252 141 1253 142 l=100 w=150 "VNB" "A" 200 0 "Y" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 1096 141 1097 142 l=100 w=150 "VNB" "A" 200 0 "VGND" 150 0 "Y" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 912 141 913 142 l=100 w=150 "VNB" "A" 200 0 "Y" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 756 141 757 142 l=100 w=150 "VNB" "A" 200 0 "VGND" 150 0 "Y" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 600 141 601 142 l=100 w=150 "VNB" "A" 200 0 "Y" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 444 141 445 142 l=100 w=150 "VNB" "A" 200 0 "VGND" 150 0 "Y" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 288 141 289 142 l=100 w=150 "VNB" "A" 200 0 "Y" 150 0 "VGND" 150 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 132 141 133 142 l=100 w=150 "VNB" "A" 200 0 "VGND" 150 0 "Y" 150 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1252 443 1253 444 l=100 w=300 "VPB" "A" 200 0 "Y" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 1096 443 1097 444 l=100 w=300 "VPB" "A" 200 0 "VPWR" 300 0 "Y" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 940 443 941 444 l=100 w=300 "VPB" "A" 200 0 "Y" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 784 443 785 444 l=100 w=300 "VPB" "A" 200 0 "VPWR" 300 0 "Y" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 628 443 629 444 l=100 w=300 "VPB" "A" 200 0 "Y" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 472 443 473 444 l=100 w=300 "VPB" "A" 200 0 "VPWR" 300 0 "Y" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 316 443 317 444 l=100 w=300 "VPB" "A" 200 0 "Y" 300 0 "VPWR" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 160 443 161 444 l=100 w=300 "VPB" "A" 200 0 "VPWR" 300 0 "Y" 300 0
diff --git a/mag/unused/sky130_fd_sc_hvl__schmittbuf_1.ext b/mag/unused/sky130_fd_sc_hvl__schmittbuf_1.ext
new file mode 100644
index 0000000..b5361fa
--- /dev/null
+++ b/mag/unused/sky130_fd_sc_hvl__schmittbuf_1.ext
@@ -0,0 +1,89 @@
+timestamp 1646909064
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
+parameters sky130_fd_pr__res_generic_nd__hv l=l w=w
+parameters sky130_fd_pr__res_generic_pd__hv l=l w=w
+port "VGND" 2 0 51 1056 125 m1
+port "X" 6 991 612 1025 646 li
+port "X" 6 991 538 1025 572 li
+port "X" 6 991 464 1025 498 li
+port "X" 6 991 390 1025 424 li
+port "X" 6 991 316 1025 350 li
+port "X" 6 991 242 1025 276 li
+port "X" 6 991 168 1025 202 li
+port "A" 1 511 390 545 424 li
+port "A" 1 415 390 449 424 li
+port "A" 1 607 390 641 424 li
+port "VPWR" 5 0 689 1056 763 m1
+port "VPB" 4 528 802 528 802 m1
+port "VPB" 4 0 791 1056 814 m1
+port "VNB" 3 528 11 528 11 m1
+port "VNB" 3 0 0 1056 23 m1
+node "resistive_li1_ok" 0 0 255 141 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "resistive_li1_ok" 0 0 121 718 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "schmittbuf_1" 0 0 0 0 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_386_107#" 533 0 386 107 mvrnd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15718 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 322 2346.47 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 37912 872 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54964 968 78144 2260 0 0 0 0 0 0 0 0 0 0
+node "a_217_207#" 831 158.851 217 207 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 9156 554 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17294 914 0 0 0 0 0 0 0 0 0 0 0 0
+node "X" 1520 104.783 991 168 li 0 0 0 0 0 0 0 0 0 0 0 0 7950 406 15900 706 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42880 1414 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_231_463#" 1719 0 231 463 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16350 818 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32666 1446 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_78_463#" 932 208.226 78 463 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 2436 200 7950 406 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31587 1638 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 551 432.782 607 390 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91654 2134 0 0 15222 634 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 859 90.8998 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40890 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76947 1142 78144 2260 0 0 0 0 0 0 0 0 0 0
+node "a_198_685#" 2048 0 198 685 mvrpd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36076 1360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_64_207#" 684 88.7951 64 207 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 4452 274 2436 200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28726 1578 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_117_181#" 1780 735.694 117 181 p 0 0 0 0 0 0 0 0 0 0 0 0 4452 274 7950 406 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124952 3028 0 0 57569 2376 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 8162 1825.79 0 791 m1 0 0 0 0 608598 3452 0 0 0 0 0 0 35904 2180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35904 2180 48576 2204 0 0 0 0 0 0 0 0 0 0
+substrate "VNB" 0 0 0 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35904 2180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35904 2180 48576 2204 0 0 0 0 0 0 0 0 0 0
+cap "A" "VPWR" 70.6267
+cap "VGND" "a_217_207#" 28.2455
+cap "A" "a_217_207#" 137.527
+cap "a_117_181#" "a_78_463#" 410.397
+cap "a_117_181#" "VPB" 462.436
+cap "a_64_207#" "VPWR" 123.346
+cap "VGND" "a_78_463#" 141.583
+cap "a_64_207#" "a_217_207#" 23.2955
+cap "A" "a_78_463#" 8.53947
+cap "A" "VPB" 313.641
+cap "VGND" "a_117_181#" 342.682
+cap "a_117_181#" "A" 596.693
+cap "a_231_463#" "VPWR" 97.4719
+cap "a_231_463#" "a_217_207#" 19.0199
+cap "a_64_207#" "a_78_463#" 398.183
+cap "a_64_207#" "VPB" 347.903
+cap "VGND" "A" 38.735
+cap "a_64_207#" "a_117_181#" 56.8657
+cap "X" "VPWR" 219.443
+cap "a_231_463#" "a_78_463#" 71.5945
+cap "a_231_463#" "VPB" 285.64
+cap "a_231_463#" "a_117_181#" 316.929
+cap "a_64_207#" "A" 5.94792
+cap "X" "VPB" 137.141
+cap "a_231_463#" "A" 184.306
+cap "a_78_463#" "a_217_207#" 255.9
+cap "VPB" "VPWR" 2232.31
+cap "a_117_181#" "X" 279.37
+cap "a_117_181#" "VPWR" 321.81
+cap "a_117_181#" "a_217_207#" 301.937
+cap "a_231_463#" "a_64_207#" 38.7619
+cap "VGND" "X" 153.869
+cap "A" "X" 6.26045
+cap "VGND" "VPWR" 42.5652
+cap "a_78_463#" "VPB" 39.9019
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 873 107 874 108 l=100 w=150 "VNB" "a_117_181#" 200 0 "VGND" 150 0 "X" 150 0
+device rsubckt sky130_fd_pr__res_generic_nd__hv 386 107 387 108 l=271 w=58 "VNB" "a_386_107#" 0 0 "a_78_463#" 58 0 "VGND" 58 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 539 225 540 226 l=100 w=84 "VNB" "A" 200 0 "a_217_207#" 84 0 "VGND" 84 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 383 225 384 226 l=100 w=84 "VNB" "A" 200 0 "a_117_181#" 84 0 "a_217_207#" 84 0
+device msubckt sky130_fd_pr__nfet_g5v0d10v5 117 207 118 208 l=100 w=84 "VNB" "a_117_181#" 200 0 "a_64_207#" 84 0 "a_217_207#" 84 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 873 443 874 444 l=100 w=300 "VPB" "a_117_181#" 200 0 "VPWR" 300 0 "X" 300 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 553 463 554 464 l=100 w=150 "VPB" "A" 200 0 "a_231_463#" 150 0 "VPWR" 150 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 397 463 398 464 l=100 w=150 "VPB" "A" 200 0 "a_117_181#" 150 0 "a_231_463#" 150 0
+device msubckt sky130_fd_pr__pfet_g5v0d10v5 131 463 132 464 l=100 w=150 "VPB" "a_117_181#" 200 0 "a_78_463#" 150 0 "a_231_463#" 150 0
+device rsubckt sky130_fd_pr__res_generic_pd__hv 198 685 199 686 l=622 w=58 "VPB" "a_198_685#" 0 0 "a_64_207#" 58 0 "VPWR" 58 0
diff --git a/mag/unused/user_analog_proj_example.ext b/mag/unused/user_analog_proj_example.ext
new file mode 100644
index 0000000..19f24a8
--- /dev/null
+++ b/mag/unused/user_analog_proj_example.ext
@@ -0,0 +1,11 @@
+timestamp 1639841760
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use example_por example_por_1 1 0 14132 0 1 -22
+use example_por example_por_0 -1 0 11285 0 1 -14
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "example_por_1/a_7438_7387#" "example_por_0/a_7438_7387#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "example_por_0/a_7438_7387#" "VSUBS"
diff --git a/mag/user_analog_proj_example.mag b/mag/unused/user_analog_proj_example.mag
similarity index 100%
rename from mag/user_analog_proj_example.mag
rename to mag/unused/user_analog_proj_example.mag
diff --git a/mag/unused/user_analog_project_wrapper_-_copy_beforehand.mag b/mag/unused/user_analog_project_wrapper_-_copy_beforehand.mag
new file mode 100644
index 0000000..a4f3d92
--- /dev/null
+++ b/mag/unused/user_analog_project_wrapper_-_copy_beforehand.mag
@@ -0,0 +1,2362 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1639841760
+<< mvpsubdiff >>
+rect 345740 628255 345764 629032
+rect 371078 628255 371102 629032
+<< mvpsubdiffcont >>
+rect 345764 628255 371078 629032
+<< locali >>
+rect 345748 628255 345764 629032
+rect 371078 628255 371094 629032
+<< viali >>
+rect 357593 628300 359298 629000
+<< metal1 >>
+rect 357470 629399 359442 629457
+rect 357470 628057 357538 629399
+rect 359388 628057 359442 629399
+rect 357470 627990 359442 628057
+<< via1 >>
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+rect 357538 628300 357593 629000
+rect 357593 628300 359298 629000
+rect 359298 628300 359388 629000
+rect 357538 628057 359388 628300
+<< metal2 >>
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+rect 357470 628057 357538 629399
+rect 359388 628057 359442 629399
+rect 357470 627990 359442 628057
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+rect 351918 613071 359350 614900
+rect 363318 617835 365147 617929
+rect 363318 615255 363412 617835
+rect 364987 615255 365147 617835
+rect 363318 601572 365147 615255
+rect 363318 597231 363414 601572
+rect 364992 597231 365147 601572
+rect 363318 597052 365147 597231
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use user_analog_proj_example user_analog_proj_example_0
+timestamp 1639841760
+transform 1 0 345668 0 -1 627114
+box -59 -22 25476 8324
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
+flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
+flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
+flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/unused/user_analog_project_wrapper_-_fails_xor_dunno_why.mag b/mag/unused/user_analog_project_wrapper_-_fails_xor_dunno_why.mag
new file mode 100644
index 0000000..525f56f
--- /dev/null
+++ b/mag/unused/user_analog_project_wrapper_-_fails_xor_dunno_why.mag
@@ -0,0 +1,2581 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647528854
+<< metal1 >>
+rect 41834 512460 42329 512530
+rect 42399 512460 42405 512530
+rect 30376 511755 30382 511807
+rect 30434 511798 30440 511807
+rect 30434 511764 31078 511798
+rect 30434 511755 30440 511764
+<< via1 >>
+rect 42329 512460 42399 512530
+rect 30382 511755 30434 511807
+<< metal2 >>
+rect 42923 514919 42932 514929
+rect 41864 514879 42932 514919
+rect 42923 514869 42932 514879
+rect 42992 514869 43001 514929
+rect 42783 514759 42792 514769
+rect 41864 514719 42792 514759
+rect 42783 514709 42792 514719
+rect 42852 514709 42861 514769
+rect 41864 514639 42260 514679
+rect 42220 514632 42260 514639
+rect 42557 514632 42566 514642
+rect 41862 514559 42150 514599
+rect 42220 514592 42566 514632
+rect 42557 514582 42566 514592
+rect 42626 514582 42635 514642
+rect 42110 514466 42150 514559
+rect 42287 514466 42296 514476
+rect 42110 514426 42296 514466
+rect 42287 514416 42296 514426
+rect 42356 514416 42365 514476
+rect 42296 512530 42578 512563
+rect 42296 512460 42329 512530
+rect 42399 512460 42578 512530
+rect 42296 512427 42578 512460
+rect 42714 512427 42723 512563
+rect 30382 511807 30434 511813
+rect 1320 511757 30382 511806
+rect 882 511553 891 511613
+rect 951 511607 960 511613
+rect 1320 511607 1369 511757
+rect 30382 511749 30434 511755
+rect 951 511558 1369 511607
+rect 951 511553 960 511558
+rect 29734 511158 29743 511218
+rect 29803 511158 31089 511218
+rect 524 -800 636 480
+rect 1706 -800 1818 480
+rect 2888 -800 3000 480
+rect 4070 -800 4182 480
+rect 5252 -800 5364 480
+rect 6434 -800 6546 480
+rect 7616 -800 7728 480
+rect 8798 -800 8910 480
+rect 9980 -800 10092 480
+rect 11162 -800 11274 480
+rect 12344 -800 12456 480
+rect 13526 -800 13638 480
+rect 14708 -800 14820 480
+rect 15890 -800 16002 480
+rect 17072 -800 17184 480
+rect 18254 -800 18366 480
+rect 19436 -800 19548 480
+rect 20618 -800 20730 480
+rect 21800 -800 21912 480
+rect 22982 -800 23094 480
+rect 24164 -800 24276 480
+rect 25346 -800 25458 480
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+rect 27710 -800 27822 480
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+rect 30074 -800 30186 480
+rect 31256 -800 31368 480
+rect 32438 -800 32550 480
+rect 33620 -800 33732 480
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+rect 37166 -800 37278 480
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+rect 39530 -800 39642 480
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+rect 44258 -800 44370 480
+rect 45440 -800 45552 480
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+rect 51350 -800 51462 480
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+rect -800 2726 480 2838
+rect 583428 2726 584800 2838
+rect -800 1544 480 1656
+rect 583520 1544 584800 1656
+<< rmetal3 >>
+rect 682 375954 738 376066
+rect 882 332732 938 332844
+rect 992 289510 1048 289622
+rect 798 246488 854 246600
+<< via3 >>
+rect 52487 685179 56641 689333
+rect 171434 685131 175588 689285
+rect 222925 685131 227079 689285
+rect 323730 689286 327884 689294
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+rect 520816 685139 524972 689295
+rect 66197 639795 70995 644593
+rect 31016 534689 31260 534933
+rect 37554 534892 37798 535136
+rect 31328 525666 31572 525910
+rect 41336 535034 41580 535278
+rect 37892 525764 38136 526008
+rect 52486 533156 56642 537312
+rect 566344 639784 571144 644584
+rect 41686 525828 41930 526072
+rect 66205 523773 71003 528571
+rect 42927 514929 42997 514934
+rect 42927 514869 42932 514929
+rect 42932 514869 42992 514929
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+rect 46754 514867 46818 514931
+rect 42787 514769 42857 514774
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+rect 46482 514707 46546 514771
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+rect 42566 514582 42626 514642
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+rect 42561 514577 42631 514582
+rect 46236 514580 46300 514644
+rect 42291 514476 42361 514481
+rect 42291 514416 42296 514476
+rect 42296 514416 42356 514476
+rect 42356 514416 42361 514476
+rect 42291 514411 42361 514416
+rect 45936 514414 46000 514478
+rect 878 468334 942 468398
+rect 29741 468334 29805 468398
+rect 1293 425069 1427 425203
+rect 42578 425068 42714 425204
+rect 902 378336 966 378400
+rect 872 375954 984 376066
+rect 1120 335112 1184 335176
+rect 1138 332732 1250 332844
+rect 1616 291900 1680 291964
+rect 1344 289510 1456 289622
+rect 46754 378336 46818 378400
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+rect 46482 335112 46546 335176
+rect 68357 332733 68467 332843
+rect 46236 291900 46300 291964
+rect 68547 289511 68657 289621
+rect 1250 248866 1314 248930
+rect 45936 248866 46000 248930
+rect 968 246488 1080 246600
+rect 68295 246489 68405 246599
+<< metal4 >>
+rect 165594 702300 170594 704800
+rect 175894 702300 180894 704800
+rect 217294 702300 222294 704800
+rect 227594 702300 232594 704800
+rect 318994 702300 323994 704800
+rect 329294 702300 334294 704800
+rect 52486 689333 173688 689334
+rect 52486 685179 52487 689333
+rect 56641 689286 173688 689333
+rect 510920 689295 515078 689296
+rect 520815 689295 524973 689296
+rect 323729 689294 510921 689295
+rect 323729 689287 323730 689294
+rect 323728 689286 323730 689287
+rect 327884 689286 510921 689294
+rect 56641 689285 323729 689286
+rect 56641 685179 171434 689285
+rect 52486 685178 171434 685179
+rect 52534 684716 56690 685178
+rect 171433 685131 171434 685178
+rect 175588 685131 222925 689285
+rect 227079 685131 323729 689285
+rect 171433 685130 323729 685131
+rect 327885 685139 510921 689286
+rect 515077 685139 520816 689295
+rect 524972 685139 525998 689295
+rect 327885 685130 327886 685139
+rect 510920 685138 515078 685139
+rect 520815 685138 524973 685139
+rect 323728 685129 327886 685130
+rect 66196 644593 70996 644594
+rect 66196 639795 66197 644593
+rect 70995 644584 70996 644593
+rect 566343 644584 571145 644585
+rect 70995 639795 566344 644584
+rect 66196 639784 566344 639795
+rect 571144 639784 571145 644584
+rect 66196 639608 70996 639784
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+rect 52534 537313 56690 538472
+rect 52485 537312 56690 537313
+rect 52485 537295 52486 537312
+rect 27934 535278 52486 537295
+rect 27934 535136 41336 535278
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+rect 27934 526008 41686 526072
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+rect 38136 525828 41686 526008
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+rect 31572 525666 66205 525764
+rect 27934 523784 66205 525666
+rect 44462 523773 66205 523784
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+rect 44462 523772 71004 523773
+rect 42926 514934 42998 514935
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+rect 984 375954 68572 375955
+rect 871 375953 985 375954
+rect 1119 335176 1185 335177
+rect 1119 335112 1120 335176
+rect 1184 335174 1185 335176
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+rect 1184 335114 46482 335174
+rect 1184 335112 1185 335114
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+rect 46546 335112 46547 335176
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+rect 1137 332844 1251 332845
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+rect 1250 332843 68468 332844
+rect 1250 332733 68357 332843
+rect 68467 332733 68468 332843
+rect 1250 332732 68468 332733
+rect 1137 332731 1251 332732
+rect 1615 291964 1681 291965
+rect 1615 291900 1616 291964
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+rect 46235 291964 46301 291965
+rect 46235 291962 46236 291964
+rect 1680 291902 46236 291962
+rect 1680 291900 1681 291902
+rect 1615 291899 1681 291900
+rect 46235 291900 46236 291902
+rect 46300 291900 46301 291964
+rect 46235 291899 46301 291900
+rect 1343 289622 1457 289623
+rect 1343 289510 1344 289622
+rect 1456 289621 68658 289622
+rect 1456 289511 68547 289621
+rect 68657 289511 68658 289621
+rect 1456 289510 68658 289511
+rect 1343 289509 1457 289510
+rect 1249 248930 1315 248931
+rect 1249 248866 1250 248930
+rect 1314 248928 1315 248930
+rect 45935 248930 46001 248931
+rect 45935 248928 45936 248930
+rect 1314 248868 45936 248928
+rect 1314 248866 1315 248868
+rect 1249 248865 1315 248866
+rect 45935 248866 45936 248868
+rect 46000 248866 46001 248930
+rect 45935 248865 46001 248866
+rect 967 246600 1081 246601
+rect 967 246488 968 246600
+rect 1080 246599 68406 246600
+rect 1080 246489 68295 246599
+rect 68405 246489 68406 246599
+rect 1080 246488 68406 246489
+rect 967 246487 1081 246488
+<< metal5 >>
+rect 165594 702300 170594 704800
+rect 175894 702300 180894 704800
+rect 217294 702300 222294 704800
+rect 227594 702300 232594 704800
+rect 318994 702300 323994 704800
+rect 329294 702300 334294 704800
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use vco_with_fdivs vco_with_fdivs_0 ~/Desktop/GitSandboxes/caravel_user_project_analog_vco/mag/3-stage_cs-vco_dp9
+timestamp 1647518745
+transform -1 0 39745 0 1 512921
+box -2159 -1766 8717 2867
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 568331 640208 579394 644177 0 FreeSans 16000 0 0 0 VCCD1
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+rlabel metal3 511536 689919 514534 698292 0 VSSA1
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/unused/user_analog_project_wrapper_empty.mag
similarity index 100%
rename from mag/user_analog_project_wrapper_empty.mag
rename to mag/unused/user_analog_project_wrapper_empty.mag
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/unused/user_analog_project_wrapper_empty_-_copy_beforehand.mag
similarity index 100%
copy from mag/user_analog_project_wrapper_empty.mag
copy to mag/unused/user_analog_project_wrapper_empty_-_copy_beforehand.mag
diff --git a/mag/unused/user_analog_project_wrapper_vco_-_seccopy_16-3-2022_18y54.mag b/mag/unused/user_analog_project_wrapper_vco_-_seccopy_16-3-2022_18y54.mag
new file mode 100644
index 0000000..e1160eb
--- /dev/null
+++ b/mag/unused/user_analog_project_wrapper_vco_-_seccopy_16-3-2022_18y54.mag
@@ -0,0 +1,2281 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647453171
+<< metal1 >>
+rect 468633 664418 468639 664573
+rect 468794 664530 535456 664573
+rect 468794 664460 540362 664530
+rect 468794 664418 535456 664460
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+rect 551118 663764 579024 663798
+rect 579018 663755 579024 663764
+rect 579076 663755 579082 663807
+<< via1 >>
+rect 468639 664418 468794 664573
+rect 579024 663755 579076 663807
+<< metal2 >>
+rect 468639 664573 468794 664579
+rect 468630 664418 468639 664573
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+rect 468639 664412 468794 664418
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+<< via2 >>
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+<< metal3 >>
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+<< via3 >>
+rect 171434 685131 175588 689285
+rect 222925 685131 227079 689285
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+<< metal4 >>
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+rect 566343 639783 571145 639784
+<< metal5 >>
+rect 165594 702300 170594 704800
+rect 175894 702300 180894 704800
+rect 217294 702300 222294 704800
+rect 227594 702300 232594 704800
+rect 318994 702300 323994 704800
+rect 329294 702300 334294 704800
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use vco_with_fdivs vco_with_fdivs_0 ~/Desktop/GitSandboxes/caravel_user_project_analog_vco/mag/3-stage_cs-vco_dp9
+timestamp 1647427158
+transform 1 0 542451 0 1 664921
+box -2159 -1766 8717 2867
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 568331 640208 579394 644177 0 FreeSans 16000 0 0 0 VCCD1
+rlabel metal3 511536 689919 514534 698292 0 VSSA1
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/unused/vco_with_fdivs.gds b/mag/unused/vco_with_fdivs.gds
new file mode 100644
index 0000000..61306e3
--- /dev/null
+++ b/mag/unused/vco_with_fdivs.gds
Binary files differ
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
new file mode 100644
index 0000000..d5e93a6
--- /dev/null
+++ b/mag/user_analog_project_wrapper.ext
@@ -0,0 +1,1531 @@
+timestamp 1647618066
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use vco_with_fdivs vco_with_fdivs_0 -1 0 32535 0 1 510678
+port "io_analog[4]" 41 329294 702300 334294 704800 m5
+port "io_analog[4]" 47 318994 702300 323994 704800 m5
+port "io_analog[5]" 42 227594 702300 232594 704800 m5
+port "io_analog[5]" 48 217294 702300 222294 704800 m5
+port "io_analog[6]" 43 175894 702300 180894 704800 m5
+port "io_analog[6]" 49 165594 702300 170594 704800 m5
+port "io_analog[4]" 41 329294 702300 334294 704800 m4
+port "io_analog[4]" 47 318994 702300 323994 704800 m4
+port "io_analog[5]" 42 227594 702300 232594 704800 m4
+port "io_analog[5]" 48 217294 702300 222294 704800 m4
+port "io_analog[6]" 43 175894 702300 180894 704800 m4
+port "io_analog[6]" 49 165594 702300 170594 704800 m4
+port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
+port "io_oeb[26]" 128 -800 1544 480 1656 m3
+port "io_in[0]" 56 583520 2726 584800 2838 m3
+port "io_out[26]" 155 -800 2726 480 2838 m3
+port "io_out[0]" 137 583520 3908 584800 4020 m3
+port "io_in[26]" 74 -800 3908 480 4020 m3
+port "io_oeb[0]" 110 583520 5090 584800 5202 m3
+port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
+port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
+port "io_oeb[25]" 127 -800 6272 480 6384 m3
+port "io_in[1]" 67 583520 7454 584800 7566 m3
+port "io_out[25]" 154 -800 7454 480 7566 m3
+port "io_out[1]" 148 583520 8636 584800 8748 m3
+port "io_in[25]" 73 -800 8636 480 8748 m3
+port "io_oeb[1]" 121 583520 9818 584800 9930 m3
+port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
+port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
+port "io_oeb[24]" 126 -800 11000 480 11112 m3
+port "io_in[2]" 75 583520 12182 584800 12294 m3
+port "io_out[24]" 153 -800 12182 480 12294 m3
+port "io_out[2]" 156 583520 13364 584800 13476 m3
+port "io_in[24]" 72 -800 13364 480 13476 m3
+port "io_oeb[2]" 129 583520 14546 584800 14658 m3
+port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
+port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
+port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
+port "io_in[3]" 76 583520 16910 584800 17022 m3
+port "gpio_analog[17]" 8 -800 16910 480 17022 m3
+port "io_out[3]" 157 583520 18092 584800 18204 m3
+port "io_oeb[3]" 130 583520 19274 584800 19386 m3
+port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
+port "io_in[4]" 77 583520 21638 584800 21750 m3
+port "io_out[4]" 158 583520 22820 584800 22932 m3
+port "io_oeb[4]" 131 583520 24002 584800 24114 m3
+port "io_oeb[23]" 125 -800 32422 480 32534 m3
+port "io_out[23]" 152 -800 33604 480 33716 m3
+port "io_in[23]" 71 -800 34786 480 34898 m3
+port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
+port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
+port "gpio_analog[16]" 7 -800 38332 480 38444 m3
+port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
+port "io_in[5]" 78 583520 48096 584800 48208 m3
+port "io_out[5]" 159 583520 49278 584800 49390 m3
+port "io_oeb[5]" 132 583520 50460 584800 50572 m3
+port "io_oeb[22]" 124 -800 75644 480 75756 m3
+port "io_out[22]" 151 -800 76826 480 76938 m3
+port "io_in[22]" 70 -800 78008 480 78120 m3
+port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
+port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
+port "gpio_analog[15]" 6 -800 81554 480 81666 m3
+port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
+port "io_in[6]" 79 583520 92754 584800 92866 m3
+port "io_out[6]" 160 583520 93936 584800 94048 m3
+port "io_oeb[6]" 133 583520 95118 584800 95230 m3
+port "io_oeb[21]" 123 -800 118866 480 118978 m3
+port "io_out[21]" 150 -800 120048 480 120160 m3
+port "io_in[21]" 69 -800 121230 480 121342 m3
+port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
+port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
+port "gpio_analog[14]" 5 -800 124776 480 124888 m3
+port "vssa1" 565 582340 136830 584800 141630 m3
+port "vssa1" 564 582340 146830 584800 151630 m3
+port "vssd2" 571 0 162888 1660 167688 m3
+port "vssd2" 570 0 172888 1660 177688 m3
+port "vssd1" 569 582340 181430 584800 186230 m3
+port "vssd1" 568 582340 191430 584800 196230 m3
+port "vdda2" 560 0 204888 1660 209688 m3
+port "vdda2" 561 0 214888 1660 219688 m3
+port "vdda1" 559 582340 225230 584800 230030 m3
+port "vdda1" 558 582340 235230 584800 240030 m3
+port "io_oeb[20]" 122 -800 246488 480 246600 m3
+port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
+port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
+port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
+port "io_in[7]" 80 583520 272776 584800 272888 m3
+port "io_out[7]" 161 583520 273958 584800 274070 m3
+port "io_oeb[7]" 134 583520 275140 584800 275252 m3
+port "io_out[20]" 149 -800 247670 480 247782 m3
+port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
+port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
+port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
+port "io_in[8]" 81 583520 317198 584800 317310 m3
+port "io_out[8]" 162 583520 318380 584800 318492 m3
+port "io_oeb[8]" 135 583520 319562 584800 319674 m3
+port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
+port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
+port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
+port "io_in[9]" 82 583520 362420 584800 362532 m3
+port "io_out[9]" 163 583520 363602 584800 363714 m3
+port "io_oeb[9]" 136 583520 364784 584800 364896 m3
+port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
+port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
+port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
+port "io_in[10]" 57 583520 408842 584800 408954 m3
+port "io_out[10]" 138 583520 410024 584800 410136 m3
+port "io_oeb[10]" 111 583520 411206 584800 411318 m3
+port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
+port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
+port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
+port "io_in[11]" 58 583520 453264 584800 453376 m3
+port "io_out[11]" 139 583520 454446 584800 454558 m3
+port "io_oeb[11]" 112 583520 455628 584800 455740 m3
+port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
+port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
+port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
+port "io_in[12]" 59 583520 497686 584800 497798 m3
+port "io_out[12]" 140 583520 498868 584800 498980 m3
+port "io_oeb[12]" 113 583520 500050 584800 500162 m3
+port "vdda1" 556 582340 540562 584800 545362 m3
+port "vdda1" 557 582340 550562 584800 555362 m3
+port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
+port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
+port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
+port "io_in[13]" 60 583520 587108 584800 587220 m3
+port "io_out[13]" 141 583520 588290 584800 588402 m3
+port "io_oeb[13]" 114 583520 589472 584800 589584 m3
+port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
+port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
+port "gpio_analog[13]" 4 -800 252398 480 252510 m3
+port "io_oeb[19]" 120 -800 289510 480 289622 m3
+port "io_out[19]" 147 -800 290692 480 290804 m3
+port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
+port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
+port "gpio_analog[12]" 3 -800 295420 480 295532 m3
+port "io_oeb[18]" 119 -800 332732 480 332844 m3
+port "io_out[18]" 146 -800 333914 480 334026 m3
+port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
+port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
+port "gpio_analog[11]" 2 -800 338642 480 338754 m3
+port "io_oeb[17]" 118 -800 375954 480 376066 m3
+port "io_out[17]" 145 -800 377136 480 377248 m3
+port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
+port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
+port "gpio_analog[10]" 1 -800 381864 480 381976 m3
+port "io_oeb[16]" 117 -800 419176 480 419288 m3
+port "io_out[16]" 144 -800 420358 480 420470 m3
+port "io_in[16]" 63 -800 421540 480 421652 m3
+port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
+port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
+port "io_oeb[15]" 116 -800 462398 480 462510 m3
+port "io_in[15]" 62 -800 464762 480 464874 m3
+port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
+port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
+port "io_analog[0]" 36 582300 677984 584800 682984 m3
+port "io_analog[1]" 38 566594 702300 571594 704800 m3
+port "gpio_analog[8]" 16 -800 468308 480 468420 m3
+port "io_oeb[14]" 115 -800 505620 480 505732 m3
+port "io_in[14]" 61 -800 507984 480 508096 m3
+port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
+port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
+port "gpio_analog[7]" 15 -800 511530 480 511642 m3
+port "vssa2" 567 0 549442 1660 554242 m3
+port "vssa2" 566 0 559442 1660 564242 m3
+port "vccd2" 555 0 633842 1660 638642 m3
+port "vccd2" 554 0 643842 1660 648642 m3
+port "io_analog[10]" 37 0 680242 1700 685242 m3
+port "io_analog[2]" 39 465394 702300 470394 704800 m3
+port "io_analog[3]" 40 413394 702300 418394 704800 m3
+port "io_analog[4]" 41 329294 702300 334294 704800 m3
+port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
+port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
+port "io_analog[4]" 47 318994 702300 323994 704800 m3
+port "io_analog[5]" 42 227594 702300 232594 704800 m3
+port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
+port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
+port "io_analog[5]" 48 217294 702300 222294 704800 m3
+port "io_analog[6]" 43 175894 702300 180894 704800 m3
+port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
+port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
+port "io_analog[6]" 49 165594 702300 170594 704800 m3
+port "io_analog[7]" 44 120194 702300 125194 704800 m3
+port "io_analog[8]" 45 68194 702300 73194 704800 m3
+port "io_analog[9]" 46 16194 702300 21194 704800 m3
+port "user_irq[2]" 551 583250 -800 583362 480 m2
+port "user_irq[1]" 550 582068 -800 582180 480 m2
+port "user_irq[0]" 549 580886 -800 580998 480 m2
+port "user_clock2" 548 579704 -800 579816 480 m2
+port "la_oenb[127]" 450 578522 -800 578634 480 m2
+port "la_data_out[127]" 322 577340 -800 577452 480 m2
+port "la_data_in[127]" 194 576158 -800 576270 480 m2
+port "la_oenb[126]" 449 574976 -800 575088 480 m2
+port "la_data_out[126]" 321 573794 -800 573906 480 m2
+port "la_data_in[126]" 193 572612 -800 572724 480 m2
+port "la_oenb[125]" 448 571430 -800 571542 480 m2
+port "la_data_out[125]" 320 570248 -800 570360 480 m2
+port "la_data_in[125]" 192 569066 -800 569178 480 m2
+port "la_oenb[124]" 447 567884 -800 567996 480 m2
+port "la_data_out[124]" 319 566702 -800 566814 480 m2
+port "la_data_in[124]" 191 565520 -800 565632 480 m2
+port "la_oenb[123]" 446 564338 -800 564450 480 m2
+port "la_data_out[123]" 318 563156 -800 563268 480 m2
+port "la_data_in[123]" 190 561974 -800 562086 480 m2
+port "la_oenb[122]" 445 560792 -800 560904 480 m2
+port "la_data_out[122]" 317 559610 -800 559722 480 m2
+port "la_data_in[122]" 189 558428 -800 558540 480 m2
+port "la_oenb[121]" 444 557246 -800 557358 480 m2
+port "la_data_out[121]" 316 556064 -800 556176 480 m2
+port "la_data_in[121]" 188 554882 -800 554994 480 m2
+port "la_oenb[120]" 443 553700 -800 553812 480 m2
+port "la_data_out[120]" 315 552518 -800 552630 480 m2
+port "la_data_in[120]" 187 551336 -800 551448 480 m2
+port "la_oenb[119]" 441 550154 -800 550266 480 m2
+port "la_data_out[119]" 313 548972 -800 549084 480 m2
+port "la_data_in[119]" 185 547790 -800 547902 480 m2
+port "la_oenb[118]" 440 546608 -800 546720 480 m2
+port "la_data_out[118]" 312 545426 -800 545538 480 m2
+port "la_data_in[118]" 184 544244 -800 544356 480 m2
+port "la_oenb[117]" 439 543062 -800 543174 480 m2
+port "la_data_out[117]" 311 541880 -800 541992 480 m2
+port "la_data_in[117]" 183 540698 -800 540810 480 m2
+port "la_oenb[116]" 438 539516 -800 539628 480 m2
+port "la_data_out[116]" 310 538334 -800 538446 480 m2
+port "la_data_in[116]" 182 537152 -800 537264 480 m2
+port "la_oenb[115]" 437 535970 -800 536082 480 m2
+port "la_data_out[115]" 309 534788 -800 534900 480 m2
+port "la_data_in[115]" 181 533606 -800 533718 480 m2
+port "la_oenb[114]" 436 532424 -800 532536 480 m2
+port "la_data_out[114]" 308 531242 -800 531354 480 m2
+port "la_data_in[114]" 180 530060 -800 530172 480 m2
+port "la_oenb[113]" 435 528878 -800 528990 480 m2
+port "la_data_out[113]" 307 527696 -800 527808 480 m2
+port "la_data_in[113]" 179 526514 -800 526626 480 m2
+port "la_oenb[112]" 434 525332 -800 525444 480 m2
+port "la_data_out[112]" 306 524150 -800 524262 480 m2
+port "la_data_in[112]" 178 522968 -800 523080 480 m2
+port "la_oenb[111]" 433 521786 -800 521898 480 m2
+port "la_data_out[111]" 305 520604 -800 520716 480 m2
+port "la_data_in[111]" 177 519422 -800 519534 480 m2
+port "la_oenb[110]" 432 518240 -800 518352 480 m2
+port "la_data_out[110]" 304 517058 -800 517170 480 m2
+port "la_data_in[110]" 176 515876 -800 515988 480 m2
+port "la_oenb[109]" 430 514694 -800 514806 480 m2
+port "la_data_out[109]" 302 513512 -800 513624 480 m2
+port "la_data_in[109]" 174 512330 -800 512442 480 m2
+port "la_oenb[108]" 429 511148 -800 511260 480 m2
+port "la_data_out[108]" 301 509966 -800 510078 480 m2
+port "la_data_in[108]" 173 508784 -800 508896 480 m2
+port "la_oenb[107]" 428 507602 -800 507714 480 m2
+port "la_data_out[107]" 300 506420 -800 506532 480 m2
+port "la_data_in[107]" 172 505238 -800 505350 480 m2
+port "la_oenb[106]" 427 504056 -800 504168 480 m2
+port "la_data_out[106]" 299 502874 -800 502986 480 m2
+port "la_data_in[106]" 171 501692 -800 501804 480 m2
+port "la_oenb[105]" 426 500510 -800 500622 480 m2
+port "la_data_out[105]" 298 499328 -800 499440 480 m2
+port "la_data_in[105]" 170 498146 -800 498258 480 m2
+port "la_oenb[104]" 425 496964 -800 497076 480 m2
+port "la_data_out[104]" 297 495782 -800 495894 480 m2
+port "la_data_in[104]" 169 494600 -800 494712 480 m2
+port "la_oenb[103]" 424 493418 -800 493530 480 m2
+port "la_data_out[103]" 296 492236 -800 492348 480 m2
+port "la_data_in[103]" 168 491054 -800 491166 480 m2
+port "la_oenb[102]" 423 489872 -800 489984 480 m2
+port "la_data_out[102]" 295 488690 -800 488802 480 m2
+port "la_data_in[102]" 167 487508 -800 487620 480 m2
+port "la_oenb[101]" 422 486326 -800 486438 480 m2
+port "la_data_out[101]" 294 485144 -800 485256 480 m2
+port "la_data_in[101]" 166 483962 -800 484074 480 m2
+port "la_oenb[100]" 421 482780 -800 482892 480 m2
+port "la_data_out[100]" 293 481598 -800 481710 480 m2
+port "la_data_in[100]" 165 480416 -800 480528 480 m2
+port "la_oenb[99]" 546 479234 -800 479346 480 m2
+port "la_data_out[99]" 418 478052 -800 478164 480 m2
+port "la_data_in[99]" 290 476870 -800 476982 480 m2
+port "la_oenb[98]" 545 475688 -800 475800 480 m2
+port "la_data_out[98]" 417 474506 -800 474618 480 m2
+port "la_data_in[98]" 289 473324 -800 473436 480 m2
+port "la_oenb[97]" 544 472142 -800 472254 480 m2
+port "la_data_out[97]" 416 470960 -800 471072 480 m2
+port "la_data_in[97]" 288 469778 -800 469890 480 m2
+port "la_oenb[96]" 543 468596 -800 468708 480 m2
+port "la_data_out[96]" 415 467414 -800 467526 480 m2
+port "la_data_in[96]" 287 466232 -800 466344 480 m2
+port "la_oenb[95]" 542 465050 -800 465162 480 m2
+port "la_data_out[95]" 414 463868 -800 463980 480 m2
+port "la_data_in[95]" 286 462686 -800 462798 480 m2
+port "la_oenb[94]" 541 461504 -800 461616 480 m2
+port "la_data_out[94]" 413 460322 -800 460434 480 m2
+port "la_data_in[94]" 285 459140 -800 459252 480 m2
+port "la_oenb[93]" 540 457958 -800 458070 480 m2
+port "la_data_out[93]" 412 456776 -800 456888 480 m2
+port "la_data_in[93]" 284 455594 -800 455706 480 m2
+port "la_oenb[92]" 539 454412 -800 454524 480 m2
+port "la_data_out[92]" 411 453230 -800 453342 480 m2
+port "la_data_in[92]" 283 452048 -800 452160 480 m2
+port "la_oenb[91]" 538 450866 -800 450978 480 m2
+port "la_data_out[91]" 410 449684 -800 449796 480 m2
+port "la_data_in[91]" 282 448502 -800 448614 480 m2
+port "la_oenb[90]" 537 447320 -800 447432 480 m2
+port "la_data_out[90]" 409 446138 -800 446250 480 m2
+port "la_data_in[90]" 281 444956 -800 445068 480 m2
+port "la_oenb[89]" 535 443774 -800 443886 480 m2
+port "la_data_out[89]" 407 442592 -800 442704 480 m2
+port "la_data_in[89]" 279 441410 -800 441522 480 m2
+port "la_oenb[88]" 534 440228 -800 440340 480 m2
+port "la_data_out[88]" 406 439046 -800 439158 480 m2
+port "la_data_in[88]" 278 437864 -800 437976 480 m2
+port "la_oenb[87]" 533 436682 -800 436794 480 m2
+port "la_data_out[87]" 405 435500 -800 435612 480 m2
+port "la_data_in[87]" 277 434318 -800 434430 480 m2
+port "la_oenb[86]" 532 433136 -800 433248 480 m2
+port "la_data_out[86]" 404 431954 -800 432066 480 m2
+port "la_data_in[86]" 276 430772 -800 430884 480 m2
+port "la_oenb[85]" 531 429590 -800 429702 480 m2
+port "la_data_out[85]" 403 428408 -800 428520 480 m2
+port "la_data_in[85]" 275 427226 -800 427338 480 m2
+port "la_oenb[84]" 530 426044 -800 426156 480 m2
+port "la_data_out[84]" 402 424862 -800 424974 480 m2
+port "la_data_in[84]" 274 423680 -800 423792 480 m2
+port "la_oenb[83]" 529 422498 -800 422610 480 m2
+port "la_data_out[83]" 401 421316 -800 421428 480 m2
+port "la_data_in[83]" 273 420134 -800 420246 480 m2
+port "la_oenb[82]" 528 418952 -800 419064 480 m2
+port "la_data_out[82]" 400 417770 -800 417882 480 m2
+port "la_data_in[82]" 272 416588 -800 416700 480 m2
+port "la_oenb[81]" 527 415406 -800 415518 480 m2
+port "la_data_out[81]" 399 414224 -800 414336 480 m2
+port "la_data_in[81]" 271 413042 -800 413154 480 m2
+port "la_oenb[80]" 526 411860 -800 411972 480 m2
+port "la_data_out[80]" 398 410678 -800 410790 480 m2
+port "la_data_in[80]" 270 409496 -800 409608 480 m2
+port "la_oenb[79]" 524 408314 -800 408426 480 m2
+port "la_data_out[79]" 396 407132 -800 407244 480 m2
+port "la_data_in[79]" 268 405950 -800 406062 480 m2
+port "la_oenb[78]" 523 404768 -800 404880 480 m2
+port "la_data_out[78]" 395 403586 -800 403698 480 m2
+port "la_data_in[78]" 267 402404 -800 402516 480 m2
+port "la_oenb[77]" 522 401222 -800 401334 480 m2
+port "la_data_out[77]" 394 400040 -800 400152 480 m2
+port "la_data_in[77]" 266 398858 -800 398970 480 m2
+port "la_oenb[76]" 521 397676 -800 397788 480 m2
+port "la_data_out[76]" 393 396494 -800 396606 480 m2
+port "la_data_in[76]" 265 395312 -800 395424 480 m2
+port "la_oenb[75]" 520 394130 -800 394242 480 m2
+port "la_data_out[75]" 392 392948 -800 393060 480 m2
+port "la_data_in[75]" 264 391766 -800 391878 480 m2
+port "la_oenb[74]" 519 390584 -800 390696 480 m2
+port "la_data_out[74]" 391 389402 -800 389514 480 m2
+port "la_data_in[74]" 263 388220 -800 388332 480 m2
+port "la_oenb[73]" 518 387038 -800 387150 480 m2
+port "la_data_out[73]" 390 385856 -800 385968 480 m2
+port "la_data_in[73]" 262 384674 -800 384786 480 m2
+port "la_oenb[72]" 517 383492 -800 383604 480 m2
+port "la_data_out[72]" 389 382310 -800 382422 480 m2
+port "la_data_in[72]" 261 381128 -800 381240 480 m2
+port "la_oenb[71]" 516 379946 -800 380058 480 m2
+port "la_data_out[71]" 388 378764 -800 378876 480 m2
+port "la_data_in[71]" 260 377582 -800 377694 480 m2
+port "la_oenb[70]" 515 376400 -800 376512 480 m2
+port "la_data_out[70]" 387 375218 -800 375330 480 m2
+port "la_data_in[70]" 259 374036 -800 374148 480 m2
+port "la_oenb[69]" 513 372854 -800 372966 480 m2
+port "la_data_out[69]" 385 371672 -800 371784 480 m2
+port "la_data_in[69]" 257 370490 -800 370602 480 m2
+port "la_oenb[68]" 512 369308 -800 369420 480 m2
+port "la_data_out[68]" 384 368126 -800 368238 480 m2
+port "la_data_in[68]" 256 366944 -800 367056 480 m2
+port "la_oenb[67]" 511 365762 -800 365874 480 m2
+port "la_data_out[67]" 383 364580 -800 364692 480 m2
+port "la_data_in[67]" 255 363398 -800 363510 480 m2
+port "la_oenb[66]" 510 362216 -800 362328 480 m2
+port "la_data_out[66]" 382 361034 -800 361146 480 m2
+port "la_data_in[66]" 254 359852 -800 359964 480 m2
+port "la_oenb[65]" 509 358670 -800 358782 480 m2
+port "la_data_out[65]" 381 357488 -800 357600 480 m2
+port "la_data_in[65]" 253 356306 -800 356418 480 m2
+port "la_oenb[64]" 508 355124 -800 355236 480 m2
+port "la_data_out[64]" 380 353942 -800 354054 480 m2
+port "la_data_in[64]" 252 352760 -800 352872 480 m2
+port "la_oenb[63]" 507 351578 -800 351690 480 m2
+port "la_data_out[63]" 379 350396 -800 350508 480 m2
+port "la_data_in[63]" 251 349214 -800 349326 480 m2
+port "la_oenb[62]" 506 348032 -800 348144 480 m2
+port "la_data_out[62]" 378 346850 -800 346962 480 m2
+port "la_data_in[62]" 250 345668 -800 345780 480 m2
+port "la_oenb[61]" 505 344486 -800 344598 480 m2
+port "la_data_out[61]" 377 343304 -800 343416 480 m2
+port "la_data_in[61]" 249 342122 -800 342234 480 m2
+port "la_oenb[60]" 504 340940 -800 341052 480 m2
+port "la_data_out[60]" 376 339758 -800 339870 480 m2
+port "la_data_in[60]" 248 338576 -800 338688 480 m2
+port "la_oenb[59]" 502 337394 -800 337506 480 m2
+port "la_data_out[59]" 374 336212 -800 336324 480 m2
+port "la_data_in[59]" 246 335030 -800 335142 480 m2
+port "la_oenb[58]" 501 333848 -800 333960 480 m2
+port "la_data_out[58]" 373 332666 -800 332778 480 m2
+port "la_data_in[58]" 245 331484 -800 331596 480 m2
+port "la_oenb[57]" 500 330302 -800 330414 480 m2
+port "la_data_out[57]" 372 329120 -800 329232 480 m2
+port "la_data_in[57]" 244 327938 -800 328050 480 m2
+port "la_oenb[56]" 499 326756 -800 326868 480 m2
+port "la_data_out[56]" 371 325574 -800 325686 480 m2
+port "la_data_in[56]" 243 324392 -800 324504 480 m2
+port "la_oenb[55]" 498 323210 -800 323322 480 m2
+port "la_data_out[55]" 370 322028 -800 322140 480 m2
+port "la_data_in[55]" 242 320846 -800 320958 480 m2
+port "la_oenb[54]" 497 319664 -800 319776 480 m2
+port "la_data_out[54]" 369 318482 -800 318594 480 m2
+port "la_data_in[54]" 241 317300 -800 317412 480 m2
+port "la_oenb[53]" 496 316118 -800 316230 480 m2
+port "la_data_out[53]" 368 314936 -800 315048 480 m2
+port "la_data_in[53]" 240 313754 -800 313866 480 m2
+port "la_oenb[52]" 495 312572 -800 312684 480 m2
+port "la_data_out[52]" 367 311390 -800 311502 480 m2
+port "la_data_in[52]" 239 310208 -800 310320 480 m2
+port "la_oenb[51]" 494 309026 -800 309138 480 m2
+port "la_data_out[51]" 366 307844 -800 307956 480 m2
+port "la_data_in[51]" 238 306662 -800 306774 480 m2
+port "la_oenb[50]" 493 305480 -800 305592 480 m2
+port "la_data_out[50]" 365 304298 -800 304410 480 m2
+port "la_data_in[50]" 237 303116 -800 303228 480 m2
+port "la_oenb[49]" 491 301934 -800 302046 480 m2
+port "la_data_out[49]" 363 300752 -800 300864 480 m2
+port "la_data_in[49]" 235 299570 -800 299682 480 m2
+port "la_oenb[48]" 490 298388 -800 298500 480 m2
+port "la_data_out[48]" 362 297206 -800 297318 480 m2
+port "la_data_in[48]" 234 296024 -800 296136 480 m2
+port "la_oenb[47]" 489 294842 -800 294954 480 m2
+port "la_data_out[47]" 361 293660 -800 293772 480 m2
+port "la_data_in[47]" 233 292478 -800 292590 480 m2
+port "la_oenb[46]" 488 291296 -800 291408 480 m2
+port "la_data_out[46]" 360 290114 -800 290226 480 m2
+port "la_data_in[46]" 232 288932 -800 289044 480 m2
+port "la_oenb[45]" 487 287750 -800 287862 480 m2
+port "la_data_out[45]" 359 286568 -800 286680 480 m2
+port "la_data_in[45]" 231 285386 -800 285498 480 m2
+port "la_oenb[44]" 486 284204 -800 284316 480 m2
+port "la_data_out[44]" 358 283022 -800 283134 480 m2
+port "la_data_in[44]" 230 281840 -800 281952 480 m2
+port "la_oenb[43]" 485 280658 -800 280770 480 m2
+port "la_data_out[43]" 357 279476 -800 279588 480 m2
+port "la_data_in[43]" 229 278294 -800 278406 480 m2
+port "la_oenb[42]" 484 277112 -800 277224 480 m2
+port "la_data_out[42]" 356 275930 -800 276042 480 m2
+port "la_data_in[42]" 228 274748 -800 274860 480 m2
+port "la_oenb[41]" 483 273566 -800 273678 480 m2
+port "la_data_out[41]" 355 272384 -800 272496 480 m2
+port "la_data_in[41]" 227 271202 -800 271314 480 m2
+port "la_oenb[40]" 482 270020 -800 270132 480 m2
+port "la_data_out[40]" 354 268838 -800 268950 480 m2
+port "la_data_in[40]" 226 267656 -800 267768 480 m2
+port "la_oenb[39]" 480 266474 -800 266586 480 m2
+port "la_data_out[39]" 352 265292 -800 265404 480 m2
+port "la_data_in[39]" 224 264110 -800 264222 480 m2
+port "la_oenb[38]" 479 262928 -800 263040 480 m2
+port "la_data_out[38]" 351 261746 -800 261858 480 m2
+port "la_data_in[38]" 223 260564 -800 260676 480 m2
+port "la_oenb[37]" 478 259382 -800 259494 480 m2
+port "la_data_out[37]" 350 258200 -800 258312 480 m2
+port "la_data_in[37]" 222 257018 -800 257130 480 m2
+port "la_oenb[36]" 477 255836 -800 255948 480 m2
+port "la_data_out[36]" 349 254654 -800 254766 480 m2
+port "la_data_in[36]" 221 253472 -800 253584 480 m2
+port "la_oenb[35]" 476 252290 -800 252402 480 m2
+port "la_data_out[35]" 348 251108 -800 251220 480 m2
+port "la_data_in[35]" 220 249926 -800 250038 480 m2
+port "la_oenb[34]" 475 248744 -800 248856 480 m2
+port "la_data_out[34]" 347 247562 -800 247674 480 m2
+port "la_data_in[34]" 219 246380 -800 246492 480 m2
+port "la_oenb[33]" 474 245198 -800 245310 480 m2
+port "la_data_out[33]" 346 244016 -800 244128 480 m2
+port "la_data_in[33]" 218 242834 -800 242946 480 m2
+port "la_oenb[32]" 473 241652 -800 241764 480 m2
+port "la_data_out[32]" 345 240470 -800 240582 480 m2
+port "la_data_in[32]" 217 239288 -800 239400 480 m2
+port "la_oenb[31]" 472 238106 -800 238218 480 m2
+port "la_data_out[31]" 344 236924 -800 237036 480 m2
+port "la_data_in[31]" 216 235742 -800 235854 480 m2
+port "la_oenb[30]" 471 234560 -800 234672 480 m2
+port "la_data_out[30]" 343 233378 -800 233490 480 m2
+port "la_data_in[30]" 215 232196 -800 232308 480 m2
+port "la_oenb[29]" 469 231014 -800 231126 480 m2
+port "la_data_out[29]" 341 229832 -800 229944 480 m2
+port "la_data_in[29]" 213 228650 -800 228762 480 m2
+port "la_oenb[28]" 468 227468 -800 227580 480 m2
+port "la_data_out[28]" 340 226286 -800 226398 480 m2
+port "la_data_in[28]" 212 225104 -800 225216 480 m2
+port "la_oenb[27]" 467 223922 -800 224034 480 m2
+port "la_data_out[27]" 339 222740 -800 222852 480 m2
+port "la_data_in[27]" 211 221558 -800 221670 480 m2
+port "la_oenb[26]" 466 220376 -800 220488 480 m2
+port "la_data_out[26]" 338 219194 -800 219306 480 m2
+port "la_data_in[26]" 210 218012 -800 218124 480 m2
+port "la_oenb[25]" 465 216830 -800 216942 480 m2
+port "la_data_out[25]" 337 215648 -800 215760 480 m2
+port "la_data_in[25]" 209 214466 -800 214578 480 m2
+port "la_oenb[24]" 464 213284 -800 213396 480 m2
+port "la_data_out[24]" 336 212102 -800 212214 480 m2
+port "la_data_in[24]" 208 210920 -800 211032 480 m2
+port "la_oenb[23]" 463 209738 -800 209850 480 m2
+port "la_data_out[23]" 335 208556 -800 208668 480 m2
+port "la_data_in[23]" 207 207374 -800 207486 480 m2
+port "la_oenb[22]" 462 206192 -800 206304 480 m2
+port "la_data_out[22]" 334 205010 -800 205122 480 m2
+port "la_data_in[22]" 206 203828 -800 203940 480 m2
+port "la_oenb[21]" 461 202646 -800 202758 480 m2
+port "la_data_out[21]" 333 201464 -800 201576 480 m2
+port "la_data_in[21]" 205 200282 -800 200394 480 m2
+port "la_oenb[20]" 460 199100 -800 199212 480 m2
+port "la_data_out[20]" 332 197918 -800 198030 480 m2
+port "la_data_in[20]" 204 196736 -800 196848 480 m2
+port "la_oenb[19]" 458 195554 -800 195666 480 m2
+port "la_data_out[19]" 330 194372 -800 194484 480 m2
+port "la_data_in[19]" 202 193190 -800 193302 480 m2
+port "la_oenb[18]" 457 192008 -800 192120 480 m2
+port "la_data_out[18]" 329 190826 -800 190938 480 m2
+port "la_data_in[18]" 201 189644 -800 189756 480 m2
+port "la_oenb[17]" 456 188462 -800 188574 480 m2
+port "la_data_out[17]" 328 187280 -800 187392 480 m2
+port "la_data_in[17]" 200 186098 -800 186210 480 m2
+port "la_oenb[16]" 455 184916 -800 185028 480 m2
+port "la_data_out[16]" 327 183734 -800 183846 480 m2
+port "la_data_in[16]" 199 182552 -800 182664 480 m2
+port "la_oenb[15]" 454 181370 -800 181482 480 m2
+port "la_data_out[15]" 326 180188 -800 180300 480 m2
+port "la_data_in[15]" 198 179006 -800 179118 480 m2
+port "la_oenb[14]" 453 177824 -800 177936 480 m2
+port "la_data_out[14]" 325 176642 -800 176754 480 m2
+port "la_data_in[14]" 197 175460 -800 175572 480 m2
+port "la_oenb[13]" 452 174278 -800 174390 480 m2
+port "la_data_out[13]" 324 173096 -800 173208 480 m2
+port "la_data_in[13]" 196 171914 -800 172026 480 m2
+port "la_oenb[12]" 451 170732 -800 170844 480 m2
+port "la_data_out[12]" 323 169550 -800 169662 480 m2
+port "la_data_in[12]" 195 168368 -800 168480 480 m2
+port "la_oenb[11]" 442 167186 -800 167298 480 m2
+port "la_data_out[11]" 314 166004 -800 166116 480 m2
+port "la_data_in[11]" 186 164822 -800 164934 480 m2
+port "la_oenb[10]" 431 163640 -800 163752 480 m2
+port "la_data_out[10]" 303 162458 -800 162570 480 m2
+port "la_data_in[10]" 175 161276 -800 161388 480 m2
+port "la_oenb[9]" 547 160094 -800 160206 480 m2
+port "la_data_out[9]" 419 158912 -800 159024 480 m2
+port "la_data_in[9]" 291 157730 -800 157842 480 m2
+port "la_oenb[8]" 536 156548 -800 156660 480 m2
+port "la_data_out[8]" 408 155366 -800 155478 480 m2
+port "la_data_in[8]" 280 154184 -800 154296 480 m2
+port "la_oenb[7]" 525 153002 -800 153114 480 m2
+port "la_data_out[7]" 397 151820 -800 151932 480 m2
+port "la_data_in[7]" 269 150638 -800 150750 480 m2
+port "la_oenb[6]" 514 149456 -800 149568 480 m2
+port "la_data_out[6]" 386 148274 -800 148386 480 m2
+port "la_data_in[6]" 258 147092 -800 147204 480 m2
+port "la_oenb[5]" 503 145910 -800 146022 480 m2
+port "la_data_out[5]" 375 144728 -800 144840 480 m2
+port "la_data_in[5]" 247 143546 -800 143658 480 m2
+port "la_oenb[4]" 492 142364 -800 142476 480 m2
+port "la_data_out[4]" 364 141182 -800 141294 480 m2
+port "la_data_in[4]" 236 140000 -800 140112 480 m2
+port "la_oenb[3]" 481 138818 -800 138930 480 m2
+port "la_data_out[3]" 353 137636 -800 137748 480 m2
+port "la_data_in[3]" 225 136454 -800 136566 480 m2
+port "la_oenb[2]" 470 135272 -800 135384 480 m2
+port "la_data_out[2]" 342 134090 -800 134202 480 m2
+port "la_data_in[2]" 214 132908 -800 133020 480 m2
+port "la_oenb[1]" 459 131726 -800 131838 480 m2
+port "la_data_out[1]" 331 130544 -800 130656 480 m2
+port "la_data_in[1]" 203 129362 -800 129474 480 m2
+port "la_oenb[0]" 420 128180 -800 128292 480 m2
+port "la_data_out[0]" 292 126998 -800 127110 480 m2
+port "la_data_in[0]" 164 125816 -800 125928 480 m2
+port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
+port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
+port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
+port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
+port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
+port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
+port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
+port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
+port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
+port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
+port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
+port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
+port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
+port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
+port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
+port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
+port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
+port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
+port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
+port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
+port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
+port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
+port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
+port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
+port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
+port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
+port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
+port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
+port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
+port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
+port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
+port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
+port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
+port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
+port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
+port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
+port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
+port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
+port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
+port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
+port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
+port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
+port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
+port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
+port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
+port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
+port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
+port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
+port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
+port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
+port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
+port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
+port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
+port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
+port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
+port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
+port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
+port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
+port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
+port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
+port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
+port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
+port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
+port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
+port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
+port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
+port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
+port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
+port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
+port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
+port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
+port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
+port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
+port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
+port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
+port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
+port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
+port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
+port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
+port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
+port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
+port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
+port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
+port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
+port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
+port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
+port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
+port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
+port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
+port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
+port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
+port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
+port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
+port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
+port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
+port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
+port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
+port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
+port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
+port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
+port "wbs_we_i" 677 6434 -800 6546 480 m2
+port "wbs_stb_i" 676 5252 -800 5364 480 m2
+port "wbs_cyc_i" 607 4070 -800 4182 480 m2
+port "wbs_ack_o" 574 2888 -800 3000 480 m2
+port "wb_rst_i" 573 1706 -800 1818 480 m2
+port "wb_clk_i" 572 524 -800 636 480 m2
+port "vccd1" 553 582340 629784 584800 634584 m3
+port "vccd1" 552 582340 639784 584800 644584 m3
+port "vssa1" 563 510594 702340 515394 704800 m3
+port "vssa1" 562 520594 702340 525394 704800 m3
+port "io_out[15]" 143 -800 463580 480 463692 m3
+port "io_out[14]" 142 -800 506802 480 506914 m3
+port "io_in[20]" 68 -800 248852 480 248964 m3
+port "io_in[19]" 66 -800 291874 480 291986 m3
+port "io_in[18]" 65 -800 335096 480 335208 m3
+port "io_in[17]" 64 -800 378318 480 378430 m3
+port "gpio_analog[9]" 17 -800 425086 480 425198 m3
+node "io_analog[4]" 0 2925 329294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2925 318994 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[5]" 0 2925 227594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[5]" 0 2925 217294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[6]" 0 2925 175894 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[6]" 0 2925 165594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2775 329294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[4]" 0 2775 318994 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[5]" 0 2775 227594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[5]" 0 2775 217294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[6]" 0 2775 175894 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[6]" 0 2775 165594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_in_3v3[0]" 1 613.728 583520 1544 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[26]" 1 613.728 -800 1544 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[0]" 1 613.728 583520 2726 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[26]" 1 613.728 -800 2726 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[0]" 1 613.728 583520 3908 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[26]" 1 613.728 -800 3908 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[0]" 1 613.728 583520 5090 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[26]" 1 613.728 -800 5090 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[1]" 1 613.728 583520 6272 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[25]" 1 613.728 -800 6272 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[1]" 1 613.728 583520 7454 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[25]" 1 613.728 -800 7454 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[1]" 1 613.728 583520 8636 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[25]" 1 613.728 -800 8636 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[1]" 1 613.728 583520 9818 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[25]" 1 613.728 -800 9818 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in_3v3[2]" 1 613.728 583520 11000 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[24]" 1 613.728 -800 11000 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[2]" 1 613.728 583520 12182 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[24]" 1 613.728 -800 12182 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "wbs_dat_o[1]" 1 589.888 14708 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[1]" 1 589.888 13526 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[1]" 1 589.888 12344 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[0]" 1 589.888 11162 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[0]" 1 589.888 9980 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[0]" 1 589.888 8798 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[0]" 1 589.888 7616 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_we_i" 1 589.888 6434 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_stb_i" 1 589.888 5252 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_cyc_i" 1 589.888 4070 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_ack_o" 1 589.888 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_rst_i" 1 589.888 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_clk_i" 1 589.888 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "vccd1" 0 1.9225e+06 582340 639784 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18704128 334904 1030509414 1290946 5418724192 1250112 0 0 0 0
+node "vssa1" 0 1.68355e+06 520594 702340 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9402352 168350 803481910 956150 5128604952 1185092 0 0 0 0
+node "io_out[15]" 28 28965.7 -800 463580 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2357884 46072 4422056 88220 0 0 0 0 0 0
+node "io_out[14]" 27 10923.3 -800 506802 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2554640 45844 290304 5408 0 0 0 0 0 0
+node "io_in[20]" 0 127973 -800 248852 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2011524 68092 16212096 535054 0 0 0 0 0 0
+node "io_in[19]" 0 109855 -800 291874 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2033772 68950 13637616 449238 0 0 0 0 0 0
+node "io_in[18]" 0 91652.6 -800 335096 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2066444 70136 11043816 362778 0 0 0 0 0 0
+node "io_in[17]" 0 73477.7 -800 378318 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2085284 70912 8463816 276778 0 0 0 0 0 0
+node "gpio_analog[9]" 1 51813.2 -800 425086 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15190 574 2268800 65104 6378250 178658 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_in[20]" "io_in[17]" 270.783
+cap "vssa1" "io_out[15]" 146.48
+cap "io_analog[5]" "io_analog[5]" 21250
+cap "io_in[20]" "io_in[19]" 81236.2
+cap "io_in[20]" "vccd1" 384.752
+cap "io_in[17]" "io_in[18]" 51673.9
+cap "vssa1" "io_in[17]" 238.496
+cap "io_analog[4]" "io_clamp_low[0]" 525
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_in[18]" "io_in[19]" 60510.7
+cap "io_clamp_low[1]" "io_analog[5]" 525
+cap "io_in[18]" "vccd1" 148.36
+cap "vssa1" "io_in[19]" 238.496
+cap "vssa1" "vccd1" 262239
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_analog[6]" "io_analog[6]" 26250
+cap "gpio_analog[9]" "vccd1" 213.255
+cap "io_out[14]" "vssa1" 92.4336
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_in[20]" "io_in[18]" 534.024
+cap "io_in[20]" "vssa1" 238.496
+cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_analog[4]" "io_clamp_high[0]" 525
+cap "vssa1" "io_in[18]" 238.496
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_analog[6]" "io_clamp_low[2]" 525
+cap "io_analog[5]" "io_analog[5]" 21250
+cap "vssa1" "gpio_analog[9]" 252.112
+cap "io_clamp_high[1]" "io_analog[5]" 525
+cap "io_clamp_high[2]" "io_analog[6]" 525
+cap "io_clamp_high[1]" "io_clamp_low[1]" 525
+cap "io_in[17]" "io_in[19]" 410.624
+cap "io_in[17]" "vccd1" 27.008
+cap "io_clamp_low[2]" "io_clamp_high[2]" 525
+cap "io_in[19]" "vccd1" 267.608
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_analog[4]" "io_analog[4]" 26250
+device devres sky130_fd_pr__res_generic_m3 2660 246488 2661 246489 56 112 "m3_2660_246488#" 0 0 "io_oeb[20]" 112 0 "vccd1" 112 0
+device devres sky130_fd_pr__res_generic_m3 2504 289510 2505 289511 56 112 "m3_2504_289510#" 0 0 "io_oeb[19]" 112 0 "vccd1" 112 0
+device devres sky130_fd_pr__res_generic_m3 1978 332732 1979 332733 56 112 "m3_1978_332732#" 0 0 "io_oeb[18]" 112 0 "vccd1" 112 0
+device devres sky130_fd_pr__res_generic_m3 1892 375954 1893 375955 56 112 "m3_1892_375954#" 0 0 "io_oeb[17]" 112 0 "vccd1" 112 0
+device devres sky130_fd_pr__res_generic_m3 1453 462398 1454 462399 56 112 "m3_1453_462398#" 0 0 "io_oeb[15]" 112 0 "vssa1" 112 0
+device devres sky130_fd_pr__res_generic_m3 1347 505620 1348 505621 56 112 "m3_1347_505620#" 0 0 "io_oeb[14]" 112 0 "vssa1" 112 0
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/w_7680_n1770#" -126.091
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/out_div256_buf" 48.2391
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VGND" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VPWR" -212.11
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VPWR" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_0/A" 58.1575
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VGND" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 47.995
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VGND" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_1/A" -37.1134
+cap "vco_with_fdivs_0/li_8588_n1221#" "vco_with_fdivs_0/w_7680_n1770#" 13.7755
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/out" "vco_with_fdivs_0/FD_v2_4/GND" 5.16204
+cap "vco_with_fdivs_0/FD_v2_9/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 61.8999
+cap "vco_with_fdivs_0/FD_v2_9/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/out" 125.52
+cap "vco_with_fdivs_0/FD_v2_9/VDD" "vco_with_fdivs_0/FD_v2_4/GND" -18.0768
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/vctrl" -17.01
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/a_8547_n771#" -44.9728
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/vctrl" 8.30537
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VNB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VPB" -564.72
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VPB" "vco_with_fdivs_0/out_div128_buf" 43.8789
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VNB" "vco_with_fdivs_0/out_div128_buf" -21.4782
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_1/A" -60.2456
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 114.152
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/A" 213.247
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VPB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_1/A" 23.3805
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VPB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/A" 7.00455
+cap "vco_with_fdivs_0/FD_v5_0/Clk_Out" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VPB" 226.527
+cap "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VPB" -890.654
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd" "vco_with_fdivs_0/FD_v2_4/VDD" -84.217
+cap "vco_with_fdivs_0/FD_v2_4/GND" "vco_with_fdivs_0/FD_v2_3/Clk_Out" 251.345
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "vco_with_fdivs_0/FD_v2_4/VDD" 39.6636
+cap "vco_with_fdivs_0/FD_v2_3/Clk_Out" "vco_with_fdivs_0/FD_v2_4/VDD" 4.26013
+cap "vco_with_fdivs_0/FD_v2_4/GND" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" 1.87193
+cap "vco_with_fdivs_0/out" "vco_with_fdivs_0/FD_v2_4/VDD" 9.918
+cap "vco_with_fdivs_0/FD_v2_4/GND" "vco_with_fdivs_0/FD_v2_4/VDD" -520.422
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/vctrl" -17.01
+cap "vco_with_fdivs_0/vctrl" "vccd1" -13.4625
+cap "vco_with_fdivs_0/vctrl" "vco_with_fdivs_0/a_8547_n771#" 61.6817
+cap "vco_with_fdivs_0/a_8547_n771#" "vccd1" -625.088
+cap "vco_with_fdivs_0/out_div128_buf" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VNB" -6.7002
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/out_div128_buf" 38.8479
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VNB" -604.11
+cap "vco_with_fdivs_0/FD_v5_0/Clk_Out" "vco_with_fdivs_0/w_7680_n1770#" 86.34
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB" -1025.58
+cap "vco_with_fdivs_0/FD_v2_3/GND" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/out" 12.842
+cap "vco_with_fdivs_0/FD_v2_3/GND" "vco_with_fdivs_0/vdd" -481.689
+cap "vco_with_fdivs_0/out" "vco_with_fdivs_0/FD_v2_3/GND" 11.628
+cap "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/out" 271.996
+cap "vco_with_fdivs_0/out" "vco_with_fdivs_0/vdd" 11.4453
+cap "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 61.0609
+cap "vco_with_fdivs_0/vsel0" "vco_with_fdivs_0/a_8547_n771#" 41.028
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel2" 15.072
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/vsel0" -7.14286
+cap "vco_with_fdivs_0/vsel1" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel2" -55
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/a_8547_n771#" 41.028
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel2" "vco_with_fdivs_0/vsel0" -10
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/vsel1" 15.072
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel2" "vco_with_fdivs_0/a_8547_n771#" 41.028
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel2" -50
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/vsel0" 17.176
+cap "vco_with_fdivs_0/vsel1" "vco_with_fdivs_0/vsel0" -16.6667
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/a_8547_n771#" -575.675
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/w_7680_n1770#" 17.176
+cap "vco_with_fdivs_0/vsel1" "vco_with_fdivs_0/a_8547_n771#" 41.028
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/vsel1" -16.6667
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/w_7680_n1770#" -0.199786
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/w_7680_n1770#" 49.0656
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/a_8547_n771#" 67.6223
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/w_7680_n1770#" -42.399
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/out" "vco_with_fdivs_0/vdd" 7.01129
+cap "vco_with_fdivs_0/vss" "vco_with_fdivs_0/vdd" 278.792
+cap "vco_with_fdivs_0/w_7680_n1770#" "vco_with_fdivs_0/a_8547_n771#" -10.1978
+cap "vco_with_fdivs_0/a_8547_n771#" "vco_with_fdivs_0/w_7680_n1770#" -63.2605
+merge "vco_with_fdivs_0/vss" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vss" -5602.74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1073507 -29146 0 0 0 0 0 0
+merge "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vss" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VNB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VNB"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VNB" "vco_with_fdivs_0/FD_v2_4/GND"
+merge "vco_with_fdivs_0/FD_v2_4/GND" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VGND"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VGND" "vco_with_fdivs_0/a_8547_n771#"
+merge "vco_with_fdivs_0/a_8547_n771#" "vssa1"
+merge "vssa1" "VSUBS"
+merge "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/FD_v2_4/VDD" -7233.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 485173 -36084 0 0 0 0 0 0
+merge "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VPB"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_3/VPB" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VPB"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_16_2/VPB" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd"
+merge "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VPWR"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_4_1/VPWR" "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_0/VPWR"
+merge "vco_with_fdivs_0/sky130_fd_sc_hd__clkbuf_2_0/VPWR" "vco_with_fdivs_0/w_7680_n1770#"
+merge "vco_with_fdivs_0/w_7680_n1770#" "vccd1"
+merge "vco_with_fdivs_0/out_div128_buf" "io_out[14]" -89.5701 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -49812 -360 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/m2_n2159_1638#" "io_in[20]" -31.08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel2" "io_in[19]" -191.865 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -17800 -970 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/sel0" "vco_with_fdivs_0/vsel0" -25.572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11360 -160 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/vsel0" "io_in[17]"
+merge "vco_with_fdivs_0/vsel1" "io_in[18]" -32.668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1760 -168 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/vctrl" "gpio_analog[9]" -62.9958 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8609 -280 0 0 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/out_div256_buf" "io_out[15]" -73.898 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8466 -370 0 0 0 0 0 0 0 0
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index a4f3d92..2370e4c 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,33 +1,131 @@
magic
tech sky130A
magscale 1 2
-timestamp 1639841760
-<< mvpsubdiff >>
-rect 345740 628255 345764 629032
-rect 371078 628255 371102 629032
-<< mvpsubdiffcont >>
-rect 345764 628255 371078 629032
-<< locali >>
-rect 345748 628255 345764 629032
-rect 371078 628255 371094 629032
-<< viali >>
-rect 357593 628300 359298 629000
+timestamp 1647618066
<< metal1 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
+rect 34624 510217 34765 510287
+rect 34835 510217 34841 510287
<< via1 >>
-rect 357538 629000 359388 629399
-rect 357538 628300 357593 629000
-rect 357593 628300 359298 629000
-rect 359298 628300 359388 629000
-rect 357538 628057 359388 628300
+rect 34765 510217 34835 510287
<< metal2 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
+rect 36395 512676 36404 512686
+rect 34654 512636 36404 512676
+rect 36395 512626 36404 512636
+rect 36464 512626 36473 512686
+rect 36169 512516 36178 512526
+rect 34650 512476 36178 512516
+rect 36169 512466 36178 512476
+rect 36238 512466 36247 512526
+rect 34650 512396 35978 512436
+rect 34654 512316 35744 512356
+rect 35938 512349 35978 512396
+rect 35704 512207 35744 512316
+rect 35928 512340 35988 512349
+rect 35928 512271 35988 512280
+rect 35694 512198 35754 512207
+rect 35694 512129 35754 512138
+rect 2486 511530 19754 511642
+rect 1685 506914 1787 506918
+rect 2486 506914 2598 511530
+rect 34765 510287 34835 510293
+rect 34835 510217 35039 510287
+rect 35109 510217 35118 510287
+rect 34765 510211 34835 510217
+rect 18912 509517 19760 509522
+rect 18908 509427 18917 509517
+rect 19007 509427 19760 509517
+rect 18912 509422 19760 509427
+rect 1680 506909 2598 506914
+rect 1680 506807 1685 506909
+rect 1787 506807 2598 506909
+rect 1680 506802 2598 506807
+rect 1685 506798 1787 506802
+rect 1705 505732 1807 505736
+rect 1700 505727 43605 505732
+rect 1700 505625 1705 505727
+rect 1807 505625 43605 505727
+rect 1700 505620 43605 505625
+rect 43717 505620 43726 505732
+rect 1705 505616 1807 505620
+rect 18917 468412 19007 468416
+rect 3243 468407 19012 468412
+rect 3243 468317 18917 468407
+rect 19007 468317 19012 468407
+rect 3243 468312 19012 468317
+rect 1781 463692 1883 463696
+rect 3243 463692 3355 468312
+rect 18917 468308 19007 468312
+rect 1776 463687 3355 463692
+rect 1776 463585 1781 463687
+rect 1883 463585 3355 463687
+rect 1776 463580 3355 463585
+rect 1781 463576 1883 463580
+rect 1815 462510 1917 462514
+rect 1810 462505 43598 462510
+rect 1810 462403 1815 462505
+rect 1917 462403 43598 462505
+rect 1810 462398 43598 462403
+rect 43710 462398 43719 462510
+rect 1815 462394 1917 462398
+rect 3066 425115 3075 425185
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+rect 3145 425120 35044 425180
+rect 35104 425120 35113 425180
+rect 3145 425115 35109 425120
+rect 36406 378398 36462 378405
+rect 2961 378338 2970 378398
+rect 3030 378396 36464 378398
+rect 3030 378340 36406 378396
+rect 36462 378340 36464 378396
+rect 3030 378338 36464 378340
+rect 36406 378331 36462 378338
+rect 2891 376066 2993 376070
+rect 2886 376061 44616 376066
+rect 2886 375959 2891 376061
+rect 2993 375959 44616 376061
+rect 2886 375954 44616 375959
+rect 44728 375954 44737 376066
+rect 2891 375950 2993 375954
+rect 36180 335178 36236 335185
+rect 2901 335118 2910 335178
+rect 2970 335176 36238 335178
+rect 2970 335120 36180 335176
+rect 36236 335120 36238 335176
+rect 2970 335118 36238 335120
+rect 36180 335111 36236 335118
+rect 2769 332844 2871 332848
+rect 2764 332839 44594 332844
+rect 2764 332737 2769 332839
+rect 2871 332737 44594 332839
+rect 2764 332732 44594 332737
+rect 44706 332732 44715 332844
+rect 2769 332728 2871 332732
+rect 3093 291894 3102 291954
+rect 3162 291952 35988 291954
+rect 3162 291896 35930 291952
+rect 35986 291896 35995 291952
+rect 3162 291894 35988 291896
+rect 3141 289622 3243 289626
+rect 3136 289617 44584 289622
+rect 3136 289515 3141 289617
+rect 3243 289515 44584 289617
+rect 3136 289510 44584 289515
+rect 44696 289510 44705 289622
+rect 3141 289506 3243 289510
+rect 35696 248930 35752 248937
+rect 3119 248870 3128 248930
+rect 3188 248928 35754 248930
+rect 3188 248872 35696 248928
+rect 35752 248872 35754 248928
+rect 3188 248870 35754 248872
+rect 35696 248863 35752 248870
+rect 3103 246600 3205 246604
+rect 3098 246595 44578 246600
+rect 3098 246493 3103 246595
+rect 3205 246493 44578 246595
+rect 3098 246488 44578 246493
+rect 44690 246488 44699 246600
+rect 3103 246484 3205 246488
rect 524 -800 636 480
rect 1706 -800 1818 480
rect 2888 -800 3000 480
@@ -523,133 +621,264 @@
rect 582068 -800 582180 480
rect 583250 -800 583362 480
<< via2 >>
-rect 357538 628057 359388 629399
+rect 36404 512626 36464 512686
+rect 36178 512466 36238 512526
+rect 35928 512280 35988 512340
+rect 35694 512138 35754 512198
+rect 35039 510217 35109 510287
+rect 18917 509427 19007 509517
+rect 1685 506807 1787 506909
+rect 1705 505625 1807 505727
+rect 43605 505620 43717 505732
+rect 18917 468317 19007 468407
+rect 1781 463585 1883 463687
+rect 1815 462403 1917 462505
+rect 43598 462398 43710 462510
+rect 3075 425115 3145 425185
+rect 35044 425120 35104 425180
+rect 2970 378338 3030 378398
+rect 36406 378340 36462 378396
+rect 2891 375959 2993 376061
+rect 44616 375954 44728 376066
+rect 2910 335118 2970 335178
+rect 36180 335120 36236 335176
+rect 2769 332737 2871 332839
+rect 44594 332732 44706 332844
+rect 3102 291894 3162 291954
+rect 35930 291896 35986 291952
+rect 3141 289515 3243 289617
+rect 44584 289510 44696 289622
+rect 3128 248870 3188 248930
+rect 35696 248872 35752 248928
+rect 3103 246493 3205 246595
+rect 44578 246488 44690 246600
<< metal3 >>
rect 16194 702300 21194 704800
rect 68194 702300 73194 704800
rect 120194 702300 125194 704800
rect 165594 702300 170594 704800
-rect 170894 700788 173094 704800
-rect 170894 690603 173094 700738
-rect -800 680242 1700 685242
-rect 170894 683764 173094 684327
-rect 173394 700786 175594 704800
+rect 170894 702300 173094 704800
+rect 173394 702300 175594 704800
rect 175894 702300 180894 704800
rect 217294 702300 222294 704800
-rect 173394 690603 175594 700736
-rect 173394 683764 175594 684327
-rect 222594 700836 224794 704800
-rect 222594 690636 224794 700786
-rect 222594 683913 224794 684360
-rect 225094 700846 227294 704800
+rect 222594 702300 224794 704800
+rect 225094 702300 227294 704800
rect 227594 702300 232594 704800
-rect 225094 690636 227294 700796
-rect 225094 683913 227294 684360
-rect 318994 649497 323994 704800
-rect 324294 701130 326494 704800
-rect 324294 690618 326494 701080
-rect 326794 701150 328994 704800
-rect 326794 694292 328994 701100
-rect 329294 694292 334294 704800
+rect 318994 702300 323994 704800
+rect 324294 702300 326494 704800
+rect 326794 702300 328994 704800
+rect 329294 702300 334294 704800
rect 413394 702300 418394 704800
rect 465394 702300 470394 704800
-rect 326794 692092 334294 694292
-rect 324294 684038 326494 684344
+rect -800 680242 1700 685242
+rect 510594 676686 515394 704800
+rect 81134 675221 84248 675227
rect -800 643842 1660 648642
-rect 318994 642983 323994 643740
-rect 329294 649497 334294 692092
-rect 329294 642983 334294 643740
-rect 510594 690564 515394 704800
rect -800 633842 1660 638642
-rect 510594 637598 515394 684332
-rect 510594 631116 515394 631780
-rect 520594 690564 525394 704800
-rect 566594 702300 571594 704800
-rect 520594 637598 525394 684332
-rect 582300 677984 584800 682984
-rect 560050 639784 560566 644584
-rect 566742 639784 584800 644584
-rect 520594 631116 525394 631780
-rect 560050 629784 560566 634584
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-rect 357470 629399 359442 629457
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-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
-rect 339960 620294 345660 620363
-rect 371099 620302 533609 620371
rect -800 559442 1660 564242
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+rect 30252 554460 30600 554466
rect -800 549442 1660 554242
-rect 339960 511642 340072 620294
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-rect 533089 619583 533095 619585
-rect 533159 619583 533165 619647
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-rect 340967 463692 341079 619212
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@@ -659,56 +888,64 @@
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-rect -800 295420 480 295532
-rect -800 294238 480 294350
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rect 583520 275140 584800 275252
rect 583520 273958 584800 274070
rect 583520 272776 584800 272888
rect 583520 271594 584800 271706
rect 583520 270412 584800 270524
rect 583520 269230 584800 269342
-rect -800 252398 480 252510
-rect -800 251216 480 251328
-rect -800 250034 480 250146
-rect -800 248852 480 248964
-rect -800 247670 480 247782
-rect -800 246488 480 246600
+rect -800 246488 2660 246600
+rect 2716 246595 3210 246600
+rect 2716 246493 3103 246595
+rect 3205 246493 3210 246595
+rect 2716 246488 3210 246493
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+rect 44478 241883 44824 246488
rect 582340 235230 584800 240030
rect 582340 225230 584800 230030
rect -800 214888 1660 219688
rect -800 204888 1660 209688
-rect 13406 191430 13991 196230
-rect 17427 191430 573605 196230
-rect 576629 191430 584800 196230
+rect 582340 191430 584800 196230
rect 582340 181430 584800 186230
rect -800 172888 1660 177688
rect -800 162888 1660 167688
@@ -775,45 +1012,31 @@
rect -800 1544 480 1656
rect 583520 1544 584800 1656
<< rmetal3 >>
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+rect 1347 505620 1403 505732
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+rect 1892 375954 1948 376066
+rect 1978 332732 2034 332844
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+rect 2660 246488 2716 246600
<< via3 >>
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+rect 90730 530374 93844 533488
<< metal4 >>
rect 165594 702300 170594 704800
rect 175894 702300 180894 704800
@@ -821,125 +1044,60 @@
rect 227594 702300 232594 704800
rect 318994 702300 323994 704800
rect 329294 702300 334294 704800
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-rect 573464 191191 576816 191430
-<< via4 >>
-rect 357559 643394 359314 649837
-rect 352028 615249 353603 617829
-rect 363412 615255 364987 617835
-rect 363414 597231 364992 601572
+rect 44232 676686 529086 678872
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+rect 11894 527744 101738 528679
<< metal5 >>
rect 165594 702300 170594 704800
rect 175894 702300 180894 704800
@@ -947,31 +1105,15 @@
rect 227594 702300 232594 704800
rect 318994 702300 323994 704800
rect 329294 702300 334294 704800
-rect 357521 649837 359350 649991
-rect 357521 643394 357559 649837
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-rect 363318 601572 365147 615255
-rect 363318 597231 363414 601572
-rect 364992 597231 365147 601572
-rect 363318 597052 365147 597231
<< comment >>
rect -100 704000 584100 704100
rect -100 0 0 704000
rect 584000 0 584100 704000
rect -100 -100 584100 0
-use user_analog_proj_example user_analog_proj_example_0
-timestamp 1639841760
-transform 1 0 345668 0 -1 627114
-box -59 -22 25476 8324
+use vco_with_fdivs vco_with_fdivs_0 ~/Desktop/GitSandboxes/caravel_user_project_analog_vco/mag/3-stage_cs-vco_dp9
+timestamp 1647616692
+transform -1 0 32535 0 1 510678
+box -2159 -1770 12877 2867
<< labels >>
flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
port 0 nsew signal bidirectional
@@ -2123,8 +2265,6 @@
port 561 nsew signal bidirectional
flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
port 562 nsew signal bidirectional
-flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
-port 563 nsew signal bidirectional
flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
port 564 nsew signal bidirectional
flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
@@ -2353,10 +2493,8 @@
port 676 nsew signal input
flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
port 677 nsew signal input
-flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
-flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
-flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
-flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
<< properties >>
string FIXED_BBOX 0 0 584000 704000
<< end >>
diff --git a/mag/user_analog_project_wrapper.spice b/mag/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..23387a4
--- /dev/null
+++ b/mag/user_analog_project_wrapper.spice
@@ -0,0 +1,550 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hd__clkbuf_8 A VGND VPWR X VNB VPB
+X0 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.65e+12p pd=1.53e+07u as=2.8e+11p ps=2.56e+06u w=1e+06u l=150000u
+X1 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=1.12e+12p ps=1.024e+07u w=1e+06u l=150000u
+X2 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=4.704e+11p pd=5.6e+06u as=6.951e+11p ps=8.35e+06u w=420000u l=150000u
+X5 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.176e+11p ps=1.4e+06u w=420000u l=150000u
+X9 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X17 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X19 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_4 A VGND VPWR X VNB VPB
+X0 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=9.1e+11p pd=7.82e+06u as=2.65e+11p ps=2.53e+06u w=1e+06u l=150000u
+X1 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=3.801e+11p pd=4.33e+06u as=2.352e+11p ps=2.8e+06u w=420000u l=150000u
+X2 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=5.6e+11p pd=5.12e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=150000u
+X6 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VPWR X VNB VPB
+X0 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=5.85e+11p pd=5.17e+06u as=2.65e+11p ps=2.53e+06u w=1e+06u l=150000u
+X1 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X2 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=2.457e+11p pd=2.85e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.134e+11p pd=1.38e+06u as=0p ps=0u w=420000u l=150000u
+X5 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt FD_v5 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb_buf 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPTgate2 5 6 5 6 Clk_In_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VPWR X VNB VPB
+X0 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=3.045e+12p pd=2.809e+07u as=5.6e+11p ps=5.12e+06u w=1e+06u l=150000u
+X1 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.24e+12p ps=2.048e+07u w=1e+06u l=150000u
+X2 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=2.352e+11p pd=2.8e+06u as=1.2789e+12p ps=1.533e+07u w=420000u l=150000u
+X8 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=9.408e+11p ps=1.12e+07u w=420000u l=150000u
+X9 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X17 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X18 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X20 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X22 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X26 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X28 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X29 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X30 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X33 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X36 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X37 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X38 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X39 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel3 sel2 vss vdd
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128_buf vsel0 vsel1 vsel2 out_div256_buf vsel3
++ vdd vss
+Xsky130_fd_sc_hd__clkbuf_8_1 sky130_fd_sc_hd__clkbuf_8_1/A vss vdd sky130_fd_sc_hd__clkbuf_8_1/X
++ vss vdd sky130_fd_sc_hd__clkbuf_8
+XFD_v2_3 FD_v2_3/Clk_In vdd vss FD_v2_4/Clk_In FD_v2
+XFD_v2_4 FD_v2_4/Clk_In vdd vss FD_v2_5/Clk_In FD_v2
+XFD_v2_5 FD_v2_5/Clk_In vdd vss FD_v2_6/Clk_In FD_v2
+XFD_v2_6 FD_v2_6/Clk_In vdd vss FD_v2_7/Clk_In FD_v2
+XFD_v2_7 FD_v2_7/Clk_In vdd vss FD_v2_8/Clk_In FD_v2
+XFD_v2_8 FD_v2_8/Clk_In vdd vss FD_v2_9/Clk_In FD_v2
+Xsky130_fd_sc_hd__clkbuf_4_0 sky130_fd_sc_hd__clkbuf_4_0/A vss vdd sky130_fd_sc_hd__clkbuf_8_0/A
++ vss vdd sky130_fd_sc_hd__clkbuf_4
+XFD_v2_9 FD_v2_9/Clk_In vdd vss FD_v2_9/Clk_Out FD_v2
+Xsky130_fd_sc_hd__clkbuf_4_1 sky130_fd_sc_hd__clkbuf_4_1/A vss vdd sky130_fd_sc_hd__clkbuf_8_1/A
++ vss vdd sky130_fd_sc_hd__clkbuf_4
+Xsky130_fd_sc_hd__clkbuf_2_0 FD_v2_8/Clk_In vss vdd sky130_fd_sc_hd__clkbuf_4_0/A
++ vss vdd sky130_fd_sc_hd__clkbuf_2
+Xsky130_fd_sc_hd__clkbuf_2_1 FD_v2_7/Clk_In vss vdd sky130_fd_sc_hd__clkbuf_4_1/A
++ vss vdd sky130_fd_sc_hd__clkbuf_2
+XFD_v5_0 out vdd vss FD_v2_1/Clk_In FD_v5
+Xsky130_fd_sc_hd__clkbuf_16_0 sky130_fd_sc_hd__clkbuf_8_1/X vss vdd sky130_fd_sc_hd__clkbuf_16_3/A
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_1 sky130_fd_sc_hd__clkbuf_8_0/X vss vdd out_div256_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_2 sky130_fd_sc_hd__clkbuf_16_3/A vss vdd out_div128_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_3 sky130_fd_sc_hd__clkbuf_16_3/A vss vdd out_div128_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel3 vsel2 vss vdd x3-stage_cs-vco_dp9
+XFD_v2_1 FD_v2_1/Clk_In vdd vss FD_v2_2/Clk_In FD_v2
+Xsky130_fd_sc_hd__clkbuf_8_0 sky130_fd_sc_hd__clkbuf_8_0/A vss vdd sky130_fd_sc_hd__clkbuf_8_0/X
++ vss vdd sky130_fd_sc_hd__clkbuf_8
+XFD_v2_2 FD_v2_2/Clk_In vdd vss FD_v2_3/Clk_In FD_v2
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xvco_with_fdivs_0 gpio_analog[9] io_out[14] io_in[17] io_in[18] io_in[19] io_out[15]
++ io_in[20] vccd1 vssa1 vco_with_fdivs
+R0 io_oeb[14] vssa1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R1 io_oeb[15] vssa1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R2 io_oeb[19] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R3 io_oeb[18] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R4 io_oeb[20] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R5 io_oeb[17] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+.ends
+
diff --git a/mag/user_analog_project_wrapper_vco.ext b/mag/user_analog_project_wrapper_vco.ext
new file mode 100644
index 0000000..46a9be0
--- /dev/null
+++ b/mag/user_analog_project_wrapper_vco.ext
@@ -0,0 +1,1495 @@
+timestamp 1647506347
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use vco_with_fdivs vco_with_fdivs_0 -1 0 39745 0 1 512921
+port "io_analog[4]" 41 329294 702300 334294 704800 m5
+port "io_analog[4]" 47 318994 702300 323994 704800 m5
+port "io_analog[5]" 42 227594 702300 232594 704800 m5
+port "io_analog[5]" 48 217294 702300 222294 704800 m5
+port "io_analog[6]" 43 175894 702300 180894 704800 m5
+port "io_analog[6]" 49 165594 702300 170594 704800 m5
+port "io_analog[4]" 41 329294 702300 334294 704800 m4
+port "io_analog[4]" 47 318994 702300 323994 704800 m4
+port "io_analog[5]" 42 227594 702300 232594 704800 m4
+port "io_analog[5]" 48 217294 702300 222294 704800 m4
+port "io_analog[6]" 43 175894 702300 180894 704800 m4
+port "io_analog[6]" 49 165594 702300 170594 704800 m4
+port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
+port "io_oeb[26]" 128 -800 1544 480 1656 m3
+port "io_in[0]" 56 583520 2726 584800 2838 m3
+port "io_out[26]" 155 -800 2726 480 2838 m3
+port "io_out[0]" 137 583520 3908 584800 4020 m3
+port "io_in[26]" 74 -800 3908 480 4020 m3
+port "io_oeb[0]" 110 583520 5090 584800 5202 m3
+port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
+port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
+port "io_oeb[25]" 127 -800 6272 480 6384 m3
+port "io_in[1]" 67 583520 7454 584800 7566 m3
+port "io_out[25]" 154 -800 7454 480 7566 m3
+port "io_out[1]" 148 583520 8636 584800 8748 m3
+port "io_in[25]" 73 -800 8636 480 8748 m3
+port "io_oeb[1]" 121 583520 9818 584800 9930 m3
+port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
+port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
+port "io_oeb[24]" 126 -800 11000 480 11112 m3
+port "io_in[2]" 75 583520 12182 584800 12294 m3
+port "io_out[24]" 153 -800 12182 480 12294 m3
+port "io_out[2]" 156 583520 13364 584800 13476 m3
+port "io_in[24]" 72 -800 13364 480 13476 m3
+port "io_oeb[2]" 129 583520 14546 584800 14658 m3
+port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
+port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
+port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
+port "io_in[3]" 76 583520 16910 584800 17022 m3
+port "gpio_analog[17]" 8 -800 16910 480 17022 m3
+port "io_out[3]" 157 583520 18092 584800 18204 m3
+port "io_oeb[3]" 130 583520 19274 584800 19386 m3
+port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
+port "io_in[4]" 77 583520 21638 584800 21750 m3
+port "io_out[4]" 158 583520 22820 584800 22932 m3
+port "io_oeb[4]" 131 583520 24002 584800 24114 m3
+port "io_oeb[23]" 125 -800 32422 480 32534 m3
+port "io_out[23]" 152 -800 33604 480 33716 m3
+port "io_in[23]" 71 -800 34786 480 34898 m3
+port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
+port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
+port "gpio_analog[16]" 7 -800 38332 480 38444 m3
+port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
+port "io_in[5]" 78 583520 48096 584800 48208 m3
+port "io_out[5]" 159 583520 49278 584800 49390 m3
+port "io_oeb[5]" 132 583520 50460 584800 50572 m3
+port "io_oeb[22]" 124 -800 75644 480 75756 m3
+port "io_out[22]" 151 -800 76826 480 76938 m3
+port "io_in[22]" 70 -800 78008 480 78120 m3
+port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
+port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
+port "gpio_analog[15]" 6 -800 81554 480 81666 m3
+port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
+port "io_in[6]" 79 583520 92754 584800 92866 m3
+port "io_out[6]" 160 583520 93936 584800 94048 m3
+port "io_oeb[6]" 133 583520 95118 584800 95230 m3
+port "io_oeb[21]" 123 -800 118866 480 118978 m3
+port "io_out[21]" 150 -800 120048 480 120160 m3
+port "io_in[21]" 69 -800 121230 480 121342 m3
+port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
+port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
+port "gpio_analog[14]" 5 -800 124776 480 124888 m3
+port "vssa1" 565 582340 136830 584800 141630 m3
+port "vssa1" 564 582340 146830 584800 151630 m3
+port "vssd2" 571 0 162888 1660 167688 m3
+port "vssd2" 570 0 172888 1660 177688 m3
+port "vssd1" 569 582340 181430 584800 186230 m3
+port "vssd1" 568 582340 191430 584800 196230 m3
+port "vdda2" 560 0 204888 1660 209688 m3
+port "vdda2" 561 0 214888 1660 219688 m3
+port "vdda1" 559 582340 225230 584800 230030 m3
+port "vdda1" 558 582340 235230 584800 240030 m3
+port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
+port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
+port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
+port "io_in[7]" 80 583520 272776 584800 272888 m3
+port "io_out[7]" 161 583520 273958 584800 274070 m3
+port "io_oeb[7]" 134 583520 275140 584800 275252 m3
+port "io_oeb[20]" 122 -800 246488 480 246600 m3
+port "io_out[20]" 149 -800 247670 480 247782 m3
+port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
+port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
+port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
+port "io_in[8]" 81 583520 317198 584800 317310 m3
+port "io_out[8]" 162 583520 318380 584800 318492 m3
+port "io_oeb[8]" 135 583520 319562 584800 319674 m3
+port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
+port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
+port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
+port "io_in[9]" 82 583520 362420 584800 362532 m3
+port "io_out[9]" 163 583520 363602 584800 363714 m3
+port "io_oeb[9]" 136 583520 364784 584800 364896 m3
+port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
+port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
+port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
+port "io_in[10]" 57 583520 408842 584800 408954 m3
+port "io_out[10]" 138 583520 410024 584800 410136 m3
+port "io_oeb[10]" 111 583520 411206 584800 411318 m3
+port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
+port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
+port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
+port "io_in[11]" 58 583520 453264 584800 453376 m3
+port "io_out[11]" 139 583520 454446 584800 454558 m3
+port "io_oeb[11]" 112 583520 455628 584800 455740 m3
+port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
+port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
+port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
+port "io_in[12]" 59 583520 497686 584800 497798 m3
+port "io_out[12]" 140 583520 498868 584800 498980 m3
+port "io_oeb[12]" 113 583520 500050 584800 500162 m3
+port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
+port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
+port "gpio_analog[13]" 4 -800 252398 480 252510 m3
+port "io_oeb[19]" 120 -800 289510 480 289622 m3
+port "io_out[19]" 147 -800 290692 480 290804 m3
+port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
+port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
+port "gpio_analog[12]" 3 -800 295420 480 295532 m3
+port "io_oeb[18]" 119 -800 332732 480 332844 m3
+port "io_out[18]" 146 -800 333914 480 334026 m3
+port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
+port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
+port "gpio_analog[11]" 2 -800 338642 480 338754 m3
+port "io_oeb[17]" 118 -800 375954 480 376066 m3
+port "io_out[17]" 145 -800 377136 480 377248 m3
+port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
+port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
+port "gpio_analog[10]" 1 -800 381864 480 381976 m3
+port "io_oeb[16]" 117 -800 419176 480 419288 m3
+port "io_out[16]" 144 -800 420358 480 420470 m3
+port "io_in[16]" 63 -800 421540 480 421652 m3
+port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
+port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
+port "io_oeb[15]" 116 -800 462398 480 462510 m3
+port "io_out[15]" 143 -800 463580 480 463692 m3
+port "io_in[15]" 62 -800 464762 480 464874 m3
+port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
+port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
+port "vdda1" 556 582340 540562 584800 545362 m3
+port "vdda1" 557 582340 550562 584800 555362 m3
+port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
+port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
+port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
+port "io_in[13]" 60 583520 587108 584800 587220 m3
+port "io_out[13]" 141 583520 588290 584800 588402 m3
+port "io_oeb[13]" 114 583520 589472 584800 589584 m3
+port "io_oeb[14]" 115 -800 505620 480 505732 m3
+port "io_out[14]" 142 -800 506802 480 506914 m3
+port "io_in[14]" 61 -800 507984 480 508096 m3
+port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
+port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
+port "vccd1" 552 582340 629784 584800 634584 m3
+port "vccd1" 552 582340 639784 584800 644584 m3
+port "io_analog[0]" 36 582300 677984 584800 682984 m3
+port "vssa2" 567 0 549442 1660 554242 m3
+port "vssa2" 566 0 559442 1660 564242 m3
+port "vccd2" 555 0 633842 1660 638642 m3
+port "vccd2" 554 0 643842 1660 648642 m3
+port "io_analog[10]" 37 0 680242 1700 685242 m3
+port "io_analog[1]" 38 566594 702300 571594 704800 m3
+port "io_analog[2]" 39 465394 702300 470394 704800 m3
+port "io_analog[3]" 40 413394 702300 418394 704800 m3
+port "io_analog[4]" 41 329294 702300 334294 704800 m3
+port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
+port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
+port "io_analog[4]" 47 318994 702300 323994 704800 m3
+port "io_analog[5]" 42 227594 702300 232594 704800 m3
+port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
+port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
+port "io_analog[5]" 48 217294 702300 222294 704800 m3
+port "io_analog[6]" 43 175894 702300 180894 704800 m3
+port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
+port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
+port "io_analog[6]" 49 165594 702300 170594 704800 m3
+port "io_analog[7]" 44 120194 702300 125194 704800 m3
+port "io_analog[8]" 45 68194 702300 73194 704800 m3
+port "io_analog[9]" 46 16194 702300 21194 704800 m3
+port "vssa1" 562 520594 702340 525394 704800 m3
+port "vssa1" 563 510594 702340 515394 704800 m3
+port "user_irq[2]" 551 583250 -800 583362 480 m2
+port "user_irq[1]" 550 582068 -800 582180 480 m2
+port "user_irq[0]" 549 580886 -800 580998 480 m2
+port "user_clock2" 548 579704 -800 579816 480 m2
+port "la_oenb[127]" 450 578522 -800 578634 480 m2
+port "la_data_out[127]" 322 577340 -800 577452 480 m2
+port "la_data_in[127]" 194 576158 -800 576270 480 m2
+port "la_oenb[126]" 449 574976 -800 575088 480 m2
+port "la_data_out[126]" 321 573794 -800 573906 480 m2
+port "la_data_in[126]" 193 572612 -800 572724 480 m2
+port "la_oenb[125]" 448 571430 -800 571542 480 m2
+port "la_data_out[125]" 320 570248 -800 570360 480 m2
+port "la_data_in[125]" 192 569066 -800 569178 480 m2
+port "la_oenb[124]" 447 567884 -800 567996 480 m2
+port "la_data_out[124]" 319 566702 -800 566814 480 m2
+port "la_data_in[124]" 191 565520 -800 565632 480 m2
+port "la_oenb[123]" 446 564338 -800 564450 480 m2
+port "la_data_out[123]" 318 563156 -800 563268 480 m2
+port "la_data_in[123]" 190 561974 -800 562086 480 m2
+port "la_oenb[122]" 445 560792 -800 560904 480 m2
+port "la_data_out[122]" 317 559610 -800 559722 480 m2
+port "la_data_in[122]" 189 558428 -800 558540 480 m2
+port "la_oenb[121]" 444 557246 -800 557358 480 m2
+port "la_data_out[121]" 316 556064 -800 556176 480 m2
+port "la_data_in[121]" 188 554882 -800 554994 480 m2
+port "la_oenb[120]" 443 553700 -800 553812 480 m2
+port "la_data_out[120]" 315 552518 -800 552630 480 m2
+port "la_data_in[120]" 187 551336 -800 551448 480 m2
+port "la_oenb[119]" 441 550154 -800 550266 480 m2
+port "la_data_out[119]" 313 548972 -800 549084 480 m2
+port "la_data_in[119]" 185 547790 -800 547902 480 m2
+port "la_oenb[118]" 440 546608 -800 546720 480 m2
+port "la_data_out[118]" 312 545426 -800 545538 480 m2
+port "la_data_in[118]" 184 544244 -800 544356 480 m2
+port "la_oenb[117]" 439 543062 -800 543174 480 m2
+port "la_data_out[117]" 311 541880 -800 541992 480 m2
+port "la_data_in[117]" 183 540698 -800 540810 480 m2
+port "la_oenb[116]" 438 539516 -800 539628 480 m2
+port "la_data_out[116]" 310 538334 -800 538446 480 m2
+port "la_data_in[116]" 182 537152 -800 537264 480 m2
+port "la_oenb[115]" 437 535970 -800 536082 480 m2
+port "la_data_out[115]" 309 534788 -800 534900 480 m2
+port "la_data_in[115]" 181 533606 -800 533718 480 m2
+port "la_oenb[114]" 436 532424 -800 532536 480 m2
+port "la_data_out[114]" 308 531242 -800 531354 480 m2
+port "la_data_in[114]" 180 530060 -800 530172 480 m2
+port "la_oenb[113]" 435 528878 -800 528990 480 m2
+port "la_data_out[113]" 307 527696 -800 527808 480 m2
+port "la_data_in[113]" 179 526514 -800 526626 480 m2
+port "la_oenb[112]" 434 525332 -800 525444 480 m2
+port "la_data_out[112]" 306 524150 -800 524262 480 m2
+port "la_data_in[112]" 178 522968 -800 523080 480 m2
+port "la_oenb[111]" 433 521786 -800 521898 480 m2
+port "la_data_out[111]" 305 520604 -800 520716 480 m2
+port "la_data_in[111]" 177 519422 -800 519534 480 m2
+port "la_oenb[110]" 432 518240 -800 518352 480 m2
+port "la_data_out[110]" 304 517058 -800 517170 480 m2
+port "la_data_in[110]" 176 515876 -800 515988 480 m2
+port "la_oenb[109]" 430 514694 -800 514806 480 m2
+port "la_data_out[109]" 302 513512 -800 513624 480 m2
+port "la_data_in[109]" 174 512330 -800 512442 480 m2
+port "la_oenb[108]" 429 511148 -800 511260 480 m2
+port "la_data_out[108]" 301 509966 -800 510078 480 m2
+port "la_data_in[108]" 173 508784 -800 508896 480 m2
+port "la_oenb[107]" 428 507602 -800 507714 480 m2
+port "la_data_out[107]" 300 506420 -800 506532 480 m2
+port "la_data_in[107]" 172 505238 -800 505350 480 m2
+port "la_oenb[106]" 427 504056 -800 504168 480 m2
+port "la_data_out[106]" 299 502874 -800 502986 480 m2
+port "la_data_in[106]" 171 501692 -800 501804 480 m2
+port "la_oenb[105]" 426 500510 -800 500622 480 m2
+port "la_data_out[105]" 298 499328 -800 499440 480 m2
+port "la_data_in[105]" 170 498146 -800 498258 480 m2
+port "la_oenb[104]" 425 496964 -800 497076 480 m2
+port "la_data_out[104]" 297 495782 -800 495894 480 m2
+port "la_data_in[104]" 169 494600 -800 494712 480 m2
+port "la_oenb[103]" 424 493418 -800 493530 480 m2
+port "la_data_out[103]" 296 492236 -800 492348 480 m2
+port "la_data_in[103]" 168 491054 -800 491166 480 m2
+port "la_oenb[102]" 423 489872 -800 489984 480 m2
+port "la_data_out[102]" 295 488690 -800 488802 480 m2
+port "la_data_in[102]" 167 487508 -800 487620 480 m2
+port "la_oenb[101]" 422 486326 -800 486438 480 m2
+port "la_data_out[101]" 294 485144 -800 485256 480 m2
+port "la_data_in[101]" 166 483962 -800 484074 480 m2
+port "la_oenb[100]" 421 482780 -800 482892 480 m2
+port "la_data_out[100]" 293 481598 -800 481710 480 m2
+port "la_data_in[100]" 165 480416 -800 480528 480 m2
+port "la_oenb[99]" 546 479234 -800 479346 480 m2
+port "la_data_out[99]" 418 478052 -800 478164 480 m2
+port "la_data_in[99]" 290 476870 -800 476982 480 m2
+port "la_oenb[98]" 545 475688 -800 475800 480 m2
+port "la_data_out[98]" 417 474506 -800 474618 480 m2
+port "la_data_in[98]" 289 473324 -800 473436 480 m2
+port "la_oenb[97]" 544 472142 -800 472254 480 m2
+port "la_data_out[97]" 416 470960 -800 471072 480 m2
+port "la_data_in[97]" 288 469778 -800 469890 480 m2
+port "la_oenb[96]" 543 468596 -800 468708 480 m2
+port "la_data_out[96]" 415 467414 -800 467526 480 m2
+port "la_data_in[96]" 287 466232 -800 466344 480 m2
+port "la_oenb[95]" 542 465050 -800 465162 480 m2
+port "la_data_out[95]" 414 463868 -800 463980 480 m2
+port "la_data_in[95]" 286 462686 -800 462798 480 m2
+port "la_oenb[94]" 541 461504 -800 461616 480 m2
+port "la_data_out[94]" 413 460322 -800 460434 480 m2
+port "la_data_in[94]" 285 459140 -800 459252 480 m2
+port "la_oenb[93]" 540 457958 -800 458070 480 m2
+port "la_data_out[93]" 412 456776 -800 456888 480 m2
+port "la_data_in[93]" 284 455594 -800 455706 480 m2
+port "la_oenb[92]" 539 454412 -800 454524 480 m2
+port "la_data_out[92]" 411 453230 -800 453342 480 m2
+port "la_data_in[92]" 283 452048 -800 452160 480 m2
+port "la_oenb[91]" 538 450866 -800 450978 480 m2
+port "la_data_out[91]" 410 449684 -800 449796 480 m2
+port "la_data_in[91]" 282 448502 -800 448614 480 m2
+port "la_oenb[90]" 537 447320 -800 447432 480 m2
+port "la_data_out[90]" 409 446138 -800 446250 480 m2
+port "la_data_in[90]" 281 444956 -800 445068 480 m2
+port "la_oenb[89]" 535 443774 -800 443886 480 m2
+port "la_data_out[89]" 407 442592 -800 442704 480 m2
+port "la_data_in[89]" 279 441410 -800 441522 480 m2
+port "la_oenb[88]" 534 440228 -800 440340 480 m2
+port "la_data_out[88]" 406 439046 -800 439158 480 m2
+port "la_data_in[88]" 278 437864 -800 437976 480 m2
+port "la_oenb[87]" 533 436682 -800 436794 480 m2
+port "la_data_out[87]" 405 435500 -800 435612 480 m2
+port "la_data_in[87]" 277 434318 -800 434430 480 m2
+port "la_oenb[86]" 532 433136 -800 433248 480 m2
+port "la_data_out[86]" 404 431954 -800 432066 480 m2
+port "la_data_in[86]" 276 430772 -800 430884 480 m2
+port "la_oenb[85]" 531 429590 -800 429702 480 m2
+port "la_data_out[85]" 403 428408 -800 428520 480 m2
+port "la_data_in[85]" 275 427226 -800 427338 480 m2
+port "la_oenb[84]" 530 426044 -800 426156 480 m2
+port "la_data_out[84]" 402 424862 -800 424974 480 m2
+port "la_data_in[84]" 274 423680 -800 423792 480 m2
+port "la_oenb[83]" 529 422498 -800 422610 480 m2
+port "la_data_out[83]" 401 421316 -800 421428 480 m2
+port "la_data_in[83]" 273 420134 -800 420246 480 m2
+port "la_oenb[82]" 528 418952 -800 419064 480 m2
+port "la_data_out[82]" 400 417770 -800 417882 480 m2
+port "la_data_in[82]" 272 416588 -800 416700 480 m2
+port "la_oenb[81]" 527 415406 -800 415518 480 m2
+port "la_data_out[81]" 399 414224 -800 414336 480 m2
+port "la_data_in[81]" 271 413042 -800 413154 480 m2
+port "la_oenb[80]" 526 411860 -800 411972 480 m2
+port "la_data_out[80]" 398 410678 -800 410790 480 m2
+port "la_data_in[80]" 270 409496 -800 409608 480 m2
+port "la_oenb[79]" 524 408314 -800 408426 480 m2
+port "la_data_out[79]" 396 407132 -800 407244 480 m2
+port "la_data_in[79]" 268 405950 -800 406062 480 m2
+port "la_oenb[78]" 523 404768 -800 404880 480 m2
+port "la_data_out[78]" 395 403586 -800 403698 480 m2
+port "la_data_in[78]" 267 402404 -800 402516 480 m2
+port "la_oenb[77]" 522 401222 -800 401334 480 m2
+port "la_data_out[77]" 394 400040 -800 400152 480 m2
+port "la_data_in[77]" 266 398858 -800 398970 480 m2
+port "la_oenb[76]" 521 397676 -800 397788 480 m2
+port "la_data_out[76]" 393 396494 -800 396606 480 m2
+port "la_data_in[76]" 265 395312 -800 395424 480 m2
+port "la_oenb[75]" 520 394130 -800 394242 480 m2
+port "la_data_out[75]" 392 392948 -800 393060 480 m2
+port "la_data_in[75]" 264 391766 -800 391878 480 m2
+port "la_oenb[74]" 519 390584 -800 390696 480 m2
+port "la_data_out[74]" 391 389402 -800 389514 480 m2
+port "la_data_in[74]" 263 388220 -800 388332 480 m2
+port "la_oenb[73]" 518 387038 -800 387150 480 m2
+port "la_data_out[73]" 390 385856 -800 385968 480 m2
+port "la_data_in[73]" 262 384674 -800 384786 480 m2
+port "la_oenb[72]" 517 383492 -800 383604 480 m2
+port "la_data_out[72]" 389 382310 -800 382422 480 m2
+port "la_data_in[72]" 261 381128 -800 381240 480 m2
+port "la_oenb[71]" 516 379946 -800 380058 480 m2
+port "la_data_out[71]" 388 378764 -800 378876 480 m2
+port "la_data_in[71]" 260 377582 -800 377694 480 m2
+port "la_oenb[70]" 515 376400 -800 376512 480 m2
+port "la_data_out[70]" 387 375218 -800 375330 480 m2
+port "la_data_in[70]" 259 374036 -800 374148 480 m2
+port "la_oenb[69]" 513 372854 -800 372966 480 m2
+port "la_data_out[69]" 385 371672 -800 371784 480 m2
+port "la_data_in[69]" 257 370490 -800 370602 480 m2
+port "la_oenb[68]" 512 369308 -800 369420 480 m2
+port "la_data_out[68]" 384 368126 -800 368238 480 m2
+port "la_data_in[68]" 256 366944 -800 367056 480 m2
+port "la_oenb[67]" 511 365762 -800 365874 480 m2
+port "la_data_out[67]" 383 364580 -800 364692 480 m2
+port "la_data_in[67]" 255 363398 -800 363510 480 m2
+port "la_oenb[66]" 510 362216 -800 362328 480 m2
+port "la_data_out[66]" 382 361034 -800 361146 480 m2
+port "la_data_in[66]" 254 359852 -800 359964 480 m2
+port "la_oenb[65]" 509 358670 -800 358782 480 m2
+port "la_data_out[65]" 381 357488 -800 357600 480 m2
+port "la_data_in[65]" 253 356306 -800 356418 480 m2
+port "la_oenb[64]" 508 355124 -800 355236 480 m2
+port "la_data_out[64]" 380 353942 -800 354054 480 m2
+port "la_data_in[64]" 252 352760 -800 352872 480 m2
+port "la_oenb[63]" 507 351578 -800 351690 480 m2
+port "la_data_out[63]" 379 350396 -800 350508 480 m2
+port "la_data_in[63]" 251 349214 -800 349326 480 m2
+port "la_oenb[62]" 506 348032 -800 348144 480 m2
+port "la_data_out[62]" 378 346850 -800 346962 480 m2
+port "la_data_in[62]" 250 345668 -800 345780 480 m2
+port "la_oenb[61]" 505 344486 -800 344598 480 m2
+port "la_data_out[61]" 377 343304 -800 343416 480 m2
+port "la_data_in[61]" 249 342122 -800 342234 480 m2
+port "la_oenb[60]" 504 340940 -800 341052 480 m2
+port "la_data_out[60]" 376 339758 -800 339870 480 m2
+port "la_data_in[60]" 248 338576 -800 338688 480 m2
+port "la_oenb[59]" 502 337394 -800 337506 480 m2
+port "la_data_out[59]" 374 336212 -800 336324 480 m2
+port "la_data_in[59]" 246 335030 -800 335142 480 m2
+port "la_oenb[58]" 501 333848 -800 333960 480 m2
+port "la_data_out[58]" 373 332666 -800 332778 480 m2
+port "la_data_in[58]" 245 331484 -800 331596 480 m2
+port "la_oenb[57]" 500 330302 -800 330414 480 m2
+port "la_data_out[57]" 372 329120 -800 329232 480 m2
+port "la_data_in[57]" 244 327938 -800 328050 480 m2
+port "la_oenb[56]" 499 326756 -800 326868 480 m2
+port "la_data_out[56]" 371 325574 -800 325686 480 m2
+port "la_data_in[56]" 243 324392 -800 324504 480 m2
+port "la_oenb[55]" 498 323210 -800 323322 480 m2
+port "la_data_out[55]" 370 322028 -800 322140 480 m2
+port "la_data_in[55]" 242 320846 -800 320958 480 m2
+port "la_oenb[54]" 497 319664 -800 319776 480 m2
+port "la_data_out[54]" 369 318482 -800 318594 480 m2
+port "la_data_in[54]" 241 317300 -800 317412 480 m2
+port "la_oenb[53]" 496 316118 -800 316230 480 m2
+port "la_data_out[53]" 368 314936 -800 315048 480 m2
+port "la_data_in[53]" 240 313754 -800 313866 480 m2
+port "la_oenb[52]" 495 312572 -800 312684 480 m2
+port "la_data_out[52]" 367 311390 -800 311502 480 m2
+port "la_data_in[52]" 239 310208 -800 310320 480 m2
+port "la_oenb[51]" 494 309026 -800 309138 480 m2
+port "la_data_out[51]" 366 307844 -800 307956 480 m2
+port "la_data_in[51]" 238 306662 -800 306774 480 m2
+port "la_oenb[50]" 493 305480 -800 305592 480 m2
+port "la_data_out[50]" 365 304298 -800 304410 480 m2
+port "la_data_in[50]" 237 303116 -800 303228 480 m2
+port "la_oenb[49]" 491 301934 -800 302046 480 m2
+port "la_data_out[49]" 363 300752 -800 300864 480 m2
+port "la_data_in[49]" 235 299570 -800 299682 480 m2
+port "la_oenb[48]" 490 298388 -800 298500 480 m2
+port "la_data_out[48]" 362 297206 -800 297318 480 m2
+port "la_data_in[48]" 234 296024 -800 296136 480 m2
+port "la_oenb[47]" 489 294842 -800 294954 480 m2
+port "la_data_out[47]" 361 293660 -800 293772 480 m2
+port "la_data_in[47]" 233 292478 -800 292590 480 m2
+port "la_oenb[46]" 488 291296 -800 291408 480 m2
+port "la_data_out[46]" 360 290114 -800 290226 480 m2
+port "la_data_in[46]" 232 288932 -800 289044 480 m2
+port "la_oenb[45]" 487 287750 -800 287862 480 m2
+port "la_data_out[45]" 359 286568 -800 286680 480 m2
+port "la_data_in[45]" 231 285386 -800 285498 480 m2
+port "la_oenb[44]" 486 284204 -800 284316 480 m2
+port "la_data_out[44]" 358 283022 -800 283134 480 m2
+port "la_data_in[44]" 230 281840 -800 281952 480 m2
+port "la_oenb[43]" 485 280658 -800 280770 480 m2
+port "la_data_out[43]" 357 279476 -800 279588 480 m2
+port "la_data_in[43]" 229 278294 -800 278406 480 m2
+port "la_oenb[42]" 484 277112 -800 277224 480 m2
+port "la_data_out[42]" 356 275930 -800 276042 480 m2
+port "la_data_in[42]" 228 274748 -800 274860 480 m2
+port "la_oenb[41]" 483 273566 -800 273678 480 m2
+port "la_data_out[41]" 355 272384 -800 272496 480 m2
+port "la_data_in[41]" 227 271202 -800 271314 480 m2
+port "la_oenb[40]" 482 270020 -800 270132 480 m2
+port "la_data_out[40]" 354 268838 -800 268950 480 m2
+port "la_data_in[40]" 226 267656 -800 267768 480 m2
+port "la_oenb[39]" 480 266474 -800 266586 480 m2
+port "la_data_out[39]" 352 265292 -800 265404 480 m2
+port "la_data_in[39]" 224 264110 -800 264222 480 m2
+port "la_oenb[38]" 479 262928 -800 263040 480 m2
+port "la_data_out[38]" 351 261746 -800 261858 480 m2
+port "la_data_in[38]" 223 260564 -800 260676 480 m2
+port "la_oenb[37]" 478 259382 -800 259494 480 m2
+port "la_data_out[37]" 350 258200 -800 258312 480 m2
+port "la_data_in[37]" 222 257018 -800 257130 480 m2
+port "la_oenb[36]" 477 255836 -800 255948 480 m2
+port "la_data_out[36]" 349 254654 -800 254766 480 m2
+port "la_data_in[36]" 221 253472 -800 253584 480 m2
+port "la_oenb[35]" 476 252290 -800 252402 480 m2
+port "la_data_out[35]" 348 251108 -800 251220 480 m2
+port "la_data_in[35]" 220 249926 -800 250038 480 m2
+port "la_oenb[34]" 475 248744 -800 248856 480 m2
+port "la_data_out[34]" 347 247562 -800 247674 480 m2
+port "la_data_in[34]" 219 246380 -800 246492 480 m2
+port "la_oenb[33]" 474 245198 -800 245310 480 m2
+port "la_data_out[33]" 346 244016 -800 244128 480 m2
+port "la_data_in[33]" 218 242834 -800 242946 480 m2
+port "la_oenb[32]" 473 241652 -800 241764 480 m2
+port "la_data_out[32]" 345 240470 -800 240582 480 m2
+port "la_data_in[32]" 217 239288 -800 239400 480 m2
+port "la_oenb[31]" 472 238106 -800 238218 480 m2
+port "la_data_out[31]" 344 236924 -800 237036 480 m2
+port "la_data_in[31]" 216 235742 -800 235854 480 m2
+port "la_oenb[30]" 471 234560 -800 234672 480 m2
+port "la_data_out[30]" 343 233378 -800 233490 480 m2
+port "la_data_in[30]" 215 232196 -800 232308 480 m2
+port "la_oenb[29]" 469 231014 -800 231126 480 m2
+port "la_data_out[29]" 341 229832 -800 229944 480 m2
+port "la_data_in[29]" 213 228650 -800 228762 480 m2
+port "la_oenb[28]" 468 227468 -800 227580 480 m2
+port "la_data_out[28]" 340 226286 -800 226398 480 m2
+port "la_data_in[28]" 212 225104 -800 225216 480 m2
+port "la_oenb[27]" 467 223922 -800 224034 480 m2
+port "la_data_out[27]" 339 222740 -800 222852 480 m2
+port "la_data_in[27]" 211 221558 -800 221670 480 m2
+port "la_oenb[26]" 466 220376 -800 220488 480 m2
+port "la_data_out[26]" 338 219194 -800 219306 480 m2
+port "la_data_in[26]" 210 218012 -800 218124 480 m2
+port "la_oenb[25]" 465 216830 -800 216942 480 m2
+port "la_data_out[25]" 337 215648 -800 215760 480 m2
+port "la_data_in[25]" 209 214466 -800 214578 480 m2
+port "la_oenb[24]" 464 213284 -800 213396 480 m2
+port "la_data_out[24]" 336 212102 -800 212214 480 m2
+port "la_data_in[24]" 208 210920 -800 211032 480 m2
+port "la_oenb[23]" 463 209738 -800 209850 480 m2
+port "la_data_out[23]" 335 208556 -800 208668 480 m2
+port "la_data_in[23]" 207 207374 -800 207486 480 m2
+port "la_oenb[22]" 462 206192 -800 206304 480 m2
+port "la_data_out[22]" 334 205010 -800 205122 480 m2
+port "la_data_in[22]" 206 203828 -800 203940 480 m2
+port "la_oenb[21]" 461 202646 -800 202758 480 m2
+port "la_data_out[21]" 333 201464 -800 201576 480 m2
+port "la_data_in[21]" 205 200282 -800 200394 480 m2
+port "la_oenb[20]" 460 199100 -800 199212 480 m2
+port "la_data_out[20]" 332 197918 -800 198030 480 m2
+port "la_data_in[20]" 204 196736 -800 196848 480 m2
+port "la_oenb[19]" 458 195554 -800 195666 480 m2
+port "la_data_out[19]" 330 194372 -800 194484 480 m2
+port "la_data_in[19]" 202 193190 -800 193302 480 m2
+port "la_oenb[18]" 457 192008 -800 192120 480 m2
+port "la_data_out[18]" 329 190826 -800 190938 480 m2
+port "la_data_in[18]" 201 189644 -800 189756 480 m2
+port "la_oenb[17]" 456 188462 -800 188574 480 m2
+port "la_data_out[17]" 328 187280 -800 187392 480 m2
+port "la_data_in[17]" 200 186098 -800 186210 480 m2
+port "la_oenb[16]" 455 184916 -800 185028 480 m2
+port "la_data_out[16]" 327 183734 -800 183846 480 m2
+port "la_data_in[16]" 199 182552 -800 182664 480 m2
+port "la_oenb[15]" 454 181370 -800 181482 480 m2
+port "la_data_out[15]" 326 180188 -800 180300 480 m2
+port "la_data_in[15]" 198 179006 -800 179118 480 m2
+port "la_oenb[14]" 453 177824 -800 177936 480 m2
+port "la_data_out[14]" 325 176642 -800 176754 480 m2
+port "la_data_in[14]" 197 175460 -800 175572 480 m2
+port "la_oenb[13]" 452 174278 -800 174390 480 m2
+port "la_data_out[13]" 324 173096 -800 173208 480 m2
+port "la_data_in[13]" 196 171914 -800 172026 480 m2
+port "la_oenb[12]" 451 170732 -800 170844 480 m2
+port "la_data_out[12]" 323 169550 -800 169662 480 m2
+port "la_data_in[12]" 195 168368 -800 168480 480 m2
+port "la_oenb[11]" 442 167186 -800 167298 480 m2
+port "la_data_out[11]" 314 166004 -800 166116 480 m2
+port "la_data_in[11]" 186 164822 -800 164934 480 m2
+port "la_oenb[10]" 431 163640 -800 163752 480 m2
+port "la_data_out[10]" 303 162458 -800 162570 480 m2
+port "la_data_in[10]" 175 161276 -800 161388 480 m2
+port "la_oenb[9]" 547 160094 -800 160206 480 m2
+port "la_data_out[9]" 419 158912 -800 159024 480 m2
+port "la_data_in[9]" 291 157730 -800 157842 480 m2
+port "la_oenb[8]" 536 156548 -800 156660 480 m2
+port "la_data_out[8]" 408 155366 -800 155478 480 m2
+port "la_data_in[8]" 280 154184 -800 154296 480 m2
+port "la_oenb[7]" 525 153002 -800 153114 480 m2
+port "la_data_out[7]" 397 151820 -800 151932 480 m2
+port "la_data_in[7]" 269 150638 -800 150750 480 m2
+port "la_oenb[6]" 514 149456 -800 149568 480 m2
+port "la_data_out[6]" 386 148274 -800 148386 480 m2
+port "la_data_in[6]" 258 147092 -800 147204 480 m2
+port "la_oenb[5]" 503 145910 -800 146022 480 m2
+port "la_data_out[5]" 375 144728 -800 144840 480 m2
+port "la_data_in[5]" 247 143546 -800 143658 480 m2
+port "la_oenb[4]" 492 142364 -800 142476 480 m2
+port "la_data_out[4]" 364 141182 -800 141294 480 m2
+port "la_data_in[4]" 236 140000 -800 140112 480 m2
+port "la_oenb[3]" 481 138818 -800 138930 480 m2
+port "la_data_out[3]" 353 137636 -800 137748 480 m2
+port "la_data_in[3]" 225 136454 -800 136566 480 m2
+port "la_oenb[2]" 470 135272 -800 135384 480 m2
+port "la_data_out[2]" 342 134090 -800 134202 480 m2
+port "la_data_in[2]" 214 132908 -800 133020 480 m2
+port "la_oenb[1]" 459 131726 -800 131838 480 m2
+port "la_data_out[1]" 331 130544 -800 130656 480 m2
+port "la_data_in[1]" 203 129362 -800 129474 480 m2
+port "la_oenb[0]" 420 128180 -800 128292 480 m2
+port "la_data_out[0]" 292 126998 -800 127110 480 m2
+port "la_data_in[0]" 164 125816 -800 125928 480 m2
+port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
+port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
+port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
+port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
+port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
+port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
+port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
+port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
+port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
+port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
+port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
+port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
+port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
+port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
+port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
+port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
+port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
+port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
+port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
+port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
+port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
+port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
+port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
+port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
+port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
+port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
+port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
+port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
+port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
+port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
+port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
+port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
+port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
+port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
+port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
+port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
+port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
+port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
+port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
+port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
+port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
+port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
+port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
+port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
+port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
+port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
+port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
+port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
+port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
+port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
+port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
+port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
+port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
+port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
+port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
+port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
+port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
+port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
+port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
+port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
+port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
+port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
+port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
+port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
+port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
+port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
+port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
+port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
+port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
+port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
+port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
+port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
+port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
+port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
+port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
+port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
+port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
+port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
+port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
+port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
+port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
+port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
+port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
+port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
+port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
+port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
+port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
+port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
+port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
+port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
+port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
+port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
+port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
+port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
+port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
+port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
+port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
+port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
+port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
+port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
+port "wbs_we_i" 677 6434 -800 6546 480 m2
+port "wbs_stb_i" 676 5252 -800 5364 480 m2
+port "wbs_cyc_i" 607 4070 -800 4182 480 m2
+port "wbs_ack_o" 574 2888 -800 3000 480 m2
+port "wb_rst_i" 573 1706 -800 1818 480 m2
+port "wb_clk_i" 572 524 -800 636 480 m2
+port "gpio_analog[8]" 16 -800 468308 480 468420 m3
+port "io_in[20]" 68 -800 248852 480 248964 m3
+port "io_in[19]" 66 -800 291874 480 291986 m3
+port "io_in[18]" 65 -800 335096 480 335208 m3
+port "io_in[17]" 64 -800 378318 480 378430 m3
+port "gpio_analog[7]" 15 -800 511530 480 511642 m3
+port "gpio_analog[9]" 17 -800 425086 480 425198 m3
+node "io_analog[4]" 0 2925 329294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2925 318994 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[5]" 0 2925 227594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[5]" 0 2925 217294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[6]" 0 2925 175894 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[6]" 0 2925 165594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2775 329294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[4]" 0 2775 318994 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[5]" 0 2775 227594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[5]" 0 2775 217294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[6]" 0 2775 175894 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[6]" 0 2775 165594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_in_3v3[0]" 1 613.728 583520 1544 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[26]" 1 613.728 -800 1544 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[0]" 1 654.539 583520 2726 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153664 2968 0 0 0 0 0 0
+node "io_out[26]" 1 613.728 -800 2726 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_out[0]" 1 613.728 583520 3908 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_in[26]" 1 613.728 -800 3908 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "io_oeb[0]" 1 613.728 583520 5090 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
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+node "wbs_adr_i[5]" 1 589.888 30074 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[4]" 1 589.888 28892 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[4]" 1 589.888 27710 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[4]" 1 589.888 26528 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[3]" 1 589.888 25346 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[3]" 1 589.888 24164 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[3]" 1 589.888 22982 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[3]" 1 589.888 21800 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[2]" 1 589.888 20618 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[2]" 1 589.888 19436 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[2]" 1 589.888 18254 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[2]" 1 589.888 17072 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[1]" 1 589.888 15890 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[1]" 1 589.888 14708 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[1]" 1 589.888 13526 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[1]" 1 589.888 12344 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[0]" 1 589.888 11162 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[0]" 1 589.888 9980 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[0]" 1 589.888 8798 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[0]" 1 589.888 7616 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_we_i" 1 589.888 6434 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_stb_i" 1 589.888 5252 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_cyc_i" 1 589.888 4070 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_ack_o" 1 589.888 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_rst_i" 1 589.888 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_clk_i" 1 589.888 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "gpio_analog[8]" 3 30775.5 -800 468308 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81300 2830 2747684 89704 1736532 58002 0 0 0 0
+node "io_in[20]" 2 133489 -800 248852 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27000 1392 16145240 536320 2909832 97226 0 0 0 0
+node "io_in[19]" 3 115335 -800 291874 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34280 1756 13595480 451328 2907672 97154 0 0 0 0
+node "io_in[18]" 3 97020.6 -800 335096 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41440 2114 10980260 364154 2953464 98680 0 0 0 0
+node "io_in[17]" 4 78756 -800 378318 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47040 2394 8380724 277546 2990712 99922 0 0 0 0
+node "gpio_analog[7]" 4 13073.7 -800 511530 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25020 1508 1459437 59652 172620 3756 0 0 0 0 0 0
+node "gpio_analog[9]" 2 57386.9 -800 425086 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39970 1282 58072 1126 12176720 180064 5633804 83122 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_in[18]" "io_in[20]" 1163.62
+cap "io_analog[6]" "io_clamp_low[2]" 525
+cap "io_analog[5]" "io_clamp_low[1]" 525
+cap "io_analog[4]" "io_clamp_low[0]" 525
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_analog[4]" "io_clamp_high[0]" 525
+cap "io_in[17]" "io_in[20]" 651.545
+cap "io_in[19]" "io_in[20]" 61128
+cap "io_clamp_low[0]" "io_clamp_high[0]" 696.36
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_in[18]" "VCCD1" 162.388
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_clamp_low[1]" "io_clamp_high[1]" 675.78
+cap "io_clamp_high[1]" "io_analog[5]" 525
+cap "io_in[17]" "VCCD1" 57.516
+cap "vssa1" "VCCD1" 47839.5
+cap "io_in[19]" "VCCD1" 267.26
+cap "io_analog[5]" "io_analog[5]" 21250
+cap "io_in[18]" "io_in[17]" 43472
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_in[18]" "io_in[19]" 65131.3
+cap "io_clamp_high[2]" "io_clamp_low[2]" 778.68
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "gpio_analog[9]" "VCCD1" 60.5
+cap "io_analog[6]" "io_clamp_high[2]" 525
+cap "io_in[19]" "io_in[17]" 1248.52
+cap "io_analog[5]" "io_analog[5]" 21250
+cap "io_in[20]" "VCCD1" 394.433
+device devres sky130_fd_pr__res_generic_m3 798 246488 799 246489 56 112 "m3_798_246488#" 0 0 "io_oeb[20]" 112 0 "VCCD1" 112 0
+device devres sky130_fd_pr__res_generic_m3 992 289510 993 289511 56 112 "m3_992_289510#" 0 0 "io_oeb[19]" 112 0 "VCCD1" 112 0
+device devres sky130_fd_pr__res_generic_m3 882 332732 883 332733 56 112 "m3_882_332732#" 0 0 "io_oeb[18]" 112 0 "VCCD1" 112 0
+device devres sky130_fd_pr__res_generic_m3 682 375954 683 375955 56 112 "m3_682_375954#" 0 0 "io_oeb[17]" 112 0 "VCCD1" 112 0
+cap "gpio_analog[8]" "vco_with_fdivs_0/m1_n1029_1423#" 1.768
+cap "vco_with_fdivs_0/m1_n1029_1423#" "gpio_analog[8]" 5.448
+cap "vssa1" "vco_with_fdivs_0/FD_v2_9/VDD" 134.867
+cap "vco_with_fdivs_0/out_div128" "vco_with_fdivs_0/m1_n1029_1423#" -38.9015
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/m1_n1029_1423#" -821.157
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/out_div128" 38.798
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/m1_n1029_1423#" -103.378
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 30.4747
+cap "vco_with_fdivs_0/FD_v2_4/GND" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/out" 48.9288
+cap "vco_with_fdivs_0/FD_v2_4/Clk_In" "vco_with_fdivs_0/FD_v2_4/GND" 150.95
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/out" 137.074
+cap "vco_with_fdivs_0/FD_v2_4/Clk_In" "vco_with_fdivs_0/FD_v2_4/VDD" 7.72888
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/FD_v2_4/GND" -201.331
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "vco_with_fdivs_0/m1_n1029_1423#" 30.4747
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/m1_n1029_1423#" -325.336
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/vctrl" 142.883
+cap "vco_with_fdivs_0/vctrl" "vco_with_fdivs_0/m1_n1029_1423#" -9.4875
+cap "vco_with_fdivs_0/FD_v5_0/Clk_Out" "vco_with_fdivs_0/m1_n1029_1423#" -189.2
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/m1_n1047_2276#" -1177.18
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/FD_v5_0/Clk_Out" 279.705
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/m1_n1047_2276#" -202.674
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/pg3" 2.88693
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd" -173.533
+cap "vco_with_fdivs_0/out" "vco_with_fdivs_0/m1_n1047_2276#" 13.338
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/FD_v2_3/Clk_Out" 75.9944
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/pg3" 36.5614
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/m1_n1047_2276#" -548.328
+cap "vco_with_fdivs_0/out" "vco_with_fdivs_0/FD_v2_4/VDD" 22.0662
+cap "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/FD_v2_3/Clk_Out" 3.88726
+cap "vssa1" "vco_with_fdivs_0/m1_n1029_1423#" -638.628
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/m1_n1047_2276#" -778.04
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/m1_n1029_1423#" -111.366
+cap "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/out" 183.107
+cap "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" 30.0605
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/out" "vco_with_fdivs_0/vss" 14.4936
+cap "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/vss" -64.0634
+cap "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vco_switch_p_3/sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd" 30.0605
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/vsel0" 23.488
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/vsel2" -50
+cap "vco_with_fdivs_0/vsel2" "vco_with_fdivs_0/vsel1" -50
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/m1_n1047_2276#" -388.388
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/vsel0" 81.004
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/m2_n2159_1638#" 25.2215
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/vsel1" 23.488
+cap "vco_with_fdivs_0/vsel0" "vco_with_fdivs_0/m2_n2159_1638#" -7.14286
+cap "vco_with_fdivs_0/vsel0" "vco_with_fdivs_0/vsel1" -16.6667
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/m2_n2159_1638#" 81.004
+cap "vco_with_fdivs_0/m1_n1029_1423#" "vco_with_fdivs_0/vsel2" 23.488
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/vsel1" 81.004
+cap "vco_with_fdivs_0/vsel0" "vco_with_fdivs_0/vsel2" -10
+cap "vco_with_fdivs_0/m1_n1047_2276#" "vco_with_fdivs_0/vsel2" 81.004
+cap "vco_with_fdivs_0/m2_n2159_1638#" "vco_with_fdivs_0/vsel1" -16.6667
+merge "vco_with_fdivs_0/VSUBS" "VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/out_div256" "gpio_analog[8]" -430.272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 352912 -3054 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/vdd" "vco_with_fdivs_0/FD_v2_4/VDD" -4725.66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -281165 -27286 0 0 0 0 0 0
+merge "vco_with_fdivs_0/FD_v2_4/VDD" "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd"
+merge "vco_with_fdivs_0/3-stage_cs-vco_dp9_0/vdd" "vco_with_fdivs_0/m1_n1029_1423#"
+merge "vco_with_fdivs_0/m1_n1029_1423#" "VCCD1"
+merge "vco_with_fdivs_0/vss" "vco_with_fdivs_0/FD_v2_4/GND" -4868.72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 195628 -24324 0 0 0 0 0 0
+merge "vco_with_fdivs_0/FD_v2_4/GND" "vco_with_fdivs_0/m1_n1047_2276#"
+merge "vco_with_fdivs_0/m1_n1047_2276#" "vssa1"
+merge "vco_with_fdivs_0/m2_n2159_1638#" "io_in[20]" -24.5576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3386 -164 10957 0 9381 0 0 0 0 0
+merge "vco_with_fdivs_0/vsel2" "io_in[19]" -107.342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -181040 -160 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/vsel1" "io_in[18]" -60.6366 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -71145 -160 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/vctrl" "gpio_analog[9]" -72.1639 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15750 -280 38896 -290 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/vsel0" "io_in[17]" -26.065 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10200 -160 0 0 0 0 0 0 0 0
+merge "vco_with_fdivs_0/out_div128" "gpio_analog[7]" -57.424 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -35360 -168 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/user_analog_project_wrapper_vco.spice b/mag/user_analog_project_wrapper_vco.spice
new file mode 100644
index 0000000..720a6ad
--- /dev/null
+++ b/mag/user_analog_project_wrapper_vco.spice
@@ -0,0 +1,440 @@
+* NGSPICE file created from user_analog_project_wrapper_vco.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt FD_v5 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb_buf 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPTgate2 5 6 5 6 Clk_In_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel3 sel2 vdd vss
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128 vsel0 vsel1 vsel2 out_div256 vss vsel3 vdd
++ VSUBS
+XFD_v2_3 FD_v2_3/Clk_In vdd vss FD_v2_4/Clk_In FD_v2
+XFD_v2_4 FD_v2_4/Clk_In vdd vss FD_v2_5/Clk_In FD_v2
+XFD_v2_5 FD_v2_5/Clk_In vdd vss FD_v2_6/Clk_In FD_v2
+XFD_v2_6 FD_v2_6/Clk_In vdd vss out_div128 FD_v2
+XFD_v2_7 out_div128 vdd vss out_div256 FD_v2
+XFD_v2_8 out_div256 vdd vss FD_v2_9/Clk_In FD_v2
+XFD_v2_9 FD_v2_9/Clk_In vdd vss FD_v2_9/Clk_Out FD_v2
+XFD_v5_0 out vdd vss FD_v2_1/Clk_In FD_v5
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel3 vsel2 vdd vss x3-stage_cs-vco_dp9
+XFD_v2_1 FD_v2_1/Clk_In vdd vss FD_v2_2/Clk_In FD_v2
+XFD_v2_2 FD_v2_2/Clk_In vdd vss FD_v2_3/Clk_In FD_v2
+.ends
+
+.subckt user_analog_project_wrapper_vco gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xvco_with_fdivs_0 gpio_analog[9] gpio_analog[7] io_in[17] io_in[18] io_in[19] gpio_analog[8]
++ vssa1 io_in[20] vccd1 VSUBS vco_with_fdivs
+R0 io_oeb[20] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R1 io_oeb[19] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R2 io_oeb[17] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R3 io_oeb[18] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+.ends
+
diff --git a/mag/vco_switch_n_v2.ext b/mag/vco_switch_n_v2.ext
new file mode 100644
index 0000000..6abd159
--- /dev/null
+++ b/mag/vco_switch_n_v2.ext
@@ -0,0 +1,87 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0 1 0 549 0 1 981
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0 1 0 549 0 1 727
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_1 0 -1 828 -1 0 607
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 0 -1 828 1 0 701
+use sky130_fd_pr__pfet_01v8_ACAZ2B XM25 0 -1 789 1 0 957
+port "in" 0 376 876 407 911 m1
+port "sel" 1 478 793 520 839 m1
+port "out" 2 927 784 985 865 m1
+port "vdd" 4 376 1080 414 1176 m1
+port "vss" 3 376 488 414 632 m1
+node "m1_656_924#" 0 5.23973 656 924 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3960 252 0 0 0 0 0 0 0 0 0 0
+node "li_560_674#" 73 595.795 560 674 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2871 304 13978 808 0 0 0 0 0 0 0 0 0 0
+node "in" 24 241.855 376 876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2040 188 27313 1456 0 0 0 0 0 0 0 0 0 0
+node "selb" 40 48.5894 576 765 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "sel" 82 300.595 478 793 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4216 384 12058 742 0 0 0 0 0 0 0 0 0 0
+node "li_610_937#" 29 3.11143 610 937 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3256 250 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 170 151.067 927 784 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16082 1014 4698 278 0 0 0 0 0 0 0 0 0 0
+node "vdd" 5970 699.298 376 1080 m1 0 0 0 0 225856 2176 0 0 9384 620 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14659 690 33284 840 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 376 488 m1 0 0 0 0 0 0 0 0 0 0 8680 566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16423 876 69470 1542 0 0 0 0 0 0 0 0 0 0
+cap "m1_656_924#" "li_560_674#" 12.5581
+cap "in" "vdd" 305.745
+cap "vdd" "selb" 25.6024
+cap "in" "li_560_674#" 69.4985
+cap "li_610_937#" "out" 5.06639
+cap "selb" "li_560_674#" 19.4464
+cap "vdd" "out" 119.292
+cap "sel" "vdd" 44.249
+cap "li_560_674#" "out" 3.5
+cap "m1_656_924#" "in" 96.4286
+cap "sel" "li_560_674#" 129.263
+cap "in" "selb" 23.1304
+cap "vdd" "li_610_937#" 68.7837
+cap "m1_656_924#" "sel" 29.6703
+cap "in" "out" 118.361
+cap "selb" "out" 11.234
+cap "in" "sel" 524.804
+cap "sel" "selb" 73.7852
+cap "vdd" "li_560_674#" 15.6432
+cap "m1_656_924#" "li_610_937#" 36.5189
+cap "sel" "out" 33.5213
+cap "m1_656_924#" "vdd" 62.6389
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" 44.7292
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" 24.9046
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" 72.3306
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 48.4129
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" 30.674
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" 137.365
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" 10.0179
+cap "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" 23.393
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" -15.68
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" -12.8826
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" 9.62368
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 49.2705
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" -34.8758
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" 21.0908
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" 51.1319
+merge "XM25/a_n33_67#" "m1_656_924#" -153.269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3273 -608 -2668 -208 0 0 0 0 0 0 0 0 0 0
+merge "m1_656_924#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n18_n99#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_15_n96#"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_15_n96#" "li_560_674#"
+merge "li_560_674#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "selb"
+merge "selb" "li_610_937#"
+merge "XM25/a_18_n108#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" -34.4963 0 0 0 0 0 0 0 0 -4872 -284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3662 -418 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_n76_n73#" "out"
+merge "XM25/a_n76_n108#" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" -78.8077 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2040 -188 -1224 -290 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "in"
+merge "XM25/w_n112_n170#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#" -399.882 0 0 0 0 -133294 -2306 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "vdd"
+merge "XM25/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" -117.459 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3128 -320 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/VSUBS" "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_18_n73#"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_1/a_18_n73#" "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS" "vss"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" -127.685 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 -2006 -254 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" "sel"
+merge "sel" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#"
diff --git a/mag/vco_switch_p.ext b/mag/vco_switch_p.ext
new file mode 100644
index 0000000..b142e4d
--- /dev/null
+++ b/mag/vco_switch_p.ext
@@ -0,0 +1,75 @@
+timestamp 1647613837
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_hvt_N83GLL sky130_fd_pr__pfet_01v8_hvt_N83GLL_0 1 0 549 0 1 981
+use sky130_fd_pr__pfet_01v8_ACAZ2B_v2 sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 0 -1 789 1 0 957
+use sky130_fd_pr__pfet_01v8_5YXW2B sky130_fd_pr__pfet_01v8_5YXW2B_0 0 -1 825 1 0 1051
+use sky130_fd_pr__nfet_01v8_M34CP3 sky130_fd_pr__nfet_01v8_M34CP3_0 1 0 549 0 1 727
+use sky130_fd_pr__nfet_01v8_HGTGXE_v2 sky130_fd_pr__nfet_01v8_HGTGXE_v2_0 0 -1 828 1 0 701
+port "in" 0 376 876 407 911 m1
+port "out" 2 927 784 985 865 m1
+port "sel" 1 478 793 520 839 m1
+port "vdd" 4 376 1080 414 1176 nw
+port "vss" 3 376 488 414 632 m1
+node "in" 24 221.558 376 876 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2040 188 27313 1456 0 0 0 0 0 0 0 0 0 0
+node "selb" 40 48.2225 576 765 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3808 292 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_610_903#" 29 3.63303 610 903 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3293 252 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 170 147.767 927 784 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16082 1014 4698 278 0 0 0 0 0 0 0 0 0 0
+node "sel" 306 383.732 478 793 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4572 276 0 0 16660 1184 25196 1532 0 0 0 0 0 0 0 0 0 0
+node "vdd" 6009 699.298 376 1080 nw 0 0 0 0 225856 2176 0 0 9384 620 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10540 688 47015 1254 0 0 0 0 0 0 0 0 0 0
+substrate "vss" 0 0 376 488 m1 0 0 0 0 0 0 0 0 0 0 8228 552 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9418 622 65270 1442 0 0 0 0 0 0 0 0 0 0
+cap "in" "out" 118.361
+cap "out" "li_610_903#" 5.0875
+cap "vdd" "out" 119.292
+cap "selb" "out" 11.234
+cap "vdd" "in" 332.708
+cap "selb" "in" 23.1304
+cap "out" "sel" 38.489
+cap "in" "sel" 730.084
+cap "vdd" "li_610_903#" 65.4914
+cap "vdd" "selb" 25.283
+cap "sel" "li_610_903#" 24.4665
+cap "vdd" "sel" 634.013
+cap "selb" "sel" 84.7852
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" 100.345
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 39.2136
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 8.49929
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" 3.85567
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" 23.2405
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" -31.6358
+cap "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 67.4141
+cap "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" 150.695
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" -35.181
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 72.3306
+cap "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 27.0717
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" 10.0179
+cap "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 34.8277
+cap "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" 227.173
+cap "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" 4.8755
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_18_n73#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" -78.8077 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2040 -188 -1224 -290 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n76_n108#" "in"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n76_n73#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n76_n72#" -17.0247 0 0 0 0 0 0 0 0 0 0 -8352 -404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5702 -538 -6624 -380 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n76_n72#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#"
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_18_n108#" "out"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_15_n96#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -999 -338 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/a_n68_67#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_15_n100#" "selb"
+merge "selb" "li_610_903#"
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_18_n72#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/w_n112_n134#" -579.978 0 0 0 0 -193326 -3290 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 -3456 -336 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/w_n112_n134#" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/w_n112_n170#"
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/w_n112_n170#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/w_n109_n136#" "vdd"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/a_n18_n99#" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" -124.952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -132 0 0 -2346 -274 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_56#" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/a_n15_n132#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#"
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/a_n18_n98#" "sel"
+merge "sky130_fd_pr__nfet_01v8_HGTGXE_v2_0/VSUBS" "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS" -44.6487 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/VSUBS" "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#"
+merge "sky130_fd_pr__nfet_01v8_M34CP3_0/a_n73_n96#" "sky130_fd_pr__pfet_01v8_5YXW2B_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_5YXW2B_0/VSUBS" "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_ACAZ2B_v2_0/VSUBS" "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_hvt_N83GLL_0/VSUBS" "vss"
diff --git a/mag/vco_with_fdivs.ext b/mag/vco_with_fdivs.ext
new file mode 100644
index 0000000..2c33848
--- /dev/null
+++ b/mag/vco_with_fdivs.ext
@@ -0,0 +1,874 @@
+timestamp 1647616692
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use 3-stage_cs-vco_dp9 3-stage_cs-vco_dp9_0 1 0 25 0 1 226
+use FD_v2 FD_v2_2 -1 0 5933 0 -1 -29
+use FD_v2 FD_v2_3 -1 0 4118 0 -1 -29
+use FD_v2 FD_v2_4 1 0 2167 0 1 -83
+use FD_v2 FD_v2_5 1 0 3982 0 1 -83
+use FD_v2 FD_v2_8 -1 0 5933 0 -1 -1491
+use FD_v2 FD_v2_9 -1 0 4118 0 -1 -1491
+use FD_v5 FD_v5_0 1 0 2617 0 1 1451
+use FD_v2 FD_v2_7 -1 0 7748 0 -1 -1491
+use FD_v2 FD_v2_6 1 0 5797 0 1 -83
+use FD_v2 FD_v2_1 -1 0 7748 0 -1 -29
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_3 1 0 8560 0 -1 687
+use sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_8_1 1 0 9408 0 1 -657
+use sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_8_0 1 0 9408 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_4_1 1 0 8856 0 1 -657
+use sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_4_0 1 0 8856 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_2_1 1 0 8488 0 1 -657
+use sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_2_0 1 0 8488 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_0 1 0 10400 0 1 -657
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_1 1 0 10400 0 -1 -962
+use sky130_fd_sc_hd__clkbuf_16 sky130_fd_sc_hd__clkbuf_16_2 -1 0 12240 0 -1 687
+port "vctrl" 1 -1702 -522 -1659 -476 m1
+port "vsel3" 8 -1161 1449 -1138 1475 m1
+port "vsel2" 7 -1248 1534 -1225 1560 m1
+port "vsel1" 6 -1330 1605 -1307 1631 m1
+port "vsel0" 5 -1407 1757 -1384 1783 m1
+port "vdd" 3 1732 2426 1789 2460 m1
+port "vss" 4 1994 2687 2051 2721 m1
+port "out_div256_buf" 9 12793 -1239 12853 -1185 m2
+port "out_div128_buf" 2 12803 879 12857 931 m2
+node "m2_n2159_1638#" 3 519.697 -2159 1638 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43240 2242 0 0 0 0 0 0 0 0
+node "m2_n2159_1718#" 3 486.537 -2159 1718 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40400 2100 0 0 0 0 0 0 0 0
+node "m2_n2159_1798#" 3 456.177 -2159 1798 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36840 1922 0 0 0 0 0 0 0 0
+node "m2_n2159_1958#" 3 511.013 -2159 1958 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33440 1752 0 0 0 0 0 0 0 0
+node "vctrl" 0 134.133 -1702 -522 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4324 280 0 0 0 0 0 0 0 0 0 0
+node "m1_n2159_n461#" 1 295.61 -2159 -461 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30520 1012 0 0 0 0 0 0 0 0 0 0
+node "m1_2161_286#" 2 493.837 2161 286 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12280 656 10008 568 50596 1802 0 0 0 0 0 0
+node "m1_7680_300#" 4 740.571 7680 300 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65090 2922 0 0 0 0 0 0 0 0 0 0
+node "m1_n889_1476#" 0 84.687 -889 1476 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 384 0 0 0 0 0 0 0 0 0 0
+node "vsel3" 0 25.6106 -1161 1449 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel2" 0 25.6106 -1248 1534 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel1" 0 25.6106 -1330 1605 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 924 122 0 0 0 0 0 0 0 0 0 0
+node "vsel0" 0 24.3208 -1407 1757 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 832 116 0 0 0 0 0 0 0 0 0 0
+node "vdd" 0 46.009 1732 2426 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2660 216 0 0 0 0 0 0 0 0 0 0
+node "vss" 0 86.9735 1994 2687 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2660 216 0 0 0 0 0 0 0 0 0 0
+node "out_div256_buf" 14 489.358 12793 -1239 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7134 338 12099 440 73021 1908 0 0 0 0 0 0 0 0
+node "li_10187_n1210#" 122 145.666 10187 -1210 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 12220 736 0 0 0 0 0 0 0 0 0 0
+node "li_9326_n1210#" 72 88.6247 9326 -1210 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 7656 476 0 0 0 0 0 0 0 0 0 0
+node "li_8782_n1210#" 72 108.473 8782 -1210 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 9144 572 0 0 0 0 0 0 0 0 0 0
+node "li_8588_n1221#" 21 1383.2 8588 -1221 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2304 192 11450 630 180493 6358 74372 2710 0 0 0 0 0 0
+node "li_10185_n451#" 122 311.164 10185 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 408 12356 744 0 0 0 0 0 0 0 0 0 0
+node "li_9325_n451#" 72 194.218 9325 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 7240 460 0 0 0 0 0 0 0 0 0 0
+node "li_8789_n451#" 72 221.635 8789 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2312 272 8770 550 0 0 0 0 0 0 0 0 0 0
+node "li_8577_n451#" 18 1004.68 8577 -451 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 58190 3474 0 0 0 0 0 0 0 0 0 0
+node "li_8587_462#" 239 809.308 8587 462 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6902 746 86706 4372 172163 8076 0 0 0 0 0 0 0 0
+node "out_div128_buf" 37 2826.11 12803 879 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22222 670 26208 648 238352 5886 62624 1534 0 0 0 0 0 0
+node "out" 216 332.429 1728 1040 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28280 1494 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_7680_n1770#" 59765 55333 7680 -1770 nw 0 0 0 0 5874215 21806 0 0 250240 14856 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 246908 14660 3225826 57614 4184598 94244 1114300 25460 0 0 0 0 0 0
+substrate "a_8547_n771#" 0 0 8547 -771 ppd 0 0 0 0 0 0 0 0 0 0 247316 14684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243712 14472 1651869 44136 3629178 82228 978840 22452 0 0 0 0 0 0
+cap "w_7680_n1770#" "li_8782_n1210#" 146.832
+cap "m1_n889_1476#" "vsel3" 0.914634
+cap "w_7680_n1770#" "m1_2161_286#" 150.819
+cap "li_9326_n1210#" "li_8782_n1210#" 9.85063
+cap "w_7680_n1770#" "li_8577_n451#" 64.3486
+cap "m2_n2159_1958#" "m2_n2159_1798#" 348.333
+cap "m1_n889_1476#" "vsel2" 4.44611
+cap "li_8588_n1221#" "li_8782_n1210#" 29.2195
+cap "li_8587_462#" "out_div128_buf" 30.4924
+cap "m2_n2159_1718#" "m2_n2159_1798#" 1151.25
+cap "w_7680_n1770#" "out_div256_buf" 464.121
+cap "w_7680_n1770#" "li_9325_n451#" 22.2458
+cap "w_7680_n1770#" "li_10185_n451#" 40.6135
+cap "w_7680_n1770#" "m2_n2159_1638#" 481.971
+cap "m2_n2159_1718#" "vsel0" 16.6513
+cap "w_7680_n1770#" "li_9326_n1210#" 128.186
+cap "w_7680_n1770#" "vsel3" 46.3848
+cap "m1_n2159_n461#" "vctrl" 3
+cap "li_8789_n451#" "li_8577_n451#" 24.7995
+cap "m2_n2159_1958#" "m2_n2159_1638#" 149.286
+cap "w_7680_n1770#" "m2_n2159_1958#" 75.34
+cap "w_7680_n1770#" "li_8588_n1221#" 2063.08
+cap "li_8789_n451#" "li_9325_n451#" 9.76017
+cap "m2_n2159_1718#" "m2_n2159_1638#" 1262.5
+cap "m2_n2159_1718#" "w_7680_n1770#" 300.375
+cap "w_7680_n1770#" "out_div128_buf" 177.017
+cap "w_7680_n1770#" "li_8587_462#" 7142.79
+cap "m2_n2159_1718#" "m2_n2159_1958#" 209
+cap "li_8587_462#" "m1_7680_300#" 78.0189
+cap "w_7680_n1770#" "li_10187_n1210#" 202.557
+cap "w_7680_n1770#" "m1_n889_1476#" 44.1
+cap "m2_n2159_1798#" "m2_n2159_1638#" 383.75
+cap "w_7680_n1770#" "m2_n2159_1798#" 219.814
+cap "w_7680_n1770#" "m1_n2159_n461#" 68.3125
+cap "w_7680_n1770#" "li_8789_n451#" 27.9986
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/sel1" 112.371
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "3-stage_cs-vco_dp9_0/sel1" 60.8111
+cap "3-stage_cs-vco_dp9_0/vctrl" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 11.6418
+cap "3-stage_cs-vco_dp9_0/vctrl" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" 1386.29
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 205.873
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" 60.8646
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/sel2" 140.584
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/sel" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" 159.615
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "3-stage_cs-vco_dp9_0/sel2" 60.8249
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/sel3" 666.667
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/in" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" 23.2836
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "3-stage_cs-vco_dp9_0/sel3" -1.74933
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/sel" 379.429
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_1/sel" 144.539
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_3/sel" 314.227
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" "FD_v2_4/Clk_In" 34.7407
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/in" 11.6418
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/sel" 2.85714
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "FD_v2_4/Clk_In" 8.96197
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" 19.4813
+cap "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" "3-stage_cs-vco_dp9_0/ng3" 7.44363
+cap "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v2_4/Clkb" 15.0072
+cap "FD_v2_9/7" "FD_v2_4/Clk_In" 10.0581
+cap "FD_v2_4/GND" "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 13.9615
+cap "FD_v2_4/3" "FD_v2_3/VDD" 4.60465
+cap "FD_v2_4/GND" "FD_v2_9/2" 5.44323
+cap "FD_v2_3/VDD" "FD_v2_4/Clk_In" 10.7368
+cap "FD_v2_4/2" "FD_v2_4/GND" 6
+cap "FD_v2_4/GND" "FD_v2_4/6" 14.8618
+cap "FD_v2_4/3" "FD_v2_9/2" 0.68546
+cap "FD_v2_9/4" "FD_v2_4/Clkb" 2.51825
+cap "FD_v2_3/VDD" "FD_v2_4/5" 5.78133
+cap "FD_v2_9/4" "FD_v2_4/GND" 17.7273
+cap "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v2_4/5" 2.60252
+cap "FD_v2_4/4" "FD_v2_4/GND" 26.0114
+cap "FD_v2_9/6" "FD_v2_4/GND" 37.7137
+cap "FD_v2_4/Clkb" "FD_v2_9/5" 2.60252
+cap "FD_v2_4/2" "FD_v2_3/VDD" 2.77806
+cap "FD_v2_4/GND" "FD_v2_9/5" 23.9658
+cap "FD_v2_4/GND" "FD_v2_4/Clkb" 26.5514
+cap "FD_v2_4/6" "FD_v2_3/VDD" 3.15689
+cap "FD_v2_9/Clk_Out" "FD_v2_4/GND" 5.17315
+cap "FD_v2_9/6" "FD_v2_4/3" 0.172324
+cap "FD_v2_9/6" "FD_v2_4/Clk_In" 15.4867
+cap "FD_v2_4/GND" "FD_v2_4/3" 11.5455
+cap "FD_v2_4/Clkb" "FD_v2_9/7" 5.79832
+cap "FD_v2_4/GND" "FD_v2_4/Clk_In" 133.008
+cap "FD_v2_4/4" "FD_v2_3/VDD" 9.09184
+cap "FD_v2_4/GND" "FD_v2_9/7" 12.0649
+cap "FD_v2_4/GND" "FD_v2_4/5" 23.9658
+cap "FD_v2_4/GND" "FD_v2_3/VDD" 2.55831
+cap "FD_v2_4/4" "FD_v2_9/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 2.51825
+cap "FD_v2_9/3" "FD_v2_4/6" 0.172324
+cap "FD_v2_5/Clkb" "FD_v2_4/7" 4.45238
+cap "FD_v2_8/5" "FD_v2_4/GND" 3.5625
+cap "FD_v2_4/GND" "FD_v2_8/7" 25.8788
+cap "FD_v2_4/2" "FD_v2_4/GND" 5.44323
+cap "FD_v2_5/Clkb" "FD_v2_4/GND" 29.5029
+cap "FD_v2_4/GND" "FD_v2_8/6" 37.7137
+cap "FD_v2_5/Clkb" "FD_v2_8/7" 5.79832
+cap "FD_v2_8/Clk_Out" "FD_v2_8/VDD" 69.1959
+cap "FD_v2_8/Clk_Out" "FD_v2_9/Clkb" 71.7391
+cap "FD_v2_5/4" "FD_v2_2/VDD" 8.54464
+cap "FD_v2_4/7" "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 19.5299
+cap "FD_v2_8/Clk_Out" "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.89315
+cap "FD_v2_4/6" "FD_v2_4/GND" 22.8519
+cap "FD_v2_8/Clk_Out" "FD_v2_9/3" 34.375
+cap "FD_v2_4/GND" "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 6
+cap "FD_v2_5/3" "FD_v2_4/GND" 11.5455
+cap "FD_v2_4/Clk_Out" "FD_v2_4/7" 67.426
+cap "FD_v2_5/3" "FD_v2_8/6" 0.172324
+cap "FD_v2_8/VDD" "FD_v2_9/Clkb" 37.8022
+cap "FD_v2_4/Clk_Out" "FD_v2_4/GND" 76.8732
+cap "FD_v2_4/Clk_Out" "FD_v2_8/7" 10.0581
+cap "FD_v2_8/Clk_Out" "FD_v2_4/7" 10.0581
+cap "FD_v2_4/Clk_Out" "FD_v2_5/Clkb" 40.8913
+cap "FD_v2_4/Clk_Out" "FD_v2_8/6" 15.4867
+cap "FD_v2_2/VDD" "FD_v2_4/7" 2.77806
+cap "FD_v2_8/Clk_Out" "FD_v2_4/GND" 76.8732
+cap "FD_v2_8/Clk_Out" "FD_v2_8/7" 80.363
+cap "FD_v2_8/Clk_Out" "FD_v2_8/6" 18.7444
+cap "FD_v2_2/VDD" "FD_v2_4/2" 0.126276
+cap "FD_v2_4/Clk_Out" "FD_v2_4/6" 15.4398
+cap "FD_v2_4/Clk_Out" "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 5.89315
+cap "FD_v2_8/2" "FD_v2_4/GND" 5.44323
+cap "FD_v2_4/7" "FD_v2_9/Clkb" 5.79832
+cap "FD_v2_4/Clk_Out" "FD_v2_5/3" 19.5938
+cap "FD_v2_5/4" "FD_v2_4/GND" 24.8295
+cap "FD_v2_8/Clk_Out" "FD_v2_4/6" 15.4867
+cap "FD_v2_8/VDD" "FD_v2_8/7" 14.5814
+cap "FD_v2_9/Clkb" "FD_v2_4/GND" 29.5029
+cap "FD_v2_9/Clkb" "FD_v2_8/7" 4.45238
+cap "FD_v2_2/VDD" "FD_v2_4/6" 9.59694
+cap "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_4/GND" 6
+cap "FD_v2_9/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_8/7" 22.4939
+cap "FD_v2_2/VDD" "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 2.77806
+cap "FD_v2_5/3" "FD_v2_2/VDD" 4.60465
+cap "FD_v2_9/3" "FD_v2_4/GND" 11.5455
+cap "FD_v2_9/3" "FD_v2_4/2" 0.68546
+cap "FD_v2_8/2" "FD_v2_5/3" 0.68546
+cap "FD_v2_4/GND" "FD_v2_9/4" 8.28409
+cap "FD_v2_4/Clk_Out" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_4/7" "FD_v2_4/GND" 25.8788
+cap "FD_v2_5/7" "FD_v2_8/Clkb" 5.79832
+cap "FD_v2_5/6" "FD_v2_2/VDD" 12.7538
+cap "FD_v2_8/Clk_In" "FD_v2_5/6" 15.4867
+cap "FD_v2_5/5" "FD_v2_2/VDD" 5.78133
+cap "FD_v2_5/4" "FD_v2_2/VDD" 0.547194
+cap "FD_v2_8/Clk_In" "FD_v2_5/GND" 57.3743
+cap "FD_v2_6/Clkb" "FD_v2_7/7" 5.79832
+cap "FD_v2_8/Clkb" "FD_v2_5/a_971_n597#" 15.0072
+cap "FD_v2_5/Clk_Out" "FD_v2_7/7" 10.0581
+cap "FD_v2_8/Clkb" "FD_v2_8/VDD" 37.8022
+cap "FD_v2_7/6" "FD_v2_5/GND" 9.55283
+cap "FD_v2_5/a_971_n597#" "FD_v2_8/5" 2.60252
+cap "FD_v2_6/Clkb" "FD_v2_5/Clk_Out" 40.8913
+cap "FD_v2_5/2" "FD_v2_8/3" 0.68546
+cap "FD_v2_7/6" "FD_v2_8/Clk_In" 18.7444
+cap "FD_v2_6/Clkb" "FD_v2_5/7" 4.45238
+cap "FD_v2_5/Clk_Out" "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 5.89315
+cap "FD_v2_5/GND" "FD_v2_8/2" 6
+cap "FD_v2_5/7" "FD_v2_5/Clk_Out" 67.426
+cap "FD_v2_8/Clkb" "FD_v2_5/5" 2.60252
+cap "FD_v2_5/4" "FD_v2_8/Clkb" 2.51825
+cap "FD_v2_7/7" "FD_v2_8/VDD" 14.5814
+cap "FD_v2_8/Clkb" "FD_v2_5/GND" 43.4645
+cap "FD_v2_5/7" "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" 19.5299
+cap "FD_v2_8/3" "FD_v2_5/6" 0.172324
+cap "FD_v2_5/Clk_Out" "FD_v2_6/3" 19.5938
+cap "FD_v2_8/3" "FD_v2_5/GND" 11.5455
+cap "FD_v2_8/Clk_In" "FD_v2_8/2" 3.9507
+cap "FD_v2_5/GND" "FD_v2_8/5" 20.4033
+cap "FD_v2_8/Clkb" "FD_v2_8/Clk_In" 71.7391
+cap "FD_v2_8/4" "FD_v2_5/a_971_n597#" 2.51825
+cap "FD_v2_7/7" "FD_v2_5/GND" 25.8788
+cap "FD_v2_8/3" "FD_v2_8/Clk_In" 34.375
+cap "FD_v2_5/Clk_Out" "FD_v2_5/6" 15.4398
+cap "FD_v2_6/Clkb" "FD_v2_5/GND" 29.5029
+cap "FD_v2_5/Clk_Out" "FD_v2_5/GND" 64.3867
+cap "FD_v2_7/7" "FD_v2_8/Clk_In" 72.6071
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_5/GND" 6
+cap "FD_v2_5/7" "FD_v2_5/GND" 25.8788
+cap "FD_v2_5/Clk_Out" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_8/4" "FD_v2_5/GND" 26.0114
+cap "FD_v2_6/3" "FD_v2_5/GND" 5.17051
+cap "FD_v2_5/GND" "FD_v2_5/a_971_n597#" 13.9615
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_7/6" "FD_v2_5/Clk_Out" 2.78372
+cap "FD_v2_5/7" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_5/7" "FD_v2_8/Clk_In" 10.0581
+cap "FD_v2_7/7" "FD_v2_8/2" 22.4939
+cap "FD_v2_5/2" "FD_v2_5/GND" 5.44323
+cap "FD_v2_6/3" "FD_v2_2/VDD" 0.287791
+cap "FD_v2_8/Clkb" "FD_v2_7/7" 4.45238
+cap "FD_v2_8/Clk_In" "FD_v2_8/VDD" 176.155
+cap "FD_v2_7/6" "FD_v2_6/3" 0.172324
+cap "FD_v2_5/GND" "FD_v2_5/6" 37.7137
+cap "FD_v2_5/2" "FD_v2_2/VDD" 0.126276
+cap "FD_v2_5/GND" "FD_v2_5/5" 23.9658
+cap "FD_v2_5/4" "FD_v2_5/GND" 1.18182
+cap "FD_v2_5/GND" "FD_v2_7/Clkb" 19.132
+cap "FD_v2_5/GND" "FD_v2_6/6" 37.7137
+cap "FD_v2_5/GND" "FD_v2_5/Clk_Out" 12.4865
+cap "FD_v2_7/Clk_In" "FD_v2_7/Clkb" 6.23494
+cap "FD_v2_6/6" "FD_v2_7/Clk_In" 15.4867
+cap "FD_v2_6/4" "FD_v2_7/Clkb" 2.51825
+cap "FD_v2_5/GND" "FD_v2_7/2" 11.4432
+cap "FD_v2_5/Clk_Out" "FD_v2_7/6" 12.703
+cap "FD_v2_6/Clkb" "FD_v2_7/Clkb" 15.0072
+cap "FD_v2_7/Clk_In" "FD_v2_7/2" 0.566547
+cap "FD_v2_6/5" "FD_v2_7/Clkb" 2.60252
+cap "FD_v2_5/GND" "FD_v2_7/3" 11.5455
+cap "FD_v2_5/GND" "FD_v2_6/7" 12.0649
+cap "FD_v2_2/VDD" "FD_v2_6/2" 0.126276
+cap "FD_v2_6/7" "FD_v2_7/Clk_In" 23.7481
+cap "FD_v2_5/GND" "FD_v2_7/6" 28.1609
+cap "FD_v2_5/GND" "FD_v2_7/Clk_In" 39.3068
+cap "FD_v2_5/GND" "FD_v2_6/4" 26.0114
+cap "FD_v2_2/VDD" "FD_v2_6/6" 12.7538
+cap "FD_v2_6/3" "FD_v2_7/2" 0.68546
+cap "FD_v2_5/GND" "FD_v2_6/Clkb" 13.9615
+cap "FD_v2_5/GND" "FD_v2_7/4" 26.0114
+cap "FD_v2_5/GND" "FD_v2_6/5" 23.9658
+cap "FD_v2_5/GND" "FD_v2_6/3" 6.375
+cap "FD_v2_7/5" "FD_v2_5/GND" 23.9658
+cap "FD_v2_7/4" "FD_v2_6/Clkb" 2.51825
+cap "FD_v2_2/VDD" "FD_v2_6/7" 2.77806
+cap "FD_v2_5/Clk_Out" "FD_v2_6/2" -5.68434e-14
+cap "FD_v2_2/VDD" "FD_v2_6/4" 9.09184
+cap "FD_v2_7/5" "FD_v2_6/Clkb" 2.60252
+cap "FD_v2_6/2" "FD_v2_7/3" 0.68546
+cap "FD_v2_2/VDD" "FD_v2_6/5" 5.78133
+cap "FD_v2_5/GND" "FD_v2_6/2" 5.44323
+cap "FD_v2_6/6" "FD_v2_7/3" 0.172324
+cap "FD_v2_2/VDD" "FD_v2_6/3" 4.31686
+cap "FD_v2_6/7" "FD_v2_7/Clkb" 5.79832
+cap "FD_v2_7/Clkb" "FD_v2_7/Clk_In" 6.23494
+cap "sky130_fd_sc_hd__clkbuf_4_0/A" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 50.9448
+cap "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_0/A" 30.778
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 42.3299
+cap "FD_v2_7/VDD" "FD_v2_7/GND" -5.8028
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "FD_v2_7/GND" 64.549
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "FD_v2_7/GND" 66.7364
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_4_0/A" 58.4298
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_2_0/A" 13.9379
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_4_1/A" 8.38944
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 48.4715
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" -106.4
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_4_0/A" 5.78465
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_2_0/A" -34.3099
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_4_0/A" 1.98847
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_0/A" 16.7895
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/A" 307.734
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "FD_v2_7/GND" 3.25789
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "FD_v2_7/Clk_In" 16.7895
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 2.01546
+cap "FD_v2_6/7" "FD_v2_7/Clk_In" 13.6899
+cap "sky130_fd_sc_hd__clkbuf_4_0/A" "sky130_fd_sc_hd__clkbuf_2_0/A" 16.9745
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "FD_v2_7/Clk_In" 35.2546
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "FD_v2_7/GND" 3.25789
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 3.97695
+cap "FD_v2_7/GND" "FD_v2_7/Clk_In" 205.119
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/A" 5.21801
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 9.29272
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 72.0941
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_8_0/A" 5.81607
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 2.01546
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "FD_v2_7/GND" 79.5029
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_0/A" -130.115
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "FD_v2_7/Clk_In" 16.1276
+cap "FD_v2_7/VDD" "FD_v2_7/Clk_In" 5.81161
+cap "FD_v2_7/GND" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 56.1057
+cap "FD_v2_7/VDD" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 70.4965
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/A" 12.052
+cap "FD_v2_7/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_7/Clk_In" 0.566547
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" 107.689
+cap "FD_v2_7/Clk_In" "sky130_fd_sc_hd__clkbuf_2_0/A" 1.98847
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 0.530259
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 188.97
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_0/X" 5.64474
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 15.9078
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 7.42363
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 22.1814
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 16.8441
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 4.75714
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 19.2794
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 45.5248
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 91.4874
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 79.3129
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/X" 209.582
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" -21.0416
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 6.84435
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 17.7031
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 128.924
+cap "sky130_fd_sc_hd__clkbuf_8_0/X" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 58.3619
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" -101.52
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 99.2513
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 24.3112
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 95.6317
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_4_0/A" 12.052
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/VPB" 22.4136
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/X" 43.1172
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" -75.8408
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 31.6347
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 8.16582
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 115.663
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_8_1/VPB" 7.0036
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" 77.6983
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_0/X" 100.606
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_8_0/A" 3.97695
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 49.6879
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 12.0812
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 12.0812
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 5.60377
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_1/VNB" 7.10543e-15
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/A" 5.21801
+cap "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_0/X" 150.457
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_8_1/X" 3.69079
+cap "sky130_fd_sc_hd__clkbuf_2_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" 23.4765
+cap "sky130_fd_sc_hd__clkbuf_8_0/A" "sky130_fd_sc_hd__clkbuf_8_0/VPB" 107.515
+cap "sky130_fd_sc_hd__clkbuf_4_0/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_0/A" 8.28293
+cap "sky130_fd_sc_hd__clkbuf_8_1/VPB" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 53.8883
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_8_1/VGND" "sky130_fd_sc_hd__clkbuf_16_0/X" 246.935
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/X" -87.58
+cap "sky130_fd_sc_hd__clkbuf_8_0/X" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 14.3373
+cap "sky130_fd_sc_hd__clkbuf_8_0/X" "sky130_fd_sc_hd__clkbuf_8_1/X" 7.95389
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 14.1026
+cap "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 35.2832
+cap "sky130_fd_sc_hd__clkbuf_8_0/X" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 43.4105
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" -140.43
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/X" 159.063
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 183.828
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 23.8617
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 24.8218
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_0/X" 6.81728
+cap "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 175.349
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 27.6506
+cap "sky130_fd_sc_hd__clkbuf_8_1/VPB" "sky130_fd_sc_hd__clkbuf_8_1/X" 2.52354
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 2.12629
+cap "sky130_fd_sc_hd__clkbuf_16_1/X" "sky130_fd_sc_hd__clkbuf_8_1/VGND" 137.717
+cap "sky130_fd_sc_hd__clkbuf_8_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_0/X" 36.3246
+cap "sky130_fd_sc_hd__clkbuf_16_0/VGND" "sky130_fd_sc_hd__clkbuf_16_1/X" 50.8858
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/X" -52.2788
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 21.3163
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 10.8508
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 88.6816
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_1/X" -102.92
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_1/a_110_47#" 7.95389
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" 1.13687e-13
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/VPB" 4.25665
+cap "FD_v2_3/VDD" "FD_v2_3/Clk_Out" 58.4053
+cap "FD_v2_3/GND" "FD_v2_3/Clk_Out" 180.219
+cap "FD_v2_3/VDD" "FD_v2_3/GND" 52.0237
+cap "FD_v2_3/GND" "FD_v2_3/6" 37.7137
+cap "FD_v2_3/GND" "FD_v2_3/4" 17.7273
+cap "FD_v2_4/Clkb" "FD_v2_3/7" 9.47414
+cap "FD_v5_0/Clkb_buf" "FD_v2_3/GND" 10.9463
+cap "FD_v2_3/Clk_Out" "FD_v2_3/7" 5.05366
+cap "FD_v2_3/6" "FD_v2_3/VDD" 30.6077
+cap "FD_v2_4/5" "FD_v2_3/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 4.4
+cap "FD_v2_3/2" "FD_v2_4/3" 0.695783
+cap "FD_v2_4/6" "FD_v2_3/VDD" 8.25689
+cap "FD_v2_3/GND" "FD_v2_3/7" 12.0649
+cap "FD_v2_3/4" "FD_v2_3/VDD" 16.4158
+cap "FD_v2_3/Clk_Out" "FD_v2_3/GND" 486.292
+cap "FD_v2_4/5" "FD_v2_3/VDD" 17.4046
+cap "FD_v2_3/2" "FD_v2_3/GND" 5.44323
+cap "FD_v2_3/Clk_Out" "FD_v2_3/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" 10.7812
+cap "FD_v5_0/Clkb_buf" "FD_v2_3/5" 0.540984
+cap "FD_v2_3/6" "FD_v5_0/dus" 1.60108
+cap "FD_v2_4/3" "FD_v2_3/VDD" 21.0238
+cap "FD_v2_4/Clkb" "FD_v2_3/VDD" 22.7108
+cap "FD_v2_3/7" "FD_v2_3/VDD" 12.0794
+cap "FD_v2_3/4" "FD_v5_0/dus" 0.142857
+cap "3-stage_cs-vco_dp9_0/out" "FD_v2_3/7" 2.14286
+cap "FD_v2_3/Clk_Out" "FD_v2_3/VDD" 104.475
+cap "FD_v2_3/Clk_Out" "FD_v2_3/5" 4.4
+cap "FD_v2_3/GND" "FD_v2_3/VDD" -187.542
+cap "FD_v2_3/2" "FD_v2_3/VDD" 6.77581
+cap "FD_v2_3/GND" "FD_v2_3/5" 23.9658
+cap "FD_v2_3/GND" "3-stage_cs-vco_dp9_0/out" 1.72174
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_3/VDD" 43.6154
+cap "FD_v2_3/GND" "FD_v5_0/dus" 10.9463
+cap "FD_v2_3/5" "FD_v2_3/VDD" 23.1859
+cap "FD_v2_4/2" "FD_v2_3/VDD" 2.77806
+cap "FD_v2_3/GND" "FD_v5_0/Clkb_int" 6.06486
+cap "FD_v2_3/GND" "FD_v2_3/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" 13.9615
+cap "FD_v2_4/4" "FD_v2_3/VDD" 14.1918
+cap "FD_v2_4/Clkb" "FD_v2_3/6" 2.22581
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_4/7" 2.96392
+cap "FD_v5_0/MNinv1/a_n73_37#" "FD_v2_2/6" 2.14286
+cap "FD_v2_2/5" "FD_v5_0/Clk_In_buf" 0.236559
+cap "FD_v2_2/2" "FD_v2_2/GND" 5.44323
+cap "FD_v2_2/VDD" "FD_v2_4/6" 9.59694
+cap "FD_v2_4/Clk_Out" "FD_v2_4/6" 3.3046
+cap "FD_v2_2/VDD" "FD_v2_5/4" 13.6446
+cap "FD_v2_2/Clk_Out" "FD_v5_0/Clk_In_buf" 7.89641
+cap "FD_v2_2/7" "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 22.4939
+cap "FD_v2_2/5" "FD_v2_2/GND" 3.5625
+cap "FD_v5_0/Clk_In_buf" "FD_v2_2/GND" 11.3614
+cap "FD_v2_2/Clk_Out" "FD_v2_4/7" 2.875
+cap "FD_v2_3/4" "FD_v2_2/GND" 8.28409
+cap "FD_v5_0/Clkb_buf" "FD_v2_2/Clk_Out" 1.78571
+cap "FD_v2_2/6" "FD_v5_0/3" 2.18833
+cap "FD_v2_3/Clkb" "FD_v2_2/7" 4.45238
+cap "FD_v5_0/Clkb_buf" "FD_v2_2/GND" 5.47317
+cap "FD_v2_2/Clk_Out" "FD_v2_2/GND" 76.8732
+cap "FD_v2_2/VDD" "FD_v2_3/3" 21.0238
+cap "FD_v2_2/VDD" "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.55612
+cap "FD_v2_2/VDD" "FD_v2_2/7" 26.6608
+cap "FD_v2_4/Clk_Out" "FD_v2_2/7" 2.875
+cap "FD_v5_0/3" "FD_v2_2/2" 3.06557
+cap "FD_v2_5/Clkb" "FD_v2_2/7" 9.47414
+cap "FD_v2_3/Clkb" "FD_v2_2/VDD" 60.5129
+cap "FD_v2_2/6" "FD_v2_2/VDD" 30.6077
+cap "FD_v2_5/Clkb" "FD_v2_2/6" 2.22581
+cap "FD_v2_4/Clk_Out" "FD_v2_2/VDD" 78.4973
+cap "FD_v2_4/2" "FD_v2_3/3" 0.695783
+cap "FD_v2_2/7" "FD_v5_0/Clk_In_buf" 7.66667
+cap "FD_v2_2/2" "FD_v2_2/VDD" 6.77581
+cap "FD_v5_0/dus" "FD_v2_2/Clk_Out" 2.63359
+cap "FD_v2_5/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_2/VDD" 2.77806
+cap "FD_v2_5/Clkb" "FD_v2_2/VDD" 60.5129
+cap "FD_v2_5/Clkb" "FD_v2_4/Clk_Out" 30.8478
+cap "FD_v5_0/Clkb_buf" "FD_v2_3/3" 2.64
+cap "FD_v2_2/6" "FD_v5_0/Clk_In_buf" 40.3918
+cap "FD_v2_2/Clk_Out" "FD_v2_3/3" 34.375
+cap "FD_v2_2/Clk_Out" "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" 5.89315
+cap "FD_v2_2/Clk_Out" "FD_v2_2/7" 80.363
+cap "FD_v2_3/3" "FD_v2_2/GND" 11.5455
+cap "FD_v2_3/Clkb" "FD_v2_4/7" 9.47414
+cap "FD_v5_0/3" "FD_v2_2/GND" 10.9463
+cap "FD_v2_3/sky130_fd_pr__pfet_01v8_A7DS5R_1/a_n15_n133#" "FD_v2_2/GND" 6
+cap "FD_v2_2/7" "FD_v2_2/GND" 25.8788
+cap "FD_v2_2/5" "FD_v2_2/VDD" 2.85
+cap "FD_v2_2/Clk_Out" "FD_v2_3/Clkb" 71.7391
+cap "FD_v2_2/Clk_Out" "FD_v2_2/6" 18.7444
+cap "FD_v2_2/VDD" "FD_v2_5/3" 21.0238
+cap "FD_v2_4/Clk_Out" "FD_v2_5/3" 14.7812
+cap "FD_v2_2/sky130_fd_pr__nfet_01v8_NDE37H_1/a_n118_22#" "FD_v5_0/Clk_In_buf" 0.214953
+cap "FD_v2_3/4" "FD_v2_2/VDD" 6.86786
+cap "FD_v2_4/2" "FD_v2_2/VDD" 6.64953
+cap "FD_v2_2/2" "FD_v2_5/3" 0.695783
+cap "FD_v2_3/Clkb" "FD_v2_2/GND" 29.5029
+cap "FD_v2_2/6" "FD_v2_2/GND" 37.7137
+cap "FD_v2_2/VDD" "FD_v2_4/7" 23.8827
+cap "FD_v2_4/Clk_Out" "FD_v2_4/7" 12.937
+cap "FD_v2_2/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/VDD" 18.2308
+cap "FD_v2_3/Clkb" "FD_v2_4/6" 2.22581
+cap "FD_v2_2/Clk_Out" "FD_v2_2/VDD" 81.2753
+cap "FD_v2_5/7" "FD_v2_2/Clk_In" 2.875
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_2/VDD" 2.77806
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/2" 2.20447
+cap "FD_v2_5/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/5" 4.4
+cap "FD_v2_2/2" "FD_v2_1/7" 22.4939
+cap "FD_v2_2/Clkb" "FD_v2_2/GND" 43.4645
+cap "FD_v2_2/Clkb" "FD_v2_5/7" 9.47414
+cap "FD_v5_0/5" "FD_v2_2/GND" 10.9463
+cap "FD_v2_5/4" "FD_v2_2/VDD" 0.547194
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/5" 1.77419
+cap "FD_v2_2/5" "FD_v5_0/3" 3.7651
+cap "FD_v2_6/3" "FD_v2_5/Clk_Out" 14.7812
+cap "FD_v2_6/3" "FD_v2_2/VDD" 7.11079
+cap "FD_v2_2/VDD" "FD_v2_2/2" 5.55612
+cap "FD_v2_5/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/VDD" 43.6154
+cap "FD_v2_2/3" "FD_v5_0/3" 8.13086
+cap "FD_v2_2/Clk_In" "FD_v2_2/2" 5.89315
+cap "FD_v2_6/sky130_fd_pr__nfet_01v8_PW5BNL_1/a_n73_37#" "FD_v2_5/7" 2.96392
+cap "FD_v2_6/Clkb" "FD_v2_1/7" 9.47414
+cap "FD_v2_5/sky130_fd_pr__pfet_01v8_ACPHKB_1/a_n33_37#" "FD_v2_2/Clk_In" 10.7812
+cap "FD_v2_2/VDD" "FD_v2_1/6" 8.41837
+cap "FD_v2_2/VDD" "FD_v2_5/5" 17.4046
+cap "FD_v2_2/Clk_In" "FD_v2_1/6" 18.7444
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/4" 2.20447
+cap "FD_v2_1/7" "FD_v5_0/4" 1.57143
+cap "FD_v2_2/3" "FD_v5_0/4" 2.03077
+cap "FD_v2_5/5" "FD_v2_2/Clk_In" 4.4
+cap "FD_v2_2/VDD" "FD_v2_2/5" 20.3359
+cap "FD_v5_0/3" "FD_v2_2/4" 4.36576
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/Clk_In" 81.9701
+cap "FD_v2_5/Clk_Out" "FD_v2_6/Clkb" 30.8478
+cap "FD_v2_2/VDD" "FD_v2_6/Clkb" 45.2822
+cap "FD_v2_5/Clk_Out" "FD_v2_1/7" 2.875
+cap "FD_v5_0/3" "FD_v2_2/Clk_In" 9.51092
+cap "FD_v2_2/VDD" "FD_v2_1/7" 26.6608
+cap "FD_v2_2/3" "FD_v2_2/VDD" 21.0238
+cap "FD_v2_2/3" "FD_v2_5/2" 0.695783
+cap "FD_v2_2/Clk_In" "FD_v2_1/7" 80.363
+cap "FD_v2_2/3" "FD_v2_2/Clk_In" 34.375
+cap "FD_v2_2/2" "FD_v2_2/GND" 6
+cap "FD_v2_2/VDD" "FD_v2_2/4" 23.2837
+cap "FD_v2_2/VDD" "FD_v2_5/Clk_Out" 78.4973
+cap "FD_v2_2/Clkb" "FD_v5_0/a_2222_n669#" 128.661
+cap "FD_v2_1/6" "FD_v2_2/GND" 9.55283
+cap "FD_v2_2/VDD" "FD_v2_2/Clk_In" 106.66
+cap "FD_v2_5/2" "FD_v2_2/VDD" 6.64953
+cap "FD_v2_2/Clkb" "FD_v5_0/3" 3.34177
+cap "FD_v2_5/Clk_Out" "FD_v2_5/6" 3.3046
+cap "FD_v2_2/VDD" "FD_v2_5/6" 17.8538
+cap "FD_v5_0/a_2222_n669#" "FD_v2_2/GND" 26.9811
+cap "FD_v2_2/Clkb" "FD_v2_1/7" 4.45238
+cap "FD_v2_2/5" "FD_v2_2/GND" 20.4033
+cap "FD_v5_0/3" "FD_v2_2/GND" 177.766
+cap "FD_v2_2/3" "FD_v2_2/GND" 11.5455
+cap "FD_v2_1/7" "FD_v2_2/GND" 25.8788
+cap "FD_v2_2/Clkb" "FD_v2_2/VDD" 60.5129
+cap "FD_v5_0/4" "FD_v2_2/GND" 21.8927
+cap "FD_v2_2/Clkb" "FD_v2_2/Clk_In" 71.7391
+cap "FD_v2_2/4" "FD_v2_2/GND" 26.0114
+cap "FD_v2_2/Clkb" "FD_v2_5/6" 2.22581
+cap "FD_v2_5/Clk_Out" "FD_v2_5/7" 12.937
+cap "FD_v2_2/Clk_In" "FD_v5_0/5" 2.34426
+cap "FD_v2_2/VDD" "FD_v2_5/7" 23.8827
+cap "FD_v2_2/Clk_In" "FD_v2_2/GND" 76.8732
+cap "FD_v2_1/5" "FD_v5_0/6" 5.30025
+cap "FD_v2_1/3" "FD_v2_2/VDD" 21.0238
+cap "FD_v2_1/5" "FD_v2_2/VDD" 23.1859
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/Clk_In" 8.29184
+cap "FD_v2_6/5" "FD_v2_2/VDD" 17.4046
+cap "FD_v2_1/Clk_In" "FD_v2_6/7" 2.875
+cap "FD_v2_5/GND" "FD_v5_0/6" 25.6327
+cap "FD_v2_6/2" "FD_v2_1/3" 0.695783
+cap "FD_v2_5/GND" "FD_v2_1/6" 28.1609
+cap "FD_v2_1/2" "FD_v2_5/GND" 11.4432
+cap "FD_v2_5/Clk_Out" "FD_v2_1/5" 4.4
+cap "FD_v2_2/VDD" "FD_v2_1/Clkb" 22.7108
+cap "FD_v2_6/6" "FD_v2_2/VDD" 17.8538
+cap "FD_v5_0/5" "FD_v2_1/6" 7.99683
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/6" 37.7139
+cap "FD_v2_1/4" "FD_v2_5/GND" 26.0114
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/2" 3.50625
+cap "FD_v2_6/4" "FD_v2_2/VDD" 14.1918
+cap "FD_v2_1/Clk_In" "FD_v5_0/6" 45.3525
+cap "FD_v2_6/7" "FD_v2_2/VDD" 9.30132
+cap "FD_v2_1/4" "FD_v5_0/5" 2.95331
+cap "FD_v2_1/4" "FD_v5_0/Clkb_buf" 2.20447
+cap "FD_v2_1/Clk_In" "FD_v2_2/VDD" 48.919
+cap "FD_v2_1/3" "FD_v2_5/GND" 11.5455
+cap "FD_v2_1/5" "FD_v2_5/GND" 23.9658
+cap "FD_v2_6/Clk_Out" "FD_v2_2/VDD" 6.52326
+cap "FD_v5_0/2" "FD_v2_1/Clkb" 1.80328
+cap "FD_v2_5/Clk_Out" "FD_v2_1/Clk_In" 10.7812
+cap "FD_v5_0/6" "FD_v2_1/6" 2.45093
+cap "FD_v5_0/2" "FD_v2_5/GND" 10.9463
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/3" 4.02151
+cap "FD_v5_0/5" "FD_v2_1/5" 8.13086
+cap "FD_v2_5/GND" "FD_v2_1/Clkb" 19.132
+cap "FD_v2_6/6" "FD_v2_1/Clkb" 2.22581
+cap "FD_v2_2/VDD" "FD_v2_1/6" 22.1893
+cap "FD_v2_6/Clkb" "FD_v2_1/6" 2.22581
+cap "FD_v2_2/VDD" "FD_v2_1/2" 12.3319
+cap "FD_v2_6/5" "FD_v2_1/Clk_In" 4.4
+cap "FD_v5_0/5" "FD_v2_1/Clkb" 9.18987
+cap "FD_v5_0/Clkb_buf" "FD_v2_1/Clkb" 84.4225
+cap "FD_v2_6/Clkb" "FD_v2_2/VDD" 15.2308
+cap "FD_v5_0/5" "FD_v2_5/GND" 177.766
+cap "FD_v5_0/Clkb_buf" "FD_v2_5/GND" 27.3962
+cap "FD_v2_6/7" "FD_v2_1/Clkb" 9.47414
+cap "FD_v2_1/4" "FD_v2_2/VDD" 23.2837
+cap "FD_v2_1/2" "FD_v2_6/3" 0.695783
+cap "FD_v2_6/2" "FD_v2_2/VDD" 6.64953
+cap "FD_v2_5/Clk_Out" "FD_v2_2/VDD" 43.6154
+cap "FD_v2_2/VDD" "FD_v2_6/3" 13.9131
+cap "FD_v2_1/Clk_In" "FD_v2_5/GND" 20.4435
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 35.5947
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 118.763
+cap "FD_v2_6/VDD" "sky130_fd_sc_hd__clkbuf_8_1/A" 5.81607
+cap "FD_v2_6/Clk_Out" "FD_v2_6/VDD" 5.81161
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "FD_v5_0/GND" 5.83377
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "FD_v2_6/VDD" 1.96107
+cap "FD_v5_0/MNbuf1/a_n73_37#" "FD_v5_0/GND" 1.0102
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "FD_v2_6/VDD" 24
+cap "sky130_fd_sc_hd__clkbuf_16_3/A" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 1.2349
+cap "FD_v2_6/VDD" "sky130_fd_sc_hd__clkbuf_4_1/A" 63.3118
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 2.11421
+cap "FD_v2_6/VDD" "FD_v5_0/GND" 45.6124
+cap "sky130_fd_sc_hd__clkbuf_16_3/A" "FD_v5_0/GND" 60.8993
+cap "FD_v5_0/Clk_Out" "FD_v2_6/VDD" 0.252551
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_4_1/A" 6.8484
+cap "FD_v2_6/Clk_Out" "sky130_fd_sc_hd__clkbuf_4_1/A" 2.4497
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "FD_v2_6/VDD" 29.7555
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 8.61495
+cap "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" "FD_v5_0/GND" 56.7732
+cap "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_16_3/X" 11.3904
+cap "FD_v2_6/Clk_Out" "FD_v5_0/GND" 74.6465
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "FD_v5_0/GND" 2.19415
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_4_1/A" 2.08516
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "FD_v2_6/VDD" 100.332
+cap "FD_v5_0/Clk_Out" "FD_v5_0/GND" 124.164
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "FD_v5_0/GND" 100.884
+cap "sky130_fd_sc_hd__clkbuf_16_3/A" "FD_v2_6/VDD" 7.23176
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 20.3747
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/VPWR" 187.38
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 173.899
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 79.236
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_8_1/A" 3.14714
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_8_1/A" 166.966
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 38.1486
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "li_8587_462#" -87.955
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_8_1/A" 6.8484
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/X" 15.5833
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/VPWR" 4.75714
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 2.43529
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 18.5887
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 3.66667
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_8_1/A" 0.551532
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 16.3188
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 11.7315
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/A" 2.77852
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 8.67403
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 0.174142
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 550.297
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_8_1/A" 1.95395
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_3/VPWR" 374.019
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" -86.6276
+cap "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" "sky130_fd_sc_hd__clkbuf_2_1/a_27_47#" 5.77345
+cap "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 22.4136
+cap "sky130_fd_sc_hd__clkbuf_8_1/A" "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" 32.1735
+cap "sky130_fd_sc_hd__clkbuf_4_1/A" "sky130_fd_sc_hd__clkbuf_4_1/a_27_47#" 2.67915
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 207.187
+cap "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/VPWR" -1.81899e-12
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 4.01342
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 18.5887
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 453.974
+cap "sky130_fd_sc_hd__clkbuf_16_3/VGND" "sky130_fd_sc_hd__clkbuf_16_3/VPB" -2.4869e-14
+cap "li_8587_462#" "sky130_fd_sc_hd__clkbuf_16_3/VPB" -87.955
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" 12.349
+cap "sky130_fd_sc_hd__clkbuf_8_1/X" "sky130_fd_sc_hd__clkbuf_16_3/VPB" 16.8595
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/a_110_47#" 38.1486
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_3/X" 18.7
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/X" -4.54747e-13
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_3/VPB" 180.023
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/VPB" -2.04636e-12
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/X" 6.70188
+cap "sky130_fd_sc_hd__clkbuf_8_1/a_110_47#" "sky130_fd_sc_hd__clkbuf_8_1/X" 8.67403
+cap "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/VPB" 109.547
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 42.8826
+cap "sky130_fd_sc_hd__clkbuf_16_3/X" "sky130_fd_sc_hd__clkbuf_16_3/VPB" 112.952
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_3/VGND" 221.213
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 4.25665
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/X" 6.70188
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/VGND" 85.5178
+cap "sky130_fd_sc_hd__clkbuf_16_0/VGND" "sky130_fd_sc_hd__clkbuf_16_0/X" 20.6392
+cap "sky130_fd_sc_hd__clkbuf_16_2/a_110_47#" "sky130_fd_sc_hd__clkbuf_16_0/VPB" 29.7555
+cap "sky130_fd_sc_hd__clkbuf_16_0/X" "sky130_fd_sc_hd__clkbuf_16_0/a_110_47#" 4.01342
+cap "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_16_0/X" 180.381
+cap "sky130_fd_sc_hd__clkbuf_16_0/VGND" "sky130_fd_sc_hd__clkbuf_16_0/VPB" 1.13687e-13
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" 245.05
+cap "3-stage_cs-vco_dp9_0/sel0" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 99.539
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel1" 133.343
+cap "3-stage_cs-vco_dp9_0/sel1" "3-stage_cs-vco_dp9_0/sel0" 36.6895
+cap "3-stage_cs-vco_dp9_0/sel1" "3-stage_cs-vco_dp9_0/sel3" 70.8562
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel0" 81.739
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/sel3" 103.016
+cap "3-stage_cs-vco_dp9_0/sel0" "3-stage_cs-vco_dp9_0/sel3" 71.7863
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 11.0169
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/sel1" 21.9036
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" 130.64
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/sel0" 43.8795
+cap "3-stage_cs-vco_dp9_0/sel2" "3-stage_cs-vco_dp9_0/sel3" 18.1536
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg0" 7.61076
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" 22.0339
+cap "3-stage_cs-vco_dp9_0/pg1" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" 28.3946
+cap "3-stage_cs-vco_dp9_0/pg1" "w_7680_n1770#" 7.37105
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_p_0/in" 4.54747e-13
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_2/sel" 12.5
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_0/sel" 18.377
+cap "3-stage_cs-vco_dp9_0/sel3" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" -1.3874
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/pg0" 28.773
+cap "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_1/sel" 14.0684
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_2/sel" 1.51515
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vdd" 111.872
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_3/sel" 13.1673
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_p_2/in" 11.0169
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/pg2" 20.9677
+cap "3-stage_cs-vco_dp9_0/out" "3-stage_cs-vco_dp9_0/vdd" 52.005
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/vco_switch_p_3/sel" 0.114213
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/pg2" 5.31335
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/pg3" 20.7447
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/out" -10.163
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/pg3" 5.28455
+cap "3-stage_cs-vco_dp9_0/out" "3-stage_cs-vco_dp9_0/XM12/a_15_n240#" 0.456221
+cap "3-stage_cs-vco_dp9_0/out" "3-stage_cs-vco_dp9_0/vss" -146.715
+cap "3-stage_cs-vco_dp9_0/out" "FD_v5_0/Clkb_int" 1.03321
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/vss" -275.329
+cap "3-stage_cs-vco_dp9_0/out" "3-stage_cs-vco_dp9_0/vdd" 1.59677
+cap "3-stage_cs-vco_dp9_0/out" "FD_v5_0/dus" 0.876106
+cap "FD_v5_0/Clk_Out" "FD_v5_0/7" 3.88522
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg1" 7.37105
+cap "w_7680_n1770#" "3-stage_cs-vco_dp9_0/pg0" 7.61076
+cap "3-stage_cs-vco_dp9_0/pg2" "3-stage_cs-vco_dp9_0/vdd" 5.31335
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/vss" 70.3896
+cap "3-stage_cs-vco_dp9_0/vdd" "3-stage_cs-vco_dp9_0/pg3" 5.28455
+cap "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vdd" 29.7491
+merge "FD_v5_0/VDD" "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" -13951.4 0 0 0 0 -999772 -47606 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -278714 -964 1959366 -74764 125300 -6284 -157760 -3748 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/vco_switch_p_0/vdd" "vdd"
+merge "vdd" "m1_n889_1476#"
+merge "m1_n889_1476#" "sky130_fd_sc_hd__clkbuf_16_2/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VPWR" "sky130_fd_sc_hd__clkbuf_16_2/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VPB" "sky130_fd_sc_hd__clkbuf_16_3/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VPWR" "sky130_fd_sc_hd__clkbuf_16_3/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VPB" "sky130_fd_sc_hd__clkbuf_16_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VPWR" "sky130_fd_sc_hd__clkbuf_16_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VPB" "sky130_fd_sc_hd__clkbuf_16_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VPWR" "sky130_fd_sc_hd__clkbuf_16_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VPB" "sky130_fd_sc_hd__clkbuf_2_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VPWR" "sky130_fd_sc_hd__clkbuf_2_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VPB" "sky130_fd_sc_hd__clkbuf_2_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VPWR" "sky130_fd_sc_hd__clkbuf_2_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VPB" "sky130_fd_sc_hd__clkbuf_4_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VPWR" "sky130_fd_sc_hd__clkbuf_4_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VPB" "sky130_fd_sc_hd__clkbuf_4_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VPWR" "sky130_fd_sc_hd__clkbuf_4_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VPB" "sky130_fd_sc_hd__clkbuf_8_0/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VPWR" "sky130_fd_sc_hd__clkbuf_8_0/VPB"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VPB" "sky130_fd_sc_hd__clkbuf_8_1/VPWR"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VPWR" "sky130_fd_sc_hd__clkbuf_8_1/VPB"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VPB" "FD_v2_1/VDD"
+merge "FD_v2_1/VDD" "FD_v2_6/VDD"
+merge "FD_v2_6/VDD" "FD_v2_7/VDD"
+merge "FD_v2_7/VDD" "FD_v2_8/VDD"
+merge "FD_v2_8/VDD" "FD_v2_5/VDD"
+merge "FD_v2_5/VDD" "FD_v2_2/VDD"
+merge "FD_v2_2/VDD" "3-stage_cs-vco_dp9_0/vdd"
+merge "3-stage_cs-vco_dp9_0/vdd" "FD_v2_9/VDD"
+merge "FD_v2_9/VDD" "FD_v2_4/VDD"
+merge "FD_v2_4/VDD" "FD_v2_3/VDD"
+merge "FD_v2_3/VDD" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vdd" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vdd" "w_7680_n1770#"
+merge "3-stage_cs-vco_dp9_0/vco_switch_p_0/vss" "vss" -17638.1 0 0 0 0 0 0 0 0 0 0 -239136 -408 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -362814 -964 3373368 -73630 311932 -3614 35550 -280 0 0 0 0 0 0
+merge "vss" "sky130_fd_sc_hd__clkbuf_16_2/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VNB" "sky130_fd_sc_hd__clkbuf_16_2/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_2/VGND" "sky130_fd_sc_hd__clkbuf_16_3/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VNB" "sky130_fd_sc_hd__clkbuf_16_3/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_3/VGND" "FD_v5_0/GND"
+merge "FD_v5_0/GND" "sky130_fd_sc_hd__clkbuf_16_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VNB" "sky130_fd_sc_hd__clkbuf_16_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_1/VGND" "sky130_fd_sc_hd__clkbuf_16_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VNB" "sky130_fd_sc_hd__clkbuf_16_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_16_0/VGND" "sky130_fd_sc_hd__clkbuf_2_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VNB" "sky130_fd_sc_hd__clkbuf_2_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_2_0/VGND" "sky130_fd_sc_hd__clkbuf_2_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VNB" "sky130_fd_sc_hd__clkbuf_2_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_2_1/VGND" "sky130_fd_sc_hd__clkbuf_4_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VNB" "sky130_fd_sc_hd__clkbuf_4_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_4_0/VGND" "sky130_fd_sc_hd__clkbuf_4_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VNB" "sky130_fd_sc_hd__clkbuf_4_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_4_1/VGND" "sky130_fd_sc_hd__clkbuf_8_0/VNB"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VNB" "sky130_fd_sc_hd__clkbuf_8_0/VGND"
+merge "sky130_fd_sc_hd__clkbuf_8_0/VGND" "sky130_fd_sc_hd__clkbuf_8_1/VNB"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VNB" "sky130_fd_sc_hd__clkbuf_8_1/VGND"
+merge "sky130_fd_sc_hd__clkbuf_8_1/VGND" "FD_v2_1/GND"
+merge "FD_v2_1/GND" "FD_v2_6/GND"
+merge "FD_v2_6/GND" "FD_v2_7/GND"
+merge "FD_v2_7/GND" "FD_v2_8/GND"
+merge "FD_v2_8/GND" "FD_v2_5/GND"
+merge "FD_v2_5/GND" "FD_v2_2/GND"
+merge "FD_v2_2/GND" "FD_v2_9/GND"
+merge "FD_v2_9/GND" "FD_v2_4/GND"
+merge "FD_v2_4/GND" "FD_v2_3/GND"
+merge "FD_v2_3/GND" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_2/vss" "3-stage_cs-vco_dp9_0/vss"
+merge "3-stage_cs-vco_dp9_0/vss" "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss"
+merge "3-stage_cs-vco_dp9_0/vco_switch_n_v2_0/vss" "a_8547_n771#"
+merge "3-stage_cs-vco_dp9_0/vco_switch_p_2/sel" "3-stage_cs-vco_dp9_0/sel2" -103.843 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -924 -122 10800 -320 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/sel2" "vsel2"
+merge "vsel2" "m2_n2159_1718#"
+merge "sky130_fd_sc_hd__clkbuf_16_2/X" "sky130_fd_sc_hd__clkbuf_16_3/X" -412.327 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10134 -924 0 0 120594 -2116 39240 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_3/X" "out_div128_buf"
+merge "FD_v5_0/Clk_Out" "FD_v2_1/Clk_In" -40.9159 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12486 -160 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_1/Clk_In" "m1_7680_300#"
+merge "FD_v2_6/Clk_In" "FD_v2_5/Clk_Out" -1.239 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19540 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_2_0/X" "sky130_fd_sc_hd__clkbuf_4_0/A" -114.439 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14144 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_4_0/A" "li_8782_n1210#"
+merge "FD_v2_1/Clk_Out" "FD_v2_2/Clk_In" -5.6304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12784 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_2/A" "sky130_fd_sc_hd__clkbuf_16_3/A" -619.566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -26456 -746 0 0 -120400 -5600 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_3/A" "sky130_fd_sc_hd__clkbuf_16_0/X"
+merge "sky130_fd_sc_hd__clkbuf_16_0/X" "li_8587_462#"
+merge "3-stage_cs-vco_dp9_0/vctrl" "vctrl" -110.952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14444 -430 0 0 0 0 0 0 0 0 0 0
+merge "vctrl" "m1_n2159_n461#"
+merge "sky130_fd_sc_hd__clkbuf_2_1/A" "FD_v2_6/Clk_Out" -93.6667 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4252 -136 819 -136 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_6/Clk_Out" "FD_v2_7/Clk_In"
+merge "FD_v2_7/Clk_In" "li_8577_n451#"
+merge "sky130_fd_sc_hd__clkbuf_4_1/X" "sky130_fd_sc_hd__clkbuf_8_1/A" -71.3998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71217 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_1/A" "li_9325_n451#"
+merge "3-stage_cs-vco_dp9_0/sel0" "vsel0" -81.2058 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -832 -116 -4200 -290 0 0 0 0 0 0 0 0
+merge "vsel0" "m2_n2159_1958#"
+merge "sky130_fd_sc_hd__clkbuf_2_0/A" "FD_v2_7/Clk_Out" -244.308 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2304 -192 58310 -482 47520 0 0 0 0 0 0 0 0 0
+merge "FD_v2_7/Clk_Out" "FD_v2_8/Clk_In"
+merge "FD_v2_8/Clk_In" "li_8588_n1221#"
+merge "3-stage_cs-vco_dp9_0/sel1" "vsel1" -98.7726 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -924 -122 -4480 -304 0 0 0 0 0 0 0 0
+merge "vsel1" "m2_n2159_1798#"
+merge "3-stage_cs-vco_dp9_0/sel3" "vsel3" -109.501 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11484 -122 8560 -290 0 0 0 0 0 0 0 0
+merge "vsel3" "m2_n2159_1638#"
+merge "FD_v2_9/Clk_In" "FD_v2_8/Clk_Out" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_4_0/X" "sky130_fd_sc_hd__clkbuf_8_0/A" -106.451 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13158 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_0/A" "li_9326_n1210#"
+merge "FD_v2_5/Clk_In" "FD_v2_4/Clk_Out" -22.3913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13002 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_16_1/X" "out_div256_buf" -132.952 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30832 -338 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_3/Clk_In" "FD_v2_2/Clk_Out" -13.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_2_1/X" "sky130_fd_sc_hd__clkbuf_4_1/A" -115.438 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32143 -272 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_4_1/A" "li_8789_n451#"
+merge "FD_v2_3/Clk_Out" "FD_v2_4/Clk_In" -59.5376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8696 -318 0 0 0 0 0 0 0 0 0 0
+merge "FD_v2_4/Clk_In" "m1_2161_286#"
+merge "sky130_fd_sc_hd__clkbuf_16_1/A" "sky130_fd_sc_hd__clkbuf_8_0/X" -74.8368 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18292 -408 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_0/X" "li_10187_n1210#"
+merge "sky130_fd_sc_hd__clkbuf_16_0/A" "sky130_fd_sc_hd__clkbuf_8_1/X" -175.416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -11590 -408 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_sc_hd__clkbuf_8_1/X" "li_10185_n451#"
+merge "FD_v5_0/Clk_In" "3-stage_cs-vco_dp9_0/out" -155.652 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -89099 -472 0 0 0 0 0 0 0 0 0 0 0 0
+merge "3-stage_cs-vco_dp9_0/out" "out"
diff --git a/mag/vco_with_fdivs.spice b/mag/vco_with_fdivs.spice
new file mode 100644
index 0000000..473251a
--- /dev/null
+++ b/mag/vco_with_fdivs.spice
@@ -0,0 +1,325 @@
+* NGSPICE file created from vco_with_fdivs.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt FD_v5 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb_buf 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPTgate2 5 6 5 6 Clk_In_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel3 sel2 vdd vss
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128 vdd vss vsel0 vsel1 vsel2 vsel3 out_div256
+XFD_v2_3 FD_v2_3/Clk_In vdd vss FD_v2_4/Clk_In FD_v2
+XFD_v2_4 FD_v2_4/Clk_In vdd vss FD_v2_5/Clk_In FD_v2
+XFD_v2_5 FD_v2_5/Clk_In vdd vss FD_v2_6/Clk_In FD_v2
+XFD_v2_6 FD_v2_6/Clk_In vdd vss out_div128 FD_v2
+XFD_v2_7 out_div128 vdd vss out_div256 FD_v2
+XFD_v2_8 out_div256 vdd vss FD_v2_9/Clk_In FD_v2
+XFD_v2_9 FD_v2_9/Clk_In vdd vss FD_v2_9/Clk_Out FD_v2
+XFD_v5_0 out vdd vss FD_v2_1/Clk_In FD_v5
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel3 vsel2 vdd vss x3-stage_cs-vco_dp9
+XFD_v2_1 FD_v2_1/Clk_In vdd vss FD_v2_2/Clk_In FD_v2
+XFD_v2_2 FD_v2_2/Clk_In vdd vss FD_v2_3/Clk_In FD_v2
+.ends
+
diff --git a/mag/vco_with_fdivs_-_lvs_clean_on_spro7.spice b/mag/vco_with_fdivs_-_lvs_clean_on_spro7.spice
new file mode 100755
index 0000000..74693b4
--- /dev/null
+++ b/mag/vco_with_fdivs_-_lvs_clean_on_spro7.spice
@@ -0,0 +1,433 @@
+* NGSPICE file created from vco_with_fdivs.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hd__clkbuf_8 A VGND VPWR X VNB VPB
+X0 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.65e+12p pd=1.53e+07u as=2.8e+11p ps=2.56e+06u w=1e+06u l=150000u
+X1 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=1.12e+12p ps=1.024e+07u w=1e+06u l=150000u
+X2 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=4.704e+11p pd=5.6e+06u as=6.951e+11p ps=8.35e+06u w=420000u l=150000u
+X5 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.176e+11p ps=1.4e+06u w=420000u l=150000u
+X9 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X17 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X19 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_4 A VGND VPWR X VNB VPB
+X0 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=9.1e+11p pd=7.82e+06u as=2.65e+11p ps=2.53e+06u w=1e+06u l=150000u
+X1 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=3.801e+11p pd=4.33e+06u as=2.352e+11p ps=2.8e+06u w=420000u l=150000u
+X2 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=5.6e+11p pd=5.12e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=150000u
+X6 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VPWR X VNB VPB
+X0 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=5.85e+11p pd=5.17e+06u as=2.65e+11p ps=2.53e+06u w=1e+06u l=150000u
+X1 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u
+X2 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=2.457e+11p pd=2.85e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=150000u
+X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.134e+11p pd=1.38e+06u as=0p ps=0u w=420000u l=150000u
+X5 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt FD_v5 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb_buf 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPTgate2 5 6 5 6 Clk_In_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+.ends
+
+.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VPWR X VNB VPB
+X0 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=3.045e+12p pd=2.809e+07u as=5.6e+11p ps=5.12e+06u w=1e+06u l=150000u
+X1 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.24e+12p ps=2.048e+07u w=1e+06u l=150000u
+X2 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=2.352e+11p pd=2.8e+06u as=1.2789e+12p ps=1.533e+07u w=420000u l=150000u
+X8 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=9.408e+11p ps=1.12e+07u w=420000u l=150000u
+X9 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_110_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 VGND A a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X17 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X18 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X20 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_110_47# A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X22 VPWR A a_110_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X26 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X28 VGND a_110_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X29 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X30 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X33 VPWR a_110_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 X a_110_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X36 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X37 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X38 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X39 X a_110_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel3 sel2 vss vdd
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128_buf vdd vss vsel0 vsel1 vsel2 vsel3 out_div256_buf
+Xsky130_fd_sc_hd__clkbuf_8_1 sky130_fd_sc_hd__clkbuf_8_1/A vss vdd sky130_fd_sc_hd__clkbuf_8_1/X
++ vss vdd sky130_fd_sc_hd__clkbuf_8
+XFD_v2_3 FD_v2_3/Clk_In vdd vss FD_v2_4/Clk_In FD_v2
+XFD_v2_4 FD_v2_4/Clk_In vdd vss FD_v2_5/Clk_In FD_v2
+XFD_v2_5 FD_v2_5/Clk_In vdd vss FD_v2_6/Clk_In FD_v2
+XFD_v2_6 FD_v2_6/Clk_In vdd vss FD_v2_7/Clk_In FD_v2
+XFD_v2_7 FD_v2_7/Clk_In vdd vss FD_v2_8/Clk_In FD_v2
+XFD_v2_8 FD_v2_8/Clk_In vdd vss FD_v2_9/Clk_In FD_v2
+Xsky130_fd_sc_hd__clkbuf_4_0 sky130_fd_sc_hd__clkbuf_4_0/A vss vdd sky130_fd_sc_hd__clkbuf_8_0/A
++ vss vdd sky130_fd_sc_hd__clkbuf_4
+XFD_v2_9 FD_v2_9/Clk_In vdd vss FD_v2_9/Clk_Out FD_v2
+Xsky130_fd_sc_hd__clkbuf_4_1 sky130_fd_sc_hd__clkbuf_4_1/A vss vdd sky130_fd_sc_hd__clkbuf_8_1/A
++ vss vdd sky130_fd_sc_hd__clkbuf_4
+Xsky130_fd_sc_hd__clkbuf_2_0 FD_v2_8/Clk_In vss vdd sky130_fd_sc_hd__clkbuf_4_0/A
++ vss vdd sky130_fd_sc_hd__clkbuf_2
+Xsky130_fd_sc_hd__clkbuf_2_1 FD_v2_7/Clk_In vss vdd sky130_fd_sc_hd__clkbuf_4_1/A
++ vss vdd sky130_fd_sc_hd__clkbuf_2
+XFD_v5_0 out vdd vss FD_v2_1/Clk_In FD_v5
+Xsky130_fd_sc_hd__clkbuf_16_0 sky130_fd_sc_hd__clkbuf_8_1/X vss vdd sky130_fd_sc_hd__clkbuf_16_3/A
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_1 sky130_fd_sc_hd__clkbuf_8_0/X vss vdd out_div256_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_2 sky130_fd_sc_hd__clkbuf_16_3/A vss vdd out_div128_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+Xsky130_fd_sc_hd__clkbuf_16_3 sky130_fd_sc_hd__clkbuf_16_3/A vss vdd out_div128_buf
++ vss vdd sky130_fd_sc_hd__clkbuf_16
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel3 vsel2 vss vdd x3-stage_cs-vco_dp9
+XFD_v2_1 FD_v2_1/Clk_In vdd vss FD_v2_2/Clk_In FD_v2
+Xsky130_fd_sc_hd__clkbuf_8_0 sky130_fd_sc_hd__clkbuf_8_0/A vss vdd sky130_fd_sc_hd__clkbuf_8_0/X
++ vss vdd sky130_fd_sc_hd__clkbuf_8
+XFD_v2_2 FD_v2_2/Clk_In vdd vss FD_v2_3/Clk_In FD_v2
+.ends
+
diff --git a/netgen/comp.out b/netgen/comp.out
index 42163df..bd3c101 100644
--- a/netgen/comp.out
+++ b/netgen/comp.out
@@ -1,18 +1,80 @@
-Equate elements: no current cell.
-Equate elements: no current cell.
-Equate elements: no current cell.
-Equate elements: no current cell.
-Equate elements: no current cell.
-Equate elements: no current cell.
-Equate elements: no current cell.
+Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 is a placeholder, treated as a black box.
-Class sky130_fd_sc_hvl__buf_8(0): Merged 18 parallel devices.
-Class sky130_fd_sc_hvl__buf_8(1): Merged 18 parallel devices.
-Subcircuit summary:
-Circuit 1: sky130_fd_sc_hvl__buf_8 |Circuit 2: sky130_fd_sc_hvl__buf_8
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8
-------------------------------------------|-------------------------------------------
-sky130_fd_pr__nfet_g5v0d10v5 (2) |sky130_fd_pr__nfet_g5v0d10v5 (2)
-sky130_fd_pr__pfet_g5v0d10v5 (2) |sky130_fd_pr__pfet_g5v0d10v5 (2)
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.
+Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
+Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
+Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
+-------------------------------------------|-------------------------------------------
+1 |1
+2 |2
+3 |3
+4 |4
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_5YXW2B in circuit vco_switch_p (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_hvt_N83GLL in circuit vco_switch_p (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_M34CP3 in circuit vco_switch_p (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_ACAZ2B_v2 in circuit vco_switch_p (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_HGTGXE_v2 in circuit vco_switch_p (0)(1 instance)
+Flattening unmatched subcell sky130_fd_sc_hd__inv_1[[0]] in circuit vco_switch_p (1)(1 instance)
+
+Subcircuit summary:
+Circuit 1: vco_switch_p |Circuit 2: vco_switch_p
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8 (2) |sky130_fd_pr__pfet_01v8 (2)
+sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
+sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
+Number of devices: 5 |Number of devices: 5
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: vco_switch_p |Circuit 2: vco_switch_p
+-------------------------------------------|-------------------------------------------
+in |in
+out |out
+vss |vss
+sel |sel
+vdd |vdd
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes vco_switch_p and vco_switch_p are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_8 (0): Merged 16 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
+sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
@@ -20,1405 +82,1606 @@
Netlists match uniquely.
Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__buf_8 |Circuit 2: sky130_fd_sc_hvl__buf_8
+Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
-------------------------------------------|-------------------------------------------
-A |A
-VPWR |VPWR
-VPB |VPB
X |X
VGND |VGND
VNB |VNB
+A |A
+VPWR |VPWR
+VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__buf_8 and sky130_fd_sc_hvl__buf_8 are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
+Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
Subcircuit summary:
-Circuit 1: sky130_fd_sc_hvl__schmittbuf_1 |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
-------------------------------------------|-------------------------------------------
-sky130_fd_pr__nfet_g5v0d10v5 (4) |sky130_fd_pr__nfet_g5v0d10v5 (4)
-sky130_fd_pr__pfet_g5v0d10v5 (4) |sky130_fd_pr__pfet_g5v0d10v5 (4)
-sky130_fd_pr__res_generic_nd__hv (1) |sky130_fd_pr__res_generic_nd__hv (1)
-sky130_fd_pr__res_generic_pd__hv (1) |sky130_fd_pr__res_generic_pd__hv (1)
-Number of devices: 10 |Number of devices: 10
-Number of nets: 11 |Number of nets: 11
+sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
+sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.
Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__schmittbuf_1 |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+A |A
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_2 (0): Merged 2 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
+sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
-------------------------------------------|-------------------------------------------
A |A
-VPB |VPB
-VNB |VNB
-VGND |VGND
VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__schmittbuf_1 and sky130_fd_sc_hvl__schmittbuf_1 are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_PW6BNL in circuit FD_v5 (0)(5 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_A4DS5R in circuit FD_v5 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_PW7BNL in circuit FD_v5 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_PW8BNL in circuit FD_v5 (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_A8DS5R in circuit FD_v5 (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_A2DS5R in circuit FD_v5 (0)(3 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_A1DS5R in circuit FD_v5 (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_PW9BNL in circuit FD_v5 (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_A9DS5R in circuit FD_v5 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_PW4BNL in circuit FD_v5 (0)(1 instance)
-Class sky130_fd_sc_hvl__inv_8(0): Merged 14 parallel devices.
-Class sky130_fd_sc_hvl__inv_8(1): Merged 14 parallel devices.
+Class FD_v5 (0): Merged 62 parallel devices.
Subcircuit summary:
-Circuit 1: sky130_fd_sc_hvl__inv_8 |Circuit 2: sky130_fd_sc_hvl__inv_8
+Circuit 1: FD_v5 |Circuit 2: FD_v5
-------------------------------------------|-------------------------------------------
-sky130_fd_pr__pfet_g5v0d10v5 (1) |sky130_fd_pr__pfet_g5v0d10v5 (1)
-sky130_fd_pr__nfet_g5v0d10v5 (1) |sky130_fd_pr__nfet_g5v0d10v5 (1)
-Number of devices: 2 |Number of devices: 2
-Number of nets: 6 |Number of nets: 6
+sky130_fd_pr__nfet_01v8 (41->11) |sky130_fd_pr__nfet_01v8 (41->11)
+sky130_fd_pr__pfet_01v8 (43->11) |sky130_fd_pr__pfet_01v8 (43->11)
+Number of devices: 22 |Number of devices: 22
+Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.
Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__inv_8 |Circuit 2: sky130_fd_sc_hvl__inv_8
+Circuit 1: FD_v5 |Circuit 2: FD_v5
+-------------------------------------------|-------------------------------------------
+Clk_Out |Clk_Out
+Clk_In |Clk_In
+VDD |VDD
+GND |GND
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes FD_v5 and FD_v5 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_16 (0): Merged 36 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
+sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
-------------------------------------------|-------------------------------------------
VPWR |VPWR
+X |X
VPB |VPB
VGND |VGND
VNB |VNB
A |A
-Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__inv_8 and sky130_fd_sc_hvl__inv_8 are equivalent.
-Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit example_por (0)(4 instances)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit example_por (0)(1 instance)
-Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit example_por (0)(1 instance)
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
-Class example_por(0): Merged 20 parallel devices.
-Class example_por(0): Merged 24 series devices.
+Class sky130_fd_sc_hd__clkbuf_2[[0]] (1): Merged 2 parallel devices.
Subcircuit summary:
-Circuit 1: example_por |Circuit 2: example_por
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2[[0]]
-------------------------------------------|-------------------------------------------
-sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1)
-sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2)
-sky130_fd_pr__pfet_g5v0d10v5 (8) |sky130_fd_pr__pfet_g5v0d10v5 (8)
-sky130_fd_pr__nfet_g5v0d10v5 (3) |sky130_fd_pr__nfet_g5v0d10v5 (3)
-sky130_fd_pr__res_xhigh_po_0p69 (3) |sky130_fd_pr__res_xhigh_po_0p69 (3)
-sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1)
-sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1)
-sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1)
-Number of devices: 20 |Number of devices: 20
-Number of nets: 16 |Number of nets: 16
+sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
+sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.
Subcircuit pins:
-Circuit 1: example_por |Circuit 2: example_por
+Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2[[0]]
-------------------------------------------|-------------------------------------------
-vdd3v3 |vdd3v3
-porb_h |porb_h
-porb_l |porb_l
-por_l |por_l
-vdd1v8 |vdd1v8
+A |A
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2[[0]] are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_4[[0]] (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4[[0]]
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
+sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4[[0]]
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+A |A
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4[[0]] are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_8[[0]] (1): Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8[[0]]
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
+sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8[[0]]
+-------------------------------------------|-------------------------------------------
+X |X
+VGND |VGND
+VNB |VNB
+A |A
+VPWR |VPWR
+VPB |VPB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8[[0]] are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_16[[0]] (1): Merged 36 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16[[0]]
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
+sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16[[0]]
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+X |X
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16[[0]] are equivalent.
+Flattening unmatched subcell FD_v2 in circuit vco_with_fdivs (0)(9 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_NDE37H in circuit vco_with_fdivs (0)(18 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_A7DS5R in circuit vco_with_fdivs (0)(54 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_PW5BNL in circuit vco_with_fdivs (0)(54 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_ACPHKB in circuit vco_with_fdivs (0)(18 instances)
+Flattening unmatched subcell x3-stage_cs-vco_dp9 in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_UUCHZP in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_NC2CGG in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_XZZ25Z in circuit vco_with_fdivs (0)(3 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_TUVSF7 in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_44BYND in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_B87NCT in circuit vco_with_fdivs (0)(3 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_NNRSEG in circuit vco_with_fdivs (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_26QSQN in circuit vco_with_fdivs (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_LS30AB in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell vco_switch_n_v2 in circuit vco_with_fdivs (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_ACAZ2B in circuit vco_with_fdivs (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_hvt_N83GLL in circuit vco_with_fdivs (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_M34CP3 in circuit vco_with_fdivs (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_HGTGXE_v2 in circuit vco_with_fdivs (0)(8 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_TPJM7Z in circuit vco_with_fdivs (0)(5 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_MP1P4U in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_TWMWTA in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_EMZ8SC in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_MP0P75 in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_MP0P50 in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_MP3P0U in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_8T82FM in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_MV8TJR in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_4XEGTB in circuit vco_with_fdivs (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_KQRM7Z in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AZHELG in circuit vco_with_fdivs (0)(1 instance)
+Flattening unmatched subcell 3-stage_cs-vco_dp9 in circuit vco_with_fdivs (1)(1 instance)
+Flattening unmatched subcell vco_switch_n in circuit vco_with_fdivs (1)(4 instances)
+Flattening unmatched subcell sky130_fd_sc_hd__inv_1[[0]] in circuit vco_with_fdivs (1)(4 instances)
+Flattening unmatched subcell FD in circuit vco_with_fdivs (1)(9 instances)
+
+Class vco_with_fdivs (0): Merged 10 parallel devices.
+Class vco_with_fdivs (1): Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: vco_with_fdivs |Circuit 2: vco_with_fdivs
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hd__clkbuf_8 (2) |sky130_fd_sc_hd__clkbuf_8[[0]] (2)
+sky130_fd_pr__nfet_01v8 (101->97) |sky130_fd_pr__nfet_01v8 (101->97)
+sky130_fd_pr__pfet_01v8 (95->89) |sky130_fd_pr__pfet_01v8 (93->89)
+sky130_fd_sc_hd__clkbuf_4 (2) |sky130_fd_sc_hd__clkbuf_4 (2)
+sky130_fd_sc_hd__clkbuf_2 (2) |sky130_fd_sc_hd__clkbuf_2 (2)
+FD_v5 (1) |FD_v5 (1)
+sky130_fd_sc_hd__clkbuf_16 (4) |sky130_fd_sc_hd__clkbuf_16[[0]] (4)
+sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
+vco_switch_p (4) |vco_switch_p (4)
+Number of devices: 205 |Number of devices: 205
+Number of nets: 110 |Number of nets: 110
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match with 1 symmetry.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: vco_with_fdivs |Circuit 2: vco_with_fdivs
+-------------------------------------------|-------------------------------------------
+vsel0 |vsel0
+vsel1 |vsel1
+vsel2 |vsel2
+vsel3 |vsel3
+vctrl |vctrl
+out_div256_buf |out_div256_buf
+vdd |vdd
vss |vss
+out_div128_buf |out_div128_buf
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
-Device classes example_por and example_por are equivalent.
-Flattening unmatched subcell user_analog_proj_example in circuit user_analog_project_wrapper (0)(1 instance)
+Device classes vco_with_fdivs and vco_with_fdivs are equivalent.
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[0]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[10]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[11]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[12]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[13]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[14]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[15]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[16]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[17]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[1]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[2]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[4]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[5]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[6]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[8]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[9]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[0]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[10]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[11]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[12]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[13]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[14]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[15]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[16]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[17]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[1]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[2]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[3]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[4]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[5]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[6]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[7]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[8]
-Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[0]
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-Cell user_analog_project_wrapper(0) disconnected node: io_analog[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_analog[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[11]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[12]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[15]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[16]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_in[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[11]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[12]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[15]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[16]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[24]
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-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_oeb[9]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[0]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[10]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[13]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[14]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[17]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[18]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[19]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[1]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[20]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[21]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[22]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[23]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[24]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[25]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[26]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[2]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[3]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[4]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[5]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[6]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[7]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[8]
-Cell user_analog_project_wrapper(0) disconnected node: io_out[9]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[0]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[100]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[101]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[102]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[103]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[104]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[105]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[106]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[107]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[108]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[109]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[10]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[110]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[111]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[112]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[113]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[114]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[115]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[116]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[117]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[118]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[119]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[11]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[120]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[121]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[122]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[123]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[124]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[125]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[126]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[127]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[12]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[13]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[14]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[15]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[16]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[17]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[18]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[19]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[1]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[20]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[21]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[22]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[23]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[24]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[25]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[26]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[27]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[28]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[29]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[2]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[30]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[31]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[32]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[33]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[34]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[35]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[36]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[37]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[38]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[39]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[3]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[40]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[41]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[42]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[43]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[44]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[45]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[46]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[47]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[48]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[49]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[4]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[50]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[51]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[52]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[53]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[54]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[55]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[56]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[57]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[58]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[59]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[5]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[60]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[61]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[62]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[63]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[64]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[65]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[66]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[67]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[68]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[69]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[6]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[70]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[71]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[72]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[73]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[74]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[75]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[76]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[77]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[78]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[7]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[80]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[81]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[86]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[89]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[8]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[90]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[91]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[94]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[95]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[97]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[98]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[99]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_in[9]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[0]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[100]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[101]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[102]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[103]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[104]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[105]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[106]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[107]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[108]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[109]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[10]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[110]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[111]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[112]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[113]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[114]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[115]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[118]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[119]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[11]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[120]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[121]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[122]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[123]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[124]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[125]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[126]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[127]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[12]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[13]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[14]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[15]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[16]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[17]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[18]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[19]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[1]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[20]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[21]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[22]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[23]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[24]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[25]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[26]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[27]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[28]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[29]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[2]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[30]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[31]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[32]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[33]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[34]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[35]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[36]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[37]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[38]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[39]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[3]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[40]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[41]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[43]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[49]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[4]
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-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[54]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[55]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[56]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[57]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[58]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[59]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[5]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[60]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[61]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[62]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[63]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[64]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[65]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[66]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[67]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[68]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[69]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[6]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[70]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[71]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[72]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[73]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[74]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[75]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[76]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[77]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[78]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[79]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[7]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[80]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[81]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[82]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[83]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[84]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[85]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[86]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[87]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[88]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[89]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[8]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[90]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[91]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[92]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[93]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[94]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[95]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[96]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[97]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[98]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[99]
-Cell user_analog_project_wrapper(0) disconnected node: la_data_out[9]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[0]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[100]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[101]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[102]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[103]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[104]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[105]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[106]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[107]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[108]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[109]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[10]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[110]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[111]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[112]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[113]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[114]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[115]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[116]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[117]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[118]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[119]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[11]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[120]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[121]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[122]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[123]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[124]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[125]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[126]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[127]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[12]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[13]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[14]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[15]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[16]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[17]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[18]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[19]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[1]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[20]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[21]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[22]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[23]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[24]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[25]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[26]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[27]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[28]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[29]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[2]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[30]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[31]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[32]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[33]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[34]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[35]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[36]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[37]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[38]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[39]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[3]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[40]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[41]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[42]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[43]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[44]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[45]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[46]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[47]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[48]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[49]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[4]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[50]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[51]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[52]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[53]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[54]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[55]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[56]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[57]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[58]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[59]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[5]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[60]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[61]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[62]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[63]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[64]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[65]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[66]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[67]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[68]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[69]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[6]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[70]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[71]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[72]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[73]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[74]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[75]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[76]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[77]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[78]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[79]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[7]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[80]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[81]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[82]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[83]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[84]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[85]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[86]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[87]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[88]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[89]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[8]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[90]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[91]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[92]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[93]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[94]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[95]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[96]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[97]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[98]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[99]
-Cell user_analog_project_wrapper(0) disconnected node: la_oenb[9]
-Cell user_analog_project_wrapper(0) disconnected node: user_clock2
-Cell user_analog_project_wrapper(0) disconnected node: user_irq[0]
-Cell user_analog_project_wrapper(0) disconnected node: user_irq[1]
-Cell user_analog_project_wrapper(0) disconnected node: user_irq[2]
-Cell user_analog_project_wrapper(0) disconnected node: vccd2
-Cell user_analog_project_wrapper(0) disconnected node: vdda2
-Cell user_analog_project_wrapper(0) disconnected node: vssa2
-Cell user_analog_project_wrapper(0) disconnected node: vssd2
-Cell user_analog_project_wrapper(0) disconnected node: wb_clk_i
-Cell user_analog_project_wrapper(0) disconnected node: wb_rst_i
-Cell user_analog_project_wrapper(0) disconnected node: wbs_ack_o
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[10]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[11]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[12]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[13]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[14]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[15]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[16]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[17]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[18]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[19]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[20]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[21]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[22]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[23]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[24]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[25]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[26]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[27]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[28]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[29]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[30]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[31]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[4]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[5]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[6]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[7]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[8]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_adr_i[9]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_cyc_i
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[10]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[11]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[12]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[13]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[14]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[15]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[16]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[17]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[18]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[19]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[20]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[21]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[22]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[23]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[24]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[25]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[26]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[27]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[28]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[29]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[30]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[31]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[4]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[5]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[6]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[7]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[8]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_i[9]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[10]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[11]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[12]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[13]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[14]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[15]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[16]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[17]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[18]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[19]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[20]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[21]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[22]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[23]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[24]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[25]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[26]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[27]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[28]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[29]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[30]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[31]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[4]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[5]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[6]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[7]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[8]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_dat_o[9]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[0]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[1]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[2]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_sel_i[3]
-Cell user_analog_project_wrapper(0) disconnected node: wbs_stb_i
-Cell user_analog_project_wrapper(0) disconnected node: wbs_we_i
-Cell user_analog_project_wrapper(1) disconnected node: vdda2
-Cell user_analog_project_wrapper(1) disconnected node: vssa2
-Cell user_analog_project_wrapper(1) disconnected node: vccd2
-Cell user_analog_project_wrapper(1) disconnected node: vssd2
-Cell user_analog_project_wrapper(1) disconnected node: wb_clk_i
-Cell user_analog_project_wrapper(1) disconnected node: wb_rst_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_stb_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_cyc_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_we_i
-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[3]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[2]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[1]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_sel_i[0]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[31]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[30]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[29]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[28]
-Cell user_analog_project_wrapper(1) disconnected node: wbs_dat_i[27]
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-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[36]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[35]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[34]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[33]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[32]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[31]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[30]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[29]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[28]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[27]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[26]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[25]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[24]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[23]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[22]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[21]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[20]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[19]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[18]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[17]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[16]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[15]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[14]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[13]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[12]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[11]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[10]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[9]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[8]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[7]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[6]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[5]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[4]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[3]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[2]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[1]
-Cell user_analog_project_wrapper(1) disconnected node: la_data_out[0]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[127]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[126]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[125]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[124]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[123]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[122]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[121]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[120]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[119]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[118]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[117]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[116]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[115]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[114]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[113]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[112]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[111]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[110]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[109]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[108]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[107]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[106]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[105]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[104]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[103]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[102]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[101]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[100]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[99]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[98]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[97]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[96]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[95]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[94]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[93]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[92]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[91]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[90]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[89]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[88]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[87]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[86]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[85]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[84]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[83]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[82]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[81]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[80]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[79]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[78]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[77]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[76]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[75]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[74]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[73]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[72]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[71]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[70]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[69]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[68]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[67]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[66]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[65]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[64]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[63]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[62]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[61]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[60]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[59]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[58]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[57]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[56]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[55]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[54]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[53]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[52]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[51]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[50]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[49]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[48]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[47]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[46]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[45]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[44]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[43]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[42]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[41]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[40]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[39]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[38]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[37]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[36]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[35]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[34]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[33]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[32]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[31]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[30]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[29]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[28]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[27]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[26]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[25]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[24]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[23]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[22]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[21]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[20]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[19]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[18]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[17]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[16]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[15]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[14]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[13]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[12]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[11]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[10]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[9]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[8]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[7]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[6]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[5]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[4]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[3]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[2]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[1]
-Cell user_analog_project_wrapper(1) disconnected node: la_oenb[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[26]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[25]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[24]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[23]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[22]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[21]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[20]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[19]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[18]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[17]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[16]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[15]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[14]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[13]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[12]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[11]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[10]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[4]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_in[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[26]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[25]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[24]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[23]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[22]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[21]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[20]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[19]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[18]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[17]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[16]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[15]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[14]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[13]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[12]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[11]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[10]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[4]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_in_3v3[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[26]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[25]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[24]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[23]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[22]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[21]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[20]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[19]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[18]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[17]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[14]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[13]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[10]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[4]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_out[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[26]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[25]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[24]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[23]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[22]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[21]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[20]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[19]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[18]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[17]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[14]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[13]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[10]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[4]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_oeb[0]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[17]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[16]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[15]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[14]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[13]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[12]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[11]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[10]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[9]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[8]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[6]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[5]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[4]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[2]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[1]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[0]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[17]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[16]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[15]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[14]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[13]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[12]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[11]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[10]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[9]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[8]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[7]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[6]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[5]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[4]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[3]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[2]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[1]
-Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[0]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[10]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[9]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[8]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[7]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[6]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[5]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[3]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[2]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[1]
-Cell user_analog_project_wrapper(1) disconnected node: io_analog[0]
-Cell user_analog_project_wrapper(1) disconnected node: user_clock2
-Cell user_analog_project_wrapper(1) disconnected node: user_irq[2]
-Cell user_analog_project_wrapper(1) disconnected node: user_irq[1]
-Cell user_analog_project_wrapper(1) disconnected node: user_irq[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
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+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[46]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[45]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[44]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[43]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[42]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[41]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[40]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[39]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[38]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[37]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[36]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[35]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[34]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[33]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[32]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[31]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[30]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[29]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[28]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[27]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[26]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[25]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[24]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[23]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[22]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[21]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[20]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[19]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[18]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[17]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[16]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[15]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[14]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[13]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[12]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[11]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[10]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[9]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[8]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[7]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[6]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[5]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[4]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[3]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[2]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[1]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[0]
Subcircuit summary:
Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
-------------------------------------------|-------------------------------------------
-example_por (2) |example_por (2)
-sky130_fd_pr__res_generic_m3 (10) |sky130_fd_pr__res_generic_m3 (10)
-Number of devices: 12 |Number of devices: 12
-Number of nets: 21 |Number of nets: 21
+vco_with_fdivs (1) |vco_with_fdivs (1)
+sky130_fd_pr__res_generic_m3 (6) |sky130_fd_pr__res_generic_m3 (6)
+Number of devices: 7 |Number of devices: 7
+Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
@@ -1428,27 +1691,21 @@
Subcircuit pins:
Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
-------------------------------------------|-------------------------------------------
-vssd1 |vssd1
vssa1 |vssa1
vccd1 |vccd1
-io_analog[4] |io_analog[4]
-vdda1 |vdda1
-gpio_analog[3] |gpio_analog[3]
-io_out[11] |io_out[11]
-io_out[12] |io_out[12]
-gpio_analog[7] |gpio_analog[7]
+io_oeb[17] |io_oeb[17]
+io_oeb[20] |io_oeb[20]
+io_oeb[18] |io_oeb[18]
+io_oeb[19] |io_oeb[19]
+gpio_analog[9] |gpio_analog[9]
+io_in[17] |io_in[17]
+io_in[18] |io_in[18]
+io_in[19] |io_in[19]
+io_in[20] |io_in[20]
+io_out[14] |io_out[14]
io_out[15] |io_out[15]
-io_out[16] |io_out[16]
-io_clamp_low[2] |io_clamp_low[2]
-io_clamp_high[2] |io_clamp_high[2]
-io_clamp_low[1] |io_clamp_low[1]
-io_clamp_high[1] |io_clamp_high[1]
-io_clamp_low[0] |io_clamp_low[0]
-io_clamp_high[0] |io_clamp_high[0]
-io_oeb[12] |io_oeb[12]
-io_oeb[16] |io_oeb[16]
-io_oeb[11] |io_oeb[11]
io_oeb[15] |io_oeb[15]
+io_oeb[14] |io_oeb[14]
gpio_analog[0] |gpio_analog[0]
gpio_analog[10] |gpio_analog[10]
gpio_analog[11] |gpio_analog[11]
@@ -1460,11 +1717,12 @@
gpio_analog[17] |gpio_analog[17]
gpio_analog[1] |gpio_analog[1]
gpio_analog[2] |gpio_analog[2]
+gpio_analog[3] |gpio_analog[3]
gpio_analog[4] |gpio_analog[4]
gpio_analog[5] |gpio_analog[5]
gpio_analog[6] |gpio_analog[6]
+gpio_analog[7] |gpio_analog[7]
gpio_analog[8] |gpio_analog[8]
-gpio_analog[9] |gpio_analog[9]
gpio_noesd[0] |gpio_noesd[0]
gpio_noesd[10] |gpio_noesd[10]
gpio_noesd[11] |gpio_noesd[11]
@@ -1491,8 +1749,15 @@
io_analog[7] |io_analog[7]
io_analog[8] |io_analog[8]
io_analog[9] |io_analog[9]
+io_analog[4] |io_analog[4]
io_analog[5] |io_analog[5]
io_analog[6] |io_analog[6]
+io_clamp_high[0] |io_clamp_high[0]
+io_clamp_high[1] |io_clamp_high[1]
+io_clamp_high[2] |io_clamp_high[2]
+io_clamp_low[0] |io_clamp_low[0]
+io_clamp_low[1] |io_clamp_low[1]
+io_clamp_low[2] |io_clamp_low[2]
io_in[0] |io_in[0]
io_in[10] |io_in[10]
io_in[11] |io_in[11]
@@ -1501,11 +1766,7 @@
io_in[14] |io_in[14]
io_in[15] |io_in[15]
io_in[16] |io_in[16]
-io_in[17] |io_in[17]
-io_in[18] |io_in[18]
-io_in[19] |io_in[19]
io_in[1] |io_in[1]
-io_in[20] |io_in[20]
io_in[21] |io_in[21]
io_in[22] |io_in[22]
io_in[23] |io_in[23]
@@ -1549,13 +1810,11 @@
io_in_3v3[9] |io_in_3v3[9]
io_oeb[0] |io_oeb[0]
io_oeb[10] |io_oeb[10]
+io_oeb[11] |io_oeb[11]
+io_oeb[12] |io_oeb[12]
io_oeb[13] |io_oeb[13]
-io_oeb[14] |io_oeb[14]
-io_oeb[17] |io_oeb[17]
-io_oeb[18] |io_oeb[18]
-io_oeb[19] |io_oeb[19]
+io_oeb[16] |io_oeb[16]
io_oeb[1] |io_oeb[1]
-io_oeb[20] |io_oeb[20]
io_oeb[21] |io_oeb[21]
io_oeb[22] |io_oeb[22]
io_oeb[23] |io_oeb[23]
@@ -1572,8 +1831,10 @@
io_oeb[9] |io_oeb[9]
io_out[0] |io_out[0]
io_out[10] |io_out[10]
+io_out[11] |io_out[11]
+io_out[12] |io_out[12]
io_out[13] |io_out[13]
-io_out[14] |io_out[14]
+io_out[16] |io_out[16]
io_out[17] |io_out[17]
io_out[18] |io_out[18]
io_out[19] |io_out[19]
@@ -1982,8 +2243,10 @@
user_irq[1] |user_irq[1]
user_irq[2] |user_irq[2]
vccd2 |vccd2
+vdda1 |vdda1
vdda2 |vdda2
vssa2 |vssa2
+vssd1 |vssd1
vssd2 |vssd2
wb_clk_i |wb_clk_i
wb_rst_i |wb_rst_i
diff --git a/netgen/ng.ini b/netgen/ng.ini
new file mode 100644
index 0000000..330ced1
--- /dev/null
+++ b/netgen/ng.ini
@@ -0,0 +1 @@
+recentfile "../xschem/user_analog_project_wrapper.spice user_analog_project_wrapper"
diff --git a/netgen/setup.tcl b/netgen/setup.tcl
new file mode 100644
index 0000000..2b1d1af
--- /dev/null
+++ b/netgen/setup.tcl
@@ -0,0 +1,449 @@
+#---------------------------------------------------------------
+# Setup file for netgen LVS
+# SkyWater sky130A
+#---------------------------------------------------------------
+permute default
+property default
+property parallel none
+
+# Allow override of default #columns in the output format.
+catch {format $env(NETGEN_COLUMNS)}
+
+#---------------------------------------------------------------
+# For the following, get the cell lists from
+# circuit1 and circuit2.
+#---------------------------------------------------------------
+
+set cells1 [cells list -all -circuit1]
+set cells2 [cells list -all -circuit2]
+
+# NOTE: In accordance with the LVS manager GUI, the schematic is
+# always circuit2, so some items like property "par1" only need to
+# be specified for circuit2.
+
+#-------------------------------------------
+# Resistors (except metal)
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__res_iso_pw
+lappend devices sky130_fd_pr__res_high_po_0p35
+lappend devices sky130_fd_pr__res_high_po_0p69
+lappend devices sky130_fd_pr__res_high_po_1p41
+lappend devices sky130_fd_pr__res_high_po_2p85
+lappend devices sky130_fd_pr__res_high_po_5p73
+lappend devices sky130_fd_pr__res_high_po
+lappend devices sky130_fd_pr__res_xhigh_po_0p35
+lappend devices sky130_fd_pr__res_xhigh_po_0p69
+lappend devices sky130_fd_pr__res_xhigh_po_1p41
+lappend devices sky130_fd_pr__res_xhigh_po_2p85
+lappend devices sky130_fd_pr__res_xhigh_po_5p73
+lappend devices sky130_fd_pr__res_xhigh_po
+lappend devices sky130_fd_pr__res_generic_nd
+lappend devices sky130_fd_pr__res_generic_pd
+lappend devices sky130_fd_pr__res_generic_nd__hv
+lappend devices sky130_fd_pr__res_generic_pd__hv
+lappend devices mrdn_hv mrdp_hv
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ permute "-circuit1 $dev" 1 2
+ property "-circuit1 $dev" series enable
+ property "-circuit1 $dev" series {w critical}
+ property "-circuit1 $dev" series {l add}
+ property "-circuit1 $dev" parallel enable
+ property "-circuit1 $dev" parallel {l critical}
+ property "-circuit1 $dev" parallel {w add}
+ property "-circuit1 $dev" parallel {value par}
+ property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+ # Ignore these properties
+ property "-circuit1 $dev" delete mult
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ permute "-circuit2 $dev" 1 2
+ property "-circuit2 $dev" series enable
+ property "-circuit2 $dev" series {w critical}
+ property "-circuit2 $dev" series {l add}
+ property "-circuit2 $dev" parallel enable
+ property "-circuit2 $dev" parallel {l critical}
+ property "-circuit2 $dev" parallel {w add}
+ property "-circuit2 $dev" parallel {value par}
+ property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+ # Ignore these properties
+ property "-circuit2 $dev" delete mult
+ }
+}
+
+#-------------------------------------------
+# MRM (metal) resistors and poly resistor
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__res_generic_po
+lappend devices sky130_fd_pr__res_generic_l1
+lappend devices sky130_fd_pr__res_generic_m1
+lappend devices sky130_fd_pr__res_generic_m2
+lappend devices sky130_fd_pr__res_generic_m3
+lappend devices sky130_fd_pr__res_generic_m4
+lappend devices sky130_fd_pr__res_generic_m5
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ permute "-circuit1 $dev" end_a end_b
+ property "-circuit1 $dev" series enable
+ property "-circuit1 $dev" series {w critical}
+ property "-circuit1 $dev" series {l add}
+ property "-circuit1 $dev" parallel enable
+ property "-circuit1 $dev" parallel {l critical}
+ property "-circuit1 $dev" parallel {w add}
+ property "-circuit1 $dev" parallel {value par}
+ property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+ # Ignore these properties
+ property "-circuit1 $dev" delete mult
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ permute "-circuit2 $dev" end_a end_b
+ property "-circuit2 $dev" series enable
+ property "-circuit2 $dev" series {w critical}
+ property "-circuit2 $dev" series {l add}
+ property "-circuit2 $dev" parallel enable
+ property "-circuit2 $dev" parallel {l critical}
+ property "-circuit2 $dev" parallel {w add}
+ property "-circuit2 $dev" parallel {value par}
+ property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+ # Ignore these properties
+ property "-circuit2 $dev" delete mult
+ }
+}
+
+#-------------------------------------------
+# (MOS) transistors
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__nfet_01v8
+lappend devices sky130_fd_pr__nfet_01v8_lvt
+lappend devices sky130_fd_bs_flash__special_sonosfet_star
+lappend devices sky130_fd_pr__nfet_g5v0d10v5
+lappend devices sky130_fd_pr__nfet_05v0_nvt
+lappend devices sky130_fd_pr__pfet_01v8
+lappend devices sky130_fd_pr__pfet_01v8_lvt
+lappend devices sky130_fd_pr__pfet_01v8_mvt
+lappend devices sky130_fd_pr__pfet_01v8_hvt
+lappend devices sky130_fd_pr__pfet_g5v0d10v5
+lappend devices sky130_fd_pr__special_pfet_pass
+lappend devices sky130_fd_pr__special_nfet_pass
+lappend devices sky130_fd_pr__special_nfet_latch
+lappend devices sky130_fd_pr__cap_var_lvt
+lappend devices sky130_fd_pr__cap_var_hvt
+lappend devices sky130_fd_pr__cap_var
+lappend devices sky130_fd_pr__nfet_20v0_nvt
+lappend devices sky130_fd_pr__nfet_20v0
+lappend devices sky130_fd_pr__pfet_20v0
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ permute "-circuit1 $dev" 1 3
+ property "-circuit1 $dev" parallel enable
+ property "-circuit1 $dev" parallel {l critical}
+ property "-circuit1 $dev" parallel {w add}
+ property "-circuit1 $dev" tolerance {w 0.01} {l 0.01}
+ # Ignore these properties
+ property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ permute "-circuit2 $dev" 1 3
+ property "-circuit2 $dev" parallel enable
+ property "-circuit2 $dev" parallel {l critical}
+ property "-circuit2 $dev" parallel {w add}
+ property "-circuit2 $dev" tolerance {w 0.01} {l 0.01}
+ # Ignore these properties
+ property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+ }
+}
+
+#---------------------------------------------------------------------
+# (MOS) ESD transistors. Note that the ESD transistors have a flanged
+# gate. Magic disagrees slightly on how to interpret the width of the
+# devices, so the tolerance is increased to 7% to cover the difference
+#---------------------------------------------------------------------
+
+lappend devices sky130_fd_pr__esd_nfet_g5v0d10v5
+lappend devices sky130_fd_pr__esd_pfet_g5v0d10v5
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ permute "-circuit1 $dev" 1 3
+ property "-circuit1 $dev" parallel enable
+ property "-circuit1 $dev" parallel {l critical}
+ property "-circuit1 $dev" parallel {w add}
+ property "-circuit1 $dev" tolerance {w 0.07} {l 0.01}
+ # Ignore these properties
+ property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ permute "-circuit2 $dev" 1 3
+ property "-circuit2 $dev" parallel enable
+ property "-circuit2 $dev" parallel {l critical}
+ property "-circuit2 $dev" parallel {w add}
+ property "-circuit2 $dev" tolerance {w 0.07} {l 0.01}
+ # Ignore these properties
+ property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+ }
+}
+
+#-------------------------------------------
+# diodes
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__diode_pw2nd_05v5
+lappend devices sky130_fd_pr__diode_pw2nd_05v5_lvt
+lappend devices sky130_fd_pr__diode_pw2nd_05v5_nvt
+lappend devices sky130_fd_pr__diode_pd2nw_05v5
+lappend devices sky130_fd_pr__diode_pd2nw_05v5_lvt
+lappend devices sky130_fd_pr__diode_pd2nw_05v5_hvt
+lappend devices sky130_fd_pr__diode_pw2nd_11v0
+lappend devices sky130_fd_pr__diode_pd2nw_11v0
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ property "-circuit1 $dev" parallel enable
+ property "-circuit1 $dev" parallel {area add}
+ property "-circuit1 $dev" parallel {value add}
+ property "-circuit1 $dev" tolerance {area 0.02}
+ # Ignore these properties
+ property "-circuit1 $dev" delete mult perim
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ property "-circuit2 $dev" parallel enable
+ property "-circuit2 $dev" parallel {area add}
+ property "-circuit2 $dev" parallel {value add}
+ property "-circuit2 $dev" tolerance {area 0.02}
+ # Ignore these properties
+ property "-circuit2 $dev" delete mult perim
+ }
+}
+
+#-------------------------------------------
+# capacitors
+# MiM capacitors
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__cap_mim_m3_1
+lappend devices sky130_fd_pr__cap_mim_m3_2
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ property "-circuit1 $dev" parallel enable
+ property "-circuit1 $dev" parallel {area add}
+ property "-circuit1 $dev" parallel {value add}
+ property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+ # Ignore these properties
+ property "-circuit1 $dev" delete mult perim mf
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ property "-circuit2 $dev" parallel enable
+ property "-circuit2 $dev" parallel {area add}
+ property "-circuit2 $dev" parallel {value add}
+ property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+ # Ignore these properties
+ property "-circuit2 $dev" delete mult perim mf
+ }
+}
+
+#-------------------------------------------
+# Fixed-layout devices
+# bipolar transistors,
+# VPP capacitors
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__npn_05v5_W1p00L1p00
+lappend devices sky130_fd_pr__npn_05v5_W1p00L2p00
+lappend devices sky130_fd_pr__pnp_05v5_W0p68L0p68
+lappend devices sky130_fd_pr__pnp_05v5_W3p40L3p40
+lappend devices sky130_fd_pr__npn_05v5
+lappend devices sky130_fd_pr__pnp_05v5
+lappend devices sky130_fd_pr__npn_11v0
+
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m4_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_pom4_shield
+lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_lim4_shield
+lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_polym4_shield
+lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_li_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_shield
+lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_li_shield
+lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_m3_shield
+lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_li_shield
+lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_shield
+lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_li_shield
+lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_shield
+lappend devices sky130_fd_pr__ind_04_01
+lappend devices sky130_fd_pr__ind_04_02
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ property "-circuit1 $dev" parallel enable
+ # Ignore these properties
+ property "-circuit1 $dev" delete mult
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ property "-circuit2 $dev" parallel enable
+ # Ignore these properties
+ property "-circuit2 $dev" delete mult
+ }
+}
+
+#---------------------------------------------------------------
+# Schematic cells which are not extractable
+#---------------------------------------------------------------
+
+set devices {sky130_fd_io__condiode sky130_fd_io__tap_1}
+
+foreach dev $devices {
+ if {[lsearch $cells1 $dev] >= 0} {
+ ignore class "-circuit1 $dev"
+ }
+ if {[lsearch $cells2 $dev] >= 0} {
+ ignore class "-circuit2 $dev"
+ }
+}
+
+#---------------------------------------------------------------
+# Digital cells (ignore decap, fill, and tap cells)
+# Make a separate list for each supported library
+#---------------------------------------------------------------
+# e.g., ignore class "-circuit2 sky130_fc_sc_hd__decap_3"
+#---------------------------------------------------------------
+
+if { [info exist ::env(MAGIC_EXT_USE_GDS)] && $::env(MAGIC_EXT_USE_GDS) } {
+ foreach cell $cells1 {
+# if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+# ignore class "-circuit1 $cell"
+# }
+ if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+ ignore class "-circuit1 $cell"
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+ ignore class "-circuit1 $cell"
+ }
+ if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+ ignore class "-circuit1 $cell"
+ }
+ }
+ foreach cell $cells2 {
+# if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+# ignore class "-circuit2 $cell"
+# }
+ if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+ ignore class "-circuit2 $cell"
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+ ignore class "-circuit2 $cell"
+ }
+ if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+ ignore class "-circuit2 $cell"
+ }
+ }
+}
+
+#---------------------------------------------------------------
+# Allow the fill, decap, etc., cells to be parallelized
+#---------------------------------------------------------------
+
+foreach cell $cells1 {
+ if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+ property "-circuit1 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+ property "-circuit1 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+ property "-circuit1 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} {
+ property "-circuit1 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} {
+ property "-circuit1 $cell" parallel enable
+ }
+ if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+ property "-circuit1 $cell" parallel enable
+ }
+}
+foreach cell $cells2 {
+ if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+ property "-circuit2 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+ property "-circuit2 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+ property "-circuit2 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} {
+ property "-circuit2 $cell" parallel enable
+ }
+ if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} {
+ property "-circuit2 $cell" parallel enable
+ }
+ if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+ property "-circuit2 $cell" parallel enable
+ }
+}
+
+#---------------------------------------------------------------
+# Handle cells captured from Electric
+#
+# Find cells of the form "<library>__<cellname>" in the netlist
+# from Electric where the extracted layout netlist has only
+# "<cellname>". Cross-check by ensuring that the full name
+# "<library>__<cellname>" does not exist in both cells, and that
+# the truncated name "<cellname>" does not exist in both cells.
+#---------------------------------------------------------------
+# e.g., hydra_spi_controller__hydra_spi_controller
+#---------------------------------------------------------------
+
+foreach cell $cells1 {
+ if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+ if {([lsearch $cells2 $cell] < 0) && \
+ ([lsearch $cells2 $cellname] >= 0) && \
+ ([lsearch $cells1 $cellname] < 0)} {
+ equate classes "-circuit1 $cell" "-circuit2 $cellname"
+ puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2"
+ equate pins "-circuit1 $cell" "-circuit2 $cellname"
+ }
+ }
+}
+
+foreach cell $cells2 {
+ if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+ if {([lsearch $cells1 $cell] < 0) && \
+ ([lsearch $cells1 $cellname] >= 0) && \
+ ([lsearch $cells2 $cellname] < 0)} {
+ equate classes "-circuit1 $cellname" "-circuit2 $cell"
+ puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2"
+ equate pins "-circuit1 $cellname" "-circuit2 $cell"
+ }
+ }
+}
+
+# Match pins on black-box cells if LVS is called with "-blackbox"
+if {[model blackbox]} {
+ foreach cell $cells1 {
+ if {[model "-circuit1 $cell"] == "blackbox"} {
+ if {[lsearch $cells2 $cell] >= 0} {
+ puts stdout "Matching pins of $cell in circuits 1 and 2"
+ equate pins "-circuit1 $cell" "-circuit2 $cell"
+ }
+ }
+ }
+}
+
+#---------------------------------------------------------------
diff --git a/netgen/example_por.spice b/netgen/unused/example_por.spice
similarity index 100%
rename from netgen/example_por.spice
rename to netgen/unused/example_por.spice
diff --git a/netgen/unused/user_analog_project_wrapper_-_copy_beforehand.spice b/netgen/unused/user_analog_project_wrapper_-_copy_beforehand.spice
new file mode 100644
index 0000000..c3851a3
--- /dev/null
+++ b/netgen/unused/user_analog_project_wrapper_-_copy_beforehand.spice
@@ -0,0 +1,336 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW c2_n3079_n3000# m4_n3179_n3100#
+X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_sc_hvl__buf_8 A VGND VPWR X VNB VPB
+X0 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X2 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X3 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X5 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X9 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X15 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X16 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X18 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X19 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X20 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X21 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ a_n683_n200# a_n189_n297# a_29_n297# a_189_n200#
++ a_n901_n200# a_247_n297# a_n407_n297# a_465_n297# a_407_n200# a_n625_n297# a_683_n297#
++ a_625_n200# a_n843_n297# w_n1101_n497# a_843_n200# a_n29_n200# a_n247_n200# a_n465_n200#
+X0 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X2 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X4 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X7 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n792_n200# a_298_n200# a_516_n200# a_734_n200#
++ w_n962_n458# a_138_n288# a_n298_n288# a_80_n200# a_356_n288# a_n516_n288# a_574_n288#
++ a_n734_n288# a_n138_n200# a_n356_n200# a_n574_n200# a_n80_n288#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X2 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X3 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X4 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X6 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n1806_2500# a_n4122_n2932# a_n5280_2500#
++ a_2054_n2932# a_896_n2932# a_4756_2500# a_3598_n2932# a_3212_2500# a_n3736_n2932#
++ a_1668_n2932# a_n1806_n2932# a_5142_n2932# a_896_2500# a_510_n2932# a_n3350_2500#
++ a_n4508_2500# a_3212_n2932# a_n4894_2500# a_1282_2500# w_n5446_n3098# a_4756_n2932#
++ a_2826_2500# a_2826_n2932# a_n2192_n2932# a_n1034_2500# a_n2578_2500# a_n1420_2500#
++ a_n2964_2500# a_n648_n2932# a_n648_2500# a_n5280_n2932# a_n3350_n2932# a_4370_2500#
++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_n4894_n2932# a_124_2500# a_n2964_n2932#
++ a_n4122_2500# a_2054_2500# a_510_2500# a_n4508_n2932# a_4370_n2932# a_3598_2500#
++ a_3984_2500# a_2440_n2932# a_2440_2500# a_3984_n2932# a_n2192_2500# a_n3736_2500#
++ a_1668_2500# a_n262_n2932# a_n262_2500# a_n1034_n2932# a_5142_2500# a_n2578_n2932#
+X0 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X1 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X2 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X3 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X4 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X5 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X6 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X7 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X8 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X9 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X10 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X11 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X12 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X13 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X14 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X15 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X16 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X17 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X18 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X19 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X20 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X21 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X22 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X23 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X24 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X25 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X26 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X27 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VPWR X VNB VPB
+X0 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X1 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X4 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
+X5 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
+X6 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X7 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW c1_n3036_n3000# m3_n3136_n3100#
+X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV a_n792_n200# a_138_n297# a_n298_n297#
++ a_298_n200# a_356_n297# a_n516_n297# a_574_n297# a_516_n200# a_n734_n297# a_734_n200#
++ a_n80_n297# a_80_n200# a_n138_n200# a_n356_n200# a_n574_n200# w_n992_n497#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X2 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X3 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X4 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X6 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__inv_8 A VGND VPWR Y VNB VPB
+X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X1 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X2 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X5 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X7 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X10 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.ends
+
+.subckt example_por vdd3v3 vss porb_h por_l porb_l vdd1v8
+Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_2_W5U4AW
+Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 porb_l vss vdd1v8
++ sky130_fd_sc_hvl__buf_8
+Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653#
++ vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653#
++ m1_502_7653# vdd3v3 vdd3v3 vdd3v3 m1_502_7653# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
+Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss vss m1_721_6815#
++ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
++ m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
+Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_3322_5813# li_1391_165# vss li_7567_165#
++ li_6023_165# vdd3v3 li_9111_165# li_8726_5813# li_1391_165# li_6795_165# li_3707_165#
++ vss li_6410_5813# li_6023_165# li_1778_5813# li_1006_5813# li_8339_165# vss li_6410_5813#
++ vss li_9883_165# li_7954_5813# li_8339_165# li_2935_165# li_4094_5813# li_2550_5813#
++ li_4094_5813# li_2550_5813# li_4479_165# li_4866_5813# vss li_2163_165# li_9498_5813#
++ li_6795_165# li_5251_165# li_3707_165# li_619_165# li_5638_5813# li_2163_165# li_1006_5813#
++ li_7182_5813# li_5638_5813# li_619_165# li_9883_165# li_8726_5813# li_9498_5813#
++ li_7567_165# li_7954_5813# li_9111_165# li_3322_5813# li_1778_5813# li_7182_5813#
++ li_5251_165# li_4866_5813# li_4479_165# vss li_2935_165# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 m1_185_6573# m1_721_6815# vdd3v3 m1_2993_7658#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vdd3v3 sky130_fd_sc_hvl__inv_8_0/A
++ vss vdd3v3 sky130_fd_sc_hvl__schmittbuf_1
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 m1_2756_6573# m1_4283_8081# vdd3v3 m1_2756_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 m1_2756_6573# sky130_fd_sc_hvl__schmittbuf_1_0/A
++ vdd3v3 m1_6249_7690# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 m1_185_6573# m1_502_7653# vdd3v3 m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 m1_4283_8081# m1_6249_7690# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
+Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_2756_6573# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
+Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss m1_185_6573# vss li_2550_5813# sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
+Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_1_WRT4AW
+Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
++ m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
++ vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 m1_502_7653# m1_2993_7658# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
+Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 por_l vss vdd1v8
++ sky130_fd_sc_hvl__inv_8
+Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd3v3 porb_h vss vdd3v3
++ sky130_fd_sc_hvl__buf_8
+.ends
+
+.subckt user_analog_proj_example example_por_0/por_l example_por_1/por_l example_por_1/vdd3v3
++ example_por_1/porb_l example_por_0/vdd3v3 example_por_1/porb_h example_por_0/porb_l
++ example_por_0/porb_h VSUBS example_por_0/vdd1v8 example_por_1/vdd1v8
+Xexample_por_0 example_por_0/vdd3v3 VSUBS example_por_0/porb_h example_por_0/por_l
++ example_por_0/porb_l example_por_0/vdd1v8 example_por
+Xexample_por_1 example_por_1/vdd3v3 VSUBS example_por_1/porb_h example_por_1/por_l
++ example_por_1/porb_l example_por_1/vdd1v8 example_por
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xuser_analog_proj_example_0 io_out[16] io_out[12] vdda1 io_out[11] io_analog[4] gpio_analog[3]
++ io_out[15] gpio_analog[7] vssa1 vccd1 vccd1 user_analog_proj_example
+R0 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+R1 io_oeb[15] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=600000u
+R2 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+R3 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 w=560000u l=580000u
+R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+R5 io_oeb[16] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=310000u
+R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+R7 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 w=560000u l=490000u
+R8 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+R9 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+.ends
+
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index c3851a3..e9036eb 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -1,217 +1,329 @@
* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
-.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW c2_n3079_n3000# m4_n3179_n3100#
-X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.subckt sky130_fd_pr__nfet_01v8_NDE37H a_15_n115# a_n118_22# a_n73_n115# VSUBS
+X0 a_15_n115# a_n118_22# a_n73_n115# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
.ends
-.subckt sky130_fd_sc_hvl__buf_8 A VGND VPWR X VNB VPB
-X0 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X2 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X3 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X4 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X5 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X9 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X10 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X12 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X15 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X16 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X18 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X19 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X20 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X21 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.subckt sky130_fd_pr__pfet_01v8_A7DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ a_n683_n200# a_n189_n297# a_29_n297# a_189_n200#
-+ a_n901_n200# a_247_n297# a_n407_n297# a_465_n297# a_407_n200# a_n625_n297# a_683_n297#
-+ a_625_n200# a_n843_n297# w_n1101_n497# a_843_n200# a_n29_n200# a_n247_n200# a_n465_n200#
-X0 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X7 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__nfet_01v8_PW5BNL a_15_n79# a_n73_37# a_n73_n79# VSUBS
+X0 a_15_n79# a_n73_37# a_n73_n79# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
.ends
-.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n792_n200# a_298_n200# a_516_n200# a_734_n200#
-+ w_n962_n458# a_138_n288# a_n298_n288# a_80_n200# a_356_n288# a_n516_n288# a_574_n288#
-+ a_n734_n288# a_n138_n200# a_n356_n200# a_n574_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__pfet_01v8_ACPHKB a_n33_37# a_15_n78# a_n73_n78# w_n109_n140#
+X0 a_15_n78# a_n33_37# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
.ends
-.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n1806_2500# a_n4122_n2932# a_n5280_2500#
-+ a_2054_n2932# a_896_n2932# a_4756_2500# a_3598_n2932# a_3212_2500# a_n3736_n2932#
-+ a_1668_n2932# a_n1806_n2932# a_5142_n2932# a_896_2500# a_510_n2932# a_n3350_2500#
-+ a_n4508_2500# a_3212_n2932# a_n4894_2500# a_1282_2500# w_n5446_n3098# a_4756_n2932#
-+ a_2826_2500# a_2826_n2932# a_n2192_n2932# a_n1034_2500# a_n2578_2500# a_n1420_2500#
-+ a_n2964_2500# a_n648_n2932# a_n648_2500# a_n5280_n2932# a_n3350_n2932# a_4370_2500#
-+ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_n4894_n2932# a_124_2500# a_n2964_n2932#
-+ a_n4122_2500# a_2054_2500# a_510_2500# a_n4508_n2932# a_4370_n2932# a_3598_2500#
-+ a_3984_2500# a_2440_n2932# a_2440_2500# a_3984_n2932# a_n2192_2500# a_n3736_2500#
-+ a_1668_2500# a_n262_n2932# a_n262_2500# a_n1034_n2932# a_5142_2500# a_n2578_n2932#
-X0 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X1 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X2 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X3 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X4 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X5 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X6 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X7 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X8 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X9 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X10 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X11 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X12 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X13 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X14 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X15 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X16 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X17 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X18 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X19 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X20 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X21 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X22 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X23 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X24 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X25 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X26 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
-X27 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.subckt FD_v2 Clk_In VDD GND Clk_Out
+Xsky130_fd_pr__nfet_01v8_NDE37H_0 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__nfet_01v8_NDE37H_1 6 Clkb 5 GND sky130_fd_pr__nfet_01v8_NDE37H
+Xsky130_fd_pr__pfet_01v8_A7DS5R_0 Clkb VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_1 3 VDD VDD 2 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_2 5 VDD VDD 4 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_3 2 VDD VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_5 Clk_Out VDD VDD 7 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__pfet_01v8_A7DS5R_4 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A7DS5R
+Xsky130_fd_pr__nfet_01v8_PW5BNL_1 3 2 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_0 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_2 5 4 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_3 2 6 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__nfet_01v8_PW5BNL_4 GND 6 7 GND sky130_fd_pr__nfet_01v8_PW5BNL
+Xsky130_fd_pr__pfet_01v8_ACPHKB_1 Clk_In 6 5 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__pfet_01v8_ACPHKB_0 Clkb 4 3 VDD sky130_fd_pr__pfet_01v8_ACPHKB
+Xsky130_fd_pr__nfet_01v8_PW5BNL_5 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8_PW5BNL
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__nfet_01v8_PW6BNL a_103_n163# a_191_n163# a_n73_n163# a_n73_37#
++ a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
.ends
-.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VPWR X VNB VPB
-X0 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X1 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
-X4 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
-X5 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
-X6 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X7 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+.subckt sky130_fd_pr__pfet_01v8_A4DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_455_n36# a_n73_n36# a_543_n36# a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_543_n36# a_n15_n133# a_455_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_455_n36# a_n15_n133# a_367_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X4 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X5 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X6 a_367_n36# a_n15_n133# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__nfet_01v8_PW7BNL a_n73_n163# a_n73_37# a_15_n163# VSUBS
+X0 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
.ends
-.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__nfet_01v8_PW8BNL a_103_n163# a_n73_n163# a_n73_37# a_15_n163#
++ VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
.ends
-.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
-X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__pfet_01v8_A8DS5R a_279_n36# a_15_n36# a_103_n36# a_n73_n36#
++ a_191_n36# w_n109_n86# a_n15_n133#
+X0 a_279_n36# a_n15_n133# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n133# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW c1_n3036_n3000# m3_n3136_n3100#
-X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.subckt sky130_fd_pr__pfet_01v8_A2DS5R a_279_n36# a_15_n36# a_103_n36# a_367_n36#
++ a_n15_n81# a_n73_n36# a_191_n36# w_n109_n86#
+X0 a_279_n36# a_n15_n81# a_191_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_103_n36# a_n15_n81# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X2 a_15_n36# a_n15_n81# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X3 a_191_n36# a_n15_n81# a_103_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.44e+06u l=150000u
+X4 a_367_n36# a_n15_n81# a_279_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=0p ps=0u w=1.44e+06u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV a_n792_n200# a_138_n297# a_n298_n297#
-+ a_298_n200# a_356_n297# a_n516_n297# a_574_n297# a_516_n200# a_n734_n297# a_734_n200#
-+ a_n80_n297# a_80_n200# a_n138_n200# a_n356_n200# a_n574_n200# w_n992_n497#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X1 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X2 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X3 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X4 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X5 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
-X6 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__pfet_01v8_A1DS5R a_15_n36# a_103_n36# a_n73_n36# w_n109_n86#
++ a_n15_n133#
+X0 a_103_n36# a_n15_n133# a_15_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+X1 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
.ends
-.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
-X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.subckt sky130_fd_pr__nfet_01v8_PW9BNL a_103_n163# a_279_n163# a_n15_n199# a_543_n163#
++ a_191_n163# a_n73_n163# a_367_n163# a_631_n163# a_15_n163# a_455_n163# VSUBS
+X0 a_543_n163# a_n15_n199# a_455_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_103_n163# a_n15_n199# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_279_n163# a_n15_n199# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_455_n163# a_n15_n199# a_367_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X4 a_631_n163# a_n15_n199# a_543_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X5 a_15_n163# a_n15_n199# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X6 a_367_n163# a_n15_n199# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_191_n163# a_n15_n199# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
.ends
-.subckt sky130_fd_sc_hvl__inv_8 A VGND VPWR Y VNB VPB
-X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X1 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X2 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X3 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X4 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X5 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X6 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X7 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X8 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X9 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X10 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X11 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X13 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
-X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
-X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.subckt sky130_fd_pr__pfet_01v8_A9DS5R a_15_n36# a_n73_n36# w_n109_n86# a_n15_n133#
+X0 a_15_n36# a_n15_n133# a_n73_n36# w_n109_n86# sky130_fd_pr__pfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
.ends
-.subckt example_por vdd3v3 vss porb_h por_l porb_l vdd1v8
-Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_2_W5U4AW
-Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 porb_l vss vdd1v8
-+ sky130_fd_sc_hvl__buf_8
-Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653#
-+ vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653#
-+ m1_502_7653# vdd3v3 vdd3v3 vdd3v3 m1_502_7653# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
-Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss vss m1_721_6815#
-+ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
-+ m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
-Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_3322_5813# li_1391_165# vss li_7567_165#
-+ li_6023_165# vdd3v3 li_9111_165# li_8726_5813# li_1391_165# li_6795_165# li_3707_165#
-+ vss li_6410_5813# li_6023_165# li_1778_5813# li_1006_5813# li_8339_165# vss li_6410_5813#
-+ vss li_9883_165# li_7954_5813# li_8339_165# li_2935_165# li_4094_5813# li_2550_5813#
-+ li_4094_5813# li_2550_5813# li_4479_165# li_4866_5813# vss li_2163_165# li_9498_5813#
-+ li_6795_165# li_5251_165# li_3707_165# li_619_165# li_5638_5813# li_2163_165# li_1006_5813#
-+ li_7182_5813# li_5638_5813# li_619_165# li_9883_165# li_8726_5813# li_9498_5813#
-+ li_7567_165# li_7954_5813# li_9111_165# li_3322_5813# li_1778_5813# li_7182_5813#
-+ li_5251_165# li_4866_5813# li_4479_165# vss li_2935_165# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 m1_185_6573# m1_721_6815# vdd3v3 m1_2993_7658#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vdd3v3 sky130_fd_sc_hvl__inv_8_0/A
-+ vss vdd3v3 sky130_fd_sc_hvl__schmittbuf_1
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 m1_2756_6573# m1_4283_8081# vdd3v3 m1_2756_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 m1_2756_6573# sky130_fd_sc_hvl__schmittbuf_1_0/A
-+ vdd3v3 m1_6249_7690# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 m1_185_6573# m1_502_7653# vdd3v3 m1_185_6573#
-+ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 m1_4283_8081# m1_6249_7690# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
-Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_2756_6573# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
-Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss m1_185_6573# vss li_2550_5813# sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
-Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_1_WRT4AW
-Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
-+ m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081#
-+ vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
-Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 m1_502_7653# m1_2993_7658# vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
-Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd1v8 por_l vss vdd1v8
-+ sky130_fd_sc_hvl__inv_8
-Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vdd3v3 porb_h vss vdd3v3
-+ sky130_fd_sc_hvl__buf_8
+.subckt sky130_fd_pr__nfet_01v8_PW4BNL a_103_n163# a_279_n163# a_191_n163# a_n73_n163#
++ a_n73_37# a_367_n163# a_15_n163# VSUBS
+X0 a_103_n163# a_n73_37# a_15_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X1 a_279_n163# a_n73_37# a_191_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X2 a_15_n163# a_n73_37# a_n73_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=2.436e+11p ps=2.26e+06u w=840000u l=150000u
+X3 a_367_n163# a_n73_37# a_279_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=2.436e+11p pd=2.26e+06u as=0p ps=0u w=840000u l=150000u
+X4 a_191_n163# a_n73_37# a_103_n163# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
.ends
-.subckt user_analog_proj_example example_por_0/por_l example_por_1/por_l example_por_1/vdd3v3
-+ example_por_1/porb_l example_por_0/vdd3v3 example_por_1/porb_h example_por_0/porb_l
-+ example_por_0/porb_h VSUBS example_por_0/vdd1v8 example_por_1/vdd1v8
-Xexample_por_0 example_por_0/vdd3v3 VSUBS example_por_0/porb_h example_por_0/por_l
-+ example_por_0/porb_l example_por_0/vdd1v8 example_por
-Xexample_por_1 example_por_1/vdd3v3 VSUBS example_por_1/porb_h example_por_1/por_l
-+ example_por_1/porb_l example_por_1/vdd1v8 example_por
+.subckt FD_v5 Clk_In VDD GND Clk_Out
+XMNinv2 GND 5 GND 4 5 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNinv1 GND 3 GND 2 3 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMNClkin GND Clk_In_buf GND Clkb_buf Clk_In_buf GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__nfet_01v8_PW6BNL_0 GND dus GND Clkb_int dus GND sky130_fd_pr__nfet_01v8_PW6BNL
+Xsky130_fd_pr__pfet_01v8_A4DS5R_0 VDD Clkb_buf VDD Clkb_buf VDD VDD Clkb_buf Clkb_buf
++ VDD dus sky130_fd_pr__pfet_01v8_A4DS5R
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8_PW7BNL
+XMNbuf2 GND GND 7 Clk_Out GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPfb VDD 2 VDD VDD 2 VDD 6 sky130_fd_pr__pfet_01v8_A8DS5R
+Xsky130_fd_pr__pfet_01v8_A2DS5R_0 VDD dus VDD dus Clkb_int VDD dus VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__pfet_01v8_A1DS5R_0 Clkb_int VDD VDD VDD Clk_In sky130_fd_pr__pfet_01v8_A1DS5R
+XMNfb GND 2 GND 6 2 GND sky130_fd_pr__nfet_01v8_PW6BNL
+XMPinv1 VDD 3 VDD VDD 3 VDD 2 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPinv2 VDD 5 VDD VDD 5 VDD 4 sky130_fd_pr__pfet_01v8_A8DS5R
+XMPClkin VDD Clk_In_buf VDD VDD Clk_In_buf VDD Clkb_buf sky130_fd_pr__pfet_01v8_A8DS5R
+XMPTgate1 3 4 3 4 Clkb_buf 3 4 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+Xsky130_fd_pr__nfet_01v8_PW8BNL_0 GND GND Clk_In Clkb_int GND sky130_fd_pr__nfet_01v8_PW8BNL
+XMPTgate2 5 6 5 6 Clk_In_buf 5 6 VDD sky130_fd_pr__pfet_01v8_A2DS5R
+XMNTgate1 3 3 Clk_In_buf 4 4 3 4 3 4 3 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf1 VDD 7 VDD 6 sky130_fd_pr__pfet_01v8_A9DS5R
+XMNTgate2 5 5 Clkb_buf 6 6 5 6 5 6 5 GND sky130_fd_pr__nfet_01v8_PW9BNL
+XMPbuf2 Clk_Out VDD VDD VDD 7 sky130_fd_pr__pfet_01v8_A1DS5R
+Xsky130_fd_pr__nfet_01v8_PW4BNL_0 GND GND Clkb_buf GND dus Clkb_buf Clkb_buf GND sky130_fd_pr__nfet_01v8_PW4BNL
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NC2CGG a_15_n240# w_n109_n340# a_n73_n240# a_n33_n337#
+X0 a_15_n240# a_n33_n337# a_n73_n240# w_n109_n340# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_UUCHZP a_n173_n220# a_n129_n366# a_n33_310# a_63_n366#
++ a_18_n220# a_114_n220# w_n209_n320# a_n78_n220#
+X0 a_114_n220# a_63_n366# a_18_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.49e+11p pd=4.99e+06u as=6.6e+11p ps=5e+06u w=2.2e+06u l=180000u
+X1 a_n78_n220# a_n129_n366# a_n173_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5e+06u as=6.49e+11p ps=4.99e+06u w=2.2e+06u l=180000u
+X2 a_18_n220# a_n33_310# a_n78_n220# w_n209_n320# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XZZ25Z a_18_n136# a_n33_95# w_n112_n198# a_n76_n136#
+X0 a_18_n136# a_n33_95# a_n76_n136# w_n112_n198# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_44BYND a_n73_n120# a_15_n120# a_n33_142# VSUBS
+X0 a_15_n120# a_n33_142# a_n73_n120# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TUVSF7 a_n33_n217# a_n76_n129# a_18_n129# VSUBS
+X0 a_18_n129# a_n33_n217# a_n76_n129# VSUBS sky130_fd_pr__nfet_01v8 ad=3.741e+11p pd=3.16e+06u as=3.741e+11p ps=3.16e+06u w=1.29e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_B87NCT a_n76_n69# a_18_n69# a_n33_n157# VSUBS
+X0 a_18_n69# a_n33_n157# a_n76_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NNRSEG a_18_n29# a_n33_n117# a_n76_n29# VSUBS
+X0 a_18_n29# a_n33_n117# a_n76_n29# VSUBS sky130_fd_pr__nfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_26QSQN a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_LS30AB a_n73_n80# a_n33_33# a_15_n80# VSUBS
+X0 a_15_n80# a_n33_33# a_n73_n80# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B w_n112_n170# a_n76_n108# a_18_n108# a_n33_67#
+X0 a_18_n108# a_n33_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_hvt_N83GLL a_n73_n100# a_15_n100# w_n109_n136# a_n15_n132#
+X0 a_15_n100# a_n15_n132# a_n73_n100# w_n109_n136# sky130_fd_pr__pfet_01v8_hvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_M34CP3 a_15_n96# a_n73_56# a_n73_n96# VSUBS
+X0 a_15_n96# a_n73_56# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.885e+11p pd=1.88e+06u as=1.885e+11p ps=1.88e+06u w=650000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HGTGXE_v2 a_18_n73# a_n18_n99# a_n76_n73# VSUBS
+X0 a_18_n73# a_n18_n99# a_n76_n73# VSUBS sky130_fd_pr__nfet_01v8 ad=1.218e+11p pd=1.42e+06u as=1.218e+11p ps=1.42e+06u w=420000u l=180000u
+.ends
+
+.subckt vco_switch_n_v2 in sel out vss vdd
+XXM25 vdd in out selb sky130_fd_pr__pfet_01v8_ACAZ2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_1 vss selb out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_TPJM7Z a_18_n276# w_n112_n338# a_n33_235# a_n76_n276#
+X0 a_18_n276# a_n33_235# a_n76_n276# w_n112_n338# sky130_fd_pr__pfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP1P4U a_n73_n144# a_n33_n241# a_15_n144# w_n109_n244#
+X0 a_15_n144# a_n33_n241# a_n73_n144# w_n109_n244# sky130_fd_pr__pfet_01v8 ad=4.06e+11p pd=3.38e+06u as=4.06e+11p ps=3.38e+06u w=1.4e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_TWMWTA a_n76_n209# a_18_n209# a_n33_n297# VSUBS
+X0 a_18_n209# a_n33_n297# a_n76_n209# VSUBS sky130_fd_pr__nfet_01v8 ad=6.96e+11p pd=5.38e+06u as=6.96e+11p ps=5.38e+06u w=2.4e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EMZ8SC a_n73_n103# a_15_n103# a_n33_63# VSUBS
+X0 a_15_n103# a_n33_63# a_n73_n103# VSUBS sky130_fd_pr__nfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP0P75 a_n73_n64# a_n33_n161# w_n109_n164# a_15_n64#
+X0 a_15_n64# a_n33_n161# a_n73_n64# w_n109_n164# sky130_fd_pr__pfet_01v8 ad=2.175e+11p pd=2.08e+06u as=2.175e+11p ps=2.08e+06u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MP0P50 a_n33_33# a_15_n96# a_n73_n96# VSUBS
+X0 a_15_n96# a_n33_33# a_n73_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MP3P0U a_n73_n236# w_n109_n298# a_n33_395# a_15_n236#
+X0 a_15_n236# a_n33_395# a_n73_n236# w_n109_n298# sky130_fd_pr__pfet_01v8 ad=8.7e+11p pd=6.58e+06u as=8.7e+11p ps=6.58e+06u w=3e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8T82FM a_n33_135# a_15_n175# a_n73_n175# VSUBS
+X0 a_15_n175# a_n33_135# a_n73_n175# VSUBS sky130_fd_pr__nfet_01v8 ad=4.176e+11p pd=3.46e+06u as=4.176e+11p ps=3.46e+06u w=1.44e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MV8TJR a_n76_n89# a_18_n89# a_n33_n177# VSUBS
+X0 a_18_n89# a_n33_n177# a_n76_n89# VSUBS sky130_fd_pr__nfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5YXW2B a_18_n72# w_n112_n134# a_n18_n98# a_n76_n72#
+X0 a_18_n72# a_n18_n98# a_n76_n72# w_n112_n134# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ACAZ2B_v2 w_n112_n170# a_n68_67# a_n76_n108# a_18_n108#
+X0 a_18_n108# a_n68_67# a_n76_n108# w_n112_n170# sky130_fd_pr__pfet_01v8 ad=2.088e+11p pd=2.02e+06u as=2.088e+11p ps=2.02e+06u w=720000u l=180000u
+.ends
+
+.subckt vco_switch_p in sel out vss vdd
+Xsky130_fd_pr__pfet_01v8_5YXW2B_0 vdd vdd sel out sky130_fd_pr__pfet_01v8_5YXW2B
+Xsky130_fd_pr__pfet_01v8_hvt_N83GLL_0 vdd selb vdd sel sky130_fd_pr__pfet_01v8_hvt_N83GLL
+Xsky130_fd_pr__pfet_01v8_ACAZ2B_v2_0 vdd selb in out sky130_fd_pr__pfet_01v8_ACAZ2B_v2
+Xsky130_fd_pr__nfet_01v8_M34CP3_0 selb sel vss vss sky130_fd_pr__nfet_01v8_M34CP3
+Xsky130_fd_pr__nfet_01v8_HGTGXE_v2_0 in sel out vss sky130_fd_pr__nfet_01v8_HGTGXE_v2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4XEGTB a_18_n96# w_n112_n158# a_n33_55# a_n76_n96#
+X0 a_18_n96# a_n33_55# a_n76_n96# w_n112_n158# sky130_fd_pr__pfet_01v8 ad=1.74e+11p pd=1.78e+06u as=1.74e+11p ps=1.78e+06u w=600000u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_KQRM7Z a_n76_n156# a_18_n156# w_n112_n218# a_n33_115#
+X0 a_18_n156# a_n33_115# a_n76_n156# w_n112_n218# sky130_fd_pr__pfet_01v8 ad=3.48e+11p pd=2.98e+06u as=3.48e+11p ps=2.98e+06u w=1.2e+06u l=180000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AZHELG w_n109_n58# a_15_n22# a_n72_n22# a_n15_n53#
+X0 a_15_n22# a_n15_n53# a_n72_n22# w_n109_n58# sky130_fd_pr__pfet_01v8 ad=2.32e+11p pd=2.18e+06u as=2.28e+11p ps=2.17e+06u w=800000u l=150000u
+.ends
+
+.subckt x3-stage_cs-vco_dp9 out vctrl sel0 sel1 sel3 sel2 vdd vss
+XXM12 net7 vdd vdd net6 sky130_fd_pr__pfet_01v8_NC2CGG
+XXM23 vdd net7 net7 net7 vdd out vdd out sky130_fd_pr__pfet_01v8_UUCHZP
+XXM25 vdd vgp vdd vgp sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM13 vss net7 net6 vss sky130_fd_pr__nfet_01v8_44BYND
+XXM24 net7 vss out vss sky130_fd_pr__nfet_01v8_TUVSF7
+XXM26 vgp vss vctrl vss sky130_fd_pr__nfet_01v8_B87NCT
+XXM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16D_1 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM22_0p42 vss net5 net6 vss sky130_fd_pr__nfet_01v8_LS30AB
+XXM16D_2 net8 vss ng3 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+Xvco_switch_n_v2_0 vctrl sel0 ng0 vss vdd vco_switch_n_v2
+XXMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_n_v2_1 vctrl sel1 ng1 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_2 vctrl sel2 ng2 vss vdd vco_switch_n_v2
+Xvco_switch_n_v2_3 vctrl sel3 ng3 vss vdd vco_switch_n_v2
+XXMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_XZZ25Z
+XXM1 net2 net5 net3 vdd sky130_fd_pr__pfet_01v8_MP1P4U
+XXMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8_B87NCT
+XXMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8_TWMWTA
+XXM2 net8 net3 net5 vss sky130_fd_pr__nfet_01v8_EMZ8SC
+XXM3 vdd net3 vdd net4 sky130_fd_pr__pfet_01v8_MP0P75
+XXM11D_1 net2 vdd pg3 vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM4 net3 net4 vss vss sky130_fd_pr__nfet_01v8_MP0P50
+XXM11D_2 vdd vdd pg3 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+XXM5 net5 vdd net4 vdd sky130_fd_pr__pfet_01v8_MP3P0U
+XXM6 net4 net5 vss vss sky130_fd_pr__nfet_01v8_8T82FM
+XXMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8_26QSQN
+XXM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8_NNRSEG
+XXM16B net8 vss ng1 vss sky130_fd_pr__nfet_01v8_MV8TJR
+XXM16C net8 vss ng2 vss sky130_fd_pr__nfet_01v8_26QSQN
+XXMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8_TPJM7Z
+Xvco_switch_p_0 vgp sel0 pg0 vss vdd vco_switch_p
+XXM11A vdd vdd pg0 net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11B vdd net2 vdd pg1 sky130_fd_pr__pfet_01v8_KQRM7Z
+Xvco_switch_p_2 vgp sel2 pg2 vss vdd vco_switch_p
+Xvco_switch_p_1 vgp sel1 pg1 vss vdd vco_switch_p
+XXM21 vdd net6 vdd net5 sky130_fd_pr__pfet_01v8_AZHELG
+Xvco_switch_p_3 vgp sel3 pg3 vss vdd vco_switch_p
+XXM11 vdd vdd vgp net2 sky130_fd_pr__pfet_01v8_4XEGTB
+XXM11C vdd vdd pg2 net2 sky130_fd_pr__pfet_01v8_TPJM7Z
+.ends
+
+.subckt vco_with_fdivs vctrl out_div128 vsel0 vsel1 vsel2 out_div256 sky130_fd_sc_hd__clkbuf_2_0/VGND
++ out_div128_buf out_div256_buf w_7680_n1770# a_8547_n771# sky130_fd_sc_hd__clkbuf_16_2/VNB
++ sky130_fd_sc_hd__clkbuf_16_2/VPB vsel3 sky130_fd_sc_hd__clkbuf_2_0/VPWR vdd vss
++ sky130_fd_sc_hd__clkbuf_16_3/VNB sky130_fd_sc_hd__clkbuf_16_3/VPB
+XFD_v2_3 FD_v2_3/Clk_In vdd vss FD_v2_4/Clk_In FD_v2
+XFD_v2_4 FD_v2_4/Clk_In vdd vss FD_v2_5/Clk_In FD_v2
+XFD_v2_5 FD_v2_5/Clk_In vdd vss FD_v2_6/Clk_In FD_v2
+XFD_v2_6 FD_v2_6/Clk_In vdd vss out_div128 FD_v2
+XFD_v2_7 out_div128 vdd vss out_div256 FD_v2
+XFD_v2_8 out_div256 vdd vss FD_v2_9/Clk_In FD_v2
+XFD_v2_9 FD_v2_9/Clk_In vdd vss FD_v2_9/Clk_Out FD_v2
+XFD_v5_0 out vdd vss FD_v2_1/Clk_In FD_v5
+X3-stage_cs-vco_dp9_0 out vctrl vsel0 vsel1 vsel3 vsel2 vdd vss x3-stage_cs-vco_dp9
+XFD_v2_1 FD_v2_1/Clk_In vdd vss FD_v2_2/Clk_In FD_v2
+XFD_v2_2 FD_v2_2/Clk_In vdd vss FD_v2_3/Clk_In FD_v2
.ends
.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
@@ -221,7 +333,7 @@
+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
-+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
+ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
+ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
+ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
@@ -320,17 +432,12 @@
+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+ wbs_stb_i wbs_we_i
-Xuser_analog_proj_example_0 io_out[16] io_out[12] vdda1 io_out[11] io_analog[4] gpio_analog[3]
-+ io_out[15] gpio_analog[7] vssa1 vccd1 vccd1 user_analog_proj_example
-R0 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R1 io_oeb[15] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=600000u
-R2 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R3 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 w=560000u l=580000u
-R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R5 io_oeb[16] vssd1 sky130_fd_pr__res_generic_m3 w=560000u l=310000u
-R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R7 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 w=560000u l=490000u
-R8 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
-R9 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 w=1.1e+07u l=250000u
+Xvco_with_fdivs_0 gpio_analog[9] vco_with_fdivs_0/out_div128 io_in[17] io_in[18] io_in[19]
++ vco_with_fdivs_0/out_div256 vssa1 gpio_analog[7] gpio_analog[8] vccd1 vssa1 vssa1
++ vccd1 io_in[20] vccd1 vccd1 vssa1 vssa1 vccd1 vco_with_fdivs
+R0 io_oeb[19] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R1 io_oeb[18] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R2 io_oeb[20] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
+R3 io_oeb[17] vccd1 sky130_fd_pr__res_generic_m3 w=560000u l=280000u
.ends
diff --git a/verilog/dv/verify.log b/verilog/dv/verify.log
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/verilog/dv/verify.log
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/unused/example_por.v
similarity index 100%
rename from verilog/rtl/example_por.v
rename to verilog/rtl/unused/example_por.v
diff --git a/verilog/rtl/unused/uprj_analog_netlists_-_copy_beforehand.v b/verilog/rtl/unused/uprj_analog_netlists_-_copy_beforehand.v
new file mode 100644
index 0000000..062a873
--- /dev/null
+++ b/verilog/rtl/unused/uprj_analog_netlists_-_copy_beforehand.v
@@ -0,0 +1,38 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ `default_nettype wire
+ // Use behavorial model with gate-level simulation
+ `include "rtl/user_analog_project_wrapper.v"
+ `include "rtl/user_analog_proj_example.v"
+`else
+ `include "user_analog_project_wrapper.v"
+ `include "user_analog_proj_example.v"
+`endif
diff --git a/verilog/rtl/unused/user_analog_proj_example_-_copy_beforehand.v b/verilog/rtl/unused/user_analog_proj_example_-_copy_beforehand.v
new file mode 100644
index 0000000..94412da
--- /dev/null
+++ b/verilog/rtl/unused/user_analog_proj_example_-_copy_beforehand.v
@@ -0,0 +1,221 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`include "example_por.v"
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module user_analog_proj_example (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+
+ wire isupply; // Independent 3.3V supply
+ wire io16, io15, io12, io11;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ assign io_out[12:11] = {io12, io11};
+ assign io_oeb[12:11] = {vssd1, vssd1};
+
+ assign io_out[16:15] = {io16, io15};
+ assign io_oeb[16:15] = {vssd1, vssd1};
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA --- unused (no need to connect to anything)
+ // assign la_data_out = {128{1'b0}}; // Unused
+
+ // Instantiate the POR. Connect the digital power to user area 1
+ // VCCD, and connect the analog power to user area 1 VDDA.
+
+ // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
+ // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
+
+ example_por por1 (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vdda1),
+ .vdd1v8(vccd1),
+ .vss(vssa1),
+ `endif
+ .porb_h(gpio_analog[3]), // 3.3V domain output
+ .porb_l(io11), // 1.8V domain output
+ .por_l(io12) // 1.8V domain output
+ );
+
+ // Instantiate 2nd POR with the analog power supply on one of the
+ // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
+ // pad with io_clamp_high/low[0].
+
+ `ifdef USE_POWER_PINS
+ assign isupply = io_analog[4];
+ assign io_clamp_high[0] = isupply;
+ assign io_clamp_low[0] = vssa1;
+
+ // Tie off remaining clamps
+ assign io_clamp_high[2:1] = vssa1;
+ assign io_clamp_low[2:1] = vssa1;
+ `endif
+
+ // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
+ // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
+
+ example_por por2 (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(isupply),
+ .vdd1v8(vccd1),
+ .vss(vssa1),
+ `endif
+ .porb_h(gpio_analog[7]), // 3.3V domain output
+ .porb_l(io15), // 1.8V domain output
+ .por_l(io16) // 1.8V domain output
+ );
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/unused/user_analog_project_wrapper_-_copy_beforehand.v b/verilog/rtl/unused/user_analog_project_wrapper_-_copy_beforehand.v
new file mode 100644
index 0000000..7a73f76
--- /dev/null
+++ b/verilog/rtl/unused/user_analog_project_wrapper_-_copy_beforehand.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+ .io_in (io_in),
+ .io_in_3v3 (io_in_3v3),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // GPIO-analog
+ .gpio_analog(gpio_analog),
+ .gpio_noesd(gpio_noesd),
+
+ // Dedicated analog
+ .io_analog(io_analog),
+ .io_clamp_high(io_clamp_high),
+ .io_clamp_low(io_clamp_low),
+
+ // Clock
+ .user_clock2(user_clock2),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_analog_project_wrapper
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
index 94412da..88cd270 100644
--- a/verilog/rtl/user_analog_proj_example.v
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -15,7 +15,9 @@
`default_nettype none
-`include "example_por.v"
+//`include "example_por.v"
+`include "vco_with_fdivs.v"
+
/*
* I/O mapping for analog
@@ -141,7 +143,10 @@
// wire [3:0] wstrb;
wire isupply; // Independent 3.3V supply
- wire io16, io15, io12, io11;
+
+//VCO: REMOVING THESE
+// wire io16, io15, io12, io11;
+
// WB MI A
// assign valid = wbs_cyc_i && wbs_stb_i;
@@ -158,12 +163,19 @@
// assign io_oeb[14:13] = 11'b1;
// assign io_oeb[10:0] = 11'b1;
- // IO --- enable outputs on 11, 12, 15, and 16
- assign io_out[12:11] = {io12, io11};
- assign io_oeb[12:11] = {vssd1, vssd1};
- assign io_out[16:15] = {io16, io15};
- assign io_oeb[16:15] = {vssd1, vssd1};
+//VCO: REMOVING THESE
+//
+// // IO --- enable outputs on 11, 12, 15, and 16
+// assign io_out[12:11] = {io12, io11};
+// assign io_oeb[12:11] = {vssd1, vssd1};
+//
+// assign io_out[16:15] = {io16, io15};
+// assign io_oeb[16:15] = {vssd1, vssd1};
+
+//VCO: I ADD THESE:
+ assign io_oeb[20:17] = {vccd1, vccd1, vccd1, vccd1};
+
// IRQ
assign irq = 3'b000; // Unused
@@ -177,43 +189,30 @@
// Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
// Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
- example_por por1 (
- `ifdef USE_POWER_PINS
- .vdd3v3(vdda1),
- .vdd1v8(vccd1),
- .vss(vssa1),
- `endif
- .porb_h(gpio_analog[3]), // 3.3V domain output
- .porb_l(io11), // 1.8V domain output
- .por_l(io12) // 1.8V domain output
- );
+// example_por por1 (
+// `ifdef USE_POWER_PINS
+// .vdd3v3(vdda1),
+// .vdd1v8(vccd1),
+// .vss(vssa1),
+// `endif
+// .porb_h(gpio_analog[3]), // 3.3V domain output
+// .porb_l(io11), // 1.8V domain output
+// .por_l(io12) // 1.8V domain output
+// );
- // Instantiate 2nd POR with the analog power supply on one of the
- // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
- // pad with io_clamp_high/low[0].
- `ifdef USE_POWER_PINS
- assign isupply = io_analog[4];
- assign io_clamp_high[0] = isupply;
- assign io_clamp_low[0] = vssa1;
-
- // Tie off remaining clamps
- assign io_clamp_high[2:1] = vssa1;
- assign io_clamp_low[2:1] = vssa1;
- `endif
-
- // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
- // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
-
- example_por por2 (
- `ifdef USE_POWER_PINS
- .vdd3v3(isupply),
- .vdd1v8(vccd1),
- .vss(vssa1),
- `endif
- .porb_h(gpio_analog[7]), // 3.3V domain output
- .porb_l(io15), // 1.8V domain output
- .por_l(io16) // 1.8V domain output
+ vco_with_fdivs vco_with_fdivs_0 (
+ `ifdef USE_POWER_PINS
+ .vdd(vccd1),
+ .vss(vssa1),
+ `endif
+ .vctrl(gpio_analog[9]),
+ .out_div128(gpio_analog[7]),
+ .out_div256(gpio_analog[8]),
+ .vsel0(io_in[17]),
+ .vsel1(io_in[18]),
+ .vsel2(io_in[19]),
+ .vsel3(io_in[20])
);
endmodule
diff --git a/verilog/rtl/vco_with_fdivs.v b/verilog/rtl/vco_with_fdivs.v
new file mode 100644
index 0000000..ff89c26
--- /dev/null
+++ b/verilog/rtl/vco_with_fdivs.v
@@ -0,0 +1,65 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module vco_with_fdivs(
+`ifdef USE_POWER_PINS
+ inout vdd,
+ inout vss,
+`endif
+ output out_div128,
+ output out_div256,
+ input vctrl,
+ input vsel0,
+ input vsel1,
+ input vsel2,
+ input vsel3
+);
+
+ //wire wire1;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd) begin
+ #500 inode <= 1'b0;
+ end
+
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ //assign por_l = ~porb_l;
+ assign out_div128 = vctrl;
+ assign out_div256 = vctrl;
+endmodule
+`default_nettype wire
diff --git a/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sch b/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sch
new file mode 100755
index 0000000..539b051
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sch
@@ -0,0 +1,846 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1350 -20 1350 40 { lab=vss}
+N 1350 40 1390 40 { lab=vss}
+N 3740 -600 3880 -600 { lab=out}
+N 2260 -1230 2260 -1160 { lab=vdd}
+N 2260 -1230 2300 -1230 { lab=vdd}
+N 780 -130 820 -130 { lab=vctrl}
+N 660 -130 780 -130 { lab=vctrl}
+N 860 -820 860 -400 { lab=vgp}
+N 900 -1030 920 -1030 { lab=vgp}
+N 920 -1030 920 -960 { lab=vgp}
+N 860 -960 920 -960 { lab=vgp}
+N 2420 -820 2420 -700 { lab=net2}
+N 860 -100 860 -20 { lab=vss}
+N 860 -130 890 -130 { lab=vss}
+N 890 -130 890 -20 { lab=vss}
+N 860 -20 890 -20 { lab=vss}
+N 1510 -100 1510 -20 { lab=vss}
+N 1510 -130 1540 -130 { lab=vss}
+N 1540 -130 1540 -20 { lab=vss}
+N 1510 -20 1540 -20 { lab=vss}
+N 2340 -1160 2340 -1060 { lab=vdd}
+N 2380 -1160 2380 -1030 { lab=vdd}
+N 2340 -1030 2380 -1030 { lab=vdd}
+N 2140 -20 3090 -20 { lab=vss}
+N 820 -1030 860 -1030 { lab=vdd}
+N 820 -1160 820 -1030 { lab=vdd}
+N 2100 -1160 2420 -1160 { lab=vdd}
+N 860 -1160 860 -1060 { lab=vdd}
+N 2420 -670 2470 -670 { lab=vdd}
+N 2900 -670 2950 -670 { lab=vdd}
+N 3060 -670 3110 -670 { lab=vdd}
+N 2420 -530 2470 -530 { lab=vss}
+N 2900 -530 2950 -530 { lab=vss}
+N 3060 -530 3110 -530 { lab=vss}
+N 2420 -640 2420 -560 { lab=net3}
+N 2900 -640 2900 -560 { lab=net4}
+N 3060 -640 3060 -560 { lab=net5}
+N 2360 -670 2380 -670 { lab=net5}
+N 2360 -670 2360 -530 { lab=net5}
+N 2360 -530 2380 -530 { lab=net5}
+N 2840 -670 2860 -670 { lab=net3}
+N 2840 -670 2840 -530 { lab=net3}
+N 2840 -530 2860 -530 { lab=net3}
+N 3000 -670 3020 -670 { lab=net4}
+N 3000 -670 3000 -530 { lab=net4}
+N 3000 -530 3020 -530 { lab=net4}
+N 2420 -600 2520 -600 { lab=net3}
+N 2900 -600 3000 -600 { lab=net4}
+N 3060 -600 3160 -600 { lab=net5}
+N 2300 -460 3160 -460 { lab=net5}
+N 2300 -600 2300 -460 { lab=net5}
+N 2300 -600 2360 -600 { lab=net5}
+N 3300 -640 3300 -560 { lab=net6}
+N 3220 -670 3260 -670 { lab=net5}
+N 3220 -530 3260 -530 { lab=net5}
+N 3220 -670 3220 -530 { lab=net5}
+N 3160 -600 3220 -600 { lab=net5}
+N 3300 -670 3350 -670 { lab=vdd}
+N 3300 -530 3350 -530 { lab=vss}
+N 3740 -640 3740 -560 { lab=out}
+N 3660 -670 3700 -670 { lab=net7}
+N 3660 -530 3700 -530 { lab=net7}
+N 3660 -670 3660 -530 { lab=net7}
+N 3740 -670 3790 -670 { lab=vdd}
+N 3740 -530 3790 -530 { lab=vss}
+N 3300 -600 3440 -600 { lab=net6}
+N 3090 -20 3520 -20 { lab=vss}
+N 3090 -1160 3510 -1160 { lab=vdd}
+N 3160 -600 3160 -460 { lab=net5}
+N 3520 -640 3520 -560 { lab=net7}
+N 3440 -670 3480 -670 { lab=net6}
+N 3440 -530 3480 -530 { lab=net6}
+N 3440 -670 3440 -530 { lab=net6}
+N 3520 -670 3570 -670 { lab=vdd}
+N 3520 -530 3570 -530 { lab=vss}
+N 3520 -600 3660 -600 { lab=net7}
+N 3510 -1160 3730 -1160 { lab=vdd}
+N 3520 -20 3740 -20 { lab=vss}
+N 2890 180 2890 260 { lab=vss}
+N 2890 150 2920 150 { lab=vss}
+N 2920 150 2920 260 { lab=vss}
+N 2890 260 2920 260 { lab=vss}
+N 2890 90 2890 120 { lab=vss}
+N 2890 90 2920 90 { lab=vss}
+N 2920 90 2920 150 { lab=vss}
+N 2830 150 2850 150 { lab=vss}
+N 2830 150 2830 260 { lab=vss}
+N 2830 260 2890 260 { lab=vss}
+N 1460 190 1460 270 { lab=vss}
+N 1460 160 1490 160 { lab=vss}
+N 1490 160 1490 270 { lab=vss}
+N 1460 270 1490 270 { lab=vss}
+N 1460 100 1460 130 { lab=vss}
+N 1460 100 1490 100 { lab=vss}
+N 1490 100 1490 160 { lab=vss}
+N 1400 160 1420 160 { lab=vss}
+N 1400 160 1400 270 { lab=vss}
+N 1400 270 1460 270 { lab=vss}
+N 770 170 770 250 { lab=vss}
+N 770 140 800 140 { lab=vss}
+N 800 140 800 250 { lab=vss}
+N 770 250 800 250 { lab=vss}
+N 770 80 770 110 { lab=vss}
+N 770 80 800 80 { lab=vss}
+N 800 80 800 140 { lab=vss}
+N 710 140 730 140 { lab=vss}
+N 710 140 710 250 { lab=vss}
+N 710 250 770 250 { lab=vss}
+N 2840 -1320 2870 -1320 { lab=vdd}
+N 2870 -1400 2870 -1320 { lab=vdd}
+N 2840 -1400 2870 -1400 { lab=vdd}
+N 2840 -1400 2840 -1350 { lab=vdd}
+N 2840 -1290 2840 -1260 { lab=vdd}
+N 2840 -1260 2870 -1260 { lab=vdd}
+N 2870 -1320 2870 -1260 { lab=vdd}
+N 2780 -1320 2800 -1320 { lab=vdd}
+N 2780 -1400 2780 -1320 { lab=vdd}
+N 2780 -1400 2840 -1400 { lab=vdd}
+N 1420 -1300 1450 -1300 { lab=vdd}
+N 1450 -1380 1450 -1300 { lab=vdd}
+N 1420 -1380 1450 -1380 { lab=vdd}
+N 1420 -1380 1420 -1330 { lab=vdd}
+N 1420 -1270 1420 -1240 { lab=vdd}
+N 1420 -1240 1450 -1240 { lab=vdd}
+N 1450 -1300 1450 -1240 { lab=vdd}
+N 1360 -1300 1380 -1300 { lab=vdd}
+N 1360 -1380 1360 -1300 { lab=vdd}
+N 1360 -1380 1420 -1380 { lab=vdd}
+N 750 -1310 780 -1310 { lab=vdd}
+N 780 -1390 780 -1310 { lab=vdd}
+N 750 -1390 780 -1390 { lab=vdd}
+N 750 -1390 750 -1340 { lab=vdd}
+N 750 -1280 750 -1250 { lab=vdd}
+N 750 -1250 780 -1250 { lab=vdd}
+N 780 -1310 780 -1250 { lab=vdd}
+N 690 -1310 710 -1310 { lab=vdd}
+N 690 -1390 690 -1310 { lab=vdd}
+N 690 -1390 750 -1390 { lab=vdd}
+N 2490 -600 2490 -590 { lab=net3}
+N 2470 -530 2490 -530 { lab=vss}
+N 2970 -600 2970 -590 { lab=net4}
+N 2950 -530 2970 -530 { lab=vss}
+N 3130 -600 3130 -590 { lab=net5}
+N 3110 -530 3130 -530 { lab=vss}
+N 2520 -600 2680 -600 { lab=net3}
+N 2680 -600 2730 -600 { lab=net3}
+N 2730 -600 2840 -600 { lab=net3}
+N 950 170 950 250 { lab=vss}
+N 950 140 980 140 { lab=vss}
+N 980 140 980 250 { lab=vss}
+N 950 250 980 250 { lab=vss}
+N 950 80 950 110 { lab=vss}
+N 950 80 980 80 { lab=vss}
+N 980 80 980 140 { lab=vss}
+N 890 140 910 140 { lab=vss}
+N 890 140 890 250 { lab=vss}
+N 890 250 950 250 { lab=vss}
+N 910 -1310 940 -1310 { lab=vdd}
+N 940 -1390 940 -1310 { lab=vdd}
+N 910 -1390 940 -1390 { lab=vdd}
+N 910 -1390 910 -1340 { lab=vdd}
+N 910 -1280 910 -1250 { lab=vdd}
+N 910 -1250 940 -1250 { lab=vdd}
+N 940 -1310 940 -1250 { lab=vdd}
+N 850 -1310 870 -1310 { lab=vdd}
+N 850 -1390 850 -1310 { lab=vdd}
+N 850 -1390 910 -1390 { lab=vdd}
+N 820 -1160 980 -1160 { lab=vdd}
+N 1410 -130 1470 -130 { lab=ng0}
+N 1330 -80 1330 -20 { lab=vss}
+N 1230 -130 1250 -130 { lab=vctrl}
+N 1230 -240 1230 -130 { lab=vctrl}
+N 990 -240 1230 -240 { lab=vctrl}
+N 780 -240 780 -130 { lab=vctrl}
+N 1920 -100 1920 -20 { lab=vss}
+N 1920 -130 1950 -130 { lab=vss}
+N 1950 -130 1950 -20 { lab=vss}
+N 1920 -20 1950 -20 { lab=vss}
+N 1820 -130 1880 -130 { lab=ng1}
+N 1740 -80 1740 -20 { lab=vss}
+N 1640 -130 1660 -130 { lab=vctrl}
+N 1640 -240 1640 -130 { lab=vctrl}
+N 2320 -100 2320 -20 { lab=vss}
+N 2320 -130 2350 -130 { lab=vss}
+N 2350 -130 2350 -20 { lab=vss}
+N 2320 -20 2350 -20 { lab=vss}
+N 2220 -130 2280 -130 { lab=ng2}
+N 2140 -80 2140 -20 { lab=vss}
+N 2040 -130 2060 -130 { lab=vctrl}
+N 2040 -240 2040 -130 { lab=vctrl}
+N 2720 -100 2720 -20 { lab=vss}
+N 2720 -130 2750 -130 { lab=vss}
+N 2750 -130 2750 -20 { lab=vss}
+N 2720 -20 2750 -20 { lab=vss}
+N 2620 -130 2680 -130 { lab=ng3}
+N 2540 -80 2540 -20 { lab=vss}
+N 2440 -130 2460 -130 { lab=vctrl}
+N 2440 -240 2440 -130 { lab=vctrl}
+N 1100 -20 2140 -20 { lab=vss}
+N 1230 -240 2440 -240 { lab=vctrl}
+N 1510 -320 1510 -160 { lab=net8}
+N 1920 -320 1920 -160 { lab=net8}
+N 2320 -320 2320 -160 { lab=net8}
+N 2720 -320 2720 -160 { lab=net8}
+N 1510 -320 2720 -320 { lab=net8}
+N 2420 -500 2420 -320 { lab=net8}
+N 1330 -220 1330 -180 { lab=vdd}
+N 1740 -220 1740 -180 { lab=vdd}
+N 2140 -220 2140 -180 { lab=vdd}
+N 2540 -220 2540 -180 { lab=vdd}
+N 1190 -110 1250 -110 { lab=sel0}
+N 1600 -110 1660 -110 { lab=sel1}
+N 2000 -110 2060 -110 { lab=sel2}
+N 2400 -110 2460 -110 { lab=sel3}
+N 2240 -1030 2300 -1030 { lab=pg2}
+N 2160 -1120 2160 -1080 { lab=vdd}
+N 2020 -1010 2080 -1010 { lab=sel2}
+N 2160 -980 2160 -940 { lab=vss}
+N 2060 -1030 2080 -1030 { lab=vgp}
+N 2060 -1030 2060 -920 { lab=vgp}
+N 2340 -820 2420 -820 { lab=net2}
+N 2340 -1000 2340 -820 { lab=net2}
+N 2420 -820 2600 -820 { lab=net2}
+N 1680 -820 2340 -820 { lab=net2}
+N 2760 -1160 2760 -1060 { lab=vdd}
+N 2760 -1160 2800 -1160 { lab=vdd}
+N 2800 -1160 2800 -1030 { lab=vdd}
+N 2760 -1030 2800 -1030 { lab=vdd}
+N 2660 -1030 2720 -1030 { lab=pg3}
+N 2580 -1120 2580 -1080 { lab=vdd}
+N 2440 -1010 2500 -1010 { lab=sel3}
+N 2580 -980 2580 -940 { lab=vss}
+N 2480 -1030 2500 -1030 { lab=vgp}
+N 2480 -1030 2480 -920 { lab=vgp}
+N 2760 -1000 2760 -820 { lab=net2}
+N 3730 -1160 3740 -1160 { lab=vdd}
+N 2600 -820 2760 -820 { lab=net2}
+N 1240 -920 2480 -920 { lab=vgp}
+N 1920 -1160 1920 -1060 { lab=vdd}
+N 1960 -1160 1960 -1030 { lab=vdd}
+N 1920 -1030 1960 -1030 { lab=vdd}
+N 1820 -1030 1880 -1030 { lab=pg1}
+N 1740 -1120 1740 -1080 { lab=vdd}
+N 1600 -1010 1660 -1010 { lab=sel1}
+N 1740 -980 1740 -940 { lab=vss}
+N 1640 -1030 1660 -1030 { lab=vgp}
+N 1640 -1030 1640 -920 { lab=vgp}
+N 1920 -1000 1920 -820 { lab=net2}
+N 1520 -1160 1520 -1060 { lab=vdd}
+N 1520 -1160 1560 -1160 { lab=vdd}
+N 1560 -1160 1560 -1030 { lab=vdd}
+N 1520 -1030 1560 -1030 { lab=vdd}
+N 1420 -1030 1480 -1030 { lab=pg0}
+N 1340 -1120 1340 -1080 { lab=vdd}
+N 1200 -1010 1260 -1010 { lab=sel0}
+N 1340 -980 1340 -940 { lab=vss}
+N 1240 -1030 1260 -1030 { lab=vgp}
+N 1240 -1030 1240 -920 { lab=vgp}
+N 1520 -1000 1520 -820 { lab=net2}
+N 1520 -820 1680 -820 { lab=net2}
+N 860 -1000 860 -820 { lab=vgp}
+N 1170 -1160 3090 -1160 { lab=vdd}
+N 860 -400 860 -160 { lab=vgp}
+N 780 -240 800 -240 { lab=vctrl}
+N 890 -20 910 -20 { lab=vss}
+N 3740 -1160 3740 -700 { lab=vdd}
+N 3520 -1160 3520 -700 { lab=vdd}
+N 3300 -1160 3300 -700 { lab=vdd}
+N 3060 -1160 3060 -700 { lab=vdd}
+N 2900 -1160 2900 -700 { lab=vdd}
+N 3060 -500 3060 -20 { lab=vss}
+N 2900 -500 2900 -20 { lab=vss}
+N 3300 -500 3300 -20 { lab=vss}
+N 3520 -500 3520 -20 { lab=vss}
+N 3740 -500 3740 -20 { lab=vss}
+N 570 -320 650 -320 { lab=sel0}
+N 570 -290 650 -290 { lab=sel1}
+N 570 -260 650 -260 { lab=sel2}
+N 570 -230 650 -230 { lab=sel3}
+N 910 -20 1100 -20 { lab=vss}
+N 800 -240 990 -240 { lab=vctrl}
+N 1070 -100 1070 -20 { lab=vss}
+N 1070 -130 1100 -130 { lab=vss}
+N 1100 -130 1100 -20 { lab=vss}
+N 1070 -20 1100 -20 { lab=vss}
+N 1070 -320 1070 -160 { lab=net8}
+N 980 -130 1030 -130 { lab=vctrl}
+N 980 -240 980 -130 { lab=vctrl}
+N 1070 -320 1510 -320 { lab=net8}
+N 1080 -1160 1080 -1060 { lab=vdd}
+N 1080 -1160 1120 -1160 { lab=vdd}
+N 1120 -1160 1120 -1030 { lab=vdd}
+N 1080 -1030 1120 -1030 { lab=vdd}
+N 1080 -1000 1080 -820 { lab=net2}
+N 1000 -1030 1000 -920 { lab=vgp}
+N 920 -1030 960 -1030 { lab=vgp}
+N 1000 -1030 1040 -1030 { lab=vgp}
+N 980 -1160 1170 -1160 { lab=vdd}
+N 1000 -920 1240 -920 { lab=vgp}
+N 960 -1030 1000 -1030 { lab=vgp}
+N 1080 -820 1520 -820 { lab=net2}
+C {iopin.sym} 2300 -1230 0 0 {name=p2 lab=vdd}
+C {iopin.sym} 1390 40 0 0 {name=p3 lab=vss}
+C {opin.sym} 3880 -600 0 0 {name=p4 lab=out}
+C {sky130_fd_pr/pfet_01v8.sym} 880 -1030 0 1 {name=M25
+L=0.18
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 840 -130 0 0 {name=M26
+L=0.18
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2320 -1030 0 0 {name=M11C
+L=0.18
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1490 -130 0 0 {name=M16A
+L=0.18
+W=0.6
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2400 -670 0 0 {name=M1
+L=0.15
+W=1.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2880 -670 0 0 {name=M3
+L=0.15
+W=0.75
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3040 -670 0 0 {name=M5
+L=0.15
+W=3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2400 -530 0 0 {name=M2
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2880 -530 0 0 {name=M4
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3040 -530 0 0 {name=M6
+L=0.15
+W=1.44
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 660 -130 0 0 {name=p5 lab=vctrl}
+C {lab_wire.sym} 2470 -670 0 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2950 -670 0 0 {name=l2 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3110 -670 0 0 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2470 -530 0 0 {name=l6 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 2950 -530 0 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3110 -530 0 0 {name=l8 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 3280 -670 0 0 {name=M21
+L=0.15
+W=0.8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3280 -530 0 0 {name=M22
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3720 -670 0 0 {name=M23
+L=0.18
+W=6.6
+nf=3
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3720 -530 0 0 {name=M24
+L=0.18
+W=1.29
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 3350 -670 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3790 -670 0 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3350 -530 0 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3790 -530 0 0 {name=l14 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 3500 -670 0 0 {name=M12
+L=0.15
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3500 -530 0 0 {name=M13
+L=0.15
+W=1.2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 3570 -670 0 0 {name=l4 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3570 -530 0 0 {name=l5 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 2870 150 0 0 {name=MDUM16B
+L=0.18
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1440 160 0 0 {name=MDUM16
+L=0.18
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 750 140 0 0 {name=MDUM26
+L=0.18
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 730 140 0 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1410 160 0 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 2840 150 0 0 {name=l15 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 2820 -1320 0 0 {name=MDUM11B
+L=0.18
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2830 -1400 0 0 {name=l16 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 1400 -1300 0 0 {name=MDUM11
+L=0.18
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1410 -1380 0 0 {name=l17 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 730 -1310 0 0 {name=MDUM25
+L=0.18
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 740 -1390 0 0 {name=l18 sig_type=std_logic lab=vdd}
+C {capa.sym} 2490 -560 0 0 {name=Cnet8
+m=1
+value=0.87f
+footprint=1206
+device="ceramic capacitor"}
+C {capa.sym} 2970 -560 0 0 {name=Cnet9
+m=1
+value=1.14f
+footprint=1206
+device="ceramic capacitor"}
+C {capa.sym} 3130 -560 0 0 {name=Cnet10
+m=1
+value=3.49f
+footprint=1206
+device="ceramic capacitor"}
+C {sky130_fd_pr/nfet_01v8.sym} 930 140 0 0 {name=MDUM26B
+L=0.18
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 910 140 0 0 {name=l23 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 890 -1310 0 0 {name=MDUM25B
+L=0.18
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 900 -1390 0 0 {name=l24 sig_type=std_logic lab=vdd}
+C {vco_switch_n.sym} 1330 -130 0 0 {name=x1n}
+C {sky130_fd_pr/nfet_01v8.sym} 1900 -130 0 0 {name=M16B
+L=0.18
+W=1.2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {vco_switch_n.sym} 1740 -130 0 0 {name=x2n}
+C {sky130_fd_pr/nfet_01v8.sym} 2300 -130 0 0 {name=M16C
+L=0.18
+W=2.4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {vco_switch_n.sym} 2140 -130 0 0 {name=x3n}
+C {sky130_fd_pr/nfet_01v8.sym} 2700 -130 0 0 {name=M16D
+L=0.18
+W=2.4
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {vco_switch_n.sym} 2540 -130 0 0 {name=x4n}
+C {lab_wire.sym} 1330 -200 0 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1740 -200 0 0 {name=l22 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2140 -200 0 0 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2540 -200 0 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1220 -110 0 0 {name=l27 sig_type=std_logic lab=sel0}
+C {lab_wire.sym} 1630 -110 0 0 {name=l28 sig_type=std_logic lab=sel1}
+C {lab_wire.sym} 2030 -110 0 0 {name=l29 sig_type=std_logic lab=sel2}
+C {lab_wire.sym} 2430 -110 0 0 {name=l30 sig_type=std_logic lab=sel3}
+C {vco_switch_p.sym} 2160 -1030 0 0 {name=x3p}
+C {lab_wire.sym} 2160 -1100 0 0 {name=l19 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2050 -1010 0 0 {name=l20 sig_type=std_logic lab=sel2}
+C {lab_wire.sym} 2160 -950 0 0 {name=l31 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 2740 -1030 0 0 {name=M11D
+L=0.18
+W=2.4
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {vco_switch_p.sym} 2580 -1030 0 0 {name=x4p}
+C {lab_wire.sym} 2580 -1100 0 0 {name=l32 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2470 -1010 0 0 {name=l33 sig_type=std_logic lab=sel3}
+C {lab_wire.sym} 2580 -950 0 0 {name=l34 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 1900 -1030 0 0 {name=M11B
+L=0.18
+W=1.2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {vco_switch_p.sym} 1740 -1030 0 0 {name=x2p}
+C {lab_wire.sym} 1740 -1100 0 0 {name=l35 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1630 -1010 0 0 {name=l36 sig_type=std_logic lab=sel1}
+C {lab_wire.sym} 1740 -950 0 0 {name=l37 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 1500 -1030 0 0 {name=M11A
+L=0.18
+W=0.6
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {vco_switch_p.sym} 1340 -1030 0 0 {name=x1p}
+C {lab_wire.sym} 1340 -1100 0 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1230 -1010 0 0 {name=l39 sig_type=std_logic lab=sel0}
+C {lab_wire.sym} 1340 -950 0 0 {name=l40 sig_type=std_logic lab=vss}
+C {ipin.sym} 570 -320 0 0 {name=p1 lab=sel0}
+C {lab_wire.sym} 630 -320 0 0 {name=l41 sig_type=std_logic lab=sel0}
+C {ipin.sym} 570 -290 0 0 {name=p6 lab=sel1}
+C {lab_wire.sym} 630 -290 0 0 {name=l42 sig_type=std_logic lab=sel1}
+C {ipin.sym} 570 -260 0 0 {name=p7 lab=sel2}
+C {lab_wire.sym} 630 -260 0 0 {name=l43 sig_type=std_logic lab=sel2}
+C {ipin.sym} 570 -230 0 0 {name=p8 lab=sel3}
+C {lab_wire.sym} 630 -230 0 0 {name=l44 sig_type=std_logic lab=sel3}
+C {lab_wire.sym} 860 -930 0 0 {name=l45 sig_type=std_logic lab=vgp}
+C {lab_wire.sym} 2650 -600 0 0 {name=l46 sig_type=std_logic lab=net3}
+C {lab_wire.sym} 2960 -600 0 0 {name=l47 sig_type=std_logic lab=net4}
+C {lab_wire.sym} 3200 -600 0 0 {name=l48 sig_type=std_logic lab=net5}
+C {lab_wire.sym} 3400 -600 0 0 {name=l49 sig_type=std_logic lab=net6}
+C {lab_wire.sym} 3610 -600 0 0 {name=l50 sig_type=std_logic lab=net7}
+C {lab_wire.sym} 2420 -780 0 0 {name=l51 sig_type=std_logic lab=net2}
+C {lab_wire.sym} 2420 -420 0 0 {name=l52 sig_type=std_logic lab=net8}
+C {lab_wire.sym} 1450 -130 0 0 {name=l53 sig_type=std_logic lab=ng0}
+C {lab_wire.sym} 1860 -130 0 0 {name=l54 sig_type=std_logic lab=ng1}
+C {lab_wire.sym} 2260 -130 0 0 {name=l55 sig_type=std_logic lab=ng2}
+C {lab_wire.sym} 2660 -130 0 0 {name=l56 sig_type=std_logic lab=ng3}
+C {lab_wire.sym} 1460 -1030 0 0 {name=l57 sig_type=std_logic lab=pg0}
+C {lab_wire.sym} 1860 -1030 0 0 {name=l58 sig_type=std_logic lab=pg1}
+C {lab_wire.sym} 2280 -1030 0 0 {name=l59 sig_type=std_logic lab=pg2}
+C {lab_wire.sym} 2700 -1030 0 0 {name=l60 sig_type=std_logic lab=pg3}
+C {sky130_fd_pr/nfet_01v8.sym} 1050 -130 0 0 {name=M16
+L=0.18
+W=0.6
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1060 -1030 0 0 {name=M11
+L=0.18
+W=0.6
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
diff --git a/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sym b/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sym
new file mode 100755
index 0000000..3edf36f
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sym
@@ -0,0 +1,39 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -30 -60 30 {}
+L 4 60 -30 60 30 {}
+L 4 60 0 80 0 {}
+L 4 -80 -20 -60 -20 {}
+L 4 -60 -30 60 -30 {}
+L 4 -60 30 60 30 {}
+L 4 -80 -10 -60 -10 {}
+L 4 -80 0 -60 0 {}
+L 4 -80 10 -60 10 {}
+L 4 -80 20 -60 20 {}
+L 7 0 -50 0 -30 {}
+L 7 0 30 0 50 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=out dir=out }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=vctrl dir=in }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout }
+B 5 -82.5 -12.5 -77.5 -7.5 {name=sel0 dir=in }
+B 5 -82.5 -2.5 -77.5 2.5 {name=sel1 dir=in }
+B 5 -82.5 7.5 -77.5 12.5 {name=sel2 dir=in }
+B 5 -82.5 17.5 -77.5 22.5 {name=sel3 dir=in }
+T {@symname} -31.5 -6 0 0 0.3 0.3 {}
+T {@name} 35 -42 0 0 0.2 0.2 {}
+T {vdd} 5 -24 0 1 0.2 0.2 {}
+T {out} 55 -4 0 1 0.2 0.2 {}
+T {vctrl} -55 -24 0 0 0.2 0.2 {}
+T {vss} 5 16 0 1 0.2 0.2 {}
+T {sel0} -55 -14 0 0 0.2 0.2 {}
+T {sel1} -55 -4 0 0 0.2 0.2 {}
+T {sel2} -55 6 0 0 0.2 0.2 {}
+T {sel3} -55 16 0 0 0.2 0.2 {}
diff --git a/xschem/3-stage_cs-vco_dp9/FD.sch b/xschem/3-stage_cs-vco_dp9/FD.sch
new file mode 100755
index 0000000..94f915e
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/FD.sch
@@ -0,0 +1,368 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 2730 -430 2780 -430 { lab=VDD}
+N 2730 -290 2780 -290 { lab=GND}
+N 2730 -400 2730 -320 { lab=7}
+N 2670 -430 2690 -430 { lab=6}
+N 2670 -430 2670 -290 { lab=6}
+N 2670 -290 2690 -290 { lab=6}
+N 2730 -520 2730 -460 { lab=VDD}
+N 2730 -260 2730 -200 { lab=GND}
+N 2730 -360 2950 -360 { lab=7}
+N 2570 -360 2670 -360 { lab=6}
+N 340 -420 390 -420 { lab=VDD}
+N 340 -280 390 -280 { lab=GND}
+N 280 -420 300 -420 { lab=6}
+N 280 -420 280 -280 { lab=6}
+N 280 -280 300 -280 { lab=6}
+N 340 -510 340 -450 { lab=VDD}
+N 340 -250 340 -170 { lab=GND}
+N 200 -350 280 -350 { lab=6}
+N 340 110 390 110 { lab=VDD}
+N 340 250 390 250 { lab=GND}
+N 280 110 300 110 { lab=Clk_In}
+N 280 110 280 250 { lab=Clk_In}
+N 280 250 300 250 { lab=Clk_In}
+N 340 20 340 80 { lab=VDD}
+N 340 280 340 360 { lab=GND}
+N 200 180 280 180 { lab=Clk_In}
+N 1700 -420 1750 -420 { lab=VDD}
+N 1700 -280 1750 -280 { lab=GND}
+N 1640 -420 1660 -420 { lab=4}
+N 1640 -420 1640 -280 { lab=4}
+N 1640 -280 1660 -280 { lab=4}
+N 1700 -510 1700 -450 { lab=VDD}
+N 1700 -250 1700 -170 { lab=GND}
+N 1560 -350 1640 -350 { lab=4}
+N 780 -420 830 -420 { lab=VDD}
+N 780 -280 830 -280 { lab=GND}
+N 720 -420 740 -420 { lab=2}
+N 720 -420 720 -280 { lab=2}
+N 720 -280 740 -280 { lab=2}
+N 780 -510 780 -450 { lab=VDD}
+N 780 -250 780 -170 { lab=GND}
+N 640 -350 720 -350 { lab=2}
+N 1220 -320 1220 -270 { lab=VDD}
+N 1220 -450 1220 -400 { lab=GND}
+N 1110 -450 1190 -450 { lab=3}
+N 1110 -270 1190 -270 { lab=3}
+N 1110 -450 1110 -270 { lab=3}
+N 1250 -450 1330 -450 { lab=4}
+N 1250 -270 1330 -270 { lab=4}
+N 1330 -450 1330 -270 { lab=4}
+N 1030 -350 1110 -350 { lab=3}
+N 1330 -350 1410 -350 { lab=4}
+N 1220 -540 1220 -490 { lab=Clk_In}
+N 1220 -230 1220 -180 { lab=Clkb}
+N 2170 -330 2170 -280 { lab=VDD}
+N 2170 -460 2170 -410 { lab=GND}
+N 2060 -460 2140 -460 { lab=5}
+N 2060 -280 2140 -280 { lab=5}
+N 2060 -460 2060 -280 { lab=5}
+N 2200 -460 2280 -460 { lab=6}
+N 2200 -280 2280 -280 { lab=6}
+N 2280 -460 2280 -280 { lab=6}
+N 1980 -360 2060 -360 { lab=5}
+N 2280 -360 2360 -360 { lab=6}
+N 2170 -550 2170 -500 { lab=Clkb}
+N 2170 -240 2170 -190 { lab=Clk_In}
+N 1700 -390 1700 -310 { lab=5}
+N 1700 -350 1820 -350 { lab=5}
+N 780 -390 780 -310 { lab=3}
+N 780 -350 920 -350 { lab=3}
+N 340 -390 340 -310 { lab=2}
+N 340 -350 500 -350 { lab=2}
+N 340 140 340 220 { lab=Clkb}
+N 340 180 480 180 { lab=Clkb}
+N 3200 -430 3250 -430 { lab=VDD}
+N 3200 -290 3250 -290 { lab=GND}
+N 3200 -400 3200 -320 { lab=Clk_Out}
+N 3140 -430 3160 -430 { lab=7}
+N 3140 -430 3140 -290 { lab=7}
+N 3140 -290 3160 -290 { lab=7}
+N 3200 -520 3200 -460 { lab=VDD}
+N 3200 -260 3200 -200 { lab=GND}
+N 3200 -360 3420 -360 { lab=Clk_Out}
+N 3040 -360 3140 -360 { lab=7}
+N -140 -510 -60 -510 { lab=VDD}
+N -140 -170 -60 -170 { lab=GND}
+C {sky130_fd_pr/pfet_01v8.sym} 2710 -430 0 0 {name=M15
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2710 -290 0 0 {name=M16
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2600 -360 0 1 {name=l1 sig_type=std_logic lab=6}
+C {lab_wire.sym} 2880 -360 0 1 {name=l2 sig_type=std_logic lab=7}
+C {sky130_fd_pr/pfet_01v8.sym} 320 -420 0 0 {name=M11
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 320 -280 0 0 {name=M12
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 460 -350 0 1 {name=l7 sig_type=std_logic lab=2}
+C {lab_wire.sym} 340 -490 0 1 {name=l5 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 210 -350 0 1 {name=l9 sig_type=std_logic lab=6}
+C {sky130_fd_pr/pfet_01v8.sym} 320 110 0 0 {name=M13
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 320 250 0 0 {name=M14
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 440 180 0 1 {name=l17 sig_type=std_logic lab=Clkb}
+C {lab_wire.sym} 210 180 0 1 {name=l20 sig_type=std_logic lab=Clk_In}
+C {sky130_fd_pr/pfet_01v8.sym} 1680 -420 0 0 {name=M7
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1680 -280 0 0 {name=M8
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1790 -350 0 1 {name=l24 sig_type=std_logic lab=5}
+C {lab_wire.sym} 1570 -350 0 1 {name=l27 sig_type=std_logic lab=4}
+C {sky130_fd_pr/pfet_01v8.sym} 760 -420 0 0 {name=M1
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 760 -280 0 0 {name=M2
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 880 -350 0 1 {name=l31 sig_type=std_logic lab=3}
+C {lab_wire.sym} 650 -350 0 1 {name=l34 sig_type=std_logic lab=2}
+C {sky130_fd_pr/pfet_01v8.sym} 1220 -250 3 0 {name=M3
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1220 -470 1 0 {name=M4
+L=0.15
+W=0.84
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1050 -350 0 1 {name=l35 sig_type=std_logic lab=3}
+C {lab_wire.sym} 1380 -350 0 1 {name=l36 sig_type=std_logic lab=4}
+C {lab_wire.sym} 1220 -500 1 0 {name=l37 sig_type=std_logic lab=Clk_In}
+C {lab_wire.sym} 1220 -190 1 0 {name=l38 sig_type=std_logic lab=Clkb}
+C {sky130_fd_pr/pfet_01v8.sym} 2170 -260 3 0 {name=M9
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2170 -480 1 0 {name=M10
+L=0.15
+W=0.84
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2000 -360 0 1 {name=l43 sig_type=std_logic lab=5}
+C {lab_wire.sym} 2330 -360 0 1 {name=l44 sig_type=std_logic lab=6}
+C {lab_wire.sym} 2170 -510 1 0 {name=l45 sig_type=std_logic lab=Clkb}
+C {lab_wire.sym} 2170 -200 1 0 {name=l46 sig_type=std_logic lab=Clk_In}
+C {ipin.sym} 200 180 0 0 {name=p1 lab=Clk_In}
+C {sky130_fd_pr/pfet_01v8.sym} 3180 -430 0 0 {name=M19
+L=0.15
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3180 -290 0 0 {name=M20
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 3070 -360 0 1 {name=l71 sig_type=std_logic lab=7}
+C {lab_wire.sym} 3350 -360 0 1 {name=l72 sig_type=std_logic lab=Clk_Out}
+C {iopin.sym} -140 -510 0 1 {name=p2 lab=VDD}
+C {iopin.sym} -140 -170 0 1 {name=p3 lab=GND}
+C {opin.sym} 3420 -360 0 0 {name=p4 lab=Clk_Out}
+C {lab_wire.sym} 780 -480 0 1 {name=l6 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 360 -420 0 1 {name=l3 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 810 -420 0 1 {name=l12 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 1220 -290 0 1 {name=l23 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 1710 -420 0 1 {name=l28 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 1700 -470 0 1 {name=l30 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2170 -300 0 1 {name=l21 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2730 -480 0 1 {name=l25 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2740 -430 0 1 {name=l32 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 3200 -480 0 1 {name=l13 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 3210 -430 0 1 {name=l15 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 340 60 0 1 {name=l40 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 360 110 0 1 {name=l10 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 340 330 0 1 {name=l18 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 360 250 0 1 {name=l11 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 340 -190 0 1 {name=l19 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 350 -280 0 1 {name=l41 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 780 -190 0 1 {name=l4 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 790 -280 0 1 {name=l8 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 1220 -410 0 1 {name=l29 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 1730 -280 0 1 {name=l33 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 1700 -190 0 1 {name=l39 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2170 -430 0 1 {name=l22 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2760 -290 0 1 {name=l26 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2730 -200 0 1 {name=l42 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 3230 -290 0 1 {name=l14 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 3200 -200 0 1 {name=l16 sig_type=std_logic lab=GND}
diff --git a/xschem/3-stage_cs-vco_dp9/FD.sym b/xschem/3-stage_cs-vco_dp9/FD.sym
new file mode 100755
index 0000000..29ef38a
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/FD.sym
@@ -0,0 +1,23 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -27 -6 0 0 0.3 0.3 {}
+T {@name} 135 -42 0 0 0.2 0.2 {}
+L 4 -130 -30 130 -30 {}
+L 4 -130 30 130 30 {}
+L 4 -130 -30 -130 30 {}
+L 4 130 -30 130 30 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=VDD dir=inout }
+L 7 130 -20 150 -20 {}
+T {VDD} 125 -24 0 1 0.2 0.2 {}
+B 5 147.5 -2.5 152.5 2.5 {name=Clk_Out dir=out }
+L 4 130 0 150 0 {}
+T {Clk_Out} 125 -4 0 1 0.2 0.2 {}
+B 5 147.5 17.5 152.5 22.5 {name=GND dir=inout }
+L 7 130 20 150 20 {}
+T {GND} 125 16 0 1 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=Clk_In dir=in }
+L 4 -150 -20 -130 -20 {}
+T {Clk_In} -125 -24 0 0 0.2 0.2 {}
diff --git a/xschem/3-stage_cs-vco_dp9/FD_v5.sch b/xschem/3-stage_cs-vco_dp9/FD_v5.sch
new file mode 100755
index 0000000..8915d86
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/FD_v5.sch
@@ -0,0 +1,503 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 2730 -420 2780 -420 { lab=VDD}
+N 2730 -280 2780 -280 { lab=GND}
+N 2730 -390 2730 -310 { lab=7}
+N 2670 -420 2690 -420 { lab=6}
+N 2670 -420 2670 -280 { lab=6}
+N 2670 -280 2690 -280 { lab=6}
+N 2730 -510 2730 -450 { lab=VDD}
+N 2730 -250 2730 -190 { lab=GND}
+N 2730 -350 2950 -350 { lab=7}
+N 2570 -350 2670 -350 { lab=6}
+N 870 180 920 180 { lab=VDD}
+N 870 320 920 320 { lab=GND}
+N 810 180 830 180 { lab=Clkb_buf}
+N 810 180 810 320 { lab=Clkb_buf}
+N 810 320 830 320 { lab=Clkb_buf}
+N 870 90 870 150 { lab=VDD}
+N 870 350 870 430 { lab=GND}
+N -130 250 -50 250 { lab=Clk_In}
+N 1700 -420 1750 -420 { lab=VDD}
+N 1700 -280 1750 -280 { lab=GND}
+N 1640 -420 1660 -420 { lab=4}
+N 1640 -420 1640 -280 { lab=4}
+N 1640 -280 1660 -280 { lab=4}
+N 1700 -510 1700 -450 { lab=VDD}
+N 1700 -250 1700 -170 { lab=GND}
+N 1560 -350 1640 -350 { lab=4}
+N 780 -420 830 -420 { lab=VDD}
+N 780 -280 830 -280 { lab=GND}
+N 720 -420 740 -420 { lab=2}
+N 720 -420 720 -280 { lab=2}
+N 720 -280 740 -280 { lab=2}
+N 780 -510 780 -450 { lab=VDD}
+N 780 -250 780 -170 { lab=GND}
+N 640 -350 720 -350 { lab=2}
+N 1220 -320 1220 -270 { lab=VDD}
+N 1220 -450 1220 -400 { lab=GND}
+N 1110 -450 1190 -450 { lab=3}
+N 1110 -270 1190 -270 { lab=3}
+N 1110 -450 1110 -270 { lab=3}
+N 1250 -450 1330 -450 { lab=4}
+N 1250 -270 1330 -270 { lab=4}
+N 1330 -450 1330 -270 { lab=4}
+N 1030 -350 1110 -350 { lab=3}
+N 1330 -350 1410 -350 { lab=4}
+N 1220 -540 1220 -490 { lab=Clk_In_buf}
+N 1220 -230 1220 -180 { lab=Clkb_buf}
+N 2170 -320 2170 -270 { lab=VDD}
+N 2170 -450 2170 -400 { lab=GND}
+N 2060 -450 2140 -450 { lab=5}
+N 2060 -270 2140 -270 { lab=5}
+N 2060 -450 2060 -270 { lab=5}
+N 2200 -450 2280 -450 { lab=6}
+N 2200 -270 2280 -270 { lab=6}
+N 2280 -450 2280 -270 { lab=6}
+N 1980 -350 2060 -350 { lab=5}
+N 2280 -350 2360 -350 { lab=6}
+N 2170 -540 2170 -490 { lab=Clkb_buf}
+N 2170 -230 2170 -180 { lab=Clk_In_buf}
+N 1700 -390 1700 -310 { lab=5}
+N 1700 -350 1820 -350 { lab=5}
+N 780 -390 780 -310 { lab=3}
+N 780 -350 920 -350 { lab=3}
+N 870 210 870 290 { lab=Clk_In_buf}
+N 870 250 1010 250 { lab=Clk_In_buf}
+N 3010 -420 3060 -420 { lab=VDD}
+N 3010 -280 3060 -280 { lab=GND}
+N 3010 -390 3010 -310 { lab=Clk_Out}
+N 2950 -420 2970 -420 { lab=7}
+N 2950 -420 2950 -280 { lab=7}
+N 2950 -280 2970 -280 { lab=7}
+N 3010 -510 3010 -450 { lab=VDD}
+N 3010 -250 3010 -190 { lab=GND}
+N 3010 -350 3230 -350 { lab=Clk_Out}
+N 240 -520 320 -520 { lab=VDD}
+N 240 -180 320 -180 { lab=GND}
+N 2380 -60 2430 -60 { lab=VDD}
+N 2380 100 2430 100 { lab=GND}
+N 2430 -150 2430 -90 { lab=VDD}
+N 2430 130 2430 210 { lab=GND}
+N 2510 30 2590 30 { lab=6}
+N 2270 30 2430 30 { lab=2}
+N 2470 -60 2510 -60 { lab=6}
+N 2510 -60 2510 100 { lab=6}
+N 2470 100 2510 100 { lab=6}
+N 2430 -30 2430 70 { lab=2}
+N 540 30 2270 30 { lab=2}
+N 540 -350 540 30 { lab=2}
+N 540 -350 640 -350 { lab=2}
+N 920 -350 1030 -350 { lab=3}
+N 1410 -350 1560 -350 { lab=4}
+N 1820 -350 1980 -350 { lab=5}
+N 2360 -350 2570 -350 { lab=6}
+N 2590 -350 2590 30 { lab=6}
+N 290 180 340 180 { lab=VDD}
+N 290 320 340 320 { lab=GND}
+N 230 180 250 180 { lab=Clkb_int}
+N 230 180 230 320 { lab=Clkb_int}
+N 230 320 250 320 { lab=Clkb_int}
+N 290 90 290 150 { lab=VDD}
+N 290 350 290 430 { lab=GND}
+N 150 250 230 250 { lab=Clkb_int}
+N 290 210 290 290 { lab=#net1}
+N 130 180 180 180 { lab=VDD}
+N 130 320 180 320 { lab=GND}
+N 70 180 90 180 { lab=Clk_In}
+N 70 180 70 320 { lab=Clk_In}
+N 70 320 90 320 { lab=Clk_In}
+N 130 90 130 150 { lab=VDD}
+N 130 350 130 430 { lab=GND}
+N -10 250 70 250 { lab=Clk_In}
+N 130 210 130 290 { lab=Clkb_int}
+N -50 250 -10 250 { lab=Clk_In}
+N 130 250 150 250 { lab=Clkb_int}
+N 690 250 810 250 { lab=Clkb_buf}
+N 500 180 550 180 { lab=VDD}
+N 440 180 460 180 { lab=#net1}
+N 500 90 500 150 { lab=VDD}
+N 500 320 550 320 { lab=GND}
+N 440 320 460 320 { lab=#net1}
+N 500 350 500 430 { lab=GND}
+N 440 180 440 320 { lab=#net1}
+N 500 210 500 290 { lab=Clkb_buf}
+N 500 250 690 250 { lab=Clkb_buf}
+N 290 250 440 250 { lab=#net1}
+C {sky130_fd_pr/pfet_01v8.sym} 2710 -420 0 0 {name=MPbuf1
+L=0.15
+W=1.44
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2710 -280 0 0 {name=MNbuf1
+L=0.15
+W=0.84
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2600 -350 0 1 {name=l1 sig_type=std_logic lab=6}
+C {lab_wire.sym} 2800 -350 0 1 {name=l2 sig_type=std_logic lab=7}
+C {sky130_fd_pr/pfet_01v8.sym} 850 180 0 0 {name=MPClkin
+L=0.15
+W=1.44
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 850 320 0 0 {name=MNClkin
+L=0.15
+W=0.84
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 740 250 0 1 {name=l17 sig_type=std_logic lab=Clkb_buf}
+C {lab_wire.sym} -120 250 0 1 {name=l20 sig_type=std_logic lab=Clk_In}
+C {sky130_fd_pr/pfet_01v8.sym} 1680 -420 0 0 {name=MPinv2
+L=0.15
+W=1.44
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1680 -280 0 0 {name=MNinv2
+L=0.15
+W=0.84
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1790 -350 0 1 {name=l24 sig_type=std_logic lab=5}
+C {lab_wire.sym} 1570 -350 0 1 {name=l27 sig_type=std_logic lab=4}
+C {sky130_fd_pr/pfet_01v8.sym} 760 -420 0 0 {name=MPinv1
+L=0.15
+W=1.44
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 760 -280 0 0 {name=MNinv1
+L=0.15
+W=0.84
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 880 -350 0 1 {name=l31 sig_type=std_logic lab=3}
+C {lab_wire.sym} 650 -350 0 1 {name=l34 sig_type=std_logic lab=2}
+C {sky130_fd_pr/pfet_01v8.sym} 1220 -250 3 0 {name=MPTgate1
+L=0.15
+W=1.44
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1220 -470 1 0 {name=MNTgate1
+L=0.15
+W=0.84
+nf=1
+mult=8
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1050 -350 0 1 {name=l35 sig_type=std_logic lab=3}
+C {lab_wire.sym} 1380 -350 0 1 {name=l36 sig_type=std_logic lab=4}
+C {lab_wire.sym} 1220 -510 1 0 {name=l37 sig_type=std_logic lab=Clk_In_buf}
+C {lab_wire.sym} 1220 -180 1 0 {name=l38 sig_type=std_logic lab=Clkb_buf}
+C {sky130_fd_pr/pfet_01v8.sym} 2170 -250 3 0 {name=MPTgate2
+L=0.15
+W=1.44
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2170 -470 1 0 {name=MNTgate2
+L=0.15
+W=0.84
+nf=1
+mult=8
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2000 -350 0 1 {name=l43 sig_type=std_logic lab=5}
+C {lab_wire.sym} 2330 -350 0 1 {name=l44 sig_type=std_logic lab=6}
+C {lab_wire.sym} 2170 -510 1 0 {name=l45 sig_type=std_logic lab=Clkb_buf}
+C {lab_wire.sym} 2170 -180 1 0 {name=l46 sig_type=std_logic lab=Clk_In_buf}
+C {ipin.sym} -130 250 0 0 {name=p1 lab=Clk_In}
+C {sky130_fd_pr/pfet_01v8.sym} 2990 -420 0 0 {name=MPbuf2
+L=0.15
+W=1.44
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2990 -280 0 0 {name=MNbuf2
+L=0.15
+W=0.84
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 3160 -350 0 1 {name=l72 sig_type=std_logic lab=Clk_Out}
+C {iopin.sym} 240 -520 0 1 {name=p2 lab=VDD}
+C {iopin.sym} 240 -180 0 1 {name=p3 lab=GND}
+C {opin.sym} 3230 -350 0 0 {name=p4 lab=Clk_Out}
+C {lab_wire.sym} 780 -480 0 1 {name=l6 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 810 -420 0 1 {name=l12 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 1220 -290 0 1 {name=l23 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 1710 -420 0 1 {name=l28 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 1700 -470 0 1 {name=l30 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2170 -290 0 1 {name=l21 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2730 -470 0 1 {name=l25 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2740 -420 0 1 {name=l32 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 3010 -470 0 1 {name=l13 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 3020 -420 0 1 {name=l15 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 870 130 0 1 {name=l40 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 890 180 0 1 {name=l10 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 870 400 0 1 {name=l18 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 890 320 0 1 {name=l11 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 780 -190 0 1 {name=l4 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 790 -280 0 1 {name=l8 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 1220 -410 0 1 {name=l29 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 1730 -280 0 1 {name=l33 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 1700 -190 0 1 {name=l39 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2170 -420 0 1 {name=l22 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2760 -280 0 1 {name=l26 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2730 -190 0 1 {name=l42 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 3040 -280 0 1 {name=l14 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 3010 -190 0 1 {name=l16 sig_type=std_logic lab=GND}
+C {sky130_fd_pr/pfet_01v8.sym} 2450 -60 0 1 {name=MPfb
+L=0.15
+W=1.44
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2450 100 0 1 {name=MNfb
+L=0.15
+W=0.84
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2300 30 0 1 {name=l47 sig_type=std_logic lab=2}
+C {lab_wire.sym} 2430 -130 0 1 {name=l48 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2570 30 0 1 {name=l49 sig_type=std_logic lab=6}
+C {lab_wire.sym} 2400 -60 0 1 {name=l50 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 2430 190 0 1 {name=l51 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 2390 100 0 1 {name=l52 sig_type=std_logic lab=GND}
+C {sky130_fd_pr/pfet_01v8.sym} 270 180 0 0 {name=MPClkin_b2
+L=0.15
+W=1.44
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 270 320 0 0 {name=MNClkin_b2
+L=0.15
+W=0.84
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 290 130 0 1 {name=l7 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 310 180 0 1 {name=l9 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 290 400 0 1 {name=l19 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 310 320 0 1 {name=l41 sig_type=std_logic lab=GND}
+C {sky130_fd_pr/pfet_01v8.sym} 110 180 0 0 {name=MPClkin_b1
+L=0.15
+W=1.44
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 110 320 0 0 {name=MNClkin_b1
+L=0.15
+W=0.84
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 130 130 0 1 {name=l3 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 150 180 0 1 {name=l5 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 130 400 0 1 {name=l53 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 150 320 0 1 {name=l54 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 150 250 0 1 {name=l55 sig_type=std_logic lab=Clkb_int}
+C {lab_wire.sym} 920 250 0 1 {name=l56 sig_type=std_logic lab=Clk_In_buf}
+C {sky130_fd_pr/pfet_01v8.sym} 480 180 0 0 {name=MPClkin_b3
+L=0.15
+W=1.44
+nf=1
+mult=7
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 500 130 0 1 {name=l57 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 520 180 0 1 {name=l58 sig_type=std_logic lab=VDD}
+C {sky130_fd_pr/nfet_01v8.sym} 480 320 0 0 {name=MNClkin_b3
+L=0.15
+W=0.84
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 500 400 0 1 {name=l59 sig_type=std_logic lab=GND}
+C {lab_wire.sym} 520 320 0 1 {name=l60 sig_type=std_logic lab=GND}
diff --git a/xschem/3-stage_cs-vco_dp9/FD_v5.sym b/xschem/3-stage_cs-vco_dp9/FD_v5.sym
new file mode 100755
index 0000000..9aba6a9
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/FD_v5.sym
@@ -0,0 +1,27 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -30 130 -30 {}
+L 4 -130 30 130 30 {}
+L 4 -130 -30 -130 30 {}
+L 4 130 -30 130 30 {}
+L 4 130 0 150 0 {}
+L 4 -150 -20 -130 -20 {}
+L 7 130 -20 150 -20 {}
+L 7 130 20 150 20 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=VDD dir=inout }
+B 5 147.5 -2.5 152.5 2.5 {name=Clk_Out dir=out }
+B 5 147.5 17.5 152.5 22.5 {name=GND dir=inout }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=Clk_In dir=in }
+T {@symname} -27 -6 0 0 0.3 0.3 {}
+T {@name} 135 -42 0 0 0.2 0.2 {}
+T {VDD} 125 -24 0 1 0.2 0.2 {}
+T {Clk_Out} 125 -4 0 1 0.2 0.2 {}
+T {GND} 125 16 0 1 0.2 0.2 {}
+T {Clk_In} -125 -24 0 0 0.2 0.2 {}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_switch_n.sch b/xschem/3-stage_cs-vco_dp9/vco_switch_n.sch
new file mode 100755
index 0000000..deac8e3
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_switch_n.sch
@@ -0,0 +1,87 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 260 -40 320 -40 { lab=out}
+N 320 -40 320 140 { lab=out}
+N 260 140 320 140 { lab=out}
+N 140 140 200 140 { lab=in}
+N 140 -40 200 -40 { lab=in}
+N 140 -40 140 140 { lab=in}
+N 230 -40 230 10 { lab=vdd}
+N 230 90 230 140 { lab=vss}
+N 230 -120 230 -80 { lab=selb}
+N 230 180 230 230 { lab=sel}
+N 320 40 500 40 { lab=out}
+N -40 40 140 40 { lab=in}
+N 460 40 460 170 { lab=out}
+N 460 230 460 280 { lab=vss}
+N 370 200 420 200 { lab=selb}
+N -40 210 0 210 { lab=sel}
+N 80 210 130 210 { lab=selb}
+N -40 280 10 280 { lab=vss}
+N -40 -120 10 -120 { lab=vdd}
+N 460 200 510 200 { lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 230 160 3 0 {name=M26
+L=0.18
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -60 3 1 {name=M25
+L=0.18
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 230 0 0 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 230 110 0 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 230 210 0 0 {name=l3 sig_type=std_logic lab=sel}
+C {lab_wire.sym} 230 -100 0 0 {name=l4 sig_type=std_logic lab=selb}
+C {lab_wire.sym} 80 40 0 0 {name=l5 sig_type=std_logic lab=in}
+C {sky130_fd_pr/nfet_01v8.sym} 440 200 0 0 {name=M1
+L=0.18
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 460 270 0 0 {name=l6 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 400 200 0 0 {name=l7 sig_type=std_logic lab=selb}
+C {sky130_stdcells/inv_1.sym} 40 210 0 0 {name=x1 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_wire.sym} 120 210 0 0 {name=l8 sig_type=std_logic lab=selb}
+C {lab_wire.sym} -10 210 0 0 {name=l9 sig_type=std_logic lab=sel}
+C {lab_wire.sym} 0 280 0 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 0 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {ipin.sym} -40 40 0 0 {name=p5 lab=in}
+C {ipin.sym} -40 210 0 0 {name=p1 lab=sel}
+C {opin.sym} 500 40 0 0 {name=p4 lab=out}
+C {iopin.sym} -40 280 2 0 {name=p3 lab=vss}
+C {iopin.sym} -40 -120 2 0 {name=p2 lab=vdd}
+C {lab_wire.sym} 500 200 0 0 {name=l12 sig_type=std_logic lab=vss}
+C {code_shown.sym} 370 -80 0 0 {name=s1 only_toplevel=false value=".include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_switch_n.sym b/xschem/3-stage_cs-vco_dp9/vco_switch_n.sym
new file mode 100755
index 0000000..677530b
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_switch_n.sym
@@ -0,0 +1,36 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -30 -60 30 {}
+L 4 60 -30 60 30 {}
+L 4 60 0 80 0 {}
+L 4 -80 0 -60 0 {}
+L 4 -60 -30 60 -30 {}
+L 4 -60 30 60 30 {}
+L 4 -80 20 -60 20 {}
+L 4 -40 0 -30 0 {}
+L 4 -30 0 -20 -10 {}
+L 4 -20 0 30 0 {}
+L 4 -0 0 -0 10 {}
+L 4 0 20 0 30 {}
+L 4 0 20 10 10 {}
+L 7 0 -50 0 -30 {}
+L 7 0 30 0 50 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=out dir=out }
+B 5 -82.5 -2.5 -77.5 2.5 {name=in dir=in }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout }
+B 5 -82.5 17.5 -77.5 22.5 {name=sel dir=in }
+T {@symname} -31.5 -16 0 0 0.3 0.3 {}
+T {@name} 35 -42 0 0 0.2 0.2 {}
+T {vdd} 5 -24 0 1 0.2 0.2 {}
+T {out} 55 -4 0 1 0.2 0.2 {}
+T {in} -55 -4 0 0 0.2 0.2 {}
+T {vss} 5 16 0 1 0.2 0.2 {}
+T {sel} -55 16 0 0 0.2 0.2 {}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_switch_p.sch b/xschem/3-stage_cs-vco_dp9/vco_switch_p.sch
new file mode 100755
index 0000000..663cd02
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_switch_p.sch
@@ -0,0 +1,87 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 260 -40 320 -40 { lab=out}
+N 320 -40 320 140 { lab=out}
+N 260 140 320 140 { lab=out}
+N 140 140 200 140 { lab=in}
+N 140 -40 200 -40 { lab=in}
+N 140 -40 140 140 { lab=in}
+N 230 -40 230 10 { lab=vdd}
+N 230 90 230 140 { lab=vss}
+N 230 -120 230 -80 { lab=selb}
+N 230 180 230 230 { lab=sel}
+N 320 40 500 40 { lab=out}
+N -40 40 140 40 { lab=in}
+N 460 -90 460 40 { lab=out}
+N 370 -120 420 -120 { lab=sel}
+N -40 210 0 210 { lab=sel}
+N 80 210 130 210 { lab=selb}
+N -40 280 10 280 { lab=vss}
+N -40 -120 10 -120 { lab=vdd}
+N 460 -120 510 -120 { lab=vdd}
+N 460 -200 460 -150 { lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 230 160 3 0 {name=M26
+L=0.18
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -60 3 1 {name=M25
+L=0.18
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 230 0 0 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 230 110 0 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 230 210 0 0 {name=l3 sig_type=std_logic lab=sel}
+C {lab_wire.sym} 230 -100 0 0 {name=l4 sig_type=std_logic lab=selb}
+C {lab_wire.sym} 80 40 0 0 {name=l5 sig_type=std_logic lab=in}
+C {lab_wire.sym} 400 -120 0 0 {name=l7 sig_type=std_logic lab=sel}
+C {sky130_stdcells/inv_1.sym} 40 210 0 0 {name=x1 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_wire.sym} 120 210 0 0 {name=l8 sig_type=std_logic lab=selb}
+C {lab_wire.sym} -10 210 0 0 {name=l9 sig_type=std_logic lab=sel}
+C {lab_wire.sym} 0 280 0 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 0 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {ipin.sym} -40 40 0 0 {name=p5 lab=in}
+C {ipin.sym} -40 210 0 0 {name=p1 lab=sel}
+C {opin.sym} 500 40 0 0 {name=p4 lab=out}
+C {iopin.sym} -40 280 2 0 {name=p3 lab=vss}
+C {iopin.sym} -40 -120 2 0 {name=p2 lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 440 -120 2 1 {name=M1
+L=0.18
+W=0.72
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 500 -120 0 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 460 -190 0 0 {name=l12 sig_type=std_logic lab=vdd}
+C {code_shown.sym} 40 320 0 0 {name=s1 only_toplevel=false value=".include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_switch_p.sym b/xschem/3-stage_cs-vco_dp9/vco_switch_p.sym
new file mode 100755
index 0000000..3c0c73f
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_switch_p.sym
@@ -0,0 +1,36 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -30 -60 30 {}
+L 4 60 -30 60 30 {}
+L 4 60 0 80 0 {}
+L 4 -80 0 -60 0 {}
+L 4 -60 -30 60 -30 {}
+L 4 -60 30 60 30 {}
+L 4 -80 20 -60 20 {}
+L 4 -40 0 -30 0 {}
+L 4 -30 0 -20 -10 {}
+L 4 -20 0 30 0 {}
+L 4 0 -10 0 0 {}
+L 4 0 -30 0 -20 {}
+L 4 0 -10 10 -20 {}
+L 7 0 -50 0 -30 {}
+L 7 0 30 0 50 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=out dir=out }
+B 5 -82.5 -2.5 -77.5 2.5 {name=in dir=in }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout }
+B 5 -82.5 17.5 -77.5 22.5 {name=sel dir=in }
+T {@symname} -31.5 -16 0 0 0.3 0.3 {}
+T {@name} 35 -42 0 0 0.2 0.2 {}
+T {vdd} 5 -24 0 1 0.2 0.2 {}
+T {out} 55 -4 0 1 0.2 0.2 {}
+T {in} -55 -4 0 0 0.2 0.2 {}
+T {vss} 5 16 0 1 0.2 0.2 {}
+T {sel} -55 16 0 0 0.2 0.2 {}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sch b/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sch
new file mode 100644
index 0000000..52b32b5
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sch
@@ -0,0 +1,174 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 2840 -630 2920 -630 { lab=out}
+N 2580 -650 2680 -650 { lab=vctrl}
+N 2500 -820 2760 -820 { lab=vdd}
+N 2500 -440 2760 -440 { lab=vss}
+N 2420 -820 2500 -820 { lab=vdd}
+N 2420 -440 2500 -440 { lab=vss}
+N 2760 -720 2760 -680 { lab=vdd}
+N 2760 -820 2760 -780 { lab=vdd}
+N 2760 -480 2760 -440 { lab=vss}
+N 2760 -580 2760 -540 { lab=vss}
+N 3000 -630 3050 -630 { lab=out}
+N 3350 -590 3400 -590 { lab=vss}
+N 3350 -630 3400 -630 { lab=vdd}
+N 3160 270 3190 270 { lab=out_div128}
+N 3960 270 4010 270 { lab=out_div128_buf}
+N 3910 270 3960 270 { lab=out_div128_buf}
+N 3390 270 3430 270 { lab=buf2a_out}
+N 3510 270 3550 270 { lab=buf4a_out}
+N 2480 -640 2680 -640 { lab=vsel0}
+N 2510 -630 2680 -630 { lab=vsel1}
+N 2540 -620 2680 -620 { lab=vsel2}
+N 2570 -610 2680 -610 { lab=vsel3}
+N 3350 -610 3460 -610 { lab=out_div2}
+N 3760 -590 3810 -590 { lab=vss}
+N 3760 -630 3810 -630 { lab=vdd}
+N 3760 -610 3870 -610 { lab=out_div4}
+N 3460 -630 3460 -610 { lab=out_div2}
+N 3350 -440 3400 -440 { lab=vss}
+N 3350 -480 3400 -480 { lab=vdd}
+N 3350 -460 3460 -460 { lab=out_div8}
+N 3050 -530 3050 -480 { lab=out_div4}
+N 3050 -530 3870 -530 { lab=out_div4}
+N 3870 -610 3870 -530 { lab=out_div4}
+N 3760 -440 3810 -440 { lab=vss}
+N 3760 -480 3810 -480 { lab=vdd}
+N 3760 -460 3870 -460 { lab=out_div16}
+N 3460 -480 3460 -460 { lab=out_div8}
+N 3350 -290 3400 -290 { lab=vss}
+N 3350 -330 3400 -330 { lab=vdd}
+N 3350 -310 3460 -310 { lab=out_div32}
+N 3050 -380 3050 -330 { lab=out_div16}
+N 3050 -380 3870 -380 { lab=out_div16}
+N 3870 -460 3870 -380 { lab=out_div16}
+N 3760 -290 3810 -290 { lab=vss}
+N 3760 -330 3810 -330 { lab=vdd}
+N 3760 -310 3870 -310 { lab=out_div64}
+N 3460 -330 3460 -310 { lab=out_div32}
+N 3350 -140 3400 -140 { lab=vss}
+N 3350 -180 3400 -180 { lab=vdd}
+N 3350 -160 3460 -160 { lab=out_div128}
+N 3050 -230 3050 -180 { lab=out_div64}
+N 3050 -230 3870 -230 { lab=out_div64}
+N 3870 -310 3870 -230 { lab=out_div64}
+N 3760 -140 3810 -140 { lab=vss}
+N 3760 -180 3810 -180 { lab=vdd}
+N 3760 -160 3870 -160 { lab=out_div256}
+N 3460 -180 3460 -160 { lab=out_div128}
+N 2920 -630 3000 -630 { lab=out}
+N 2760 -540 2760 -480 { lab=vss}
+N 2760 -780 2760 -720 { lab=vdd}
+N 2380 -650 2580 -650 { lab=vctrl}
+N 2380 -640 2480 -640 { lab=vsel0}
+N 2380 -630 2510 -630 { lab=vsel1}
+N 2380 -620 2540 -620 { lab=vsel2}
+N 2380 -610 2570 -610 { lab=vsel3}
+N 3040 270 3160 270 { lab=out_div128}
+N 3160 360 3190 360 { lab=out_div256}
+N 3860 360 3910 360 { lab=out_div256_buf}
+N 3810 360 3860 360 { lab=out_div256_buf}
+N 3390 360 3430 360 { lab=buf2b_out}
+N 3510 360 3550 360 { lab=buf4b_out}
+N 3040 360 3160 360 { lab=out_div256}
+N 3350 10 3400 10 { lab=vss}
+N 3350 -30 3400 -30 { lab=vdd}
+N 3350 -10 3460 -10 { lab=out_div512}
+N 3050 -80 3050 -30 { lab=out_div256}
+N 3050 -80 3870 -80 { lab=out_div256}
+N 3870 -160 3870 -80 { lab=out_div256}
+N 3760 10 3810 10 { lab=vss}
+N 3760 -30 3810 -30 { lab=vdd}
+N 3760 -10 3870 -10 { lab=out_div1024}
+N 3460 -30 3460 -10 { lab=out_div512}
+N 3190 270 3310 270 { lab=out_div128}
+N 3190 360 3310 360 { lab=out_div256}
+N 3630 270 3670 270 { lab=buf8a_out}
+N 3630 360 3670 360 { lab=buf8b_out}
+N 3750 360 3810 360 { lab=out_div256_buf}
+N 3800 220 3800 300 { lab=buf16a_out}
+N 3880 220 3880 300 { lab=out_div128_buf}
+N 3880 270 3910 270 { lab=out_div128_buf}
+N 3750 270 3800 270 { lab=buf16a_out}
+C {3-stage_cs-vco_dp9.sym} 2760 -630 0 0 {name=xvco}
+C {lab_wire.sym} 2640 -820 0 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2650 -440 0 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 2650 -650 0 0 {name=l4 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 2960 -630 0 0 {name=l5 sig_type=std_logic lab=out}
+C {ipin.sym} 2380 -650 0 0 {name=p1 lab=vctrl}
+C {FD_v5.sym} 3200 -610 0 0 {name=xFD_0}
+C {lab_wire.sym} 3390 -630 0 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -590 0 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3180 270 0 0 {name=l8 sig_type=std_logic lab=out_div128}
+C {sky130_stdcells/clkbuf_2.sym} 3350 270 0 0 {name=xbuf2a VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_4.sym} 3470 270 0 0 {name=xbuf4a VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_8.sym} 3590 270 0 0 {name=xbuf8a VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {opin.sym} 4010 270 0 0 {name=p4 lab=out_div128_buf}
+C {lab_wire.sym} 2550 -640 0 0 {name=l11 sig_type=std_logic lab=vsel0}
+C {lab_wire.sym} 2580 -630 0 0 {name=l12 sig_type=std_logic lab=vsel1}
+C {lab_wire.sym} 2600 -620 0 0 {name=l13 sig_type=std_logic lab=vsel2}
+C {lab_wire.sym} 2630 -610 0 0 {name=l14 sig_type=std_logic lab=vsel3}
+C {lab_wire.sym} 3400 -610 0 0 {name=l17 sig_type=std_logic lab=out_div2}
+C {FD.sym} 3610 -610 0 0 {name=xFD_1}
+C {lab_wire.sym} 3800 -630 0 0 {name=l18 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -590 0 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3810 -610 0 0 {name=l20 sig_type=std_logic lab=out_div4}
+C {FD.sym} 3200 -460 0 0 {name=xFD_2}
+C {lab_wire.sym} 3390 -480 0 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -440 0 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3400 -460 0 0 {name=l23 sig_type=std_logic lab=out_div8}
+C {FD.sym} 3610 -460 0 0 {name=xFD_3}
+C {lab_wire.sym} 3800 -480 0 0 {name=l24 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -440 0 0 {name=l25 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3810 -460 0 0 {name=l26 sig_type=std_logic lab=out_div16}
+C {FD.sym} 3200 -310 0 0 {name=xFD_4}
+C {lab_wire.sym} 3390 -330 0 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -290 0 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3400 -310 0 0 {name=l29 sig_type=std_logic lab=out_div32}
+C {FD.sym} 3610 -310 0 0 {name=xFD_5}
+C {lab_wire.sym} 3800 -330 0 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -290 0 0 {name=l31 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3810 -310 0 0 {name=l32 sig_type=std_logic lab=out_div64}
+C {FD.sym} 3200 -160 0 0 {name=xFD_6}
+C {lab_wire.sym} 3390 -180 0 0 {name=l33 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -140 0 0 {name=l34 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3420 -160 0 0 {name=l35 sig_type=std_logic lab=out_div128}
+C {FD.sym} 3610 -160 0 0 {name=xFD_7}
+C {lab_wire.sym} 3800 -180 0 0 {name=l36 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -140 0 0 {name=l37 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3840 -160 0 0 {name=l38 sig_type=std_logic lab=out_div256}
+C {iopin.sym} 2420 -820 0 1 {name=p2 lab=vdd}
+C {iopin.sym} 2420 -440 0 1 {name=p3 lab=vss}
+C {ipin.sym} 2380 -640 0 0 {name=p5 lab=vsel0}
+C {ipin.sym} 2380 -630 0 0 {name=p6 lab=vsel1}
+C {ipin.sym} 2380 -620 0 0 {name=p7 lab=vsel2}
+C {ipin.sym} 2380 -610 0 0 {name=p8 lab=vsel3}
+C {lab_wire.sym} 3420 270 0 0 {name=l3 sig_type=std_logic lab=buf2a_out}
+C {lab_wire.sym} 3540 270 0 0 {name=l9 sig_type=std_logic lab=buf4a_out}
+C {lab_wire.sym} 3180 360 0 0 {name=l15 sig_type=std_logic lab=out_div256}
+C {sky130_stdcells/clkbuf_2.sym} 3350 360 0 0 {name=xbuf2b VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_4.sym} 3470 360 0 0 {name=xbuf4b VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_8.sym} 3590 360 0 0 {name=xbuf8b VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {opin.sym} 3910 360 0 0 {name=p9 lab=out_div256_buf}
+C {lab_wire.sym} 3420 360 0 0 {name=l39 sig_type=std_logic lab=buf2b_out}
+C {lab_wire.sym} 3540 360 0 0 {name=l40 sig_type=std_logic lab=buf4b_out}
+C {FD.sym} 3200 -10 0 0 {name=xFD_8}
+C {lab_wire.sym} 3390 -30 0 0 {name=l41 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 10 0 0 {name=l42 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3420 -10 0 0 {name=l43 sig_type=std_logic lab=out_div512}
+C {FD.sym} 3610 -10 0 0 {name=xFD_9}
+C {lab_wire.sym} 3800 -30 0 0 {name=l44 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 10 0 0 {name=l45 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3840 -10 0 0 {name=l46 sig_type=std_logic lab=out_div1024}
+C {sky130_stdcells/clkbuf_16.sym} 3710 270 0 0 {name=xbuf16a VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_wire.sym} 3660 270 0 0 {name=l10 sig_type=std_logic lab=buf8a_out}
+C {sky130_stdcells/clkbuf_16.sym} 3710 360 0 0 {name=xbuf16b VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_wire.sym} 3660 360 0 0 {name=l16 sig_type=std_logic lab=buf8b_out}
+C {sky130_stdcells/clkbuf_16.sym} 3840 220 0 0 {name=xbuf32a_1 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/clkbuf_16.sym} 3840 300 0 0 {name=xbuf32a_2 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_wire.sym} 3790 270 0 0 {name=l47 sig_type=std_logic lab=buf16a_out}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sym b/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sym
new file mode 100755
index 0000000..a27417e
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sym
@@ -0,0 +1,42 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -50 130 -50 {}
+L 4 -130 50 130 50 {}
+L 4 -130 -50 -130 50 {}
+L 4 130 -50 130 50 {}
+L 4 -150 -40 -130 -40 {}
+L 4 -150 -20 -130 -20 {}
+L 4 -150 0 -130 0 {}
+L 4 -150 20 -130 20 {}
+L 4 -150 40 -130 40 {}
+L 4 130 0 150 0 {}
+L 4 130 20 150 20 {}
+L 7 130 -40 150 -40 {}
+L 7 130 -20 150 -20 {}
+B 5 147.5 -42.5 152.5 -37.5 {name=vdd dir=inout }
+B 5 -152.5 -42.5 -147.5 -37.5 {name=vctrl dir=in }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=vsel0 dir=in }
+B 5 -152.5 -2.5 -147.5 2.5 {name=vsel1 dir=in }
+B 5 -152.5 17.5 -147.5 22.5 {name=vsel2 dir=in }
+B 5 -152.5 37.5 -147.5 42.5 {name=vsel3 dir=in }
+B 5 147.5 -22.5 152.5 -17.5 {name=vss dir=inout }
+B 5 147.5 -2.5 152.5 2.5 {name=out_div128_buf dir=out }
+B 5 147.5 17.5 152.5 22.5 {name=out_div256_buf dir=out }
+T {@symname} -81 -6 0 0 0.3 0.3 {}
+T {@name} 135 -62 0 0 0.2 0.2 {}
+T {vdd} 125 -44 0 1 0.2 0.2 {}
+T {vctrl} -125 -44 0 0 0.2 0.2 {}
+T {vsel0} -125 -24 0 0 0.2 0.2 {}
+T {vsel1} -125 -4 0 0 0.2 0.2 {}
+T {vsel2} -125 16 0 0 0.2 0.2 {}
+T {vsel3} -125 36 0 0 0.2 0.2 {}
+T {vss} 125 -24 0 1 0.2 0.2 {}
+T {out_div128_buf} 125 -4 0 1 0.2 0.2 {}
+T {out_div256_buf} 125 16 0 1 0.2 0.2 {}
diff --git a/xschem/3-stage_cs-vco_dp9/vco_with_fdivs_-_before_adding_BB.sch b/xschem/3-stage_cs-vco_dp9/vco_with_fdivs_-_before_adding_BB.sch
new file mode 100755
index 0000000..9b7d1bd
--- /dev/null
+++ b/xschem/3-stage_cs-vco_dp9/vco_with_fdivs_-_before_adding_BB.sch
@@ -0,0 +1,138 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 2840 -630 2920 -630 { lab=out}
+N 2580 -650 2680 -650 { lab=vctrl}
+N 2500 -820 2760 -820 { lab=vdd}
+N 2500 -440 2760 -440 { lab=vss}
+N 2420 -820 2500 -820 { lab=vdd}
+N 2420 -440 2500 -440 { lab=vss}
+N 2760 -720 2760 -680 { lab=vdd}
+N 2760 -820 2760 -780 { lab=vdd}
+N 2760 -480 2760 -440 { lab=vss}
+N 2760 -580 2760 -540 { lab=vss}
+N 3000 -630 3050 -630 { lab=out}
+N 3350 -590 3400 -590 { lab=vss}
+N 3350 -630 3400 -630 { lab=vdd}
+N 3680 270 3730 270 { lab=out_div128}
+N 3630 270 3680 270 { lab=out_div128}
+N 2480 -640 2680 -640 { lab=vsel0}
+N 2510 -630 2680 -630 { lab=vsel1}
+N 2540 -620 2680 -620 { lab=vsel2}
+N 2570 -610 2680 -610 { lab=vsel3}
+N 3350 -610 3460 -610 { lab=out_div2}
+N 3760 -590 3810 -590 { lab=vss}
+N 3760 -630 3810 -630 { lab=vdd}
+N 3760 -610 3870 -610 { lab=out_div4}
+N 3460 -630 3460 -610 { lab=out_div2}
+N 3350 -440 3400 -440 { lab=vss}
+N 3350 -480 3400 -480 { lab=vdd}
+N 3350 -460 3460 -460 { lab=out_div8}
+N 3050 -530 3050 -480 { lab=out_div4}
+N 3050 -530 3870 -530 { lab=out_div4}
+N 3870 -610 3870 -530 { lab=out_div4}
+N 3760 -440 3810 -440 { lab=vss}
+N 3760 -480 3810 -480 { lab=vdd}
+N 3760 -460 3870 -460 { lab=out_div16}
+N 3460 -480 3460 -460 { lab=out_div8}
+N 3350 -290 3400 -290 { lab=vss}
+N 3350 -330 3400 -330 { lab=vdd}
+N 3350 -310 3460 -310 { lab=out_div32}
+N 3050 -380 3050 -330 { lab=out_div16}
+N 3050 -380 3870 -380 { lab=out_div16}
+N 3870 -460 3870 -380 { lab=out_div16}
+N 3760 -290 3810 -290 { lab=vss}
+N 3760 -330 3810 -330 { lab=vdd}
+N 3760 -310 3870 -310 { lab=out_div64}
+N 3460 -330 3460 -310 { lab=out_div32}
+N 3350 -140 3400 -140 { lab=vss}
+N 3350 -180 3400 -180 { lab=vdd}
+N 3350 -160 3460 -160 { lab=out_div128}
+N 3050 -230 3050 -180 { lab=out_div64}
+N 3050 -230 3870 -230 { lab=out_div64}
+N 3870 -310 3870 -230 { lab=out_div64}
+N 3760 -140 3810 -140 { lab=vss}
+N 3760 -180 3810 -180 { lab=vdd}
+N 3760 -160 3870 -160 { lab=out_div256}
+N 3460 -180 3460 -160 { lab=out_div128}
+N 2920 -630 3000 -630 { lab=out}
+N 2760 -540 2760 -480 { lab=vss}
+N 2760 -780 2760 -720 { lab=vdd}
+N 2380 -650 2580 -650 { lab=vctrl}
+N 2380 -640 2480 -640 { lab=vsel0}
+N 2380 -630 2510 -630 { lab=vsel1}
+N 2380 -620 2540 -620 { lab=vsel2}
+N 2380 -610 2570 -610 { lab=vsel3}
+N 3680 360 3730 360 { lab=out_div256}
+N 3630 360 3680 360 { lab=out_div256}
+N 3350 10 3400 10 { lab=vss}
+N 3350 -30 3400 -30 { lab=vdd}
+N 3350 -10 3460 -10 { lab=out_div512}
+N 3050 -80 3050 -30 { lab=out_div256}
+N 3050 -80 3870 -80 { lab=out_div256}
+N 3870 -160 3870 -80 { lab=out_div256}
+N 3760 10 3810 10 { lab=vss}
+N 3760 -30 3810 -30 { lab=vdd}
+N 3760 -10 3870 -10 { lab=out_div1024}
+N 3460 -30 3460 -10 { lab=out_div512}
+C {3-stage_cs-vco_dp9.sym} 2760 -630 0 0 {name=xvco}
+C {lab_wire.sym} 2640 -820 0 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2650 -440 0 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 2650 -650 0 0 {name=l4 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 2960 -630 0 0 {name=l5 sig_type=std_logic lab=out}
+C {ipin.sym} 2380 -650 0 0 {name=p1 lab=vctrl}
+C {FD_v5.sym} 3200 -610 0 0 {name=xFD_0}
+C {lab_wire.sym} 3390 -630 0 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -590 0 0 {name=l7 sig_type=std_logic lab=vss}
+C {opin.sym} 3730 270 0 0 {name=p4 lab=out_div128}
+C {lab_wire.sym} 2550 -640 0 0 {name=l11 sig_type=std_logic lab=vsel0}
+C {lab_wire.sym} 2580 -630 0 0 {name=l12 sig_type=std_logic lab=vsel1}
+C {lab_wire.sym} 2600 -620 0 0 {name=l13 sig_type=std_logic lab=vsel2}
+C {lab_wire.sym} 2630 -610 0 0 {name=l14 sig_type=std_logic lab=vsel3}
+C {lab_wire.sym} 3400 -610 0 0 {name=l17 sig_type=std_logic lab=out_div2}
+C {FD.sym} 3610 -610 0 0 {name=xFD_1}
+C {lab_wire.sym} 3800 -630 0 0 {name=l18 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -590 0 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3810 -610 0 0 {name=l20 sig_type=std_logic lab=out_div4}
+C {FD.sym} 3200 -460 0 0 {name=xFD_2}
+C {lab_wire.sym} 3390 -480 0 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -440 0 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3400 -460 0 0 {name=l23 sig_type=std_logic lab=out_div8}
+C {FD.sym} 3610 -460 0 0 {name=xFD_3}
+C {lab_wire.sym} 3800 -480 0 0 {name=l24 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -440 0 0 {name=l25 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3810 -460 0 0 {name=l26 sig_type=std_logic lab=out_div16}
+C {FD.sym} 3200 -310 0 0 {name=xFD_4}
+C {lab_wire.sym} 3390 -330 0 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -290 0 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3400 -310 0 0 {name=l29 sig_type=std_logic lab=out_div32}
+C {FD.sym} 3610 -310 0 0 {name=xFD_5}
+C {lab_wire.sym} 3800 -330 0 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -290 0 0 {name=l31 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3810 -310 0 0 {name=l32 sig_type=std_logic lab=out_div64}
+C {FD.sym} 3200 -160 0 0 {name=xFD_6}
+C {lab_wire.sym} 3390 -180 0 0 {name=l33 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 -140 0 0 {name=l34 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3420 -160 0 0 {name=l35 sig_type=std_logic lab=out_div128}
+C {FD.sym} 3610 -160 0 0 {name=xFD_7}
+C {lab_wire.sym} 3800 -180 0 0 {name=l36 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 -140 0 0 {name=l37 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3840 -160 0 0 {name=l38 sig_type=std_logic lab=out_div256}
+C {iopin.sym} 2420 -820 0 1 {name=p2 lab=vdd}
+C {iopin.sym} 2420 -440 0 1 {name=p3 lab=vss}
+C {ipin.sym} 2380 -640 0 0 {name=p5 lab=vsel0}
+C {ipin.sym} 2380 -630 0 0 {name=p6 lab=vsel1}
+C {ipin.sym} 2380 -620 0 0 {name=p7 lab=vsel2}
+C {ipin.sym} 2380 -610 0 0 {name=p8 lab=vsel3}
+C {opin.sym} 3730 360 0 0 {name=p9 lab=out_div256}
+C {FD.sym} 3200 -10 0 0 {name=xFD_8}
+C {lab_wire.sym} 3390 -30 0 0 {name=l41 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3390 10 0 0 {name=l42 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3420 -10 0 0 {name=l43 sig_type=std_logic lab=out_div512}
+C {FD.sym} 3610 -10 0 0 {name=xFD_9}
+C {lab_wire.sym} 3800 -30 0 0 {name=l44 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 3800 10 0 0 {name=l45 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 3840 -10 0 0 {name=l46 sig_type=std_logic lab=out_div1024}
diff --git a/xschem/devices/adc_bridge.sym b/xschem/devices/adc_bridge.sym
new file mode 100644
index 0000000..26f23d2
--- /dev/null
+++ b/xschem/devices/adc_bridge.sym
@@ -0,0 +1,17 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=delay
+verilog_ignore=true
+vhdl_ignore=true
+format="@name [ @@s ] [ @@d ] @adc_bridge_model"
+template="name=A1 adc_bridge_model= adc_buff"
+}
+V {}
+S {}
+E {}
+L 4 -30 0 30 0 {}
+L 4 -10 -5 10 0 {}
+L 4 -10 5 10 0 {}
+B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire propag=1}
+B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire propag=0}
+T {@name} -25 -10 0 0 0.12 0.12 {}
+T {@adc_bridge_model} 0 -10 0 0 0.12 0.12 {}
diff --git a/xschem/devices/ammeter.sym b/xschem/devices/ammeter.sym
new file mode 100644
index 0000000..eb51401
--- /dev/null
+++ b/xschem/devices/ammeter.sym
@@ -0,0 +1,18 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=current_probe
+format="@name @pinlist 0
+.save I( ?1 @name )"
+template="name=Vmeas"}
+V {}
+S {}
+E {}
+L 4 0 -30 0 30 {}
+L 4 -7.5 0 -0 10 {}
+L 4 -0 10 7.5 0 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout propag=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout propag=0}
+T {@current} 10 2.5 0 0 0.2 0.2 {layer=15}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/arch_declarations.sym b/xschem/devices/arch_declarations.sym
new file mode 100644
index 0000000..88a1b39
--- /dev/null
+++ b/xschem/devices/arch_declarations.sym
@@ -0,0 +1,16 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=arch_declarations
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+template="
+
+signal AAA: std_logic;
+
+"}
+V {}
+S {}
+E {}
+L 4 -0 -10 355 -10 {}
+T {ARCHITECTURE DECLARATIONS} 5 -25 0 0 0.3 0.3 {}
+T {HIDDEN} 45 5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/architecture.sym b/xschem/devices/architecture.sym
new file mode 100644
index 0000000..cadb5a6
--- /dev/null
+++ b/xschem/devices/architecture.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=architecture
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+vhdl_ignore=true
+template=" nothing here, use global schematic properties "}
+V {}
+S {}
+E {}
+L 4 0 -10 355 -10 {}
+T {ARCHITECTURE} 5 -30 0 0 0.3 0.3 {}
+T {@schprop@schverilogprop@schvhdlprop@schsymbolprop} 45 5 0 0 0.3 0.3 {font=monospace layer=8}
diff --git a/xschem/devices/asrc.sym b/xschem/devices/asrc.sym
new file mode 100644
index 0000000..a3b0c3e
--- /dev/null
+++ b/xschem/devices/asrc.sym
@@ -0,0 +1,19 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @pinlist @function"
+template="name=B1 function=\\"v=tanh(v(1))\\""
+}
+V {}
+S {}
+E {}
+L 4 -20 -20 -10 -20 {}
+L 4 -15 -25 -15 -15 {}
+L 4 0 -30 0 30 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {@function} 20 0 0 0 0.2 0.2 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/assign.sym b/xschem/devices/assign.sym
new file mode 100644
index 0000000..ce5dc70
--- /dev/null
+++ b/xschem/devices/assign.sym
@@ -0,0 +1,17 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=delay
+function0="1"
+verilog_format="assign #@delay @@d = @@s ;"
+vhdl_format=" @@d <= @@s after @delay ns;"
+format="@name @pinlist 0"
+template="name=V1 delay=1"}
+V {}
+S {}
+E {}
+L 4 -30 0 30 0 {}
+L 4 -10 -5 10 0 {}
+L 4 -10 5 10 0 {}
+B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire }
+B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire goto=0 propag=0}
+T {@name @delay} -25 -10 0 0 0.1 0.1 {}
diff --git a/xschem/devices/attributes.sym b/xschem/devices/attributes.sym
new file mode 100644
index 0000000..f3fa1fb
--- /dev/null
+++ b/xschem/devices/attributes.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=attributes
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+template="
+ attribute async_set_reset of RPTL : signal is "true";
+"}
+V {}
+S {}
+E {}
+L 4 -0 -10 355 -10 {}
+T {VHDL ATTRIBUTES} 5 -25 0 0 0.3 0.3 {}
+T {@prop_ptr} 45 5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/bsource.sym b/xschem/devices/bsource.sym
new file mode 100644
index 0000000..808ac9d
--- /dev/null
+++ b/xschem/devices/bsource.sym
@@ -0,0 +1,21 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @pinlist @VAR = @FUNC "
+template="name=B1 VAR=I FUNC=\\"pwl(V(plus,minus),0,0, 1,10m, 2, 100m)\\""}
+V {}
+S {}
+E {}
+L 4 0 -30 0 -15 {}
+L 4 -10 0 10 0 {}
+L 4 0 15 0 30 {}
+L 4 -20 -20 -10 -20 {}
+L 4 -15 -25 -15 -15 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@VAR
+@FUNC} 20 0 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/bus_connect.sym b/xschem/devices/bus_connect.sym
new file mode 100644
index 0000000..01c1337
--- /dev/null
+++ b/xschem/devices/bus_connect.sym
@@ -0,0 +1,11 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=label
+format=".alias @lab"
+template="name=l1 lab=xxx"}
+V {}
+S {}
+E {}
+L 1 0 0 10 -10 {}
+B 5 9.375 -10.625 10.625 -9.375 {name=p dir=inout}
+T {@lab} 12.5 -12.5 3 0 0.27 0.27 {}
diff --git a/xschem/devices/bus_connect_nolab.sym b/xschem/devices/bus_connect_nolab.sym
new file mode 100644
index 0000000..b7a6b25
--- /dev/null
+++ b/xschem/devices/bus_connect_nolab.sym
@@ -0,0 +1,10 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=show_label
+template="name=r1"
+highlight=true}
+V {}
+S {}
+E {}
+L 1 0 0 10 -10 {}
+B 5 9.84375 -10.15625 10.15625 -9.84375 {name=x dir=inout}
diff --git a/xschem/devices/capa-2.sym b/xschem/devices/capa-2.sym
new file mode 100644
index 0000000..d86e224
--- /dev/null
+++ b/xschem/devices/capa-2.sym
@@ -0,0 +1,32 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=polarized_capacitor
+format="@name @pinlist @value m=@m"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+@comptag"
+verilog_ignore=true
+template="name=C1
+m=1
+value=1p
+footprint=1206
+device=polarized_capacitor
+}
+V {}
+S {}
+E {}
+L 4 0 5 0 30 {}
+L 4 0 -30 0 -5 {}
+L 4 -10 -5 10 -5 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout propag=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout propag=0 pinnumber=2}
+A 4 0 26.25 21.25 61.92751306414704 56.14497387170592 {}
+T {@value} 15 0 0 0 0.25 0.2 {}
+T {@name} 15 -13.75 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 16.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/capa.sym b/xschem/devices/capa.sym
new file mode 100644
index 0000000..d666ce8
--- /dev/null
+++ b/xschem/devices/capa.sym
@@ -0,0 +1,33 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=capacitor
+format="@name @pinlist @value m=@m"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+@comptag"
+verilog_ignore=true
+template="name=C1
+m=1
+value=1p
+footprint=1206
+device=\\"ceramic capacitor\\""
+}
+V {}
+S {}
+E {}
+L 4 0 5 0 30 {}
+L 4 0 -30 0 -5 {}
+L 4 -10 -5 10 -5 {}
+L 4 -10 5 10 5 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
+T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 16.25 0 1 0.2 0.2 {layer=13}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -6.25 0 0 0.2 0.2 {}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
+T {m=@m} 15 6.25 0 0 0.2 0.2 {}
diff --git a/xschem/devices/cccs.sym b/xschem/devices/cccs.sym
new file mode 100644
index 0000000..756f1cb
--- /dev/null
+++ b/xschem/devices/cccs.sym
@@ -0,0 +1,25 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=vcvs
+format="@name @pinlist @vnam @value"
+template="name=F1 vnam=v1 value=1"}
+V {}
+S {}
+E {}
+L 4 0 -20 20 -0 {}
+L 4 -20 0 0 -20 {}
+L 4 -20 0 0 20 {}
+L 4 0 20 20 0 {}
+L 4 0 20 0 30 {}
+L 4 0 -30 -0 -20 {}
+L 4 -5 5 0 10 {}
+L 4 -5 5 5 5 {}
+L 4 0 10 5 5 {}
+L 4 0 -5 0 5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=in}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=in}
+T {@value} 25 10 0 0 0.2 0.2 {}
+T {@name} 25 -15 0 0 0.2 0.2 {}
+T {@vnam} 25 -2.5 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/ccvs.sym b/xschem/devices/ccvs.sym
new file mode 100644
index 0000000..3dac8c5
--- /dev/null
+++ b/xschem/devices/ccvs.sym
@@ -0,0 +1,22 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=vcvs
+format="@name @pinlist @vnam @value"
+template="name=H1 vnam=v1 value=1"}
+V {}
+S {}
+E {}
+L 4 0 -20 20 -0 {}
+L 4 -20 0 0 -20 {}
+L 4 -20 0 0 20 {}
+L 4 0 20 20 0 {}
+L 4 0 -30 0 30 {}
+L 4 10 -20 20 -20 {}
+L 4 15 -25 15 -15 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+T {@value} 25 10 0 0 0.2 0.2 {}
+T {@name} 25 -15 0 0 0.2 0.2 {}
+T {@vnam} 25 -2.5 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/code.sym b/xschem/devices/code.sym
new file mode 100644
index 0000000..296db4f
--- /dev/null
+++ b/xschem/devices/code.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=netlist_commands
+template="name=s1 only_toplevel=false value=blabla"
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 4 20 30 60 30 {}
+L 4 20 40 40 40 {}
+L 4 20 50 60 50 {}
+L 4 20 60 50 60 {}
+L 4 20 70 50 70 {}
+L 4 20 80 90 80 {}
+L 4 20 90 40 90 {}
+L 4 20 20 70 20 {}
+L 4 20 10 40 10 {}
+L 4 100 10 110 10 {}
+L 4 110 10 110 110 {}
+L 4 20 110 110 110 {}
+L 4 20 100 20 110 {}
+L 4 100 0 100 100 {}
+L 4 10 100 100 100 {}
+L 4 10 0 10 100 {}
+L 4 10 0 100 0 {}
+T {@name} 15 -25 0 0 0.3 0.3 {}
diff --git a/xschem/devices/code_shown.sym b/xschem/devices/code_shown.sym
new file mode 100644
index 0000000..498ebb0
--- /dev/null
+++ b/xschem/devices/code_shown.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=netlist_commands
+template="name=s1 only_toplevel=false value=blabla"
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 4 0 -10 70 -10 {}
+L 4 0 -10 0 10 {}
+T {@name} 5 -30 0 0 0.3 0.3 {}
+T {@value} 15 -5 0 0 0.3 0.3 {}
diff --git a/xschem/devices/conn_10x2.sym b/xschem/devices/conn_10x2.sym
new file mode 100644
index 0000000..17999a8
--- /dev/null
+++ b/xschem/devices/conn_10x2.sym
@@ -0,0 +1,83 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=connector
+verilog_ignore=true
+format="*connector(8,1) @pinlist"
+tedax_format="footprint @name @footprint"
+template="name=c1 footprint=connector(8,1)"
+}
+V {}
+S {}
+E {}
+L 4 -30 -20 -20 -20 {}
+L 4 20 -20 30 -20 {}
+L 4 -30 0 -20 0 {}
+L 4 20 0 30 0 {}
+L 4 -30 20 -20 20 {}
+L 4 20 20 30 20 {}
+L 4 -30 40 -20 40 {}
+L 4 20 40 30 40 {}
+L 4 -30 60 -20 60 {}
+L 4 20 60 30 60 {}
+L 4 -30 80 -20 80 {}
+L 4 20 80 30 80 {}
+L 4 -30 100 -20 100 {}
+L 4 20 100 30 100 {}
+L 4 -30 120 -20 120 {}
+L 4 20 120 30 120 {}
+L 4 -30 140 -20 140 {}
+L 4 20 140 30 140 {}
+L 4 -30 160 -20 160 {}
+L 4 20 160 30 160 {}
+L 4 0 -30 0 170 {}
+L 4 -20 150 20 150 {}
+L 4 -20 130 20 130 {}
+L 4 -20 110 20 110 {}
+L 4 -20 90 20 90 {}
+L 4 -20 70 20 70 {}
+L 4 -20 50 20 50 {}
+L 4 -20 30 20 30 {}
+L 4 -20 10 20 10 {}
+L 4 -20 -10 20 -10 {}
+B 5 -31.25 -21.25 -28.75 -18.75 {name=conn_1 dir=inout pinnumber=1}
+B 5 -31.25 -1.25 -28.75 1.25 {name=conn_2 dir=inout pinnumber=2}
+B 5 -31.25 18.75 -28.75 21.25 {name=conn_3 dir=inout pinnumber=3}
+B 5 -31.25 38.75 -28.75 41.25 {name=conn_4 dir=inout pinnumber=4}
+B 5 -31.25 58.75 -28.75 61.25 {name=conn_5 dir=inout pinnumber=5}
+B 5 -31.25 78.75 -28.75 81.25 {name=conn_6 dir=inout pinnumber=6}
+B 5 -31.25 98.75 -28.75 101.25 {name=conn_7 dir=inout pinnumber=7}
+B 5 -31.25 118.75 -28.75 121.25 {name=conn_8 dir=inout pinnumber=8}
+B 5 -31.25 138.75 -28.75 141.25 {name=conn_7 dir=inout pinnumber=9}
+B 5 -31.25 158.75 -28.75 161.25 {name=conn_8 dir=inout pinnumber=10}
+B 5 28.75 158.75 31.25 161.25 {name=conn_1 dir=inout pinnumber=11}
+B 5 28.75 138.75 31.25 141.25 {name=conn_2 dir=inout pinnumber=12}
+B 5 28.75 118.75 31.25 121.25 {name=conn_3 dir=inout pinnumber=13}
+B 5 28.75 98.75 31.25 101.25 {name=conn_4 dir=inout pinnumber=14}
+B 5 28.75 78.75 31.25 81.25 {name=conn_5 dir=inout pinnumber=15}
+B 5 28.75 58.75 31.25 61.25 {name=conn_6 dir=inout pinnumber=16}
+B 5 28.75 38.75 31.25 41.25 {name=conn_7 dir=inout pinnumber=17}
+B 5 28.75 18.75 31.25 21.25 {name=conn_8 dir=inout pinnumber=18}
+B 5 28.75 -1.25 31.25 1.25 {name=conn_7 dir=inout pinnumber=19}
+B 5 28.75 -21.25 31.25 -18.75 {name=conn_8 dir=inout pinnumber=20}
+P 4 5 -20 170 20 170 20 -30 -20 -30 -20 170 {}
+T {@name} -13.75 -43.75 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -23.75 -31.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -23.75 -11.25 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} -23.75 8.75 0 1 0.2 0.2 {layer=13}
+T {@#3:pinnumber} -23.75 28.75 0 1 0.2 0.2 {layer=13}
+T {@#4:pinnumber} -23.75 48.75 0 1 0.2 0.2 {layer=13}
+T {@#5:pinnumber} -23.75 68.75 0 1 0.2 0.2 {layer=13}
+T {@#6:pinnumber} -23.75 88.75 0 1 0.2 0.2 {layer=13}
+T {@#7:pinnumber} -23.75 108.75 0 1 0.2 0.2 {layer=13}
+T {@#8:pinnumber} -23.75 128.75 0 1 0.2 0.2 {layer=13}
+T {@#9:pinnumber} -23.75 148.75 0 1 0.2 0.2 {layer=13}
+T {@#10:pinnumber} 23.75 148.75 0 0 0.2 0.2 {layer=13}
+T {@#11:pinnumber} 23.75 128.75 0 0 0.2 0.2 {layer=13}
+T {@#12:pinnumber} 23.75 108.75 0 0 0.2 0.2 {layer=13}
+T {@#13:pinnumber} 23.75 88.75 0 0 0.2 0.2 {layer=13}
+T {@#14:pinnumber} 23.75 68.75 0 0 0.2 0.2 {layer=13}
+T {@#15:pinnumber} 23.75 48.75 0 0 0.2 0.2 {layer=13}
+T {@#16:pinnumber} 23.75 28.75 0 0 0.2 0.2 {layer=13}
+T {@#17:pinnumber} 23.75 8.75 0 0 0.2 0.2 {layer=13}
+T {@#18:pinnumber} 23.75 -11.25 0 0 0.2 0.2 {layer=13}
+T {@#19:pinnumber} 23.75 -31.25 0 0 0.2 0.2 {layer=13}
diff --git a/xschem/devices/conn_14x1.sym b/xschem/devices/conn_14x1.sym
new file mode 100644
index 0000000..df10e8c
--- /dev/null
+++ b/xschem/devices/conn_14x1.sym
@@ -0,0 +1,60 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=connector
+verilog_ignore=true
+format="*connector(8,1) @pinlist"
+tedax_format="footprint @name @footprint
+device @name @device
+value @name @value
+@comptag"
+template="name=c1 footprint=connector(14,1)"
+}
+V {}
+S {}
+E {}
+B 5 18.75 -131.25 21.25 -128.75 {name=conn_1 dir=inout pinnumber=1}
+B 5 18.75 -111.25 21.25 -108.75 {name=conn_2 dir=inout pinnumber=2}
+B 5 18.75 -91.25 21.25 -88.75 {name=conn_3 dir=inout pinnumber=3}
+B 5 18.75 -71.25 21.25 -68.75 {name=conn_4 dir=inout pinnumber=4}
+B 5 18.75 -51.25 21.25 -48.75 {name=conn_5 dir=inout pinnumber=5}
+B 5 18.75 -31.25 21.25 -28.75 {name=conn_6 dir=inout pinnumber=6}
+B 5 18.75 -11.25 21.25 -8.75 {name=conn_7 dir=inout pinnumber=7}
+B 5 18.75 8.75 21.25 11.25 {name=conn_8 dir=inout pinnumber=8}
+B 5 18.75 28.75 21.25 31.25 {name=conn_9 dir=inout pinnumber=9}
+B 5 18.75 48.75 21.25 51.25 {name=conn_10 dir=inout pinnumber=10}
+B 5 18.75 68.75 21.25 71.25 {name=conn_11 dir=inout pinnumber=11}
+B 5 18.75 88.75 21.25 91.25 {name=conn_12 dir=inout pinnumber=12}
+B 5 18.75 108.75 21.25 111.25 {name=conn_13 dir=inout pinnumber=13}
+B 5 18.75 128.75 21.25 131.25 {name=conn_14 dir=inout pinnumber=14
+}
+A 4 15 -130 5 270 360 {}
+A 4 15 -110 5 270 360 {}
+A 4 15 -90 5 270 360 {}
+A 4 15 -70 5 270 360 {}
+A 4 15 -50 5 270 360 {}
+A 4 15 -30 5 270 360 {}
+A 4 15 -10 5 270 360 {}
+A 4 15 10 5 270 360 {}
+A 4 15 30 5 270 360 {}
+A 4 15 50 5 270 360 {}
+A 4 15 70 5 270 360 {}
+A 4 15 90 5 270 360 {}
+A 4 15 110 5 270 360 {}
+A 4 15 130 5 270 360 {}
+P 4 5 10 140 -10 140 -10 -140 10 -140 10 140 {}
+T {@#0:pinnumber} 6.25 -136.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} 6.25 -116.25 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 6.25 -96.25 0 1 0.2 0.2 {layer=13}
+T {@name} -18.75 -153.75 0 0 0.2 0.2 {}
+T {@#3:pinnumber} 6.25 -76.25 0 1 0.2 0.2 {layer=13}
+T {@#4:pinnumber} 6.25 -56.25 0 1 0.2 0.2 {layer=13}
+T {@#5:pinnumber} 6.25 -36.25 0 1 0.2 0.2 {layer=13}
+T {@#6:pinnumber} 6.25 -16.25 0 1 0.2 0.2 {layer=13}
+T {@#7:pinnumber} 6.25 3.75 0 1 0.2 0.2 {layer=13}
+T {@#8:pinnumber} 6.25 23.75 0 1 0.2 0.2 {layer=13}
+T {@#9:pinnumber} 6.25 43.75 0 1 0.2 0.2 {layer=13}
+T {@#10:pinnumber} 6.25 63.75 0 1 0.2 0.2 {layer=13}
+T {@#11:pinnumber} 6.25 83.75 0 1 0.2 0.2 {layer=13}
+T {@#12:pinnumber} 6.25 103.75 0 1 0.2 0.2 {layer=13}
+T {@#13:pinnumber} 6.25 123.75 0 1 0.2 0.2 {layer=13}
+T {@value} -18.75 -173.75 0 0 0.2 0.2 {}
diff --git a/xschem/devices/conn_3x1.sym b/xschem/devices/conn_3x1.sym
new file mode 100644
index 0000000..9cd49c1
--- /dev/null
+++ b/xschem/devices/conn_3x1.sym
@@ -0,0 +1,28 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=connector
+format="*connector(3,1) @pinlist"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=c1 footprint=connector(3,1)"
+}
+V {}
+S {}
+E {}
+B 5 18.75 -21.25 21.25 -18.75 {name=conn_1 dir=inout pinnumber=1}
+B 5 18.75 -1.25 21.25 1.25 {name=conn_2 dir=inout pinnumber=2}
+B 5 18.75 18.75 21.25 21.25 {name=conn_3 dir=inout pinnumber=3}
+A 4 15 -20 5 270 360 {}
+A 4 15 0 5 270 360 {}
+A 4 15 20 5 270 360 {}
+P 4 5 10 30 -10 30 -10 -30 10 -30 10 30 {}
+T {@#0:pinnumber} 7.5 -23.75 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} 7.5 -3.75 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 7.5 16.25 0 1 0.2 0.2 {layer=13}
+T {@name} -18.75 -43.75 0 0 0.2 0.2 {}
diff --git a/xschem/devices/conn_4x1.sym b/xschem/devices/conn_4x1.sym
new file mode 100644
index 0000000..5d60fe9
--- /dev/null
+++ b/xschem/devices/conn_4x1.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=connector
+format="*connector(3,1) @pinlist"
+tedax_format="footprint @name @footprint"
+template="name=c1 footprint=connector(3,1)"
+}
+V {}
+S {}
+E {}
+B 5 18.75 -31.25 21.25 -28.75 {name=conn_1 dir=inout pinnumber=1}
+B 5 18.75 -11.25 21.25 -8.75 {name=conn_2 dir=inout pinnumber=2}
+B 5 18.75 8.75 21.25 11.25 {name=conn_3 dir=inout pinnumber=3}
+B 5 18.75 28.75 21.25 31.25 {name=conn_4 dir=inout pinnumber=4}
+A 4 15 -30 5 270 360 {}
+A 4 15 -10 5 270 360 {}
+A 4 15 10 5 270 360 {}
+A 4 15 30 5 270 360 {}
+P 4 5 10 40 -10 40 -10 -40 10 -40 10 40 {}
+T {@#0:pinnumber} 7.5 -33.75 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} 7.5 -13.75 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 7.5 6.25 0 1 0.2 0.2 {layer=13}
+T {@name} -18.75 -53.75 0 0 0.2 0.2 {}
+T {@#3:pinnumber} 7.5 26.25 0 1 0.2 0.2 {layer=13}
diff --git a/xschem/devices/conn_6x1.sym b/xschem/devices/conn_6x1.sym
new file mode 100644
index 0000000..2e2da3e
--- /dev/null
+++ b/xschem/devices/conn_6x1.sym
@@ -0,0 +1,38 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=connector
+verilog_ignore=true
+format="*connector(6,1) @pinlist"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=c1 footprint=connector(6,1)"
+}
+V {}
+S {}
+E {}
+B 5 18.75 -21.25 21.25 -18.75 {name=conn_1 dir=inout pinnumber=1}
+B 5 18.75 -1.25 21.25 1.25 {name=conn_2 dir=inout pinnumber=2}
+B 5 18.75 18.75 21.25 21.25 {name=conn_3 dir=inout pinnumber=3}
+B 5 18.75 38.75 21.25 41.25 {name=conn_4 dir=inout pinnumber=4}
+B 5 18.75 58.75 21.25 61.25 {name=conn_5 dir=inout pinnumber=5}
+B 5 18.75 78.75 21.25 81.25 {name=conn_6 dir=inout pinnumber=6}
+A 4 15 -20 5 270 360 {}
+A 4 15 0 5 270 360 {}
+A 4 15 20 5 270 360 {}
+A 4 15 40 5 270 360 {}
+A 4 15 60 5 270 360 {}
+A 4 15 80 5 270 360 {}
+P 4 5 10 90 -10 90 -10 -30 10 -30 10 90 {}
+T {@#0:pinnumber} 6.25 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} 6.25 -6.25 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 6.25 13.75 0 1 0.2 0.2 {layer=13}
+T {@name} -18.75 -43.75 0 0 0.2 0.2 {}
+T {@#3:pinnumber} 6.25 33.75 0 1 0.2 0.2 {layer=13}
+T {@#4:pinnumber} 6.25 53.75 0 1 0.2 0.2 {layer=13}
+T {@#5:pinnumber} 6.25 73.75 0 1 0.2 0.2 {layer=13}
diff --git a/xschem/devices/conn_8x1.sym b/xschem/devices/conn_8x1.sym
new file mode 100644
index 0000000..1f76228
--- /dev/null
+++ b/xschem/devices/conn_8x1.sym
@@ -0,0 +1,44 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=connector
+verilog_ignore=true
+format="*connector(8,1) @pinlist"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=c1 footprint=connector(8,1)"
+}
+V {}
+S {}
+E {}
+B 5 18.75 -21.25 21.25 -18.75 {name=conn_1 dir=inout pinnumber=1}
+B 5 18.75 -1.25 21.25 1.25 {name=conn_2 dir=inout pinnumber=2}
+B 5 18.75 18.75 21.25 21.25 {name=conn_3 dir=inout pinnumber=3}
+B 5 18.75 38.75 21.25 41.25 {name=conn_4 dir=inout pinnumber=4}
+B 5 18.75 58.75 21.25 61.25 {name=conn_5 dir=inout pinnumber=5}
+B 5 18.75 78.75 21.25 81.25 {name=conn_6 dir=inout pinnumber=6}
+B 5 18.75 98.75 21.25 101.25 {name=conn_7 dir=inout pinnumber=7}
+B 5 18.75 118.75 21.25 121.25 {name=conn_8 dir=inout pinnumber=8}
+A 4 15 -20 5 270 360 {}
+A 4 15 0 5 270 360 {}
+A 4 15 20 5 270 360 {}
+A 4 15 40 5 270 360 {}
+A 4 15 60 5 270 360 {}
+A 4 15 80 5 270 360 {}
+A 4 15 100 5 270 360 {}
+A 4 15 120 5 270 360 {}
+P 4 5 10 130 -10 130 -10 -30 10 -30 10 130 {}
+T {@#0:pinnumber} 6.25 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} 6.25 -6.25 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 6.25 13.75 0 1 0.2 0.2 {layer=13}
+T {@name} -18.75 -43.75 0 0 0.2 0.2 {}
+T {@#3:pinnumber} 6.25 33.75 0 1 0.2 0.2 {layer=13}
+T {@#4:pinnumber} 6.25 53.75 0 1 0.2 0.2 {layer=13}
+T {@#5:pinnumber} 6.25 73.75 0 1 0.2 0.2 {layer=13}
+T {@#6:pinnumber} 6.25 93.75 0 1 0.2 0.2 {layer=13}
+T {@#7:pinnumber} 6.25 113.75 0 1 0.2 0.2 {layer=13}
diff --git a/xschem/devices/connect.sym b/xschem/devices/connect.sym
new file mode 100644
index 0000000..8cbd2c6
--- /dev/null
+++ b/xschem/devices/connect.sym
@@ -0,0 +1,25 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=resistor
+format="@name @pinlist 0.01 m=@m"
+template="name=R1 m=1"}
+V {}
+S {}
+E {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 0 -30 -0 -15 {}
+L 4 0 -15 5 -15 {}
+L 4 5 -15 5 15 {}
+L 4 -5 15 5 15 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 -15 0 -15 {}
+L 4 -0 15 -0 30 {}
+L 4 -5 -10 -0 -15 {}
+L 4 -5 -5 5 -15 {}
+L 4 -5 -0 5 -10 {}
+L 4 -5 5 5 -5 {}
+L 4 -5 10 5 0 {}
+L 4 -5 15 5 5 {}
+L 4 0 15 5 10 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=out propag=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=in propag=0}
diff --git a/xschem/devices/connector.sym b/xschem/devices/connector.sym
new file mode 100644
index 0000000..7c210e3
--- /dev/null
+++ b/xschem/devices/connector.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=connector
+format="*connector(1,1) @pinlist"
+tedax_format="footprint @name @footprint"
+template="name=c1 footprint=connector(1,1)"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=conn_1 dir=inout pinnumber=1}
+A 4 -5 0 5 270 360 {}
+P 4 5 -10 10 -30 10 -30 -10 -10 -10 -10 10 {}
+T {@#0:pinnumber} -13.75 -1.25 0 1 0.1 0.1 {}
+T {@name} -38.75 -23.75 0 0 0.2 0.2 {}
diff --git a/xschem/devices/crystal-2.sym b/xschem/devices/crystal-2.sym
new file mode 100644
index 0000000..bc08239
--- /dev/null
+++ b/xschem/devices/crystal-2.sym
@@ -0,0 +1,38 @@
+v {xschem version=2.9.5_RC6 file_version=1.1}
+G {type=crystal
+format="@name @pinlist @symname"
+verilog_format="tran @name (@@P\\\\, @@M\\\\);"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+@comptag"
+template="name=X1
+value=12MHz
+footprint=CRYSTAL\\ 300
+device=CRYSTAL"
+}
+V {}
+S {}
+E {}
+L 4 0 12.5 0 30 {}
+L 4 0 -30 0 -12.5 {}
+L 4 -15 12.5 15 12.5 {}
+L 4 -15 -12.5 15 -12.5 {}
+L 4 -30 -0 -15 -0 {}
+L 4 -15 0 -15 5 {}
+L 4 -18.75 5 -11.25 5 {}
+L 4 -18.75 7.5 -11.25 7.5 {}
+L 4 -15 7.5 -15 12.5 {}
+L 4 -15 -12.5 -15 -7.5 {}
+L 4 -18.75 -7.5 -11.25 -7.5 {}
+L 4 -18.75 -5 -11.25 -5 {}
+L 4 -15 -5 -15 0 {}
+B 4 -7.5 -7.5 7.5 7.5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1}
+B 5 -32.5 -2.5 -27.5 2.5 {name=G dir=inout propag=0 pinnumber=2}
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=3}
+T {@name} 25 -13.75 0 0 0.2 0.2 {}
+T {@value} 25 1.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} 5 -26.25 0 0 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 5 16.25 0 0 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -22.5 -13.75 0 1 0.2 0.2 {layer=13}
diff --git a/xschem/devices/crystal.sym b/xschem/devices/crystal.sym
new file mode 100644
index 0000000..b86ba5a
--- /dev/null
+++ b/xschem/devices/crystal.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=crystal
+format="@name @pinlist @symname"
+verilog_format="tran @name (@@P\\\\, @@M\\\\);"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+@comptag"
+template="name=X1
+value=12MHz
+footprint=CRYSTAL\\ 300
+device=CRYSTAL"
+}
+V {}
+S {}
+E {}
+L 4 0 12.5 0 30 {}
+L 4 0 -30 0 -12.5 {}
+L 4 -15 12.5 15 12.5 {}
+L 4 -15 -12.5 15 -12.5 {}
+B 4 -7.5 -7.5 7.5 7.5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2}
+T {@name} 25 -13.75 0 0 0.2 0.2 {}
+T {@value} 25 1.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/dac_bridge.sym b/xschem/devices/dac_bridge.sym
new file mode 100644
index 0000000..d3366a2
--- /dev/null
+++ b/xschem/devices/dac_bridge.sym
@@ -0,0 +1,17 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=delay
+verilog_ignore=true
+vhdl_ignore=true
+format="@name [ @@s ] [ @@d ] @dac_bridge_model"
+template="name=A1 dac_bridge_model= dac_buff"
+}
+V {}
+S {}
+E {}
+L 4 -30 0 30 0 {}
+L 4 -10 -5 10 0 {}
+L 4 -10 5 10 0 {}
+B 5 27.5 -2.5 32.5 2.5 {name=d dir=out verilog_type=wire propag=1}
+B 5 -32.5 -2.5 -27.5 2.5 {name=s dir=in verilog_type=wire propag=0}
+T {@name} -25 -10 0 0 0.12 0.12 {}
+T {@dac_bridge_model} 0 -10 0 0 0.12 0.12 {}
diff --git a/xschem/devices/delay.sym b/xschem/devices/delay.sym
new file mode 100644
index 0000000..2093165
--- /dev/null
+++ b/xschem/devices/delay.sym
@@ -0,0 +1,17 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=delay_eldo
+format="del@name @pinlist @del"
+template="name=d1 del=2e-9"}
+V {}
+S {}
+E {}
+L 4 -40 0 -30 0 {}
+L 4 -30 -10 -30 10 {}
+L 4 -30 10 30 10 {}
+L 4 30 -10 30 10 {}
+L 4 -30 -10 30 -10 {}
+L 4 30 -0 40 -0 {}
+B 5 -42.5 -2.5 -37.5 2.5 {name=inp dir=in}
+B 5 37.5 -2.5 42.5 2.5 {name=outp dir=out}
+T {del=@del} -27.5 -3.75 0 0 0.15 0.15 {}
+T {@name} -25 -22.5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/delay_line.sym b/xschem/devices/delay_line.sym
new file mode 100644
index 0000000..31f4044
--- /dev/null
+++ b/xschem/devices/delay_line.sym
@@ -0,0 +1,20 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=transmission_line
+format="@name @pinlist z0=@z0 td=@td"
+template="name=T1 z0=50 td=10n"}
+V {}
+S {}
+E {}
+L 4 -70 -15 70 -15 {}
+L 4 -70 -5 70 -5 {}
+L 4 -70 -5 -70 10 {}
+L 4 -80 10 -70 10 {}
+L 4 70 -5 70 10 {}
+L 4 70 10 80 10 {}
+L 4 -80 -10 80 -10 {}
+B 5 -82.5 -12.5 -77.5 -7.5 {name=nap dir=in}
+B 5 -82.5 7.5 -77.5 12.5 {name=nam dir=in}
+B 5 77.5 -12.5 82.5 -7.5 {name=nbp dir=out}
+B 5 77.5 7.5 82.5 12.5 {name=nbm dir=out}
+T {z0=@z0 delay=@td} -60 -30 0 0 0.25 0.2 {}
+T {@name} -40 -47.5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/diode.sym b/xschem/devices/diode.sym
new file mode 100644
index 0000000..787d7c7
--- /dev/null
+++ b/xschem/devices/diode.sym
@@ -0,0 +1,29 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=diode
+format="@name @pinlist @model area=@area"
+function1="U H 0 m"
+function0="L U 1 m"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=D1 model=D1N914 area=1"}
+V {}
+S {}
+E {}
+L 4 0 5 0 30 {}
+L 4 0 -30 0 -5 {}
+L 4 -10 5 10 5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1 propag=1 goto=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2 goto=0}
+P 4 4 -0 5 -10 -5 10 -5 0 5 {fill=true}
+T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@model} 15 -6.25 0 0 0.2 0.2 {}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/flash_cell.sym b/xschem/devices/flash_cell.sym
new file mode 100644
index 0000000..6bd8a99
--- /dev/null
+++ b/xschem/devices/flash_cell.sym
@@ -0,0 +1,26 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=flash
+vhdl_stop=true
+format="@name @pinlist @model dvt=@dvt width=@width length=@length m=1"
+template="name=X1 model=flash1 dvt=0 width=0.16u length=0.3u m=1"}
+V {}
+S {}
+E {}
+L 4 -15 -30 -15 30 {}
+L 4 -15 -20 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 -15 20 0 20 {}
+L 4 0 20 0 30 {}
+L 4 -30 -15 -30 15 {}
+L 4 -30 0 -30 5 {}
+L 4 -40 0 -32.5 0 {}
+L 4 -40 0 -30 0 {}
+L 4 -15 0 0 0 {}
+L 8 -22.5 -15 -22.5 15 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=D dir=inout}
+B 5 -42.5 -2.5 -37.5 2.5 {name=G dir=in}
+B 5 -2.5 27.5 2.5 32.5 {name=S dir=inout}
+B 5 -2.5 -2.5 2.5 2.5 {name=B dir=in}
+T {DVT=@dvt} -11 4 0 0 0.2 0.2 {}
+T {@name} -10 -12 0 0 0.2 0.2 {}
diff --git a/xschem/devices/generic_pin.sym b/xschem/devices/generic_pin.sym
new file mode 100644
index 0000000..367bba5
--- /dev/null
+++ b/xschem/devices/generic_pin.sym
@@ -0,0 +1,12 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=generic
+template="name=g1 generic_type=time value=\\"2 ns\\" lab=xxx"}
+V {}
+S {}
+E {}
+L 8 -15 -5 -5 -5 {}
+L 8 -5 -5 0 0 {}
+L 8 -5 5 0 0 {}
+L 8 -15 5 -5 5 {}
+L 8 -15 -5 -15 5 {}
+T {@lab : @generic_type := @value} -17.5 -7.5 0 1 0.3 0.3 {}
diff --git a/xschem/devices/gnd.sym b/xschem/devices/gnd.sym
new file mode 100644
index 0000000..00a0c98
--- /dev/null
+++ b/xschem/devices/gnd.sym
@@ -0,0 +1,16 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=label
+function0="L"
+global=true
+format="*.alias @lab"
+template="name=l1 lab=GND"}
+V {}
+S {}
+E {}
+L 4 0 0 0 12.5 {}
+L 4 -5 12.5 5 12.5 {}
+L 4 0 17.5 5 12.5 {}
+L 4 -5 12.5 0 17.5 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout goto=0}
+T {@lab} 7.5 5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/ind.sym b/xschem/devices/ind.sym
new file mode 100644
index 0000000..4738bd3
--- /dev/null
+++ b/xschem/devices/ind.sym
@@ -0,0 +1,48 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=inductor
+format="@name @pinlist @value m=@m"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+@comptag"
+template="name=L1
+m=1
+value=1n
+footprint=1206
+device=inductor"}
+V {}
+S {}
+E {}
+L 4 7.5 -26.25 7.5 -21.25 {}
+L 4 5 -23.75 10 -23.75 {}
+L 4 0 20 0 30 {}
+L 4 0 -30 0 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout propag=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout propag=0 pinnumber=2}
+A 4 -2.96875 7.5 4.506939094329987 123.6900675259798 112.6198649480404 {}
+A 4 -2.96875 0 4.506939094329987 123.6900675259798 112.6198649480404 {}
+A 4 -2.96875 -7.5 4.506939094329987 123.6900675259798 112.6198649480404 {}
+A 4 -2.96875 -15 4.506939094329987 123.6900675259798 112.6198649480404 {}
+A 4 -2.96875 15 4.506939094329987 123.6900675259798 112.6198649480404 {}
+A 4 3.835589171974519 23.41859076433121 15.31813724370252 77.95854130716134 49.44368436931695 {}
+A 4 0.693993506493513 1.109983766233766 11.86588963153925 238.7102444862858 65.37387308202111 {}
+A 4 6.477272727272734 9.776278409090908 1.448867988239896 306.7294670949065 120.7910985079907 {}
+A 4 3.835589171974519 15.91859076433121 15.31813724370252 77.95854130716134 49.44368436931695 {}
+A 4 0.693993506493513 -6.390016233766234 11.86588963153925 238.7102444862858 65.37387308202111 {}
+A 4 6.477272727272734 2.276278409090908 1.448867988239896 306.7294670949065 120.7910985079907 {}
+A 4 3.835589171974519 8.41859076433121 15.31813724370252 77.95854130716134 49.44368436931695 {}
+A 4 0.693993506493513 -13.89001623376623 11.86588963153925 238.7102444862858 65.37387308202111 {}
+A 4 6.477272727272734 -5.223721590909092 1.448867988239896 306.7294670949065 120.7910985079907 {}
+A 4 3.835589171974519 0.9185907643312099 15.31813724370252 77.95854130716134 49.44368436931695 {}
+A 4 0.693993506493513 -21.39001623376623 11.86588963153925 238.7102444862858 65.37387308202111 {}
+A 4 6.477272727272734 -12.72372159090909 1.448867988239896 306.7294670949065 120.7910985079907 {}
+A 4 -0.8264802631578947 11.02796052631579 9.010025634965597 238.9869162847902 36.27616431119463 {}
+A 4 -0.8339654126213593 -11.06070805521845 8.978108864537402 84.67018262004025 36.40963787914448 {}
+T {@#0:pinnumber} -10 -27.5 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 17.5 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@value} 15 -3.75 0 0 0.2 0.2 {}
+T {m=@m} 15 11.25 0 0 0.2 0.2 {}
diff --git a/xschem/devices/iopin.sym b/xschem/devices/iopin.sym
new file mode 100644
index 0000000..19f8eae
--- /dev/null
+++ b/xschem/devices/iopin.sym
@@ -0,0 +1,11 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=iopin
+format="*.iopin @lab"
+template="name=p1 lab=xxx"
+}
+V {}
+S {}
+E {}
+B 5 -0.0098 -0.009765619999999999 0.0098 0.009765619999999999 {name=p dir=inout}
+P 5 7 0 0 5.625 -4.84375 10.7812 -4.84375 16.4062 -0 10.7812 4.84375 5.625 4.84375 -0 0 {fill=true}
+T {@lab} 19.8438 -8.75 0 0 0.33 0.33 {}
diff --git a/xschem/devices/ipin.sym b/xschem/devices/ipin.sym
new file mode 100644
index 0000000..348e415
--- /dev/null
+++ b/xschem/devices/ipin.sym
@@ -0,0 +1,12 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=ipin
+format="*.ipin @lab"
+template="name=p1 lab=xxx"
+}
+V {}
+S {}
+E {}
+B 5 -0.009765619999999999 -0.009765619999999999 0.009765619999999999 0.009765619999999999 {name=p dir=out}
+P 5 6 -0 -0 -6.25 -5 -14.375 -5 -14.375 5 -6.25 5 0 0 {fill=true}
+T {@lab} -18.75 -8.75 0 1 0.33 0.33 {}
diff --git a/xschem/devices/isource.sym b/xschem/devices/isource.sym
new file mode 100644
index 0000000..27ea873
--- /dev/null
+++ b/xschem/devices/isource.sym
@@ -0,0 +1,20 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @pinlist @value"
+template="name=I0 value=1m"}
+V {}
+S {}
+E {}
+L 4 0 -30 0 -15 {}
+L 4 0 15 0 30 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+P 4 7 -0 -7.5 -0 2.5 2.5 2.5 -0 10 -2.5 2.5 0 2.5 -0 -7.5 {fill=true}
+T {@name
+@value} 20 -10 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/isource_arith.sym b/xschem/devices/isource_arith.sym
new file mode 100644
index 0000000..21b7cea
--- /dev/null
+++ b/xschem/devices/isource_arith.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @pinlist CUR=' @CUR ' MIN=' @MIN ' MAX=' @MAX ' "
+template="name=G1 CUR=cos(V(IN)) MIN=-2 MAX=2"}
+V {}
+S {}
+E {}
+L 4 0 -30 0 -15 {}
+L 4 -10 0 10 0 {}
+L 4 -20 12.5 -17.5 5 {}
+L 4 -22.5 5 -17.5 5 {}
+L 4 -22.5 5 -20 12.5 {}
+L 4 0 15 0 30 {}
+L 4 -20 -12.5 -20 5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@CUR
+MIN=@MIN
+MAX=@MAX} 20 0 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/isource_pwl.sym b/xschem/devices/isource_pwl.sym
new file mode 100644
index 0000000..0102820
--- /dev/null
+++ b/xschem/devices/isource_pwl.sym
@@ -0,0 +1,40 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @@p @@m pwl(1) @@cp @@cm @TABLE"
+template="name=G1 TABLE=\\"1 0 2 1m\\""
+}
+V {}
+S {}
+E {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 -20 0 0 -20 {}
+L 4 -20 0 0 20 {}
+L 4 0 20 20 0 {}
+L 4 0 -20 20 0 {}
+L 4 -40 -20 -35 -20 {}
+L 4 -30 -20 -25 -20 {}
+L 4 -20 -20 -15 -20 {}
+L 4 -40 20 -35 20 {}
+L 4 -30 20 -25 20 {}
+L 4 -20 20 -15 20 {}
+L 4 0 20 0 30 {}
+L 4 0 -30 0 -20 {}
+L 4 -5 5 0 10 {}
+L 4 -5 5 5 5 {}
+L 4 0 10 5 5 {}
+L 4 0 -5 0 5 {}
+L 4 -37.5 -12.5 -32.5 -12.5 {}
+L 4 -35 -15 -35 -10 {}
+L 4 -37.5 12.5 -32.5 12.5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+B 5 -42.5 -22.5 -37.5 -17.5 {name=cp dir=in}
+B 5 -42.5 17.5 -37.5 22.5 {name=cm dir=in}
+T {pwl(1)=@TABLE} 20 0 0 0 0.2 0.2 {}
+T {@name} 20 -15 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} -45 -32.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} -45 22.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/isource_table.sym b/xschem/devices/isource_table.sym
new file mode 100644
index 0000000..531efe5
--- /dev/null
+++ b/xschem/devices/isource_table.sym
@@ -0,0 +1,23 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @pinlist TABLE \{ @CTRL \} = @TABLE"
+template="name=G1 CTRL=\\"V(plus,minus)\\" TABLE=\\"(0, 0) (1, 100m) (2, 300m)\\""}
+V {}
+S {}
+E {}
+L 4 0 -30 0 -15 {}
+L 4 -10 0 10 0 {}
+L 4 -20 12.5 -17.5 5 {}
+L 4 -22.5 5 -17.5 5 {}
+L 4 -22.5 5 -20 12.5 {}
+L 4 0 15 0 30 {}
+L 4 -20 -12.5 -20 5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@CTRL
+@TABLE} 20 0 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/jumper.sym b/xschem/devices/jumper.sym
new file mode 100644
index 0000000..c2d99f2
--- /dev/null
+++ b/xschem/devices/jumper.sym
@@ -0,0 +1,28 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=jumper
+format="* @name @pinlist"
+verilog_format="// @name (@@P\\\\, @@M\\\\);"
+tedax_format="footprint @name @footprint
+device @name @device"
+template="name=J1
+footprint=JUMPER2
+device=JUMPER"
+}
+V {}
+S {}
+E {}
+L 4 0 15 0 30 {}
+L 4 0 -30 0 -15 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2}
+A 4 0 12.5 2.5 270 360 {}
+A 4 0 -12.5 2.5 270 360 {}
+T {@name} 15 -13.75 0 0 0.2 0.2 {}
+T {@value} 15 1.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/k.sym b/xschem/devices/k.sym
new file mode 100644
index 0000000..7d15129
--- /dev/null
+++ b/xschem/devices/k.sym
@@ -0,0 +1,13 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=coupler
+format="@name @L1 @L2 @K"
+template="name=K1 K=0.9 L1=L1 L2=L2"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 -5 -30 -5 30 {}
+T {K=@K} -20 60 0 0 0.25 0.2 {}
+T {@name} -20 42.5 0 0 0.2 0.2 {}
+T {@L1} -10 -10 0 1 0.25 0.2 {}
+T {@L2} 10 -10 0 0 0.25 0.2 {}
diff --git a/xschem/devices/lab_generic.sym b/xschem/devices/lab_generic.sym
new file mode 100644
index 0000000..01ae745
--- /dev/null
+++ b/xschem/devices/lab_generic.sym
@@ -0,0 +1,9 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=label
+format=".alias @lab"
+template="name=l1 lab=lll value=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab = @value} -7.5 -5 0 1 0.3 0.3 {}
diff --git a/xschem/devices/lab_pin.sym b/xschem/devices/lab_pin.sym
new file mode 100644
index 0000000..e80c512
--- /dev/null
+++ b/xschem/devices/lab_pin.sym
@@ -0,0 +1,10 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -7.5 -8.125 0 1 0.33 0.33 {}
diff --git a/xschem/devices/lab_show.sym b/xschem/devices/lab_show.sym
new file mode 100644
index 0000000..f2a1516
--- /dev/null
+++ b/xschem/devices/lab_show.sym
@@ -0,0 +1,12 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=show_label
+template="name=l1"
+net_name=true
+highlight=true}
+V {}
+S {}
+E {}
+L 4 -20 -20 0 0 {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@#0:net_name} -22.5 -30.625 0 1 0.33 0.33 {}
diff --git a/xschem/devices/lab_wire.sym b/xschem/devices/lab_wire.sym
new file mode 100644
index 0000000..dd9788a
--- /dev/null
+++ b/xschem/devices/lab_wire.sym
@@ -0,0 +1,9 @@
+v {xschem version=2.9.5_RC6 file_version=1.1}
+G {type=label
+format="*.alias @lab"
+template="name=l1 sig_type=std_logic lab=xxx"}
+V {}
+S {}
+E {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
+T {@lab} -2.5 -1.25 2 0 0.27 0.27 {}
diff --git a/xschem/devices/launcher.sym b/xschem/devices/launcher.sym
new file mode 100644
index 0000000..dd05f20
--- /dev/null
+++ b/xschem/devices/launcher.sym
@@ -0,0 +1,15 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=launcher
+format="** @descr : @url"
+verilog_ignore=true
+vhdl_ignore=true
+spice_ignore=true
+template="name=h1
+descr=google
+url=www.google.com"}
+V {}
+S {}
+E {}
+P 4 9 -0 -0 -30 -12.5 -30 -5 -60 -5 -50 0 -60 5 -30 5 -30 12.5 -0 0 {fill=true}
+T {@descr} 10 0 0 0 0.4 0.4 {vcenter=true}
diff --git a/xschem/devices/led.sym b/xschem/devices/led.sym
new file mode 100644
index 0000000..93f5669
--- /dev/null
+++ b/xschem/devices/led.sym
@@ -0,0 +1,34 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=diode
+format="@spiceprefix@name @pinlist @model"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=X1 model=XXX device=XXX"}
+V {}
+S {}
+E {}
+L 4 0 5 0 30 {}
+L 4 0 -30 0 -5 {}
+L 4 -20 5 20 5 {}
+L 4 -30 -2.5 -20 -12.5 {}
+L 4 -30 -12.5 -30 -2.5 {}
+L 4 -45 2.5 -30 -12.5 {}
+L 4 -35 10 -25 0 {}
+L 4 -35 0 -35 10 {}
+L 4 -50 15 -35 0 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
+P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
+T {@name} 7.5 -20 0 0 0.2 0.2 {}
+T {@value} 7.5 12.5 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 16.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/netlist.sym b/xschem/devices/netlist.sym
new file mode 100644
index 0000000..374468b
--- /dev/null
+++ b/xschem/devices/netlist.sym
@@ -0,0 +1,13 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=netlist_commands
+template="name=s1 value=blabla"
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 4 0 -10 70 -10 {}
+L 4 0 -10 0 10 {}
+T {NETLIST} 5 -25 0 0 0.3 0.3 {}
+T {@value} 15 -5 0 0 0.3 0.3 {}
diff --git a/xschem/devices/netlist_at_end.sym b/xschem/devices/netlist_at_end.sym
new file mode 100644
index 0000000..ba40f94
--- /dev/null
+++ b/xschem/devices/netlist_at_end.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=netlist_commands
+place=end
+template="name=s1 value=blabla"
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 4 0 -10 70 -10 {}
+L 4 0 -10 0 10 {}
+T {@name} 5 -25 0 0 0.3 0.3 {}
+T {@value} 15 -5 0 0 0.3 0.3 {}
diff --git a/xschem/devices/netlist_not_shown.sym b/xschem/devices/netlist_not_shown.sym
new file mode 100644
index 0000000..4250d2d
--- /dev/null
+++ b/xschem/devices/netlist_not_shown.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=netlist_commands
+template="name=s1 only_toplevel=false value=blabla"
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 4 100 10 110 10 {}
+L 4 110 10 110 110 {}
+L 4 20 110 110 110 {}
+L 4 20 100 20 110 {}
+L 4 100 0 100 100 {}
+L 4 10 100 100 100 {}
+L 4 10 0 10 100 {}
+L 4 10 0 100 0 {}
+L 4 20 30 60 30 {}
+L 4 20 40 40 40 {}
+L 4 20 50 60 50 {}
+L 4 20 60 50 60 {}
+L 4 20 70 50 70 {}
+L 4 20 80 90 80 {}
+L 4 20 90 40 90 {}
+L 4 20 20 70 20 {}
+L 4 20 10 40 10 {}
+T {@name} 15 -25 0 0 0.3 0.3 {}
diff --git a/xschem/devices/netlist_not_shown_at_end.sym b/xschem/devices/netlist_not_shown_at_end.sym
new file mode 100644
index 0000000..6ff33f8
--- /dev/null
+++ b/xschem/devices/netlist_not_shown_at_end.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=netlist_commands
+place=end
+vhdl_ignore=true
+verilog_ignore=true
+template="name=s1 value=blabla"
+format="
+@value
+"}
+V {}
+S {}
+E {}
+L 4 100 0 100 100 {}
+L 4 10 100 100 100 {}
+L 4 10 0 10 100 {}
+L 4 10 0 100 0 {}
+L 4 100 10 110 10 {}
+L 4 110 10 110 110 {}
+L 4 20 110 110 110 {}
+L 4 20 100 20 110 {}
+L 4 20 30 60 30 {}
+L 4 20 40 40 40 {}
+L 4 20 50 60 50 {}
+L 4 20 60 50 60 {}
+L 4 20 70 50 70 {}
+L 4 20 80 90 80 {}
+L 4 20 90 40 90 {}
+L 4 20 20 70 20 {}
+L 4 20 10 40 10 {}
+T {@name} 15 -25 0 0 0.3 0.3 {}
diff --git a/xschem/devices/netlist_options.sym b/xschem/devices/netlist_options.sym
new file mode 100644
index 0000000..8bb2f4d
--- /dev/null
+++ b/xschem/devices/netlist_options.sym
@@ -0,0 +1,16 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=netlist_options
+template="
+bus_replacement_char="[]"
+top_subckt=false
+spiceprefix=true
+hiersep=.
+"
+}
+V {}
+S {}
+E {}
+L 4 -0 -10 355 -10 {}
+T {NETLIST_OPTIONS} 5 -25 0 0 0.3 0.3 {}
+T {@prop_ptr} 45 5 0 0 0.3 0.3 {layer=8}
diff --git a/xschem/devices/ngspice_get_expr.sym b/xschem/devices/ngspice_get_expr.sym
new file mode 100644
index 0000000..9a7d9cb
--- /dev/null
+++ b/xschem/devices/ngspice_get_expr.sym
@@ -0,0 +1,15 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=raw_data_show
+vhdl_ignore=true
+spice_ignore=false
+verilog_ignore=true
+tedax_ignore=true
+template="name=r1 node=xxx
+descr=\\"I=\\""}
+V {}
+S {}
+E {}
+A 15 0 0 1.875 90 360 {fill=true}
+T {tcleval(@node\\)} 6.875 -16.09375 0 0 0.2 0.2 {layer=15}
+T {@descr} 6.875 -28.59375 0 0 0.2 0.2 {layer=15}
diff --git a/xschem/devices/ngspice_get_value.sym b/xschem/devices/ngspice_get_value.sym
new file mode 100644
index 0000000..c50b9d9
--- /dev/null
+++ b/xschem/devices/ngspice_get_value.sym
@@ -0,0 +1,15 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=raw_data_show
+vhdl_ignore=true
+spice_ignore=false
+verilog_ignore=true
+tedax_ignore=true
+template="name=r1 node=xxx
+descr=\\"I=\\""}
+V {}
+S {}
+E {}
+A 15 0 0 1.875 90 360 {fill=true}
+T {tcleval([ ngspice::get_node [subst -nocommand \{@node\\\}] ] )} 4.375 -8.59375 0 0 0.2 0.2 {vcenter=true layer=15}
+T {@descr} 4.375 -21.09375 0 0 0.2 0.2 {vcenter=true layer=15}
diff --git a/xschem/devices/ngspice_probe.sym b/xschem/devices/ngspice_probe.sym
new file mode 100644
index 0000000..c09e716
--- /dev/null
+++ b/xschem/devices/ngspice_probe.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=ngprobe
+vhdl_ignore=true
+spice_ignore=false
+verilog_ignore=true
+tedax_ignore=true
+template="name=r1"}
+V {}
+S {}
+E {}
+L 15 -0 -0 5 -5 {}
+B 5 -0.46875 -0.46875 0.46875 0.46875 {name=p dir=xxx}
+T {tcleval( [ ngspice::get_node v([set path]@@p\\) ] )} 6.875 -13.59375 0 0 0.2 0.2 {vcenter=true layer=15}
diff --git a/xschem/devices/nmos-sub.sym b/xschem/devices/nmos-sub.sym
new file mode 100644
index 0000000..c63e31d
--- /dev/null
+++ b/xschem/devices/nmos-sub.sym
@@ -0,0 +1,26 @@
+v {xschem version=2.9.5_RC8 file_version=1.1}
+G {type=nmos
+format="@name @pinlist @substrate @model w=@w l=@l m=@m"
+template="name=M1 model=nmos substrate=VSS w=5u l=0.18u m=1"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 0 -5 5 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 -5 0 {}
+L 4 10 0 20 0 {}
+L 4 5 -5 10 0 {}
+L 4 5 5 10 -0 {}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
+T {@w\\/@l\\/@m} 7.5 -17.5 0 0 0.2 0.2 {}
+T {@name} 7.5 6.25 0 0 0.2 0.2 {}
+T {D} 25 -27.5 0 0 0.15 0.15 {}
+T {@substrate} 22.5 -3.125 0 0 0.1 0.1 {layer=4}
diff --git a/xschem/devices/nmos.sym b/xschem/devices/nmos.sym
new file mode 100644
index 0000000..b2f177c
--- /dev/null
+++ b/xschem/devices/nmos.sym
@@ -0,0 +1,35 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=nmos
+format="@spiceprefix@name @pinlist @model @extra m=@m"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=M1 model=M2N7002 device=2N7002 footprint=SOT23 m=1"
+verilog_format="@symname #@del @name ( @@d , @@s , @@g );"}
+V {}
+S {}
+E {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 0 -5 5 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 -5 0 {}
+L 4 5 -27.5 5 27.5 {}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout pinnumber=3}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in pinnumber=1}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout pinnumber=2}
+T {@#0:pinnumber} 25 -27.5 0 0 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 25 17.5 0 0 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -8.75 6.25 0 1 0.2 0.2 {layer=13}
+T {@device} 21.25 -11.25 0 0 0.2 0.2 {}
+T {@name} 21.25 3.75 0 0 0.2 0.2 {}
+T {D} 10 -17.5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/nmos3.sym b/xschem/devices/nmos3.sym
new file mode 100644
index 0000000..a335f7a
--- /dev/null
+++ b/xschem/devices/nmos3.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=nmos
+format="@name @pinlist @model m=@m"
+template="name=X1 model=irf540 m=1"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -20 0 -5 0 {}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout pinnumber=1}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in pinnumber=2}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout pinnumber=3}
+T {D} 7.5 -17.5 0 0 0.2 0.2 {}
+T {@name} 8.75 6.25 0 0 0.2 0.2 {}
+T {@model x @m} 8.75 -6.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} 25 -27.5 0 0 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 25 17.5 0 0 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 6.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/nmos4.sym b/xschem/devices/nmos4.sym
new file mode 100644
index 0000000..0afe519
--- /dev/null
+++ b/xschem/devices/nmos4.sym
@@ -0,0 +1,32 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=nmos
+format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
+template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
+verilog_format="nmos #@del @name ( @@d , @@s , @@g );"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 0 -5 5 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 -5 0 {}
+L 4 10 0 20 0 {}
+L 4 5 -5 10 0 {}
+L 4 5 5 10 -0 {}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
+B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
+T {@w\\/@l\\/@m} 7.5 -18.75 0 0 0.2 0.2 {}
+T {@spiceprefix@name} 7.5 7.5 0 0 0.2 0.2 {}
+T {D} 25 -27.5 0 0 0.15 0.15 {}
+T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/nmos4_depl.sym b/xschem/devices/nmos4_depl.sym
new file mode 100644
index 0000000..902cd3a
--- /dev/null
+++ b/xschem/devices/nmos4_depl.sym
@@ -0,0 +1,33 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=nmos
+format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
+template="name=M1 model=nmos_depl w=5u l=0.18u del=0 m=1"
+verilog_format="rnmos #@del @name ( @@s , @@d , @@d );"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 10 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 10 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 0 -5 5 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 -5 0 {}
+L 4 15 0 20 0 {}
+L 4 10 -5 15 0 {}
+L 4 10 5 15 0 {}
+B 4 5 -20 10 20 {}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
+B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
+T {@w\\/@l\\/@m} 12.5 -18.75 0 0 0.2 0.2 {}
+T {@spiceprefix@name} 12.5 7.5 0 0 0.2 0.2 {}
+T {D} 25 -30 0 0 0.15 0.15 {}
+T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/noconn.sym b/xschem/devices/noconn.sym
new file mode 100644
index 0000000..14e3045
--- /dev/null
+++ b/xschem/devices/noconn.sym
@@ -0,0 +1,15 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=noconn
+format="* noconn "
+vhdl_ignore=true
+verilog_ignore=true
+spice_ignore=true
+template="name=l1"}
+V {}
+S {}
+E {}
+L 4 -3.75 0 0 -0 {}
+B 5 -1.25 -1.25 1.25 1.25 {name=p dir=inout}
+T {@#0:net_name} -20.625 -4.375 0 1 0.15 0.15 {layer=15}
+T {NC} -16.25 -4.375 0 0 0.15 0.15 { layer=4}
diff --git a/xschem/devices/npn.sym b/xschem/devices/npn.sym
new file mode 100644
index 0000000..981507b
--- /dev/null
+++ b/xschem/devices/npn.sym
@@ -0,0 +1,39 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=npn
+format="@name @pinlist @model area=@area m=@m"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=Q1
+model=MMBT2222
+device=MMBT2222
+footprint=SOT23
+area=1
+m=1"
+}
+V {}
+S {}
+E {}
+L 4 0 -30 0 30 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 0 0 {}
+L 4 -0 10 8.75 18.75 {}
+L 4 0 -10 20 -30 {}
+B 5 17.5 -32.5 22.5 -27.5 {name=C dir=inout pinnumber=3}
+B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1}
+B 5 17.5 27.5 22.5 32.5 {name=E dir=inout pinnumber=2}
+P 4 4 20 30 13.75 13.75 3.75 23.75 20 30 {fill=true}
+T {@model} 20 -12.5 0 0 0.2 0.2 {}
+T {@name} 20 0 0 0 0.2 0.2 {}
+T {@#0:pinnumber} 25 -25 0 0 0.2 0.2 {layer=13}
+T {@#2:pinnumber} 25 12.5 0 0 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 25 23.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/opin.sym b/xschem/devices/opin.sym
new file mode 100644
index 0000000..461973d
--- /dev/null
+++ b/xschem/devices/opin.sym
@@ -0,0 +1,12 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=opin
+format="*.opin @lab"
+template="name=p1 lab=xxx"
+}
+V {}
+S {}
+E {}
+B 5 -0.009765619999999999 -0.009765619999999999 0.009765619999999999 0.009765619999999999 {name=p dir=in}
+P 5 6 -0 -5 0 5 8.125 5 14.375 0 8.125 -5 -0 -5 {fill=true}
+T {@lab} 20 -8.75 0 0 0.33 0.33 {}
diff --git a/xschem/devices/package.sym b/xschem/devices/package.sym
new file mode 100644
index 0000000..d3b2984
--- /dev/null
+++ b/xschem/devices/package.sym
@@ -0,0 +1,47 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=package
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+template="
+ library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+ package aaa is
+ type real_vector is array(natural range <>) of real;
+ constant dx : real := 0.001 ;
+
+ procedure assegna(
+ signal A : inout real;
+ signal A_OLD : in real;
+ A_VAL : in real
+ );
+
+ end aaa; -- end package declaration
+
+
+ package body aaa is
+
+
+ procedure assegna(
+ signal A : inout real;
+ signal A_OLD : in real;
+ A_VAL : in real ) is
+ constant tdelay: time := 0.01 ns;
+ begin
+ if (A /= A_VAL) then
+ A <= A_OLD+dx, A_VAL after tdelay;
+ end if;
+ end assegna;
+
+
+ end aaa; -- end package body
+"}
+V {}
+S {}
+E {}
+L 4 0 -10 355 -10 {}
+T {PACKAGE} 5 -25 0 0 0.3 0.3 {}
+T {@prop_ptr} 25 5 0 0 0.18 0.12 {}
diff --git a/xschem/devices/package_not_shown.sym b/xschem/devices/package_not_shown.sym
new file mode 100644
index 0000000..b32a1b6
--- /dev/null
+++ b/xschem/devices/package_not_shown.sym
@@ -0,0 +1,49 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=package
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+template="
+
+-- THIS IS A TEMPLATE, REPLACE WITH ACTUAL CODE OR REMOVE INSTANCE!!
+ library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+ package aaa is
+ type real_vector is array(natural range <>) of real;
+ constant dx : real := 0.001 ;
+
+ procedure assegna(
+ signal A : inout real;
+ signal A_OLD : in real;
+ A_VAL : in real
+ );
+
+ end aaa; -- end package declaration
+
+
+ package body aaa is
+
+
+ procedure assegna(
+ signal A : inout real;
+ signal A_OLD : in real;
+ A_VAL : in real ) is
+ constant tdelay: time := 0.01 ns;
+ begin
+ if (A /= A_VAL) then
+ A <= A_OLD+dx, A_VAL after tdelay;
+ end if;
+ end assegna;
+
+
+ end aaa; -- end package body
+"}
+V {}
+S {}
+E {}
+L 4 0 -10 355 -10 {}
+T {PACKAGE} 5 -25 0 0 0.3 0.3 {}
+T {HIDDEN} 135 -5 0 0 0.3 0.3 {}
diff --git a/xschem/devices/param.sym b/xschem/devices/param.sym
new file mode 100644
index 0000000..f299d3c
--- /dev/null
+++ b/xschem/devices/param.sym
@@ -0,0 +1,9 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=spice_parameters
+template="name=s1 value=\\"w=10u\\""
+format=".param @value"}
+V {}
+S {}
+E {}
+L 4 0 -10 90 -10 {}
+T {PARAMETER @value} 5 -25 0 0 0.3 0.3 {}
diff --git a/xschem/devices/param_agauss.sym b/xschem/devices/param_agauss.sym
new file mode 100644
index 0000000..5551fb6
--- /dev/null
+++ b/xschem/devices/param_agauss.sym
@@ -0,0 +1,18 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=spice_parameters
+
+template="name=s1
+sigma=1u
+param=W
+value=10u
+"
+
+format=".param @param = agauss(@value , @sigma , 1)"}
+V {}
+S {}
+E {}
+L 4 0 -10 140 -10 {}
+T { PARAMETER
+ name: @param
+ value: @value
+1-sigma: @sigma} 5 -25 0 0 0.3 0.3 {}
diff --git a/xschem/devices/parax_cap.sym b/xschem/devices/parax_cap.sym
new file mode 100644
index 0000000..41809c9
--- /dev/null
+++ b/xschem/devices/parax_cap.sym
@@ -0,0 +1,22 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=parax_cap
+format="@name @pinlist @gnd @value m=@m"
+verilog_ignore=true
+template="name=C1 gnd=0 value=4f m=1"}
+V {}
+S {}
+E {}
+L 4 0 -10 0 0 {}
+L 4 -5 0 5 0 {}
+L 4 -5 5 5 5 {}
+L 4 0 5 0 12.5 {}
+L 4 -2.5 12.5 2.5 12.5 {}
+L 4 -2.5 12.5 0 15 {}
+L 4 0 15 2.5 12.5 {}
+B 5 -2.5 -12.5 2.5 -7.5 {name=p dir=in}
+T {@value} 10 13.75 0 0 0.2 0.15 {}
+T {@name} 10 3.75 0 0 0.2 0.15 {}
+T {@gnd} -5 7.5 0 1 0.2 0.15 {}
+T {m=@m} 10 -6.25 0 0 0.2 0.15 {}
+T {@#0:net_name} 5 -22.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/pmos-sub.sym b/xschem/devices/pmos-sub.sym
new file mode 100644
index 0000000..38a8015
--- /dev/null
+++ b/xschem/devices/pmos-sub.sym
@@ -0,0 +1,32 @@
+v {xschem version=2.9.5_RC8 file_version=1.1}
+G {type=pmos
+format="@name @pinlist @substrate @model w=@w l=@l m=@m"
+template="name=M1 model=pmos substrate=VCC w=5u l=0.18u m=1"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {11}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 -5 -5 -0 {}
+L 4 -7.5 -5 -5 -2.5 {}
+L 4 -10 -5 -7.5 -5 {}
+L 4 -12.5 -2.5 -10 -5 {}
+L 4 -12.5 -2.5 -12.5 2.5 {}
+L 4 -12.5 2.5 -10 5 {}
+L 4 -10 5 -7.5 5 {}
+L 4 -7.5 5 -5 2.5 {}
+L 4 -20 0 -12.5 -0 {}
+L 4 10 0 20 0 {}
+L 4 5 -5 10 0 {}
+L 4 5 5 10 -0 {}
+B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
+T {@w\\/@l\\/@m} 7.5 -17.5 0 0 0.2 0.2 {}
+T {@name} 7.5 6.25 0 0 0.2 0.2 {999}
+T {D} 25 20 0 0 0.15 0.15 {}
+T {@substrate} 22.5 -3.125 0 0 0.1 0.1 {layer=4}
diff --git a/xschem/devices/pmos.sym b/xschem/devices/pmos.sym
new file mode 100644
index 0000000..c173573
--- /dev/null
+++ b/xschem/devices/pmos.sym
@@ -0,0 +1,38 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=pmos
+format="@spiceprefix@name @pinlist @model @extra m=@m"
+verilog_format="@symname #@del @name ( @@d , @@s , @@g );"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=M1
+model=DMP2035U
+device=DMP2035U
+m=1"
+}
+V {}
+S {}
+E {}
+L 4 5 -27.5 5 27.5 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 -5 -15 -5 15 {}
+L 4 -20 0 -12.5 0 {}
+B 5 17.5 27.5 22.5 32.5 {name=d dir=inout pinnumber=3}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in pinnumber=1}
+B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout pinnumber=2}
+A 4 -8.75 0 3.75 270 360 {}
+T {@device} 18.75 -13.75 0 0 0.2 0.2 {}
+T {@name} 18.75 0 0 0 0.2 0.2 {}
+T {D} 7.5 8.75 0 0 0.2 0.2 {}
+T {@#2:pinnumber} 25 -28.75 0 0 0.2 0.2 {layer=13}
+T {@#0:pinnumber} 25 18.75 0 0 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -13.75 6.25 0 1 0.2 0.2 {layer=13}
diff --git a/xschem/devices/pmos3.sym b/xschem/devices/pmos3.sym
new file mode 100644
index 0000000..4bb834c
--- /dev/null
+++ b/xschem/devices/pmos3.sym
@@ -0,0 +1,26 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=pmos
+format="@name @pinlist @model"
+template="name=X1 model=irf5305"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {11}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 -5 -5 -0 {}
+L 4 -20 -0 -12.5 -0 {}
+B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
+A 4 -8.75 0 3.75 270 360 {}
+T {@model} 7.5 -17.5 0 0 0.2 0.2 {}
+T {@name} 7.5 5 0 0 0.2 0.2 {999}
+T {D} 25 20 0 0 0.15 0.15 {}
+T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/pmos4.sym b/xschem/devices/pmos4.sym
new file mode 100644
index 0000000..e8fd1a9
--- /dev/null
+++ b/xschem/devices/pmos4.sym
@@ -0,0 +1,38 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=pmos
+format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
+template="name=M1 model=pmos w=5u l=0.18u del=0 m=1"
+verilog_format="pmos #@del @name ( @@d , @@s , @@g );"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {11}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 -5 -5 -0 {}
+L 4 -7.5 -5 -5 -2.5 {}
+L 4 -10 -5 -7.5 -5 {}
+L 4 -12.5 -2.5 -10 -5 {}
+L 4 -12.5 -2.5 -12.5 2.5 {}
+L 4 -12.5 2.5 -10 5 {}
+L 4 -10 5 -7.5 5 {}
+L 4 -7.5 5 -5 2.5 {}
+L 4 -20 0 -12.5 -0 {}
+L 4 10 0 20 0 {}
+L 4 5 -5 10 0 {}
+L 4 5 5 10 -0 {}
+B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
+B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
+T {@w\\/@l\\/@m} 7.5 -17.5 0 0 0.2 0.2 {}
+T {@spiceprefix@name} 7.5 7.5 0 0 0.2 0.2 {}
+T {D} 25 20 0 0 0.15 0.15 {}
+T {@#2:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#0:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} 25 1.25 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/pmoshv4.sym b/xschem/devices/pmoshv4.sym
new file mode 100644
index 0000000..469a6fd
--- /dev/null
+++ b/xschem/devices/pmoshv4.sym
@@ -0,0 +1,26 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=pmos
+format="@name @pinlist @model w=@w l=@l number=@m"
+template="name=X1 model=tepbsim3 m=1 w=5u l=0.7u"}
+V {}
+S {}
+E {}
+L 4 5 -27.5 5 27.5 {11}
+L 4 5 20 20 20 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 -5 -15 -5 15 {}
+L 4 -20 0 -12.5 -0 {}
+L 4 10 0 20 0 {}
+L 4 5 -5 10 0 {}
+L 4 5 5 10 -0 {}
+L 4 20 20 20 30 {}
+B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
+B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
+A 4 -8.75 -0 3.75 180 360 {}
+T {@w\\/@l\\/@m} 7.5 5 0 0 0.25 0.2 {}
+T {@name} 7.5 -17.5 0 0 0.2 0.2 {999}
+T {HV} -20 -20 0 0 0.2 0.2 {}
+T {D} 11.875 23.125 0 0 0.15 0.15 {}
diff --git a/xschem/devices/pmosnat.sym b/xschem/devices/pmosnat.sym
new file mode 100644
index 0000000..0842daa
--- /dev/null
+++ b/xschem/devices/pmosnat.sym
@@ -0,0 +1,28 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=pmos
+format="@name @pinlist vdd @model number=@m w=@w l=@l"
+template="name=X1 model=npbsim3 m=1 w=5u l=2u"}
+V {}
+S {}
+E {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 -5 -5 -0 {}
+L 4 -7.5 -5 -5 -2.5 {}
+L 4 -10 -5 -7.5 -5 {}
+L 4 -12.5 -2.5 -10 -5 {}
+L 4 -12.5 -2.5 -12.5 2.5 {}
+L 4 -12.5 2.5 -10 5 {}
+L 4 -10 5 -7.5 5 {}
+L 4 -7.5 5 -5 2.5 {}
+L 4 -20 0 -12.5 -0 {}
+L 4 10 -20 10 20 {}
+L 4 5 -27.5 5 27.5 {}
+B 5 17.5 27.5 22.5 32.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 -32.5 22.5 -27.5 {name=s dir=inout}
+T {@w\\/@l\\/@m} 12.5 -17.5 0 0 0.25 0.2 {}
+T {@name} 12.5 5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/pnp.sym b/xschem/devices/pnp.sym
new file mode 100644
index 0000000..d07b8fe
--- /dev/null
+++ b/xschem/devices/pnp.sym
@@ -0,0 +1,37 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=pnp
+format="@spiceprefix@name @pinlist @model area=@area m=@m"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=Q1
+model=Q2N2907
+device=2N2907
+footprint=TO92
+area=1
+m=1"}
+V {}
+S {}
+E {}
+L 4 0 -30 0 30 {}
+L 4 -20 0 0 0 {}
+L 4 10 -20 20 -30 {}
+L 4 0 10 20 30 {}
+B 5 17.5 27.5 22.5 32.5 {name=C dir=inout pinnumber=3}
+B 5 -22.5 -2.5 -17.5 2.5 {name=B dir=in pinnumber=1}
+B 5 17.5 -32.5 22.5 -27.5 {name=E dir=inout pinnumber=2}
+P 4 4 0 -10 15 -15 5 -25 0 -10 {fill=true}
+T {@model} 20 -12.5 0 0 0.2 0.2 {}
+T {@name} 20 0 0 0 0.2 0.2 {}
+T {@#2:pinnumber} 25 -25 0 0 0.2 0.2 {layer=13}
+T {@#0:pinnumber} 25 12.5 0 0 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 6.25 0 1 0.2 0.2 {layer=13}
+T {@#2:net_name} 25 -33.75 0 0 0.15 0.15 {layer=15}
+T {@#0:net_name} 25 23.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -6.25 -12.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/port_attributes.sym b/xschem/devices/port_attributes.sym
new file mode 100644
index 0000000..b2dc921
--- /dev/null
+++ b/xschem/devices/port_attributes.sym
@@ -0,0 +1,14 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=port_attributes
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+template="
+ attribute async_set_reset of RPTL : signal is "true";
+"}
+V {}
+S {}
+E {}
+L 4 -0 -10 355 -10 {}
+T {VHDL PORT ATTRIBUTES} 5 -25 0 0 0.3 0.3 {}
+T {@prop_ptr} 45 5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/res.sym b/xschem/devices/res.sym
new file mode 100644
index 0000000..108b78f
--- /dev/null
+++ b/xschem/devices/res.sym
@@ -0,0 +1,49 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=resistor
+
+function0="1"
+function1="0"
+
+format="@name @pinlist @value m=@m"
+
+verilog_format="tran @name (@@P\\\\, @@M\\\\);"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=R1
+value=1k
+footprint=1206
+device=resistor
+m=1"
+}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1 goto=1}
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2 goto=0}
+T {@name} -15 -13.75 0 1 0.2 0.2 {}
+T {@value} 15 -6.25 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
+T {m=@m} -15 1.25 0 1 0.2 0.2 {}
diff --git a/xschem/devices/res_ac.sym b/xschem/devices/res_ac.sym
new file mode 100644
index 0000000..90fb539
--- /dev/null
+++ b/xschem/devices/res_ac.sym
@@ -0,0 +1,36 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=resistor
+format="@name @pinlist @value ac=@ac m=@m"
+verilog_format="tran @name (@@P\\\\, @@M\\\\);"
+template="name=R1
+value=1k
+ac=1k
+m=1"
+}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2}
+T {@name} 15 -13.75 0 0 0.2 0.2 {}
+T {AC=@ac} -15 3.75 0 1 0.2 0.2 {}
+T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
+T {m=@m} 15 1.25 0 0 0.2 0.2 {}
+T {DC=@value} -15 -11.25 0 1 0.2 0.2 {}
diff --git a/xschem/devices/rgb_led.sym b/xschem/devices/rgb_led.sym
new file mode 100644
index 0000000..d8b02ab
--- /dev/null
+++ b/xschem/devices/rgb_led.sym
@@ -0,0 +1,44 @@
+v {xschem version=2.9.5_RC6 file_version=1.1}
+G {type=diode
+format="@spiceprefix@name @pinlist @model"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+@comptag"
+template="name=X1 model=XXX device=XXX"}
+V {}
+S {}
+E {}
+L 4 5 -30 30 -30 {}
+L 4 -30 -30 -5 -30 {}
+L 4 5 0 30 0 {}
+L 4 -30 0 -5 0 {}
+L 4 5 -10 5 10 {}
+L 4 5 30 30 30 {}
+L 4 -30 30 -5 30 {}
+L 4 -20 -45 -20 45 {}
+L 4 -20 45 20 45 {}
+L 4 20 -45 20 45 {}
+L 4 -20 -45 20 -45 {}
+L 7 5 20 5 40 {}
+L 12 5 -40 5 -20 {}
+B 5 -32.5 -32.5 -27.5 -27.5 {name=b dir=inout pinnumber=1}
+B 5 -32.5 -2.5 -27.5 2.5 {name=g dir=inout pinnumber=2}
+B 5 -32.5 27.5 -27.5 32.5 {name=r dir=inout pinnumber=3}
+B 5 27.5 27.5 32.5 32.5 {name=gr dir=inout pinnumber=4}
+B 5 27.5 -2.5 32.5 2.5 {name=gg dir=inout pinnumber=5}
+B 5 27.5 -32.5 32.5 -27.5 {name=gb dir=inout pinnumber=6}
+P 7 4 -5 23.75 5 30 -5 36.25 -5 23.75 {}
+P 11 4 -5 -6.25 5 0 -5 6.25 -5 -6.25 {}
+P 12 4 -5 -36.25 5 -30 -5 -23.75 -5 -36.25 {}
+T {@name} -17.5 -60 0 0 0.2 0.2 {}
+T {@value} -17.5 -77.5 0 0 0.2 0.2 {}
+T {@#0:pinnumber} -25 -46.25 0 1 0.2 0.2 {layer=13}
+T {B} -15 -30 0 0 0.25 0.25 {}
+T {G} -15 0 0 0 0.25 0.25 {}
+T {R} -15 30 0 0 0.25 0.25 {}
+T {@#1:pinnumber} -25 -16.25 0 1 0.2 0.2 {layer=13}
+T {@#2:pinnumber} -25 13.75 0 1 0.2 0.2 {layer=13}
+T {@#5:pinnumber} 25 -46.25 0 0 0.2 0.2 {layer=13}
+T {@#4:pinnumber} 25 -16.25 0 0 0.2 0.2 {layer=13}
+T {@#3:pinnumber} 25 13.75 0 0 0.2 0.2 {layer=13}
diff --git a/xschem/devices/rnmos4.sym b/xschem/devices/rnmos4.sym
new file mode 100644
index 0000000..8950d96
--- /dev/null
+++ b/xschem/devices/rnmos4.sym
@@ -0,0 +1,33 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=nmos
+format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
+template="name=M1 model=nmos w=5u l=0.18u del=0 m=1"
+verilog_format="rnmos #@del @name ( @@s , @@d , @@g );"}
+V {}
+S {}
+E {}
+L 4 5 -30 5 30 {}
+L 4 5 -20 20 -20 {}
+L 4 20 -30 20 -20 {}
+L 4 5 20 20 20 {}
+L 4 20 20 20 30 {}
+L 4 -5 -15 -5 15 {}
+L 4 -5 0 -5 5 {}
+L 4 -20 0 -12.5 0 {}
+L 4 -20 0 -5 0 {}
+L 4 15 0 20 0 {}
+L 4 10 -5 15 0 {}
+L 4 10 5 15 0 {}
+L 4 10 -20 10 20 {dash=3}
+B 5 17.5 -32.5 22.5 -27.5 {name=d dir=inout}
+B 5 -22.5 -2.5 -17.5 2.5 {name=g dir=in}
+B 5 17.5 27.5 22.5 32.5 {name=s dir=inout}
+B 5 17.5 -2.5 22.5 2.5 {name=b dir=in}
+T {@w\\/@l\\/@m} 12.5 -18.75 0 0 0.2 0.2 {}
+T {@spiceprefix@name} 12.5 7.5 0 0 0.2 0.2 {}
+T {D} 25 -27.5 0 0 0.15 0.15 {}
+T {@#0:net_name} 25 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 25 32.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} -25 -12.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} 25 0.625 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/spice_probe.sym b/xschem/devices/spice_probe.sym
new file mode 100644
index 0000000..bd52712
--- /dev/null
+++ b/xschem/devices/spice_probe.sym
@@ -0,0 +1,25 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=probe
+vhdl_ignore=true
+spice_ignore=false
+verilog_ignore=true
+tedax_ignore=true
+format=".save @attrs v( @@p )"
+template="name=p1 attrs=\\"\\""}
+V {}
+S {}
+E {}
+L 15 3.75 -8.75 10 -16.25 {}
+L 15 0 -0 3.75 -8.75 {}
+L 15 10 -27.5 10 -13.75 {}
+L 15 7.5 -16.25 28.75 -16.25 {}
+L 15 12.5 -20 17.5 -20 {}
+L 15 17.5 -23.75 17.5 -20 {}
+L 15 17.5 -23.75 21.25 -23.75 {}
+L 15 21.25 -23.75 21.25 -20 {}
+L 15 21.25 -20 25 -20 {}
+L 15 25 -23.75 25 -20 {}
+L 15 25 -23.75 27.8125 -23.75 {}
+B 5 -0.46875 -0.46875 0.46875 0.46875 {name=p dir=xxx}
+T {@voltage} 12.5 -37.5 0 0 0.2 0.2 {layer=15}
diff --git a/xschem/devices/spice_probe_vdiff.sym b/xschem/devices/spice_probe_vdiff.sym
new file mode 100644
index 0000000..980afc1
--- /dev/null
+++ b/xschem/devices/spice_probe_vdiff.sym
@@ -0,0 +1,23 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=differential_probe
+format=".save v(@@p\\\\) v(@@m\\\\)"
+template="name=p1"}
+V {}
+S {}
+E {}
+L 15 0 -17.5 0 -12.5 {}
+L 15 -2.5 -15 2.5 -15 {}
+L 15 -2.5 15 2.5 15 {}
+L 15 -5 0 0 0 {}
+L 15 0 -3.75 0 0 {}
+L 15 0 -3.75 3.75 -3.75 {}
+L 15 3.75 -3.75 3.75 0 {}
+L 15 3.75 0 7.5 0 {}
+L 15 7.5 -3.75 7.5 0 {}
+L 15 7.5 -3.75 10.3125 -3.75 {}
+L 15 -7.5 -7.5 -7.5 6.25 {}
+L 15 -10 3.75 11.25 3.75 {}
+B 5 -1.25 -21.25 1.25 -18.75 {name=p dir=in}
+B 5 -1.25 18.75 1.25 21.25 {name=m dir=in}
+T {@voltage} 15 -5 0 0 0.2 0.2 {layer=15}
diff --git a/xschem/devices/sqwsource.sym b/xschem/devices/sqwsource.sym
new file mode 100644
index 0000000..ae8b850
--- /dev/null
+++ b/xschem/devices/sqwsource.sym
@@ -0,0 +1,32 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=vsource
+format="@name @pinlist \\\\
+pulse 0 @vhi \\\\
+'0.495/ @freq ' \\\\
+'0.01/@freq ' \\\\
+'0.01/@freq ' \\\\
+'0.49/@freq ' \\\\
+'1/@freq '"
+template="name=V1 vhi=3 freq=1e6"
+}
+V {}
+S {}
+E {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 -0 15 -0 30 {}
+L 4 0 -30 -0 -15 {}
+L 4 -10 5 -5 5 {}
+L 4 -5 5 -2.5 -10 {}
+L 4 -2.5 -10 2.5 -10 {}
+L 4 2.5 -10 5 5 {}
+L 4 5 5 10 5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {V=@vhi} 20 -6.25 0 0 0.2 0.2 {}
+T {@name} 20 -18.75 0 0 0.2 0.2 {}
+T {@#0:net_name} 10 -30 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
+T {f=@freq Hz} 20 6.25 0 0 0.2 0.2 {}
diff --git a/xschem/devices/switch.sym b/xschem/devices/switch.sym
new file mode 100644
index 0000000..11a5297
--- /dev/null
+++ b/xschem/devices/switch.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=switch
+format="@name @@P @@M vcr pwl(1) @@CP @@CM @TABLE"
+template="name=G1 TABLE=\\"1.0 1G 2.0 10\\""
+}
+V {}
+S {}
+E {}
+L 4 0 10 0 30 {}
+L 4 -10 -10 0 10 {}
+L 4 0 -30 0 -10 {}
+L 4 -40 0 -5 0 {}
+L 4 -5 -25 -5 -20 {}
+L 4 -7.5 -22.5 -2.5 -22.5 {}
+L 4 -10 0 -10 20 {}
+L 4 -40 20 -10 20 {}
+L 4 -32.5 -7.5 -32.5 -2.5 {}
+L 4 -35 -5 -30 -5 {}
+B 5 -42.5 -2.5 -37.5 2.5 {name=CP dir=in }
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout }
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout }
+B 5 -42.5 17.5 -37.5 22.5 {name=CM dir=in }
+T {@name} 5 -13 2 1 0.2 0.2 {}
+T {@TABLE} 5 2 2 1 0.2 0.2 {}
diff --git a/xschem/devices/switch_ngspice.sym b/xschem/devices/switch_ngspice.sym
new file mode 100644
index 0000000..a594b1f
--- /dev/null
+++ b/xschem/devices/switch_ngspice.sym
@@ -0,0 +1,29 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=switch
+format="@name @@P @@M @@CP @@CM @model"
+template="name=S1 model=SWITCH1"
+}
+V {}
+S {}
+E {}
+L 4 0 10 0 30 {}
+L 4 -10 -10 0 10 {}
+L 4 0 -30 0 -10 {}
+L 4 -40 0 -5 0 {}
+L 4 -5 -25 -5 -20 {}
+L 4 -7.5 -22.5 -2.5 -22.5 {}
+L 4 -10 0 -10 20 {}
+L 4 -40 20 -10 20 {}
+L 4 -32.5 -7.5 -32.5 -2.5 {}
+L 4 -35 -5 -30 -5 {}
+B 5 -42.5 -2.5 -37.5 2.5 {name=CP dir=in }
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout }
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout }
+B 5 -42.5 17.5 -37.5 22.5 {name=CM dir=in }
+T {@name} 5 -13 2 1 0.2 0.2 {}
+T {@model} 5 -2 0 0 0.2 0.2 {}
+T {@#1:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#0:net_name} -45 -12.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} -45 22.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/switch_v_xyce.sym b/xschem/devices/switch_v_xyce.sym
new file mode 100644
index 0000000..931da32
--- /dev/null
+++ b/xschem/devices/switch_v_xyce.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.5_RC8 file_version=1.1}
+G {type=switch
+format="@name @@P @@M @@CP @@CM @model @state"
+template="name=S1 model=SWMOD1 state=OFF"
+}
+V {}
+S {}
+E {}
+L 4 0 10 0 30 {}
+L 4 -10 -10 0 10 {}
+L 4 0 -30 0 -10 {}
+L 4 -40 0 -5 0 {}
+L 4 -5 -25 -5 -20 {}
+L 4 -7.5 -22.5 -2.5 -22.5 {}
+L 4 -10 0 -10 20 {}
+L 4 -40 20 -10 20 {}
+L 4 -32.5 -7.5 -32.5 -2.5 {}
+L 4 -35 -5 -30 -5 {}
+B 5 -42.5 -2.5 -37.5 2.5 {name=CP dir=in }
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout }
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout }
+B 5 -42.5 17.5 -37.5 22.5 {name=CM dir=in }
+T {@name} 5 -13 2 1 0.2 0.2 {}
+T {@model} 5 -2 0 0 0.2 0.2 {}
diff --git a/xschem/devices/title-2.sym b/xschem/devices/title-2.sym
new file mode 100644
index 0000000..d8c39b4
--- /dev/null
+++ b/xschem/devices/title-2.sym
@@ -0,0 +1,29 @@
+v {xschem version=2.9.7 file_version=1.2}
+G {}
+K {type=logo
+template="name=l1 author=\\"Stefan Schippers\\" rev=1.0"
+verilog_ignore=true
+vhdl_ignore=true
+spice_ignore=true
+tedax_ignore=true}
+V {}
+S {}
+E {}
+L 4 385 0 3430 0 {}
+L 4 0 0 65 0 {}
+L 4 3430 -2350 3430 0 {}
+L 4 0 -2350 3430 -2350 {}
+L 4 0 -2350 0 0 {}
+L 4 2110 -160 2110 0 {}
+L 4 2110 -160 3430 -160 {}
+L 4 2110 -80 3430 -80 {}
+L 4 2740 -80 2740 0 {}
+L 4 2740 -160 2740 -80 {}
+L 4 2450 -80 2450 0 {}
+P 5 13 165 -30 135 0 165 30 145 30 125 10 105 30 85 30 115 0 85 -30 105 -30 125 -10 145 -30 165 -30 {fill=true}
+T {SCHEM} 165 -25 0 0 1 1 {}
+T {@time_last_modified} 2750 -60 0 0 0.8 0.8 {}
+T {@author} 2120 -140 0 0 0.8 0.8 {}
+T {Page @page of @pages} 2120 -60 0 0 0.8 0.8 {}
+T {@title} 2750 -120 0 0 0.6 0.6 {vcenter=true}
+T {Rev. @rev} 2460 -60 0 0 0.8 0.8 {}
diff --git a/xschem/devices/title.sym b/xschem/devices/title.sym
new file mode 100644
index 0000000..9efcc8d
--- /dev/null
+++ b/xschem/devices/title.sym
@@ -0,0 +1,18 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=logo
+template="name=l1 author=\\"Stefan Schippers\\""
+verilog_ignore=true
+vhdl_ignore=true
+spice_ignore=true
+tedax_ignore=true}
+V {}
+S {}
+E {}
+L 6 225 0 1020 0 {}
+L 6 -160 0 -95 0 {}
+P 5 13 5 -30 -25 0 5 30 -15 30 -35 10 -55 30 -75 30 -45 0 -75 -30 -55 -30 -35 -10 -15 -30 5 -30 {fill=true}
+T {@schname} 235 5 0 0 0.4 0.4 {}
+T {@author} 235 -25 0 0 0.4 0.4 {}
+T {@time_last_modified} 1020 -25 0 1 0.4 0.3 {}
+T {SCHEM} 5 -25 0 0 1 1 {}
diff --git a/xschem/devices/use.sym b/xschem/devices/use.sym
new file mode 100644
index 0000000..d66bd99
--- /dev/null
+++ b/xschem/devices/use.sym
@@ -0,0 +1,18 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=use
+spice_ignore=true
+verilog_ignore=true
+tedax_ignore=true
+template="
+ library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+"}
+V {}
+S {}
+E {}
+L 4 -0 -10 355 -10 {}
+T {VHDL USE} 5 -25 0 0 0.3 0.3 {}
+T {@prop_ptr} 45 5 0 0 0.2 0.2 {}
diff --git a/xschem/devices/var_res.sym b/xschem/devices/var_res.sym
new file mode 100644
index 0000000..a8569c7
--- /dev/null
+++ b/xschem/devices/var_res.sym
@@ -0,0 +1,45 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=resistor
+format="@name @#0 @#1 @value m=@m"
+verilog_format="tran @name (@@P\\\\, @@M\\\\);"
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device"
+template="name=R1
+value=1k
+footprint=1206
+device=variable\\\\ resistor
+m=1"
+}
+V {}
+S {}
+E {}
+L 4 0 20 0 30 {}
+L 4 0 20 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 17.5 {}
+L 4 -7.5 12.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 7.5 {}
+L 4 -7.5 2.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -2.5 {}
+L 4 -7.5 -7.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 7.5 -12.5 {}
+L 4 -7.5 -17.5 0 -20 {}
+L 4 0 -30 0 -20 {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 -20 -5 -10 0 {}
+L 4 -20 -5 -20 5 {}
+L 4 -20 5 -10 -0 {}
+L 4 -30 0 -20 -0 {}
+B 5 -32.5 -2.5 -27.5 2.5 {name=C dir=inout propag=1 pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2}
+B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=3}
+T {@name} 15 -13.75 0 0 0.2 0.2 {}
+T {@value} 15 1.25 0 0 0.2 0.2 {}
+T {@#2:pinnumber} -10 -28.75 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -10 18.75 0 1 0.2 0.2 {layer=13}
+T {@#0:pinnumber} -30 3.75 0 1 0.2 0.2 {layer=13}
+T {@#2:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#0:net_name} -35 -12.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/vccs.sym b/xschem/devices/vccs.sym
new file mode 100644
index 0000000..d867851
--- /dev/null
+++ b/xschem/devices/vccs.sym
@@ -0,0 +1,39 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=vccs
+format="@name @pinlist @value"
+template="name=G1 value=1e-6"}
+V {}
+S {}
+E {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 -20 -0 -0 -20 {}
+L 4 -20 -0 -0 20 {}
+L 4 -0 20 20 0 {}
+L 4 0 -20 20 0 {}
+L 4 -40 -20 -35 -20 {}
+L 4 -30 -20 -25 -20 {}
+L 4 -20 -20 -15 -20 {}
+L 4 -40 20 -35 20 {}
+L 4 -30 20 -25 20 {}
+L 4 -20 20 -15 20 {}
+L 4 0 20 0 30 {}
+L 4 0 -30 0 -20 {}
+L 4 -5 5 0 10 {}
+L 4 -5 5 5 5 {}
+L 4 0 10 5 5 {}
+L 4 0 -5 0 5 {}
+L 4 -37.5 -12.5 -32.5 -12.5 {}
+L 4 -35 -15 -35 -10 {}
+L 4 -37.5 12.5 -32.5 12.5 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+B 5 -42.5 -22.5 -37.5 -17.5 {name=cp dir=in}
+B 5 -42.5 17.5 -37.5 22.5 {name=cm dir=in}
+T {@value} 20 5 0 0 0.2 0.2 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} -45 -32.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} -45 22.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/vcr.sym b/xschem/devices/vcr.sym
new file mode 100644
index 0000000..ce0c921
--- /dev/null
+++ b/xschem/devices/vcr.sym
@@ -0,0 +1,37 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @@p @@m @function @@cp @@cm @TABLE"
+template="name=G1 function=\\"vcr pwl(1)\\" TABLE=\\"1 0 2 3\\""
+}
+V {}
+S {}
+E {}
+L 4 -5 15 5 15 {}
+L 4 15 -5 15 5 {}
+L 4 -5 -15 5 -15 {}
+L 4 -15 -5 -15 5 {}
+L 4 5 -15 11.25 -11.25 {}
+L 4 11.25 -11.25 15 -5 {}
+L 4 11.25 11.25 15 5 {}
+L 4 5 15 11.25 11.25 {}
+L 4 -11.25 11.25 -5 15 {}
+L 4 -15 5 -11.25 11.25 {}
+L 4 -15 -5 -11.25 -11.25 {}
+L 4 -11.25 -11.25 -5 -15 {}
+L 4 0 -30 0 -15 {}
+L 4 0 15 0 30 {}
+L 4 0 -15 0 15 {}
+L 4 -20 -20 -10 -20 {}
+L 4 -15 -25 -15 -15 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+B 5 -42.5 -22.5 -37.5 -17.5 {name=cp dir=in}
+B 5 -42.5 17.5 -37.5 22.5 {name=cm dir=in}
+T {pwl(1)=@TABLE} 20 0 0 0 0.2 0.2 {}
+T {@function} 20 -12.5 0 0 0.2 0.2 {}
+T {@name} 20 -25 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} -45 -32.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} -45 22.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/vcvs.sym b/xschem/devices/vcvs.sym
new file mode 100644
index 0000000..97cb2da
--- /dev/null
+++ b/xschem/devices/vcvs.sym
@@ -0,0 +1,31 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=vcvs
+format="@name @pinlist @value"
+template="name=E1 value=3"}
+V {}
+S {}
+E {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 -0 -30 -0 30 {}
+L 4 -20 -0 -0 -20 {}
+L 4 -20 -0 -0 20 {}
+L 4 -0 20 20 0 {}
+L 4 0 -20 20 0 {}
+L 4 -40 -20 -35 -20 {}
+L 4 -30 -20 -25 -20 {}
+L 4 -20 -20 -15 -20 {}
+L 4 -40 20 -35 20 {}
+L 4 -30 20 -25 20 {}
+L 4 -20 20 -15 20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+B 5 -42.5 -22.5 -37.5 -17.5 {name=cp dir=in}
+B 5 -42.5 17.5 -37.5 22.5 {name=cm dir=in}
+T {@value} 20 5 0 0 0.2 0.2 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} -45 -32.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} -45 22.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/vdd.sym b/xschem/devices/vdd.sym
new file mode 100644
index 0000000..4a4f79b
--- /dev/null
+++ b/xschem/devices/vdd.sym
@@ -0,0 +1,14 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=label
+function0="H"
+global=true
+format="*.alias @lab"
+template="name=l1 lab=VDD"}
+V {}
+S {}
+E {}
+L 4 0 -20 0 0 {}
+L 4 -10 -20 10 -20 {}
+B 5 -2.5 -2.5 2.5 2.5 {name=p dir=inout verilog_type=wire goto=0}
+T {@lab} -12.5 -35 0 0 0.2 0.2 {}
diff --git a/xschem/devices/verilog_delay.sch b/xschem/devices/verilog_delay.sch
new file mode 100644
index 0000000..6e96b0b
--- /dev/null
+++ b/xschem/devices/verilog_delay.sch
@@ -0,0 +1,12 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {}
+V {// This is a transport (non inertial) delay
+reg x;
+always @(inp) x <= #del inp;
+assign outp = x;
+
+}
+S {}
+E {}
+C {ipin.sym} 60 -50 0 0 {name=p1 lab=inp}
+C {opin.sym} 160 -50 0 0 {name=p2 lab=outp verilog_type=wire}
diff --git a/xschem/devices/verilog_delay.sym b/xschem/devices/verilog_delay.sym
new file mode 100644
index 0000000..a8adb6a
--- /dev/null
+++ b/xschem/devices/verilog_delay.sym
@@ -0,0 +1,21 @@
+v {xschem version=2.9.5_RC5 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"
+template="name=d1 del=200"}
+V {}
+S {}
+E {}
+L 4 -40 0 -30 0 {}
+L 4 -30 -5 -30 5 {}
+L 4 -30 5 30 5 {}
+L 4 30 -5 30 5 {}
+L 4 -30 -5 30 -5 {}
+L 4 30 -0 40 -0 {}
+L 6 -0 -2.5 20 -0 {}
+L 6 -0 -2.5 0 2.5 {}
+L 6 0 2.5 20 -0 {}
+L 6 -25 0 -0 -0 {}
+B 5 -42.5 -2.5 -37.5 2.5 {name=inp dir=in}
+B 5 37.5 -2.5 42.5 2.5 {name=outp dir=out verilog_type=wire}
+T {del=@del} -37.5 6.25 0 0 0.15 0.12 {}
+T {@name} -20 -12.5 0 0 0.12 0.12 {}
diff --git a/xschem/devices/verilog_preprocessor.sym b/xschem/devices/verilog_preprocessor.sym
new file mode 100644
index 0000000..41bc27d
--- /dev/null
+++ b/xschem/devices/verilog_preprocessor.sym
@@ -0,0 +1,16 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=verilog_preprocessor
+vhdl_ignore=true
+spice_ignore=true
+tedax_ignore=true
+template="name=s1 string=\\"`include \\\\\\"file\\\\\\"\\""
+verilog_format="@string"
+}
+V {}
+S {}
+E {}
+L 4 0 -10 70 -10 {}
+L 4 0 -10 0 10 {}
+T {PREPROCESSOR DIRECTIVE} 5 -25 0 0 0.3 0.3 {}
+T {@string} 15 -5 0 0 0.3 0.3 {font=monospace}
diff --git a/xschem/devices/verilog_timescale.sym b/xschem/devices/verilog_timescale.sym
new file mode 100644
index 0000000..82c8e48
--- /dev/null
+++ b/xschem/devices/verilog_timescale.sym
@@ -0,0 +1,15 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=timescale
+spice_ignore=true
+vhdl_ignore=true
+tedax_ignore=true
+template="name=s1 timestep=\\"100ps\\" precision=\\"100ps\\" "
+verilog_format="`timescale @timestep / @precision"}
+V {}
+S {}
+E {}
+L 4 0 -10 70 -10 {}
+L 4 0 -10 0 10 {}
+T {TIMESCALE} 5 -25 0 0 0.3 0.3 {}
+T {`timescale @timestep\\/@precision} 15 -5 0 0 0.3 0.3 {}
diff --git a/xschem/devices/vsource.sym b/xschem/devices/vsource.sym
new file mode 100644
index 0000000..e8309da
--- /dev/null
+++ b/xschem/devices/vsource.sym
@@ -0,0 +1,18 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=vsource
+format="@name @pinlist @value"
+template="name=V1 value=3"}
+V {}
+S {}
+E {}
+L 4 2.5 -22.5 7.5 -22.5 {}
+L 4 5 -25 5 -20 {}
+L 4 -0 -30 -0 30 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {@name} 20 -18.75 0 0 0.2 0.2 {}
+T {@value} 20 -6.25 0 0 0.2 0.2 {}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/vsource_arith.sym b/xschem/devices/vsource_arith.sym
new file mode 100644
index 0000000..4aab3b0
--- /dev/null
+++ b/xschem/devices/vsource_arith.sym
@@ -0,0 +1,19 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @pinlist VOL=' @VOL '"
+template="name=E1 VOL=cos(V(IN))"
+}
+V {}
+S {}
+E {}
+L 4 -20 -20 -10 -20 {}
+L 4 -15 -25 -15 -15 {}
+L 4 0 -30 0 30 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+A 4 0 0 15 270 360 {}
+T {@VOL} 20 0 0 0 0.2 0.2 {}
+T {@name} 20 -17.5 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
diff --git a/xschem/devices/vsource_pwl.sym b/xschem/devices/vsource_pwl.sym
new file mode 100644
index 0000000..22fe237
--- /dev/null
+++ b/xschem/devices/vsource_pwl.sym
@@ -0,0 +1,23 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=isource
+format="@name @@p @@m pwl(1) @@cp @@cm @TABLE"
+template="name=E1 TABLE=\\"1 0 2 3\\""
+}
+V {}
+S {}
+E {}
+L 4 -20 -20 -10 -20 {}
+L 4 -15 -25 -15 -15 {}
+L 4 -0 -30 -0 30 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
+B 5 -42.5 -22.5 -37.5 -17.5 {name=cp dir=in}
+B 5 -42.5 17.5 -37.5 22.5 {name=cm dir=in}
+A 4 0 0 15 270 360 {}
+T {pwl(1)=@TABLE} 20 0 0 0 0.2 0.2 {}
+T {@name} 20 -15 0 0 0.2 0.2 {}
+T {@#0:net_name} 5 -42.5 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 5 32.5 0 0 0.15 0.15 {layer=15}
+T {@#2:net_name} -45 -32.5 0 1 0.15 0.15 {layer=15}
+T {@#3:net_name} -45 22.5 0 1 0.15 0.15 {layer=15}
diff --git a/xschem/devices/zener.sym b/xschem/devices/zener.sym
new file mode 100644
index 0000000..5668ed6
--- /dev/null
+++ b/xschem/devices/zener.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=diode
+format="@spiceprefix@name @pinlist @model"
+
+tedax_format="footprint @name @footprint
+value @name @value
+device @name @device
+spicedev @name @spicedev
+spiceval @name @spiceval
+comptag @name @comptag"
+
+template="name=X1 model=XXX device=XXX"}
+V {}
+S {}
+E {}
+L 4 0 5 0 30 {}
+L 4 0 -30 0 -5 {}
+L 4 -20 5 20 5 {}
+L 4 20 -5 20 5 {}
+L 4 -20 5 -20 15 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout pinnumber=1}
+B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout pinnumber=2}
+P 4 4 -0 5 -10 -5 10 -5 -0 5 {fill=true}
+T {@#0:pinnumber} -5 -26.25 0 1 0.2 0.2 {layer=13}
+T {@#1:pinnumber} -5 17.5 0 1 0.2 0.2 {layer=13}
+T {@name} 15 -18.75 0 0 0.2 0.2 {}
+T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
+T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
+T {@model} 15 6.25 0 0 0.2 0.2 {}
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/unused/analog_wrapper_tb.sch
similarity index 100%
rename from xschem/analog_wrapper_tb.sch
rename to xschem/unused/analog_wrapper_tb.sch
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/unused/analog_wrapper_tb.spice
similarity index 100%
rename from xschem/analog_wrapper_tb.spice
rename to xschem/unused/analog_wrapper_tb.spice
diff --git a/xschem/current_test.spice b/xschem/unused/current_test.spice
similarity index 100%
rename from xschem/current_test.spice
rename to xschem/unused/current_test.spice
diff --git a/xschem/example_por.sch b/xschem/unused/example_por.sch
similarity index 100%
rename from xschem/example_por.sch
rename to xschem/unused/example_por.sch
diff --git a/xschem/example_por.sym b/xschem/unused/example_por.sym
similarity index 100%
rename from xschem/example_por.sym
rename to xschem/unused/example_por.sym
diff --git a/xschem/example_por_tb.sch b/xschem/unused/example_por_tb.sch
similarity index 100%
rename from xschem/example_por_tb.sch
rename to xschem/unused/example_por_tb.sch
diff --git a/xschem/example_por_tb.spice b/xschem/unused/example_por_tb.spice
similarity index 100%
rename from xschem/example_por_tb.spice
rename to xschem/unused/example_por_tb.spice
diff --git a/xschem/example_por_tb.spice.orig b/xschem/unused/example_por_tb.spice.orig
similarity index 100%
rename from xschem/example_por_tb.spice.orig
rename to xschem/unused/example_por_tb.spice.orig
diff --git a/xschem/test.data b/xschem/unused/test.data
similarity index 100%
rename from xschem/test.data
rename to xschem/unused/test.data
diff --git a/xschem/threshold_test_tb.spice b/xschem/unused/threshold_test_tb.spice
similarity index 100%
rename from xschem/threshold_test_tb.spice
rename to xschem/unused/threshold_test_tb.spice
diff --git a/xschem/unused/user_analog_project_wrapper_-_copy_seems_to_work_with_example.spice b/xschem/unused/user_analog_project_wrapper_-_copy_seems_to_work_with_example.spice
new file mode 100644
index 0000000..3177e6b
--- /dev/null
+++ b/xschem/unused/user_analog_project_wrapper_-_copy_seems_to_work_with_example.spice
@@ -0,0 +1,158 @@
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/user_analog_project_wrapper.sch
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] io_in[26]
++ io_in[25] io_in[24] io_in[23] io_in[22] io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15]
++ io_in[14] io_in[13] io_in[12] io_in[11] io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4]
++ io_in[3] io_in[2] io_in[1] io_in[0] io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22]
++ io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14]
++ io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6]
++ io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] user_clock2 io_out[26] io_out[25]
++ io_out[24] io_out[23] io_out[22] io_out[21] io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15]
++ io_out[14] io_out[13] io_out[12] io_out[11] io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5]
++ io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22]
++ io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12]
++ io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2]
++ io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] gpio_analog[15] gpio_analog[14] gpio_analog[13]
++ gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] gpio_analog[8] gpio_analog[7] gpio_analog[6]
++ gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] gpio_analog[1] gpio_analog[0] gpio_noesd[17]
++ gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] gpio_noesd[12] gpio_noesd[11] gpio_noesd[10]
++ gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] gpio_noesd[4] gpio_noesd[3] gpio_noesd[2]
++ gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[5]
++ io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] io_clamp_high[2] io_clamp_high[1]
++ io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_irq[2] user_irq[1] user_irq[0] la_oenb[127]
++ la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] la_oenb[119]
++ la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] la_oenb[111]
++ la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] la_oenb[103]
++ la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] la_oenb[94]
++ la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] la_oenb[85]
++ la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] la_oenb[76]
++ la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] la_oenb[67]
++ la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] la_oenb[58]
++ la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] la_oenb[49]
++ la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] la_oenb[40]
++ la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] la_oenb[31]
++ la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] la_oenb[22]
++ la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] la_oenb[13]
++ la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] la_oenb[4]
++ la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0]
+*.PININFO vdda1:B vdda2:B vssa1:B vssa2:B vccd1:B vccd2:B vssd1:B vssd2:B wb_clk_i:I wb_rst_i:I
+*+ wbs_stb_i:I wbs_cyc_i:I wbs_we_i:I wbs_sel_i[3:0]:I wbs_dat_i[31:0]:I wbs_adr_i[31:0]:I wbs_ack_o:O
+*+ wbs_dat_o[31:0]:O la_data_in[127:0]:I la_data_out[127:0]:O io_in[26:0]:I io_in_3v3[26:0]:I user_clock2:I
+*+ io_out[26:0]:O io_oeb[26:0]:O gpio_analog[17:0]:B gpio_noesd[17:0]:B io_analog[10:0]:B io_clamp_high[2:0]:B
+*+ io_clamp_low[2:0]:B user_irq[2:0]:O la_oenb[127:0]:I
+x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
+x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
+R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R8 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=0.56 L=0.49 m=1
+R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=0.56 L=0.31 m=1
+R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=0.56 L=0.58 m=1
+R12 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=0.56 L=0.6 m=1
+.ends
+
+* expanding symbol: example_por.sym # of pins=6
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/example_por.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.PININFO vdd3v3:B vss:B porb_h:O porb_l:O por_l:O vdd1v8:B
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 VM=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.end
diff --git a/xschem/unused/user_analog_project_wrapper_-_example_pors.sch b/xschem/unused/user_analog_project_wrapper_-_example_pors.sch
new file mode 100644
index 0000000..e3cbcec
--- /dev/null
+++ b/xschem/unused/user_analog_project_wrapper_-_example_pors.sch
@@ -0,0 +1,180 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 3830 -460 3830 -390 { lab=vdda1}
+N 3730 -460 3830 -460 { lab=vdda1}
+N 3860 -230 3860 -180 { lab=vssa1}
+N 3770 -180 3860 -180 { lab=vssa1}
+N 3890 -460 3890 -390 { lab=vccd1}
+N 3890 -460 3960 -460 { lab=vccd1}
+N 3890 -130 3890 -60 { lab=vccd1}
+N 3890 -130 3950 -130 { lab=vccd1}
+N 3830 -130 3830 -60 { lab=io_analog[4]}
+N 3790 -130 3830 -130 { lab=io_analog[4]}
+N 3860 100 3860 150 { lab=vssa1}
+N 3800 150 3860 150 { lab=vssa1}
+N 4010 -10 4110 -10 { lab=gpio_analog[7]}
+N 4010 20 4110 20 { lab=io_out[15]}
+N 4010 50 4110 50 { lab=io_out[16]}
+N 4010 -340 4130 -340 { lab=gpio_analog[3]}
+N 4010 -310 4130 -310 { lab=io_out[11]}
+N 4010 -280 4130 -280 { lab=io_out[12]}
+N 3670 300 3670 340 { lab=io_clamp_low[2]}
+N 3670 400 3670 420 { lab=vssa1}
+N 3670 440 3670 460 { lab=io_clamp_high[2]}
+N 3670 520 3670 530 { lab=vssa1}
+N 3670 570 3670 590 { lab=io_clamp_low[1]}
+N 3670 650 3670 670 { lab=vssa1}
+N 4160 300 4160 330 { lab=io_clamp_high[1]}
+N 4160 390 4160 410 { lab=vssa1}
+N 4160 440 4160 460 { lab=io_clamp_low[0]}
+N 4160 520 4160 530 { lab=vssa1}
+N 4160 550 4160 560 { lab=io_clamp_high[0]}
+N 4160 620 4160 640 { lab=io_analog[4]}
+N 3630 300 3670 300 { lab=io_clamp_low[2]}
+N 3630 420 3670 420 { lab=vssa1}
+N 3630 440 3670 440 { lab=io_clamp_high[2]}
+N 3630 530 3670 530 { lab=vssa1}
+N 3630 570 3670 570 { lab=io_clamp_low[1]}
+N 3630 670 3670 670 { lab=vssa1}
+N 4130 300 4160 300 { lab=io_clamp_high[1]}
+N 4130 410 4160 410 { lab=vssa1}
+N 4130 440 4160 440 { lab=io_clamp_low[0]}
+N 4130 530 4160 530 { lab=vssa1}
+N 4130 550 4160 550 { lab=io_clamp_high[0]}
+N 4130 640 4160 640 { lab=io_analog[4]}
+N 3670 710 3670 750 { lab=io_oeb[12]}
+N 3670 810 3670 830 { lab=vssd1}
+N 3670 850 3670 870 { lab=io_oeb[16]}
+N 3670 930 3670 940 { lab=vssd1}
+N 4160 710 4160 740 { lab=io_oeb[11]}
+N 4160 800 4160 820 { lab=vssd1}
+N 4160 850 4160 870 { lab=#net1}
+N 4160 930 4160 940 { lab=vssd1}
+N 3630 710 3670 710 { lab=io_oeb[12]}
+N 3630 830 3670 830 { lab=vssd1}
+N 3630 850 3670 850 { lab=io_oeb[16]}
+N 3630 940 3670 940 { lab=vssd1}
+N 4130 710 4160 710 { lab=io_oeb[11]}
+N 4130 820 4160 820 { lab=vssd1}
+N 4130 850 4160 850 { lab=#net1}
+N 4130 940 4160 940 { lab=vssd1}
+C {example_por.sym} 3860 -310 0 0 {name=x1}
+C {example_por.sym} 3860 20 0 0 {name=x2}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
+C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
+C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
+C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
+C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
+C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
+C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
+C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 370 0 0 {name=R1
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 490 0 0 {name=R2
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 620 0 0 {name=R4
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 360 0 0 {name=R5
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 490 0 0 {name=R6
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 590 0 0 {name=R7
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 3630 300 0 0 {name=l13 sig_type=std_logic lab=io_clamp_low[2]}
+C {devices/lab_pin.sym} 3630 440 0 0 {name=l14 sig_type=std_logic lab=io_clamp_high[2]}
+C {devices/lab_pin.sym} 3630 570 0 0 {name=l15 sig_type=std_logic lab=io_clamp_low[1]}
+C {devices/lab_pin.sym} 4130 300 0 0 {name=l16 sig_type=std_logic lab=io_clamp_high[1]}
+C {devices/lab_pin.sym} 4130 440 0 0 {name=l17 sig_type=std_logic lab=io_clamp_low[0]}
+C {devices/lab_pin.sym} 3630 420 0 0 {name=l18 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3630 530 0 0 {name=l19 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 410 0 0 {name=l20 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 530 0 0 {name=l21 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3630 670 0 0 {name=l22 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 550 0 0 {name=l23 sig_type=std_logic lab=io_clamp_high[0]}
+C {devices/lab_pin.sym} 4130 640 0 0 {name=l24 sig_type=std_logic lab=io_analog[4]}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 780 0 0 {name=R8
+W=0.56
+L=0.49
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 900 0 0 {name=R9
+W=0.56
+L=0.31
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 770 0 0 {name=R11
+W=0.56
+L=0.58
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 900 0 0 {name=R12
+W=0.56
+L=0.6
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 4130 850 0 0 {name=l25 sig_type=std_logic lab=io_oeb[15]}
+C {devices/lab_pin.sym} 3630 850 0 0 {name=l26 sig_type=std_logic lab=io_oeb[16]}
+C {devices/lab_pin.sym} 4130 710 0 0 {name=l27 sig_type=std_logic lab=io_oeb[11]}
+C {devices/lab_pin.sym} 3630 710 0 0 {name=l28 sig_type=std_logic lab=io_oeb[12]}
+C {devices/lab_pin.sym} 3630 830 0 0 {name=l29 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 3630 940 0 0 {name=l30 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 4130 820 0 0 {name=l31 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 4130 940 0 0 {name=l32 sig_type=std_logic lab=vssd1}
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/unused/user_analog_project_wrapper_-_example_pors.sym
similarity index 100%
rename from xschem/user_analog_project_wrapper.sym
rename to xschem/unused/user_analog_project_wrapper_-_example_pors.sym
diff --git a/xschem/unused/user_analog_project_wrapper_vco_-_seccopy_18-3-2022_10y11.sch b/xschem/unused/user_analog_project_wrapper_vco_-_seccopy_18-3-2022_10y11.sch
new file mode 100644
index 0000000..812eb89
--- /dev/null
+++ b/xschem/unused/user_analog_project_wrapper_vco_-_seccopy_18-3-2022_10y11.sch
@@ -0,0 +1,101 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 3720 330 3720 370 { lab=vccd1}
+N 3720 430 3720 450 { lab=io_oeb[17]}
+N 3720 470 3720 490 { lab=vccd1}
+N 3720 550 3720 560 { lab=io_oeb[18]}
+N 4210 330 4210 360 { lab=vccd1}
+N 4210 420 4210 440 { lab=io_oeb[19]}
+N 4210 470 4210 490 { lab=vccd1}
+N 4210 550 4210 560 { lab=io_oeb[20]}
+N 3680 330 3720 330 { lab=vccd1}
+N 3680 450 3720 450 { lab=io_oeb[17]}
+N 3680 470 3720 470 { lab=vccd1}
+N 3680 560 3720 560 { lab=io_oeb[18]}
+N 4180 330 4210 330 { lab=vccd1}
+N 4180 440 4210 440 { lab=io_oeb[19]}
+N 4180 470 4210 470 { lab=vccd1}
+N 4180 560 4210 560 { lab=io_oeb[20]}
+N 4040 -210 4100 -210 { lab=vccd1}
+N 4040 -190 4100 -190 { lab=vssa1}
+N 4040 -170 4100 -170 { lab=gpio_analog[7]}
+N 4040 -150 4100 -150 { lab=gpio_analog[8]}
+N 3680 -210 3740 -210 { lab=gpio_analog[9]}
+N 3680 -190 3740 -190 { lab=io_in[17]}
+N 3680 -170 3740 -170 { lab=io_in[18]}
+N 3680 -150 3740 -150 { lab=io_in[19]}
+N 3680 -130 3740 -130 { lab=io_in[20]}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {sky130_fd_pr/res_generic_m1.sym} 3720 400 0 0 {name=R8
+W=0.56
+L=0.28
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3720 520 0 0 {name=R9
+W=0.56
+L=0.28
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4210 390 0 0 {name=R11
+W=0.56
+L=0.28
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4210 520 0 0 {name=R12
+W=0.56
+L=0.28
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 4180 560 0 0 {name=l25 sig_type=std_logic lab=io_oeb[20]}
+C {devices/lab_pin.sym} 3680 560 0 0 {name=l26 sig_type=std_logic lab=io_oeb[18]}
+C {devices/lab_pin.sym} 4180 440 0 0 {name=l27 sig_type=std_logic lab=io_oeb[19]}
+C {devices/lab_pin.sym} 3680 450 0 0 {name=l28 sig_type=std_logic lab=io_oeb[17]}
+C {devices/lab_pin.sym} 3680 330 0 0 {name=l29 sig_type=std_logic lab=vccd1}
+C {/home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_with_fdivs.sym} 3890 -170 0 0 {name=x1}
+C {devices/lab_pin.sym} 4100 -210 0 1 {name=l33 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4100 -190 0 1 {name=l7 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4100 -150 0 1 {name=l9 sig_type=std_logic lab=gpio_analog[8]}
+C {devices/lab_pin.sym} 3680 -210 0 0 {name=l34 sig_type=std_logic lab=gpio_analog[9]}
+C {devices/lab_pin.sym} 4100 -170 0 1 {name=l8 sig_type=std_logic lab=gpio_analog[7]}
+C {devices/lab_pin.sym} 3680 -190 0 0 {name=l35 sig_type=std_logic lab=io_in[17]}
+C {devices/lab_pin.sym} 3680 -170 0 0 {name=l36 sig_type=std_logic lab=io_in[18]}
+C {devices/lab_pin.sym} 3680 -150 0 0 {name=l37 sig_type=std_logic lab=io_in[19]}
+C {devices/lab_pin.sym} 3680 -130 0 0 {name=l38 sig_type=std_logic lab=io_in[20]}
+C {devices/lab_pin.sym} 3680 470 0 0 {name=l1 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4180 470 0 0 {name=l2 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4180 330 0 0 {name=l3 sig_type=std_logic lab=vccd1}
diff --git a/xschem/unused/user_analog_project_wrapper_vco_for_lvs.sch b/xschem/unused/user_analog_project_wrapper_vco_for_lvs.sch
new file mode 100644
index 0000000..ab72653
--- /dev/null
+++ b/xschem/unused/user_analog_project_wrapper_vco_for_lvs.sch
@@ -0,0 +1,93 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 3670 300 3670 340 { lab=io_clamp_low[2]}
+N 3670 400 3670 420 { lab=vssa1}
+N 3670 440 3670 460 { lab=io_clamp_high[2]}
+N 3670 520 3670 530 { lab=vssa1}
+N 3670 570 3670 590 { lab=io_clamp_low[1]}
+N 3670 650 3670 670 { lab=vssa1}
+N 4160 300 4160 330 { lab=io_clamp_high[1]}
+N 4160 390 4160 410 { lab=vssa1}
+N 4160 440 4160 460 { lab=io_clamp_low[0]}
+N 4160 520 4160 530 { lab=vssa1}
+N 4160 550 4160 560 { lab=io_clamp_high[0]}
+N 4160 620 4160 640 { lab=vssa1}
+N 3630 300 3670 300 { lab=io_clamp_low[2]}
+N 3630 420 3670 420 { lab=vssa1}
+N 3630 440 3670 440 { lab=io_clamp_high[2]}
+N 3630 530 3670 530 { lab=vssa1}
+N 3630 570 3670 570 { lab=io_clamp_low[1]}
+N 3630 670 3670 670 { lab=vssa1}
+N 4130 300 4160 300 { lab=io_clamp_high[1]}
+N 4130 410 4160 410 { lab=vssa1}
+N 4130 440 4160 440 { lab=io_clamp_low[0]}
+N 4130 530 4160 530 { lab=vssa1}
+N 4130 550 4160 550 { lab=io_clamp_high[0]}
+N 4130 640 4160 640 { lab=vssa1}
+N 3990 170 4050 170 { lab=vccd1}
+N 3990 190 4050 190 { lab=vssa1}
+N 3990 210 4050 210 { lab=io_analog[0]}
+N 3990 230 4050 230 { lab=io_analog[1]}
+N 3630 170 3690 170 { lab=io_analog[2]}
+N 3630 190 3690 190 { lab=io_in[0]}
+N 3630 210 3690 210 { lab=io_in[1]}
+N 3630 230 3690 230 { lab=io_in[2]}
+N 3630 250 3690 250 { lab=io_in[3]}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {devices/lab_pin.sym} 3630 300 0 0 {name=l13 sig_type=std_logic lab=io_clamp_low[2]}
+C {devices/lab_pin.sym} 3630 440 0 0 {name=l14 sig_type=std_logic lab=io_clamp_high[2]}
+C {devices/lab_pin.sym} 3630 570 0 0 {name=l15 sig_type=std_logic lab=io_clamp_low[1]}
+C {devices/lab_pin.sym} 4130 300 0 0 {name=l16 sig_type=std_logic lab=io_clamp_high[1]}
+C {devices/lab_pin.sym} 4130 440 0 0 {name=l17 sig_type=std_logic lab=io_clamp_low[0]}
+C {devices/lab_pin.sym} 3630 420 0 0 {name=l18 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3630 530 0 0 {name=l19 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 410 0 0 {name=l20 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 530 0 0 {name=l21 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3630 670 0 0 {name=l22 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 550 0 0 {name=l23 sig_type=std_logic lab=io_clamp_high[0]}
+C {/home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_with_fdivs.sym} 3840 210 0 0 {name=x1}
+C {devices/lab_pin.sym} 4050 170 0 1 {name=l33 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4050 190 0 1 {name=l7 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4050 230 0 1 {name=l9 sig_type=std_logic lab=io_analog[1]}
+C {devices/lab_pin.sym} 3630 170 0 0 {name=l34 sig_type=std_logic lab=io_analog[2]}
+C {devices/lab_pin.sym} 4050 210 0 1 {name=l8 sig_type=std_logic lab=io_analog[0]}
+C {devices/lab_pin.sym} 3630 190 0 0 {name=l35 sig_type=std_logic lab=io_in[0]}
+C {devices/lab_pin.sym} 3630 210 0 0 {name=l36 sig_type=std_logic lab=io_in[1]}
+C {devices/lab_pin.sym} 3630 230 0 0 {name=l37 sig_type=std_logic lab=io_in[2]}
+C {devices/lab_pin.sym} 3630 250 0 0 {name=l38 sig_type=std_logic lab=io_in[3]}
+C {devices/lab_pin.sym} 4130 640 0 0 {name=l4 sig_type=std_logic lab=vssa1}
diff --git a/xschem/unused/user_analog_project_wrapper_vco_for_lvs.spice b/xschem/unused/user_analog_project_wrapper_vco_for_lvs.spice
new file mode 100644
index 0000000..72aedd8
--- /dev/null
+++ b/xschem/unused/user_analog_project_wrapper_vco_for_lvs.spice
@@ -0,0 +1,419 @@
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/user_analog_project_wrapper_vco_for_lvs.sch
+.subckt user_analog_project_wrapper_vco_for_lvs vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2
++ wb_clk_i wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0]
++ wbs_dat_i[31] wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24]
++ wbs_dat_i[23] wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16]
++ wbs_dat_i[15] wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8]
++ wbs_dat_i[7] wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0]
++ wbs_adr_i[31] wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24]
++ wbs_adr_i[23] wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16]
++ wbs_adr_i[15] wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8]
++ wbs_adr_i[7] wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0]
++ wbs_ack_o wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25]
++ wbs_dat_o[24] wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17]
++ wbs_dat_o[16] wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9]
++ wbs_dat_o[8] wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1]
++ wbs_dat_o[0] la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122]
++ la_data_in[121] la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115]
++ la_data_in[114] la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108]
++ la_data_in[107] la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101]
++ la_data_in[100] la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94]
++ la_data_in[93] la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87]
++ la_data_in[86] la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80]
++ la_data_in[79] la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73]
++ la_data_in[72] la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66]
++ la_data_in[65] la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59]
++ la_data_in[58] la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52]
++ la_data_in[51] la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45]
++ la_data_in[44] la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38]
++ la_data_in[37] la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31]
++ la_data_in[30] la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24]
++ la_data_in[23] la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17]
++ la_data_in[16] la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10]
++ la_data_in[9] la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2]
++ la_data_in[1] la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] io_in[26]
++ io_in[25] io_in[24] io_in[23] io_in[22] io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15]
++ io_in[14] io_in[13] io_in[12] io_in[11] io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4]
++ io_in[3] io_in[2] io_in[1] io_in[0] io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22]
++ io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14]
++ io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6]
++ io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] user_clock2 io_out[26] io_out[25]
++ io_out[24] io_out[23] io_out[22] io_out[21] io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15]
++ io_out[14] io_out[13] io_out[12] io_out[11] io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5]
++ io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22]
++ io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12]
++ io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2]
++ io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] gpio_analog[15] gpio_analog[14] gpio_analog[13]
++ gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] gpio_analog[8] gpio_analog[7] gpio_analog[6]
++ gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] gpio_analog[1] gpio_analog[0] gpio_noesd[17]
++ gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] gpio_noesd[12] gpio_noesd[11] gpio_noesd[10]
++ gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] gpio_noesd[4] gpio_noesd[3] gpio_noesd[2]
++ gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[5]
++ io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] io_clamp_high[2] io_clamp_high[1]
++ io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_irq[2] user_irq[1] user_irq[0] la_oenb[127]
++ la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] la_oenb[119]
++ la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] la_oenb[111]
++ la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] la_oenb[103]
++ la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] la_oenb[94]
++ la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] la_oenb[85]
++ la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] la_oenb[76]
++ la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] la_oenb[67]
++ la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] la_oenb[58]
++ la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] la_oenb[49]
++ la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] la_oenb[40]
++ la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] la_oenb[31]
++ la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] la_oenb[22]
++ la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] la_oenb[13]
++ la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] la_oenb[4]
++ la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0]
+*.PININFO vdda1:B vdda2:B vssa1:B vssa2:B vccd1:B vccd2:B vssd1:B vssd2:B wb_clk_i:I wb_rst_i:I
+*+ wbs_stb_i:I wbs_cyc_i:I wbs_we_i:I wbs_sel_i[3:0]:I wbs_dat_i[31:0]:I wbs_adr_i[31:0]:I wbs_ack_o:O
+*+ wbs_dat_o[31:0]:O la_data_in[127:0]:I la_data_out[127:0]:O io_in[26:0]:I io_in_3v3[26:0]:I user_clock2:I
+*+ io_out[26:0]:O io_oeb[26:0]:O gpio_analog[17:0]:B gpio_noesd[17:0]:B io_analog[10:0]:B io_clamp_high[2:0]:B
+*+ io_clamp_low[2:0]:B user_irq[2:0]:O la_oenb[127:0]:I
+x1 vccd1 io_analog[2] io_in[0] io_in[1] io_in[2] io_in[3] vssa1 io_analog[0] io_analog[1]
++ vco_with_fdivs
+.ends
+
+* expanding symbol:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_with_fdivs.sym # of pins=9
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_with_fdivs.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_with_fdivs.sch
+.subckt vco_with_fdivs vdd vctrl vsel0 vsel1 vsel2 vsel3 vss out_div128 out_div256
+*.PININFO vctrl:I out_div128:O vdd:B vss:B vsel0:I vsel1:I vsel2:I vsel3:I out_div256:O
+xvco vdd out vctrl vss vsel0 vsel1 vsel2 vsel3 3-stage_cs-vco_dp9
+xFD_0 vdd out_div2 vss out FD_v5
+xFD_1 vdd out_div4 vss out_div2 FD
+xFD_2 vdd out_div8 vss out_div4 FD
+xFD_3 vdd out_div16 vss out_div8 FD
+xFD_4 vdd out_div32 vss out_div16 FD
+xFD_5 vdd out_div64 vss out_div32 FD
+xFD_6 vdd out_div128 vss out_div64 FD
+xFD_7 vdd out_div256 vss out_div128 FD
+xFD_8 vdd out_div512 vss out_div256 FD
+xFD_9 vdd out_div1024 vss out_div512 FD
+.ends
+
+
+* expanding symbol: 3-stage_cs-vco_dp9.sym # of pins=8
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/3-stage_cs-vco_dp9.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/3-stage_cs-vco_dp9.sch
+.subckt 3-stage_cs-vco_dp9 vdd out vctrl vss sel0 sel1 sel2 sel3
+*.PININFO vdd:B vss:B out:O vctrl:I sel0:I sel1:I sel2:I sel3:I
+XM25 vgp vgp vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 vgp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11C net2 pg2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 net3 net5 net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net4 net3 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net5 net4 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 net5 net8 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net4 net3 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net5 net4 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 net6 net5 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 net6 net5 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 out net7 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=6.6 nf=3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 out net7 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1.29 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net7 net6 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net7 net6 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+*Cnet8 net3 vss 0.87f m=1
+*Cnet9 net4 vss 1.14f m=1
+*Cnet10 net5 vss 3.49f m=1
+XMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1n vdd ng0 vctrl vss sel0 vco_switch_n
+XM16B net8 ng1 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2n vdd ng1 vctrl vss sel1 vco_switch_n
+XM16C net8 ng2 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x3n vdd ng2 vctrl vss sel2 vco_switch_n
+XM16D net8 ng3 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+x4n vdd ng3 vctrl vss sel3 vco_switch_n
+x3p vdd pg2 vgp vss sel2 vco_switch_p
+XM11D net2 pg3 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+x4p vdd pg3 vgp vss sel3 vco_switch_p
+XM11B net2 pg1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2p vdd pg1 vgp vss sel1 vco_switch_p
+XM11A net2 pg0 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1p vdd pg0 vgp vss sel0 vco_switch_p
+XM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 vgp vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: FD_v5.sym # of pins=4
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/FD_v5.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/FD_v5.sch
+.subckt FD_v5 VDD Clk_Out GND Clk_In
+*.PININFO Clk_In:I VDD:B GND:B Clk_Out:O
+XMPbuf1 7 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMPClkin Clk_In_buf Clkb_buf VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XMNClkin Clk_In_buf Clkb_buf GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XMPinv2 5 4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNinv2 5 4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPinv1 3 2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNinv1 3 2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPTgate1 4 Clkb_buf 3 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNTgate1 4 Clk_In_buf 3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XMPTgate2 6 Clk_In_buf 5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNTgate2 6 Clkb_buf 5 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XMPbuf2 Clk_Out 7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMNbuf2 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMPfb 2 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNfb 2 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPClkin_b2 net1 Clkb_int VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNClkin_b2 net1 Clkb_int GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XMPClkin_b1 Clkb_int Clk_In VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMNClkin_b1 Clkb_int Clk_In GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMPClkin_b3 Clkb_buf net1 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=7 m=7
+XMNClkin_b3 Clkb_buf net1 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+.ends
+
+
+* expanding symbol: FD.sym # of pins=4
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/FD.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/FD.sch
+.subckt FD VDD Clk_Out GND Clk_In
+*.PININFO Clk_In:I VDD:B GND:B Clk_Out:O
+XM15 7 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 7 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 2 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 2 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Clkb Clk_In VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM14 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 5 4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 5 4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 3 2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 3 2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 4 Clkb 3 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 6 Clk_In 5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 6 Clkb 5 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 Clk_Out 7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: vco_switch_n.sym # of pins=5
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_switch_n.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_switch_n.sch
+.subckt vco_switch_n vdd out in vss sel
+*.PININFO in:I sel:I out:O vss:B vdd:B
+XM26 in sel out vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out selb in vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 out selb vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 sel vss vss vdd vdd selb sky130_fd_sc_hd__inv_1
+**** begin user architecture code
+
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+.ends
+
+
+* expanding symbol: vco_switch_p.sym # of pins=5
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_switch_p.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/VCO_spro3/VCO_-_seccopy_16-3-2022_11y40/vco/xschem/vco_switch_p.sch
+.subckt vco_switch_p vdd out in vss sel
+*.PININFO in:I sel:I out:O vss:B vdd:B
+XM26 in sel out vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out selb in vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 sel vss vss vdd vdd selb sky130_fd_sc_hd__inv_1
+XM1 vdd sel out vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**** begin user architecture code
+
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+.ends
+
+.end
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
index e3cbcec..65f821f 100644
--- a/xschem/user_analog_project_wrapper.sch
+++ b/xschem/user_analog_project_wrapper.sch
@@ -1,69 +1,42 @@
-v {xschem version=2.9.9 file_version=1.2 }
+v {xschem version=3.0.0 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
-N 3830 -460 3830 -390 { lab=vdda1}
-N 3730 -460 3830 -460 { lab=vdda1}
-N 3860 -230 3860 -180 { lab=vssa1}
-N 3770 -180 3860 -180 { lab=vssa1}
-N 3890 -460 3890 -390 { lab=vccd1}
-N 3890 -460 3960 -460 { lab=vccd1}
-N 3890 -130 3890 -60 { lab=vccd1}
-N 3890 -130 3950 -130 { lab=vccd1}
-N 3830 -130 3830 -60 { lab=io_analog[4]}
-N 3790 -130 3830 -130 { lab=io_analog[4]}
-N 3860 100 3860 150 { lab=vssa1}
-N 3800 150 3860 150 { lab=vssa1}
-N 4010 -10 4110 -10 { lab=gpio_analog[7]}
-N 4010 20 4110 20 { lab=io_out[15]}
-N 4010 50 4110 50 { lab=io_out[16]}
-N 4010 -340 4130 -340 { lab=gpio_analog[3]}
-N 4010 -310 4130 -310 { lab=io_out[11]}
-N 4010 -280 4130 -280 { lab=io_out[12]}
-N 3670 300 3670 340 { lab=io_clamp_low[2]}
-N 3670 400 3670 420 { lab=vssa1}
-N 3670 440 3670 460 { lab=io_clamp_high[2]}
-N 3670 520 3670 530 { lab=vssa1}
-N 3670 570 3670 590 { lab=io_clamp_low[1]}
-N 3670 650 3670 670 { lab=vssa1}
-N 4160 300 4160 330 { lab=io_clamp_high[1]}
-N 4160 390 4160 410 { lab=vssa1}
-N 4160 440 4160 460 { lab=io_clamp_low[0]}
-N 4160 520 4160 530 { lab=vssa1}
-N 4160 550 4160 560 { lab=io_clamp_high[0]}
-N 4160 620 4160 640 { lab=io_analog[4]}
-N 3630 300 3670 300 { lab=io_clamp_low[2]}
-N 3630 420 3670 420 { lab=vssa1}
-N 3630 440 3670 440 { lab=io_clamp_high[2]}
-N 3630 530 3670 530 { lab=vssa1}
-N 3630 570 3670 570 { lab=io_clamp_low[1]}
-N 3630 670 3670 670 { lab=vssa1}
-N 4130 300 4160 300 { lab=io_clamp_high[1]}
-N 4130 410 4160 410 { lab=vssa1}
-N 4130 440 4160 440 { lab=io_clamp_low[0]}
-N 4130 530 4160 530 { lab=vssa1}
-N 4130 550 4160 550 { lab=io_clamp_high[0]}
-N 4130 640 4160 640 { lab=io_analog[4]}
-N 3670 710 3670 750 { lab=io_oeb[12]}
-N 3670 810 3670 830 { lab=vssd1}
-N 3670 850 3670 870 { lab=io_oeb[16]}
-N 3670 930 3670 940 { lab=vssd1}
-N 4160 710 4160 740 { lab=io_oeb[11]}
-N 4160 800 4160 820 { lab=vssd1}
-N 4160 850 4160 870 { lab=#net1}
-N 4160 930 4160 940 { lab=vssd1}
-N 3630 710 3670 710 { lab=io_oeb[12]}
-N 3630 830 3670 830 { lab=vssd1}
-N 3630 850 3670 850 { lab=io_oeb[16]}
-N 3630 940 3670 940 { lab=vssd1}
-N 4130 710 4160 710 { lab=io_oeb[11]}
-N 4130 820 4160 820 { lab=vssd1}
-N 4130 850 4160 850 { lab=#net1}
-N 4130 940 4160 940 { lab=vssd1}
-C {example_por.sym} 3860 -310 0 0 {name=x1}
-C {example_por.sym} 3860 20 0 0 {name=x2}
+N 3720 330 3720 370 { lab=vccd1}
+N 3720 430 3720 450 { lab=io_oeb[17]}
+N 3720 470 3720 490 { lab=vccd1}
+N 3720 550 3720 560 { lab=io_oeb[18]}
+N 4210 330 4210 360 { lab=vccd1}
+N 4210 420 4210 440 { lab=io_oeb[19]}
+N 4210 470 4210 490 { lab=vccd1}
+N 4210 550 4210 560 { lab=io_oeb[20]}
+N 3680 330 3720 330 { lab=vccd1}
+N 3680 450 3720 450 { lab=io_oeb[17]}
+N 3680 470 3720 470 { lab=vccd1}
+N 3680 560 3720 560 { lab=io_oeb[18]}
+N 4180 330 4210 330 { lab=vccd1}
+N 4180 440 4210 440 { lab=io_oeb[19]}
+N 4180 470 4210 470 { lab=vccd1}
+N 4180 560 4210 560 { lab=io_oeb[20]}
+N 4040 -210 4100 -210 { lab=vccd1}
+N 4040 -190 4100 -190 { lab=vssa1}
+N 4040 -170 4100 -170 { lab=io_out[14]}
+N 4040 -150 4100 -150 { lab=gpio_analog[8]}
+N 3680 -210 3740 -210 { lab=gpio_analog[9]}
+N 3680 -190 3740 -190 { lab=io_in[17]}
+N 3680 -170 3740 -170 { lab=io_in[18]}
+N 3680 -150 3740 -150 { lab=io_in[19]}
+N 3680 -130 3740 -130 { lab=io_in[20]}
+N 3720 180 3720 200 { lab=vssa1}
+N 3680 200 3720 200 { lab=vssa1}
+N 3720 80 3720 120 { lab=io_oeb[14]}
+N 3680 80 3720 80 { lab=io_oeb[14]}
+N 4210 180 4210 200 { lab=vssa1}
+N 4170 200 4210 200 { lab=vssa1}
+N 4210 80 4210 120 { lab=io_oeb[15]}
+N 4170 80 4210 80 { lab=io_oeb[15]}
C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
@@ -96,85 +69,55 @@
C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
-C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
-C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
-C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
-C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
-C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
-C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
-C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
-C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
-C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
-C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}
-C {sky130_fd_pr/res_generic_m1.sym} 3670 370 0 0 {name=R1
-W=11
-L=0.25
-model=res_generic_m3
-mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 3670 490 0 0 {name=R2
-W=11
-L=0.25
-model=res_generic_m3
-mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 3670 620 0 0 {name=R4
-W=11
-L=0.25
-model=res_generic_m3
-mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 4160 360 0 0 {name=R5
-W=11
-L=0.25
-model=res_generic_m3
-mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 4160 490 0 0 {name=R6
-W=11
-L=0.25
-model=res_generic_m3
-mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 4160 590 0 0 {name=R7
-W=11
-L=0.25
-model=res_generic_m3
-mult=1}
-C {devices/lab_pin.sym} 3630 300 0 0 {name=l13 sig_type=std_logic lab=io_clamp_low[2]}
-C {devices/lab_pin.sym} 3630 440 0 0 {name=l14 sig_type=std_logic lab=io_clamp_high[2]}
-C {devices/lab_pin.sym} 3630 570 0 0 {name=l15 sig_type=std_logic lab=io_clamp_low[1]}
-C {devices/lab_pin.sym} 4130 300 0 0 {name=l16 sig_type=std_logic lab=io_clamp_high[1]}
-C {devices/lab_pin.sym} 4130 440 0 0 {name=l17 sig_type=std_logic lab=io_clamp_low[0]}
-C {devices/lab_pin.sym} 3630 420 0 0 {name=l18 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 3630 530 0 0 {name=l19 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 4130 410 0 0 {name=l20 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 4130 530 0 0 {name=l21 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 3630 670 0 0 {name=l22 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 4130 550 0 0 {name=l23 sig_type=std_logic lab=io_clamp_high[0]}
-C {devices/lab_pin.sym} 4130 640 0 0 {name=l24 sig_type=std_logic lab=io_analog[4]}
-C {sky130_fd_pr/res_generic_m1.sym} 3670 780 0 0 {name=R8
+C {sky130_fd_pr/res_generic_m1.sym} 3720 400 0 0 {name=R8
W=0.56
-L=0.49
+L=0.28
model=res_generic_m3
mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 3670 900 0 0 {name=R9
+C {sky130_fd_pr/res_generic_m1.sym} 3720 520 0 0 {name=R9
W=0.56
-L=0.31
+L=0.28
model=res_generic_m3
mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 4160 770 0 0 {name=R11
+C {sky130_fd_pr/res_generic_m1.sym} 4210 390 0 0 {name=R11
W=0.56
-L=0.58
+L=0.28
model=res_generic_m3
mult=1}
-C {sky130_fd_pr/res_generic_m1.sym} 4160 900 0 0 {name=R12
+C {sky130_fd_pr/res_generic_m1.sym} 4210 520 0 0 {name=R12
W=0.56
-L=0.6
+L=0.28
model=res_generic_m3
mult=1}
-C {devices/lab_pin.sym} 4130 850 0 0 {name=l25 sig_type=std_logic lab=io_oeb[15]}
-C {devices/lab_pin.sym} 3630 850 0 0 {name=l26 sig_type=std_logic lab=io_oeb[16]}
-C {devices/lab_pin.sym} 4130 710 0 0 {name=l27 sig_type=std_logic lab=io_oeb[11]}
-C {devices/lab_pin.sym} 3630 710 0 0 {name=l28 sig_type=std_logic lab=io_oeb[12]}
-C {devices/lab_pin.sym} 3630 830 0 0 {name=l29 sig_type=std_logic lab=vssd1}
-C {devices/lab_pin.sym} 3630 940 0 0 {name=l30 sig_type=std_logic lab=vssd1}
-C {devices/lab_pin.sym} 4130 820 0 0 {name=l31 sig_type=std_logic lab=vssd1}
-C {devices/lab_pin.sym} 4130 940 0 0 {name=l32 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 4180 560 0 0 {name=l25 sig_type=std_logic lab=io_oeb[20]}
+C {devices/lab_pin.sym} 3680 560 0 0 {name=l26 sig_type=std_logic lab=io_oeb[18]}
+C {devices/lab_pin.sym} 4180 440 0 0 {name=l27 sig_type=std_logic lab=io_oeb[19]}
+C {devices/lab_pin.sym} 3680 450 0 0 {name=l28 sig_type=std_logic lab=io_oeb[17]}
+C {devices/lab_pin.sym} 3680 330 0 0 {name=l29 sig_type=std_logic lab=vccd1}
+C {./3-stage_cs-vco_dp9/vco_with_fdivs.sym} 3890 -170 0 0 {name=x1}
+C {devices/lab_pin.sym} 4100 -210 0 1 {name=l33 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4100 -190 0 1 {name=l7 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4100 -150 0 1 {name=l9 sig_type=std_logic lab=io_out[15]}
+C {devices/lab_pin.sym} 3680 -210 0 0 {name=l34 sig_type=std_logic lab=gpio_analog[9]}
+C {devices/lab_pin.sym} 4100 -170 0 1 {name=l8 sig_type=std_logic lab=io_out[14]}
+C {devices/lab_pin.sym} 3680 -190 0 0 {name=l35 sig_type=std_logic lab=io_in[17]}
+C {devices/lab_pin.sym} 3680 -170 0 0 {name=l36 sig_type=std_logic lab=io_in[18]}
+C {devices/lab_pin.sym} 3680 -150 0 0 {name=l37 sig_type=std_logic lab=io_in[19]}
+C {devices/lab_pin.sym} 3680 -130 0 0 {name=l38 sig_type=std_logic lab=io_in[20]}
+C {devices/lab_pin.sym} 3680 470 0 0 {name=l1 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4180 470 0 0 {name=l2 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4180 330 0 0 {name=l3 sig_type=std_logic lab=vccd1}
+C {sky130_fd_pr/res_generic_m1.sym} 3720 150 0 0 {name=R1
+W=0.56
+L=0.28
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 3680 80 0 0 {name=l4 sig_type=std_logic lab=io_oeb[14]}
+C {devices/lab_pin.sym} 3680 200 0 0 {name=l5 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/res_generic_m1.sym} 4210 150 0 0 {name=R2
+W=0.56
+L=0.28
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 4170 80 0 0 {name=l6 sig_type=std_logic lab=io_oeb[15]}
+C {devices/lab_pin.sym} 4170 200 0 0 {name=l10 sig_type=std_logic lab=vssa1}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
index 0dc2d20..3101e62 100644
--- a/xschem/user_analog_project_wrapper.spice
+++ b/xschem/user_analog_project_wrapper.spice
@@ -1,3 +1,5 @@
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/user_analog_project_wrapper.sch
.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
+ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
@@ -83,120 +85,350 @@
+ la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] la_oenb[13]
+ la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] la_oenb[4]
+ la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0]
-*.iopin vdda1
-*.iopin vdda2
-*.iopin vssa1
-*.iopin vssa2
-*.iopin vccd1
-*.iopin vccd2
-*.iopin vssd1
-*.iopin vssd2
-*.ipin wb_clk_i
-*.ipin wb_rst_i
-*.ipin wbs_stb_i
-*.ipin wbs_cyc_i
-*.ipin wbs_we_i
-*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
-*.ipin
-*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
-*.ipin
-*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
-*.opin wbs_ack_o
-*.opin
-*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
-*.ipin
-*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
-*.opin
-*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
-*.ipin
-*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
-*.ipin
-*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
-*.ipin user_clock2
-*.opin
-*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
-*.opin
-*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
-*.iopin
-*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
-*.iopin
-*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
-*.iopin
-*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
-*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
-*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
-*.opin user_irq[2],user_irq[1],user_irq[0]
-*.ipin
-*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
-x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
-x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
-R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R3 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1
-R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R8 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R10 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1
-R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
-R12 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+*.PININFO vdda1:B vdda2:B vssa1:B vssa2:B vccd1:B vccd2:B vssd1:B vssd2:B wb_clk_i:I wb_rst_i:I
+*+ wbs_stb_i:I wbs_cyc_i:I wbs_we_i:I wbs_sel_i[3:0]:I wbs_dat_i[31:0]:I wbs_adr_i[31:0]:I wbs_ack_o:O
+*+ wbs_dat_o[31:0]:O la_data_in[127:0]:I la_data_out[127:0]:O io_in[26:0]:I io_in_3v3[26:0]:I user_clock2:I
+*+ io_out[26:0]:O io_oeb[26:0]:O gpio_analog[17:0]:B gpio_noesd[17:0]:B io_analog[10:0]:B io_clamp_high[2:0]:B
+*+ io_clamp_low[2:0]:B user_irq[2:0]:O la_oenb[127:0]:I
+R8 io_oeb[17] vccd1 sky130_fd_pr__res_generic_m3 W=0.56 L=0.28 m=1
+R9 io_oeb[18] vccd1 sky130_fd_pr__res_generic_m3 W=0.56 L=0.28 m=1
+R11 io_oeb[19] vccd1 sky130_fd_pr__res_generic_m3 W=0.56 L=0.28 m=1
+R12 io_oeb[20] vccd1 sky130_fd_pr__res_generic_m3 W=0.56 L=0.28 m=1
+x1 vccd1 gpio_analog[9] io_in[17] io_in[18] io_in[19] io_in[20] vssa1 io_out[14] io_out[15]
++ vco_with_fdivs
+R1 vssa1 io_oeb[14] sky130_fd_pr__res_generic_m3 W=0.56 L=0.28 m=1
+R2 vssa1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=0.56 L=0.28 m=1
.ends
-* expanding symbol: example_por.sym # of pins=6
-* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
-* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
-.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
-*.iopin vdd3v3
-*.iopin vss
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-*.iopin vdd1v8
-XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
-XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
-XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
-XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
-XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
-x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
-x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
-x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
-x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+* expanding symbol: ./3-stage_cs-vco_dp9/vco_with_fdivs.sym # of pins=9
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sch
+.subckt vco_with_fdivs vdd vctrl vsel0 vsel1 vsel2 vsel3 vss out_div128_buf out_div256_buf
+*.PININFO vctrl:I out_div128_buf:O vdd:B vss:B vsel0:I vsel1:I vsel2:I vsel3:I out_div256_buf:O
+xvco vdd out vctrl vss vsel0 vsel1 vsel2 vsel3 3-stage_cs-vco_dp9
+xFD_0 vdd out_div2 vss out FD_v5
+xbuf2a out_div128 vss vss vdd vdd buf2a_out sky130_fd_sc_hd__clkbuf_2
+xbuf4a buf2a_out vss vss vdd vdd buf4a_out sky130_fd_sc_hd__clkbuf_4
+xbuf8a buf4a_out vss vss vdd vdd buf8a_out sky130_fd_sc_hd__clkbuf_8
+xFD_1 vdd out_div4 vss out_div2 FD
+xFD_2 vdd out_div8 vss out_div4 FD
+xFD_3 vdd out_div16 vss out_div8 FD
+xFD_4 vdd out_div32 vss out_div16 FD
+xFD_5 vdd out_div64 vss out_div32 FD
+xFD_6 vdd out_div128 vss out_div64 FD
+xFD_7 vdd out_div256 vss out_div128 FD
+xbuf2b out_div256 vss vss vdd vdd buf2b_out sky130_fd_sc_hd__clkbuf_2
+xbuf4b buf2b_out vss vss vdd vdd buf4b_out sky130_fd_sc_hd__clkbuf_4
+xbuf8b buf4b_out vss vss vdd vdd buf8b_out sky130_fd_sc_hd__clkbuf_8
+xFD_8 vdd out_div512 vss out_div256 FD
+xFD_9 vdd out_div1024 vss out_div512 FD
+xbuf16a buf8a_out vss vss vdd vdd buf16a_out sky130_fd_sc_hd__clkbuf_16
+xbuf16b buf8b_out vss vss vdd vdd out_div256_buf sky130_fd_sc_hd__clkbuf_16
+xbuf32a_1 buf16a_out vss vss vdd vdd out_div128_buf sky130_fd_sc_hd__clkbuf_16
+xbuf32a_2 buf16a_out vss vss vdd vdd out_div128_buf sky130_fd_sc_hd__clkbuf_16
.ends
-** flattened .save nodes
+
+* expanding symbol: 3-stage_cs-vco_dp9.sym # of pins=8
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sch
+.subckt 3-stage_cs-vco_dp9 vdd out vctrl vss sel0 sel1 sel2 sel3
+*.PININFO vdd:B vss:B out:O vctrl:I sel0:I sel1:I sel2:I sel3:I
+XM25 vgp vgp vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 vgp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11C net2 pg2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 net3 net5 net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net4 net3 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net5 net4 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 net5 net8 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net4 net3 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net5 net4 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 net6 net5 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 net6 net5 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 out net7 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=6.6 nf=3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 out net7 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1.29 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net7 net6 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net7 net6 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+*Cnet8 net3 vss 0.87f m=1
+*Cnet9 net4 vss 1.14f m=1
+*Cnet10 net5 vss 3.49f m=1
+XMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1n vdd ng0 vctrl vss sel0 vco_switch_n
+XM16B net8 ng1 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2n vdd ng1 vctrl vss sel1 vco_switch_n
+XM16C net8 ng2 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x3n vdd ng2 vctrl vss sel2 vco_switch_n
+XM16D net8 ng3 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+x4n vdd ng3 vctrl vss sel3 vco_switch_n
+x3p vdd pg2 vgp vss sel2 vco_switch_p
+XM11D net2 pg3 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+x4p vdd pg3 vgp vss sel3 vco_switch_p
+XM11B net2 pg1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2p vdd pg1 vgp vss sel1 vco_switch_p
+XM11A net2 pg0 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1p vdd pg0 vgp vss sel0 vco_switch_p
+XM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 vgp vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: FD_v5.sym # of pins=4
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD_v5.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD_v5.sch
+.subckt FD_v5 VDD Clk_Out GND Clk_In
+*.PININFO Clk_In:I VDD:B GND:B Clk_Out:O
+XMPbuf1 7 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMPClkin Clk_In_buf Clkb_buf VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XMNClkin Clk_In_buf Clkb_buf GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XMPinv2 5 4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNinv2 5 4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPinv1 3 2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNinv1 3 2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPTgate1 4 Clkb_buf 3 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNTgate1 4 Clk_In_buf 3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XMPTgate2 6 Clk_In_buf 5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNTgate2 6 Clkb_buf 5 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XMPbuf2 Clk_Out 7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMNbuf2 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMPfb 2 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNfb 2 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPClkin_b2 net1 Clkb_int VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNClkin_b2 net1 Clkb_int GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XMPClkin_b1 Clkb_int Clk_In VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMNClkin_b1 Clkb_int Clk_In GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMPClkin_b3 Clkb_buf net1 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=7 m=7
+XMNClkin_b3 Clkb_buf net1 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+.ends
+
+
+* expanding symbol: FD.sym # of pins=4
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD.sch
+.subckt FD VDD Clk_Out GND Clk_In
+*.PININFO Clk_In:I VDD:B GND:B Clk_Out:O
+XM15 7 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 7 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 2 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 2 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Clkb Clk_In VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM14 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 5 4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 5 4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 3 2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 3 2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 4 Clkb 3 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 6 Clk_In 5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 6 Clkb 5 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 Clk_Out 7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: vco_switch_n.sym # of pins=5
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_n.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_n.sch
+.subckt vco_switch_n vdd out in vss sel
+*.PININFO in:I sel:I out:O vss:B vdd:B
+XM26 in sel out vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out selb in vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 out selb vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 sel vss vss vdd vdd selb sky130_fd_sc_hd__inv_1
+**** begin user architecture code
+
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+.ends
+
+
+* expanding symbol: vco_switch_p.sym # of pins=5
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_p.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_p.sch
+.subckt vco_switch_p vdd out in vss sel
+*.PININFO in:I sel:I out:O vss:B vdd:B
+XM26 in sel out vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out selb in vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 sel vss vss vdd vdd selb sky130_fd_sc_hd__inv_1
+XM1 vdd sel out vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**** begin user architecture code
+
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+.ends
+
.end
diff --git a/xschem/vco_with_fdivs.spice b/xschem/vco_with_fdivs.spice
new file mode 100644
index 0000000..ad0c098
--- /dev/null
+++ b/xschem/vco_with_fdivs.spice
@@ -0,0 +1,328 @@
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_with_fdivs.sch
+.subckt vco_with_fdivs vctrl out_div128_buf vdd vss vsel0 vsel1 vsel2 vsel3 out_div256_buf
+*.PININFO vctrl:I out_div128_buf:O vdd:B vss:B vsel0:I vsel1:I vsel2:I vsel3:I out_div256_buf:O
+xvco vdd out vctrl vss vsel0 vsel1 vsel2 vsel3 3-stage_cs-vco_dp9
+xFD_0 vdd out_div2 vss out FD_v5
+xbuf2a out_div128 vss vss vdd vdd buf2a_out sky130_fd_sc_hd__clkbuf_2
+xbuf4a buf2a_out vss vss vdd vdd buf4a_out sky130_fd_sc_hd__clkbuf_4
+xbuf8a buf4a_out vss vss vdd vdd buf8a_out sky130_fd_sc_hd__clkbuf_8
+xFD_1 vdd out_div4 vss out_div2 FD
+xFD_2 vdd out_div8 vss out_div4 FD
+xFD_3 vdd out_div16 vss out_div8 FD
+xFD_4 vdd out_div32 vss out_div16 FD
+xFD_5 vdd out_div64 vss out_div32 FD
+xFD_6 vdd out_div128 vss out_div64 FD
+xFD_7 vdd out_div256 vss out_div128 FD
+xbuf2b out_div256 vss vss vdd vdd buf2b_out sky130_fd_sc_hd__clkbuf_2
+xbuf4b buf2b_out vss vss vdd vdd buf4b_out sky130_fd_sc_hd__clkbuf_4
+xbuf8b buf4b_out vss vss vdd vdd buf8b_out sky130_fd_sc_hd__clkbuf_8
+xFD_8 vdd out_div512 vss out_div256 FD
+xFD_9 vdd out_div1024 vss out_div512 FD
+xbuf16a buf8a_out vss vss vdd vdd buf16a_out sky130_fd_sc_hd__clkbuf_16
+xbuf16b buf8b_out vss vss vdd vdd out_div256_buf sky130_fd_sc_hd__clkbuf_16
+xbuf32a_1 buf16a_out vss vss vdd vdd out_div128_buf sky130_fd_sc_hd__clkbuf_16
+xbuf32a_2 buf16a_out vss vss vdd vdd out_div128_buf sky130_fd_sc_hd__clkbuf_16
+.ends
+
+* expanding symbol: 3-stage_cs-vco_dp9.sym # of pins=8
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/3-stage_cs-vco_dp9.sch
+.subckt 3-stage_cs-vco_dp9 vdd out vctrl vss sel0 sel1 sel2 sel3
+*.PININFO vdd:B vss:B out:O vctrl:I sel0:I sel1:I sel2:I sel3:I
+XM25 vgp vgp vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 vgp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11C net2 pg2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16A net8 ng0 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 net3 net5 net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net4 net3 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net5 net4 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 net5 net8 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net4 net3 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net5 net4 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 net6 net5 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 net6 net5 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 out net7 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=6.6 nf=3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 out net7 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1.29 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net7 net6 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net7 net6 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM16B vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM16 vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM26 vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM11B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM11 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM25 vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+*Cnet8 net3 vss 0.87f m=1
+*Cnet9 net4 vss 1.14f m=1
+*Cnet10 net5 vss 3.49f m=1
+XMDUM26B vss vss vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMDUM25B vdd vdd vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1n vdd ng0 vctrl vss sel0 vco_switch_n
+XM16B net8 ng1 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2n vdd ng1 vctrl vss sel1 vco_switch_n
+XM16C net8 ng2 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x3n vdd ng2 vctrl vss sel2 vco_switch_n
+XM16D net8 ng3 vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+x4n vdd ng3 vctrl vss sel3 vco_switch_n
+x3p vdd pg2 vgp vss sel2 vco_switch_p
+XM11D net2 pg3 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=2.4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+x4p vdd pg3 vgp vss sel3 vco_switch_p
+XM11B net2 pg1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=1.2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2p vdd pg1 vgp vss sel1 vco_switch_p
+XM11A net2 pg0 vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1p vdd pg0 vgp vss sel0 vco_switch_p
+XM16 net8 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 vgp vdd vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: FD_v5.sym # of pins=4
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD_v5.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD_v5.sch
+.subckt FD_v5 VDD Clk_Out GND Clk_In
+*.PININFO Clk_In:I VDD:B GND:B Clk_Out:O
+XMPbuf1 7 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMNbuf1 7 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XMPClkin Clk_In_buf Clkb_buf VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XMNClkin Clk_In_buf Clkb_buf GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XMPinv2 5 4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNinv2 5 4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPinv1 3 2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNinv1 3 2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPTgate1 4 Clkb_buf 3 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNTgate1 4 Clk_In_buf 3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XMPTgate2 6 Clk_In_buf 5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNTgate2 6 Clkb_buf 5 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XMPbuf2 Clk_Out 7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMNbuf2 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMPfb 2 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XMNfb 2 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XMPClkin_b2 net1 Clkb_int VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XMNClkin_b2 net1 Clkb_int GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XMPClkin_b1 Clkb_int Clk_In VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMNClkin_b1 Clkb_int Clk_In GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XMPClkin_b3 Clkb_buf net1 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1.44 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=7 m=7
+XMNClkin_b3 Clkb_buf net1 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+.ends
+
+
+* expanding symbol: FD.sym # of pins=4
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/FD.sch
+.subckt FD VDD Clk_Out GND Clk_In
+*.PININFO Clk_In:I VDD:B GND:B Clk_Out:O
+XM15 7 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 7 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 2 6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 2 6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Clkb Clk_In VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM14 Clkb Clk_In GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 5 4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 5 4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 3 2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 3 2 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 4 Clkb 3 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 4 Clk_In 3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 6 Clk_In 5 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 6 Clkb 5 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 Clk_Out 7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Clk_Out 7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: vco_switch_n.sym # of pins=5
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_n.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_n.sch
+.subckt vco_switch_n vdd out in vss sel
+*.PININFO in:I sel:I out:O vss:B vdd:B
+XM26 in sel out vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out selb in vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 out selb vss vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 sel vss vss vdd vdd selb sky130_fd_sc_hd__inv_1
+**** begin user architecture code
+
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+.ends
+
+
+* expanding symbol: vco_switch_p.sym # of pins=5
+** sym_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_p.sym
+** sch_path:
+*+ /home/darunixspro3/Desktop/GitSandboxes/caravel_user_project_analog_vco/xschem/3-stage_cs-vco_dp9/vco_switch_p.sch
+.subckt vco_switch_p vdd out in vss sel
+*.PININFO in:I sel:I out:O vss:B vdd:B
+XM26 in sel out vss sky130_fd_pr__nfet_01v8 L=0.18 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out selb in vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 sel vss vss vdd vdd selb sky130_fd_sc_hd__inv_1
+XM1 vdd sel out vdd sky130_fd_pr__pfet_01v8 L=0.18 W=0.72 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**** begin user architecture code
+
+.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
+
+**** end user architecture code
+.ends
+
+.end
diff --git a/xschem/xschemrc b/xschem/xschemrc
index ca6e33e..9e3a014 100644
--- a/xschem/xschemrc
+++ b/xschem/xschemrc
@@ -27,7 +27,8 @@
#### Allow user environment to override the path to the PDK
if {[catch {set PDKPATH $env(PDKPATH)}]} {
- set PDKPATH "/usr/share/pdk/sky130A"
+#### set PDKPATH "/usr/share/pdk/sky130A"
+ set PDKPATH "/usr/local/share/pdk/sky130A"
}
#### Flush any previous definition
set XSCHEM_LIBRARY_PATH {}
