|author||Teo Ene <email@example.com>||Thu Jul 23 23:35:15 2020 +0000|
|committer||Teo Ene <firstname.lastname@example.org>||Thu Jul 23 23:35:15 2020 +0000|
Updates to verilog files
System on Chip Design Flow including standard cells for SkyWater 130nm process
Thanks to the following for help, guidance and support!
This repository is released under the Apache 2.0 license. The full license text can be found in the
Copyright 2020 Board of Regents for the Oklahoma Agricultural and Mechanical Colleges Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License