Digital standard cells provided by Oklahoma State University.

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  1. b34fccd Update with corrected files by Teo Ene · 2 days ago master
  2. e7912ea Re-added in several sample hdl designs by Teo Ene · 6 weeks ago
  3. 701e93b Repurposing repository to hold the raw design flow used to create, extract, characterize, and test the OSU standard cells. by Teo Ene · 6 weeks ago
  4. 2260d92 Updates to verilog files by Teo Ene · 3 months ago
  5. 0d2d84d Fixed file naming from last commit by Teo Ene · 3 months ago

OSU_130_PDK

System on Chip Design Flow including standard cells for SkyWater 130nm process

VLSI Computer Architecture Research Group

  • James E. Stine, Jr.
  • Teo Ene
  • Landon Burleson
  • Ryan Swann
  • Ryan Ridley
  • Brett Mathis
  • Alex Underwood
  • S. Ross Thompson
  • Peter Tikalsky
  • Brandon Ong
  • Hunter Lusk

Thanks to the following for help, guidance and support!

License

This repository is released under the Apache 2.0 license. The full license text can be found in the LICENSE file.

Copyright 2020  Board of Regents for the Oklahoma Agricultural and Mechanical Colleges

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License