verilog/sky130_osu_sc_or2xl.v

// type: OR2 
`timescale 1ns/10ps
`celldefine
module sky130_osu_sc_OR2XL (Y, A, B);
	output Y;
	input A, B;

	// Function
	or (Y, A, B);

	// Timing
	specify
		(A => Y) = 0;
		(B => Y) = 0;
	endspecify
endmodule
`endcelldefine