Add files via upload
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.clock_skew.rpt
new file mode 100644
index 0000000..4f2dbf4
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_129_/CLK ^
+ 0.55
+_126_/CLK ^
+ 0.50 -0.03 0.02
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.max.rpt
new file mode 100644
index 0000000..96dcc0d
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.max.rpt
@@ -0,0 +1,276 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 2.73 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net11 (net)
+ 0.29 0.00 2.73 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.19 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.19 ^ io_oeb[1] (out)
+ 3.19 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.19 data arrival time
+-----------------------------------------------------------------------------
+ 20.56 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.23 2.71 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 net10 (net)
+ 0.27 0.00 2.71 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.17 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.17 ^ io_oeb[0] (out)
+ 3.17 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.17 data arrival time
+-----------------------------------------------------------------------------
+ 20.58 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.85 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_0 (net)
+ 0.28 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 1.65 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.29 0.00 1.65 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.54 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 net12 (net)
+ 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.83 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.84 ^ io_out[0] (out)
+ 2.84 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.84 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.27 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.27 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.90 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -8.90 data arrival time
+-----------------------------------------------------------------------------
+ 21.10 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.min.rpt
new file mode 100644
index 0000000..0ee8680
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.min.rpt
@@ -0,0 +1,283 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.57 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.57 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.57 data arrival time
+-----------------------------------------------------------------------------
+ 0.75 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.76 1.25 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 1.25 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 1.45 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.45 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 1.58 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 1.58 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.71 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.71 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.83 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.83 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.18 1.64 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.64 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.89 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.89 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 2.12 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 2.12 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.12 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.06 0.81 library hold time
+ 0.81 data required time
+-----------------------------------------------------------------------------
+ 0.81 data required time
+ -2.12 data arrival time
+-----------------------------------------------------------------------------
+ 1.31 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.98 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.98 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 2.15 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 2.15 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.15 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.04 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.15 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 2.03 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.03 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 2.22 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 2.22 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.22 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.08 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.22 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.rpt
new file mode 100644
index 0000000..e2950e1
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.rpt
@@ -0,0 +1,67 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/10-cts_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.area.rpt
new file mode 100644
index 0000000..e2d8331
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18295 u^2 4% utilization.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.clock_skew.rpt
new file mode 100644
index 0000000..4f2dbf4
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_129_/CLK ^
+ 0.55
+_126_/CLK ^
+ 0.50 -0.03 0.02
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.max.rpt
new file mode 100644
index 0000000..96dcc0d
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.max.rpt
@@ -0,0 +1,276 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 2.73 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net11 (net)
+ 0.29 0.00 2.73 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.19 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.19 ^ io_oeb[1] (out)
+ 3.19 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.19 data arrival time
+-----------------------------------------------------------------------------
+ 20.56 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.23 2.71 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 net10 (net)
+ 0.27 0.00 2.71 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.17 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.17 ^ io_oeb[0] (out)
+ 3.17 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.17 data arrival time
+-----------------------------------------------------------------------------
+ 20.58 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.85 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_0 (net)
+ 0.28 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 1.65 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.29 0.00 1.65 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.54 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 net12 (net)
+ 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.83 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.84 ^ io_out[0] (out)
+ 2.84 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.84 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.27 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.27 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.90 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -8.90 data arrival time
+-----------------------------------------------------------------------------
+ 21.10 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.min.rpt
new file mode 100644
index 0000000..0ee8680
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.min.rpt
@@ -0,0 +1,283 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.57 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.57 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.57 data arrival time
+-----------------------------------------------------------------------------
+ 0.75 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.76 1.25 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 1.25 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 1.45 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.45 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 1.58 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 1.58 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.71 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.71 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.83 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.83 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.18 1.64 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.64 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.89 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.89 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 2.12 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 2.12 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.12 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.06 0.81 library hold time
+ 0.81 data required time
+-----------------------------------------------------------------------------
+ 0.81 data required time
+ -2.12 data arrival time
+-----------------------------------------------------------------------------
+ 1.31 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.98 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.98 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 2.15 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 2.15 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.15 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.04 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.15 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 2.03 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.03 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 2.22 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 2.22 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.22 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.08 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.22 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.power.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.power.rpt
new file mode 100644
index 0000000..670e965
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 6.56e-06 1.22e-09 1.14e-04 19.6%
+Combinational 3.76e-04 9.18e-05 1.91e-07 4.68e-04 80.4%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.84e-04 9.83e-05 1.92e-07 5.82e-04 100.0%
+ 83.1% 16.9% 0.0%
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.rpt
new file mode 100644
index 0000000..e2950e1
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.rpt
@@ -0,0 +1,67 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.slew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.worst_slack.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.worst_slack.rpt
new file mode 100644
index 0000000..cb505a7
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/cts/11-cts_rsz_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.53
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.75
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/floorplan/3-initial_fp_core_area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/floorplan/3-initial_fp_core_area.rpt
new file mode 100644
index 0000000..3b55177
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/floorplan/3-initial_fp_core_area.rpt
@@ -0,0 +1 @@
+6.72 15.68 893.2 584.08
\ No newline at end of file
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/floorplan/3-initial_fp_die_area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/floorplan/3-initial_fp_die_area.rpt
new file mode 100644
index 0000000..068bdac
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/floorplan/3-initial_fp_die_area.rpt
@@ -0,0 +1 @@
+0.0 0.0 900.0 600.0
\ No newline at end of file
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/manufacturability.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/manufacturability.rpt
new file mode 100644
index 0000000..37e8ef8
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/manufacturability.rpt
@@ -0,0 +1,16 @@
+Design Name: plant_example
+Run Directory: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22
+----------------------------------------
+
+Magic DRC Summary:
+Source: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.rpt
+Total Magic DRC violations is 0
+----------------------------------------
+
+LVS Summary:
+Source: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/plant_example.lvs.lef.log
+Source not found.
+----------------------------------------
+
+Antenna Summary:
+No antenna report found.
\ No newline at end of file
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/metrics.csv b/openlane/user_proj_example/runs/user_proj_example/reports/metrics.csv
new file mode 100644
index 0000000..2e6e64a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/metrics.csv
@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
+/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example,plant_example,22_12_05_10_22,flow completed,0h2m35s0ms,0h1m24s0ms,168.98148148148147,2.16,67.5925925925926,0.42,605.0,146,0,0,0,0,0,0,0,-1,0,-1,-1,10197,737,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,20381060.0,0.0,1.08,0.57,0.0,-1,0.55,249,401,48,200,0,0,0,216,6,6,6,19,76,0,1,21,15,9,8,290,3236,0,3526,503875.2320000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,30.0,33.333333333333336,30.0,AREA 0,4,40,1,153.6,153.18,0.45,0.3,gf180mcu_fd_sc_mcu7t5v0,4
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.clock_skew.rpt
new file mode 100644
index 0000000..50da2ba
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_125_/CLK ^
+ 0.05
+_125_/CLK ^
+ 0.05 0.00 0.00
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.max.rpt
new file mode 100644
index 0000000..a275816
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.max.rpt
@@ -0,0 +1,240 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.78 0.43 6.83 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.78 0.00 6.83 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.34 0.40 7.23 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.34 0.00 7.23 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.57 7.80 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.80 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.25 0.21 8.01 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.25 0.00 8.01 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.23 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.23 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.72 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.72 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.14 0.23 8.95 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.14 0.00 8.95 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.95 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -8.95 data arrival time
+-----------------------------------------------------------------------------
+ 20.59 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.37 6.77 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.77 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.55 7.32 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.32 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.44 0.32 7.65 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.44 0.00 7.65 ^ _088_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.46 0.24 7.89 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _029_ (net)
+ 0.46 0.00 7.89 v _089_/S (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.13 0.42 8.31 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.00 _030_ (net)
+ 0.13 0.00 8.31 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.33 0.23 8.54 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.33 0.00 8.54 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.54 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.23 29.52 library setup time
+ 29.52 data required time
+-----------------------------------------------------------------------------
+ 29.52 data required time
+ -8.54 data arrival time
+-----------------------------------------------------------------------------
+ 20.98 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.37 6.77 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.77 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.55 7.32 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.32 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.44 0.32 7.65 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.44 0.00 7.65 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 7.76 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 7.76 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.28 8.04 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 8.04 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.15 0.29 8.33 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.15 0.00 8.33 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.25 0.20 8.53 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.25 0.00 8.53 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.53 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.22 29.53 library setup time
+ 29.53 data required time
+-----------------------------------------------------------------------------
+ 29.53 data required time
+ -8.53 data arrival time
+-----------------------------------------------------------------------------
+ 21.00 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.88 0.88 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.30 0.00 0.88 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.27 1.14 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.14 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.61 0.44 1.59 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.61 0.00 1.59 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.28 0.19 1.78 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.28 0.00 1.78 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1.43 0.94 2.72 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.07 io_oeb[0] (net)
+ 1.43 0.01 2.73 ^ io_oeb[0] (out)
+ 2.73 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.73 data arrival time
+-----------------------------------------------------------------------------
+ 21.02 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.88 0.88 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.30 0.00 0.88 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.27 1.14 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.14 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.61 0.44 1.59 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.61 0.00 1.59 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.28 0.19 1.78 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.28 0.00 1.78 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 1.36 0.91 2.69 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 2 0.08 io_oeb[1] (net)
+ 1.36 0.01 2.70 ^ io_oeb[1] (out)
+ 2.70 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.70 data arrival time
+-----------------------------------------------------------------------------
+ 21.05 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.min.rpt
new file mode 100644
index 0000000..17b240a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.min.rpt
@@ -0,0 +1,203 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.47 0.00 1.04 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.16 0.12 1.15 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.16 0.00 1.15 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.15 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.08 0.33 library hold time
+ 0.33 data required time
+-----------------------------------------------------------------------------
+ 0.33 data required time
+ -1.15 data arrival time
+-----------------------------------------------------------------------------
+ 0.83 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.69 0.69 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.20 0.00 0.70 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.22 0.17 0.87 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.22 0.00 0.87 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 0.99 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 0.99 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.12 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.12 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.24 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.24 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.24 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.24 data arrival time
+-----------------------------------------------------------------------------
+ 0.90 slack (MET)
+
+
+Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.27 0.78 0.78 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_2 (net)
+ 0.27 0.00 0.78 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.28 0.24 1.02 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.28 0.00 1.02 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 0.20 0.22 1.24 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 1 0.00 _017_ (net)
+ 0.20 0.00 1.24 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.16 0.28 1.52 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.16 0.00 1.52 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.13 0.11 1.63 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.13 0.00 1.63 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.63 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.63 data arrival time
+-----------------------------------------------------------------------------
+ 1.29 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.47 0.00 1.04 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.20 1.24 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.24 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.24 1.48 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 1.48 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.15 0.26 1.74 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.15 0.00 1.74 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.74 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.08 0.33 library hold time
+ 0.33 data required time
+-----------------------------------------------------------------------------
+ 0.33 data required time
+ -1.74 data arrival time
+-----------------------------------------------------------------------------
+ 1.41 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.47 0.00 1.04 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.24 1.28 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.28 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.11 0.34 1.62 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.11 0.00 1.62 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.11 0.23 1.85 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.11 0.00 1.85 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.85 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.85 data arrival time
+-----------------------------------------------------------------------------
+ 1.51 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.rpt
new file mode 100644
index 0000000..a38a080
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.rpt
@@ -0,0 +1,62 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.78 0.43 6.83 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.78 0.00 6.83 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.34 0.40 7.23 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.34 0.00 7.23 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.57 7.80 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.80 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.25 0.21 8.01 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.25 0.00 8.01 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.23 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.23 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.72 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.72 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.14 0.23 8.95 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.14 0.00 8.95 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.95 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -8.95 data arrival time
+-----------------------------------------------------------------------------
+ 20.59 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/7-gpl_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.area.rpt
new file mode 100644
index 0000000..7e0ddde
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 17966 u^2 4% utilization.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.clock_skew.rpt
new file mode 100644
index 0000000..50da2ba
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_125_/CLK ^
+ 0.05
+_125_/CLK ^
+ 0.05 0.00 0.00
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.max.rpt
new file mode 100644
index 0000000..f1a9565
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.max.rpt
@@ -0,0 +1,263 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.05 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.26 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.26 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.90 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.22 29.53 library setup time
+ 29.53 data required time
+-----------------------------------------------------------------------------
+ 29.53 data required time
+ -8.90 data arrival time
+-----------------------------------------------------------------------------
+ 20.62 slack (MET)
+
+
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _106_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.21 0.21 8.73 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.21 0.00 8.73 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.23 0.13 8.86 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.23 0.00 8.86 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.86 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.26 29.49 library setup time
+ 29.49 data required time
+-----------------------------------------------------------------------------
+ 29.49 data required time
+ -8.86 data arrival time
+-----------------------------------------------------------------------------
+ 20.63 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _088_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.30 0.24 8.27 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _029_ (net)
+ 0.30 0.00 8.27 v _089_/S (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.11 0.44 8.71 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.00 _030_ (net)
+ 0.11 0.00 8.71 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.31 0.12 8.83 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.31 0.00 8.83 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.83 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.28 29.47 library setup time
+ 29.47 data required time
+-----------------------------------------------------------------------------
+ 29.47 data required time
+ -8.83 data arrival time
+-----------------------------------------------------------------------------
+ 20.64 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.69 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.24 29.51 library setup time
+ 29.51 data required time
+-----------------------------------------------------------------------------
+ 29.51 data required time
+ -8.69 data arrival time
+-----------------------------------------------------------------------------
+ 20.82 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.min.rpt
new file mode 100644
index 0000000..de453d4
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.min.rpt
@@ -0,0 +1,203 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.09 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.09 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.09 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.08 0.33 library hold time
+ 0.33 data required time
+-----------------------------------------------------------------------------
+ 0.33 data required time
+ -1.09 data arrival time
+-----------------------------------------------------------------------------
+ 0.76 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.77 0.77 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 0.77 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 0.97 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 0.97 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 1.10 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 1.10 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.23 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.23 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.35 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.35 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.35 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.35 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.18 1.16 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.16 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.40 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.40 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 1.64 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 1.64 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.64 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -1.64 data arrival time
+-----------------------------------------------------------------------------
+ 1.31 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.20 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.20 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.49 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.49 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 1.67 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 1.67 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.67 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.05 0.30 library hold time
+ 0.30 data required time
+-----------------------------------------------------------------------------
+ 0.30 data required time
+ -1.67 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.20 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.20 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 1.55 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 1.55 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 1.74 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 1.74 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.74 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.74 data arrival time
+-----------------------------------------------------------------------------
+ 1.40 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.power.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.power.rpt
new file mode 100644
index 0000000..37b06d8
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.09e-04 6.56e-06 1.22e-09 1.15e-04 60.4%
+Combinational 3.82e-05 3.72e-05 1.89e-07 7.56e-05 39.6%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.47e-04 4.38e-05 1.90e-07 1.91e-04 100.0%
+ 76.9% 23.0% 0.1%
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.rpt
new file mode 100644
index 0000000..b46f65d
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.rpt
@@ -0,0 +1,59 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.05 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.slew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.worst_slack.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.worst_slack.rpt
new file mode 100644
index 0000000..ddad546
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/placement/8-pl_rsz_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.05
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.76
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.area.rpt
new file mode 100644
index 0000000..e2d8331
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18295 u^2 4% utilization.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.clock_skew.rpt
new file mode 100644
index 0000000..8ef9e5a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_128_/CLK ^
+ 0.55
+_125_/CLK ^
+ 0.50 -0.03 0.02
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.max.rpt
new file mode 100644
index 0000000..f912e16
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.max.rpt
@@ -0,0 +1,276 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.99 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.99 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.73 8.53 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.53 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.77 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.77 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.27 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.27 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.50 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.50 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.50 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.50 data arrival time
+-----------------------------------------------------------------------------
+ 20.52 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.36 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.36 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.30 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.30 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.49 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.49 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 2.74 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net11 (net)
+ 0.29 0.00 2.74 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.20 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.20 ^ io_oeb[1] (out)
+ 3.20 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.20 data arrival time
+-----------------------------------------------------------------------------
+ 20.55 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.36 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.36 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.30 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.30 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.49 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.49 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.23 2.72 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 net10 (net)
+ 0.27 0.00 2.72 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.18 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.18 ^ io_oeb[0] (out)
+ 3.18 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.18 data arrival time
+-----------------------------------------------------------------------------
+ 20.57 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.29 0.86 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_0 (net)
+ 0.29 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.28 0.25 1.66 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.28 0.00 1.66 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.53 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 net12 (net)
+ 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.84 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.84 ^ io_out[0] (out)
+ 2.84 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.84 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.39 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.66 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.13 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.13 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.59 7.71 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.32 8.04 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.04 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.16 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.16 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.29 8.44 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.44 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.70 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.70 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.27 0.21 8.92 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.27 0.00 8.92 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.92 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -8.92 data arrival time
+-----------------------------------------------------------------------------
+ 21.09 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.min.rpt
new file mode 100644
index 0000000..74519ae
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.min.rpt
@@ -0,0 +1,283 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.58 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.58 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.58 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.58 data arrival time
+-----------------------------------------------------------------------------
+ 0.76 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.76 1.25 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 1.25 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 1.46 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.46 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.13 1.58 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.16 0.00 1.58 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.72 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.72 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.12 1.83 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.83 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.20 0.19 1.65 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.20 0.00 1.65 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.90 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.90 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 2.13 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 2.13 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.13 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.06 0.81 library hold time
+ 0.81 data required time
+-----------------------------------------------------------------------------
+ 0.81 data required time
+ -2.13 data arrival time
+-----------------------------------------------------------------------------
+ 1.32 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.69 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.69 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.98 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.98 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 2.15 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 2.15 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.15 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.04 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.15 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.69 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.69 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 2.03 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.03 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 2.23 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 2.23 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.23 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.08 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.23 data arrival time
+-----------------------------------------------------------------------------
+ 1.39 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.power.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.power.rpt
new file mode 100644
index 0000000..b4c119a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 6.62e-06 1.22e-09 1.14e-04 19.6%
+Combinational 3.76e-04 9.26e-05 1.91e-07 4.69e-04 80.4%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.84e-04 9.92e-05 1.92e-07 5.83e-04 100.0%
+ 82.9% 17.0% 0.0%
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.rpt
new file mode 100644
index 0000000..ec2800e
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.rpt
@@ -0,0 +1,67 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.99 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.99 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.73 8.53 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.53 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.77 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.77 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.27 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.27 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.50 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.50 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.50 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.50 data arrival time
+-----------------------------------------------------------------------------
+ 20.52 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.slew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.worst_slack.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.worst_slack.rpt
new file mode 100644
index 0000000..52e4255
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/12-rt_rsz_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.52
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.76
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.clock_skew.rpt
new file mode 100644
index 0000000..29def6e
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 0.55
+_129_/CLK ^
+ 0.50 -0.03 0.02
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.max.rpt
new file mode 100644
index 0000000..2f3ee24
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.max.rpt
@@ -0,0 +1,276 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.12 0.04 6.04 ^ io_in[1] (in)
+ 2 0.00 io_in[1] (net)
+ 0.12 0.00 6.04 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.96 7.00 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 7.00 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.35 0.63 7.63 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 4 0.02 _034_ (net)
+ 0.35 0.00 7.63 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.24 7.87 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 6 0.02 _043_ (net)
+ 0.36 0.00 7.87 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.74 8.61 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.61 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.85 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.85 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.35 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.35 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.15 0.24 9.60 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp2411 (net)
+ 0.15 0.00 9.60 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.60 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.23 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.60 data arrival time
+-----------------------------------------------------------------------------
+ 20.43 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 1.02 1.57 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.57 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.37 0.32 1.89 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.37 0.00 1.89 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.47 2.36 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.36 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.54 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.54 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.32 0.27 2.82 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 net11 (net)
+ 0.32 0.00 2.82 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.47 3.29 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.29 ^ io_oeb[1] (out)
+ 3.29 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.29 data arrival time
+-----------------------------------------------------------------------------
+ 20.46 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 1.02 1.57 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.57 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.37 0.32 1.89 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.37 0.00 1.89 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.47 2.36 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.36 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.54 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.54 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.29 0.24 2.79 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 net10 (net)
+ 0.29 0.00 2.79 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.25 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.25 ^ io_oeb[0] (out)
+ 3.25 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.25 data arrival time
+-----------------------------------------------------------------------------
+ 20.50 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.34 0.89 1.44 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_0 (net)
+ 0.34 0.00 1.44 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.26 1.71 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.29 0.00 1.71 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.54 2.24 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.24 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.24 0.21 2.45 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net12 (net)
+ 0.24 0.00 2.45 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.90 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.90 ^ io_out[0] (out)
+ 2.90 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.90 data arrival time
+-----------------------------------------------------------------------------
+ 20.85 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.12 0.05 6.05 ^ wbs_we_i (in)
+ 2 0.00 wbs_we_i (net)
+ 0.12 0.00 6.05 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.48 0.44 6.48 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.03 net9 (net)
+ 0.48 0.00 6.48 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.28 0.24 6.73 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.28 0.00 6.73 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.36 0.51 7.24 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.03 _004_ (net)
+ 0.36 0.00 7.24 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.60 7.84 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.84 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.32 8.16 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.16 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.28 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.28 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.29 8.57 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.57 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.21 0.28 8.85 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.21 0.00 8.85 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.30 0.24 9.09 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 fsm_plant_opt.tmp3553 (net)
+ 0.30 0.00 9.09 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.09 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -9.09 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.min.rpt
new file mode 100644
index 0000000..b38f70a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.min.rpt
@@ -0,0 +1,283 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.74 1.24 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.28 0.00 1.24 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.29 0.25 1.49 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.29 0.00 1.49 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.17 0.13 1.62 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 fsm_plant_opt.tmp3555 (net)
+ 0.17 0.00 1.62 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.62 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.62 data arrival time
+-----------------------------------------------------------------------------
+ 0.80 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.34 0.78 1.28 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.34 0.00 1.28 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.21 1.49 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.49 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.13 1.62 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.16 0.00 1.62 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.75 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.75 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.88 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 fsm_plant_opt.tmp2410 (net)
+ 0.15 0.00 1.88 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.88 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.88 data arrival time
+-----------------------------------------------------------------------------
+ 1.06 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.74 1.24 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.28 0.00 1.24 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.29 0.25 1.49 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.29 0.00 1.49 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.23 0.21 1.70 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 4 0.01 _048_ (net)
+ 0.23 0.00 1.70 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.26 1.96 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.96 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.21 0.25 2.21 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.21 0.00 2.21 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.21 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.05 0.80 library hold time
+ 0.80 data required time
+-----------------------------------------------------------------------------
+ 0.80 data required time
+ -2.21 data arrival time
+-----------------------------------------------------------------------------
+ 1.41 slack (MET)
+
+
+Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.53 0.91 1.41 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_2 (net)
+ 0.53 0.00 1.41 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.29 0.29 1.70 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.29 0.00 1.70 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 0.21 0.22 1.92 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 1 0.00 _017_ (net)
+ 0.21 0.00 1.92 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.16 0.28 2.19 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.16 0.00 2.19 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.12 2.32 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 fsm_plant_opt.tmp2409 (net)
+ 0.14 0.00 2.32 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.07 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.47 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.74 1.24 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.28 0.00 1.24 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.29 0.25 1.49 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.29 0.00 1.49 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.39 0.27 1.76 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.01 _008_ (net)
+ 0.39 0.00 1.76 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.36 2.12 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.12 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.14 0.21 2.33 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp2411 (net)
+ 0.14 0.00 2.33 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.33 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.07 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.33 data arrival time
+-----------------------------------------------------------------------------
+ 1.49 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.rpt
new file mode 100644
index 0000000..c34bccf
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.rpt
@@ -0,0 +1,67 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.12 0.04 6.04 ^ io_in[1] (in)
+ 2 0.00 io_in[1] (net)
+ 0.12 0.00 6.04 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.96 7.00 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 7.00 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.35 0.63 7.63 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 4 0.02 _034_ (net)
+ 0.35 0.00 7.63 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.24 7.87 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 6 0.02 _043_ (net)
+ 0.36 0.00 7.87 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.74 8.61 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.61 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.85 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.85 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.35 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.35 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.15 0.24 9.60 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp2411 (net)
+ 0.15 0.00 9.60 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.60 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.23 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.60 data arrival time
+-----------------------------------------------------------------------------
+ 20.43 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/16-grt_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/19-wire_lengths.csv b/openlane/user_proj_example/runs/user_proj_example/reports/routing/19-wire_lengths.csv
new file mode 100644
index 0000000..393ced4
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/19-wire_lengths.csv
@@ -0,0 +1,172 @@
+net,length_um
+net8,816.5
+net7,688.78
+net9,448.87
+net10,391.49
+net6,382.58
+net12,374.13
+net11,372.18
+_034_,365.12
+net5,352.14
+_055_,344.5
+fsm_plant_opt.state_temperature_synth_0,241.75
+fsm_plant_opt.state_temperature_synth_2,237.88
+fsm_plant_opt.tmp2410,226.29
+fsm_plant_opt.state_temperature_synth_1,224.29
+fsm_plant_opt.state_water_synth_0,221.91
+fsm_plant_opt.state_water_synth_1,219.81
+fsm_plant_opt.tmp3553,201.65
+fsm_plant_opt.tmp2411,197.17
+fsm_plant_opt.tmp2409,196.61
+fsm_plant_opt.tmp3554,194.66
+fsm_plant_opt.state_water_synth_2,190.89
+fsm_plant_opt.tmp3555,184.34
+_037_,176.13
+_004_,82.93
+_008_,79.57
+_048_,67.91
+_019_,66.74
+_043_,62.98
+_016_,55.46
+_015_,48.13
+_035_,43.12
+_010_,42.61
+_006_,42.56
+net1,40.37
+_012_,38.93
+_031_,37.57
+_005_,35.01
+net4,35.01
+clknet_1_0__leaf_wb_clk_i,34.82
+_002_,34.21
+_000_,32.77
+_011_,29.78
+wb_clk_i,27.64
+_001_,27.49
+_038_,27.44
+_026_,25.25
+_032_,24.69
+io_in[3],24.55
+_014_,23.62
+_017_,23.57
+wbs_sel_i[0],22.92
+_009_,22.74
+net2,22.64
+io_in[2],22.31
+_040_,21.01
+_049_,20.82
+_057_,20.72
+wbs_sel_i[1],20.31
+io_in[0],20.02
+_022_,19.6
+net85,19.51
+io_out[0],19.46
+io_oeb[1],18.9
+wbs_we_i,18.63
+io_oeb[0],18.34
+net13,18.34
+io_in[1],17.78
+wbs_sel_i[2],17.51
+net24,17.22
+net29,17.22
+net34,17.22
+net39,17.22
+net14,17.22
+net44,17.22
+net49,17.22
+net19,17.22
+net59,17.22
+net64,17.22
+net69,17.22
+net74,17.22
+net79,17.22
+net84,17.22
+net54,17.22
+_020_,16.34
+_024_,16.24
+net22,16.1
+net23,16.1
+net25,16.1
+net26,16.1
+net27,16.1
+net28,16.1
+net30,16.1
+net31,16.1
+net32,16.1
+net33,16.1
+net35,16.1
+net36,16.1
+net37,16.1
+net38,16.1
+net40,16.1
+net41,16.1
+net42,16.1
+net43,16.1
+net45,16.1
+net46,16.1
+net47,16.1
+net48,16.1
+net15,16.1
+net16,16.1
+net17,16.1
+net18,16.1
+net20,16.1
+net21,16.1
+net60,16.1
+net61,16.1
+net62,16.1
+net63,16.1
+net65,16.1
+net66,16.1
+net67,16.1
+net68,16.1
+net50,16.1
+net70,16.1
+net71,16.1
+net72,16.1
+net73,16.1
+net75,16.1
+net76,16.1
+net77,16.1
+net78,16.1
+net51,16.1
+net80,16.1
+net81,16.1
+net82,16.1
+net83,16.1
+net52,16.1
+net53,16.1
+net55,16.1
+net56,16.1
+net57,16.1
+net58,16.1
+clknet_0_wb_clk_i,15.68
+wb_rst_i,15.54
+clknet_1_1__leaf_wb_clk_i,15.36
+_003_,15.22
+_041_,14.61
+_025_,14.05
+_027_,14
+_044_,13.44
+_036_,12.93
+_056_,12.93
+net3,12.93
+_028_,12.1
+_033_,11.86
+_042_,11.35
+_046_,11.3
+_054_,8.96
+_030_,8.4
+_045_,8.4
+_013_,7.84
+_029_,6.72
+_052_,6.72
+_023_,5.14
+_050_,4.48
+_039_,4.02
+_053_,3.92
+_051_,3.36
+_018_,2.8
+_021_,2.8
+_047_,2.8
+_007_,2.24
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/drt.drc b/openlane/user_proj_example/runs/user_proj_example/reports/routing/drt.drc
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/drt.drc
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/routing/drt.klayout.xml b/openlane/user_proj_example/runs/user_proj_example/reports/routing/drt.klayout.xml
new file mode 100644
index 0000000..c030035
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/routing/drt.klayout.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>plant_example</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.area.rpt
new file mode 100644
index 0000000..4a7ba55
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18642 u^2 4% utilization.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.clock_skew.rpt
new file mode 100644
index 0000000..d0a8ec5
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 0.56
+_130_/CLK ^
+ 0.51 -0.03 0.02
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.max.rpt
new file mode 100644
index 0000000..abb63eb
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.max.rpt
@@ -0,0 +1,292 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.38 slack (MET)
+
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.14 0.00 6.06 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.15 1.46 7.51 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 2.15 0.02 7.54 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.93 0.64 8.17 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 0.93 0.00 8.18 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.25 0.69 8.87 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.25 0.00 8.87 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.59 0.41 9.28 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.59 0.00 9.28 ^ _113_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.23 0.18 9.46 v _113_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 _051_ (net)
+ 0.23 0.00 9.46 v _115_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.28 0.21 9.68 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.28 0.00 9.68 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.21 0.52 10.20 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.21 0.00 10.20 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.41 0.41 10.61 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.41 0.00 10.61 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.25 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.40 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.91 1.24 1.80 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.91 0.00 1.80 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.51 0.44 2.24 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.51 0.00 2.24 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.78 0.61 2.85 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.78 0.00 2.85 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.20 3.05 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.36 0.00 3.05 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.88 0.64 3.68 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 0.88 0.00 3.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.57 4.26 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.35 0.00 4.26 ^ io_oeb[0] (out)
+ 4.26 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -4.26 data arrival time
+-----------------------------------------------------------------------------
+ 19.49 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.91 1.24 1.80 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.91 0.00 1.80 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.51 0.44 2.24 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.51 0.00 2.24 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.78 0.61 2.85 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.78 0.00 2.85 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.20 3.05 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.36 0.00 3.05 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.84 0.62 3.67 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 0.84 0.00 3.67 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.57 4.24 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.35 0.00 4.24 ^ io_oeb[1] (out)
+ 4.24 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -4.24 data arrival time
+-----------------------------------------------------------------------------
+ 19.51 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.30 0.25 8.80 ^ _065_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _007_ (net)
+ 0.30 0.00 8.80 ^ _066_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.61 0.43 9.23 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.61 0.00 9.23 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.13 0.40 9.63 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _018_ (net)
+ 0.13 0.00 9.63 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.91 0.55 10.18 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.91 0.00 10.18 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.18 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.18 data arrival time
+-----------------------------------------------------------------------------
+ 19.81 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.min.rpt
new file mode 100644
index 0000000..da7a72e
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.min.rpt
@@ -0,0 +1,289 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.28 1.96 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.39 0.00 1.96 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.96 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ 0.00 0.76 library hold time
+ 0.76 data required time
+-----------------------------------------------------------------------------
+ 0.76 data required time
+ -1.96 data arrival time
+-----------------------------------------------------------------------------
+ 1.20 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.42 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.30 0.29 1.70 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.30 0.00 1.70 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.20 0.15 1.85 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.20 0.00 1.85 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.18 0.15 2.00 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.18 0.00 2.00 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.32 2.32 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 0.47 0.00 2.32 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ -0.03 0.73 library hold time
+ 0.73 data required time
+-----------------------------------------------------------------------------
+ 0.73 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.59 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.42 v _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 0.55 0.41 1.82 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 3 0.01 _020_ (net)
+ 0.55 0.00 1.82 ^ _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.18 0.17 1.99 v _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _025_ (net)
+ 0.18 0.00 1.99 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.29 0.22 2.21 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _026_ (net)
+ 0.29 0.00 2.21 ^ _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.11 0.27 2.49 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.01 _030_ (net)
+ 0.11 0.00 2.49 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.41 0.27 2.76 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.41 0.00 2.76 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.76 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ -0.01 0.77 library hold time
+ 0.77 data required time
+-----------------------------------------------------------------------------
+ 0.77 data required time
+ -2.76 data arrival time
+-----------------------------------------------------------------------------
+ 1.99 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.26 0.21 1.90 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.26 0.00 1.90 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.15 2.05 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.16 0.00 2.05 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.18 0.29 2.34 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.18 0.00 2.34 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.64 0.49 2.83 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.64 0.00 2.83 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ 0.04 0.80 library hold time
+ 0.80 data required time
+-----------------------------------------------------------------------------
+ 0.80 data required time
+ -2.83 data arrival time
+-----------------------------------------------------------------------------
+ 2.04 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.60 0.40 2.08 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.60 0.00 2.08 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.14 0.43 2.51 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.14 0.00 2.51 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.39 0.37 2.87 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.39 0.00 2.88 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.88 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ 0.00 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.88 data arrival time
+-----------------------------------------------------------------------------
+ 2.09 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.power.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.power.rpt
new file mode 100644
index 0000000..95aaba7
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 1.52e-05 1.22e-09 1.23e-04 19.3%
+Combinational 3.81e-04 1.32e-04 7.17e-07 5.14e-04 80.7%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.89e-04 1.48e-04 7.18e-07 6.37e-04 100.0%
+ 76.7% 23.2% 0.1%
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.rpt
new file mode 100644
index 0000000..92d4381
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.rpt
@@ -0,0 +1,73 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.38 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.slew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.slew.rpt
new file mode 100644
index 0000000..97b1c40
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.slew.rpt
@@ -0,0 +1,29 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+max fanout
+
+Pin Limit Fanout Slack
+---------------------------------------------------------
+_062_/Z 4 8 -4 (VIOLATED)
+_128_/Q 4 8 -4 (VIOLATED)
+_129_/Q 4 8 -4 (VIOLATED)
+input5/Z 4 8 -4 (VIOLATED)
+input7/Z 4 8 -4 (VIOLATED)
+input8/Z 4 8 -4 (VIOLATED)
+input9/Z 4 8 -4 (VIOLATED)
+_066_/ZN 4 6 -2 (VIOLATED)
+_074_/ZN 4 6 -2 (VIOLATED)
+_104_/ZN 4 6 -2 (VIOLATED)
+_125_/Q 4 6 -2 (VIOLATED)
+_126_/Q 4 6 -2 (VIOLATED)
+_127_/Q 4 6 -2 (VIOLATED)
+_130_/Q 4 6 -2 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 14
+max cap violation count 0
+============================================================================
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.worst_slack.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.worst_slack.rpt
new file mode 100644
index 0000000..3f8d7cf
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/22-rcx_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 19.38
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.20
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/27-plant_example.lvs.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/27-plant_example.lvs.rpt
new file mode 100644
index 0000000..0a843e5
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/27-plant_example.lvs.rpt
@@ -0,0 +1,3 @@
+LVS reports no net, device, pin, or property mismatches.
+
+Total errors = 0
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/29-antenna_violators.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/29-antenna_violators.rpt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/29-antenna_violators.rpt
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.klayout.xml b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.klayout.xml
new file mode 100644
index 0000000..c030035
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.klayout.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>plant_example</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.rdb b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.rdb
new file mode 100644
index 0000000..ec4d746
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.rdb
@@ -0,0 +1 @@
+$plant_example 100
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.rpt
new file mode 100644
index 0000000..f68049a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.rpt
@@ -0,0 +1,5 @@
+plant_example
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.tcl b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.tcl
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.tr b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/drc.tr
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/signoff/spice.feedback.txt b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/spice.feedback.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/signoff/spice.feedback.txt
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis.AREA_0.chk.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis.AREA_0.chk.rpt
new file mode 100644
index 0000000..4d6bcd2
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis.AREA_0.chk.rpt
@@ -0,0 +1,80 @@
+
+19. Executing CHECK pass (checking for obvious problems).
+Checking module plant_example...
+Warning: Wire plant_example.\io_out [37] is used but has no driver.
+Warning: Wire plant_example.\io_out [36] is used but has no driver.
+Warning: Wire plant_example.\io_out [35] is used but has no driver.
+Warning: Wire plant_example.\io_out [34] is used but has no driver.
+Warning: Wire plant_example.\io_out [33] is used but has no driver.
+Warning: Wire plant_example.\io_out [32] is used but has no driver.
+Warning: Wire plant_example.\io_out [31] is used but has no driver.
+Warning: Wire plant_example.\io_out [30] is used but has no driver.
+Warning: Wire plant_example.\io_out [29] is used but has no driver.
+Warning: Wire plant_example.\io_out [28] is used but has no driver.
+Warning: Wire plant_example.\io_out [27] is used but has no driver.
+Warning: Wire plant_example.\io_out [26] is used but has no driver.
+Warning: Wire plant_example.\io_out [25] is used but has no driver.
+Warning: Wire plant_example.\io_out [24] is used but has no driver.
+Warning: Wire plant_example.\io_out [23] is used but has no driver.
+Warning: Wire plant_example.\io_out [22] is used but has no driver.
+Warning: Wire plant_example.\io_out [21] is used but has no driver.
+Warning: Wire plant_example.\io_out [20] is used but has no driver.
+Warning: Wire plant_example.\io_out [19] is used but has no driver.
+Warning: Wire plant_example.\io_out [18] is used but has no driver.
+Warning: Wire plant_example.\io_out [17] is used but has no driver.
+Warning: Wire plant_example.\io_out [16] is used but has no driver.
+Warning: Wire plant_example.\io_out [15] is used but has no driver.
+Warning: Wire plant_example.\io_out [14] is used but has no driver.
+Warning: Wire plant_example.\io_out [13] is used but has no driver.
+Warning: Wire plant_example.\io_out [12] is used but has no driver.
+Warning: Wire plant_example.\io_out [11] is used but has no driver.
+Warning: Wire plant_example.\io_out [10] is used but has no driver.
+Warning: Wire plant_example.\io_out [9] is used but has no driver.
+Warning: Wire plant_example.\io_out [8] is used but has no driver.
+Warning: Wire plant_example.\io_out [7] is used but has no driver.
+Warning: Wire plant_example.\io_out [6] is used but has no driver.
+Warning: Wire plant_example.\io_out [5] is used but has no driver.
+Warning: Wire plant_example.\io_out [4] is used but has no driver.
+Warning: Wire plant_example.\io_out [3] is used but has no driver.
+Warning: Wire plant_example.\io_out [2] is used but has no driver.
+Warning: Wire plant_example.\io_out [1] is used but has no driver.
+Warning: Wire plant_example.\io_out [0] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [37] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [36] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [35] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [34] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [33] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [32] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [31] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [30] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [29] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [28] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [27] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [26] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [25] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [24] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [23] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [22] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [21] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [20] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [19] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [18] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [17] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [16] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [15] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [14] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [13] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [12] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [11] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [10] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [9] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [8] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [7] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [6] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [5] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [4] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [3] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [2] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [1] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [0] is used but has no driver.
+Found and reported 76 problems.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis.AREA_0.stat.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis.AREA_0.stat.rpt
new file mode 100644
index 0000000..f1ecc0a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis.AREA_0.stat.rpt
@@ -0,0 +1,37 @@
+
+20. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 77
+ Number of wire bits: 191
+ Number of public wires: 19
+ Number of public wire bits: 133
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 146
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 3
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 2
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 4
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 6
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 2
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 6
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 6
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 6
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 2
+ gf180mcu_fd_sc_mcu7t5v0__mux2_2 1
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 12
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 3
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 1
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 6
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 1
+ gf180mcu_fd_sc_mcu7t5v0__nor4_1 3
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 1
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 5
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 2
+ gf180mcu_fd_sc_mcu7t5v0__or3_1 1
+ gf180mcu_fd_sc_mcu7t5v0__tiel 73
+
+ Chip area for module '\plant_example': 2070.073600
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis_dff.stat b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis_dff.stat
new file mode 100644
index 0000000..f411484
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis_dff.stat
@@ -0,0 +1,24 @@
+
+12. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 223
+ Number of wire bits: 337
+ Number of public wires: 22
+ Number of public wire bits: 136
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 216
+ $_ANDNOT_ 56
+ $_AND_ 6
+ $_MUX_ 21
+ $_NAND_ 6
+ $_NOR_ 19
+ $_NOT_ 6
+ $_ORNOT_ 19
+ $_OR_ 76
+ $_XNOR_ 1
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 6
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis_pre.stat b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis_pre.stat
new file mode 100644
index 0000000..3ec1808
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/1-synthesis_pre.stat
@@ -0,0 +1,24 @@
+
+10. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 223
+ Number of wire bits: 337
+ Number of public wires: 22
+ Number of public wire bits: 136
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 216
+ $_ANDNOT_ 56
+ $_AND_ 6
+ $_DFF_P_ 6
+ $_MUX_ 21
+ $_NAND_ 6
+ $_NOR_ 19
+ $_NOT_ 6
+ $_ORNOT_ 19
+ $_OR_ 76
+ $_XNOR_ 1
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.area.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.area.rpt
new file mode 100644
index 0000000..3881add
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 2070 u^2 100% utilization.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.clock_skew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.clock_skew.rpt
new file mode 100644
index 0000000..50da2ba
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_125_/CLK ^
+ 0.05
+_125_/CLK ^
+ 0.05 0.00 0.00
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.max.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.max.rpt
new file mode 100644
index 0000000..11312d5
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.max.rpt
@@ -0,0 +1,240 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.85 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.20 29.55 library setup time
+ 29.55 data required time
+-----------------------------------------------------------------------------
+ 29.55 data required time
+ -8.85 data arrival time
+-----------------------------------------------------------------------------
+ 20.70 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.71 v _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 1.02 0.57 7.28 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 3 0.01 _020_ (net)
+ 1.02 0.00 7.28 ^ _079_/A3 (gf180mcu_fd_sc_mcu7t5v0__and3_1)
+ 0.19 0.44 7.71 ^ _079_/Z (gf180mcu_fd_sc_mcu7t5v0__and3_1)
+ 1 0.00 _021_ (net)
+ 0.19 0.00 7.71 ^ _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.13 7.84 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _026_ (net)
+ 0.19 0.00 7.84 v _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.13 0.39 8.23 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.00 _030_ (net)
+ 0.13 0.00 8.23 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.27 0.19 8.42 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.27 0.00 8.42 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.42 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.23 29.52 library setup time
+ 29.52 data required time
+-----------------------------------------------------------------------------
+ 29.52 data required time
+ -8.42 data arrival time
+-----------------------------------------------------------------------------
+ 21.11 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 1.74 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1.40 0.90 2.63 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.07 io_oeb[0] (net)
+ 1.40 0.00 2.63 ^ io_oeb[0] (out)
+ 2.63 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.63 data arrival time
+-----------------------------------------------------------------------------
+ 21.12 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.71 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.54 7.25 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.25 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.43 0.32 7.57 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.43 0.00 7.57 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 7.69 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 7.69 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.28 7.96 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 7.96 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.13 0.27 8.23 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.13 0.00 8.23 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.20 0.16 8.39 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.20 0.00 8.39 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.39 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.22 29.53 library setup time
+ 29.53 data required time
+-----------------------------------------------------------------------------
+ 29.53 data required time
+ -8.39 data arrival time
+-----------------------------------------------------------------------------
+ 21.14 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 1.74 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 1.33 0.87 2.61 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 2 0.08 io_oeb[1] (net)
+ 1.33 0.00 2.61 ^ io_oeb[1] (out)
+ 2.61 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.61 data arrival time
+-----------------------------------------------------------------------------
+ 21.14 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.min.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.min.rpt
new file mode 100644
index 0000000..e593aa6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.min.rpt
@@ -0,0 +1,203 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_2 (net)
+ 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.46 0.00 1.01 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.09 1.11 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.14 0.00 1.11 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.11 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.11 data arrival time
+-----------------------------------------------------------------------------
+ 0.77 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.19 0.00 0.68 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.22 0.17 0.85 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.00 _033_ (net)
+ 0.22 0.00 0.85 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 0.97 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 0.97 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.10 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.10 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.11 0.09 1.19 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.11 0.00 1.19 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.19 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.19 data arrival time
+-----------------------------------------------------------------------------
+ 0.85 slack (MET)
+
+
+Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.24 0.76 0.76 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_2 (net)
+ 0.24 0.00 0.76 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.29 0.23 0.99 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.29 0.00 0.99 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 0.19 0.22 1.21 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 1 0.00 _017_ (net)
+ 0.19 0.00 1.21 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.16 0.28 1.48 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.16 0.00 1.48 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.10 0.09 1.57 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.10 0.00 1.57 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.10 0.35 library hold time
+ 0.35 data required time
+-----------------------------------------------------------------------------
+ 0.35 data required time
+ -1.57 data arrival time
+-----------------------------------------------------------------------------
+ 1.23 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_2 (net)
+ 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.46 0.00 1.01 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.19 1.21 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.21 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.24 1.45 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 1.45 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.13 0.24 1.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.13 0.00 1.69 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.69 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.69 data arrival time
+-----------------------------------------------------------------------------
+ 1.35 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_2 (net)
+ 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.46 0.00 1.01 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.31 0.23 1.25 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.31 0.00 1.25 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.11 0.33 1.58 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.11 0.00 1.58 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.09 0.21 1.80 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.09 0.00 1.80 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.80 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.10 0.35 library hold time
+ 0.35 data required time
+-----------------------------------------------------------------------------
+ 0.35 data required time
+ -1.80 data arrival time
+-----------------------------------------------------------------------------
+ 1.45 slack (MET)
+
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.power.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.power.rpt
new file mode 100644
index 0000000..aad92f1
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.09e-04 4.05e-06 1.22e-09 1.13e-04 69.1%
+Combinational 2.28e-05 2.75e-05 1.09e-08 5.04e-05 30.9%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.31e-04 3.16e-05 1.21e-08 1.63e-04 100.0%
+ 80.6% 19.4% 0.0%
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.rpt
new file mode 100644
index 0000000..5f34e03
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.rpt
@@ -0,0 +1,62 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.85 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.20 29.55 library setup time
+ 29.55 data required time
+-----------------------------------------------------------------------------
+ 29.55 data required time
+ -8.85 data arrival time
+-----------------------------------------------------------------------------
+ 20.70 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.slew.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.tns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.wns.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.worst_slack.rpt b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.worst_slack.rpt
new file mode 100644
index 0000000..15e44c2
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/reports/synthesis/2-syn_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.70
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.77
