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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-039 / 35bad51b40f45fba85a97d3a7af94316e1c8ff12 / . / openlane / user_proj_example / runs / user_proj_example / reports / synthesis / 2-syn_sta.max.rpt
blob: 11312d5730aa8a9b59934ce16eb49e14525bfe35 [file] [log] [blame]
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.33 0.17 6.17 ^ wbs_we_i (in)
4 0.02 wbs_we_i (net)
0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
2 0.01 _014_ (net)
0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 _015_ (net)
0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
2 0.01 _036_ (net)
0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _052_ (net)
0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _053_ (net)
0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
1 0.00 _054_ (net)
0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1 0.00 fsm_plant_opt.tmp2411 (net)
0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.85 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.20 29.55 library setup time
29.55 data required time
-----------------------------------------------------------------------------
29.55 data required time
-8.85 data arrival time
-----------------------------------------------------------------------------
20.70 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.33 0.17 6.17 ^ wbs_we_i (in)
4 0.02 wbs_we_i (net)
0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 _004_ (net)
0.21 0.00 6.71 v _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
1.02 0.57 7.28 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
3 0.01 _020_ (net)
1.02 0.00 7.28 ^ _079_/A3 (gf180mcu_fd_sc_mcu7t5v0__and3_1)
0.19 0.44 7.71 ^ _079_/Z (gf180mcu_fd_sc_mcu7t5v0__and3_1)
1 0.00 _021_ (net)
0.19 0.00 7.71 ^ _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.19 0.13 7.84 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _026_ (net)
0.19 0.00 7.84 v _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
0.13 0.39 8.23 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
1 0.00 _030_ (net)
0.13 0.00 8.23 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.27 0.19 8.42 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 fsm_plant_opt.tmp2409 (net)
0.27 0.00 8.42 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.42 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.23 29.52 library setup time
29.52 data required time
-----------------------------------------------------------------------------
29.52 data required time
-8.42 data arrival time
-----------------------------------------------------------------------------
21.11 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _011_ (net)
0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4 0.02 _012_ (net)
0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _028_ (net)
0.27 0.00 1.74 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1.40 0.90 2.63 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.07 io_oeb[0] (net)
1.40 0.00 2.63 ^ io_oeb[0] (out)
2.63 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-2.63 data arrival time
-----------------------------------------------------------------------------
21.12 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.33 0.17 6.17 ^ wbs_we_i (in)
4 0.02 wbs_we_i (net)
0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 _004_ (net)
0.21 0.00 6.71 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.29 0.54 7.25 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.29 0.00 7.25 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.43 0.32 7.57 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.43 0.00 7.57 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.17 0.12 7.69 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _056_ (net)
0.17 0.00 7.69 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
0.10 0.28 7.96 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
1 0.00 _057_ (net)
0.10 0.00 7.96 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.13 0.27 8.23 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2 0.01 fsm_plant_opt.tmp3554 (net)
0.13 0.00 8.23 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.20 0.16 8.39 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 fsm_plant_opt.tmp3553 (net)
0.20 0.00 8.39 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.39 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.22 29.53 library setup time
29.53 data required time
-----------------------------------------------------------------------------
29.53 data required time
-8.39 data arrival time
-----------------------------------------------------------------------------
21.14 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _011_ (net)
0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4 0.02 _012_ (net)
0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _028_ (net)
0.27 0.00 1.74 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1)
1.33 0.87 2.61 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1)
2 0.08 io_oeb[1] (net)
1.33 0.00 2.61 ^ io_oeb[1] (out)
2.61 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-2.61 data arrival time
-----------------------------------------------------------------------------
21.14 slack (MET)