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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-039 / 35bad51b40f45fba85a97d3a7af94316e1c8ff12 / . / openlane / user_proj_example / runs / user_proj_example / reports / placement / 7-gpl_sta.max.rpt
blob: a27581646cc96edc678b3cd234dc8fe76b4b0d67 [file] [log] [blame]
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.39 0.22 6.22 ^ wbs_we_i (in)
4 0.02 wbs_we_i (net)
0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.21 0.00 6.40 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
0.78 0.43 6.83 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
2 0.01 _014_ (net)
0.78 0.00 6.83 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.34 0.40 7.23 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 _015_ (net)
0.34 0.00 7.23 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.27 0.57 7.80 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
2 0.01 _036_ (net)
0.27 0.00 7.80 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.25 0.21 8.01 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 _052_ (net)
0.25 0.00 8.01 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.27 0.21 8.23 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _053_ (net)
0.27 0.00 8.23 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.17 0.49 8.72 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
1 0.00 _054_ (net)
0.17 0.00 8.72 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.14 0.23 8.95 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1 0.00 fsm_plant_opt.tmp2411 (net)
0.14 0.00 8.95 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.95 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.21 29.54 library setup time
29.54 data required time
-----------------------------------------------------------------------------
29.54 data required time
-8.95 data arrival time
-----------------------------------------------------------------------------
20.59 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.39 0.22 6.22 ^ wbs_we_i (in)
4 0.02 wbs_we_i (net)
0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.21 0.00 6.40 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.21 0.37 6.77 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 _004_ (net)
0.21 0.00 6.77 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.29 0.55 7.32 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.29 0.00 7.32 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.44 0.32 7.65 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.44 0.00 7.65 ^ _088_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.46 0.24 7.89 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _029_ (net)
0.46 0.00 7.89 v _089_/S (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
0.13 0.42 8.31 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
1 0.00 _030_ (net)
0.13 0.00 8.31 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.33 0.23 8.54 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 fsm_plant_opt.tmp2409 (net)
0.33 0.00 8.54 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.54 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.23 29.52 library setup time
29.52 data required time
-----------------------------------------------------------------------------
29.52 data required time
-8.54 data arrival time
-----------------------------------------------------------------------------
20.98 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.39 0.22 6.22 ^ wbs_we_i (in)
4 0.02 wbs_we_i (net)
0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.21 0.00 6.40 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.21 0.37 6.77 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 _004_ (net)
0.21 0.00 6.77 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.29 0.55 7.32 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.29 0.00 7.32 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.44 0.32 7.65 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.44 0.00 7.65 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.17 0.12 7.76 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _056_ (net)
0.17 0.00 7.76 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
0.10 0.28 8.04 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
1 0.00 _057_ (net)
0.10 0.00 8.04 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.15 0.29 8.33 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2 0.01 fsm_plant_opt.tmp3554 (net)
0.15 0.00 8.33 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.25 0.20 8.53 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 fsm_plant_opt.tmp3553 (net)
0.25 0.00 8.53 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.53 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.22 29.53 library setup time
29.53 data required time
-----------------------------------------------------------------------------
29.53 data required time
-8.53 data arrival time
-----------------------------------------------------------------------------
21.00 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.30 0.88 0.88 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
0.30 0.00 0.88 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.31 0.27 1.14 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _011_ (net)
0.31 0.00 1.14 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.61 0.44 1.59 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4 0.02 _012_ (net)
0.61 0.00 1.59 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.28 0.19 1.78 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _028_ (net)
0.28 0.00 1.78 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1.43 0.94 2.72 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.07 io_oeb[0] (net)
1.43 0.01 2.73 ^ io_oeb[0] (out)
2.73 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-2.73 data arrival time
-----------------------------------------------------------------------------
21.02 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.30 0.88 0.88 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
0.30 0.00 0.88 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.31 0.27 1.14 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _011_ (net)
0.31 0.00 1.14 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.61 0.44 1.59 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4 0.02 _012_ (net)
0.61 0.00 1.59 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.28 0.19 1.78 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _028_ (net)
0.28 0.00 1.78 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1)
1.36 0.91 2.69 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1)
2 0.08 io_oeb[1] (net)
1.36 0.01 2.70 ^ io_oeb[1] (out)
2.70 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-2.70 data arrival time
-----------------------------------------------------------------------------
21.05 slack (MET)