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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-039 / 35bad51b40f45fba85a97d3a7af94316e1c8ff12 / . / openlane / user_proj_example / runs / user_proj_example / reports / signoff / 22-rcx_sta.min.rpt
blob: da7a72e8a6c32f5afaca09d0f78dfd9a62883139 [file] [log] [blame]
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.06 0.06 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.04 fsm_plant_opt.state_water_synth_2 (net)
0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
4 0.02 _002_ (net)
0.34 0.00 1.68 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.39 0.28 1.96 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 fsm_plant_opt.tmp3555 (net)
0.39 0.00 1.96 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.96 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.56 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.81 clock uncertainty
-0.05 0.76 clock reconvergence pessimism
0.00 0.76 library hold time
0.76 data required time
-----------------------------------------------------------------------------
0.76 data required time
-1.96 data arrival time
-----------------------------------------------------------------------------
1.20 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.06 0.06 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
0.55 0.00 1.42 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
0.30 0.29 1.70 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
1 0.01 _033_ (net)
0.30 0.00 1.70 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.20 0.15 1.85 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _041_ (net)
0.20 0.00 1.85 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.18 0.15 2.00 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _045_ (net)
0.18 0.00 2.00 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.47 0.32 2.32 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.03 fsm_plant_opt.tmp2410 (net)
0.47 0.00 2.32 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.32 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.81 clock uncertainty
-0.05 0.76 clock reconvergence pessimism
-0.03 0.73 library hold time
0.73 data required time
-----------------------------------------------------------------------------
0.73 data required time
-2.32 data arrival time
-----------------------------------------------------------------------------
1.59 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.06 0.06 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
0.55 0.00 1.42 v _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
0.55 0.41 1.82 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
3 0.01 _020_ (net)
0.55 0.00 1.82 ^ _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.18 0.17 1.99 v _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _025_ (net)
0.18 0.00 1.99 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.29 0.22 2.21 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _026_ (net)
0.29 0.00 2.21 ^ _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
0.11 0.27 2.49 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
1 0.01 _030_ (net)
0.11 0.00 2.49 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.41 0.27 2.76 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 fsm_plant_opt.tmp2409 (net)
0.41 0.00 2.76 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.76 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.56 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.81 clock uncertainty
-0.03 0.78 clock reconvergence pessimism
-0.01 0.77 library hold time
0.77 data required time
-----------------------------------------------------------------------------
0.77 data required time
-2.76 data arrival time
-----------------------------------------------------------------------------
1.99 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.06 0.06 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.04 fsm_plant_opt.state_water_synth_2 (net)
0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
4 0.02 _002_ (net)
0.34 0.00 1.68 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.26 0.21 1.90 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.26 0.00 1.90 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.16 0.15 2.05 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _056_ (net)
0.16 0.00 2.05 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
0.18 0.29 2.34 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
1 0.01 _057_ (net)
0.18 0.00 2.34 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.64 0.49 2.83 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.04 fsm_plant_opt.tmp3554 (net)
0.64 0.00 2.83 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.83 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.56 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.81 clock uncertainty
-0.05 0.76 clock reconvergence pessimism
0.04 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-2.83 data arrival time
-----------------------------------------------------------------------------
2.04 slack (MET)
Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.06 0.06 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.04 fsm_plant_opt.state_water_synth_2 (net)
0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
4 0.02 _002_ (net)
0.34 0.00 1.68 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
0.60 0.40 2.08 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
6 0.03 _008_ (net)
0.60 0.00 2.08 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.14 0.43 2.51 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
1 0.01 _054_ (net)
0.14 0.00 2.51 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.39 0.37 2.87 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
2 0.02 fsm_plant_opt.tmp2411 (net)
0.39 0.00 2.88 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.88 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.14 0.07 0.07 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.56 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.81 clock uncertainty
-0.03 0.78 clock reconvergence pessimism
0.00 0.78 library hold time
0.78 data required time
-----------------------------------------------------------------------------
0.78 data required time
-2.88 data arrival time
-----------------------------------------------------------------------------
2.09 slack (MET)