| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: io_in[1] (input port clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 6.00 6.00 ^ input external delay |
| 0.10 0.03 6.03 ^ io_in[1] (in) |
| 1 0.00 io_in[1] (net) |
| 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1) |
| 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1) |
| 2 0.01 net2 (net) |
| 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 2 0.01 _034_ (net) |
| 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 3 0.01 _043_ (net) |
| 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1) |
| 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1) |
| 2 0.01 _044_ (net) |
| 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _053_ (net) |
| 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 1 0.00 _054_ (net) |
| 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 1 0.00 fsm_plant_opt.tmp2411 (net) |
| 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 9.49 data arrival time |
| |
| 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock source latency |
| 0.13 0.05 30.05 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 3 0.01 clknet_1_0__leaf_wb_clk_i (net) |
| 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 30.25 clock uncertainty |
| 0.00 30.25 clock reconvergence pessimism |
| -0.22 30.02 library setup time |
| 30.02 data required time |
| ----------------------------------------------------------------------------- |
| 30.02 data required time |
| -9.49 data arrival time |
| ----------------------------------------------------------------------------- |
| 20.53 slack (MET) |
| |
| |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_oeb[1] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 3 0.01 clknet_1_0__leaf_wb_clk_i (net) |
| 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net) |
| 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _011_ (net) |
| 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4 0.02 _012_ (net) |
| 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 2 0.01 _028_ (net) |
| 0.27 0.00 2.48 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.29 0.25 2.73 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 net11 (net) |
| 0.29 0.00 2.73 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.33 0.46 3.19 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_oeb[1] (net) |
| 0.33 0.00 3.19 ^ io_oeb[1] (out) |
| 3.19 data arrival time |
| |
| 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (propagated) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| -6.00 23.75 output external delay |
| 23.75 data required time |
| ----------------------------------------------------------------------------- |
| 23.75 data required time |
| -3.19 data arrival time |
| ----------------------------------------------------------------------------- |
| 20.56 slack (MET) |
| |
| |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_oeb[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 3 0.01 clknet_1_0__leaf_wb_clk_i (net) |
| 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net) |
| 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _011_ (net) |
| 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4 0.02 _012_ (net) |
| 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 2 0.01 _028_ (net) |
| 0.27 0.00 2.48 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.27 0.23 2.71 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.01 net10 (net) |
| 0.27 0.00 2.71 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.33 0.46 3.17 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_oeb[0] (net) |
| 0.33 0.00 3.17 ^ io_oeb[0] (out) |
| 3.17 data arrival time |
| |
| 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (propagated) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| -6.00 23.75 output external delay |
| 23.75 data required time |
| ----------------------------------------------------------------------------- |
| 23.75 data required time |
| -3.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 20.58 slack (MET) |
| |
| |
| Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.13 0.06 0.06 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 3 0.01 clknet_1_0__leaf_wb_clk_i (net) |
| 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.28 0.85 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_water_synth_0 (net) |
| 0.28 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.29 0.25 1.65 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 3 0.01 _000_ (net) |
| 0.29 0.00 1.65 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 0.25 0.54 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 3 0.01 _001_ (net) |
| 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 1 0.01 net12 (net) |
| 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 0.33 0.45 2.83 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3) |
| 1 0.07 io_out[0] (net) |
| 0.33 0.00 2.84 ^ io_out[0] (out) |
| 2.84 data arrival time |
| |
| 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (propagated) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| -6.00 23.75 output external delay |
| 23.75 data required time |
| ----------------------------------------------------------------------------- |
| 23.75 data required time |
| -2.84 data arrival time |
| ----------------------------------------------------------------------------- |
| 20.91 slack (MET) |
| |
| |
| Startpoint: wbs_we_i (input port clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 6.00 6.00 ^ input external delay |
| 0.10 0.03 6.03 ^ wbs_we_i (in) |
| 1 0.00 wbs_we_i (net) |
| 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 net9 (net) |
| 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 _003_ (net) |
| 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.03 _004_ (net) |
| 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 4 0.02 _005_ (net) |
| 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.01 _027_ (net) |
| 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.00 _056_ (net) |
| 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.00 _057_ (net) |
| 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 2 0.01 fsm_plant_opt.tmp3554 (net) |
| 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.27 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 fsm_plant_opt.tmp3553 (net) |
| 0.27 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 8.90 data arrival time |
| |
| 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock source latency |
| 0.13 0.05 30.05 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 3 0.01 clknet_1_0__leaf_wb_clk_i (net) |
| 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 30.25 clock uncertainty |
| 0.00 30.25 clock reconvergence pessimism |
| -0.24 30.00 library setup time |
| 30.00 data required time |
| ----------------------------------------------------------------------------- |
| 30.00 data required time |
| -8.90 data arrival time |
| ----------------------------------------------------------------------------- |
| 21.10 slack (MET) |
| |
| |
