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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-039 / 35bad51b40f45fba85a97d3a7af94316e1c8ff12 / . / openlane / user_proj_example / runs / user_proj_example / reports / routing / 16-grt_sta.max.rpt
blob: 2f3ee242f7bebab2e8b43bb07def679214fe180b [file] [log] [blame]
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: io_in[1] (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
6.00 6.00 ^ input external delay
0.12 0.04 6.04 ^ io_in[1] (in)
2 0.00 io_in[1] (net)
0.12 0.00 6.04 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
0.21 0.96 7.00 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
2 0.01 net2 (net)
0.21 0.00 7.00 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.35 0.63 7.63 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
4 0.02 _034_ (net)
0.35 0.00 7.63 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.36 0.24 7.87 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
6 0.02 _043_ (net)
0.36 0.00 7.87 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
0.29 0.74 8.61 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
2 0.01 _044_ (net)
0.29 0.00 8.61 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.27 0.24 8.85 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _053_ (net)
0.27 0.00 8.85 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.19 0.50 9.35 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
1 0.00 _054_ (net)
0.19 0.00 9.35 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.15 0.24 9.60 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
2 0.01 fsm_plant_opt.tmp2411 (net)
0.15 0.00 9.60 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.60 data arrival time
30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock source latency
0.13 0.06 30.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 30.25 clock uncertainty
0.00 30.25 clock reconvergence pessimism
-0.23 30.02 library setup time
30.02 data required time
-----------------------------------------------------------------------------
30.02 data required time
-9.60 data arrival time
-----------------------------------------------------------------------------
20.43 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.55 1.02 1.57 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
0.55 0.00 1.57 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.37 0.32 1.89 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _011_ (net)
0.37 0.00 1.89 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.62 0.47 2.36 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4 0.02 _012_ (net)
0.62 0.00 2.36 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.27 0.18 2.54 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _028_ (net)
0.27 0.00 2.54 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.32 0.27 2.82 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 net11 (net)
0.32 0.00 2.82 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.33 0.47 3.29 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_oeb[1] (net)
0.33 0.00 3.29 ^ io_oeb[1] (out)
3.29 data arrival time
30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (propagated)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-3.29 data arrival time
-----------------------------------------------------------------------------
20.46 slack (MET)
Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.55 1.02 1.57 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
0.55 0.00 1.57 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.37 0.32 1.89 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
4 0.02 _011_ (net)
0.37 0.00 1.89 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.62 0.47 2.36 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4 0.02 _012_ (net)
0.62 0.00 2.36 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.27 0.18 2.54 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _028_ (net)
0.27 0.00 2.54 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.29 0.24 2.79 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 net10 (net)
0.29 0.00 2.79 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.33 0.46 3.25 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_oeb[0] (net)
0.33 0.00 3.25 ^ io_oeb[0] (out)
3.25 data arrival time
30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (propagated)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-3.25 data arrival time
-----------------------------------------------------------------------------
20.50 slack (MET)
Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.13 0.06 0.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.34 0.89 1.44 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.02 fsm_plant_opt.state_water_synth_0 (net)
0.34 0.00 1.44 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.29 0.26 1.71 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
3 0.01 _000_ (net)
0.29 0.00 1.71 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.25 0.54 2.24 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
3 0.01 _001_ (net)
0.25 0.00 2.24 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.24 0.21 2.45 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 net12 (net)
0.24 0.00 2.45 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
0.33 0.45 2.90 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
1 0.07 io_out[0] (net)
0.33 0.00 2.90 ^ io_out[0] (out)
2.90 data arrival time
30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (propagated)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
-6.00 23.75 output external delay
23.75 data required time
-----------------------------------------------------------------------------
23.75 data required time
-2.90 data arrival time
-----------------------------------------------------------------------------
20.85 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
6.00 6.00 ^ input external delay
0.12 0.05 6.05 ^ wbs_we_i (in)
2 0.00 wbs_we_i (net)
0.12 0.00 6.05 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.48 0.44 6.48 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.03 net9 (net)
0.48 0.00 6.48 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.28 0.24 6.73 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.28 0.00 6.73 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.36 0.51 7.24 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
8 0.03 _004_ (net)
0.36 0.00 7.24 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.29 0.60 7.84 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.29 0.00 7.84 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.42 0.32 8.16 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.42 0.00 8.16 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.17 0.12 8.28 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _056_ (net)
0.17 0.00 8.28 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
0.11 0.29 8.57 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
1 0.00 _057_ (net)
0.11 0.00 8.57 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.21 0.28 8.85 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
4 0.01 fsm_plant_opt.tmp3554 (net)
0.21 0.00 8.85 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.30 0.24 9.09 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 fsm_plant_opt.tmp3553 (net)
0.30 0.00 9.09 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.09 data arrival time
30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock source latency
0.13 0.06 30.06 ^ wb_clk_i (in)
2 0.02 wb_clk_i (net)
0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
3 0.01 clknet_1_0__leaf_wb_clk_i (net)
0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 30.25 clock uncertainty
0.00 30.25 clock reconvergence pessimism
-0.24 30.01 library setup time
30.01 data required time
-----------------------------------------------------------------------------
30.01 data required time
-9.09 data arrival time
-----------------------------------------------------------------------------
20.91 slack (MET)