| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.02 fsm_plant_opt.state_water_synth_2 (net) |
| 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 4 0.02 _002_ (net) |
| 0.47 0.00 1.04 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.16 0.12 1.15 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp3555 (net) |
| 0.16 0.00 1.15 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.15 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.08 0.33 library hold time |
| 0.33 data required time |
| ----------------------------------------------------------------------------- |
| 0.33 data required time |
| -1.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.83 slack (MET) |
| |
| |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.20 0.69 0.69 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net) |
| 0.20 0.00 0.70 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1) |
| 0.22 0.17 0.87 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1) |
| 1 0.01 _033_ (net) |
| 0.22 0.00 0.87 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.16 0.12 0.99 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _041_ (net) |
| 0.16 0.00 0.99 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.16 0.13 1.12 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.00 _045_ (net) |
| 0.16 0.00 1.12 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.14 0.11 1.24 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp2410 (net) |
| 0.14 0.00 1.24 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.24 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.09 0.34 library hold time |
| 0.34 data required time |
| ----------------------------------------------------------------------------- |
| 0.34 data required time |
| -1.24 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.90 slack (MET) |
| |
| |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.27 0.78 0.78 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_temperature_synth_2 (net) |
| 0.27 0.00 0.78 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.28 0.24 1.02 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4 0.02 _012_ (net) |
| 0.28 0.00 1.02 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1) |
| 0.20 0.22 1.24 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1) |
| 1 0.00 _017_ (net) |
| 0.20 0.00 1.24 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.16 0.28 1.52 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.00 _018_ (net) |
| 0.16 0.00 1.52 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.13 0.11 1.63 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp2409 (net) |
| 0.13 0.00 1.63 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.63 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.09 0.34 library hold time |
| 0.34 data required time |
| ----------------------------------------------------------------------------- |
| 0.34 data required time |
| -1.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.29 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.02 fsm_plant_opt.state_water_synth_2 (net) |
| 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 4 0.02 _002_ (net) |
| 0.47 0.00 1.04 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.19 0.20 1.24 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 2 0.01 _048_ (net) |
| 0.19 0.00 1.24 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.10 0.24 1.48 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.00 _057_ (net) |
| 0.10 0.00 1.48 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.15 0.26 1.74 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.01 fsm_plant_opt.tmp3554 (net) |
| 0.15 0.00 1.74 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.74 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.08 0.33 library hold time |
| 0.33 data required time |
| ----------------------------------------------------------------------------- |
| 0.33 data required time |
| -1.74 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.41 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.02 fsm_plant_opt.state_water_synth_2 (net) |
| 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 4 0.02 _002_ (net) |
| 0.47 0.00 1.04 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.32 0.24 1.28 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 3 0.01 _008_ (net) |
| 0.32 0.00 1.28 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.11 0.34 1.62 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 1 0.00 _054_ (net) |
| 0.11 0.00 1.62 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.11 0.23 1.85 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 1 0.00 fsm_plant_opt.tmp2411 (net) |
| 0.11 0.00 1.85 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.85 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.09 0.34 library hold time |
| 0.34 data required time |
| ----------------------------------------------------------------------------- |
| 0.34 data required time |
| -1.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.51 slack (MET) |
| |
| |