Google Git
Sign in
foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-039 / 35bad51b40f45fba85a97d3a7af94316e1c8ff12 / . / openlane / user_proj_example / runs / user_proj_example / reports / placement / 8-pl_rsz_sta.max.rpt
blob: f1a95656f37fd83fc26ae2da9f44a70814e92088 [file] [log] [blame]
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: io_in[1] (input port clocked by wb_clk_i)
Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.10 0.03 6.03 ^ io_in[1] (in)
1 0.00 io_in[1] (net)
0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
2 0.01 net2 (net)
0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
2 0.01 _034_ (net)
0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
3 0.01 _043_ (net)
0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
2 0.01 _044_ (net)
0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _053_ (net)
0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
1 0.00 _054_ (net)
0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
1 0.00 fsm_plant_opt.tmp2411 (net)
0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.49 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.21 29.54 library setup time
29.54 data required time
-----------------------------------------------------------------------------
29.54 data required time
-9.49 data arrival time
-----------------------------------------------------------------------------
20.05 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.10 0.03 6.03 ^ wbs_we_i (in)
1 0.00 wbs_we_i (net)
0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 net9 (net)
0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.03 _004_ (net)
0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _056_ (net)
0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
1 0.00 _057_ (net)
0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
2 0.01 fsm_plant_opt.tmp3554 (net)
0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.26 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1 0.00 fsm_plant_opt.tmp3553 (net)
0.26 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.90 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.22 29.53 library setup time
29.53 data required time
-----------------------------------------------------------------------------
29.53 data required time
-8.90 data arrival time
-----------------------------------------------------------------------------
20.62 slack (MET)
Startpoint: io_in[1] (input port clocked by wb_clk_i)
Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.10 0.03 6.03 ^ io_in[1] (in)
1 0.00 io_in[1] (net)
0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
2 0.01 net2 (net)
0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
2 0.01 _034_ (net)
0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
3 0.01 _043_ (net)
0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
2 0.01 _044_ (net)
0.28 0.00 8.52 v _106_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.21 0.21 8.73 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _045_ (net)
0.21 0.00 8.73 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.23 0.13 8.86 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 fsm_plant_opt.tmp2410 (net)
0.23 0.00 8.86 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.86 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.26 29.49 library setup time
29.49 data required time
-----------------------------------------------------------------------------
29.49 data required time
-8.86 data arrival time
-----------------------------------------------------------------------------
20.63 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.10 0.03 6.03 ^ wbs_we_i (in)
1 0.00 wbs_we_i (net)
0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 net9 (net)
0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.03 _004_ (net)
0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.42 0.00 8.03 ^ _088_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.30 0.24 8.27 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _029_ (net)
0.30 0.00 8.27 v _089_/S (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
0.11 0.44 8.71 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
1 0.00 _030_ (net)
0.11 0.00 8.71 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.31 0.12 8.83 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.00 fsm_plant_opt.tmp2409 (net)
0.31 0.00 8.83 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.83 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.28 29.47 library setup time
29.47 data required time
-----------------------------------------------------------------------------
29.47 data required time
-8.83 data arrival time
-----------------------------------------------------------------------------
20.64 slack (MET)
Startpoint: wbs_we_i (input port clocked by wb_clk_i)
Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.15 0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (ideal)
6.00 6.00 ^ input external delay
0.10 0.03 6.03 ^ wbs_we_i (in)
1 0.00 wbs_we_i (net)
0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.02 net9 (net)
0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
2 0.01 _003_ (net)
0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.03 _004_ (net)
0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
4 0.02 _005_ (net)
0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.01 _027_ (net)
0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.00 _056_ (net)
0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
1 0.00 _057_ (net)
0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
2 0.01 fsm_plant_opt.tmp3554 (net)
0.18 0.00 8.69 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.69 data arrival time
0.15 30.00 30.00 clock wb_clk_i (rise edge)
0.00 30.00 clock network delay (ideal)
-0.25 29.75 clock uncertainty
0.00 29.75 clock reconvergence pessimism
29.75 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.24 29.51 library setup time
29.51 data required time
-----------------------------------------------------------------------------
29.51 data required time
-8.69 data arrival time
-----------------------------------------------------------------------------
20.82 slack (MET)