| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wbs_we_i (input port clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 6.00 6.00 ^ input external delay |
| 0.14 0.06 6.06 ^ wbs_we_i (in) |
| 2 0.01 wbs_we_i (net) |
| 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.07 net9 (net) |
| 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 _003_ (net) |
| 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 8 0.04 _004_ (net) |
| 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 4 0.02 _005_ (net) |
| 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.01 _027_ (net) |
| 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.00 _056_ (net) |
| 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.01 _057_ (net) |
| 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1) |
| 4 0.04 fsm_plant_opt.tmp3554 (net) |
| 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.03 fsm_plant_opt.tmp3553 (net) |
| 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 10.61 data arrival time |
| |
| 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock source latency |
| 0.14 0.06 30.06 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 3 0.01 clknet_1_0__leaf_wb_clk_i (net) |
| 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.25 30.26 clock uncertainty |
| 0.00 30.26 clock reconvergence pessimism |
| -0.26 30.00 library setup time |
| 30.00 data required time |
| ----------------------------------------------------------------------------- |
| 30.00 data required time |
| -10.61 data arrival time |
| ----------------------------------------------------------------------------- |
| 19.38 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
