final gds oasis
diff --git a/gds/aes.gds b/gds/aes.gds
deleted file mode 100644
index 2206d03..0000000
--- a/gds/aes.gds
+++ /dev/null
Binary files differ
diff --git a/gds/aes.gds.gz b/gds/aes.gds.gz
new file mode 100644
index 0000000..11865f6
--- /dev/null
+++ b/gds/aes.gds.gz
Binary files differ
diff --git a/gds/sbox.gds b/gds/sbox.gds
deleted file mode 100644
index 48951ae..0000000
--- a/gds/sbox.gds
+++ /dev/null
Binary files differ
diff --git a/gds/sbox.gds.gz b/gds/sbox.gds.gz
new file mode 100644
index 0000000..8f014ba
--- /dev/null
+++ b/gds/sbox.gds.gz
Binary files differ
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index 2066eb2..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..d379a26
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index 9b47490..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..1e72e9f
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..5bb8e41
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 04e1b337ee6a169f9012819a5f09f0ac7f8ef4a0
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..f3a7559
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/Askartos/fossiAES.git
+Branch: main
+Commit: 6676b4005319eea04978a86c231b16f26403ef94
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..c83c75c
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+DRC section
+BEOL section
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+Writing report database: /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 225.640s  Memory: 1768.00M
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..6b2fef0
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/opt/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+FEOL section
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+Writing report database: /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 22.140s  Memory: 1191.00M
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..7bc7a14
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+Writing report database: /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 11.460s  Memory: 695.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..5c3e6ab
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 903.00M
+"output" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.150s  Memory: 903.00M
+"output" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.110s  Memory: 903.00M
+"output" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 903.00M
+"output" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.080s  Memory: 903.00M
+"output" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 903.00M
+"output" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 903.00M
+"output" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.060s  Memory: 903.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 903.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 903.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 903.00M
+Writing report database: /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 33.040s  Memory: 709.00M
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..cc91a60
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/free_and_open_source_silicon_implementation_of_aes/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:32
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/EMP
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/EMP
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/EMP
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/EMP
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/EMP
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/EMP
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 5663336 kB
+VmHWM:	  427404 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..46525b0
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/user_project_wrapper_no_zero_areas.gds
+VmPeak:	  724492 kB
+VmHWM:	  436876 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..d04df7c
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,211 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "aes".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..19f87e1
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 27ecf1c16911f7dd4428ffab96f62c1fb876ea70
+Skywater PDK c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..7e1b273
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,112 @@
+2022-06-06 18:56:12 - [INFO] - {{Project Git Info}} Repository: https://github.com/Askartos/fossiAES.git | Branch: main | Commit: 6676b4005319eea04978a86c231b16f26403ef94
+2022-06-06 18:56:12 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: free_and_open_source_silicon_implementation_of_aes
+2022-06-06 18:56:12 - [INFO] - {{Project Type Info}} digital
+2022-06-06 18:56:12 - [INFO] - {{Project GDS Info}} user_project_wrapper: 04e1b337ee6a169f9012819a5f09f0ac7f8ef4a0
+2022-06-06 18:56:12 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-06-06 18:56:12 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+2022-06-06 18:56:12 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/logs'
+2022-06-06 18:56:12 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-06-06 18:56:12 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-06-06 18:56:13 - [INFO] - An approved LICENSE (Apache-2.0) was found in free_and_open_source_silicon_implementation_of_aes.
+2022-06-06 18:56:13 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-06-06 18:56:14 - [INFO] - An approved LICENSE (Apache-2.0) was found in free_and_open_source_silicon_implementation_of_aes.
+2022-06-06 18:56:14 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-06-06 18:56:14 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in free_and_open_source_silicon_implementation_of_aes/openlane/Makefile
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/project/target/config-classes/$a8b1e2da5b984b63cd5b$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/project/target/config-classes/$a8b1e2da5b984b63cd5b.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$05fe5d639449a6194cea$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$05fe5d639449a6194cea.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$0b5584a48be64a109044$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$0b5584a48be64a109044.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$17223d23b1f522e90c55$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$17223d23b1f522e90c55.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$1ce0de6b65365c0ee73c$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$1ce0de6b65365c0ee73c.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$3dbf9f928c7a60643b96$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$3dbf9f928c7a60643b96.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$6c98e542f2e9bc257711$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$6c98e542f2e9bc257711.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$7d19127391665036d4d3$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$7d19127391665036d4d3.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$8ec4ef238afcffada04b$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$8ec4ef238afcffada04b.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$93a17ca1f423cdc651e4$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$93a17ca1f423cdc651e4.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$95524433137b5c19968a$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$95524433137b5c19968a.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$994fac3f3d9e0262e903$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$994fac3f3d9e0262e903.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$bc53703718716965f24a$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$bc53703718716965f24a.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$c02c4dce5ad6f087b551$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$c02c4dce5ad6f087b551.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$d94027378b09dc70a687$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$d94027378b09dc70a687.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$e7ad8bb35c8c77ae989a$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$e7ad8bb35c8c77ae989a.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar): 'utf-8' codec can't decode byte 0x81 in position 10: invalid start byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain$delayedInit$body.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/mix.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/ports_mix.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/ports_sbox$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/ports_sbox.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/sbox$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/sbox.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/sboxMain$.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/sboxMain$delayedInit$body.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/sboxMain.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/whishbone_slave.class): 'utf-8' codec can't decode byte 0xca in position 0: invalid continuation byte
+2022-06-06 18:56:15 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 92 non-compliant file(s) with the SPDX Standard.
+2022-06-06 18:56:15 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['free_and_open_source_silicon_implementation_of_aes/Makefile', 'free_and_open_source_silicon_implementation_of_aes/docs/Makefile', 'free_and_open_source_silicon_implementation_of_aes/docs/environment.yml', 'free_and_open_source_silicon_implementation_of_aes/docs/source/conf.py', 'free_and_open_source_silicon_implementation_of_aes/docs/source/index.rst', 'free_and_open_source_silicon_implementation_of_aes/docs/source/quickstart.rst', 'free_and_open_source_silicon_implementation_of_aes/openlane/aes/config.tcl', 'free_and_open_source_silicon_implementation_of_aes/openlane/sbox/config.tcl', 'free_and_open_source_silicon_implementation_of_aes/openlane/user_proj_example/config.json', 'free_and_open_source_silicon_implementation_of_aes/openlane/user_proj_example/config.tcl', 'free_and_open_source_silicon_implementation_of_aes/openlane/user_project_wrapper/config.json', 'free_and_open_source_silicon_implementation_of_aes/openlane/user_project_wrapper/config.tcl', 'free_and_open_source_silicon_implementation_of_aes/sdc/aes.sdc', 'free_and_open_source_silicon_implementation_of_aes/sdc/sbox.sdc', 'free_and_open_source_silicon_implementation_of_aes/sdc/user_proj_example.sdc']
+2022-06-06 18:56:15 - [INFO] - For the full SPDX compliance report check: free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/logs/spdx_compliance_report.log
+2022-06-06 18:56:15 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-06-06 18:56:15 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-06-06 18:56:15 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-06-06 18:56:15 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-06-06 18:56:16 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-06-06 18:56:16 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-06-06 18:56:16 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-06-06 18:56:16 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-06-06 18:56:20 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
+2022-06-06 18:56:20 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
+2022-06-06 18:56:20 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
+2022-06-06 18:56:20 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
+2022-06-06 18:56:20 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-06-06 18:56:20 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-06-06 18:56:20 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-06-06 18:56:20 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances). 
+2022-06-06 18:56:20 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-06-06 18:56:20 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-06-06 18:56:20 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-06-06 18:56:20 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-06-06 18:56:20 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-06-06 18:56:21 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-06-06 18:56:21 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-06-06 18:56:33 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/user_project_wrapper.xor.gds
+2022-06-06 18:56:33 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-06-06 18:56:33 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-06-06 18:59:34 - [INFO] - 0 DRC violations
+2022-06-06 18:59:34 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 18:59:34 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-06-06 18:59:57 - [INFO] - No DRC Violations found
+2022-06-06 18:59:57 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 18:59:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-06-06 19:03:27 - [INFO] - No DRC Violations found
+2022-06-06 19:03:27 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 19:03:27 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-06-06 19:04:01 - [INFO] - No DRC Violations found
+2022-06-06 19:04:01 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 19:04:01 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-06-06 19:04:13 - [INFO] - No DRC Violations found
+2022-06-06 19:04:13 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 19:04:13 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-06-06 19:04:21 - [INFO] - No DRC Violations found
+2022-06-06 19:04:21 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 19:04:21 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-06-06 19:04:25 - [INFO] - No DRC Violations found
+2022-06-06 19:04:25 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-06 19:04:25 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/logs'
+2022-06-06 19:04:25 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..2bc8b52
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,92 @@
+/root/free_and_open_source_silicon_implementation_of_aes/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/docs/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/docs/environment.yml
+/root/free_and_open_source_silicon_implementation_of_aes/docs/source/conf.py
+/root/free_and_open_source_silicon_implementation_of_aes/docs/source/index.rst
+/root/free_and_open_source_silicon_implementation_of_aes/docs/source/quickstart.rst
+/root/free_and_open_source_silicon_implementation_of_aes/openlane/aes/config.tcl
+/root/free_and_open_source_silicon_implementation_of_aes/openlane/sbox/config.tcl
+/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_proj_example/config.json
+/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_proj_example/config.tcl
+/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_project_wrapper/config.json
+/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_project_wrapper/config.tcl
+/root/free_and_open_source_silicon_implementation_of_aes/sdc/aes.sdc
+/root/free_and_open_source_silicon_implementation_of_aes/sdc/sbox.sdc
+/root/free_and_open_source_silicon_implementation_of_aes/sdc/user_proj_example.sdc
+/root/free_and_open_source_silicon_implementation_of_aes/sdc/user_project_wrapper.sdc
+/root/free_and_open_source_silicon_implementation_of_aes/sdf/aes.sdf
+/root/free_and_open_source_silicon_implementation_of_aes/sdf/sbox.sdf
+/root/free_and_open_source_silicon_implementation_of_aes/sdf/user_proj_example.sdf
+/root/free_and_open_source_silicon_implementation_of_aes/sdf/user_project_wrapper.sdf
+/root/free_and_open_source_silicon_implementation_of_aes/spef/aes.spef
+/root/free_and_open_source_silicon_implementation_of_aes/spef/sbox.spef
+/root/free_and_open_source_silicon_implementation_of_aes/spef/user_proj_example.spef
+/root/free_and_open_source_silicon_implementation_of_aes/spef/user_project_wrapper.spef
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/aes_test.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/aes_test_tb.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/aes.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/aes.h
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/aes.hpp
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/conanfile.py
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/library.json
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/library.properties
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/test.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/test.cpp
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/test_package/conanfile.py
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/io_ports/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/io_ports/io_ports.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/io_ports/io_ports_tb.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test1/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test1/la_test1.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test1/la_test1_tb.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test2/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test2/la_test2.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test2/la_test2_tb.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/mprj_stimulus/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/mprj_stimulus/mprj_stimulus.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/wb_port/Makefile
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/wb_port/wb_port.c
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/wb_port/wb_port_tb.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/includes/includes.gl+sdf.caravel_user_project
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/includes/includes.gl.caravel_user_project
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/includes/includes.rtl.caravel_user_project
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/uprj_netlists.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/user_project_wrapper.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/build.sbt
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/run_chisel.sh
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/generated/aes.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/build.properties
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/plugins.sbt
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+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/scala-2.12/sbt-1.0/resolution-cache/default/arcabuco-build/scala_2.12/sbt_1.0/0.1.0-SNAPSHOT/resolved.xml.properties
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+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/aes.scala
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/bus.scala
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/mix.scala
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/sbox.scala
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/resolution-cache/arcabuco/arcabuco_2.12/1.0/resolved.xml.properties
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+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/resolution-cache/reports/ivy-report.xsl
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/example/uprj_netlists.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/example/user_proj_example.v
+/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/example/user_project_wrapper.v
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..30c7b02
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,367 @@
+Reading file /root/free_and_open_source_silicon_implementation_of_aes/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "aes".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+Writing layout file: /mnt/uffs/user/u4694_hanssel/design/free_and_open_source_silicon_implementation_of_aes/jobs/mpw_precheck/b1b9909d-6f64-41e3-8d0a-de3876c390d5/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.130s  Memory: 523.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..987027f
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..c0e4db4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/free_and_open_source_silicon_implementation_of_aes/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..38adfae
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,165 @@
+module user_project_wrapper (user_clock2,
+    vccd1,
+    vccd2,
+    vdda1,
+    vdda2,
+    vssa1,
+    vssa2,
+    vssd1,
+    vssd2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+
+ aes fossiAES (.clock(wb_clk_i),
+    .io_wbs_ack_o(wbs_ack_o),
+    .io_wbs_cyc_i(wbs_cyc_i),
+    .io_wbs_stb_i(wbs_stb_i),
+    .io_wbs_we_i(wbs_we_i),
+    .reset(wb_rst_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .io_wbs_adr_i({wbs_adr_i[31],
+    wbs_adr_i[30],
+    wbs_adr_i[29],
+    wbs_adr_i[28],
+    wbs_adr_i[27],
+    wbs_adr_i[26],
+    wbs_adr_i[25],
+    wbs_adr_i[24],
+    wbs_adr_i[23],
+    wbs_adr_i[22],
+    wbs_adr_i[21],
+    wbs_adr_i[20],
+    wbs_adr_i[19],
+    wbs_adr_i[18],
+    wbs_adr_i[17],
+    wbs_adr_i[16],
+    wbs_adr_i[15],
+    wbs_adr_i[14],
+    wbs_adr_i[13],
+    wbs_adr_i[12],
+    wbs_adr_i[11],
+    wbs_adr_i[10],
+    wbs_adr_i[9],
+    wbs_adr_i[8],
+    wbs_adr_i[7],
+    wbs_adr_i[6],
+    wbs_adr_i[5],
+    wbs_adr_i[4],
+    wbs_adr_i[3],
+    wbs_adr_i[2],
+    wbs_adr_i[1],
+    wbs_adr_i[0]}),
+    .io_wbs_dat_i({wbs_dat_i[31],
+    wbs_dat_i[30],
+    wbs_dat_i[29],
+    wbs_dat_i[28],
+    wbs_dat_i[27],
+    wbs_dat_i[26],
+    wbs_dat_i[25],
+    wbs_dat_i[24],
+    wbs_dat_i[23],
+    wbs_dat_i[22],
+    wbs_dat_i[21],
+    wbs_dat_i[20],
+    wbs_dat_i[19],
+    wbs_dat_i[18],
+    wbs_dat_i[17],
+    wbs_dat_i[16],
+    wbs_dat_i[15],
+    wbs_dat_i[14],
+    wbs_dat_i[13],
+    wbs_dat_i[12],
+    wbs_dat_i[11],
+    wbs_dat_i[10],
+    wbs_dat_i[9],
+    wbs_dat_i[8],
+    wbs_dat_i[7],
+    wbs_dat_i[6],
+    wbs_dat_i[5],
+    wbs_dat_i[4],
+    wbs_dat_i[3],
+    wbs_dat_i[2],
+    wbs_dat_i[1],
+    wbs_dat_i[0]}),
+    .io_wbs_dat_o({wbs_dat_o[31],
+    wbs_dat_o[30],
+    wbs_dat_o[29],
+    wbs_dat_o[28],
+    wbs_dat_o[27],
+    wbs_dat_o[26],
+    wbs_dat_o[25],
+    wbs_dat_o[24],
+    wbs_dat_o[23],
+    wbs_dat_o[22],
+    wbs_dat_o[21],
+    wbs_dat_o[20],
+    wbs_dat_o[19],
+    wbs_dat_o[18],
+    wbs_dat_o[17],
+    wbs_dat_o[16],
+    wbs_dat_o[15],
+    wbs_dat_o[14],
+    wbs_dat_o[13],
+    wbs_dat_o[12],
+    wbs_dat_o[11],
+    wbs_dat_o[10],
+    wbs_dat_o[9],
+    wbs_dat_o[8],
+    wbs_dat_o[7],
+    wbs_dat_o[6],
+    wbs_dat_o[5],
+    wbs_dat_o[4],
+    wbs_dat_o[3],
+    wbs_dat_o[2],
+    wbs_dat_o[1],
+    wbs_dat_o[0]}),
+    .io_wbs_sel_i({wbs_sel_i[3],
+    wbs_sel_i[2],
+    wbs_sel_i[1],
+    wbs_sel_i[0]}));
+endmodule
diff --git a/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..db6afd5
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,21576 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1654541974
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< metal1 >>
+rect 234154 500352 234160 500404
+rect 234212 500392 234218 500404
+rect 264974 500392 264980 500404
+rect 234212 500364 264980 500392
+rect 234212 500352 234218 500364
+rect 264974 500352 264980 500364
+rect 265032 500352 265038 500404
+rect 22738 500284 22744 500336
+rect 22796 500324 22802 500336
+rect 270770 500324 270776 500336
+rect 22796 500296 270776 500324
+rect 22796 500284 22802 500296
+rect 270770 500284 270776 500296
+rect 270828 500284 270834 500336
+rect 21358 500216 21364 500268
+rect 21416 500256 21422 500268
+rect 388622 500256 388628 500268
+rect 21416 500228 388628 500256
+rect 21416 500216 21422 500228
+rect 388622 500216 388628 500228
+rect 388680 500216 388686 500268
+rect 234062 500148 234068 500200
+rect 234120 500188 234126 500200
+rect 276566 500188 276572 500200
+rect 234120 500160 276572 500188
+rect 234120 500148 234126 500160
+rect 276566 500148 276572 500160
+rect 276624 500148 276630 500200
+rect 259638 500080 259644 500132
+rect 259696 500120 259702 500132
+rect 311986 500120 311992 500132
+rect 259696 500092 311992 500120
+rect 259696 500080 259702 500092
+rect 311986 500080 311992 500092
+rect 312044 500080 312050 500132
+rect 242802 500012 242808 500064
+rect 242860 500052 242866 500064
+rect 300394 500052 300400 500064
+rect 242860 500024 300400 500052
+rect 242860 500012 242866 500024
+rect 300394 500012 300400 500024
+rect 300452 500012 300458 500064
+rect 233878 499944 233884 499996
+rect 233936 499984 233942 499996
+rect 324314 499984 324320 499996
+rect 233936 499956 324320 499984
+rect 233936 499944 233942 499956
+rect 324314 499944 324320 499956
+rect 324372 499944 324378 499996
+rect 233970 499876 233976 499928
+rect 234028 499916 234034 499928
+rect 371234 499916 371240 499928
+rect 234028 499888 371240 499916
+rect 234028 499876 234034 499888
+rect 371234 499876 371240 499888
+rect 371292 499876 371298 499928
+rect 157978 499808 157984 499860
+rect 158036 499848 158042 499860
+rect 306374 499848 306380 499860
+rect 158036 499820 306380 499848
+rect 158036 499808 158042 499820
+rect 306374 499808 306380 499820
+rect 306432 499808 306438 499860
+rect 177298 499740 177304 499792
+rect 177356 499780 177362 499792
+rect 341610 499780 341616 499792
+rect 177356 499752 341616 499780
+rect 177356 499740 177362 499752
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