mpw_precheck/logs/spdx_compliance_report.log

/root/free_and_open_source_silicon_implementation_of_aes/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/docs/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/docs/environment.yml
/root/free_and_open_source_silicon_implementation_of_aes/docs/source/conf.py
/root/free_and_open_source_silicon_implementation_of_aes/docs/source/index.rst
/root/free_and_open_source_silicon_implementation_of_aes/docs/source/quickstart.rst
/root/free_and_open_source_silicon_implementation_of_aes/openlane/aes/config.tcl
/root/free_and_open_source_silicon_implementation_of_aes/openlane/sbox/config.tcl
/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_proj_example/config.json
/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_proj_example/config.tcl
/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_project_wrapper/config.json
/root/free_and_open_source_silicon_implementation_of_aes/openlane/user_project_wrapper/config.tcl
/root/free_and_open_source_silicon_implementation_of_aes/sdc/aes.sdc
/root/free_and_open_source_silicon_implementation_of_aes/sdc/sbox.sdc
/root/free_and_open_source_silicon_implementation_of_aes/sdc/user_proj_example.sdc
/root/free_and_open_source_silicon_implementation_of_aes/sdc/user_project_wrapper.sdc
/root/free_and_open_source_silicon_implementation_of_aes/sdf/aes.sdf
/root/free_and_open_source_silicon_implementation_of_aes/sdf/sbox.sdf
/root/free_and_open_source_silicon_implementation_of_aes/sdf/user_proj_example.sdf
/root/free_and_open_source_silicon_implementation_of_aes/sdf/user_project_wrapper.sdf
/root/free_and_open_source_silicon_implementation_of_aes/spef/aes.spef
/root/free_and_open_source_silicon_implementation_of_aes/spef/sbox.spef
/root/free_and_open_source_silicon_implementation_of_aes/spef/user_proj_example.spef
/root/free_and_open_source_silicon_implementation_of_aes/spef/user_project_wrapper.spef
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/aes_test.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/aes_test_tb.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/aes.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/aes.h
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/aes.hpp
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/conanfile.py
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/library.json
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/library.properties
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/test.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/test.cpp
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/aes_test/tiny-AES-c_lite/test_package/conanfile.py
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/io_ports/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/io_ports/io_ports.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/io_ports/io_ports_tb.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test1/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test1/la_test1.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test1/la_test1_tb.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test2/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test2/la_test2.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/la_test2/la_test2_tb.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/mprj_stimulus/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/mprj_stimulus/mprj_stimulus.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/wb_port/Makefile
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/wb_port/wb_port.c
/root/free_and_open_source_silicon_implementation_of_aes/verilog/dv/wb_port/wb_port_tb.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/includes/includes.gl+sdf.caravel_user_project
/root/free_and_open_source_silicon_implementation_of_aes/verilog/includes/includes.gl.caravel_user_project
/root/free_and_open_source_silicon_implementation_of_aes/verilog/includes/includes.rtl.caravel_user_project
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/uprj_netlists.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/user_project_wrapper.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/build.sbt
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/run_chisel.sh
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/generated/aes.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/build.properties
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/plugins.sbt
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/project/target/config-classes/$a8b1e2da5b984b63cd5b.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$05fe5d639449a6194cea.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$0b5584a48be64a109044.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$1ce0de6b65365c0ee73c.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$3dbf9f928c7a60643b96.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$6c98e542f2e9bc257711.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$7d19127391665036d4d3.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$8ec4ef238afcffada04b.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$93a17ca1f423cdc651e4.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$95524433137b5c19968a.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$994fac3f3d9e0262e903.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$bc53703718716965f24a.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$c02c4dce5ad6f087b551.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$d94027378b09dc70a687.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/config-classes/$e7ad8bb35c8c77ae989a.cache
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/scala-2.12/sbt-1.0/resolution-cache/default/aes-build/scala_2.12/sbt_1.0/0.1.0-SNAPSHOT/resolved.xml.properties
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/scala-2.12/sbt-1.0/resolution-cache/default/arcabuco-build/scala_2.12/sbt_1.0/0.1.0-SNAPSHOT/resolved.xml.properties
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/scala-2.12/sbt-1.0/resolution-cache/reports/ivy-report.css
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/project/target/scala-2.12/sbt-1.0/resolution-cache/reports/ivy-report.xsl
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/aes.scala
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/bus.scala
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/mix.scala
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/src/main/scala/sbox.scala
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/resolution-cache/arcabuco/arcabuco_2.12/1.0/resolved.xml.properties
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/resolution-cache/reports/ivy-report.css
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/aes/target/scala-2.12/resolution-cache/reports/ivy-report.xsl
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/example/uprj_netlists.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/example/user_proj_example.v
/root/free_and_open_source_silicon_implementation_of_aes/verilog/rtl/example/user_project_wrapper.v